description: Full Taiga core test
rc: 1 (means success: 0)
tags: taiga
incdirs: /tmpfs/src/github/sv-tests/tests/generated/taiga
top_module:
type: parsing
mode: parsing
files: third_party/cores/taiga/core/l1_arbiter.sv third_party/cores/taiga/core/div_unit_core_wrapper.sv third_party/cores/taiga/core/icache.sv third_party/cores/taiga/core/amo_alu.sv third_party/cores/taiga/core/write_back.sv third_party/cores/taiga/core/cycler.sv third_party/cores/taiga/core/branch_predictor_ram.sv third_party/cores/taiga/core/register_file.sv third_party/cores/taiga/core/barrel_shifter.sv third_party/cores/taiga/core/csr_types.sv third_party/cores/taiga/core/tag_bank.sv third_party/cores/taiga/core/taiga_config.sv third_party/cores/taiga/core/fetch.sv third_party/cores/taiga/core/taiga_types.sv third_party/cores/taiga/core/csr_regs.sv third_party/cores/taiga/core/taiga_fifo.sv third_party/cores/taiga/core/byte_en_BRAM.sv third_party/cores/taiga/core/gc_unit.sv third_party/cores/taiga/core/tlb_lut_ram.sv third_party/cores/taiga/core/wishbone_master.sv third_party/cores/taiga/core/dtag_banks.sv third_party/cores/taiga/core/branch_predictor.sv third_party/cores/taiga/core/placer_randomizer.sv third_party/cores/taiga/core/lut_ram.sv third_party/cores/taiga/core/ibram.sv third_party/cores/taiga/core/alu_unit.sv third_party/cores/taiga/core/mmu.sv third_party/cores/taiga/core/axi_to_arb.sv third_party/cores/taiga/core/taiga.sv third_party/cores/taiga/core/msb.sv third_party/cores/taiga/core/external_interfaces.sv third_party/cores/taiga/core/branch_comparator.sv third_party/cores/taiga/core/shift_counter.sv third_party/cores/taiga/core/one_hot_to_integer.sv third_party/cores/taiga/core/interfaces.sv third_party/cores/taiga/core/one_hot_occupancy.sv third_party/cores/taiga/core/ddata_bank.sv third_party/cores/taiga/core/id_tracking.sv third_party/cores/taiga/core/binary_occupancy.sv third_party/cores/taiga/core/branch_unit.sv third_party/cores/taiga/core/dbram.sv third_party/cores/taiga/core/dcache.sv third_party/cores/taiga/core/mul_unit.sv third_party/cores/taiga/core/avalon_master.sv third_party/cores/taiga/core/div_unit.sv third_party/cores/taiga/core/load_store_unit.sv third_party/cores/taiga/core/pre_decode.sv third_party/cores/taiga/core/clz.sv third_party/cores/taiga/core/decode.sv third_party/cores/taiga/core/ras.sv third_party/cores/taiga/core/itag_banks.sv third_party/cores/taiga/core/msb_naive.sv third_party/cores/taiga/core/mstatus_priv_reg.sv third_party/cores/taiga/core/id_inuse.sv third_party/cores/taiga/core/axi_master.sv third_party/cores/taiga/core/div_algorithms/div_radix2_ET.sv third_party/cores/taiga/core/div_algorithms/div_radix2.sv third_party/cores/taiga/core/div_algorithms/div_radix4_ET.sv third_party/cores/taiga/core/div_algorithms/div_radix4_ET_full.sv third_party/cores/taiga/core/div_algorithms/div_radix16.sv third_party/cores/taiga/core/div_algorithms/div_radix8_ET.sv third_party/cores/taiga/core/div_algorithms/div_quick_naive.sv third_party/cores/taiga/core/div_algorithms/div_algorithm.sv third_party/cores/taiga/core/div_algorithms/div_radix4.sv third_party/cores/taiga/core/div_algorithms/div_quick_clz.sv third_party/cores/taiga/core/div_algorithms/div_quick_clz_mk2.sv third_party/cores/taiga/core/div_algorithms/div_quick_radix4.sv third_party/cores/taiga/core/div_algorithms/div_radix2_ET_full.sv third_party/cores/taiga/core/div_algorithms/div_radix8.sv third_party/cores/taiga/l2_arbiter/l2_reservation_logic.sv third_party/cores/taiga/l2_arbiter/l2_arbiter.sv third_party/cores/taiga/l2_arbiter/l2_fifo.sv third_party/cores/taiga/l2_arbiter/l2_config_and_types.sv third_party/cores/taiga/l2_arbiter/l2_external_interfaces.sv third_party/cores/taiga/l2_arbiter/l2_interfaces.sv third_party/cores/taiga/l2_arbiter/l2_round_robin.sv third_party/cores/taiga/local_memory/local_memory_interface.sv third_party/cores/taiga/local_memory/local_mem.sv third_party/cores/taiga/examples/zedboard/taiga_wrapper.sv
defines:
time_elapsed: 42.280s
ram usage: 432888 KB
sh /tmpfs/tmp/tmp1qgo7jwo/scr.sh
+ surelog-uhdm -nopython -nobuiltin -parse -sverilog -I/tmpfs/src/github/sv-tests/tests/generated/taiga third_party/cores/taiga/core/l1_arbiter.sv third_party/cores/taiga/core/div_unit_core_wrapper.sv third_party/cores/taiga/core/icache.sv third_party/cores/taiga/core/amo_alu.sv third_party/cores/taiga/core/write_back.sv third_party/cores/taiga/core/cycler.sv third_party/cores/taiga/core/branch_predictor_ram.sv third_party/cores/taiga/core/register_file.sv third_party/cores/taiga/core/barrel_shifter.sv third_party/cores/taiga/core/csr_types.sv third_party/cores/taiga/core/tag_bank.sv third_party/cores/taiga/core/taiga_config.sv third_party/cores/taiga/core/fetch.sv third_party/cores/taiga/core/taiga_types.sv third_party/cores/taiga/core/csr_regs.sv third_party/cores/taiga/core/taiga_fifo.sv third_party/cores/taiga/core/byte_en_BRAM.sv third_party/cores/taiga/core/gc_unit.sv third_party/cores/taiga/core/tlb_lut_ram.sv third_party/cores/taiga/core/wishbone_master.sv third_party/cores/taiga/core/dtag_banks.sv third_party/cores/taiga/core/branch_predictor.sv third_party/cores/taiga/core/placer_randomizer.sv third_party/cores/taiga/core/lut_ram.sv third_party/cores/taiga/core/ibram.sv third_party/cores/taiga/core/alu_unit.sv third_party/cores/taiga/core/mmu.sv third_party/cores/taiga/core/axi_to_arb.sv third_party/cores/taiga/core/taiga.sv third_party/cores/taiga/core/msb.sv third_party/cores/taiga/core/external_interfaces.sv third_party/cores/taiga/core/branch_comparator.sv third_party/cores/taiga/core/shift_counter.sv third_party/cores/taiga/core/one_hot_to_integer.sv third_party/cores/taiga/core/interfaces.sv third_party/cores/taiga/core/one_hot_occupancy.sv third_party/cores/taiga/core/ddata_bank.sv third_party/cores/taiga/core/id_tracking.sv third_party/cores/taiga/core/binary_occupancy.sv third_party/cores/taiga/core/branch_unit.sv third_party/cores/taiga/core/dbram.sv third_party/cores/taiga/core/dcache.sv third_party/cores/taiga/core/mul_unit.sv third_party/cores/taiga/core/avalon_master.sv third_party/cores/taiga/core/div_unit.sv third_party/cores/taiga/core/load_store_unit.sv third_party/cores/taiga/core/pre_decode.sv third_party/cores/taiga/core/clz.sv third_party/cores/taiga/core/decode.sv third_party/cores/taiga/core/ras.sv third_party/cores/taiga/core/itag_banks.sv third_party/cores/taiga/core/msb_naive.sv third_party/cores/taiga/core/mstatus_priv_reg.sv third_party/cores/taiga/core/id_inuse.sv third_party/cores/taiga/core/axi_master.sv third_party/cores/taiga/core/div_algorithms/div_radix2_ET.sv third_party/cores/taiga/core/div_algorithms/div_radix2.sv third_party/cores/taiga/core/div_algorithms/div_radix4_ET.sv third_party/cores/taiga/core/div_algorithms/div_radix4_ET_full.sv third_party/cores/taiga/core/div_algorithms/div_radix16.sv third_party/cores/taiga/core/div_algorithms/div_radix8_ET.sv third_party/cores/taiga/core/div_algorithms/div_quick_naive.sv third_party/cores/taiga/core/div_algorithms/div_algorithm.sv third_party/cores/taiga/core/div_algorithms/div_radix4.sv third_party/cores/taiga/core/div_algorithms/div_quick_clz.sv third_party/cores/taiga/core/div_algorithms/div_quick_clz_mk2.sv third_party/cores/taiga/core/div_algorithms/div_quick_radix4.sv third_party/cores/taiga/core/div_algorithms/div_radix2_ET_full.sv third_party/cores/taiga/core/div_algorithms/div_radix8.sv third_party/cores/taiga/l2_arbiter/l2_reservation_logic.sv third_party/cores/taiga/l2_arbiter/l2_arbiter.sv third_party/cores/taiga/l2_arbiter/l2_fifo.sv third_party/cores/taiga/l2_arbiter/l2_config_and_types.sv third_party/cores/taiga/l2_arbiter/l2_external_interfaces.sv third_party/cores/taiga/l2_arbiter/l2_interfaces.sv third_party/cores/taiga/l2_arbiter/l2_round_robin.sv third_party/cores/taiga/local_memory/local_memory_interface.sv third_party/cores/taiga/local_memory/local_mem.sv third_party/cores/taiga/examples/zedboard/taiga_wrapper.sv
[INF:CM0023] Creating log file ./slpp_all/surelog.log.
[WRN:PA0205] third_party/cores/taiga/core/l1_arbiter.sv:27: No timescale set for "l1_arbiter".
[WRN:PA0205] third_party/cores/taiga/core/div_unit_core_wrapper.sv:4: No timescale set for "div_unit_core_wrapper".
[WRN:PA0205] third_party/cores/taiga/core/icache.sv:26: No timescale set for "icache".
[WRN:PA0205] third_party/cores/taiga/core/amo_alu.sv:26: No timescale set for "amo_alu".
[WRN:PA0205] third_party/cores/taiga/core/write_back.sv:26: No timescale set for "write_back".
[WRN:PA0205] third_party/cores/taiga/core/cycler.sv:24: No timescale set for "cycler".
[WRN:PA0205] third_party/cores/taiga/core/branch_predictor_ram.sv:26: No timescale set for "branch_predictor_ram".
[WRN:PA0205] third_party/cores/taiga/core/register_file.sv:26: No timescale set for "register_file".
[WRN:PA0205] third_party/cores/taiga/core/barrel_shifter.sv:26: No timescale set for "barrel_shifter".
[WRN:PA0205] third_party/cores/taiga/core/csr_types.sv:23: No timescale set for "csr_types".
[WRN:PA0205] third_party/cores/taiga/core/tag_bank.sv:26: No timescale set for "tag_bank".
[WRN:PA0205] third_party/cores/taiga/core/taiga_config.sv:23: No timescale set for "taiga_config".
[WRN:PA0205] third_party/cores/taiga/core/fetch.sv:26: No timescale set for "fetch".
[WRN:PA0205] third_party/cores/taiga/core/taiga_types.sv:23: No timescale set for "taiga_types".
[WRN:PA0205] third_party/cores/taiga/core/csr_regs.sv:27: No timescale set for "csr_regs".
[WRN:PA0205] third_party/cores/taiga/core/taiga_fifo.sv:31: No timescale set for "taiga_fifo".
[WRN:PA0205] third_party/cores/taiga/core/byte_en_BRAM.sv:26: No timescale set for "byte_en_BRAM".
[WRN:PA0205] third_party/cores/taiga/core/gc_unit.sv:27: No timescale set for "gc_unit".
[WRN:PA0205] third_party/cores/taiga/core/tlb_lut_ram.sv:26: No timescale set for "tlb_lut_ram".
[WRN:PA0205] third_party/cores/taiga/core/wishbone_master.sv:27: No timescale set for "wishbone_master".
[WRN:PA0205] third_party/cores/taiga/core/dtag_banks.sv:26: No timescale set for "dtag_banks".
[WRN:PA0205] third_party/cores/taiga/core/branch_predictor.sv:26: No timescale set for "branch_predictor".
[WRN:PA0205] third_party/cores/taiga/core/placer_randomizer.sv:1: No timescale set for "placer_randomizer".
[WRN:PA0205] third_party/cores/taiga/core/lut_ram.sv:23: No timescale set for "lut_ram".
[WRN:PA0205] third_party/cores/taiga/core/ibram.sv:26: No timescale set for "ibram".
[WRN:PA0205] third_party/cores/taiga/core/alu_unit.sv:26: No timescale set for "alu_unit".
[WRN:PA0205] third_party/cores/taiga/core/mmu.sv:27: No timescale set for "mmu".
[WRN:PA0205] third_party/cores/taiga/core/axi_to_arb.sv:28: No timescale set for "axi_to_arb".
[WRN:PA0205] third_party/cores/taiga/core/taiga.sv:26: No timescale set for "taiga".
[WRN:PA0205] third_party/cores/taiga/core/msb.sv:23: No timescale set for "msb".
[WRN:PA0205] third_party/cores/taiga/core/external_interfaces.sv:27: No timescale set for "axi_interface".
[WRN:PA0205] third_party/cores/taiga/core/external_interfaces.sv:87: No timescale set for "avalon_interface".
[WRN:PA0205] third_party/cores/taiga/core/external_interfaces.sv:105: No timescale set for "wishbone_interface".
[WRN:PA0205] third_party/cores/taiga/core/external_interfaces.sv:122: No timescale set for "l1_arbiter_request_interface".
[WRN:PA0205] third_party/cores/taiga/core/external_interfaces.sv:148: No timescale set for "l1_arbiter_return_interface".
[WRN:PA0205] third_party/cores/taiga/core/branch_comparator.sv:26: No timescale set for "branch_comparator".
[WRN:PA0205] third_party/cores/taiga/core/shift_counter.sv:26: No timescale set for "shift_counter".
[WRN:PA0205] third_party/cores/taiga/core/one_hot_to_integer.sv:25: No timescale set for "one_hot_to_integer".
[WRN:PA0205] third_party/cores/taiga/core/interfaces.sv:27: No timescale set for "branch_predictor_interface".
[WRN:PA0205] third_party/cores/taiga/core/interfaces.sv:52: No timescale set for "unit_issue_interface".
[WRN:PA0205] third_party/cores/taiga/core/interfaces.sv:64: No timescale set for "ras_interface".
[WRN:PA0205] third_party/cores/taiga/core/interfaces.sv:76: No timescale set for "csr_exception_interface".
[WRN:PA0205] third_party/cores/taiga/core/interfaces.sv:90: No timescale set for "exception_interface".
[WRN:PA0205] third_party/cores/taiga/core/interfaces.sv:103: No timescale set for "register_file_decode_interface".
[WRN:PA0205] third_party/cores/taiga/core/interfaces.sv:123: No timescale set for "register_file_writeback_interface".
[WRN:PA0205] third_party/cores/taiga/core/interfaces.sv:145: No timescale set for "tracking_interface".
[WRN:PA0205] third_party/cores/taiga/core/interfaces.sv:157: No timescale set for "fifo_interface".
[WRN:PA0205] third_party/cores/taiga/core/interfaces.sv:170: No timescale set for "mmu_interface".
[WRN:PA0205] third_party/cores/taiga/core/interfaces.sv:193: No timescale set for "tlb_interface".
[WRN:PA0205] third_party/cores/taiga/core/interfaces.sv:212: No timescale set for "ls_sub_unit_interface".
[WRN:PA0205] third_party/cores/taiga/core/interfaces.sv:227: No timescale set for "fetch_sub_unit_interface".
[WRN:PA0205] third_party/cores/taiga/core/interfaces.sv:243: No timescale set for "unsigned_division_interface".
[WRN:PA0205] third_party/cores/taiga/core/interfaces.sv:257: No timescale set for "post_issue_forwarding_interface".
[WRN:PA0205] third_party/cores/taiga/core/one_hot_occupancy.sv:26: No timescale set for "one_hot_occupancy".
[WRN:PA0205] third_party/cores/taiga/core/ddata_bank.sv:26: No timescale set for "ddata_bank".
[WRN:PA0205] third_party/cores/taiga/core/id_tracking.sv:26: No timescale set for "id_tracking".
[WRN:PA0205] third_party/cores/taiga/core/binary_occupancy.sv:26: No timescale set for "binary_occupancy".
[WRN:PA0205] third_party/cores/taiga/core/branch_unit.sv:26: No timescale set for "branch_unit".
[WRN:PA0205] third_party/cores/taiga/core/dbram.sv:26: No timescale set for "dbram".
[WRN:PA0205] third_party/cores/taiga/core/dcache.sv:26: No timescale set for "dcache".
[WRN:PA0205] third_party/cores/taiga/core/mul_unit.sv:26: No timescale set for "mul_unit".
[WRN:PA0205] third_party/cores/taiga/core/avalon_master.sv:27: No timescale set for "avalon_master".
[WRN:PA0205] third_party/cores/taiga/core/div_unit.sv:26: No timescale set for "div_unit".
[WRN:PA0205] third_party/cores/taiga/core/load_store_unit.sv:26: No timescale set for "load_store_unit".
[WRN:PA0205] third_party/cores/taiga/core/pre_decode.sv:26: No timescale set for "pre_decode".
[WRN:PA0205] third_party/cores/taiga/core/clz.sv:23: No timescale set for "clz".
[WRN:PA0205] third_party/cores/taiga/core/decode.sv:26: No timescale set for "decode".
[WRN:PA0205] third_party/cores/taiga/core/ras.sv:26: No timescale set for "ras".
[WRN:PA0205] third_party/cores/taiga/core/itag_banks.sv:26: No timescale set for "itag_banks".
[WRN:PA0205] third_party/cores/taiga/core/msb_naive.sv:25: No timescale set for "msb_naive".
[WRN:PA0205] third_party/cores/taiga/core/mstatus_priv_reg.sv:27: No timescale set for "mstatus_priv_reg".
[WRN:PA0205] third_party/cores/taiga/core/id_inuse.sv:26: No timescale set for "id_inuse".
[WRN:PA0205] third_party/cores/taiga/core/axi_master.sv:27: No timescale set for "axi_master".
[WRN:PA0205] third_party/cores/taiga/core/div_algorithms/div_radix2_ET.sv:25: No timescale set for "div_radix2_ET".
[WRN:PA0205] third_party/cores/taiga/core/div_algorithms/div_radix2.sv:25: No timescale set for "div_radix2".
[WRN:PA0205] third_party/cores/taiga/core/div_algorithms/div_radix4_ET.sv:25: No timescale set for "div_radix4_ET".
[WRN:PA0205] third_party/cores/taiga/core/div_algorithms/div_radix4_ET_full.sv:25: No timescale set for "div_radix4_ET_full".
[WRN:PA0205] third_party/cores/taiga/core/div_algorithms/div_radix16.sv:25: No timescale set for "div_radix16".
[WRN:PA0205] third_party/cores/taiga/core/div_algorithms/div_radix8_ET.sv:25: No timescale set for "div_radix8_ET".
[WRN:PA0205] third_party/cores/taiga/core/div_algorithms/div_quick_naive.sv:25: No timescale set for "div_quick_naive".
[WRN:PA0205] third_party/cores/taiga/core/div_algorithms/div_algorithm.sv:27: No timescale set for "div_algorithm".
[WRN:PA0205] third_party/cores/taiga/core/div_algorithms/div_radix4.sv:25: No timescale set for "div_radix4".
[WRN:PA0205] third_party/cores/taiga/core/div_algorithms/div_quick_clz.sv:25: No timescale set for "div_quick_clz".
[WRN:PA0205] third_party/cores/taiga/core/div_algorithms/div_quick_clz_mk2.sv:25: No timescale set for "div_quick_clz_mk2".
[WRN:PA0205] third_party/cores/taiga/core/div_algorithms/div_quick_radix4.sv:25: No timescale set for "div_quick_radix_4".
[WRN:PA0205] third_party/cores/taiga/core/div_algorithms/div_radix2_ET_full.sv:25: No timescale set for "div_radix2_ET_full".
[WRN:PA0205] third_party/cores/taiga/core/div_algorithms/div_radix8.sv:25: No timescale set for "div_radix8".
[WRN:PA0205] third_party/cores/taiga/l2_arbiter/l2_reservation_logic.sv:25: No timescale set for "l2_reservation_logic".
[WRN:PA0205] third_party/cores/taiga/l2_arbiter/l2_arbiter.sv:26: No timescale set for "l2_arbiter".
[WRN:PA0205] third_party/cores/taiga/l2_arbiter/l2_fifo.sv:23: No timescale set for "l2_fifo".
[WRN:PA0205] third_party/cores/taiga/l2_arbiter/l2_config_and_types.sv:24: No timescale set for "l2_config_and_types".
[WRN:PA0205] third_party/cores/taiga/l2_arbiter/l2_external_interfaces.sv:25: No timescale set for "l2_requester_interface".
[WRN:PA0205] third_party/cores/taiga/l2_arbiter/l2_external_interfaces.sv:69: No timescale set for "l2_memory_interface".
[WRN:PA0205] third_party/cores/taiga/l2_arbiter/l2_interfaces.sv:25: No timescale set for "l2_fifo_interface".
[WRN:PA0205] third_party/cores/taiga/l2_arbiter/l2_interfaces.sv:38: No timescale set for "l2_arbitration_interface".
[WRN:PA0205] third_party/cores/taiga/l2_arbiter/l2_round_robin.sv:25: No timescale set for "l2_round_robin".
[WRN:PA0205] third_party/cores/taiga/local_memory/local_memory_interface.sv:24: No timescale set for "local_memory_interface".
[WRN:PA0205] third_party/cores/taiga/local_memory/local_mem.sv:24: No timescale set for "local_mem".
[WRN:PA0205] third_party/cores/taiga/examples/zedboard/taiga_wrapper.sv:27: No timescale set for "taiga_wrapper".
[INF:CP0300] Compilation...
[INF:CP0301] third_party/cores/taiga/core/csr_types.sv:23: Compile package "csr_types".
[INF:CP0301] third_party/cores/taiga/core/taiga_config.sv:23: Compile package "taiga_config".
[INF:CP0301] third_party/cores/taiga/core/taiga_types.sv:23: Compile package "taiga_types".
[INF:CP0301] third_party/cores/taiga/l2_arbiter/l2_config_and_types.sv:24: Compile package "l2_config_and_types".
[INF:CP0303] third_party/cores/taiga/core/alu_unit.sv:26: Compile module "work@alu_unit".
[INF:CP0303] third_party/cores/taiga/core/amo_alu.sv:26: Compile module "work@amo_alu".
[INF:CP0304] third_party/cores/taiga/core/external_interfaces.sv:87: Compile interface "work@avalon_interface".
[INF:CP0303] third_party/cores/taiga/core/avalon_master.sv:27: Compile module "work@avalon_master".
[INF:CP0304] third_party/cores/taiga/core/external_interfaces.sv:27: Compile interface "work@axi_interface".
[INF:CP0303] third_party/cores/taiga/core/axi_master.sv:27: Compile module "work@axi_master".
[INF:CP0303] third_party/cores/taiga/core/axi_to_arb.sv:28: Compile module "work@axi_to_arb".
[INF:CP0303] third_party/cores/taiga/core/barrel_shifter.sv:26: Compile module "work@barrel_shifter".
[INF:CP0303] third_party/cores/taiga/core/binary_occupancy.sv:26: Compile module "work@binary_occupancy".
[INF:CP0303] third_party/cores/taiga/core/branch_comparator.sv:26: Compile module "work@branch_comparator".
[INF:CP0303] third_party/cores/taiga/core/branch_predictor.sv:26: Compile module "work@branch_predictor".
[INF:CP0304] third_party/cores/taiga/core/interfaces.sv:27: Compile interface "work@branch_predictor_interface".
[INF:CP0303] third_party/cores/taiga/core/branch_predictor_ram.sv:26: Compile module "work@branch_predictor_ram".
[INF:CP0303] third_party/cores/taiga/core/branch_unit.sv:26: Compile module "work@branch_unit".
[INF:CP0303] third_party/cores/taiga/core/byte_en_BRAM.sv:26: Compile module "work@byte_en_BRAM".
[INF:CP0303] third_party/cores/taiga/core/clz.sv:23: Compile module "work@clz".
[INF:CP0304] third_party/cores/taiga/core/interfaces.sv:76: Compile interface "work@csr_exception_interface".
[INF:CP0303] third_party/cores/taiga/core/csr_regs.sv:27: Compile module "work@csr_regs".
[INF:CP0303] third_party/cores/taiga/core/cycler.sv:24: Compile module "work@cycler".
[INF:CP0303] third_party/cores/taiga/core/dbram.sv:26: Compile module "work@dbram".
[INF:CP0303] third_party/cores/taiga/core/dcache.sv:26: Compile module "work@dcache".
[INF:CP0303] third_party/cores/taiga/core/ddata_bank.sv:26: Compile module "work@ddata_bank".
[INF:CP0303] third_party/cores/taiga/core/decode.sv:26: Compile module "work@decode".
[INF:CP0303] third_party/cores/taiga/core/div_algorithms/div_algorithm.sv:27: Compile module "work@div_algorithm".
[INF:CP0303] third_party/cores/taiga/core/div_algorithms/div_quick_clz.sv:25: Compile module "work@div_quick_clz".
[INF:CP0303] third_party/cores/taiga/core/div_algorithms/div_quick_clz_mk2.sv:25: Compile module "work@div_quick_clz_mk2".
[INF:CP0303] third_party/cores/taiga/core/div_algorithms/div_quick_naive.sv:25: Compile module "work@div_quick_naive".
[INF:CP0303] third_party/cores/taiga/core/div_algorithms/div_quick_radix4.sv:25: Compile module "work@div_quick_radix_4".
[INF:CP0303] third_party/cores/taiga/core/div_algorithms/div_radix16.sv:25: Compile module "work@div_radix16".
[INF:CP0303] third_party/cores/taiga/core/div_algorithms/div_radix2.sv:25: Compile module "work@div_radix2".
[INF:CP0303] third_party/cores/taiga/core/div_algorithms/div_radix2_ET.sv:25: Compile module "work@div_radix2_ET".
[INF:CP0303] third_party/cores/taiga/core/div_algorithms/div_radix2_ET_full.sv:25: Compile module "work@div_radix2_ET_full".
[INF:CP0303] third_party/cores/taiga/core/div_algorithms/div_radix4.sv:25: Compile module "work@div_radix4".
[INF:CP0303] third_party/cores/taiga/core/div_algorithms/div_radix4_ET.sv:25: Compile module "work@div_radix4_ET".
[INF:CP0303] third_party/cores/taiga/core/div_algorithms/div_radix4_ET_full.sv:25: Compile module "work@div_radix4_ET_full".
[INF:CP0303] third_party/cores/taiga/core/div_algorithms/div_radix8.sv:25: Compile module "work@div_radix8".
[INF:CP0303] third_party/cores/taiga/core/div_algorithms/div_radix8_ET.sv:25: Compile module "work@div_radix8_ET".
[INF:CP0303] third_party/cores/taiga/core/div_unit.sv:26: Compile module "work@div_unit".
[INF:CP0303] third_party/cores/taiga/core/div_unit_core_wrapper.sv:4: Compile module "work@div_unit_core_wrapper".
[INF:CP0303] third_party/cores/taiga/core/dtag_banks.sv:26: Compile module "work@dtag_banks".
[INF:CP0304] third_party/cores/taiga/core/interfaces.sv:90: Compile interface "work@exception_interface".
[INF:CP0303] third_party/cores/taiga/core/fetch.sv:26: Compile module "work@fetch".
[INF:CP0304] third_party/cores/taiga/core/interfaces.sv:227: Compile interface "work@fetch_sub_unit_interface".
[INF:CP0304] third_party/cores/taiga/core/interfaces.sv:157: Compile interface "work@fifo_interface".
[INF:CP0303] third_party/cores/taiga/core/gc_unit.sv:27: Compile module "work@gc_unit".
[INF:CP0303] third_party/cores/taiga/core/ibram.sv:26: Compile module "work@ibram".
[INF:CP0303] third_party/cores/taiga/core/icache.sv:26: Compile module "work@icache".
[INF:CP0303] third_party/cores/taiga/core/id_inuse.sv:26: Compile module "work@id_inuse".
[INF:CP0303] third_party/cores/taiga/core/id_tracking.sv:26: Compile module "work@id_tracking".
[INF:CP0303] third_party/cores/taiga/core/itag_banks.sv:26: Compile module "work@itag_banks".
[INF:CP0303] third_party/cores/taiga/core/l1_arbiter.sv:27: Compile module "work@l1_arbiter".
[INF:CP0304] third_party/cores/taiga/core/external_interfaces.sv:122: Compile interface "work@l1_arbiter_request_interface".
[INF:CP0304] third_party/cores/taiga/core/external_interfaces.sv:148: Compile interface "work@l1_arbiter_return_interface".
[INF:CP0303] third_party/cores/taiga/l2_arbiter/l2_arbiter.sv:26: Compile module "work@l2_arbiter".
[INF:CP0304] third_party/cores/taiga/l2_arbiter/l2_interfaces.sv:38: Compile interface "work@l2_arbitration_interface".
[INF:CP0303] third_party/cores/taiga/l2_arbiter/l2_fifo.sv:23: Compile module "work@l2_fifo".
[INF:CP0304] third_party/cores/taiga/l2_arbiter/l2_interfaces.sv:25: Compile interface "work@l2_fifo_interface".
[INF:CP0304] third_party/cores/taiga/l2_arbiter/l2_external_interfaces.sv:69: Compile interface "work@l2_memory_interface".
[INF:CP0304] third_party/cores/taiga/l2_arbiter/l2_external_interfaces.sv:25: Compile interface "work@l2_requester_interface".
[INF:CP0303] third_party/cores/taiga/l2_arbiter/l2_reservation_logic.sv:25: Compile module "work@l2_reservation_logic".
[INF:CP0303] third_party/cores/taiga/l2_arbiter/l2_round_robin.sv:25: Compile module "work@l2_round_robin".
[INF:CP0303] third_party/cores/taiga/core/load_store_unit.sv:26: Compile module "work@load_store_unit".
[INF:CP0303] third_party/cores/taiga/local_memory/local_mem.sv:24: Compile module "work@local_mem".
[INF:CP0304] third_party/cores/taiga/local_memory/local_memory_interface.sv:24: Compile interface "work@local_memory_interface".
[INF:CP0304] third_party/cores/taiga/core/interfaces.sv:212: Compile interface "work@ls_sub_unit_interface".
[INF:CP0303] third_party/cores/taiga/core/lut_ram.sv:23: Compile module "work@lut_ram".
[INF:CP0303] third_party/cores/taiga/core/mmu.sv:27: Compile module "work@mmu".
[INF:CP0304] third_party/cores/taiga/core/interfaces.sv:170: Compile interface "work@mmu_interface".
[INF:CP0303] third_party/cores/taiga/core/msb.sv:23: Compile module "work@msb".
[INF:CP0303] third_party/cores/taiga/core/msb_naive.sv:25: Compile module "work@msb_naive".
[INF:CP0303] third_party/cores/taiga/core/mstatus_priv_reg.sv:27: Compile module "work@mstatus_priv_reg".
[INF:CP0303] third_party/cores/taiga/core/mul_unit.sv:26: Compile module "work@mul_unit".
[INF:CP0303] third_party/cores/taiga/core/one_hot_occupancy.sv:26: Compile module "work@one_hot_occupancy".
[INF:CP0303] third_party/cores/taiga/core/one_hot_to_integer.sv:25: Compile module "work@one_hot_to_integer".
[INF:CP0303] third_party/cores/taiga/core/placer_randomizer.sv:1: Compile module "work@placer_randomizer".
[INF:CP0304] third_party/cores/taiga/core/interfaces.sv:257: Compile interface "work@post_issue_forwarding_interface".
[INF:CP0303] third_party/cores/taiga/core/pre_decode.sv:26: Compile module "work@pre_decode".
[INF:CP0303] third_party/cores/taiga/core/ras.sv:26: Compile module "work@ras".
[INF:CP0304] third_party/cores/taiga/core/interfaces.sv:64: Compile interface "work@ras_interface".
[INF:CP0303] third_party/cores/taiga/core/register_file.sv:26: Compile module "work@register_file".
[INF:CP0304] third_party/cores/taiga/core/interfaces.sv:103: Compile interface "work@register_file_decode_interface".
[INF:CP0304] third_party/cores/taiga/core/interfaces.sv:123: Compile interface "work@register_file_writeback_interface".
[INF:CP0303] third_party/cores/taiga/core/shift_counter.sv:26: Compile module "work@shift_counter".
[INF:CP0303] third_party/cores/taiga/core/tag_bank.sv:26: Compile module "work@tag_bank".
[INF:CP0303] third_party/cores/taiga/core/taiga.sv:26: Compile module "work@taiga".
[INF:CP0303] third_party/cores/taiga/core/taiga_fifo.sv:31: Compile module "work@taiga_fifo".
[INF:CP0303] third_party/cores/taiga/examples/zedboard/taiga_wrapper.sv:27: Compile module "work@taiga_wrapper".
[INF:CP0304] third_party/cores/taiga/core/interfaces.sv:193: Compile interface "work@tlb_interface".
[INF:CP0303] third_party/cores/taiga/core/tlb_lut_ram.sv:26: Compile module "work@tlb_lut_ram".
[INF:CP0304] third_party/cores/taiga/core/interfaces.sv:145: Compile interface "work@tracking_interface".
[INF:CP0304] third_party/cores/taiga/core/interfaces.sv:52: Compile interface "work@unit_issue_interface".
[INF:CP0304] third_party/cores/taiga/core/interfaces.sv:243: Compile interface "work@unsigned_division_interface".
[INF:CP0304] third_party/cores/taiga/core/external_interfaces.sv:105: Compile interface "work@wishbone_interface".
[INF:CP0303] third_party/cores/taiga/core/wishbone_master.sv:27: Compile module "work@wishbone_master".
[INF:CP0303] third_party/cores/taiga/core/write_back.sv:26: Compile module "work@write_back".
[ERR:UH0700] third_party/cores/taiga/core/branch_unit.sv:111: Unsupported expression "<n<> u<904> t<Unique> p<905> l<111>> unique if (branch_inputs.jalr)
".
[ERR:UH0700] third_party/cores/taiga/core/mstatus_priv_reg.sv:57: Unsupported expression "<n<> u<325> t<Unique> p<326> l<57>> unique if(mret | sret)
".
[ERR:UH0700] third_party/cores/taiga/core/mstatus_priv_reg.sv:94: Unsupported expression "<n<> u<720> t<Unique> p<721> l<94>> unique if (sret) begin
".
[ERR:UH0700] third_party/cores/taiga/core/mstatus_priv_reg.sv:112: Unsupported expression "<n<> u<1004> t<Unique> p<1005> l<112>> unique if (write_msr_m | write_msr_s)
".
[NTE:CP0309] third_party/cores/taiga/core/alu_unit.sv:31: Implicit port type (wire) for "wb".
[NTE:CP0309] third_party/cores/taiga/core/branch_unit.sv:32: Implicit port type (wire) for "br_results",
there are 1 more instances of this message.
[NTE:CP0309] third_party/cores/taiga/core/csr_regs.sv:37: Implicit port type (wire) for "csr_exception".
[NTE:CP0309] third_party/cores/taiga/core/decode.sv:37: Implicit port type (wire) for "alu_inputs",
there are 5 more instances of this message.
[NTE:CP0309] third_party/cores/taiga/core/div_unit.sv:35: Implicit port type (wire) for "wb".
[NTE:CP0309] third_party/cores/taiga/core/dtag_banks.sv:43: Implicit port type (wire) for "tag_hit".
[NTE:CP0309] third_party/cores/taiga/core/fetch.sv:49: Implicit port type (wire) for "branch_metadata".
[NTE:CP0309] third_party/cores/taiga/core/gc_unit.sv:73: Implicit port type (wire) for "csr_id".
[NTE:CP0309] third_party/cores/taiga/core/id_tracking.sv:33: Implicit port type (wire) for "oldest_id",
there are 1 more instances of this message.
[NTE:CP0309] third_party/cores/taiga/core/itag_banks.sv:38: Implicit port type (wire) for "tag_hit".
[NTE:CP0309] third_party/cores/taiga/core/l1_arbiter.sv:34: Implicit port type (wire) for "sc_complete",
there are 1 more instances of this message.
[NTE:CP0309] third_party/cores/taiga/core/load_store_unit.sv:51: Implicit port type (wire) for "store_done_id",
there are 2 more instances of this message.
[NTE:CP0309] third_party/cores/taiga/core/mmu.sv:34: Implicit port type (wire) for "mmu_exception".
[NTE:CP0309] third_party/cores/taiga/core/mstatus_priv_reg.sv:43: Implicit port type (wire) for "mstatus",
there are 1 more instances of this message.
[NTE:CP0309] third_party/cores/taiga/core/mul_unit.sv:32: Implicit port type (wire) for "wb".
[NTE:CP0309] third_party/cores/taiga/core/pre_decode.sv:45: Implicit port type (wire) for "fb".
[NTE:CP0309] third_party/cores/taiga/core/taiga.sv:37: Implicit port type (wire) for "tr".
[NTE:CP0309] third_party/cores/taiga/examples/zedboard/taiga_wrapper.sv:32: Implicit port type (wire) for "DDR_addr",
there are 20 more instances of this message.
[NTE:CP0309] third_party/cores/taiga/core/write_back.sv:38: Implicit port type (wire) for "oldest_id".
[INF:EL0526] Design Elaboration...
[INF:CP0335] third_party/cores/taiga/core/byte_en_BRAM.sv:47: Compile generate block "work@local_mem.inst_data_ram.genblk1".
[INF:CP0335] third_party/cores/taiga/core/taiga.sv:154: Compile generate block "work@taiga_wrapper.cpu.genblk1".
[INF:CP0335] third_party/cores/taiga/core/l1_arbiter.sv:54: Compile generate block "work@taiga_wrapper.cpu.genblk1.arb.genblk1[0]".
[INF:CP0335] third_party/cores/taiga/core/l1_arbiter.sv:54: Compile generate block "work@taiga_wrapper.cpu.genblk1.arb.genblk1[1]".
[INF:CP0335] third_party/cores/taiga/core/l1_arbiter.sv:54: Compile generate block "work@taiga_wrapper.cpu.genblk1.arb.genblk1[2]".
[INF:CP0335] third_party/cores/taiga/core/l1_arbiter.sv:54: Compile generate block "work@taiga_wrapper.cpu.genblk1.arb.genblk1[3]".
[INF:CP0335] third_party/cores/taiga/core/l1_arbiter.sv:54: Compile generate block "work@taiga_wrapper.cpu.genblk1.arb.genblk1[4]".
[INF:CP0335] third_party/cores/taiga/core/l1_arbiter.sv:54: Compile generate block "work@taiga_wrapper.cpu.genblk1.arb.genblk1[5]".
[INF:CP0335] third_party/cores/taiga/core/l1_arbiter.sv:54: Compile generate block "work@taiga_wrapper.cpu.genblk1.arb.genblk1[6]".
[INF:CP0335] third_party/cores/taiga/core/l1_arbiter.sv:54: Compile generate block "work@taiga_wrapper.cpu.genblk1.arb.genblk1[7]".
[INF:CP0335] third_party/cores/taiga/core/l1_arbiter.sv:54: Compile generate block "work@taiga_wrapper.cpu.genblk1.arb.genblk1[8]".
[INF:CP0335] third_party/cores/taiga/core/l1_arbiter.sv:61: Compile generate block "work@taiga_wrapper.cpu.genblk1.arb.genblk2".
[INF:CP0335] third_party/cores/taiga/core/l1_arbiter.sv:90: Compile generate block "work@taiga_wrapper.cpu.genblk1.arb.genblk3".
[INF:CP0335] third_party/cores/taiga/core/l1_arbiter.sv:98: Compile generate block "work@taiga_wrapper.cpu.genblk1.arb.genblk4".
[INF:CP0335] third_party/cores/taiga/core/l1_arbiter.sv:108: Compile generate block "work@taiga_wrapper.cpu.genblk1.arb.genblk5".
[INF:CP0335] third_party/cores/taiga/core/l1_arbiter.sv:120: Compile generate block "work@taiga_wrapper.cpu.genblk1.arb.genblk6".
[INF:CP0335] third_party/cores/taiga/core/l1_arbiter.sv:180: Compile generate block "work@taiga_wrapper.cpu.genblk1.arb.genblk8[0]".
[INF:CP0335] third_party/cores/taiga/core/l1_arbiter.sv:180: Compile generate block "work@taiga_wrapper.cpu.genblk1.arb.genblk8[1]".
[INF:CP0335] third_party/cores/taiga/core/l1_arbiter.sv:180: Compile generate block "work@taiga_wrapper.cpu.genblk1.arb.genblk8[2]".
[INF:CP0335] third_party/cores/taiga/core/l1_arbiter.sv:180: Compile generate block "work@taiga_wrapper.cpu.genblk1.arb.genblk8[3]".
[INF:CP0335] third_party/cores/taiga/core/l1_arbiter.sv:180: Compile generate block "work@taiga_wrapper.cpu.genblk1.arb.genblk8[4]".
[INF:CP0335] third_party/cores/taiga/core/l1_arbiter.sv:180: Compile generate block "work@taiga_wrapper.cpu.genblk1.arb.genblk8[5]".
[INF:CP0335] third_party/cores/taiga/core/l1_arbiter.sv:180: Compile generate block "work@taiga_wrapper.cpu.genblk1.arb.genblk8[6]".
[INF:CP0335] third_party/cores/taiga/core/l1_arbiter.sv:180: Compile generate block "work@taiga_wrapper.cpu.genblk1.arb.genblk8[7]".
[INF:CP0335] third_party/cores/taiga/core/l1_arbiter.sv:180: Compile generate block "work@taiga_wrapper.cpu.genblk1.arb.genblk8[8]".
[INF:CP0335] third_party/cores/taiga/core/one_hot_to_integer.sv:40: Compile generate block "work@taiga_wrapper.cpu.fetch_block.hit_way_conv.genblk1".
[INF:CP0335] third_party/cores/taiga/core/taiga_fifo.sv:65: Compile generate block "work@taiga_wrapper.cpu.fetch_block.attributes_fifo.genblk1".
[INF:CP0335] third_party/cores/taiga/core/fetch.sv:154: Compile generate block "work@taiga_wrapper.cpu.fetch_block.genblk1[0]".
[INF:CP0335] third_party/cores/taiga/core/fetch.sv:154: Compile generate block "work@taiga_wrapper.cpu.fetch_block.genblk1[1]".
[INF:CP0335] third_party/cores/taiga/core/fetch.sv:154: Compile generate block "work@taiga_wrapper.cpu.fetch_block.genblk1[2]".
[INF:CP0335] third_party/cores/taiga/core/fetch.sv:154: Compile generate block "work@taiga_wrapper.cpu.fetch_block.genblk1[3]".
[INF:CP0335] third_party/cores/taiga/core/fetch.sv:154: Compile generate block "work@taiga_wrapper.cpu.fetch_block.genblk1[4]".
[INF:CP0335] third_party/cores/taiga/core/fetch.sv:154: Compile generate block "work@taiga_wrapper.cpu.fetch_block.genblk1[5]".
[INF:CP0335] third_party/cores/taiga/core/fetch.sv:154: Compile generate block "work@taiga_wrapper.cpu.fetch_block.genblk1[6]".
[INF:CP0335] third_party/cores/taiga/core/fetch.sv:154: Compile generate block "work@taiga_wrapper.cpu.fetch_block.genblk1[7]".
[INF:CP0335] third_party/cores/taiga/core/fetch.sv:154: Compile generate block "work@taiga_wrapper.cpu.fetch_block.genblk1[8]".
[INF:CP0335] third_party/cores/taiga/core/fetch.sv:167: Compile generate block "work@taiga_wrapper.cpu.fetch_block.genblk2".
[INF:CP0335] third_party/cores/taiga/core/fetch.sv:172: Compile generate block "work@taiga_wrapper.cpu.fetch_block.genblk3".
[INF:CP0335] third_party/cores/taiga/core/cycler.sv:36: Compile generate block "work@taiga_wrapper.cpu.fetch_block.genblk3.i_cache.replacement_policy.genblk1".
[INF:CP0335] third_party/cores/taiga/core/itag_banks.sv:68: Compile generate block "work@taiga_wrapper.cpu.fetch_block.genblk3.i_cache.icache_tag_banks.tag_bank_gen[0]".
[INF:CP0335] third_party/cores/taiga/core/icache.sv:130: Compile generate block "work@taiga_wrapper.cpu.fetch_block.genblk3.i_cache.idata_bank_gen[0]".
[INF:CP0335] third_party/cores/taiga/core/byte_en_BRAM.sv:47: Compile generate block "work@taiga_wrapper.cpu.fetch_block.genblk3.i_cache.idata_bank_gen[0].idata_bank.genblk1".
[INF:CP0335] third_party/cores/taiga/core/cycler.sv:39: Compile generate block "work@taiga_wrapper.cpu.bp_block.replacement_policy.genblk1".
[INF:CP0335] third_party/cores/taiga/core/branch_predictor.sv:60: Compile generate block "work@taiga_wrapper.cpu.bp_block.branch_tag_banks".
[INF:CP0335] third_party/cores/taiga/core/branch_predictor.sv:61: Compile generate block "work@taiga_wrapper.cpu.bp_block.branch_tag_banks.branch_tag_banks[0]".
[INF:CP0335] third_party/cores/taiga/core/branch_predictor.sv:61: Compile generate block "work@taiga_wrapper.cpu.bp_block.branch_tag_banks.branch_tag_banks[1]".
[INF:CP0335] third_party/cores/taiga/core/branch_predictor.sv:61: Compile generate block "work@taiga_wrapper.cpu.bp_block.branch_tag_banks.branch_tag_banks[2]".
[INF:CP0335] third_party/cores/taiga/core/branch_predictor.sv:61: Compile generate block "work@taiga_wrapper.cpu.bp_block.branch_tag_banks.branch_tag_banks[3]".
[INF:CP0335] third_party/cores/taiga/core/branch_predictor.sv:61: Compile generate block "work@taiga_wrapper.cpu.bp_block.branch_tag_banks.branch_tag_banks[4]".
[INF:CP0335] third_party/cores/taiga/core/branch_predictor.sv:61: Compile generate block "work@taiga_wrapper.cpu.bp_block.branch_tag_banks.branch_tag_banks[5]".
[INF:CP0335] third_party/cores/taiga/core/branch_predictor.sv:61: Compile generate block "work@taiga_wrapper.cpu.bp_block.branch_tag_banks.branch_tag_banks[6]".
[INF:CP0335] third_party/cores/taiga/core/branch_predictor.sv:61: Compile generate block "work@taiga_wrapper.cpu.bp_block.branch_tag_banks.branch_tag_banks[7]".
[INF:CP0335] third_party/cores/taiga/core/branch_predictor.sv:61: Compile generate block "work@taiga_wrapper.cpu.bp_block.branch_tag_banks.branch_tag_banks[8]".
[INF:CP0335] third_party/cores/taiga/core/branch_predictor.sv:69: Compile generate block "work@taiga_wrapper.cpu.bp_block.branch_table_banks".
[INF:CP0335] third_party/cores/taiga/core/branch_predictor.sv:70: Compile generate block "work@taiga_wrapper.cpu.bp_block.branch_table_banks.branch_table_banks[0]".
[INF:CP0335] third_party/cores/taiga/core/branch_predictor.sv:70: Compile generate block "work@taiga_wrapper.cpu.bp_block.branch_table_banks.branch_table_banks[1]".
[INF:CP0335] third_party/cores/taiga/core/branch_predictor.sv:70: Compile generate block "work@taiga_wrapper.cpu.bp_block.branch_table_banks.branch_table_banks[2]".
[INF:CP0335] third_party/cores/taiga/core/branch_predictor.sv:70: Compile generate block "work@taiga_wrapper.cpu.bp_block.branch_table_banks.branch_table_banks[3]".
[INF:CP0335] third_party/cores/taiga/core/branch_predictor.sv:70: Compile generate block "work@taiga_wrapper.cpu.bp_block.branch_table_banks.branch_table_banks[4]".
[INF:CP0335] third_party/cores/taiga/core/branch_predictor.sv:70: Compile generate block "work@taiga_wrapper.cpu.bp_block.branch_table_banks.branch_table_banks[5]".
[INF:CP0335] third_party/cores/taiga/core/branch_predictor.sv:70: Compile generate block "work@taiga_wrapper.cpu.bp_block.branch_table_banks.branch_table_banks[6]".
[INF:CP0335] third_party/cores/taiga/core/branch_predictor.sv:70: Compile generate block "work@taiga_wrapper.cpu.bp_block.branch_table_banks.branch_table_banks[7]".
[INF:CP0335] third_party/cores/taiga/core/branch_predictor.sv:70: Compile generate block "work@taiga_wrapper.cpu.bp_block.branch_table_banks.branch_table_banks[8]".
[INF:CP0335] third_party/cores/taiga/core/branch_predictor.sv:78: Compile generate block "work@taiga_wrapper.cpu.bp_block.branch_hit_detection".
[INF:CP0335] third_party/cores/taiga/core/branch_predictor.sv:79: Compile generate block "work@taiga_wrapper.cpu.bp_block.branch_hit_detection.branch_hit_detection[0]".
[INF:CP0335] third_party/cores/taiga/core/branch_predictor.sv:79: Compile generate block "work@taiga_wrapper.cpu.bp_block.branch_hit_detection.branch_hit_detection[1]".
[INF:CP0335] third_party/cores/taiga/core/branch_predictor.sv:79: Compile generate block "work@taiga_wrapper.cpu.bp_block.branch_hit_detection.branch_hit_detection[2]".
[INF:CP0335] third_party/cores/taiga/core/branch_predictor.sv:79: Compile generate block "work@taiga_wrapper.cpu.bp_block.branch_hit_detection.branch_hit_detection[3]".
[INF:CP0335] third_party/cores/taiga/core/branch_predictor.sv:79: Compile generate block "work@taiga_wrapper.cpu.bp_block.branch_hit_detection.branch_hit_detection[4]".
[INF:CP0335] third_party/cores/taiga/core/branch_predictor.sv:79: Compile generate block "work@taiga_wrapper.cpu.bp_block.branch_hit_detection.branch_hit_detection[5]".
[INF:CP0335] third_party/cores/taiga/core/branch_predictor.sv:79: Compile generate block "work@taiga_wrapper.cpu.bp_block.branch_hit_detection.branch_hit_detection[6]".
[INF:CP0335] third_party/cores/taiga/core/branch_predictor.sv:79: Compile generate block "work@taiga_wrapper.cpu.bp_block.branch_hit_detection.branch_hit_detection[7]".
[INF:CP0335] third_party/cores/taiga/core/branch_predictor.sv:79: Compile generate block "work@taiga_wrapper.cpu.bp_block.branch_hit_detection.branch_hit_detection[8]".
[INF:CP0335] third_party/cores/taiga/core/branch_predictor.sv:84: Compile generate block "work@taiga_wrapper.cpu.bp_block.genblk1".
[INF:CP0335] third_party/cores/taiga/core/one_hot_to_integer.sv:40: Compile generate block "work@taiga_wrapper.cpu.bp_block.genblk1.hit_way_conv.genblk1".
[INF:CP0335] third_party/cores/taiga/core/branch_predictor.sv:119: Compile generate block "work@taiga_wrapper.cpu.bp_block.genblk2".
[INF:CP0335] third_party/cores/taiga/core/taiga.sv:167: Compile generate block "work@taiga_wrapper.cpu.genblk2".
[INF:CP0335] third_party/cores/taiga/core/taiga_fifo.sv:65: Compile generate block "work@taiga_wrapper.cpu.pre_decode_block.fb_fifo_block.genblk1".
[INF:CP0335] third_party/cores/taiga/core/decode.sv:177: Compile generate block "work@taiga_wrapper.cpu.decode_block.genblk1".
[INF:CP0335] third_party/cores/taiga/core/decode.sv:181: Compile generate block "work@taiga_wrapper.cpu.decode_block.genblk2".
[INF:CP0335] third_party/cores/taiga/core/decode.sv:190: Compile generate block "work@taiga_wrapper.cpu.decode_block.genblk3[0]".
[INF:CP0335] third_party/cores/taiga/core/decode.sv:190: Compile generate block "work@taiga_wrapper.cpu.decode_block.genblk3[1]".
[INF:CP0335] third_party/cores/taiga/core/decode.sv:256: Compile generate block "work@taiga_wrapper.cpu.decode_block.genblk4".
[INF:CP0335] third_party/cores/taiga/core/decode.sv:332: Compile generate block "work@taiga_wrapper.cpu.decode_block.genblk5".
[INF:CP0335] third_party/cores/taiga/core/decode.sv:342: Compile generate block "work@taiga_wrapper.cpu.decode_block.genblk6".
[INF:CP0335] third_party/cores/taiga/core/decode.sv:390: Compile generate block "work@taiga_wrapper.cpu.decode_block.genblk7[0]".
[INF:CP0335] third_party/cores/taiga/core/decode.sv:390: Compile generate block "work@taiga_wrapper.cpu.decode_block.genblk7[1]".
[INF:CP0335] third_party/cores/taiga/core/decode.sv:425: Compile generate block "work@taiga_wrapper.cpu.decode_block.genblk8".
[INF:CP0335] third_party/cores/taiga/core/register_file.sv:121: Compile generate block "work@taiga_wrapper.cpu.register_file_block.genblk1".
[INF:CP0335] third_party/cores/taiga/core/branch_unit.sv:171: Compile generate block "work@taiga_wrapper.cpu.branch_unit_block.genblk1".
[INF:CP0335] third_party/cores/taiga/core/branch_unit.sv:193: Compile generate block "work@taiga_wrapper.cpu.branch_unit_block.genblk2".
[INF:CP0335] third_party/cores/taiga/core/taiga_fifo.sv:65: Compile generate block "work@taiga_wrapper.cpu.load_store_unit_block.ls_input_fifo.genblk1".
[INF:CP0335] third_party/cores/taiga/core/one_hot_to_integer.sv:40: Compile generate block "work@taiga_wrapper.cpu.load_store_unit_block.hit_way_conv.genblk1".
[INF:CP0335] third_party/cores/taiga/core/taiga_fifo.sv:65: Compile generate block "work@taiga_wrapper.cpu.load_store_unit_block.attributes_fifo.genblk1".
[INF:CP0335] third_party/cores/taiga/core/load_store_unit.sv:277: Compile generate block "work@taiga_wrapper.cpu.load_store_unit_block.genblk1".
[INF:CP0335] third_party/cores/taiga/core/load_store_unit.sv:288: Compile generate block "work@taiga_wrapper.cpu.load_store_unit_block.genblk2".
[INF:CP0335] third_party/cores/taiga/core/load_store_unit.sv:297: Compile generate block "work@taiga_wrapper.cpu.load_store_unit_block.genblk2.genblk1".
[INF:CP0335] third_party/cores/taiga/core/load_store_unit.sv:299: Compile generate block "work@taiga_wrapper.cpu.load_store_unit_block.genblk2.genblk1.genblk1".
[INF:CP0335] third_party/cores/taiga/core/load_store_unit.sv:305: Compile generate block "work@taiga_wrapper.cpu.load_store_unit_block.genblk3".
[INF:CP0335] third_party/cores/taiga/core/cycler.sv:39: Compile generate block "work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.replacement_policy.genblk1".
[INF:CP0335] third_party/cores/taiga/core/one_hot_to_integer.sv:40: Compile generate block "work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.hit_way_conv.genblk1".
[INF:CP0335] third_party/cores/taiga/core/one_hot_to_integer.sv:40: Compile generate block "work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.update_way_conv.genblk1".
[INF:CP0335] third_party/cores/taiga/core/dtag_banks.sv:107: Compile generate block "work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.dcache_tag_banks.dtag_bank_gen[0]".
[INF:CP0335] third_party/cores/taiga/core/dtag_banks.sv:107: Compile generate block "work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.dcache_tag_banks.dtag_bank_gen[1]".
[INF:CP0335] third_party/cores/taiga/core/dtag_banks.sv:107: Compile generate block "work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.dcache_tag_banks.dtag_bank_gen[2]".
[INF:CP0335] third_party/cores/taiga/core/dtag_banks.sv:107: Compile generate block "work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.dcache_tag_banks.dtag_bank_gen[3]".
[INF:CP0335] third_party/cores/taiga/core/dcache.sv:211: Compile generate block "work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.genblk1".
[INF:CP0335] third_party/cores/taiga/core/byte_en_BRAM.sv:47: Compile generate block "work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.data_bank.ram_block.genblk1".
[INF:CP0335] third_party/cores/taiga/core/taiga.sv:188: Compile generate block "work@taiga_wrapper.cpu.genblk3".
[INF:CP0335] third_party/cores/taiga/core/csr_regs.sv:191: Compile generate block "work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1".
[INF:CP0335] third_party/cores/taiga/core/csr_regs.sv:420: Compile generate block "work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk2".
[INF:CP0335] third_party/cores/taiga/core/taiga.sv:195: Compile generate block "work@taiga_wrapper.cpu.genblk4".
[INF:CP0335] third_party/cores/taiga/core/taiga.sv:198: Compile generate block "work@taiga_wrapper.cpu.genblk5".
[INF:CP0335] third_party/cores/taiga/core/taiga_fifo.sv:65: Compile generate block "work@taiga_wrapper.cpu.genblk5.div_unit_block.div_input_fifo.genblk1".
[INF:CP0335] third_party/cores/taiga/core/write_back.sv:85: Compile generate block "work@taiga_wrapper.cpu.write_back_mux.interface_to_array_g[0]".
[INF:CP0335] third_party/cores/taiga/core/write_back.sv:85: Compile generate block "work@taiga_wrapper.cpu.write_back_mux.interface_to_array_g[1]".
[INF:CP0335] third_party/cores/taiga/core/write_back.sv:90: Compile generate block "work@taiga_wrapper.cpu.write_back_mux.genblk1[2]".
[INF:CP0335] third_party/cores/taiga/core/write_back.sv:90: Compile generate block "work@taiga_wrapper.cpu.write_back_mux.genblk1[3]".
[INF:CP0335] third_party/cores/taiga/core/write_back.sv:122: Compile generate block "work@taiga_wrapper.cpu.write_back_mux.genblk2[0]".
[INF:CP0335] third_party/cores/taiga/core/write_back.sv:122: Compile generate block "work@taiga_wrapper.cpu.write_back_mux.genblk2[1]".
[INF:CP0335] third_party/cores/taiga/core/write_back.sv:122: Compile generate block "work@taiga_wrapper.cpu.write_back_mux.genblk2[2]".
[INF:CP0335] third_party/cores/taiga/core/write_back.sv:122: Compile generate block "work@taiga_wrapper.cpu.write_back_mux.genblk2[3]".
[INF:CP0335] third_party/cores/taiga/core/write_back.sv:122: Compile generate block "work@taiga_wrapper.cpu.write_back_mux.genblk2[4]".
[INF:CP0335] third_party/cores/taiga/core/write_back.sv:122: Compile generate block "work@taiga_wrapper.cpu.write_back_mux.genblk2[5]".
[INF:CP0335] third_party/cores/taiga/core/write_back.sv:122: Compile generate block "work@taiga_wrapper.cpu.write_back_mux.genblk2[6]".
[INF:CP0335] third_party/cores/taiga/core/write_back.sv:122: Compile generate block "work@taiga_wrapper.cpu.write_back_mux.genblk2[7]".
[INF:CP0335] third_party/cores/taiga/core/write_back.sv:122: Compile generate block "work@taiga_wrapper.cpu.write_back_mux.genblk2[8]".
[INF:CP0335] third_party/cores/taiga/core/write_back.sv:122: Compile generate block "work@taiga_wrapper.cpu.write_back_mux.genblk2[9]".
[INF:CP0335] third_party/cores/taiga/core/write_back.sv:122: Compile generate block "work@taiga_wrapper.cpu.write_back_mux.genblk2[10]".
[INF:CP0335] third_party/cores/taiga/core/write_back.sv:122: Compile generate block "work@taiga_wrapper.cpu.write_back_mux.genblk2[11]".
[INF:CP0335] third_party/cores/taiga/core/write_back.sv:122: Compile generate block "work@taiga_wrapper.cpu.write_back_mux.genblk2[12]".
[INF:CP0335] third_party/cores/taiga/core/write_back.sv:122: Compile generate block "work@taiga_wrapper.cpu.write_back_mux.genblk2[13]".
[INF:CP0335] third_party/cores/taiga/core/write_back.sv:122: Compile generate block "work@taiga_wrapper.cpu.write_back_mux.genblk2[14]".
[INF:CP0335] third_party/cores/taiga/core/write_back.sv:122: Compile generate block "work@taiga_wrapper.cpu.write_back_mux.genblk2[15]".
[INF:CP0335] third_party/cores/taiga/core/write_back.sv:122: Compile generate block "work@taiga_wrapper.cpu.write_back_mux.genblk2[16]".
[INF:CP0335] third_party/cores/taiga/core/write_back.sv:122: Compile generate block "work@taiga_wrapper.cpu.write_back_mux.genblk2[17]".
[INF:CP0335] third_party/cores/taiga/core/write_back.sv:122: Compile generate block "work@taiga_wrapper.cpu.write_back_mux.genblk2[18]".
[INF:CP0335] third_party/cores/taiga/core/write_back.sv:140: Compile generate block "work@taiga_wrapper.cpu.write_back_mux.genblk3[0]".
[INF:CP0335] third_party/cores/taiga/core/write_back.sv:140: Compile generate block "work@taiga_wrapper.cpu.write_back_mux.genblk3[1]".
[INF:CP0335] third_party/cores/taiga/core/write_back.sv:140: Compile generate block "work@taiga_wrapper.cpu.write_back_mux.genblk3[2]".
[INF:CP0335] third_party/cores/taiga/core/write_back.sv:140: Compile generate block "work@taiga_wrapper.cpu.write_back_mux.genblk3[3]".
[INF:CP0335] third_party/cores/taiga/core/write_back.sv:140: Compile generate block "work@taiga_wrapper.cpu.write_back_mux.genblk3[4]".
[INF:CP0335] third_party/cores/taiga/core/write_back.sv:140: Compile generate block "work@taiga_wrapper.cpu.write_back_mux.genblk3[5]".
[INF:CP0335] third_party/cores/taiga/core/write_back.sv:140: Compile generate block "work@taiga_wrapper.cpu.write_back_mux.genblk3[6]".
[INF:CP0335] third_party/cores/taiga/core/write_back.sv:140: Compile generate block "work@taiga_wrapper.cpu.write_back_mux.genblk3[7]".
[INF:CP0335] third_party/cores/taiga/core/write_back.sv:140: Compile generate block "work@taiga_wrapper.cpu.write_back_mux.genblk3[8]".
[INF:CP0335] third_party/cores/taiga/core/write_back.sv:140: Compile generate block "work@taiga_wrapper.cpu.write_back_mux.genblk3[9]".
[INF:CP0335] third_party/cores/taiga/core/write_back.sv:140: Compile generate block "work@taiga_wrapper.cpu.write_back_mux.genblk3[10]".
[INF:CP0335] third_party/cores/taiga/core/write_back.sv:140: Compile generate block "work@taiga_wrapper.cpu.write_back_mux.genblk3[11]".
[INF:CP0335] third_party/cores/taiga/core/write_back.sv:140: Compile generate block "work@taiga_wrapper.cpu.write_back_mux.genblk3[12]".
[INF:CP0335] third_party/cores/taiga/core/write_back.sv:140: Compile generate block "work@taiga_wrapper.cpu.write_back_mux.genblk3[13]".
[INF:CP0335] third_party/cores/taiga/core/write_back.sv:140: Compile generate block "work@taiga_wrapper.cpu.write_back_mux.genblk3[14]".
[INF:CP0335] third_party/cores/taiga/core/write_back.sv:140: Compile generate block "work@taiga_wrapper.cpu.write_back_mux.genblk3[15]".
[INF:CP0335] third_party/cores/taiga/core/write_back.sv:140: Compile generate block "work@taiga_wrapper.cpu.write_back_mux.genblk3[16]".
[INF:CP0335] third_party/cores/taiga/core/write_back.sv:140: Compile generate block "work@taiga_wrapper.cpu.write_back_mux.genblk3[17]".
[INF:CP0335] third_party/cores/taiga/core/write_back.sv:140: Compile generate block "work@taiga_wrapper.cpu.write_back_mux.genblk3[18]".
[INF:CP0335] third_party/cores/taiga/core/write_back.sv:231: Compile generate block "work@taiga_wrapper.cpu.write_back_mux.genblk4".
[INF:CP0335] third_party/cores/taiga/core/taiga.sv:223: Compile generate block "work@taiga_wrapper.cpu.genblk6".
[INF:CP0335] third_party/cores/taiga/examples/zedboard/taiga_wrapper.sv:238: Compile generate block "work@taiga_wrapper.genblk1".
[INF:CP0335] third_party/cores/taiga/l2_arbiter/l2_arbiter.sv:88: Compile generate block "work@taiga_wrapper.genblk1.l2_arb.genblk1[0]".
[INF:CP0335] third_party/cores/taiga/l2_arbiter/l2_fifo.sv:37: Compile generate block "work@taiga_wrapper.genblk1.l2_arb.genblk1[0].input_fifo.genblk1".
[INF:CP0335] third_party/cores/taiga/l2_arbiter/l2_fifo.sv:54: Compile generate block "work@taiga_wrapper.genblk1.l2_arb.genblk1[0].input_fifo.genblk1.genblk1".
[INF:CP0335] third_party/cores/taiga/l2_arbiter/l2_arbiter.sv:88: Compile generate block "work@taiga_wrapper.genblk1.l2_arb.genblk1[1]".
[INF:CP0335] third_party/cores/taiga/l2_arbiter/l2_fifo.sv:37: Compile generate block "work@taiga_wrapper.genblk1.l2_arb.genblk1[1].input_fifo.genblk1".
[INF:CP0335] third_party/cores/taiga/l2_arbiter/l2_fifo.sv:54: Compile generate block "work@taiga_wrapper.genblk1.l2_arb.genblk1[1].input_fifo.genblk1.genblk1".
[INF:CP0335] third_party/cores/taiga/l2_arbiter/l2_arbiter.sv:118: Compile generate block "work@taiga_wrapper.genblk1.l2_arb.genblk2[0]".
[INF:CP0335] third_party/cores/taiga/l2_arbiter/l2_fifo.sv:37: Compile generate block "work@taiga_wrapper.genblk1.l2_arb.genblk2[0].input_data_fifo.genblk1".
[INF:CP0335] third_party/cores/taiga/l2_arbiter/l2_fifo.sv:54: Compile generate block "work@taiga_wrapper.genblk1.l2_arb.genblk2[0].input_data_fifo.genblk1.genblk1".
[INF:CP0335] third_party/cores/taiga/l2_arbiter/l2_arbiter.sv:118: Compile generate block "work@taiga_wrapper.genblk1.l2_arb.genblk2[1]".
[INF:CP0335] third_party/cores/taiga/l2_arbiter/l2_fifo.sv:37: Compile generate block "work@taiga_wrapper.genblk1.l2_arb.genblk2[1].input_data_fifo.genblk1".
[INF:CP0335] third_party/cores/taiga/l2_arbiter/l2_fifo.sv:54: Compile generate block "work@taiga_wrapper.genblk1.l2_arb.genblk2[1].input_data_fifo.genblk1.genblk1".
[INF:CP0335] third_party/cores/taiga/l2_arbiter/l2_round_robin.sv:42: Compile generate block "work@taiga_wrapper.genblk1.l2_arb.rr.genblk1".
[INF:CP0335] third_party/cores/taiga/l2_arbiter/l2_fifo.sv:37: Compile generate block "work@taiga_wrapper.genblk1.l2_arb.input_fifo.genblk1".
[INF:CP0335] third_party/cores/taiga/l2_arbiter/l2_fifo.sv:54: Compile generate block "work@taiga_wrapper.genblk1.l2_arb.input_fifo.genblk1.genblk1".
[INF:CP0335] third_party/cores/taiga/l2_arbiter/l2_arbiter.sv:202: Compile generate block "work@taiga_wrapper.genblk1.l2_arb.genblk3[0]".
[INF:CP0335] third_party/cores/taiga/l2_arbiter/l2_arbiter.sv:202: Compile generate block "work@taiga_wrapper.genblk1.l2_arb.genblk3[1]".
[INF:CP0335] third_party/cores/taiga/l2_arbiter/l2_arbiter.sv:218: Compile generate block "work@taiga_wrapper.genblk1.l2_arb.genblk4[0]".
[INF:CP0335] third_party/cores/taiga/l2_arbiter/l2_fifo.sv:37: Compile generate block "work@taiga_wrapper.genblk1.l2_arb.genblk4[0].inv_response_fifo.genblk1".
[INF:CP0335] third_party/cores/taiga/l2_arbiter/l2_fifo.sv:54: Compile generate block "work@taiga_wrapper.genblk1.l2_arb.genblk4[0].inv_response_fifo.genblk1.genblk1".
[INF:CP0335] third_party/cores/taiga/l2_arbiter/l2_arbiter.sv:218: Compile generate block "work@taiga_wrapper.genblk1.l2_arb.genblk4[1]".
[INF:CP0335] third_party/cores/taiga/l2_arbiter/l2_fifo.sv:37: Compile generate block "work@taiga_wrapper.genblk1.l2_arb.genblk4[1].inv_response_fifo.genblk1".
[INF:CP0335] third_party/cores/taiga/l2_arbiter/l2_fifo.sv:54: Compile generate block "work@taiga_wrapper.genblk1.l2_arb.genblk4[1].inv_response_fifo.genblk1.genblk1".
[INF:CP0335] third_party/cores/taiga/l2_arbiter/l2_fifo.sv:37: Compile generate block "work@taiga_wrapper.genblk1.l2_arb.data_attributes_fifo.genblk1".
[INF:CP0335] third_party/cores/taiga/l2_arbiter/l2_fifo.sv:54: Compile generate block "work@taiga_wrapper.genblk1.l2_arb.data_attributes_fifo.genblk1.genblk1".
[INF:CP0335] third_party/cores/taiga/l2_arbiter/l2_fifo.sv:37: Compile generate block "work@taiga_wrapper.genblk1.l2_arb.mem_data.genblk1".
[INF:CP0335] third_party/cores/taiga/l2_arbiter/l2_fifo.sv:54: Compile generate block "work@taiga_wrapper.genblk1.l2_arb.mem_data.genblk1.genblk1".
[INF:CP0335] third_party/cores/taiga/l2_arbiter/l2_fifo.sv:37: Compile generate block "work@taiga_wrapper.genblk1.l2_arb.mem_returndata.genblk1".
[INF:CP0335] third_party/cores/taiga/l2_arbiter/l2_fifo.sv:54: Compile generate block "work@taiga_wrapper.genblk1.l2_arb.mem_returndata.genblk1.genblk1".
[INF:CP0335] third_party/cores/taiga/l2_arbiter/l2_arbiter.sv:283: Compile generate block "work@taiga_wrapper.genblk1.l2_arb.genblk5[0]".
[INF:CP0335] third_party/cores/taiga/l2_arbiter/l2_fifo.sv:37: Compile generate block "work@taiga_wrapper.genblk1.l2_arb.genblk5[0].returndata_fifo.genblk1".
[INF:CP0335] third_party/cores/taiga/l2_arbiter/l2_fifo.sv:39: Compile generate block "work@taiga_wrapper.genblk1.l2_arb.genblk5[0].returndata_fifo.genblk1.genblk1".
[INF:CP0335] third_party/cores/taiga/l2_arbiter/l2_arbiter.sv:283: Compile generate block "work@taiga_wrapper.genblk1.l2_arb.genblk5[1]".
[INF:CP0335] third_party/cores/taiga/l2_arbiter/l2_fifo.sv:37: Compile generate block "work@taiga_wrapper.genblk1.l2_arb.genblk5[1].returndata_fifo.genblk1".
[INF:CP0335] third_party/cores/taiga/l2_arbiter/l2_fifo.sv:39: Compile generate block "work@taiga_wrapper.genblk1.l2_arb.genblk5[1].returndata_fifo.genblk1.genblk1".
[INF:CP0335] third_party/cores/taiga/core/byte_en_BRAM.sv:47: Compile generate block "work@taiga_wrapper.inst_data_ram.genblk1".
[NTE:EL0503] third_party/cores/taiga/core/div_unit_core_wrapper.sv:4: Top level module "work@div_unit_core_wrapper".
[NTE:EL0503] third_party/cores/taiga/core/placer_randomizer.sv:1: Top level module "work@placer_randomizer".
[NTE:EL0503] third_party/cores/taiga/core/msb.sv:23: Top level module "work@msb".
[NTE:EL0503] third_party/cores/taiga/core/one_hot_occupancy.sv:26: Top level module "work@one_hot_occupancy".
[NTE:EL0503] third_party/cores/taiga/core/binary_occupancy.sv:26: Top level module "work@binary_occupancy".
[NTE:EL0503] third_party/cores/taiga/core/mstatus_priv_reg.sv:27: Top level module "work@mstatus_priv_reg".
[NTE:EL0503] third_party/cores/taiga/local_memory/local_mem.sv:24: Top level module "work@local_mem".
[NTE:EL0503] third_party/cores/taiga/examples/zedboard/taiga_wrapper.sv:27: Top level module "work@taiga_wrapper".
[NTE:EL0504] Multiple top level modules in design.
[WRN:EL0500] third_party/cores/taiga/core/byte_en_BRAM.sv:50: Cannot find a module definition for "work@local_mem.inst_data_ram.genblk1::intel_byte_enable_ram".
[WRN:EL0500] third_party/cores/taiga/core/byte_en_BRAM.sv:50: Cannot find a module definition for "work@taiga_wrapper.cpu.fetch_block.genblk3.i_cache.idata_bank_gen[0].idata_bank.genblk1::intel_byte_enable_ram".
[WRN:EL0500] third_party/cores/taiga/core/byte_en_BRAM.sv:50: Cannot find a module definition for "work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.data_bank.ram_block.genblk1::intel_byte_enable_ram".
[WRN:EL0500] third_party/cores/taiga/core/byte_en_BRAM.sv:50: Cannot find a module definition for "work@taiga_wrapper.inst_data_ram.genblk1::intel_byte_enable_ram".
[NTE:EL0508] Nb Top level modules: 8.
[NTE:EL0509] Max instance depth: 9.
[NTE:EL0510] Nb instances: 142.
[NTE:EL0511] Nb leaf instances: 4.
[WRN:EL0512] Nb undefined modules: 4.
[WRN:EL0513] Nb undefined instances: 4.
[ FATAL] : 0
[ SYNTAX] : 0
[ ERROR] : 4
[WARNING] : 105
[ NOTE] : 32
+ cat /tmpfs/tmp/tmp1qgo7jwo/yosys-script
read_uhdm slpp_all/surelog.uhdm
hierarchy -check -top \work_l1_arbiter
proc
check
memory_dff
memory_collect
stat
check
write_json
write_verilog
+ yosys-uhdm -s /tmpfs/tmp/tmp1qgo7jwo/yosys-script
/----------------------------------------------------------------------------\
| |
| yosys -- Yosys Open SYnthesis Suite |
| |
| Copyright (C) 2012 - 2020 Claire Wolf <claire@symbioticeda.com> |
| |
| Permission to use, copy, modify, and/or distribute this software for any |
| purpose with or without fee is hereby granted, provided that the above |
| copyright notice and this permission notice appear in all copies. |
| |
| THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES |
| WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF |
| MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR |
| ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES |
| WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN |
| ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF |
| OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. |
| |
\----------------------------------------------------------------------------/
Yosys 0.9+2406 (git sha1 897adb4e, clang 7.0.0 -fvisibility-inlines-hidden -fmessage-length=0 -march=nocona -mtune=haswell -ftree-vectorize -fPIC -fstack-protector-strong -fno-plt -O2 -ffunction-sections -fdebug-prefix-map=/tmp/really-really-really-really-really-really-really-really-really-really-really-really-really-long-path/conda/conda-bld/uhdm-integration_1595257298458/work=/usr/local/src/conda/uhdm-integration-0.0_0099_g33391fc -fdebug-prefix-map=/home/kbuilder/miniconda/envs/sv-test-env=/usr/local/src/conda-prefix -fPIC -Os)
-- Executing script file `/tmpfs/tmp/tmp1qgo7jwo/yosys-script' --
1. Executing UHDM frontend.
design: (work@div_unit_core_wrapper)
|vpiName:work@div_unit_core_wrapper
|uhdmallPackages:
\_package: builtin, parent:work@div_unit_core_wrapper
|vpiDefName:builtin
|vpiFullName:builtin
|uhdmallPackages:
\_package: csr_types, file:third_party/cores/taiga/core/csr_types.sv, line:23, parent:work@div_unit_core_wrapper
|vpiDefName:csr_types
|vpiFullName:csr_types
|vpiTypedef:
\_struct_typespec: (csr_addr_t), line:37
|vpiPacked:1
|vpiName:csr_addr_t
|vpiTypespecMember:
\_typespec_member: (rw_bits), line:38
|vpiName:rw_bits
|vpiTypespec:
\_logic_typespec: , line:38
|vpiRange:
\_range: , line:38, parent:csr_addr_t
|vpiLeftRange:
\_constant: , line:38
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:38
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiTypespecMember:
\_typespec_member: (privilege), line:39
|vpiName:privilege
|vpiTypespec:
\_logic_typespec: , line:39
|vpiRange:
\_range: , line:39, parent:csr_addr_t
|vpiLeftRange:
\_constant: , line:39
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:39
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiTypespecMember:
\_typespec_member: (subtype), line:40
|vpiName:subtype
|vpiTypespec:
\_logic_typespec: , line:40
|vpiRange:
\_range: , line:40, parent:csr_addr_t
|vpiLeftRange:
\_constant: , line:40
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:40
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiTypespecMember:
\_typespec_member: (sub_addr), line:41
|vpiName:sub_addr
|vpiTypespec:
\_logic_typespec: , line:41
|vpiRange:
\_range: , line:41, parent:csr_addr_t
|vpiLeftRange:
\_constant: , line:41
|vpiConstType:7
|vpiDecompile:5
|vpiSize:32
|INT:5
|vpiRightRange:
\_constant: , line:41
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiTypedef:
\_struct_typespec: (mcause_t), line:135
|vpiPacked:1
|vpiName:mcause_t
|vpiTypespecMember:
\_typespec_member: (interrupt), line:136
|vpiName:interrupt
|vpiTypespec:
\_logic_typespec: , line:136
|vpiTypespecMember:
\_typespec_member: (zeroes), line:137
|vpiName:zeroes
|vpiTypespec:
\_logic_typespec: , line:137
|vpiRange:
\_range: , line:137, parent:mcause_t
|vpiLeftRange:
\_operation: , line:137
|vpiOpType:11
|vpiOperand:
\_operation: , line:137, parent:mcause_t
|vpiOpType:11
|vpiOperand:
\_operation: , line:137, parent:mcause_t
|vpiOpType:11
|vpiOperand:
\_ref_obj: (XLEN), line:137, parent:mcause_t
|vpiName:XLEN
|vpiFullName:mcause_t.XLEN
|vpiOperand:
\_constant: , line:137
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiOperand:
\_constant: , line:137
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiOperand:
\_ref_obj: (ECODE_W), line:137
|vpiName:ECODE_W
|vpiFullName:mcause_t.ECODE_W
|vpiRightRange:
\_constant: , line:137
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiTypespecMember:
\_typespec_member: (code), line:138
|vpiName:code
|vpiTypespec:
\_logic_typespec: , line:138
|vpiRange:
\_range: , line:138, parent:mcause_t
|vpiLeftRange:
\_operation: , line:138
|vpiOpType:11
|vpiOperand:
\_ref_obj: (ECODE_W), line:138, parent:mcause_t
|vpiName:ECODE_W
|vpiFullName:mcause_t.ECODE_W
|vpiOperand:
\_constant: , line:138
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:138
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiTypedef:
\_struct_typespec: (mie_t), line:119
|vpiPacked:1
|vpiName:mie_t
|vpiTypespecMember:
\_typespec_member: (zeros), line:120
|vpiName:zeros
|vpiTypespec:
\_logic_typespec: , line:120
|vpiRange:
\_range: , line:120, parent:mie_t
|vpiLeftRange:
\_constant: , line:120
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:120
|vpiConstType:7
|vpiDecompile:12
|vpiSize:32
|INT:12
|vpiTypespecMember:
\_typespec_member: (meie), line:121
|vpiName:meie
|vpiTypespec:
\_logic_typespec: , line:121
|vpiTypespecMember:
\_typespec_member: (zero1), line:122
|vpiName:zero1
|vpiTypespec:
\_logic_typespec: , line:122
|vpiTypespecMember:
\_typespec_member: (seie), line:123
|vpiName:seie
|vpiTypespec:
\_logic_typespec: , line:123
|vpiTypespecMember:
\_typespec_member: (ueie), line:124
|vpiName:ueie
|vpiTypespec:
\_logic_typespec: , line:124
|vpiTypespecMember:
\_typespec_member: (mtie), line:125
|vpiName:mtie
|vpiTypespec:
\_logic_typespec: , line:125
|vpiTypespecMember:
\_typespec_member: (zero2), line:126
|vpiName:zero2
|vpiTypespec:
\_logic_typespec: , line:126
|vpiTypespecMember:
\_typespec_member: (stie), line:127
|vpiName:stie
|vpiTypespec:
\_logic_typespec: , line:127
|vpiTypespecMember:
\_typespec_member: (utie), line:128
|vpiName:utie
|vpiTypespec:
\_logic_typespec: , line:128
|vpiTypespecMember:
\_typespec_member: (msie), line:129
|vpiName:msie
|vpiTypespec:
\_logic_typespec: , line:129
|vpiTypespecMember:
\_typespec_member: (zero3), line:130
|vpiName:zero3
|vpiTypespec:
\_logic_typespec: , line:130
|vpiTypespecMember:
\_typespec_member: (ssie), line:131
|vpiName:ssie
|vpiTypespec:
\_logic_typespec: , line:131
|vpiTypespecMember:
\_typespec_member: (usie), line:132
|vpiName:usie
|vpiTypespec:
\_logic_typespec: , line:132
|vpiTypedef:
\_struct_typespec: (mip_t), line:103
|vpiPacked:1
|vpiName:mip_t
|vpiTypespecMember:
\_typespec_member: (zeros), line:104
|vpiName:zeros
|vpiTypespec:
\_logic_typespec: , line:104
|vpiRange:
\_range: , line:104, parent:mip_t
|vpiLeftRange:
\_constant: , line:104
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:104
|vpiConstType:7
|vpiDecompile:12
|vpiSize:32
|INT:12
|vpiTypespecMember:
\_typespec_member: (meip), line:105
|vpiName:meip
|vpiTypespec:
\_logic_typespec: , line:105
|vpiTypespecMember:
\_typespec_member: (zero1), line:106
|vpiName:zero1
|vpiTypespec:
\_logic_typespec: , line:106
|vpiTypespecMember:
\_typespec_member: (seip), line:107
|vpiName:seip
|vpiTypespec:
\_logic_typespec: , line:107
|vpiTypespecMember:
\_typespec_member: (ueip), line:108
|vpiName:ueip
|vpiTypespec:
\_logic_typespec: , line:108
|vpiTypespecMember:
\_typespec_member: (mtip), line:109
|vpiName:mtip
|vpiTypespec:
\_logic_typespec: , line:109
|vpiTypespecMember:
\_typespec_member: (zero2), line:110
|vpiName:zero2
|vpiTypespec:
\_logic_typespec: , line:110
|vpiTypespecMember:
\_typespec_member: (stip), line:111
|vpiName:stip
|vpiTypespec:
\_logic_typespec: , line:111
|vpiTypespecMember:
\_typespec_member: (utip), line:112
|vpiName:utip
|vpiTypespec:
\_logic_typespec: , line:112
|vpiTypespecMember:
\_typespec_member: (msip), line:113
|vpiName:msip
|vpiTypespec:
\_logic_typespec: , line:113
|vpiTypespecMember:
\_typespec_member: (zero3), line:114
|vpiName:zero3
|vpiTypespec:
\_logic_typespec: , line:114
|vpiTypespecMember:
\_typespec_member: (ssip), line:115
|vpiName:ssip
|vpiTypespec:
\_logic_typespec: , line:115
|vpiTypespecMember:
\_typespec_member: (usip), line:116
|vpiName:usip
|vpiTypespec:
\_logic_typespec: , line:116
|vpiTypedef:
\_struct_typespec: (misa_t), line:45
|vpiPacked:1
|vpiName:misa_t
|vpiTypespecMember:
\_typespec_member: (base), line:46
|vpiName:base
|vpiTypespec:
\_logic_typespec: , line:46
|vpiRange:
\_range: , line:46, parent:misa_t
|vpiLeftRange:
\_constant: , line:46
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:46
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiTypespecMember:
\_typespec_member: (reserved), line:47
|vpiName:reserved
|vpiTypespec:
\_logic_typespec: , line:47
|vpiRange:
\_range: , line:47, parent:misa_t
|vpiLeftRange:
\_constant: , line:47
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiRightRange:
\_constant: , line:47
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiTypespecMember:
\_typespec_member: (Z), line:48
|vpiName:Z
|vpiTypespec:
\_logic_typespec: , line:48
|vpiTypespecMember:
\_typespec_member: (Y), line:49
|vpiName:Y
|vpiTypespec:
\_logic_typespec: , line:49
|vpiTypespecMember:
\_typespec_member: (X), line:50
|vpiName:X
|vpiTypespec:
\_logic_typespec: , line:50
|vpiTypespecMember:
\_typespec_member: (W), line:51
|vpiName:W
|vpiTypespec:
\_logic_typespec: , line:51
|vpiTypespecMember:
\_typespec_member: (V), line:52
|vpiName:V
|vpiTypespec:
\_logic_typespec: , line:52
|vpiTypespecMember:
\_typespec_member: (U), line:53
|vpiName:U
|vpiTypespec:
\_logic_typespec: , line:53
|vpiTypespecMember:
\_typespec_member: (T), line:54
|vpiName:T
|vpiTypespec:
\_logic_typespec: , line:54
|vpiTypespecMember:
\_typespec_member: (S), line:55
|vpiName:S
|vpiTypespec:
\_logic_typespec: , line:55
|vpiTypespecMember:
\_typespec_member: (R), line:56
|vpiName:R
|vpiTypespec:
\_logic_typespec: , line:56
|vpiTypespecMember:
\_typespec_member: (Q), line:57
|vpiName:Q
|vpiTypespec:
\_logic_typespec: , line:57
|vpiTypespecMember:
\_typespec_member: (P), line:58
|vpiName:P
|vpiTypespec:
\_logic_typespec: , line:58
|vpiTypespecMember:
\_typespec_member: (O), line:59
|vpiName:O
|vpiTypespec:
\_logic_typespec: , line:59
|vpiTypespecMember:
\_typespec_member: (N), line:60
|vpiName:N
|vpiTypespec:
\_logic_typespec: , line:60
|vpiTypespecMember:
\_typespec_member: (M), line:61
|vpiName:M
|vpiTypespec:
\_logic_typespec: , line:61
|vpiTypespecMember:
\_typespec_member: (L), line:62
|vpiName:L
|vpiTypespec:
\_logic_typespec: , line:62
|vpiTypespecMember:
\_typespec_member: (K), line:63
|vpiName:K
|vpiTypespec:
\_logic_typespec: , line:63
|vpiTypespecMember:
\_typespec_member: (J), line:64
|vpiName:J
|vpiTypespec:
\_logic_typespec: , line:64
|vpiTypespecMember:
\_typespec_member: (I), line:65
|vpiName:I
|vpiTypespec:
\_logic_typespec: , line:65
|vpiTypespecMember:
\_typespec_member: (H), line:66
|vpiName:H
|vpiTypespec:
\_logic_typespec: , line:66
|vpiTypespecMember:
\_typespec_member: (G), line:67
|vpiName:G
|vpiTypespec:
\_logic_typespec: , line:67
|vpiTypespecMember:
\_typespec_member: (F), line:68
|vpiName:F
|vpiTypespec:
\_logic_typespec: , line:68
|vpiTypespecMember:
\_typespec_member: (E), line:69
|vpiName:E
|vpiTypespec:
\_logic_typespec: , line:69
|vpiTypespecMember:
\_typespec_member: (D), line:70
|vpiName:D
|vpiTypespec:
\_logic_typespec: , line:70
|vpiTypespecMember:
\_typespec_member: (C), line:71
|vpiName:C
|vpiTypespec:
\_logic_typespec: , line:71
|vpiTypespecMember:
\_typespec_member: (B), line:72
|vpiName:B
|vpiTypespec:
\_logic_typespec: , line:72
|vpiTypespecMember:
\_typespec_member: (A), line:73
|vpiName:A
|vpiTypespec:
\_logic_typespec: , line:73
|vpiTypedef:
\_struct_typespec: (mstatus_t), line:78
|vpiPacked:1
|vpiName:mstatus_t
|vpiTypespecMember:
\_typespec_member: (sd), line:79
|vpiName:sd
|vpiTypespec:
\_logic_typespec: , line:79
|vpiTypespecMember:
\_typespec_member: (zeros), line:80
|vpiName:zeros
|vpiTypespec:
\_logic_typespec: , line:80
|vpiRange:
\_range: , line:80, parent:mstatus_t
|vpiLeftRange:
\_constant: , line:80
|vpiConstType:7
|vpiDecompile:7
|vpiSize:32
|INT:7
|vpiRightRange:
\_constant: , line:80
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiTypespecMember:
\_typespec_member: (tsr), line:81
|vpiName:tsr
|vpiTypespec:
\_logic_typespec: , line:81
|vpiTypespecMember:
\_typespec_member: (tw), line:82
|vpiName:tw
|vpiTypespec:
\_logic_typespec: , line:82
|vpiTypespecMember:
\_typespec_member: (tvm), line:83
|vpiName:tvm
|vpiTypespec:
\_logic_typespec: , line:83
|vpiTypespecMember:
\_typespec_member: (mxr), line:84
|vpiName:mxr
|vpiTypespec:
\_logic_typespec: , line:84
|vpiTypespecMember:
\_typespec_member: (sum), line:85
|vpiName:sum
|vpiTypespec:
\_logic_typespec: , line:85
|vpiTypespecMember:
\_typespec_member: (mprv), line:86
|vpiName:mprv
|vpiTypespec:
\_logic_typespec: , line:86
|vpiTypespecMember:
\_typespec_member: (xs), line:87
|vpiName:xs
|vpiTypespec:
\_logic_typespec: , line:87
|vpiRange:
\_range: , line:87, parent:mstatus_t
|vpiLeftRange:
\_constant: , line:87
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:87
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiTypespecMember:
\_typespec_member: (fs), line:88
|vpiName:fs
|vpiTypespec:
\_logic_typespec: , line:88
|vpiRange:
\_range: , line:88, parent:mstatus_t
|vpiLeftRange:
\_constant: , line:88
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:88
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiTypespecMember:
\_typespec_member: (mpp), line:89
|vpiName:mpp
|vpiTypespec:
\_logic_typespec: , line:89
|vpiRange:
\_range: , line:89, parent:mstatus_t
|vpiLeftRange:
\_constant: , line:89
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:89
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiTypespecMember:
\_typespec_member: (zeros1), line:90
|vpiName:zeros1
|vpiTypespec:
\_logic_typespec: , line:90
|vpiRange:
\_range: , line:90, parent:mstatus_t
|vpiLeftRange:
\_constant: , line:90
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:90
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiTypespecMember:
\_typespec_member: (spp), line:91
|vpiName:spp
|vpiTypespec:
\_logic_typespec: , line:91
|vpiTypespecMember:
\_typespec_member: (mpie), line:92
|vpiName:mpie
|vpiTypespec:
\_logic_typespec: , line:92
|vpiTypespecMember:
\_typespec_member: (zero2), line:93
|vpiName:zero2
|vpiTypespec:
\_logic_typespec: , line:93
|vpiTypespecMember:
\_typespec_member: (spie), line:94
|vpiName:spie
|vpiTypespec:
\_logic_typespec: , line:94
|vpiTypespecMember:
\_typespec_member: (upie), line:95
|vpiName:upie
|vpiTypespec:
\_logic_typespec: , line:95
|vpiTypespecMember:
\_typespec_member: (mie), line:96
|vpiName:mie
|vpiTypespec:
\_logic_typespec: , line:96
|vpiTypespecMember:
\_typespec_member: (zero3), line:97
|vpiName:zero3
|vpiTypespec:
\_logic_typespec: , line:97
|vpiTypespecMember:
\_typespec_member: (sie), line:98
|vpiName:sie
|vpiTypespec:
\_logic_typespec: , line:98
|vpiTypespecMember:
\_typespec_member: (uie), line:99
|vpiName:uie
|vpiTypespec:
\_logic_typespec: , line:99
|vpiTypedef:
\_enum_typespec: (privilege_t), line:34
|vpiName:privilege_t
|vpiBaseTypespec:
\_bit_typespec: , line:29
|vpiRange:
\_range: , line:29
|vpiLeftRange:
\_constant: , line:29
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:29
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiEnumConst:
\_enum_const: (MACHINE_PRIVILEGE), line:33
|vpiName:MACHINE_PRIVILEGE
|INT:3
|vpiEnumConst:
\_enum_const: (SUPERVISOR_PRIVILEGE), line:31
|vpiName:SUPERVISOR_PRIVILEGE
|INT:1
|vpiEnumConst:
\_enum_const: (USER_PRIVILEGE), line:30
|vpiName:USER_PRIVILEGE
|INT:0
|vpiTypedef:
\_struct_typespec: (satp_t), line:142
|vpiPacked:1
|vpiName:satp_t
|vpiTypespecMember:
\_typespec_member: (mode), line:143
|vpiName:mode
|vpiTypespec:
\_logic_typespec: , line:143
|vpiTypespecMember:
\_typespec_member: (asid), line:144
|vpiName:asid
|vpiTypespec:
\_logic_typespec: , line:144
|vpiRange:
\_range: , line:144, parent:satp_t
|vpiLeftRange:
\_operation: , line:144
|vpiOpType:11
|vpiOperand:
\_ref_obj: (ASIDLEN), line:144, parent:satp_t
|vpiName:ASIDLEN
|vpiFullName:satp_t.ASIDLEN
|vpiOperand:
\_constant: , line:144
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:144
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiTypespecMember:
\_typespec_member: (ppn), line:145
|vpiName:ppn
|vpiTypespec:
\_logic_typespec: , line:145
|vpiRange:
\_range: , line:145, parent:satp_t
|vpiLeftRange:
\_constant: , line:145
|vpiConstType:7
|vpiDecompile:21
|vpiSize:32
|INT:21
|vpiRightRange:
\_constant: , line:145
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|uhdmallPackages:
\_package: l2_config_and_types, file:third_party/cores/taiga/l2_arbiter/l2_config_and_types.sv, line:24, parent:work@div_unit_core_wrapper
|vpiDefName:l2_config_and_types
|vpiFullName:l2_config_and_types
|vpiTypedef:
\_struct_typespec: (l2_data_attributes_t), line:68
|vpiPacked:1
|vpiName:l2_data_attributes_t
|vpiTypespecMember:
\_typespec_member: (id), line:69
|vpiName:id
|vpiTypespec:
\_logic_typespec: , line:69
|vpiRange:
\_range: , line:69, parent:l2_data_attributes_t
|vpiLeftRange:
\_constant: , line:69
|vpiDecompile:0
|INT:0
|vpiRightRange:
\_constant: , line:69
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiTypespecMember:
\_typespec_member: (burst_size), line:70
|vpiName:burst_size
|vpiTypespec:
\_logic_typespec: , line:70
|vpiRange:
\_range: , line:70, parent:l2_data_attributes_t
|vpiLeftRange:
\_constant: , line:70
|vpiConstType:7
|vpiDecompile:4
|vpiSize:32
|INT:4
|vpiRightRange:
\_constant: , line:70
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiTypespecMember:
\_typespec_member: (abort), line:71
|vpiName:abort
|vpiTypespec:
\_logic_typespec: , line:71
|vpiTypedef:
\_struct_typespec: (l2_mem_request_t), line:58
|vpiPacked:1
|vpiName:l2_mem_request_t
|vpiTypespecMember:
\_typespec_member: (addr), line:59
|vpiName:addr
|vpiTypespec:
\_logic_typespec: , line:59
|vpiRange:
\_range: , line:59, parent:l2_mem_request_t
|vpiLeftRange:
\_constant: , line:59
|vpiConstType:7
|vpiDecompile:29
|vpiSize:32
|INT:29
|vpiRightRange:
\_constant: , line:59
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiTypespecMember:
\_typespec_member: (be), line:60
|vpiName:be
|vpiTypespec:
\_logic_typespec: , line:60
|vpiRange:
\_range: , line:60, parent:l2_mem_request_t
|vpiLeftRange:
\_constant: , line:60
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiRightRange:
\_constant: , line:60
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiTypespecMember:
\_typespec_member: (rnw), line:61
|vpiName:rnw
|vpiTypespec:
\_logic_typespec: , line:61
|vpiTypespecMember:
\_typespec_member: (is_amo), line:62
|vpiName:is_amo
|vpiTypespec:
\_logic_typespec: , line:62
|vpiTypespecMember:
\_typespec_member: (amo_type_or_burst_size), line:63
|vpiName:amo_type_or_burst_size
|vpiTypespec:
\_logic_typespec: , line:63
|vpiRange:
\_range: , line:63, parent:l2_mem_request_t
|vpiLeftRange:
\_constant: , line:63
|vpiConstType:7
|vpiDecompile:4
|vpiSize:32
|INT:4
|vpiRightRange:
\_constant: , line:63
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiTypespecMember:
\_typespec_member: (id), line:64
|vpiName:id
|vpiTypespec:
\_logic_typespec: , line:64
|vpiRange:
\_range: , line:64, parent:l2_mem_request_t
|vpiLeftRange:
\_constant: , line:64
|vpiDecompile:2
|INT:2
|vpiRightRange:
\_constant: , line:64
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiTypedef:
\_struct_typespec: (l2_mem_return_data_t), line:75
|vpiPacked:1
|vpiName:l2_mem_return_data_t
|vpiTypespecMember:
\_typespec_member: (id), line:76
|vpiName:id
|vpiTypespec:
\_logic_typespec: , line:76
|vpiRange:
\_range: , line:76, parent:l2_mem_return_data_t
|vpiLeftRange:
\_constant: , line:76
|vpiDecompile:0
|INT:0
|vpiRightRange:
\_constant: , line:76
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiTypespecMember:
\_typespec_member: (sub_id), line:77
|vpiName:sub_id
|vpiTypespec:
\_logic_typespec: , line:77
|vpiRange:
\_range: , line:77, parent:l2_mem_return_data_t
|vpiLeftRange:
\_constant: , line:77
|vpiDecompile:1
|INT:1
|vpiRightRange:
\_constant: , line:77
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiTypespecMember:
\_typespec_member: (data), line:78
|vpiName:data
|vpiTypespec:
\_logic_typespec: , line:78
|vpiRange:
\_range: , line:78, parent:l2_mem_return_data_t
|vpiLeftRange:
\_constant: , line:78
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:78
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiTypedef:
\_struct_typespec: (l2_request_t), line:49
|vpiPacked:1
|vpiName:l2_request_t
|vpiTypespecMember:
\_typespec_member: (addr), line:50
|vpiName:addr
|vpiTypespec:
\_logic_typespec: , line:50
|vpiRange:
\_range: , line:50, parent:l2_request_t
|vpiLeftRange:
\_constant: , line:50
|vpiConstType:7
|vpiDecompile:29
|vpiSize:32
|INT:29
|vpiRightRange:
\_constant: , line:50
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiTypespecMember:
\_typespec_member: (be), line:51
|vpiName:be
|vpiTypespec:
\_logic_typespec: , line:51
|vpiRange:
\_range: , line:51, parent:l2_request_t
|vpiLeftRange:
\_constant: , line:51
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiRightRange:
\_constant: , line:51
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiTypespecMember:
\_typespec_member: (rnw), line:52
|vpiName:rnw
|vpiTypespec:
\_logic_typespec: , line:52
|vpiTypespecMember:
\_typespec_member: (is_amo), line:53
|vpiName:is_amo
|vpiTypespec:
\_logic_typespec: , line:53
|vpiTypespecMember:
\_typespec_member: (amo_type_or_burst_size), line:54
|vpiName:amo_type_or_burst_size
|vpiTypespec:
\_logic_typespec: , line:54
|vpiRange:
\_range: , line:54, parent:l2_request_t
|vpiLeftRange:
\_constant: , line:54
|vpiConstType:7
|vpiDecompile:4
|vpiSize:32
|INT:4
|vpiRightRange:
\_constant: , line:54
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiTypespecMember:
\_typespec_member: (sub_id), line:55
|vpiName:sub_id
|vpiTypespec:
\_logic_typespec: , line:55
|vpiRange:
\_range: , line:55, parent:l2_request_t
|vpiLeftRange:
\_constant: , line:55
|vpiDecompile:1
|INT:1
|vpiRightRange:
\_constant: , line:55
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiTypedef:
\_struct_typespec: (l2_return_data_t), line:81
|vpiPacked:1
|vpiName:l2_return_data_t
|vpiTypespecMember:
\_typespec_member: (sub_id), line:82
|vpiName:sub_id
|vpiTypespec:
\_logic_typespec: , line:82
|vpiRange:
\_range: , line:82, parent:l2_return_data_t
|vpiLeftRange:
\_constant: , line:82
|vpiDecompile:1
|INT:1
|vpiRightRange:
\_constant: , line:82
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiTypespecMember:
\_typespec_member: (data), line:83
|vpiName:data
|vpiTypespec:
\_logic_typespec: , line:83
|vpiRange:
\_range: , line:83, parent:l2_return_data_t
|vpiLeftRange:
\_constant: , line:83
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:83
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiParamAssign:
\_param_assign: , line:26
|vpiRhs:
\_constant: , line:26
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiLhs:
\_parameter: (L2_NUM_PORTS), line:26
|vpiName:L2_NUM_PORTS
|vpiFullName:l2_config_and_types::L2_NUM_PORTS
|vpiParamAssign:
\_param_assign: , line:27
|vpiRhs:
\_constant: , line:27
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiLhs:
\_parameter: (L2_SUB_ID_W), line:27
|vpiName:L2_SUB_ID_W
|vpiFullName:l2_config_and_types::L2_SUB_ID_W
|vpiParamAssign:
\_param_assign: , line:34
|vpiRhs:
\_constant: , line:34
|vpiConstType:7
|vpiDecompile:4
|vpiSize:32
|INT:4
|vpiLhs:
\_parameter: (L2_INPUT_FIFO_DEPTHS), line:34
|vpiName:L2_INPUT_FIFO_DEPTHS
|vpiFullName:l2_config_and_types::L2_INPUT_FIFO_DEPTHS
|vpiParamAssign:
\_param_assign: , line:35
|vpiRhs:
\_constant: , line:35
|vpiConstType:7
|vpiDecompile:4
|vpiSize:32
|INT:4
|vpiLhs:
\_parameter: (L2_INVALIDATION_FIFO_DEPTHS), line:35
|vpiName:L2_INVALIDATION_FIFO_DEPTHS
|vpiFullName:l2_config_and_types::L2_INVALIDATION_FIFO_DEPTHS
|vpiParamAssign:
\_param_assign: , line:36
|vpiRhs:
\_constant: , line:36
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiLhs:
\_parameter: (L2_READ_RETURN_FIFO_DEPTHS), line:36
|vpiName:L2_READ_RETURN_FIFO_DEPTHS
|vpiFullName:l2_config_and_types::L2_READ_RETURN_FIFO_DEPTHS
|vpiParamAssign:
\_param_assign: , line:39
|vpiRhs:
\_constant: , line:39
|vpiConstType:7
|vpiDecompile:8
|vpiSize:32
|INT:8
|vpiLhs:
\_parameter: (L2_MEM_ADDR_FIFO_DEPTH), line:39
|vpiName:L2_MEM_ADDR_FIFO_DEPTH
|vpiFullName:l2_config_and_types::L2_MEM_ADDR_FIFO_DEPTH
|vpiParamAssign:
\_param_assign: , line:41
|vpiRhs:
\_constant: , line:41
|vpiConstType:7
|vpiDecompile:16
|vpiSize:32
|INT:16
|vpiLhs:
\_parameter: (L2_DATA_ATTRIBUTES_FIFO_DEPTH), line:41
|vpiName:L2_DATA_ATTRIBUTES_FIFO_DEPTH
|vpiFullName:l2_config_and_types::L2_DATA_ATTRIBUTES_FIFO_DEPTH
|vpiParamAssign:
\_param_assign: , line:46
|vpiRhs:
\_constant: , line:46
|vpiDecompile:3
|INT:3
|vpiLhs:
\_parameter: (L2_ID_W), line:46
|vpiName:L2_ID_W
|vpiFullName:l2_config_and_types::L2_ID_W
|vpiParameter:
\_parameter: (L2_NUM_PORTS), line:26
|vpiParameter:
\_parameter: (L2_SUB_ID_W), line:27
|vpiParameter:
\_parameter: (L2_INPUT_FIFO_DEPTHS), line:34
|vpiParameter:
\_parameter: (L2_INVALIDATION_FIFO_DEPTHS), line:35
|vpiParameter:
\_parameter: (L2_READ_RETURN_FIFO_DEPTHS), line:36
|vpiParameter:
\_parameter: (L2_MEM_ADDR_FIFO_DEPTH), line:39
|vpiParameter:
\_parameter: (L2_DATA_ATTRIBUTES_FIFO_DEPTH), line:41
|vpiParameter:
\_parameter: (L2_ID_W), line:46
|uhdmallPackages:
\_package: taiga_config, file:third_party/cores/taiga/core/taiga_config.sv, line:23, parent:work@div_unit_core_wrapper
|vpiDefName:taiga_config
|vpiFullName:taiga_config
|vpiTypedef:
\_enum_typespec: (bus_type_t), line:86
|vpiName:bus_type_t
|vpiEnumConst:
\_enum_const: (AVALON_BUS), line:84
|vpiName:AVALON_BUS
|INT:1
|vpiEnumConst:
\_enum_const: (AXI_BUS), line:83
|vpiName:AXI_BUS
|INT:0
|vpiEnumConst:
\_enum_const: (WISHBONE_BUS), line:85
|vpiName:WISHBONE_BUS
|INT:2
|vpiTypedef:
\_enum_typespec: (div_type), line:66
|vpiName:div_type
|vpiEnumConst:
\_enum_const: (QUICK_CLZ), line:63
|vpiName:QUICK_CLZ
|INT:10
|vpiEnumConst:
\_enum_const: (QUICK_CLZ_MK2), line:64
|vpiName:QUICK_CLZ_MK2
|INT:11
|vpiEnumConst:
\_enum_const: (QUICK_NAIVE), line:62
|vpiName:QUICK_NAIVE
|INT:9
|vpiEnumConst:
\_enum_const: (QUICK_RADIX_4), line:65
|vpiName:QUICK_RADIX_4
|INT:12
|vpiEnumConst:
\_enum_const: (RADIX_16), line:61
|vpiName:RADIX_16
|INT:8
|vpiEnumConst:
\_enum_const: (RADIX_2), line:53
|vpiName:RADIX_2
|INT:0
|vpiEnumConst:
\_enum_const: (RADIX_2_EARLY_TERMINATE), line:54
|vpiName:RADIX_2_EARLY_TERMINATE
|INT:1
|vpiEnumConst:
\_enum_const: (RADIX_2_EARLY_TERMINATE_FULL), line:55
|vpiName:RADIX_2_EARLY_TERMINATE_FULL
|INT:2
|vpiEnumConst:
\_enum_const: (RADIX_4), line:56
|vpiName:RADIX_4
|INT:3
|vpiEnumConst:
\_enum_const: (RADIX_4_EARLY_TERMINATE), line:57
|vpiName:RADIX_4_EARLY_TERMINATE
|INT:4
|vpiEnumConst:
\_enum_const: (RADIX_4_EARLY_TERMINATE_FULL), line:58
|vpiName:RADIX_4_EARLY_TERMINATE_FULL
|INT:5
|vpiEnumConst:
\_enum_const: (RADIX_8), line:59
|vpiName:RADIX_8
|INT:6
|vpiEnumConst:
\_enum_const: (RADIX_8_EARLY_TERMINATE), line:60
|vpiName:RADIX_8_EARLY_TERMINATE
|INT:7
|vpiParamAssign:
\_param_assign: , line:27
|vpiRhs:
\_constant: , line:27
|vpiConstType:6
|vpiDecompile:"xilinx"
|vpiSize:8
|STRING:"xilinx"
|vpiLhs:
\_parameter: (FPGA_VENDOR), line:27
|vpiName:FPGA_VENDOR
|vpiFullName:taiga_config::FPGA_VENDOR
|vpiParamAssign:
\_param_assign: , line:34
|vpiRhs:
\_constant: , line:34
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiLhs:
\_parameter: (ENABLE_M_MODE), line:34
|vpiName:ENABLE_M_MODE
|vpiFullName:taiga_config::ENABLE_M_MODE
|vpiParamAssign:
\_param_assign: , line:36
|vpiRhs:
\_constant: , line:36
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiLhs:
\_parameter: (ENABLE_S_MODE), line:36
|vpiName:ENABLE_S_MODE
|vpiFullName:taiga_config::ENABLE_S_MODE
|vpiParamAssign:
\_param_assign: , line:38
|vpiRhs:
\_constant: , line:38
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiLhs:
\_parameter: (CPU_ID), line:38
|vpiName:CPU_ID
|vpiFullName:taiga_config::CPU_ID
|vpiParamAssign:
\_param_assign: , line:39
|vpiRhs:
\_constant: , line:39
|vpiConstType:5
|vpiDecompile:32'h80000000
|vpiSize:32
|HEX:32'h80000000
|vpiLhs:
\_parameter: (RESET_VEC), line:39
|vpiName:RESET_VEC
|vpiFullName:taiga_config::RESET_VEC
|vpiTypespec:
\_bit_typespec: , line:39
|vpiRange:
\_range: , line:39
|vpiLeftRange:
\_constant: , line:39
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:39
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiParamAssign:
\_param_assign: , line:42
|vpiRhs:
\_constant: , line:42
|vpiConstType:7
|vpiDecompile:33
|vpiSize:32
|INT:33
|vpiLhs:
\_parameter: (COUNTER_W), line:42
|vpiName:COUNTER_W
|vpiFullName:taiga_config::COUNTER_W
|vpiParamAssign:
\_param_assign: , line:48
|vpiRhs:
\_constant: , line:48
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiLhs:
\_parameter: (USE_MUL), line:48
|vpiName:USE_MUL
|vpiFullName:taiga_config::USE_MUL
|vpiParamAssign:
\_param_assign: , line:49
|vpiRhs:
\_constant: , line:49
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiLhs:
\_parameter: (USE_DIV), line:49
|vpiName:USE_DIV
|vpiFullName:taiga_config::USE_DIV
|vpiParamAssign:
\_param_assign: , line:67
|vpiRhs:
\_ref_obj: (QUICK_CLZ), line:67
|vpiName:QUICK_CLZ
|vpiLhs:
\_parameter: (DIV_ALGORITHM), line:67
|vpiName:DIV_ALGORITHM
|vpiFullName:taiga_config::DIV_ALGORITHM
|vpiTypespec:
\_enum_typespec: (div_type), line:66
|vpiParamAssign:
\_param_assign: , line:70
|vpiRhs:
\_constant: , line:70
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiLhs:
\_parameter: (USE_AMO), line:70
|vpiName:USE_AMO
|vpiFullName:taiga_config::USE_AMO
|vpiParamAssign:
\_param_assign: , line:78
|vpiRhs:
\_constant: , line:78
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiLhs:
\_parameter: (USE_I_SCRATCH_MEM), line:78
|vpiName:USE_I_SCRATCH_MEM
|vpiFullName:taiga_config::USE_I_SCRATCH_MEM
|vpiParamAssign:
\_param_assign: , line:79
|vpiRhs:
\_constant: , line:79
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiLhs:
\_parameter: (USE_D_SCRATCH_MEM), line:79
|vpiName:USE_D_SCRATCH_MEM
|vpiFullName:taiga_config::USE_D_SCRATCH_MEM
|vpiParamAssign:
\_param_assign: , line:88
|vpiRhs:
\_constant: , line:88
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiLhs:
\_parameter: (USE_BUS), line:88
|vpiName:USE_BUS
|vpiFullName:taiga_config::USE_BUS
|vpiParamAssign:
\_param_assign: , line:89
|vpiRhs:
\_ref_obj: (AXI_BUS), line:89
|vpiName:AXI_BUS
|vpiLhs:
\_parameter: (BUS_TYPE), line:89
|vpiName:BUS_TYPE
|vpiFullName:taiga_config::BUS_TYPE
|vpiTypespec:
\_enum_typespec: (bus_type_t), line:86
|vpiParamAssign:
\_param_assign: , line:92
|vpiRhs:
\_constant: , line:92
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiLhs:
\_parameter: (USE_DCACHE), line:92
|vpiName:USE_DCACHE
|vpiFullName:taiga_config::USE_DCACHE
|vpiParamAssign:
\_param_assign: , line:93
|vpiRhs:
\_constant: , line:93
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiLhs:
\_parameter: (USE_ICACHE), line:93
|vpiName:USE_ICACHE
|vpiFullName:taiga_config::USE_ICACHE
|vpiParamAssign:
\_param_assign: , line:98
|vpiRhs:
\_constant: , line:98
|vpiConstType:5
|vpiDecompile:32'h80000000
|vpiSize:32
|HEX:32'h80000000
|vpiLhs:
\_parameter: (SCRATCH_ADDR_L), line:98
|vpiName:SCRATCH_ADDR_L
|vpiFullName:taiga_config::SCRATCH_ADDR_L
|vpiParamAssign:
\_param_assign: , line:99
|vpiRhs:
\_constant: , line:99
|vpiConstType:5
|vpiDecompile:32'h800FFFFF
|vpiSize:32
|HEX:32'h800FFFFF
|vpiLhs:
\_parameter: (SCRATCH_ADDR_H), line:99
|vpiName:SCRATCH_ADDR_H
|vpiFullName:taiga_config::SCRATCH_ADDR_H
|vpiParamAssign:
\_param_assign: , line:100
|vpiRhs:
\_constant: , line:100
|vpiConstType:7
|vpiDecompile:4
|vpiSize:32
|INT:4
|vpiLhs:
\_parameter: (SCRATCH_BIT_CHECK), line:100
|vpiName:SCRATCH_BIT_CHECK
|vpiFullName:taiga_config::SCRATCH_BIT_CHECK
|vpiParamAssign:
\_param_assign: , line:102
|vpiRhs:
\_constant: , line:102
|vpiConstType:5
|vpiDecompile:32'h40000000
|vpiSize:32
|HEX:32'h40000000
|vpiLhs:
\_parameter: (MEMORY_ADDR_L), line:102
|vpiName:MEMORY_ADDR_L
|vpiFullName:taiga_config::MEMORY_ADDR_L
|vpiParamAssign:
\_param_assign: , line:103
|vpiRhs:
\_constant: , line:103
|vpiConstType:5
|vpiDecompile:32'h4FFFFFFF
|vpiSize:32
|HEX:32'h4FFFFFFF
|vpiLhs:
\_parameter: (MEMORY_ADDR_H), line:103
|vpiName:MEMORY_ADDR_H
|vpiFullName:taiga_config::MEMORY_ADDR_H
|vpiParamAssign:
\_param_assign: , line:104
|vpiRhs:
\_constant: , line:104
|vpiConstType:7
|vpiDecompile:4
|vpiSize:32
|INT:4
|vpiLhs:
\_parameter: (MEMORY_BIT_CHECK), line:104
|vpiName:MEMORY_BIT_CHECK
|vpiFullName:taiga_config::MEMORY_BIT_CHECK
|vpiParamAssign:
\_param_assign: , line:106
|vpiRhs:
\_constant: , line:106
|vpiConstType:5
|vpiDecompile:32'h60000000
|vpiSize:32
|HEX:32'h60000000
|vpiLhs:
\_parameter: (BUS_ADDR_L), line:106
|vpiName:BUS_ADDR_L
|vpiFullName:taiga_config::BUS_ADDR_L
|vpiParamAssign:
\_param_assign: , line:107
|vpiRhs:
\_constant: , line:107
|vpiConstType:5
|vpiDecompile:32'h6FFFFFFF
|vpiSize:32
|HEX:32'h6FFFFFFF
|vpiLhs:
\_parameter: (BUS_ADDR_H), line:107
|vpiName:BUS_ADDR_H
|vpiFullName:taiga_config::BUS_ADDR_H
|vpiParamAssign:
\_param_assign: , line:108
|vpiRhs:
\_constant: , line:108
|vpiConstType:7
|vpiDecompile:4
|vpiSize:32
|INT:4
|vpiLhs:
\_parameter: (BUS_BIT_CHECK), line:108
|vpiName:BUS_BIT_CHECK
|vpiFullName:taiga_config::BUS_BIT_CHECK
|vpiParamAssign:
\_param_assign: , line:113
|vpiRhs:
\_constant: , line:113
|vpiConstType:7
|vpiDecompile:32
|vpiSize:32
|INT:32
|vpiLhs:
\_parameter: (C_M_AXI_ADDR_WIDTH), line:113
|vpiName:C_M_AXI_ADDR_WIDTH
|vpiFullName:taiga_config::C_M_AXI_ADDR_WIDTH
|vpiParamAssign:
\_param_assign: , line:114
|vpiRhs:
\_constant: , line:114
|vpiConstType:7
|vpiDecompile:32
|vpiSize:32
|INT:32
|vpiLhs:
\_parameter: (C_M_AXI_DATA_WIDTH), line:114
|vpiName:C_M_AXI_DATA_WIDTH
|vpiFullName:taiga_config::C_M_AXI_DATA_WIDTH
|vpiParamAssign:
\_param_assign: , line:121
|vpiRhs:
\_constant: , line:121
|vpiConstType:7
|vpiDecompile:512
|vpiSize:32
|INT:512
|vpiLhs:
\_parameter: (ICACHE_LINES), line:121
|vpiName:ICACHE_LINES
|vpiFullName:taiga_config::ICACHE_LINES
|vpiParamAssign:
\_param_assign: , line:122
|vpiRhs:
\_constant: , line:122
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiLhs:
\_parameter: (ICACHE_WAYS), line:122
|vpiName:ICACHE_WAYS
|vpiFullName:taiga_config::ICACHE_WAYS
|vpiParamAssign:
\_param_assign: , line:123
|vpiRhs:
\_constant: , line:123
|vpiDecompile:9
|INT:9
|vpiLhs:
\_parameter: (ICACHE_LINE_ADDR_W), line:123
|vpiName:ICACHE_LINE_ADDR_W
|vpiFullName:taiga_config::ICACHE_LINE_ADDR_W
|vpiParamAssign:
\_param_assign: , line:124
|vpiRhs:
\_constant: , line:124
|vpiConstType:7
|vpiDecompile:4
|vpiSize:32
|INT:4
|vpiLhs:
\_parameter: (ICACHE_LINE_W), line:124
|vpiName:ICACHE_LINE_W
|vpiFullName:taiga_config::ICACHE_LINE_W
|vpiParamAssign:
\_param_assign: , line:125
|vpiRhs:
\_constant: , line:125
|vpiDecompile:2
|INT:2
|vpiLhs:
\_parameter: (ICACHE_SUB_LINE_ADDR_W), line:125
|vpiName:ICACHE_SUB_LINE_ADDR_W
|vpiFullName:taiga_config::ICACHE_SUB_LINE_ADDR_W
|vpiParamAssign:
\_param_assign: , line:126
|vpiRhs:
\_constant: , line:126
|vpiDecompile:19
|INT:19
|vpiLhs:
\_parameter: (ICACHE_TAG_W), line:126
|vpiName:ICACHE_TAG_W
|vpiFullName:taiga_config::ICACHE_TAG_W
|vpiParamAssign:
\_param_assign: , line:133
|vpiRhs:
\_constant: , line:133
|vpiConstType:7
|vpiDecompile:512
|vpiSize:32
|INT:512
|vpiLhs:
\_parameter: (DCACHE_LINES), line:133
|vpiName:DCACHE_LINES
|vpiFullName:taiga_config::DCACHE_LINES
|vpiParamAssign:
\_param_assign: , line:134
|vpiRhs:
\_constant: , line:134
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiLhs:
\_parameter: (DCACHE_WAYS), line:134
|vpiName:DCACHE_WAYS
|vpiFullName:taiga_config::DCACHE_WAYS
|vpiParamAssign:
\_param_assign: , line:135
|vpiRhs:
\_constant: , line:135
|vpiDecompile:9
|INT:9
|vpiLhs:
\_parameter: (DCACHE_LINE_ADDR_W), line:135
|vpiName:DCACHE_LINE_ADDR_W
|vpiFullName:taiga_config::DCACHE_LINE_ADDR_W
|vpiParamAssign:
\_param_assign: , line:136
|vpiRhs:
\_constant: , line:136
|vpiConstType:7
|vpiDecompile:4
|vpiSize:32
|INT:4
|vpiLhs:
\_parameter: (DCACHE_LINE_W), line:136
|vpiName:DCACHE_LINE_W
|vpiFullName:taiga_config::DCACHE_LINE_W
|vpiParamAssign:
\_param_assign: , line:137
|vpiRhs:
\_constant: , line:137
|vpiDecompile:2
|INT:2
|vpiLhs:
\_parameter: (DCACHE_SUB_LINE_ADDR_W), line:137
|vpiName:DCACHE_SUB_LINE_ADDR_W
|vpiFullName:taiga_config::DCACHE_SUB_LINE_ADDR_W
|vpiParamAssign:
\_param_assign: , line:138
|vpiRhs:
\_constant: , line:138
|vpiDecompile:19
|INT:19
|vpiLhs:
\_parameter: (DCACHE_TAG_W), line:138
|vpiName:DCACHE_TAG_W
|vpiFullName:taiga_config::DCACHE_TAG_W
|vpiParamAssign:
\_param_assign: , line:140
|vpiRhs:
\_constant: , line:140
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiLhs:
\_parameter: (USE_DTAG_INVALIDATIONS), line:140
|vpiName:USE_DTAG_INVALIDATIONS
|vpiFullName:taiga_config::USE_DTAG_INVALIDATIONS
|vpiParamAssign:
\_param_assign: , line:145
|vpiRhs:
\_constant: , line:145
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiLhs:
\_parameter: (ITLB_WAYS), line:145
|vpiName:ITLB_WAYS
|vpiFullName:taiga_config::ITLB_WAYS
|vpiParamAssign:
\_param_assign: , line:146
|vpiRhs:
\_constant: , line:146
|vpiConstType:7
|vpiDecompile:32
|vpiSize:32
|INT:32
|vpiLhs:
\_parameter: (ITLB_DEPTH), line:146
|vpiName:ITLB_DEPTH
|vpiFullName:taiga_config::ITLB_DEPTH
|vpiParamAssign:
\_param_assign: , line:151
|vpiRhs:
\_constant: , line:151
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiLhs:
\_parameter: (DTLB_WAYS), line:151
|vpiName:DTLB_WAYS
|vpiFullName:taiga_config::DTLB_WAYS
|vpiParamAssign:
\_param_assign: , line:152
|vpiRhs:
\_constant: , line:152
|vpiConstType:7
|vpiDecompile:32
|vpiSize:32
|INT:32
|vpiLhs:
\_parameter: (DTLB_DEPTH), line:152
|vpiName:DTLB_DEPTH
|vpiFullName:taiga_config::DTLB_DEPTH
|vpiParamAssign:
\_param_assign: , line:158
|vpiRhs:
\_constant: , line:158
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiLhs:
\_parameter: (USE_BRANCH_PREDICTOR), line:158
|vpiName:USE_BRANCH_PREDICTOR
|vpiFullName:taiga_config::USE_BRANCH_PREDICTOR
|vpiParamAssign:
\_param_assign: , line:159
|vpiRhs:
\_constant: , line:159
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiLhs:
\_parameter: (BRANCH_PREDICTOR_WAYS), line:159
|vpiName:BRANCH_PREDICTOR_WAYS
|vpiFullName:taiga_config::BRANCH_PREDICTOR_WAYS
|vpiParamAssign:
\_param_assign: , line:160
|vpiRhs:
\_constant: , line:160
|vpiConstType:7
|vpiDecompile:512
|vpiSize:32
|INT:512
|vpiLhs:
\_parameter: (BRANCH_TABLE_ENTRIES), line:160
|vpiName:BRANCH_TABLE_ENTRIES
|vpiFullName:taiga_config::BRANCH_TABLE_ENTRIES
|vpiParamAssign:
\_param_assign: , line:161
|vpiRhs:
\_constant: , line:161
|vpiConstType:7
|vpiDecompile:8
|vpiSize:32
|INT:8
|vpiLhs:
\_parameter: (RAS_DEPTH), line:161
|vpiName:RAS_DEPTH
|vpiFullName:taiga_config::RAS_DEPTH
|vpiParamAssign:
\_param_assign: , line:167
|vpiRhs:
\_constant: , line:167
|vpiConstType:7
|vpiDecompile:4
|vpiSize:32
|INT:4
|vpiLhs:
\_parameter: (MAX_INFLIGHT_COUNT), line:167
|vpiName:MAX_INFLIGHT_COUNT
|vpiFullName:taiga_config::MAX_INFLIGHT_COUNT
|vpiParamAssign:
\_param_assign: , line:168
|vpiRhs:
\_constant: , line:168
|vpiConstType:7
|vpiDecompile:4
|vpiSize:32
|INT:4
|vpiLhs:
\_parameter: (FETCH_BUFFER_DEPTH), line:168
|vpiName:FETCH_BUFFER_DEPTH
|vpiFullName:taiga_config::FETCH_BUFFER_DEPTH
|vpiParamAssign:
\_param_assign: , line:172
|vpiRhs:
\_constant: , line:172
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiLhs:
\_parameter: (ENABLE_TRACE_INTERFACE), line:172
|vpiName:ENABLE_TRACE_INTERFACE
|vpiFullName:taiga_config::ENABLE_TRACE_INTERFACE
|vpiParamAssign:
\_param_assign: , line:177
|vpiRhs:
\_constant: , line:177
|vpiConstType:7
|vpiDecompile:4
|vpiSize:32
|INT:4
|vpiLhs:
\_parameter: (L1_CONNECTIONS), line:177
|vpiName:L1_CONNECTIONS
|vpiFullName:taiga_config::L1_CONNECTIONS
|vpiParamAssign:
\_param_assign: , line:178
|vpiRhs:
\_constant: , line:178
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiLhs:
\_parameter: (L1_DCACHE_ID), line:178
|vpiName:L1_DCACHE_ID
|vpiFullName:taiga_config::L1_DCACHE_ID
|vpiParamAssign:
\_param_assign: , line:179
|vpiRhs:
\_constant: , line:179
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiLhs:
\_parameter: (L1_DMMU_ID), line:179
|vpiName:L1_DMMU_ID
|vpiFullName:taiga_config::L1_DMMU_ID
|vpiParamAssign:
\_param_assign: , line:180
|vpiRhs:
\_constant: , line:180
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiLhs:
\_parameter: (L1_ICACHE_ID), line:180
|vpiName:L1_ICACHE_ID
|vpiFullName:taiga_config::L1_ICACHE_ID
|vpiParamAssign:
\_param_assign: , line:181
|vpiRhs:
\_constant: , line:181
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiLhs:
\_parameter: (L1_IMMU_ID), line:181
|vpiName:L1_IMMU_ID
|vpiFullName:taiga_config::L1_IMMU_ID
|vpiParamAssign:
\_param_assign: , line:186
|vpiRhs:
\_constant: , line:186
|vpiDecompile:4
|INT:4
|vpiLhs:
\_parameter: (NUM_WB_UNITS), line:186
|vpiName:NUM_WB_UNITS
|vpiFullName:taiga_config::NUM_WB_UNITS
|vpiParamAssign:
\_param_assign: , line:187
|vpiRhs:
\_constant: , line:187
|vpiDecompile:2
|INT:2
|vpiLhs:
\_parameter: (WB_UNITS_WIDTH), line:187
|vpiName:WB_UNITS_WIDTH
|vpiFullName:taiga_config::WB_UNITS_WIDTH
|vpiParamAssign:
\_param_assign: , line:188
|vpiRhs:
\_constant: , line:188
|vpiDecompile:6
|INT:6
|vpiLhs:
\_parameter: (NUM_UNITS), line:188
|vpiName:NUM_UNITS
|vpiFullName:taiga_config::NUM_UNITS
|vpiParamAssign:
\_param_assign: , line:190
|vpiRhs:
\_constant: , line:190
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiLhs:
\_parameter: (ALU_UNIT_WB_ID), line:190
|vpiName:ALU_UNIT_WB_ID
|vpiFullName:taiga_config::ALU_UNIT_WB_ID
|vpiParamAssign:
\_param_assign: , line:191
|vpiRhs:
\_constant: , line:191
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiLhs:
\_parameter: (LS_UNIT_WB_ID), line:191
|vpiName:LS_UNIT_WB_ID
|vpiFullName:taiga_config::LS_UNIT_WB_ID
|vpiParamAssign:
\_param_assign: , line:192
|vpiRhs:
\_constant: , line:192
|vpiDecompile:2
|INT:2
|vpiLhs:
\_parameter: (DIV_UNIT_WB_ID), line:192
|vpiName:DIV_UNIT_WB_ID
|vpiFullName:taiga_config::DIV_UNIT_WB_ID
|vpiParamAssign:
\_param_assign: , line:193
|vpiRhs:
\_constant: , line:193
|vpiDecompile:3
|INT:3
|vpiLhs:
\_parameter: (MUL_UNIT_WB_ID), line:193
|vpiName:MUL_UNIT_WB_ID
|vpiFullName:taiga_config::MUL_UNIT_WB_ID
|vpiParamAssign:
\_param_assign: , line:195
|vpiRhs:
\_constant: , line:195
|vpiDecompile:4
|INT:4
|vpiLhs:
\_parameter: (BRANCH_UNIT_ID), line:195
|vpiName:BRANCH_UNIT_ID
|vpiFullName:taiga_config::BRANCH_UNIT_ID
|vpiParamAssign:
\_param_assign: , line:196
|vpiRhs:
\_constant: , line:196
|vpiDecompile:5
|INT:5
|vpiLhs:
\_parameter: (GC_UNIT_ID), line:196
|vpiName:GC_UNIT_ID
|vpiFullName:taiga_config::GC_UNIT_ID
|vpiParameter:
\_parameter: (FPGA_VENDOR), line:27
|vpiParameter:
\_parameter: (ENABLE_M_MODE), line:34
|vpiParameter:
\_parameter: (ENABLE_S_MODE), line:36
|vpiParameter:
\_parameter: (CPU_ID), line:38
|vpiParameter:
\_parameter: (RESET_VEC), line:39
|vpiParameter:
\_parameter: (COUNTER_W), line:42
|vpiParameter:
\_parameter: (USE_MUL), line:48
|vpiParameter:
\_parameter: (USE_DIV), line:49
|vpiParameter:
\_parameter: (DIV_ALGORITHM), line:67
|vpiParameter:
\_parameter: (USE_AMO), line:70
|vpiParameter:
\_parameter: (USE_I_SCRATCH_MEM), line:78
|vpiParameter:
\_parameter: (USE_D_SCRATCH_MEM), line:79
|vpiParameter:
\_parameter: (USE_BUS), line:88
|vpiParameter:
\_parameter: (BUS_TYPE), line:89
|vpiParameter:
\_parameter: (USE_DCACHE), line:92
|vpiParameter:
\_parameter: (USE_ICACHE), line:93
|vpiParameter:
\_parameter: (SCRATCH_ADDR_L), line:98
|vpiParameter:
\_parameter: (SCRATCH_ADDR_H), line:99
|vpiParameter:
\_parameter: (SCRATCH_BIT_CHECK), line:100
|vpiParameter:
\_parameter: (MEMORY_ADDR_L), line:102
|vpiParameter:
\_parameter: (MEMORY_ADDR_H), line:103
|vpiParameter:
\_parameter: (MEMORY_BIT_CHECK), line:104
|vpiParameter:
\_parameter: (BUS_ADDR_L), line:106
|vpiParameter:
\_parameter: (BUS_ADDR_H), line:107
|vpiParameter:
\_parameter: (BUS_BIT_CHECK), line:108
|vpiParameter:
\_parameter: (C_M_AXI_ADDR_WIDTH), line:113
|vpiParameter:
\_parameter: (C_M_AXI_DATA_WIDTH), line:114
|vpiParameter:
\_parameter: (ICACHE_LINES), line:121
|vpiParameter:
\_parameter: (ICACHE_WAYS), line:122
|vpiParameter:
\_parameter: (ICACHE_LINE_ADDR_W), line:123
|vpiParameter:
\_parameter: (ICACHE_LINE_W), line:124
|vpiParameter:
\_parameter: (ICACHE_SUB_LINE_ADDR_W), line:125
|vpiParameter:
\_parameter: (ICACHE_TAG_W), line:126
|vpiParameter:
\_parameter: (DCACHE_LINES), line:133
|vpiParameter:
\_parameter: (DCACHE_WAYS), line:134
|vpiParameter:
\_parameter: (DCACHE_LINE_ADDR_W), line:135
|vpiParameter:
\_parameter: (DCACHE_LINE_W), line:136
|vpiParameter:
\_parameter: (DCACHE_SUB_LINE_ADDR_W), line:137
|vpiParameter:
\_parameter: (DCACHE_TAG_W), line:138
|vpiParameter:
\_parameter: (USE_DTAG_INVALIDATIONS), line:140
|vpiParameter:
\_parameter: (ITLB_WAYS), line:145
|vpiParameter:
\_parameter: (ITLB_DEPTH), line:146
|vpiParameter:
\_parameter: (DTLB_WAYS), line:151
|vpiParameter:
\_parameter: (DTLB_DEPTH), line:152
|vpiParameter:
\_parameter: (USE_BRANCH_PREDICTOR), line:158
|vpiParameter:
\_parameter: (BRANCH_PREDICTOR_WAYS), line:159
|vpiParameter:
\_parameter: (BRANCH_TABLE_ENTRIES), line:160
|vpiParameter:
\_parameter: (RAS_DEPTH), line:161
|vpiParameter:
\_parameter: (MAX_INFLIGHT_COUNT), line:167
|vpiParameter:
\_parameter: (FETCH_BUFFER_DEPTH), line:168
|vpiParameter:
\_parameter: (ENABLE_TRACE_INTERFACE), line:172
|vpiParameter:
\_parameter: (L1_CONNECTIONS), line:177
|vpiParameter:
\_parameter: (L1_DCACHE_ID), line:178
|vpiParameter:
\_parameter: (L1_DMMU_ID), line:179
|vpiParameter:
\_parameter: (L1_ICACHE_ID), line:180
|vpiParameter:
\_parameter: (L1_IMMU_ID), line:181
|vpiParameter:
\_parameter: (NUM_WB_UNITS), line:186
|vpiParameter:
\_parameter: (WB_UNITS_WIDTH), line:187
|vpiParameter:
\_parameter: (NUM_UNITS), line:188
|vpiParameter:
\_parameter: (ALU_UNIT_WB_ID), line:190
|vpiParameter:
\_parameter: (LS_UNIT_WB_ID), line:191
|vpiParameter:
\_parameter: (DIV_UNIT_WB_ID), line:192
|vpiParameter:
\_parameter: (MUL_UNIT_WB_ID), line:193
|vpiParameter:
\_parameter: (BRANCH_UNIT_ID), line:195
|vpiParameter:
\_parameter: (GC_UNIT_ID), line:196
|uhdmallPackages:
\_package: taiga_types, file:third_party/cores/taiga/core/taiga_types.sv, line:23, parent:work@div_unit_core_wrapper
|vpiDefName:taiga_types
|vpiFullName:taiga_types
|vpiTypedef:
\_struct_typespec: (alu_inputs_t), line:301
|vpiPacked:1
|vpiName:alu_inputs_t
|vpiTypespecMember:
\_typespec_member: (in1), line:302
|vpiName:in1
|vpiTypespec:
\_logic_typespec: , line:302
|vpiRange:
\_range: , line:302, parent:alu_inputs_t
|vpiLeftRange:
\_constant: , line:302
|vpiConstType:7
|vpiDecompile:32
|vpiSize:32
|INT:32
|vpiRightRange:
\_constant: , line:302
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiTypespecMember:
\_typespec_member: (in2), line:303
|vpiName:in2
|vpiTypespec:
\_logic_typespec: , line:303
|vpiRange:
\_range: , line:303, parent:alu_inputs_t
|vpiLeftRange:
\_constant: , line:303
|vpiConstType:7
|vpiDecompile:32
|vpiSize:32
|INT:32
|vpiRightRange:
\_constant: , line:303
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiTypespecMember:
\_typespec_member: (shifter_in), line:304
|vpiName:shifter_in
|vpiTypespec:
\_logic_typespec: , line:304
|vpiRange:
\_range: , line:304, parent:alu_inputs_t
|vpiLeftRange:
\_constant: , line:304
|vpiDecompile:31
|INT:31
|vpiRightRange:
\_constant: , line:304
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiTypespecMember:
\_typespec_member: (shift_amount), line:305
|vpiName:shift_amount
|vpiTypespec:
\_logic_typespec: , line:305
|vpiRange:
\_range: , line:305, parent:alu_inputs_t
|vpiLeftRange:
\_constant: , line:305
|vpiConstType:7
|vpiDecompile:4
|vpiSize:32
|INT:4
|vpiRightRange:
\_constant: , line:305
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiTypespecMember:
\_typespec_member: (subtract), line:306
|vpiName:subtract
|vpiTypespec:
\_logic_typespec: , line:306
|vpiTypespecMember:
\_typespec_member: (arith), line:307
|vpiName:arith
|vpiTypespec:
\_logic_typespec: , line:307
|vpiTypespecMember:
\_typespec_member: (lshift), line:308
|vpiName:lshift
|vpiTypespec:
\_logic_typespec: , line:308
|vpiTypespecMember:
\_typespec_member: (logic_op), line:309
|vpiName:logic_op
|vpiTypespec:
\_logic_typespec: , line:309
|vpiRange:
\_range: , line:309, parent:alu_inputs_t
|vpiLeftRange:
\_constant: , line:309
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:309
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiTypespecMember:
\_typespec_member: (op), line:310
|vpiName:op
|vpiTypespec:
\_logic_typespec: , line:310
|vpiRange:
\_range: , line:310, parent:alu_inputs_t
|vpiLeftRange:
\_constant: , line:310
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:310
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiTypedef:
\_enum_typespec: (alu_logic_op_t), line:84
|vpiName:alu_logic_op_t
|vpiBaseTypespec:
\_bit_typespec: , line:79
|vpiRange:
\_range: , line:79
|vpiLeftRange:
\_constant: , line:79
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:79
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiEnumConst:
\_enum_const: (ALU_LOGIC_ADD), line:83
|vpiName:ALU_LOGIC_ADD
|INT:3
|vpiEnumConst:
\_enum_const: (ALU_LOGIC_AND), line:82
|vpiName:ALU_LOGIC_AND
|INT:2
|vpiEnumConst:
\_enum_const: (ALU_LOGIC_OR), line:81
|vpiName:ALU_LOGIC_OR
|INT:1
|vpiEnumConst:
\_enum_const: (ALU_LOGIC_XOR), line:80
|vpiName:ALU_LOGIC_XOR
|INT:0
|vpiTypedef:
\_enum_typespec: (alu_op_t), line:91
|vpiName:alu_op_t
|vpiBaseTypespec:
\_bit_typespec: , line:86
|vpiRange:
\_range: , line:86
|vpiLeftRange:
\_constant: , line:86
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:86
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiEnumConst:
\_enum_const: (ALU_ADD_SUB), line:87
|vpiName:ALU_ADD_SUB
|INT:0
|vpiEnumConst:
\_enum_const: (ALU_LSHIFT), line:90
|vpiName:ALU_LSHIFT
|INT:3
|vpiEnumConst:
\_enum_const: (ALU_RSHIFT), line:89
|vpiName:ALU_RSHIFT
|INT:2
|vpiEnumConst:
\_enum_const: (ALU_SLT), line:88
|vpiName:ALU_SLT
|INT:1
|vpiTypedef:
\_enum_typespec: (alu_rs1_op_t), line:97
|vpiName:alu_rs1_op_t
|vpiBaseTypespec:
\_bit_typespec: , line:93
|vpiRange:
\_range: , line:93
|vpiLeftRange:
\_constant: , line:93
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:93
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiEnumConst:
\_enum_const: (ALU_RS1_PC), line:95
|vpiName:ALU_RS1_PC
|INT:1
|vpiEnumConst:
\_enum_const: (ALU_RS1_RF), line:96
|vpiName:ALU_RS1_RF
|INT:2
|vpiEnumConst:
\_enum_const: (ALU_RS1_ZERO), line:94
|vpiName:ALU_RS1_ZERO
|INT:0
|vpiTypedef:
\_enum_typespec: (alu_rs2_op_t), line:104
|vpiName:alu_rs2_op_t
|vpiBaseTypespec:
\_bit_typespec: , line:99
|vpiRange:
\_range: , line:99
|vpiLeftRange:
\_constant: , line:99
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:99
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiEnumConst:
\_enum_const: (ALU_RS2_ARITH_IMM), line:101
|vpiName:ALU_RS2_ARITH_IMM
|INT:1
|vpiEnumConst:
\_enum_const: (ALU_RS2_JAL_JALR), line:102
|vpiName:ALU_RS2_JAL_JALR
|INT:2
|vpiEnumConst:
\_enum_const: (ALU_RS2_LUI_AUIPC), line:100
|vpiName:ALU_RS2_LUI_AUIPC
|INT:0
|vpiEnumConst:
\_enum_const: (ALU_RS2_RF), line:103
|vpiName:ALU_RS2_RF
|INT:3
|vpiTypedef:
\_struct_typespec: (amo_alu_inputs_t), line:356
|vpiPacked:1
|vpiName:amo_alu_inputs_t
|vpiTypespecMember:
\_typespec_member: (rs1_load), line:357
|vpiName:rs1_load
|vpiTypespec:
\_logic_typespec: , line:357
|vpiRange:
\_range: , line:357, parent:amo_alu_inputs_t
|vpiLeftRange:
\_constant: , line:357
|vpiDecompile:31
|INT:31
|vpiRightRange:
\_constant: , line:357
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiTypespecMember:
\_typespec_member: (rs2), line:358
|vpiName:rs2
|vpiTypespec:
\_logic_typespec: , line:358
|vpiRange:
\_range: , line:358, parent:amo_alu_inputs_t
|vpiLeftRange:
\_constant: , line:358
|vpiDecompile:31
|INT:31
|vpiRightRange:
\_constant: , line:358
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiTypespecMember:
\_typespec_member: (op), line:359
|vpiName:op
|vpiTypespec:
\_logic_typespec: , line:359
|vpiRange:
\_range: , line:359, parent:amo_alu_inputs_t
|vpiLeftRange:
\_constant: , line:359
|vpiConstType:7
|vpiDecompile:4
|vpiSize:32
|INT:4
|vpiRightRange:
\_constant: , line:359
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiTypedef:
\_struct_typespec: (amo_details_t), line:362
|vpiPacked:1
|vpiName:amo_details_t
|vpiTypespecMember:
\_typespec_member: (is_lr), line:363
|vpiName:is_lr
|vpiTypespec:
\_logic_typespec: , line:363
|vpiTypespecMember:
\_typespec_member: (is_sc), line:364
|vpiName:is_sc
|vpiTypespec:
\_logic_typespec: , line:364
|vpiTypespecMember:
\_typespec_member: (is_amo), line:365
|vpiName:is_amo
|vpiTypespec:
\_logic_typespec: , line:365
|vpiTypespecMember:
\_typespec_member: (op), line:366
|vpiName:op
|vpiTypespec:
\_logic_typespec: , line:366
|vpiRange:
\_range: , line:366, parent:amo_details_t
|vpiLeftRange:
\_constant: , line:366
|vpiConstType:7
|vpiDecompile:4
|vpiSize:32
|INT:4
|vpiRightRange:
\_constant: , line:366
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiTypedef:
\_enum_typespec: (amo_t), line:354
|vpiName:amo_t
|vpiBaseTypespec:
\_bit_typespec: , line:342
|vpiRange:
\_range: , line:342
|vpiLeftRange:
\_constant: , line:342
|vpiConstType:7
|vpiDecompile:4
|vpiSize:32
|INT:4
|vpiRightRange:
\_constant: , line:342
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiEnumConst:
\_enum_const: (AMO_ADD), line:346
|vpiName:AMO_ADD
|INT:0
|vpiEnumConst:
\_enum_const: (AMO_AND), line:348
|vpiName:AMO_AND
|INT:12
|vpiEnumConst:
\_enum_const: (AMO_LR), line:343
|vpiName:AMO_LR
|INT:2
|vpiEnumConst:
\_enum_const: (AMO_MAX), line:351
|vpiName:AMO_MAX
|INT:20
|vpiEnumConst:
\_enum_const: (AMO_MAXU), line:353
|vpiName:AMO_MAXU
|INT:28
|vpiEnumConst:
\_enum_const: (AMO_MIN), line:350
|vpiName:AMO_MIN
|INT:16
|vpiEnumConst:
\_enum_const: (AMO_MINU), line:352
|vpiName:AMO_MINU
|INT:24
|vpiEnumConst:
\_enum_const: (AMO_OR), line:349
|vpiName:AMO_OR
|INT:8
|vpiEnumConst:
\_enum_const: (AMO_SC), line:344
|vpiName:AMO_SC
|INT:3
|vpiEnumConst:
\_enum_const: (AMO_SWAP), line:345
|vpiName:AMO_SWAP
|INT:1
|vpiEnumConst:
\_enum_const: (AMO_XOR), line:347
|vpiName:AMO_XOR
|INT:4
|vpiTypedef:
\_struct_typespec: (branch_inputs_t), line:313
|vpiPacked:1
|vpiName:branch_inputs_t
|vpiTypespecMember:
\_typespec_member: (rs1), line:314
|vpiName:rs1
|vpiTypespec:
\_logic_typespec: , line:314
|vpiRange:
\_range: , line:314, parent:branch_inputs_t
|vpiLeftRange:
\_constant: , line:314
|vpiDecompile:31
|INT:31
|vpiRightRange:
\_constant: , line:314
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiTypespecMember:
\_typespec_member: (rs2), line:315
|vpiName:rs2
|vpiTypespec:
\_logic_typespec: , line:315
|vpiRange:
\_range: , line:315, parent:branch_inputs_t
|vpiLeftRange:
\_constant: , line:315
|vpiDecompile:31
|INT:31
|vpiRightRange:
\_constant: , line:315
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiTypespecMember:
\_typespec_member: (fn3), line:316
|vpiName:fn3
|vpiTypespec:
\_logic_typespec: , line:316
|vpiRange:
\_range: , line:316, parent:branch_inputs_t
|vpiLeftRange:
\_constant: , line:316
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiRightRange:
\_constant: , line:316
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiTypespecMember:
\_typespec_member: (dec_pc), line:317
|vpiName:dec_pc
|vpiTypespec:
\_logic_typespec: , line:317
|vpiRange:
\_range: , line:317, parent:branch_inputs_t
|vpiLeftRange:
\_constant: , line:317
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:317
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiTypespecMember:
\_typespec_member: (dec_pc_valid), line:318
|vpiName:dec_pc_valid
|vpiTypespec:
\_logic_typespec: , line:318
|vpiTypespecMember:
\_typespec_member: (use_signed), line:319
|vpiName:use_signed
|vpiTypespec:
\_logic_typespec: , line:319
|vpiTypespecMember:
\_typespec_member: (jal), line:320
|vpiName:jal
|vpiTypespec:
\_logic_typespec: , line:320
|vpiTypespecMember:
\_typespec_member: (jalr), line:321
|vpiName:jalr
|vpiTypespec:
\_logic_typespec: , line:321
|vpiTypespecMember:
\_typespec_member: (is_call), line:322
|vpiName:is_call
|vpiTypespec:
\_logic_typespec: , line:322
|vpiTypespecMember:
\_typespec_member: (is_return), line:323
|vpiName:is_return
|vpiTypespec:
\_logic_typespec: , line:323
|vpiTypespecMember:
\_typespec_member: (instruction), line:324
|vpiName:instruction
|vpiTypespec:
\_logic_typespec: , line:324
|vpiRange:
\_range: , line:324, parent:branch_inputs_t
|vpiLeftRange:
\_constant: , line:324
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:324
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiTypespecMember:
\_typespec_member: (branch_metadata), line:325
|vpiName:branch_metadata
|vpiTypespec:
\_logic_typespec: (branch_predictor_metadata_t), line:32
|vpiName:branch_predictor_metadata_t
|vpiRange:
\_range: , line:32
|vpiLeftRange:
\_constant: , line:32
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:32
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiTypespecMember:
\_typespec_member: (branch_prediction_used), line:326
|vpiName:branch_prediction_used
|vpiTypespec:
\_logic_typespec: , line:326
|vpiTypespecMember:
\_typespec_member: (bp_update_way), line:327
|vpiName:bp_update_way
|vpiTypespec:
\_logic_typespec: , line:327
|vpiRange:
\_range: , line:327, parent:branch_inputs_t
|vpiLeftRange:
\_operation: , line:327
|vpiOpType:11
|vpiOperand:
\_ref_obj: (BRANCH_PREDICTOR_WAYS), line:327, parent:branch_inputs_t
|vpiName:BRANCH_PREDICTOR_WAYS
|vpiFullName:branch_inputs_t.BRANCH_PREDICTOR_WAYS
|vpiOperand:
\_constant: , line:327
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:327
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiTypedef:
\_logic_typespec: (branch_predictor_metadata_t), line:32
|vpiTypedef:
\_struct_typespec: (branch_results_t), line:330
|vpiPacked:1
|vpiName:branch_results_t
|vpiTypespecMember:
\_typespec_member: (pc_ex), line:331
|vpiName:pc_ex
|vpiTypespec:
\_logic_typespec: , line:331
|vpiRange:
\_range: , line:331, parent:branch_results_t
|vpiLeftRange:
\_constant: , line:331
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:331
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiTypespecMember:
\_typespec_member: (jump_pc), line:332
|vpiName:jump_pc
|vpiTypespec:
\_logic_typespec: , line:332
|vpiRange:
\_range: , line:332, parent:branch_results_t
|vpiLeftRange:
\_constant: , line:332
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:332
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiTypespecMember:
\_typespec_member: (njump_pc), line:333
|vpiName:njump_pc
|vpiTypespec:
\_logic_typespec: , line:333
|vpiRange:
\_range: , line:333, parent:branch_results_t
|vpiLeftRange:
\_constant: , line:333
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:333
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiTypespecMember:
\_typespec_member: (branch_taken), line:334
|vpiName:branch_taken
|vpiTypespec:
\_logic_typespec: , line:334
|vpiTypespecMember:
\_typespec_member: (branch_ex), line:335
|vpiName:branch_ex
|vpiTypespec:
\_logic_typespec: , line:335
|vpiTypespecMember:
\_typespec_member: (is_return_ex), line:336
|vpiName:is_return_ex
|vpiTypespec:
\_logic_typespec: , line:336
|vpiTypespecMember:
\_typespec_member: (branch_ex_metadata), line:337
|vpiName:branch_ex_metadata
|vpiTypespec:
\_logic_typespec: (branch_predictor_metadata_t), line:32
|vpiTypespecMember:
\_typespec_member: (branch_prediction_used), line:338
|vpiName:branch_prediction_used
|vpiTypespec:
\_logic_typespec: , line:338
|vpiTypespecMember:
\_typespec_member: (bp_update_way), line:339
|vpiName:bp_update_way
|vpiTypespec:
\_logic_typespec: , line:339
|vpiRange:
\_range: , line:339, parent:branch_results_t
|vpiLeftRange:
\_operation: , line:339
|vpiOpType:11
|vpiOperand:
\_ref_obj: (BRANCH_PREDICTOR_WAYS), line:339, parent:branch_results_t
|vpiName:BRANCH_PREDICTOR_WAYS
|vpiFullName:branch_results_t.BRANCH_PREDICTOR_WAYS
|vpiOperand:
\_constant: , line:339
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:339
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiTypedef:
\_enum_typespec: (bus_type_t), line:86
|vpiTypedef:
\_struct_typespec: (csr_inputs_t), line:396
|vpiPacked:1
|vpiName:csr_inputs_t
|vpiTypespecMember:
\_typespec_member: (rs1), line:397
|vpiName:rs1
|vpiTypespec:
\_logic_typespec: , line:397
|vpiRange:
\_range: , line:397, parent:csr_inputs_t
|vpiLeftRange:
\_constant: , line:397
|vpiDecompile:31
|INT:31
|vpiRightRange:
\_constant: , line:397
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiTypespecMember:
\_typespec_member: (csr_addr), line:398
|vpiName:csr_addr
|vpiTypespec:
\_logic_typespec: , line:398
|vpiRange:
\_range: , line:398, parent:csr_inputs_t
|vpiLeftRange:
\_constant: , line:398
|vpiConstType:7
|vpiDecompile:11
|vpiSize:32
|INT:11
|vpiRightRange:
\_constant: , line:398
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiTypespecMember:
\_typespec_member: (csr_op), line:399
|vpiName:csr_op
|vpiTypespec:
\_logic_typespec: , line:399
|vpiRange:
\_range: , line:399, parent:csr_inputs_t
|vpiLeftRange:
\_constant: , line:399
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:399
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiTypespecMember:
\_typespec_member: (rs1_is_zero), line:400
|vpiName:rs1_is_zero
|vpiTypespec:
\_logic_typespec: , line:400
|vpiTypespecMember:
\_typespec_member: (rd_is_zero), line:401
|vpiName:rd_is_zero
|vpiTypespec:
\_logic_typespec: , line:401
|vpiTypedef:
\_enum_typespec: (csr_op_t), line:218
|vpiName:csr_op_t
|vpiBaseTypespec:
\_bit_typespec: , line:214
|vpiRange:
\_range: , line:214
|vpiLeftRange:
\_constant: , line:214
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:214
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiEnumConst:
\_enum_const: (CSR_RC), line:217
|vpiName:CSR_RC
|INT:3
|vpiEnumConst:
\_enum_const: (CSR_RS), line:216
|vpiName:CSR_RS
|INT:2
|vpiEnumConst:
\_enum_const: (CSR_RW), line:215
|vpiName:CSR_RW
|INT:1
|vpiTypedef:
\_enum_typespec: (csr_t), line:201
|vpiName:csr_t
|vpiBaseTypespec:
\_bit_typespec: , line:140
|vpiRange:
\_range: , line:140
|vpiLeftRange:
\_constant: , line:140
|vpiConstType:7
|vpiDecompile:11
|vpiSize:32
|INT:11
|vpiRightRange:
\_constant: , line:140
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiEnumConst:
\_enum_const: (CYCLE), line:190
|vpiName:CYCLE
|INT:3072
|vpiEnumConst:
\_enum_const: (CYCLEH), line:193
|vpiName:CYCLEH
|INT:3200
|vpiEnumConst:
\_enum_const: (DCSR), line:198
|vpiName:DCSR
|INT:1968
|vpiEnumConst:
\_enum_const: (DPC), line:199
|vpiName:DPC
|INT:1969
|vpiEnumConst:
\_enum_const: (DSCRATCH), line:200
|vpiName:DSCRATCH
|INT:1970
|vpiEnumConst:
\_enum_const: (FCSR), line:188
|vpiName:FCSR
|INT:3
|vpiEnumConst:
\_enum_const: (FFLAGS), line:186
|vpiName:FFLAGS
|INT:1
|vpiEnumConst:
\_enum_const: (FRM), line:187
|vpiName:FRM
|INT:2
|vpiEnumConst:
\_enum_const: (INSTRET), line:192
|vpiName:INSTRET
|INT:3074
|vpiEnumConst:
\_enum_const: (INSTRETH), line:195
|vpiName:INSTRETH
|INT:3202
|vpiEnumConst:
\_enum_const: (MARCHID), line:143
|vpiName:MARCHID
|INT:3858
|vpiEnumConst:
\_enum_const: (MCAUSE), line:156
|vpiName:MCAUSE
|INT:834
|vpiEnumConst:
\_enum_const: (MCYCLE), line:161
|vpiName:MCYCLE
|INT:2816
|vpiEnumConst:
\_enum_const: (MCYCLEH), line:163
|vpiName:MCYCLEH
|INT:2944
|vpiEnumConst:
\_enum_const: (MEDELEG), line:149
|vpiName:MEDELEG
|INT:770
|vpiEnumConst:
\_enum_const: (MEPC), line:155
|vpiName:MEPC
|INT:833
|vpiEnumConst:
\_enum_const: (MHARTID), line:145
|vpiName:MHARTID
|INT:3860
|vpiEnumConst:
\_enum_const: (MIDELEG), line:150
|vpiName:MIDELEG
|INT:771
|vpiEnumConst:
\_enum_const: (MIE), line:151
|vpiName:MIE
|INT:772
|vpiEnumConst:
\_enum_const: (MIMPID), line:144
|vpiName:MIMPID
|INT:3859
|vpiEnumConst:
\_enum_const: (MINSTRET), line:162
|vpiName:MINSTRET
|INT:2818
|vpiEnumConst:
\_enum_const: (MINSTRETH), line:164
|vpiName:MINSTRETH
|INT:2946
|vpiEnumConst:
\_enum_const: (MIP), line:158
|vpiName:MIP
|INT:836
|vpiEnumConst:
\_enum_const: (MISA), line:148
|vpiName:MISA
|INT:769
|vpiEnumConst:
\_enum_const: (MSCRATCH), line:154
|vpiName:MSCRATCH
|INT:832
|vpiEnumConst:
\_enum_const: (MSTATUS), line:147
|vpiName:MSTATUS
|INT:768
|vpiEnumConst:
\_enum_const: (MTVAL), line:157
|vpiName:MTVAL
|INT:835
|vpiEnumConst:
\_enum_const: (MTVEC), line:152
|vpiName:MTVEC
|INT:773
|vpiEnumConst:
\_enum_const: (MVENDORID), line:142
|vpiName:MVENDORID
|INT:3857
|vpiEnumConst:
\_enum_const: (SATP), line:182
|vpiName:SATP
|INT:384
|vpiEnumConst:
\_enum_const: (SCAUSE), line:177
|vpiName:SCAUSE
|INT:322
|vpiEnumConst:
\_enum_const: (SEDELEG), line:169
|vpiName:SEDELEG
|INT:258
|vpiEnumConst:
\_enum_const: (SEPC), line:176
|vpiName:SEPC
|INT:321
|vpiEnumConst:
\_enum_const: (SIDELEG), line:170
|vpiName:SIDELEG
|INT:259
|vpiEnumConst:
\_enum_const: (SIE), line:171
|vpiName:SIE
|INT:260
|vpiEnumConst:
\_enum_const: (SIP), line:179
|vpiName:SIP
|INT:324
|vpiEnumConst:
\_enum_const: (SSCRATCH), line:175
|vpiName:SSCRATCH
|INT:320
|vpiEnumConst:
\_enum_const: (SSTATUS), line:168
|vpiName:SSTATUS
|INT:256
|vpiEnumConst:
\_enum_const: (STVAL), line:178
|vpiName:STVAL
|INT:323
|vpiEnumConst:
\_enum_const: (STVEC), line:172
|vpiName:STVEC
|INT:261
|vpiEnumConst:
\_enum_const: (TIME), line:191
|vpiName:TIME
|INT:3073
|vpiEnumConst:
\_enum_const: (TIMEH), line:194
|vpiName:TIMEH
|INT:3201
|vpiTypedef:
\_struct_typespec: (data_access_shared_inputs_t), line:427
|vpiPacked:1
|vpiName:data_access_shared_inputs_t
|vpiTypespecMember:
\_typespec_member: (addr), line:428
|vpiName:addr
|vpiTypespec:
\_logic_typespec: , line:428
|vpiRange:
\_range: , line:428, parent:data_access_shared_inputs_t
|vpiLeftRange:
\_constant: , line:428
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:428
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiTypespecMember:
\_typespec_member: (load), line:429
|vpiName:load
|vpiTypespec:
\_logic_typespec: , line:429
|vpiTypespecMember:
\_typespec_member: (store), line:430
|vpiName:store
|vpiTypespec:
\_logic_typespec: , line:430
|vpiTypespecMember:
\_typespec_member: (be), line:431
|vpiName:be
|vpiTypespec:
\_logic_typespec: , line:431
|vpiRange:
\_range: , line:431, parent:data_access_shared_inputs_t
|vpiLeftRange:
\_constant: , line:431
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiRightRange:
\_constant: , line:431
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiTypespecMember:
\_typespec_member: (fn3), line:432
|vpiName:fn3
|vpiTypespec:
\_logic_typespec: , line:432
|vpiRange:
\_range: , line:432, parent:data_access_shared_inputs_t
|vpiLeftRange:
\_constant: , line:432
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiRightRange:
\_constant: , line:432
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiTypespecMember:
\_typespec_member: (data_in), line:433
|vpiName:data_in
|vpiTypespec:
\_logic_typespec: , line:433
|vpiRange:
\_range: , line:433, parent:data_access_shared_inputs_t
|vpiLeftRange:
\_constant: , line:433
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:433
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiTypedef:
\_struct_typespec: (div_inputs_t), line:389
|vpiPacked:1
|vpiName:div_inputs_t
|vpiTypespecMember:
\_typespec_member: (rs1), line:390
|vpiName:rs1
|vpiTypespec:
\_logic_typespec: , line:390
|vpiRange:
\_range: , line:390, parent:div_inputs_t
|vpiLeftRange:
\_constant: , line:390
|vpiDecompile:31
|INT:31
|vpiRightRange:
\_constant: , line:390
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiTypespecMember:
\_typespec_member: (rs2), line:391
|vpiName:rs2
|vpiTypespec:
\_logic_typespec: , line:391
|vpiRange:
\_range: , line:391, parent:div_inputs_t
|vpiLeftRange:
\_constant: , line:391
|vpiDecompile:31
|INT:31
|vpiRightRange:
\_constant: , line:391
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiTypespecMember:
\_typespec_member: (op), line:392
|vpiName:op
|vpiTypespec:
\_logic_typespec: , line:392
|vpiRange:
\_range: , line:392, parent:div_inputs_t
|vpiLeftRange:
\_constant: , line:392
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:392
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiTypespecMember:
\_typespec_member: (reuse_result), line:393
|vpiName:reuse_result
|vpiTypespec:
\_logic_typespec: , line:393
|vpiTypedef:
\_enum_typespec: (div_type), line:66
|vpiTypedef:
\_enum_typespec: (exception_code_t), line:245
|vpiName:exception_code_t
|vpiBaseTypespec:
\_bit_typespec: , line:227
|vpiRange:
\_range: , line:227
|vpiLeftRange:
\_constant: , line:227
|vpiDecompile:4
|INT:4
|vpiRightRange:
\_constant: , line:227
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiEnumConst:
\_enum_const: (BREAK), line:231
|vpiName:BREAK
|INT:3
|vpiEnumConst:
\_enum_const: (ECALL_M), line:239
|vpiName:ECALL_M
|INT:11
|vpiEnumConst:
\_enum_const: (ECALL_S), line:237
|vpiName:ECALL_S
|INT:9
|vpiEnumConst:
\_enum_const: (ECALL_U), line:236
|vpiName:ECALL_U
|INT:8
|vpiEnumConst:
\_enum_const: (ILLEGAL_INST), line:230
|vpiName:ILLEGAL_INST
|INT:2
|vpiEnumConst:
\_enum_const: (INST_ACCESS_FAULT), line:229
|vpiName:INST_ACCESS_FAULT
|INT:1
|vpiEnumConst:
\_enum_const: (INST_ADDR_MISSALIGNED), line:228
|vpiName:INST_ADDR_MISSALIGNED
|INT:0
|vpiEnumConst:
\_enum_const: (INST_PAGE_FAULT), line:240
|vpiName:INST_PAGE_FAULT
|INT:12
|vpiEnumConst:
\_enum_const: (LOAD_ADDR_MISSALIGNED), line:232
|vpiName:LOAD_ADDR_MISSALIGNED
|INT:4
|vpiEnumConst:
\_enum_const: (LOAD_FAULT), line:233
|vpiName:LOAD_FAULT
|INT:5
|vpiEnumConst:
\_enum_const: (LOAD_PAGE_FAULT), line:241
|vpiName:LOAD_PAGE_FAULT
|INT:13
|vpiEnumConst:
\_enum_const: (STORE_AMO_ADDR_MISSALIGNED), line:234
|vpiName:STORE_AMO_ADDR_MISSALIGNED
|INT:6
|vpiEnumConst:
\_enum_const: (STORE_AMO_FAULT), line:235
|vpiName:STORE_AMO_FAULT
|INT:7
|vpiEnumConst:
\_enum_const: (STORE_OR_AMO_PAGE_FAULT), line:243
|vpiName:STORE_OR_AMO_PAGE_FAULT
|INT:15
|vpiTypedef:
\_struct_typespec: (exception_packet_t), line:263
|vpiPacked:1
|vpiName:exception_packet_t
|vpiTypespecMember:
\_typespec_member: (valid), line:264
|vpiName:valid
|vpiTypespec:
\_logic_typespec: , line:264
|vpiTypespecMember:
\_typespec_member: (code), line:265
|vpiName:code
|vpiTypespec:
\_enum_typespec: (exception_code_t), line:245
|vpiTypespecMember:
\_typespec_member: (pc), line:266
|vpiName:pc
|vpiTypespec:
\_logic_typespec: , line:266
|vpiRange:
\_range: , line:266, parent:exception_packet_t
|vpiLeftRange:
\_constant: , line:266
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:266
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiTypespecMember:
\_typespec_member: (tval), line:267
|vpiName:tval
|vpiTypespec:
\_logic_typespec: , line:267
|vpiRange:
\_range: , line:267, parent:exception_packet_t
|vpiLeftRange:
\_constant: , line:267
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:267
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiTypespecMember:
\_typespec_member: (id), line:268
|vpiName:id
|vpiTypespec:
\_logic_typespec: (instruction_id_t), line:30
|vpiName:instruction_id_t
|vpiRange:
\_range: , line:30
|vpiLeftRange:
\_operation: , line:30
|vpiOpType:11
|vpiOperand:
\_sys_func_call: ($clog2), line:30
|vpiName:$clog2
|vpiArgument:
\_ref_obj: (MAX_INFLIGHT_COUNT), line:30
|vpiName:MAX_INFLIGHT_COUNT
|vpiOperand:
\_constant: , line:30
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:30
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiTypedef:
\_struct_typespec: (fetch_buffer_packet_t), line:276
|vpiPacked:1
|vpiName:fetch_buffer_packet_t
|vpiTypespecMember:
\_typespec_member: (instruction), line:277
|vpiName:instruction
|vpiTypespec:
\_logic_typespec: , line:277
|vpiRange:
\_range: , line:277, parent:fetch_buffer_packet_t
|vpiLeftRange:
\_constant: , line:277
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:277
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiTypespecMember:
\_typespec_member: (pc), line:278
|vpiName:pc
|vpiTypespec:
\_logic_typespec: , line:278
|vpiRange:
\_range: , line:278, parent:fetch_buffer_packet_t
|vpiLeftRange:
\_constant: , line:278
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:278
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiTypespecMember:
\_typespec_member: (uses_rs1), line:279
|vpiName:uses_rs1
|vpiTypespec:
\_logic_typespec: , line:279
|vpiTypespecMember:
\_typespec_member: (uses_rs2), line:280
|vpiName:uses_rs2
|vpiTypespec:
\_logic_typespec: , line:280
|vpiTypespecMember:
\_typespec_member: (uses_rd), line:281
|vpiName:uses_rd
|vpiTypespec:
\_logic_typespec: , line:281
|vpiTypespecMember:
\_typespec_member: (is_call), line:282
|vpiName:is_call
|vpiTypespec:
\_logic_typespec: , line:282
|vpiTypespecMember:
\_typespec_member: (is_return), line:283
|vpiName:is_return
|vpiTypespec:
\_logic_typespec: , line:283
|vpiTypespecMember:
\_typespec_member: (branch_metadata), line:284
|vpiName:branch_metadata
|vpiTypespec:
\_logic_typespec: (branch_predictor_metadata_t), line:32
|vpiTypespecMember:
\_typespec_member: (branch_prediction_used), line:285
|vpiName:branch_prediction_used
|vpiTypespec:
\_logic_typespec: , line:285
|vpiTypespecMember:
\_typespec_member: (bp_update_way), line:286
|vpiName:bp_update_way
|vpiTypespec:
\_logic_typespec: , line:286
|vpiRange:
\_range: , line:286, parent:fetch_buffer_packet_t
|vpiLeftRange:
\_operation: , line:286
|vpiOpType:11
|vpiOperand:
\_ref_obj: (BRANCH_PREDICTOR_WAYS), line:286, parent:fetch_buffer_packet_t
|vpiName:BRANCH_PREDICTOR_WAYS
|vpiFullName:fetch_buffer_packet_t.BRANCH_PREDICTOR_WAYS
|vpiOperand:
\_constant: , line:286
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:286
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiTypespecMember:
\_typespec_member: (alu_sub), line:287
|vpiName:alu_sub
|vpiTypespec:
\_logic_typespec: , line:287
|vpiTypespecMember:
\_typespec_member: (alu_logic_op), line:288
|vpiName:alu_logic_op
|vpiTypespec:
\_logic_typespec: , line:288
|vpiRange:
\_range: , line:288, parent:fetch_buffer_packet_t
|vpiLeftRange:
\_constant: , line:288
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:288
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiTypespecMember:
\_typespec_member: (alu_op), line:289
|vpiName:alu_op
|vpiTypespec:
\_logic_typespec: , line:289
|vpiRange:
\_range: , line:289, parent:fetch_buffer_packet_t
|vpiLeftRange:
\_constant: , line:289
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:289
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiTypespecMember:
\_typespec_member: (alu_request), line:290
|vpiName:alu_request
|vpiTypespec:
\_logic_typespec: , line:290
|vpiTypespecMember:
\_typespec_member: (alu_rs1_sel), line:291
|vpiName:alu_rs1_sel
|vpiTypespec:
\_enum_typespec: (alu_rs1_op_t), line:97
|vpiTypespecMember:
\_typespec_member: (alu_rs2_sel), line:292
|vpiName:alu_rs2_sel
|vpiTypespec:
\_enum_typespec: (alu_rs2_op_t), line:104
|vpiTypedef:
\_enum_typespec: (fifo_type_t), line:440
|vpiName:fifo_type_t
|vpiEnumConst:
\_enum_const: (LUTRAM_FIFO), line:437
|vpiName:LUTRAM_FIFO
|INT:0
|vpiEnumConst:
\_enum_const: (NON_MUXED_INPUT_FIFO), line:438
|vpiName:NON_MUXED_INPUT_FIFO
|INT:1
|vpiEnumConst:
\_enum_const: (NON_MUXED_OUTPUT_FIFO), line:439
|vpiName:NON_MUXED_OUTPUT_FIFO
|INT:2
|vpiTypedef:
\_enum_typespec: (fn3_arith_t), line:76
|vpiName:fn3_arith_t
|vpiBaseTypespec:
\_bit_typespec: , line:67
|vpiRange:
\_range: , line:67
|vpiLeftRange:
\_constant: , line:67
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiRightRange:
\_constant: , line:67
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiEnumConst:
\_enum_const: (ADD_SUB_fn3), line:68
|vpiName:ADD_SUB_fn3
|INT:0
|vpiEnumConst:
\_enum_const: (AND_fn3), line:75
|vpiName:AND_fn3
|INT:7
|vpiEnumConst:
\_enum_const: (OR_fn3), line:73
|vpiName:OR_fn3
|INT:6
|vpiEnumConst:
\_enum_const: (SLL_fn3), line:69
|vpiName:SLL_fn3
|INT:1
|vpiEnumConst:
\_enum_const: (SLTU_fn3), line:71
|vpiName:SLTU_fn3
|INT:3
|vpiEnumConst:
\_enum_const: (SLT_fn3), line:70
|vpiName:SLT_fn3
|INT:2
|vpiEnumConst:
\_enum_const: (SRA_fn3), line:74
|vpiName:SRA_fn3
|INT:5
|vpiEnumConst:
\_enum_const: (XOR_fn3), line:72
|vpiName:XOR_fn3
|INT:4
|vpiTypedef:
\_enum_typespec: (fn3_branch_t), line:126
|vpiName:fn3_branch_t
|vpiBaseTypespec:
\_bit_typespec: , line:117
|vpiRange:
\_range: , line:117
|vpiLeftRange:
\_constant: , line:117
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiRightRange:
\_constant: , line:117
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiEnumConst:
\_enum_const: (BEQ_fn3), line:118
|vpiName:BEQ_fn3
|INT:0
|vpiEnumConst:
\_enum_const: (BGEU_fn3), line:125
|vpiName:BGEU_fn3
|INT:7
|vpiEnumConst:
\_enum_const: (BGE_fn3), line:123
|vpiName:BGE_fn3
|INT:5
|vpiEnumConst:
\_enum_const: (BLTU_fn3), line:124
|vpiName:BLTU_fn3
|INT:6
|vpiEnumConst:
\_enum_const: (BLT_fn3), line:122
|vpiName:BLT_fn3
|INT:4
|vpiEnumConst:
\_enum_const: (BNE_fn3), line:119
|vpiName:BNE_fn3
|INT:1
|vpiTypedef:
\_enum_typespec: (fn3_csr_t), line:212
|vpiName:fn3_csr_t
|vpiBaseTypespec:
\_bit_typespec: , line:203
|vpiRange:
\_range: , line:203
|vpiLeftRange:
\_constant: , line:203
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiRightRange:
\_constant: , line:203
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiEnumConst:
\_enum_const: (NONCSR_fn3), line:204
|vpiName:NONCSR_fn3
|INT:0
|vpiEnumConst:
\_enum_const: (RCI_fn3), line:211
|vpiName:RCI_fn3
|INT:7
|vpiEnumConst:
\_enum_const: (RC_fn3), line:207
|vpiName:RC_fn3
|INT:3
|vpiEnumConst:
\_enum_const: (RSI_fn3), line:210
|vpiName:RSI_fn3
|INT:6
|vpiEnumConst:
\_enum_const: (RS_fn3), line:206
|vpiName:RS_fn3
|INT:2
|vpiEnumConst:
\_enum_const: (RWI_fn3), line:209
|vpiName:RWI_fn3
|INT:5
|vpiEnumConst:
\_enum_const: (RW_fn3), line:205
|vpiName:RW_fn3
|INT:1
|vpiTypedef:
\_enum_typespec: (fn3_ls_t), line:115
|vpiName:fn3_ls_t
|vpiBaseTypespec:
\_bit_typespec: , line:106
|vpiRange:
\_range: , line:106
|vpiLeftRange:
\_constant: , line:106
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiRightRange:
\_constant: , line:106
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiEnumConst:
\_enum_const: (LS_B_fn3), line:107
|vpiName:LS_B_fn3
|INT:0
|vpiEnumConst:
\_enum_const: (LS_H_fn3), line:108
|vpiName:LS_H_fn3
|INT:1
|vpiEnumConst:
\_enum_const: (LS_W_fn3), line:109
|vpiName:LS_W_fn3
|INT:2
|vpiEnumConst:
\_enum_const: (L_BU_fn3), line:111
|vpiName:L_BU_fn3
|INT:4
|vpiEnumConst:
\_enum_const: (L_HU_fn3), line:112
|vpiName:L_HU_fn3
|INT:5
|vpiTypedef:
\_enum_typespec: (fn3_mul_div_t), line:138
|vpiName:fn3_mul_div_t
|vpiBaseTypespec:
\_bit_typespec: , line:129
|vpiRange:
\_range: , line:129
|vpiLeftRange:
\_constant: , line:129
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiRightRange:
\_constant: , line:129
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiEnumConst:
\_enum_const: (DIVU_fn3), line:135
|vpiName:DIVU_fn3
|INT:5
|vpiEnumConst:
\_enum_const: (DIV_fn3), line:134
|vpiName:DIV_fn3
|INT:4
|vpiEnumConst:
\_enum_const: (MULHSU_fn3), line:132
|vpiName:MULHSU_fn3
|INT:2
|vpiEnumConst:
\_enum_const: (MULHU_fn3), line:133
|vpiName:MULHU_fn3
|INT:3
|vpiEnumConst:
\_enum_const: (MULH_fn3), line:131
|vpiName:MULH_fn3
|INT:1
|vpiEnumConst:
\_enum_const: (MUL_fn3), line:130
|vpiName:MUL_fn3
|INT:0
|vpiEnumConst:
\_enum_const: (REMU_fn3), line:137
|vpiName:REMU_fn3
|INT:7
|vpiEnumConst:
\_enum_const: (REM_fn3), line:136
|vpiName:REM_fn3
|INT:6
|vpiTypedef:
\_struct_typespec: (gc_inputs_t), line:404
|vpiPacked:1
|vpiName:gc_inputs_t
|vpiTypespecMember:
\_typespec_member: (pc), line:405
|vpiName:pc
|vpiTypespec:
\_logic_typespec: , line:405
|vpiRange:
\_range: , line:405, parent:gc_inputs_t
|vpiLeftRange:
\_constant: , line:405
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:405
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiTypespecMember:
\_typespec_member: (instruction), line:406
|vpiName:instruction
|vpiTypespec:
\_logic_typespec: , line:406
|vpiRange:
\_range: , line:406, parent:gc_inputs_t
|vpiLeftRange:
\_constant: , line:406
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:406
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiTypespecMember:
\_typespec_member: (rs1), line:407
|vpiName:rs1
|vpiTypespec:
\_logic_typespec: , line:407
|vpiRange:
\_range: , line:407, parent:gc_inputs_t
|vpiLeftRange:
\_constant: , line:407
|vpiDecompile:31
|INT:31
|vpiRightRange:
\_constant: , line:407
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiTypespecMember:
\_typespec_member: (rs2), line:408
|vpiName:rs2
|vpiTypespec:
\_logic_typespec: , line:408
|vpiRange:
\_range: , line:408, parent:gc_inputs_t
|vpiLeftRange:
\_constant: , line:408
|vpiDecompile:31
|INT:31
|vpiRightRange:
\_constant: , line:408
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiTypespecMember:
\_typespec_member: (rd_is_zero), line:409
|vpiName:rd_is_zero
|vpiTypespec:
\_logic_typespec: , line:409
|vpiTypespecMember:
\_typespec_member: (is_csr), line:410
|vpiName:is_csr
|vpiTypespec:
\_logic_typespec: , line:410
|vpiTypespecMember:
\_typespec_member: (is_fence), line:411
|vpiName:is_fence
|vpiTypespec:
\_logic_typespec: , line:411
|vpiTypespecMember:
\_typespec_member: (is_i_fence), line:412
|vpiName:is_i_fence
|vpiTypespec:
\_logic_typespec: , line:412
|vpiTypespecMember:
\_typespec_member: (is_ecall), line:413
|vpiName:is_ecall
|vpiTypespec:
\_logic_typespec: , line:413
|vpiTypespecMember:
\_typespec_member: (is_ebreak), line:414
|vpiName:is_ebreak
|vpiTypespec:
\_logic_typespec: , line:414
|vpiTypespecMember:
\_typespec_member: (is_ret), line:415
|vpiName:is_ret
|vpiTypespec:
\_logic_typespec: , line:415
|vpiTypedef:
\_struct_typespec: (inflight_instruction_packet), line:271
|vpiPacked:1
|vpiName:inflight_instruction_packet
|vpiTypespecMember:
\_typespec_member: (rd_addr), line:272
|vpiName:rd_addr
|vpiTypespec:
\_logic_typespec: , line:272
|vpiRange:
\_range: , line:272, parent:inflight_instruction_packet
|vpiLeftRange:
\_constant: , line:272
|vpiConstType:7
|vpiDecompile:4
|vpiSize:32
|INT:4
|vpiRightRange:
\_constant: , line:272
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiTypespecMember:
\_typespec_member: (is_store), line:273
|vpiName:is_store
|vpiTypespec:
\_logic_typespec: , line:273
|vpiTypedef:
\_logic_typespec: (instruction_id_t), line:30
|vpiTypedef:
\_enum_typespec: (interrupt_code_t), line:261
|vpiName:interrupt_code_t
|vpiBaseTypespec:
\_bit_typespec: , line:248
|vpiRange:
\_range: , line:248
|vpiLeftRange:
\_constant: , line:248
|vpiDecompile:4
|INT:4
|vpiRightRange:
\_constant: , line:248
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiEnumConst:
\_enum_const: (M_EXTERNAL_INTERRUPT), line:260
|vpiName:M_EXTERNAL_INTERRUPT
|INT:11
|vpiEnumConst:
\_enum_const: (M_SOFTWARE_INTERRUPT), line:252
|vpiName:M_SOFTWARE_INTERRUPT
|INT:3
|vpiEnumConst:
\_enum_const: (M_TIMER_INTERRUPT), line:256
|vpiName:M_TIMER_INTERRUPT
|INT:7
|vpiEnumConst:
\_enum_const: (S_EXTERNAL_INTERRUPT), line:258
|vpiName:S_EXTERNAL_INTERRUPT
|INT:9
|vpiEnumConst:
\_enum_const: (S_SOFTWARE_INTERRUPT), line:250
|vpiName:S_SOFTWARE_INTERRUPT
|INT:1
|vpiEnumConst:
\_enum_const: (S_TIMER_INTERRUPT), line:254
|vpiName:S_TIMER_INTERRUPT
|INT:5
|vpiEnumConst:
\_enum_const: (U_EXTERNAL_INTERRUPT), line:257
|vpiName:U_EXTERNAL_INTERRUPT
|INT:8
|vpiEnumConst:
\_enum_const: (U_SOFTWARE_INTERRUPT), line:249
|vpiName:U_SOFTWARE_INTERRUPT
|INT:0
|vpiEnumConst:
\_enum_const: (U_TIMER_INTERRUPT), line:253
|vpiName:U_TIMER_INTERRUPT
|INT:4
|vpiTypedef:
\_struct_typespec: (load_store_inputs_t), line:369
|vpiPacked:1
|vpiName:load_store_inputs_t
|vpiTypespecMember:
\_typespec_member: (rs1), line:370
|vpiName:rs1
|vpiTypespec:
\_logic_typespec: , line:370
|vpiRange:
\_range: , line:370, parent:load_store_inputs_t
|vpiLeftRange:
\_constant: , line:370
|vpiDecompile:31
|INT:31
|vpiRightRange:
\_constant: , line:370
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiTypespecMember:
\_typespec_member: (offset), line:371
|vpiName:offset
|vpiTypespec:
\_logic_typespec: , line:371
|vpiRange:
\_range: , line:371, parent:load_store_inputs_t
|vpiLeftRange:
\_constant: , line:371
|vpiConstType:7
|vpiDecompile:11
|vpiSize:32
|INT:11
|vpiRightRange:
\_constant: , line:371
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiTypespecMember:
\_typespec_member: (fn3), line:372
|vpiName:fn3
|vpiTypespec:
\_logic_typespec: , line:372
|vpiRange:
\_range: , line:372, parent:load_store_inputs_t
|vpiLeftRange:
\_constant: , line:372
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiRightRange:
\_constant: , line:372
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiTypespecMember:
\_typespec_member: (load), line:373
|vpiName:load
|vpiTypespec:
\_logic_typespec: , line:373
|vpiTypespecMember:
\_typespec_member: (store), line:374
|vpiName:store
|vpiTypespec:
\_logic_typespec: , line:374
|vpiTypespecMember:
\_typespec_member: (load_store_forward), line:375
|vpiName:load_store_forward
|vpiTypespec:
\_logic_typespec: , line:375
|vpiTypespecMember:
\_typespec_member: (store_forward_id), line:376
|vpiName:store_forward_id
|vpiTypespec:
\_logic_typespec: (instruction_id_t), line:30
|vpiTypespecMember:
\_typespec_member: (pc), line:378
|vpiName:pc
|vpiTypespec:
\_logic_typespec: , line:378
|vpiRange:
\_range: , line:378, parent:load_store_inputs_t
|vpiLeftRange:
\_constant: , line:378
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:378
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiTypespecMember:
\_typespec_member: (amo), line:380
|vpiName:amo
|vpiTypespec:
\_struct_typespec: (amo_details_t), line:362
|vpiTypedef:
\_struct_typespec: (mul_inputs_t), line:383
|vpiPacked:1
|vpiName:mul_inputs_t
|vpiTypespecMember:
\_typespec_member: (rs1), line:384
|vpiName:rs1
|vpiTypespec:
\_logic_typespec: , line:384
|vpiRange:
\_range: , line:384, parent:mul_inputs_t
|vpiLeftRange:
\_constant: , line:384
|vpiDecompile:31
|INT:31
|vpiRightRange:
\_constant: , line:384
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiTypespecMember:
\_typespec_member: (rs2), line:385
|vpiName:rs2
|vpiTypespec:
\_logic_typespec: , line:385
|vpiRange:
\_range: , line:385, parent:mul_inputs_t
|vpiLeftRange:
\_constant: , line:385
|vpiDecompile:31
|INT:31
|vpiRightRange:
\_constant: , line:385
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiTypespecMember:
\_typespec_member: (op), line:386
|vpiName:op
|vpiTypespec:
\_logic_typespec: , line:386
|vpiRange:
\_range: , line:386, parent:mul_inputs_t
|vpiLeftRange:
\_constant: , line:386
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:386
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiTypedef:
\_enum_typespec: (opcodes_t), line:48
|vpiName:opcodes_t
|vpiBaseTypespec:
\_bit_typespec: , line:34
|vpiRange:
\_range: , line:34
|vpiLeftRange:
\_constant: , line:34
|vpiConstType:7
|vpiDecompile:6
|vpiSize:32
|INT:6
|vpiRightRange:
\_constant: , line:34
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiEnumConst:
\_enum_const: (AMO), line:45
|vpiName:AMO
|INT:47
|vpiEnumConst:
\_enum_const: (ARITH), line:43
|vpiName:ARITH
|INT:51
|vpiEnumConst:
\_enum_const: (ARITH_IMM), line:42
|vpiName:ARITH_IMM
|INT:19
|vpiEnumConst:
\_enum_const: (AUIPC), line:36
|vpiName:AUIPC
|INT:23
|vpiEnumConst:
\_enum_const: (BRANCH), line:39
|vpiName:BRANCH
|INT:99
|vpiEnumConst:
\_enum_const: (FENCE), line:44
|vpiName:FENCE
|INT:15
|vpiEnumConst:
\_enum_const: (JAL), line:37
|vpiName:JAL
|INT:111
|vpiEnumConst:
\_enum_const: (JALR), line:38
|vpiName:JALR
|INT:103
|vpiEnumConst:
\_enum_const: (LOAD), line:40
|vpiName:LOAD
|INT:3
|vpiEnumConst:
\_enum_const: (LUI), line:35
|vpiName:LUI
|INT:55
|vpiEnumConst:
\_enum_const: (STORE), line:41
|vpiName:STORE
|INT:35
|vpiEnumConst:
\_enum_const: (SYSTEM), line:46
|vpiName:SYSTEM
|INT:115
|vpiTypedef:
\_enum_typespec: (opcodes_trimmed_t), line:65
|vpiName:opcodes_trimmed_t
|vpiBaseTypespec:
\_bit_typespec: , line:50
|vpiRange:
\_range: , line:50
|vpiLeftRange:
\_constant: , line:50
|vpiConstType:7
|vpiDecompile:4
|vpiSize:32
|INT:4
|vpiRightRange:
\_constant: , line:50
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiEnumConst:
\_enum_const: (AMO_T), line:61
|vpiName:AMO_T
|INT:11
|vpiEnumConst:
\_enum_const: (ARITH_IMM_T), line:58
|vpiName:ARITH_IMM_T
|INT:4
|vpiEnumConst:
\_enum_const: (ARITH_T), line:59
|vpiName:ARITH_T
|INT:12
|vpiEnumConst:
\_enum_const: (AUIPC_T), line:52
|vpiName:AUIPC_T
|INT:5
|vpiEnumConst:
\_enum_const: (BRANCH_T), line:55
|vpiName:BRANCH_T
|INT:24
|vpiEnumConst:
\_enum_const: (CUSTOM_T), line:64
|vpiName:CUSTOM_T
|INT:30
|vpiEnumConst:
\_enum_const: (FENCE_T), line:60
|vpiName:FENCE_T
|INT:3
|vpiEnumConst:
\_enum_const: (JALR_T), line:54
|vpiName:JALR_T
|INT:25
|vpiEnumConst:
\_enum_const: (JAL_T), line:53
|vpiName:JAL_T
|INT:27
|vpiEnumConst:
\_enum_const: (LOAD_T), line:56
|vpiName:LOAD_T
|INT:0
|vpiEnumConst:
\_enum_const: (LUI_T), line:51
|vpiName:LUI_T
|INT:13
|vpiEnumConst:
\_enum_const: (STORE_T), line:57
|vpiName:STORE_T
|INT:8
|vpiEnumConst:
\_enum_const: (SYSTEM_T), line:62
|vpiName:SYSTEM_T
|INT:28
|vpiTypedef:
\_struct_typespec: (simulation_named_regfile), line:476
|vpiPacked:1
|vpiName:simulation_named_regfile
|vpiTypespecMember:
\_typespec_member: (zero), line:477
|vpiName:zero
|vpiTypespec:
\_logic_typespec: , line:477
|vpiRange:
\_range: , line:477, parent:simulation_named_regfile
|vpiLeftRange:
\_constant: , line:477
|vpiDecompile:31
|INT:31
|vpiRightRange:
\_constant: , line:477
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiTypespecMember:
\_typespec_member: (ra), line:478
|vpiName:ra
|vpiTypespec:
\_logic_typespec: , line:478
|vpiRange:
\_range: , line:478, parent:simulation_named_regfile
|vpiLeftRange:
\_constant: , line:478
|vpiDecompile:31
|INT:31
|vpiRightRange:
\_constant: , line:478
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiTypespecMember:
\_typespec_member: (sp), line:479
|vpiName:sp
|vpiTypespec:
\_logic_typespec: , line:479
|vpiRange:
\_range: , line:479, parent:simulation_named_regfile
|vpiLeftRange:
\_constant: , line:479
|vpiDecompile:31
|INT:31
|vpiRightRange:
\_constant: , line:479
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiTypespecMember:
\_typespec_member: (gp), line:480
|vpiName:gp
|vpiTypespec:
\_logic_typespec: , line:480
|vpiRange:
\_range: , line:480, parent:simulation_named_regfile
|vpiLeftRange:
\_constant: , line:480
|vpiDecompile:31
|INT:31
|vpiRightRange:
\_constant: , line:480
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiTypespecMember:
\_typespec_member: (tp), line:481
|vpiName:tp
|vpiTypespec:
\_logic_typespec: , line:481
|vpiRange:
\_range: , line:481, parent:simulation_named_regfile
|vpiLeftRange:
\_constant: , line:481
|vpiDecompile:31
|INT:31
|vpiRightRange:
\_constant: , line:481
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiTypespecMember:
\_typespec_member: (t0), line:482
|vpiName:t0
|vpiTypespec:
\_logic_typespec: , line:482
|vpiRange:
\_range: , line:482, parent:simulation_named_regfile
|vpiLeftRange:
\_constant: , line:482
|vpiDecompile:31
|INT:31
|vpiRightRange:
\_constant: , line:482
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiTypespecMember:
\_typespec_member: (t1), line:483
|vpiName:t1
|vpiTypespec:
\_logic_typespec: , line:483
|vpiRange:
\_range: , line:483, parent:simulation_named_regfile
|vpiLeftRange:
\_constant: , line:483
|vpiDecompile:31
|INT:31
|vpiRightRange:
\_constant: , line:483
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiTypespecMember:
\_typespec_member: (t2), line:484
|vpiName:t2
|vpiTypespec:
\_logic_typespec: , line:484
|vpiRange:
\_range: , line:484, parent:simulation_named_regfile
|vpiLeftRange:
\_constant: , line:484
|vpiDecompile:31
|INT:31
|vpiRightRange:
\_constant: , line:484
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiTypespecMember:
\_typespec_member: (s0_fp), line:485
|vpiName:s0_fp
|vpiTypespec:
\_logic_typespec: , line:485
|vpiRange:
\_range: , line:485, parent:simulation_named_regfile
|vpiLeftRange:
\_constant: , line:485
|vpiDecompile:31
|INT:31
|vpiRightRange:
\_constant: , line:485
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiTypespecMember:
\_typespec_member: (s1), line:486
|vpiName:s1
|vpiTypespec:
\_logic_typespec: , line:486
|vpiRange:
\_range: , line:486, parent:simulation_named_regfile
|vpiLeftRange:
\_constant: , line:486
|vpiDecompile:31
|INT:31
|vpiRightRange:
\_constant: , line:486
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiTypespecMember:
\_typespec_member: (a0), line:487
|vpiName:a0
|vpiTypespec:
\_logic_typespec: , line:487
|vpiRange:
\_range: , line:487, parent:simulation_named_regfile
|vpiLeftRange:
\_constant: , line:487
|vpiDecompile:31
|INT:31
|vpiRightRange:
\_constant: , line:487
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiTypespecMember:
\_typespec_member: (a1), line:488
|vpiName:a1
|vpiTypespec:
\_logic_typespec: , line:488
|vpiRange:
\_range: , line:488, parent:simulation_named_regfile
|vpiLeftRange:
\_constant: , line:488
|vpiDecompile:31
|INT:31
|vpiRightRange:
\_constant: , line:488
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiTypespecMember:
\_typespec_member: (a2), line:489
|vpiName:a2
|vpiTypespec:
\_logic_typespec: , line:489
|vpiRange:
\_range: , line:489, parent:simulation_named_regfile
|vpiLeftRange:
\_constant: , line:489
|vpiDecompile:31
|INT:31
|vpiRightRange:
\_constant: , line:489
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiTypespecMember:
\_typespec_member: (a3), line:490
|vpiName:a3
|vpiTypespec:
\_logic_typespec: , line:490
|vpiRange:
\_range: , line:490, parent:simulation_named_regfile
|vpiLeftRange:
\_constant: , line:490
|vpiDecompile:31
|INT:31
|vpiRightRange:
\_constant: , line:490
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiTypespecMember:
\_typespec_member: (a4), line:491
|vpiName:a4
|vpiTypespec:
\_logic_typespec: , line:491
|vpiRange:
\_range: , line:491, parent:simulation_named_regfile
|vpiLeftRange:
\_constant: , line:491
|vpiDecompile:31
|INT:31
|vpiRightRange:
\_constant: , line:491
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiTypespecMember:
\_typespec_member: (a5), line:492
|vpiName:a5
|vpiTypespec:
\_logic_typespec: , line:492
|vpiRange:
\_range: , line:492, parent:simulation_named_regfile
|vpiLeftRange:
\_constant: , line:492
|vpiDecompile:31
|INT:31
|vpiRightRange:
\_constant: , line:492
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiTypespecMember:
\_typespec_member: (a6), line:493
|vpiName:a6
|vpiTypespec:
\_logic_typespec: , line:493
|vpiRange:
\_range: , line:493, parent:simulation_named_regfile
|vpiLeftRange:
\_constant: , line:493
|vpiDecompile:31
|INT:31
|vpiRightRange:
\_constant: , line:493
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiTypespecMember:
\_typespec_member: (a7), line:494
|vpiName:a7
|vpiTypespec:
\_logic_typespec: , line:494
|vpiRange:
\_range: , line:494, parent:simulation_named_regfile
|vpiLeftRange:
\_constant: , line:494
|vpiDecompile:31
|INT:31
|vpiRightRange:
\_constant: , line:494
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiTypespecMember:
\_typespec_member: (s2), line:495
|vpiName:s2
|vpiTypespec:
\_logic_typespec: , line:495
|vpiRange:
\_range: , line:495, parent:simulation_named_regfile
|vpiLeftRange:
\_constant: , line:495
|vpiDecompile:31
|INT:31
|vpiRightRange:
\_constant: , line:495
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiTypespecMember:
\_typespec_member: (s3), line:496
|vpiName:s3
|vpiTypespec:
\_logic_typespec: , line:496
|vpiRange:
\_range: , line:496, parent:simulation_named_regfile
|vpiLeftRange:
\_constant: , line:496
|vpiDecompile:31
|INT:31
|vpiRightRange:
\_constant: , line:496
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiTypespecMember:
\_typespec_member: (s4), line:497
|vpiName:s4
|vpiTypespec:
\_logic_typespec: , line:497
|vpiRange:
\_range: , line:497, parent:simulation_named_regfile
|vpiLeftRange:
\_constant: , line:497
|vpiDecompile:31
|INT:31
|vpiRightRange:
\_constant: , line:497
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiTypespecMember:
\_typespec_member: (s5), line:498
|vpiName:s5
|vpiTypespec:
\_logic_typespec: , line:498
|vpiRange:
\_range: , line:498, parent:simulation_named_regfile
|vpiLeftRange:
\_constant: , line:498
|vpiDecompile:31
|INT:31
|vpiRightRange:
\_constant: , line:498
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiTypespecMember:
\_typespec_member: (s6), line:499
|vpiName:s6
|vpiTypespec:
\_logic_typespec: , line:499
|vpiRange:
\_range: , line:499, parent:simulation_named_regfile
|vpiLeftRange:
\_constant: , line:499
|vpiDecompile:31
|INT:31
|vpiRightRange:
\_constant: , line:499
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiTypespecMember:
\_typespec_member: (s7), line:500
|vpiName:s7
|vpiTypespec:
\_logic_typespec: , line:500
|vpiRange:
\_range: , line:500, parent:simulation_named_regfile
|vpiLeftRange:
\_constant: , line:500
|vpiDecompile:31
|INT:31
|vpiRightRange:
\_constant: , line:500
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiTypespecMember:
\_typespec_member: (s8), line:501
|vpiName:s8
|vpiTypespec:
\_logic_typespec: , line:501
|vpiRange:
\_range: , line:501, parent:simulation_named_regfile
|vpiLeftRange:
\_constant: , line:501
|vpiDecompile:31
|INT:31
|vpiRightRange:
\_constant: , line:501
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiTypespecMember:
\_typespec_member: (s9), line:502
|vpiName:s9
|vpiTypespec:
\_logic_typespec: , line:502
|vpiRange:
\_range: , line:502, parent:simulation_named_regfile
|vpiLeftRange:
\_constant: , line:502
|vpiDecompile:31
|INT:31
|vpiRightRange:
\_constant: , line:502
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiTypespecMember:
\_typespec_member: (s10), line:503
|vpiName:s10
|vpiTypespec:
\_logic_typespec: , line:503
|vpiRange:
\_range: , line:503, parent:simulation_named_regfile
|vpiLeftRange:
\_constant: , line:503
|vpiDecompile:31
|INT:31
|vpiRightRange:
\_constant: , line:503
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiTypespecMember:
\_typespec_member: (s11), line:504
|vpiName:s11
|vpiTypespec:
\_logic_typespec: , line:504
|vpiRange:
\_range: , line:504, parent:simulation_named_regfile
|vpiLeftRange:
\_constant: , line:504
|vpiDecompile:31
|INT:31
|vpiRightRange:
\_constant: , line:504
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiTypespecMember:
\_typespec_member: (t3), line:505
|vpiName:t3
|vpiTypespec:
\_logic_typespec: , line:505
|vpiRange:
\_range: , line:505, parent:simulation_named_regfile
|vpiLeftRange:
\_constant: , line:505
|vpiDecompile:31
|INT:31
|vpiRightRange:
\_constant: , line:505
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiTypespecMember:
\_typespec_member: (t4), line:506
|vpiName:t4
|vpiTypespec:
\_logic_typespec: , line:506
|vpiRange:
\_range: , line:506, parent:simulation_named_regfile
|vpiLeftRange:
\_constant: , line:506
|vpiDecompile:31
|INT:31
|vpiRightRange:
\_constant: , line:506
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiTypespecMember:
\_typespec_member: (t5), line:507
|vpiName:t5
|vpiTypespec:
\_logic_typespec: , line:507
|vpiRange:
\_range: , line:507, parent:simulation_named_regfile
|vpiLeftRange:
\_constant: , line:507
|vpiDecompile:31
|INT:31
|vpiRightRange:
\_constant: , line:507
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiTypespecMember:
\_typespec_member: (t6), line:508
|vpiName:t6
|vpiTypespec:
\_logic_typespec: , line:508
|vpiRange:
\_range: , line:508, parent:simulation_named_regfile
|vpiLeftRange:
\_constant: , line:508
|vpiDecompile:31
|INT:31
|vpiRightRange:
\_constant: , line:508
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiTypedef:
\_struct_typespec: (taiga_trace_events_t), line:442
|vpiPacked:1
|vpiName:taiga_trace_events_t
|vpiTypespecMember:
\_typespec_member: (operand_stall), line:444
|vpiName:operand_stall
|vpiTypespec:
\_logic_typespec: , line:444
|vpiTypespecMember:
\_typespec_member: (unit_stall), line:445
|vpiName:unit_stall
|vpiTypespec:
\_logic_typespec: , line:445
|vpiTypespecMember:
\_typespec_member: (no_id_stall), line:446
|vpiName:no_id_stall
|vpiTypespec:
\_logic_typespec: , line:446
|vpiTypespecMember:
\_typespec_member: (no_instruction_stall), line:447
|vpiName:no_instruction_stall
|vpiTypespec:
\_logic_typespec: , line:447
|vpiTypespecMember:
\_typespec_member: (other_stall), line:448
|vpiName:other_stall
|vpiTypespec:
\_logic_typespec: , line:448
|vpiTypespecMember:
\_typespec_member: (instruction_issued_dec), line:449
|vpiName:instruction_issued_dec
|vpiTypespec:
\_logic_typespec: , line:449
|vpiTypespecMember:
\_typespec_member: (branch_operand_stall), line:450
|vpiName:branch_operand_stall
|vpiTypespec:
\_logic_typespec: , line:450
|vpiTypespecMember:
\_typespec_member: (alu_operand_stall), line:451
|vpiName:alu_operand_stall
|vpiTypespec:
\_logic_typespec: , line:451
|vpiTypespecMember:
\_typespec_member: (ls_operand_stall), line:452
|vpiName:ls_operand_stall
|vpiTypespec:
\_logic_typespec: , line:452
|vpiTypespecMember:
\_typespec_member: (div_operand_stall), line:453
|vpiName:div_operand_stall
|vpiTypespec:
\_logic_typespec: , line:453
|vpiTypespecMember:
\_typespec_member: (branch_correct), line:456
|vpiName:branch_correct
|vpiTypespec:
\_logic_typespec: , line:456
|vpiTypespecMember:
\_typespec_member: (branch_misspredict), line:457
|vpiName:branch_misspredict
|vpiTypespec:
\_logic_typespec: , line:457
|vpiTypespecMember:
\_typespec_member: (return_misspredict), line:458
|vpiName:return_misspredict
|vpiTypespec:
\_logic_typespec: , line:458
|vpiTypespecMember:
\_typespec_member: (wb_mux_contention), line:461
|vpiName:wb_mux_contention
|vpiTypespec:
\_logic_typespec: , line:461
|vpiTypespecMember:
\_typespec_member: (rs1_forwarding_needed), line:464
|vpiName:rs1_forwarding_needed
|vpiTypespec:
\_logic_typespec: , line:464
|vpiTypespecMember:
\_typespec_member: (rs2_forwarding_needed), line:465
|vpiName:rs2_forwarding_needed
|vpiTypespec:
\_logic_typespec: , line:465
|vpiTypespecMember:
\_typespec_member: (rs1_and_rs2_forwarding_needed), line:466
|vpiName:rs1_and_rs2_forwarding_needed
|vpiTypespec:
\_logic_typespec: , line:466
|vpiTypedef:
\_struct_typespec: (to_l1_arbiter_packet), line:418
|vpiPacked:1
|vpiName:to_l1_arbiter_packet
|vpiTypespecMember:
\_typespec_member: (addr), line:419
|vpiName:addr
|vpiTypespec:
\_logic_typespec: , line:419
|vpiRange:
\_range: , line:419, parent:to_l1_arbiter_packet
|vpiLeftRange:
\_constant: , line:419
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:419
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiTypespecMember:
\_typespec_member: (data), line:420
|vpiName:data
|vpiTypespec:
\_logic_typespec: , line:420
|vpiRange:
\_range: , line:420, parent:to_l1_arbiter_packet
|vpiLeftRange:
\_constant: , line:420
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:420
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiTypespecMember:
\_typespec_member: (rnw), line:421
|vpiName:rnw
|vpiTypespec:
\_logic_typespec: , line:421
|vpiTypespecMember:
\_typespec_member: (be), line:422
|vpiName:be
|vpiTypespec:
\_logic_typespec: , line:422
|vpiRange:
\_range: , line:422, parent:to_l1_arbiter_packet
|vpiLeftRange:
\_constant: , line:422
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiRightRange:
\_constant: , line:422
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiTypespecMember:
\_typespec_member: (size), line:423
|vpiName:size
|vpiTypespec:
\_logic_typespec: , line:423
|vpiRange:
\_range: , line:423, parent:to_l1_arbiter_packet
|vpiLeftRange:
\_constant: , line:423
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiRightRange:
\_constant: , line:423
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiTypespecMember:
\_typespec_member: (con), line:424
|vpiName:con
|vpiTypespec:
\_logic_typespec: , line:424
|vpiTypedef:
\_struct_typespec: (trace_outputs_t), line:469
|vpiPacked:1
|vpiName:trace_outputs_t
|vpiTypespecMember:
\_typespec_member: (instruction_pc_dec), line:470
|vpiName:instruction_pc_dec
|vpiTypespec:
\_logic_typespec: , line:470
|vpiRange:
\_range: , line:470, parent:trace_outputs_t
|vpiLeftRange:
\_constant: , line:470
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:470
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiTypespecMember:
\_typespec_member: (instruction_data_dec), line:471
|vpiName:instruction_data_dec
|vpiTypespec:
\_logic_typespec: , line:471
|vpiRange:
\_range: , line:471, parent:trace_outputs_t
|vpiLeftRange:
\_constant: , line:471
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:471
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiTypespecMember:
\_typespec_member: (events), line:472
|vpiName:events
|vpiTypespec:
\_struct_typespec: (taiga_trace_events_t), line:442
|vpiTypedef:
\_logic_typespec: (unit_id_t), line:31
|vpiName:unit_id_t
|vpiRange:
\_range: , line:31
|vpiLeftRange:
\_operation: , line:31
|vpiOpType:11
|vpiOperand:
\_sys_func_call: ($clog2), line:31
|vpiName:$clog2
|vpiArgument:
\_ref_obj: (NUM_WB_UNITS), line:31
|vpiName:NUM_WB_UNITS
|vpiOperand:
\_constant: , line:31
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:31
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiTypedef:
\_struct_typespec: (unit_writeback_t), line:295
|vpiPacked:1
|vpiName:unit_writeback_t
|vpiTypespecMember:
\_typespec_member: (id), line:296
|vpiName:id
|vpiTypespec:
\_logic_typespec: (instruction_id_t), line:30
|vpiTypespecMember:
\_typespec_member: (done), line:297
|vpiName:done
|vpiTypespec:
\_logic_typespec: , line:297
|vpiTypespecMember:
\_typespec_member: (rd), line:298
|vpiName:rd
|vpiTypespec:
\_logic_typespec: , line:298
|vpiRange:
\_range: , line:298, parent:unit_writeback_t
|vpiLeftRange:
\_constant: , line:298
|vpiDecompile:31
|INT:31
|vpiRightRange:
\_constant: , line:298
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiTypedef:
\_enum_typespec: (vm_t), line:223
|vpiName:vm_t
|vpiBaseTypespec:
\_bit_typespec: , line:220
|vpiRange:
\_range: , line:220
|vpiLeftRange:
\_constant: , line:220
|vpiConstType:7
|vpiDecompile:4
|vpiSize:32
|INT:4
|vpiRightRange:
\_constant: , line:220
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiEnumConst:
\_enum_const: (BARE), line:221
|vpiName:BARE
|INT:0
|vpiEnumConst:
\_enum_const: (SV32), line:222
|vpiName:SV32
|INT:8
|vpiParamAssign:
\_param_assign: , line:26
|vpiRhs:
\_constant: , line:26
|vpiConstType:7
|vpiDecompile:32
|vpiSize:32
|INT:32
|vpiLhs:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|vpiFullName:taiga_types::XLEN
|vpiParamAssign:
\_param_assign: , line:27
|vpiRhs:
\_constant: , line:27
|vpiConstType:7
|vpiDecompile:12
|vpiSize:32
|INT:12
|vpiLhs:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|vpiFullName:taiga_types::PAGE_ADDR_W
|vpiParamAssign:
\_param_assign: , line:28
|vpiRhs:
\_constant: , line:28
|vpiConstType:7
|vpiDecompile:5
|vpiSize:32
|INT:5
|vpiLhs:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|vpiFullName:taiga_types::ECODE_W
|vpiParamAssign:
\_param_assign: , line:225
|vpiRhs:
\_constant: , line:225
|vpiConstType:7
|vpiDecompile:9
|vpiSize:32
|INT:9
|vpiLhs:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|vpiFullName:taiga_types::ASIDLEN
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|uhdmallClasses:
\_class_defn: (builtin::array)
|vpiName:builtin::array
|vpiFullName:builtin::builtin::array
|uhdmallClasses:
\_class_defn: (builtin::queue)
|vpiName:builtin::queue
|vpiFullName:builtin::builtin::queue
|uhdmallClasses:
\_class_defn: (builtin::string)
|vpiName:builtin::string
|vpiFullName:builtin::builtin::string
|uhdmallClasses:
\_class_defn: (builtin::system)
|vpiName:builtin::system
|vpiFullName:builtin::builtin::system
|uhdmallInterfaces:
\_interface: work@avalon_interface, file:third_party/cores/taiga/core/external_interfaces.sv, line:87, parent:work@div_unit_core_wrapper
|vpiDefName:work@avalon_interface
|vpiFullName:work@avalon_interface
|vpiModport:
\_modport: (master)
|vpiName:master
|vpiIODecl:
\_io_decl: (readdata)
|vpiName:readdata
|vpiDirection:1
|vpiIODecl:
\_io_decl: (waitrequest)
|vpiName:waitrequest
|vpiDirection:1
|vpiIODecl:
\_io_decl: (readdatavalid)
|vpiName:readdatavalid
|vpiDirection:1
|vpiIODecl:
\_io_decl: (writeresponsevalid)
|vpiName:writeresponsevalid
|vpiDirection:1
|vpiIODecl:
\_io_decl: (addr)
|vpiName:addr
|vpiDirection:2
|vpiIODecl:
\_io_decl: (read)
|vpiName:read
|vpiDirection:2
|vpiIODecl:
\_io_decl: (write)
|vpiName:write
|vpiDirection:2
|vpiIODecl:
\_io_decl: (byteenable)
|vpiName:byteenable
|vpiDirection:2
|vpiIODecl:
\_io_decl: (writedata)
|vpiName:writedata
|vpiDirection:2
|vpiModport:
\_modport: (slave)
|vpiName:slave
|vpiIODecl:
\_io_decl: (readdata)
|vpiName:readdata
|vpiDirection:2
|vpiIODecl:
\_io_decl: (waitrequest)
|vpiName:waitrequest
|vpiDirection:2
|vpiIODecl:
\_io_decl: (readdatavalid)
|vpiName:readdatavalid
|vpiDirection:2
|vpiIODecl:
\_io_decl: (writeresponsevalid)
|vpiName:writeresponsevalid
|vpiDirection:2
|vpiIODecl:
\_io_decl: (addr)
|vpiName:addr
|vpiDirection:1
|vpiIODecl:
\_io_decl: (read)
|vpiName:read
|vpiDirection:1
|vpiIODecl:
\_io_decl: (write)
|vpiName:write
|vpiDirection:1
|vpiIODecl:
\_io_decl: (byteenable)
|vpiName:byteenable
|vpiDirection:1
|vpiIODecl:
\_io_decl: (writedata)
|vpiName:writedata
|vpiDirection:1
|vpiNet:
\_logic_net: (addr), line:88
|vpiName:addr
|vpiFullName:work@avalon_interface.addr
|vpiNetType:36
|vpiNet:
\_logic_net: (read), line:89
|vpiName:read
|vpiFullName:work@avalon_interface.read
|vpiNetType:36
|vpiNet:
\_logic_net: (write), line:90
|vpiName:write
|vpiFullName:work@avalon_interface.write
|vpiNetType:36
|vpiNet:
\_logic_net: (byteenable), line:91
|vpiName:byteenable
|vpiFullName:work@avalon_interface.byteenable
|vpiNetType:36
|vpiNet:
\_logic_net: (readdata), line:92
|vpiName:readdata
|vpiFullName:work@avalon_interface.readdata
|vpiNetType:36
|vpiNet:
\_logic_net: (writedata), line:93
|vpiName:writedata
|vpiFullName:work@avalon_interface.writedata
|vpiNetType:36
|vpiNet:
\_logic_net: (waitrequest), line:94
|vpiName:waitrequest
|vpiFullName:work@avalon_interface.waitrequest
|vpiNetType:36
|vpiNet:
\_logic_net: (readdatavalid), line:95
|vpiName:readdatavalid
|vpiFullName:work@avalon_interface.readdatavalid
|vpiNetType:36
|vpiNet:
\_logic_net: (writeresponsevalid), line:96
|vpiName:writeresponsevalid
|vpiFullName:work@avalon_interface.writeresponsevalid
|vpiNetType:36
|vpiTypedef:
\_struct_typespec: (alu_inputs_t), line:301
|vpiTypedef:
\_enum_typespec: (alu_logic_op_t), line:84
|vpiTypedef:
\_enum_typespec: (alu_op_t), line:91
|vpiTypedef:
\_enum_typespec: (alu_rs1_op_t), line:97
|vpiTypedef:
\_enum_typespec: (alu_rs2_op_t), line:104
|vpiTypedef:
\_struct_typespec: (amo_alu_inputs_t), line:356
|vpiTypedef:
\_struct_typespec: (amo_details_t), line:362
|vpiTypedef:
\_enum_typespec: (amo_t), line:354
|vpiTypedef:
\_struct_typespec: (branch_inputs_t), line:313
|vpiTypedef:
\_logic_typespec: (branch_predictor_metadata_t), line:32
|vpiTypedef:
\_struct_typespec: (branch_results_t), line:330
|vpiTypedef:
\_enum_typespec: (bus_type_t), line:86
|vpiTypedef:
\_struct_typespec: (csr_inputs_t), line:396
|vpiTypedef:
\_enum_typespec: (csr_op_t), line:218
|vpiTypedef:
\_enum_typespec: (csr_t), line:201
|vpiTypedef:
\_struct_typespec: (data_access_shared_inputs_t), line:427
|vpiTypedef:
\_struct_typespec: (div_inputs_t), line:389
|vpiTypedef:
\_enum_typespec: (div_type), line:66
|vpiTypedef:
\_enum_typespec: (exception_code_t), line:245
|vpiTypedef:
\_struct_typespec: (exception_packet_t), line:263
|vpiTypedef:
\_struct_typespec: (fetch_buffer_packet_t), line:276
|vpiTypedef:
\_enum_typespec: (fifo_type_t), line:440
|vpiTypedef:
\_enum_typespec: (fn3_arith_t), line:76
|vpiTypedef:
\_enum_typespec: (fn3_branch_t), line:126
|vpiTypedef:
\_enum_typespec: (fn3_csr_t), line:212
|vpiTypedef:
\_enum_typespec: (fn3_ls_t), line:115
|vpiTypedef:
\_enum_typespec: (fn3_mul_div_t), line:138
|vpiTypedef:
\_struct_typespec: (gc_inputs_t), line:404
|vpiTypedef:
\_struct_typespec: (inflight_instruction_packet), line:271
|vpiTypedef:
\_logic_typespec: (instruction_id_t), line:30
|vpiTypedef:
\_enum_typespec: (interrupt_code_t), line:261
|vpiTypedef:
\_struct_typespec: (l2_data_attributes_t), line:68
|vpiTypedef:
\_struct_typespec: (l2_mem_request_t), line:58
|vpiTypedef:
\_struct_typespec: (l2_mem_return_data_t), line:75
|vpiTypedef:
\_struct_typespec: (l2_request_t), line:49
|vpiTypedef:
\_struct_typespec: (l2_return_data_t), line:81
|vpiTypedef:
\_struct_typespec: (load_store_inputs_t), line:369
|vpiTypedef:
\_struct_typespec: (mul_inputs_t), line:383
|vpiTypedef:
\_enum_typespec: (opcodes_t), line:48
|vpiTypedef:
\_enum_typespec: (opcodes_trimmed_t), line:65
|vpiTypedef:
\_struct_typespec: (simulation_named_regfile), line:476
|vpiTypedef:
\_struct_typespec: (taiga_trace_events_t), line:442
|vpiTypedef:
\_struct_typespec: (to_l1_arbiter_packet), line:418
|vpiTypedef:
\_struct_typespec: (trace_outputs_t), line:469
|vpiTypedef:
\_logic_typespec: (unit_id_t), line:31
|vpiTypedef:
\_struct_typespec: (unit_writeback_t), line:295
|vpiTypedef:
\_enum_typespec: (vm_t), line:223
|uhdmallInterfaces:
\_interface: work@axi_interface, file:third_party/cores/taiga/core/external_interfaces.sv, line:27, parent:work@div_unit_core_wrapper
|vpiDefName:work@axi_interface
|vpiFullName:work@axi_interface
|vpiModport:
\_modport: (master)
|vpiName:master
|vpiIODecl:
\_io_decl: (arready)
|vpiName:arready
|vpiDirection:1
|vpiIODecl:
\_io_decl: (rvalid)
|vpiName:rvalid
|vpiDirection:1
|vpiIODecl:
\_io_decl: (rdata)
|vpiName:rdata
|vpiDirection:1
|vpiIODecl:
\_io_decl: (rresp)
|vpiName:rresp
|vpiDirection:1
|vpiIODecl:
\_io_decl: (rlast)
|vpiName:rlast
|vpiDirection:1
|vpiIODecl:
\_io_decl: (rid)
|vpiName:rid
|vpiDirection:1
|vpiIODecl:
\_io_decl: (awready)
|vpiName:awready
|vpiDirection:1
|vpiIODecl:
\_io_decl: (wready)
|vpiName:wready
|vpiDirection:1
|vpiIODecl:
\_io_decl: (bvalid)
|vpiName:bvalid
|vpiDirection:1
|vpiIODecl:
\_io_decl: (bresp)
|vpiName:bresp
|vpiDirection:1
|vpiIODecl:
\_io_decl: (bid)
|vpiName:bid
|vpiDirection:1
|vpiIODecl:
\_io_decl: (arvalid)
|vpiName:arvalid
|vpiDirection:2
|vpiIODecl:
\_io_decl: (araddr)
|vpiName:araddr
|vpiDirection:2
|vpiIODecl:
\_io_decl: (arlen)
|vpiName:arlen
|vpiDirection:2
|vpiIODecl:
\_io_decl: (arsize)
|vpiName:arsize
|vpiDirection:2
|vpiIODecl:
\_io_decl: (arburst)
|vpiName:arburst
|vpiDirection:2
|vpiIODecl:
\_io_decl: (arcache)
|vpiName:arcache
|vpiDirection:2
|vpiIODecl:
\_io_decl: (arid)
|vpiName:arid
|vpiDirection:2
|vpiIODecl:
\_io_decl: (rready)
|vpiName:rready
|vpiDirection:2
|vpiIODecl:
\_io_decl: (awvalid)
|vpiName:awvalid
|vpiDirection:2
|vpiIODecl:
\_io_decl: (awaddr)
|vpiName:awaddr
|vpiDirection:2
|vpiIODecl:
\_io_decl: (awlen)
|vpiName:awlen
|vpiDirection:2
|vpiIODecl:
\_io_decl: (awsize)
|vpiName:awsize
|vpiDirection:2
|vpiIODecl:
\_io_decl: (awburst)
|vpiName:awburst
|vpiDirection:2
|vpiIODecl:
\_io_decl: (awcache)
|vpiName:awcache
|vpiDirection:2
|vpiIODecl:
\_io_decl: (awid)
|vpiName:awid
|vpiDirection:2
|vpiIODecl:
\_io_decl: (wvalid)
|vpiName:wvalid
|vpiDirection:2
|vpiIODecl:
\_io_decl: (wdata)
|vpiName:wdata
|vpiDirection:2
|vpiIODecl:
\_io_decl: (wstrb)
|vpiName:wstrb
|vpiDirection:2
|vpiIODecl:
\_io_decl: (wlast)
|vpiName:wlast
|vpiDirection:2
|vpiIODecl:
\_io_decl: (bready)
|vpiName:bready
|vpiDirection:2
|vpiModport:
\_modport: (slave)
|vpiName:slave
|vpiIODecl:
\_io_decl: (arvalid)
|vpiName:arvalid
|vpiDirection:1
|vpiIODecl:
\_io_decl: (araddr)
|vpiName:araddr
|vpiDirection:1
|vpiIODecl:
\_io_decl: (arlen)
|vpiName:arlen
|vpiDirection:1
|vpiIODecl:
\_io_decl: (arsize)
|vpiName:arsize
|vpiDirection:1
|vpiIODecl:
\_io_decl: (arburst)
|vpiName:arburst
|vpiDirection:1
|vpiIODecl:
\_io_decl: (arcache)
|vpiName:arcache
|vpiDirection:1
|vpiIODecl:
\_io_decl: (rready)
|vpiName:rready
|vpiDirection:1
|vpiIODecl:
\_io_decl: (awvalid)
|vpiName:awvalid
|vpiDirection:1
|vpiIODecl:
\_io_decl: (awaddr)
|vpiName:awaddr
|vpiDirection:1
|vpiIODecl:
\_io_decl: (awlen)
|vpiName:awlen
|vpiDirection:1
|vpiIODecl:
\_io_decl: (awsize)
|vpiName:awsize
|vpiDirection:1
|vpiIODecl:
\_io_decl: (awburst)
|vpiName:awburst
|vpiDirection:1
|vpiIODecl:
\_io_decl: (awcache)
|vpiName:awcache
|vpiDirection:1
|vpiIODecl:
\_io_decl: (arid)
|vpiName:arid
|vpiDirection:1
|vpiIODecl:
\_io_decl: (wvalid)
|vpiName:wvalid
|vpiDirection:1
|vpiIODecl:
\_io_decl: (wdata)
|vpiName:wdata
|vpiDirection:1
|vpiIODecl:
\_io_decl: (wstrb)
|vpiName:wstrb
|vpiDirection:1
|vpiIODecl:
\_io_decl: (wlast)
|vpiName:wlast
|vpiDirection:1
|vpiIODecl:
\_io_decl: (awid)
|vpiName:awid
|vpiDirection:1
|vpiIODecl:
\_io_decl: (bready)
|vpiName:bready
|vpiDirection:1
|vpiIODecl:
\_io_decl: (arready)
|vpiName:arready
|vpiDirection:2
|vpiIODecl:
\_io_decl: (rvalid)
|vpiName:rvalid
|vpiDirection:2
|vpiIODecl:
\_io_decl: (rdata)
|vpiName:rdata
|vpiDirection:2
|vpiIODecl:
\_io_decl: (rresp)
|vpiName:rresp
|vpiDirection:2
|vpiIODecl:
\_io_decl: (rlast)
|vpiName:rlast
|vpiDirection:2
|vpiIODecl:
\_io_decl: (rid)
|vpiName:rid
|vpiDirection:2
|vpiIODecl:
\_io_decl: (awready)
|vpiName:awready
|vpiDirection:2
|vpiIODecl:
\_io_decl: (wready)
|vpiName:wready
|vpiDirection:2
|vpiIODecl:
\_io_decl: (bvalid)
|vpiName:bvalid
|vpiDirection:2
|vpiIODecl:
\_io_decl: (bresp)
|vpiName:bresp
|vpiDirection:2
|vpiIODecl:
\_io_decl: (bid)
|vpiName:bid
|vpiDirection:2
|vpiNet:
\_logic_net: (arready), line:29
|vpiName:arready
|vpiFullName:work@axi_interface.arready
|vpiNetType:36
|vpiNet:
\_logic_net: (arvalid), line:30
|vpiName:arvalid
|vpiFullName:work@axi_interface.arvalid
|vpiNetType:36
|vpiNet:
\_logic_net: (araddr), line:31
|vpiName:araddr
|vpiFullName:work@axi_interface.araddr
|vpiNetType:36
|vpiNet:
\_logic_net: (arlen), line:32
|vpiName:arlen
|vpiFullName:work@axi_interface.arlen
|vpiNetType:36
|vpiNet:
\_logic_net: (arsize), line:33
|vpiName:arsize
|vpiFullName:work@axi_interface.arsize
|vpiNetType:36
|vpiNet:
\_logic_net: (arburst), line:34
|vpiName:arburst
|vpiFullName:work@axi_interface.arburst
|vpiNetType:36
|vpiNet:
\_logic_net: (arcache), line:35
|vpiName:arcache
|vpiFullName:work@axi_interface.arcache
|vpiNetType:36
|vpiNet:
\_logic_net: (arid), line:36
|vpiName:arid
|vpiFullName:work@axi_interface.arid
|vpiNetType:36
|vpiNet:
\_logic_net: (rready), line:39
|vpiName:rready
|vpiFullName:work@axi_interface.rready
|vpiNetType:36
|vpiNet:
\_logic_net: (rvalid), line:40
|vpiName:rvalid
|vpiFullName:work@axi_interface.rvalid
|vpiNetType:36
|vpiNet:
\_logic_net: (rdata), line:41
|vpiName:rdata
|vpiFullName:work@axi_interface.rdata
|vpiNetType:36
|vpiNet:
\_logic_net: (rresp), line:42
|vpiName:rresp
|vpiFullName:work@axi_interface.rresp
|vpiNetType:36
|vpiNet:
\_logic_net: (rlast), line:43
|vpiName:rlast
|vpiFullName:work@axi_interface.rlast
|vpiNetType:36
|vpiNet:
\_logic_net: (rid), line:44
|vpiName:rid
|vpiFullName:work@axi_interface.rid
|vpiNetType:36
|vpiNet:
\_logic_net: (awready), line:48
|vpiName:awready
|vpiFullName:work@axi_interface.awready
|vpiNetType:36
|vpiNet:
\_logic_net: (awvalid), line:49
|vpiName:awvalid
|vpiFullName:work@axi_interface.awvalid
|vpiNetType:36
|vpiNet:
\_logic_net: (awaddr), line:50
|vpiName:awaddr
|vpiFullName:work@axi_interface.awaddr
|vpiNetType:36
|vpiNet:
\_logic_net: (awlen), line:51
|vpiName:awlen
|vpiFullName:work@axi_interface.awlen
|vpiNetType:36
|vpiNet:
\_logic_net: (awsize), line:52
|vpiName:awsize
|vpiFullName:work@axi_interface.awsize
|vpiNetType:36
|vpiNet:
\_logic_net: (awburst), line:53
|vpiName:awburst
|vpiFullName:work@axi_interface.awburst
|vpiNetType:36
|vpiNet:
\_logic_net: (awcache), line:54
|vpiName:awcache
|vpiFullName:work@axi_interface.awcache
|vpiNetType:36
|vpiNet:
\_logic_net: (awid), line:55
|vpiName:awid
|vpiFullName:work@axi_interface.awid
|vpiNetType:36
|vpiNet:
\_logic_net: (wready), line:58
|vpiName:wready
|vpiFullName:work@axi_interface.wready
|vpiNetType:36
|vpiNet:
\_logic_net: (wvalid), line:59
|vpiName:wvalid
|vpiFullName:work@axi_interface.wvalid
|vpiNetType:36
|vpiNet:
\_logic_net: (wdata), line:60
|vpiName:wdata
|vpiFullName:work@axi_interface.wdata
|vpiNetType:36
|vpiNet:
\_logic_net: (wstrb), line:61
|vpiName:wstrb
|vpiFullName:work@axi_interface.wstrb
|vpiNetType:36
|vpiNet:
\_logic_net: (wlast), line:62
|vpiName:wlast
|vpiFullName:work@axi_interface.wlast
|vpiNetType:36
|vpiNet:
\_logic_net: (bready), line:65
|vpiName:bready
|vpiFullName:work@axi_interface.bready
|vpiNetType:36
|vpiNet:
\_logic_net: (bvalid), line:66
|vpiName:bvalid
|vpiFullName:work@axi_interface.bvalid
|vpiNetType:36
|vpiNet:
\_logic_net: (bresp), line:67
|vpiName:bresp
|vpiFullName:work@axi_interface.bresp
|vpiNetType:36
|vpiNet:
\_logic_net: (bid), line:68
|vpiName:bid
|vpiFullName:work@axi_interface.bid
|vpiNetType:36
|vpiTypedef:
\_struct_typespec: (alu_inputs_t), line:301
|vpiTypedef:
\_enum_typespec: (alu_logic_op_t), line:84
|vpiTypedef:
\_enum_typespec: (alu_op_t), line:91
|vpiTypedef:
\_enum_typespec: (alu_rs1_op_t), line:97
|vpiTypedef:
\_enum_typespec: (alu_rs2_op_t), line:104
|vpiTypedef:
\_struct_typespec: (amo_alu_inputs_t), line:356
|vpiTypedef:
\_struct_typespec: (amo_details_t), line:362
|vpiTypedef:
\_enum_typespec: (amo_t), line:354
|vpiTypedef:
\_struct_typespec: (branch_inputs_t), line:313
|vpiTypedef:
\_logic_typespec: (branch_predictor_metadata_t), line:32
|vpiTypedef:
\_struct_typespec: (branch_results_t), line:330
|vpiTypedef:
\_enum_typespec: (bus_type_t), line:86
|vpiTypedef:
\_struct_typespec: (csr_inputs_t), line:396
|vpiTypedef:
\_enum_typespec: (csr_op_t), line:218
|vpiTypedef:
\_enum_typespec: (csr_t), line:201
|vpiTypedef:
\_struct_typespec: (data_access_shared_inputs_t), line:427
|vpiTypedef:
\_struct_typespec: (div_inputs_t), line:389
|vpiTypedef:
\_enum_typespec: (div_type), line:66
|vpiTypedef:
\_enum_typespec: (exception_code_t), line:245
|vpiTypedef:
\_struct_typespec: (exception_packet_t), line:263
|vpiTypedef:
\_struct_typespec: (fetch_buffer_packet_t), line:276
|vpiTypedef:
\_enum_typespec: (fifo_type_t), line:440
|vpiTypedef:
\_enum_typespec: (fn3_arith_t), line:76
|vpiTypedef:
\_enum_typespec: (fn3_branch_t), line:126
|vpiTypedef:
\_enum_typespec: (fn3_csr_t), line:212
|vpiTypedef:
\_enum_typespec: (fn3_ls_t), line:115
|vpiTypedef:
\_enum_typespec: (fn3_mul_div_t), line:138
|vpiTypedef:
\_struct_typespec: (gc_inputs_t), line:404
|vpiTypedef:
\_struct_typespec: (inflight_instruction_packet), line:271
|vpiTypedef:
\_logic_typespec: (instruction_id_t), line:30
|vpiTypedef:
\_enum_typespec: (interrupt_code_t), line:261
|vpiTypedef:
\_struct_typespec: (l2_data_attributes_t), line:68
|vpiTypedef:
\_struct_typespec: (l2_mem_request_t), line:58
|vpiTypedef:
\_struct_typespec: (l2_mem_return_data_t), line:75
|vpiTypedef:
\_struct_typespec: (l2_request_t), line:49
|vpiTypedef:
\_struct_typespec: (l2_return_data_t), line:81
|vpiTypedef:
\_struct_typespec: (load_store_inputs_t), line:369
|vpiTypedef:
\_struct_typespec: (mul_inputs_t), line:383
|vpiTypedef:
\_enum_typespec: (opcodes_t), line:48
|vpiTypedef:
\_enum_typespec: (opcodes_trimmed_t), line:65
|vpiTypedef:
\_struct_typespec: (simulation_named_regfile), line:476
|vpiTypedef:
\_struct_typespec: (taiga_trace_events_t), line:442
|vpiTypedef:
\_struct_typespec: (to_l1_arbiter_packet), line:418
|vpiTypedef:
\_struct_typespec: (trace_outputs_t), line:469
|vpiTypedef:
\_logic_typespec: (unit_id_t), line:31
|vpiTypedef:
\_struct_typespec: (unit_writeback_t), line:295
|vpiTypedef:
\_enum_typespec: (vm_t), line:223
|uhdmallInterfaces:
\_interface: work@branch_predictor_interface, file:third_party/cores/taiga/core/interfaces.sv, line:27, parent:work@div_unit_core_wrapper
|vpiDefName:work@branch_predictor_interface
|vpiFullName:work@branch_predictor_interface
|vpiModport:
\_modport: (branch_predictor)
|vpiName:branch_predictor
|vpiIODecl:
\_io_decl: (if_pc)
|vpiName:if_pc
|vpiDirection:1
|vpiIODecl:
\_io_decl: (new_mem_request)
|vpiName:new_mem_request
|vpiDirection:1
|vpiIODecl:
\_io_decl: (next_pc)
|vpiName:next_pc
|vpiDirection:1
|vpiIODecl:
\_io_decl: (branch_flush_pc)
|vpiName:branch_flush_pc
|vpiDirection:2
|vpiIODecl:
\_io_decl: (predicted_pc)
|vpiName:predicted_pc
|vpiDirection:2
|vpiIODecl:
\_io_decl: (use_prediction)
|vpiName:use_prediction
|vpiDirection:2
|vpiIODecl:
\_io_decl: (update_way)
|vpiName:update_way
|vpiDirection:2
|vpiIODecl:
\_io_decl: (use_ras)
|vpiName:use_ras
|vpiDirection:2
|vpiIODecl:
\_io_decl: (metadata)
|vpiName:metadata
|vpiDirection:2
|vpiModport:
\_modport: (fetch)
|vpiName:fetch
|vpiIODecl:
\_io_decl: (branch_flush_pc)
|vpiName:branch_flush_pc
|vpiDirection:1
|vpiIODecl:
\_io_decl: (predicted_pc)
|vpiName:predicted_pc
|vpiDirection:1
|vpiIODecl:
\_io_decl: (use_prediction)
|vpiName:use_prediction
|vpiDirection:1
|vpiIODecl:
\_io_decl: (update_way)
|vpiName:update_way
|vpiDirection:1
|vpiIODecl:
\_io_decl: (use_ras)
|vpiName:use_ras
|vpiDirection:1
|vpiIODecl:
\_io_decl: (metadata)
|vpiName:metadata
|vpiDirection:1
|vpiIODecl:
\_io_decl: (if_pc)
|vpiName:if_pc
|vpiDirection:2
|vpiIODecl:
\_io_decl: (new_mem_request)
|vpiName:new_mem_request
|vpiDirection:2
|vpiIODecl:
\_io_decl: (next_pc)
|vpiName:next_pc
|vpiDirection:2
|vpiNet:
\_logic_net: (if_pc), line:29
|vpiName:if_pc
|vpiFullName:work@branch_predictor_interface.if_pc
|vpiNetType:36
|vpiNet:
\_logic_net: (new_mem_request), line:30
|vpiName:new_mem_request
|vpiFullName:work@branch_predictor_interface.new_mem_request
|vpiNetType:36
|vpiNet:
\_logic_net: (next_pc), line:31
|vpiName:next_pc
|vpiFullName:work@branch_predictor_interface.next_pc
|vpiNetType:36
|vpiNet:
\_logic_net: (branch_flush_pc), line:34
|vpiName:branch_flush_pc
|vpiFullName:work@branch_predictor_interface.branch_flush_pc
|vpiNetType:36
|vpiNet:
\_logic_net: (predicted_pc), line:35
|vpiName:predicted_pc
|vpiFullName:work@branch_predictor_interface.predicted_pc
|vpiNetType:36
|vpiNet:
\_logic_net: (use_prediction), line:36
|vpiName:use_prediction
|vpiFullName:work@branch_predictor_interface.use_prediction
|vpiNetType:36
|vpiNet:
\_logic_net: (update_way), line:37
|vpiName:update_way
|vpiFullName:work@branch_predictor_interface.update_way
|vpiNetType:36
|vpiNet:
\_logic_net: (use_ras), line:38
|vpiName:use_ras
|vpiFullName:work@branch_predictor_interface.use_ras
|vpiNetType:36
|vpiNet:
\_logic_net: (metadata), line:39
|vpiName:metadata
|vpiFullName:work@branch_predictor_interface.metadata
|vpiTypedef:
\_struct_typespec: (alu_inputs_t), line:301
|vpiTypedef:
\_enum_typespec: (alu_logic_op_t), line:84
|vpiTypedef:
\_enum_typespec: (alu_op_t), line:91
|vpiTypedef:
\_enum_typespec: (alu_rs1_op_t), line:97
|vpiTypedef:
\_enum_typespec: (alu_rs2_op_t), line:104
|vpiTypedef:
\_struct_typespec: (amo_alu_inputs_t), line:356
|vpiTypedef:
\_struct_typespec: (amo_details_t), line:362
|vpiTypedef:
\_enum_typespec: (amo_t), line:354
|vpiTypedef:
\_struct_typespec: (branch_inputs_t), line:313
|vpiTypedef:
\_logic_typespec: (branch_predictor_metadata_t), line:32
|vpiTypedef:
\_struct_typespec: (branch_results_t), line:330
|vpiTypedef:
\_enum_typespec: (bus_type_t), line:86
|vpiTypedef:
\_struct_typespec: (csr_inputs_t), line:396
|vpiTypedef:
\_enum_typespec: (csr_op_t), line:218
|vpiTypedef:
\_enum_typespec: (csr_t), line:201
|vpiTypedef:
\_struct_typespec: (data_access_shared_inputs_t), line:427
|vpiTypedef:
\_struct_typespec: (div_inputs_t), line:389
|vpiTypedef:
\_enum_typespec: (div_type), line:66
|vpiTypedef:
\_enum_typespec: (exception_code_t), line:245
|vpiTypedef:
\_struct_typespec: (exception_packet_t), line:263
|vpiTypedef:
\_struct_typespec: (fetch_buffer_packet_t), line:276
|vpiTypedef:
\_enum_typespec: (fifo_type_t), line:440
|vpiTypedef:
\_enum_typespec: (fn3_arith_t), line:76
|vpiTypedef:
\_enum_typespec: (fn3_branch_t), line:126
|vpiTypedef:
\_enum_typespec: (fn3_csr_t), line:212
|vpiTypedef:
\_enum_typespec: (fn3_ls_t), line:115
|vpiTypedef:
\_enum_typespec: (fn3_mul_div_t), line:138
|vpiTypedef:
\_struct_typespec: (gc_inputs_t), line:404
|vpiTypedef:
\_struct_typespec: (inflight_instruction_packet), line:271
|vpiTypedef:
\_logic_typespec: (instruction_id_t), line:30
|vpiTypedef:
\_enum_typespec: (interrupt_code_t), line:261
|vpiTypedef:
\_struct_typespec: (l2_data_attributes_t), line:68
|vpiTypedef:
\_struct_typespec: (l2_mem_request_t), line:58
|vpiTypedef:
\_struct_typespec: (l2_mem_return_data_t), line:75
|vpiTypedef:
\_struct_typespec: (l2_request_t), line:49
|vpiTypedef:
\_struct_typespec: (l2_return_data_t), line:81
|vpiTypedef:
\_struct_typespec: (load_store_inputs_t), line:369
|vpiTypedef:
\_struct_typespec: (mul_inputs_t), line:383
|vpiTypedef:
\_enum_typespec: (opcodes_t), line:48
|vpiTypedef:
\_enum_typespec: (opcodes_trimmed_t), line:65
|vpiTypedef:
\_struct_typespec: (simulation_named_regfile), line:476
|vpiTypedef:
\_struct_typespec: (taiga_trace_events_t), line:442
|vpiTypedef:
\_struct_typespec: (to_l1_arbiter_packet), line:418
|vpiTypedef:
\_struct_typespec: (trace_outputs_t), line:469
|vpiTypedef:
\_logic_typespec: (unit_id_t), line:31
|vpiTypedef:
\_struct_typespec: (unit_writeback_t), line:295
|vpiTypedef:
\_enum_typespec: (vm_t), line:223
|uhdmallInterfaces:
\_interface: work@csr_exception_interface, file:third_party/cores/taiga/core/interfaces.sv, line:76, parent:work@div_unit_core_wrapper
|vpiDefName:work@csr_exception_interface
|vpiFullName:work@csr_exception_interface
|vpiModport:
\_modport: (csr)
|vpiName:csr
|vpiIODecl:
\_io_decl: (valid)
|vpiName:valid
|vpiDirection:1
|vpiIODecl:
\_io_decl: (code)
|vpiName:code
|vpiDirection:1
|vpiIODecl:
\_io_decl: (pc)
|vpiName:pc
|vpiDirection:1
|vpiIODecl:
\_io_decl: (addr)
|vpiName:addr
|vpiDirection:1
|vpiIODecl:
\_io_decl: (illegal_instruction)
|vpiName:illegal_instruction
|vpiDirection:2
|vpiIODecl:
\_io_decl: (csr_pc)
|vpiName:csr_pc
|vpiDirection:2
|vpiModport:
\_modport: (econtrol)
|vpiName:econtrol
|vpiIODecl:
\_io_decl: (valid)
|vpiName:valid
|vpiDirection:2
|vpiIODecl:
\_io_decl: (code)
|vpiName:code
|vpiDirection:2
|vpiIODecl:
\_io_decl: (pc)
|vpiName:pc
|vpiDirection:2
|vpiIODecl:
\_io_decl: (addr)
|vpiName:addr
|vpiDirection:2
|vpiIODecl:
\_io_decl: (illegal_instruction)
|vpiName:illegal_instruction
|vpiDirection:1
|vpiIODecl:
\_io_decl: (csr_pc)
|vpiName:csr_pc
|vpiDirection:1
|vpiNet:
\_logic_net: (valid), line:77
|vpiName:valid
|vpiFullName:work@csr_exception_interface.valid
|vpiNetType:36
|vpiNet:
\_logic_net: (code), line:78
|vpiName:code
|vpiFullName:work@csr_exception_interface.code
|vpiNet:
\_logic_net: (pc), line:79
|vpiName:pc
|vpiFullName:work@csr_exception_interface.pc
|vpiNetType:36
|vpiNet:
\_logic_net: (addr), line:80
|vpiName:addr
|vpiFullName:work@csr_exception_interface.addr
|vpiNetType:36
|vpiNet:
\_logic_net: (illegal_instruction), line:82
|vpiName:illegal_instruction
|vpiFullName:work@csr_exception_interface.illegal_instruction
|vpiNetType:36
|vpiNet:
\_logic_net: (csr_pc), line:83
|vpiName:csr_pc
|vpiFullName:work@csr_exception_interface.csr_pc
|vpiNetType:36
|vpiTypedef:
\_struct_typespec: (alu_inputs_t), line:301
|vpiTypedef:
\_enum_typespec: (alu_logic_op_t), line:84
|vpiTypedef:
\_enum_typespec: (alu_op_t), line:91
|vpiTypedef:
\_enum_typespec: (alu_rs1_op_t), line:97
|vpiTypedef:
\_enum_typespec: (alu_rs2_op_t), line:104
|vpiTypedef:
\_struct_typespec: (amo_alu_inputs_t), line:356
|vpiTypedef:
\_struct_typespec: (amo_details_t), line:362
|vpiTypedef:
\_enum_typespec: (amo_t), line:354
|vpiTypedef:
\_struct_typespec: (branch_inputs_t), line:313
|vpiTypedef:
\_logic_typespec: (branch_predictor_metadata_t), line:32
|vpiTypedef:
\_struct_typespec: (branch_results_t), line:330
|vpiTypedef:
\_enum_typespec: (bus_type_t), line:86
|vpiTypedef:
\_struct_typespec: (csr_inputs_t), line:396
|vpiTypedef:
\_enum_typespec: (csr_op_t), line:218
|vpiTypedef:
\_enum_typespec: (csr_t), line:201
|vpiTypedef:
\_struct_typespec: (data_access_shared_inputs_t), line:427
|vpiTypedef:
\_struct_typespec: (div_inputs_t), line:389
|vpiTypedef:
\_enum_typespec: (div_type), line:66
|vpiTypedef:
\_enum_typespec: (exception_code_t), line:245
|vpiTypedef:
\_struct_typespec: (exception_packet_t), line:263
|vpiTypedef:
\_struct_typespec: (fetch_buffer_packet_t), line:276
|vpiTypedef:
\_enum_typespec: (fifo_type_t), line:440
|vpiTypedef:
\_enum_typespec: (fn3_arith_t), line:76
|vpiTypedef:
\_enum_typespec: (fn3_branch_t), line:126
|vpiTypedef:
\_enum_typespec: (fn3_csr_t), line:212
|vpiTypedef:
\_enum_typespec: (fn3_ls_t), line:115
|vpiTypedef:
\_enum_typespec: (fn3_mul_div_t), line:138
|vpiTypedef:
\_struct_typespec: (gc_inputs_t), line:404
|vpiTypedef:
\_struct_typespec: (inflight_instruction_packet), line:271
|vpiTypedef:
\_logic_typespec: (instruction_id_t), line:30
|vpiTypedef:
\_enum_typespec: (interrupt_code_t), line:261
|vpiTypedef:
\_struct_typespec: (l2_data_attributes_t), line:68
|vpiTypedef:
\_struct_typespec: (l2_mem_request_t), line:58
|vpiTypedef:
\_struct_typespec: (l2_mem_return_data_t), line:75
|vpiTypedef:
\_struct_typespec: (l2_request_t), line:49
|vpiTypedef:
\_struct_typespec: (l2_return_data_t), line:81
|vpiTypedef:
\_struct_typespec: (load_store_inputs_t), line:369
|vpiTypedef:
\_struct_typespec: (mul_inputs_t), line:383
|vpiTypedef:
\_enum_typespec: (opcodes_t), line:48
|vpiTypedef:
\_enum_typespec: (opcodes_trimmed_t), line:65
|vpiTypedef:
\_struct_typespec: (simulation_named_regfile), line:476
|vpiTypedef:
\_struct_typespec: (taiga_trace_events_t), line:442
|vpiTypedef:
\_struct_typespec: (to_l1_arbiter_packet), line:418
|vpiTypedef:
\_struct_typespec: (trace_outputs_t), line:469
|vpiTypedef:
\_logic_typespec: (unit_id_t), line:31
|vpiTypedef:
\_struct_typespec: (unit_writeback_t), line:295
|vpiTypedef:
\_enum_typespec: (vm_t), line:223
|uhdmallInterfaces:
\_interface: work@exception_interface, file:third_party/cores/taiga/core/interfaces.sv, line:90, parent:work@div_unit_core_wrapper
|vpiDefName:work@exception_interface
|vpiFullName:work@exception_interface
|vpiModport:
\_modport: (econtrol)
|vpiName:econtrol
|vpiIODecl:
\_io_decl: (valid)
|vpiName:valid
|vpiDirection:2
|vpiIODecl:
\_io_decl: (code)
|vpiName:code
|vpiDirection:2
|vpiIODecl:
\_io_decl: (pc)
|vpiName:pc
|vpiDirection:2
|vpiIODecl:
\_io_decl: (addr)
|vpiName:addr
|vpiDirection:2
|vpiIODecl:
\_io_decl: (id)
|vpiName:id
|vpiDirection:2
|vpiIODecl:
\_io_decl: (ack)
|vpiName:ack
|vpiDirection:1
|vpiModport:
\_modport: (unit)
|vpiName:unit
|vpiIODecl:
\_io_decl: (valid)
|vpiName:valid
|vpiDirection:1
|vpiIODecl:
\_io_decl: (code)
|vpiName:code
|vpiDirection:1
|vpiIODecl:
\_io_decl: (pc)
|vpiName:pc
|vpiDirection:1
|vpiIODecl:
\_io_decl: (addr)
|vpiName:addr
|vpiDirection:1
|vpiIODecl:
\_io_decl: (id)
|vpiName:id
|vpiDirection:1
|vpiIODecl:
\_io_decl: (ack)
|vpiName:ack
|vpiDirection:2
|vpiNet:
\_logic_net: (valid), line:91
|vpiName:valid
|vpiFullName:work@exception_interface.valid
|vpiNetType:36
|vpiNet:
\_logic_net: (ack), line:92
|vpiName:ack
|vpiFullName:work@exception_interface.ack
|vpiNetType:36
|vpiNet:
\_logic_net: (code), line:94
|vpiName:code
|vpiFullName:work@exception_interface.code
|vpiNet:
\_logic_net: (pc), line:95
|vpiName:pc
|vpiFullName:work@exception_interface.pc
|vpiNetType:36
|vpiNet:
\_logic_net: (addr), line:96
|vpiName:addr
|vpiFullName:work@exception_interface.addr
|vpiNetType:36
|vpiNet:
\_logic_net: (id), line:97
|vpiName:id
|vpiFullName:work@exception_interface.id
|vpiTypedef:
\_struct_typespec: (alu_inputs_t), line:301
|vpiTypedef:
\_enum_typespec: (alu_logic_op_t), line:84
|vpiTypedef:
\_enum_typespec: (alu_op_t), line:91
|vpiTypedef:
\_enum_typespec: (alu_rs1_op_t), line:97
|vpiTypedef:
\_enum_typespec: (alu_rs2_op_t), line:104
|vpiTypedef:
\_struct_typespec: (amo_alu_inputs_t), line:356
|vpiTypedef:
\_struct_typespec: (amo_details_t), line:362
|vpiTypedef:
\_enum_typespec: (amo_t), line:354
|vpiTypedef:
\_struct_typespec: (branch_inputs_t), line:313
|vpiTypedef:
\_logic_typespec: (branch_predictor_metadata_t), line:32
|vpiTypedef:
\_struct_typespec: (branch_results_t), line:330
|vpiTypedef:
\_enum_typespec: (bus_type_t), line:86
|vpiTypedef:
\_struct_typespec: (csr_inputs_t), line:396
|vpiTypedef:
\_enum_typespec: (csr_op_t), line:218
|vpiTypedef:
\_enum_typespec: (csr_t), line:201
|vpiTypedef:
\_struct_typespec: (data_access_shared_inputs_t), line:427
|vpiTypedef:
\_struct_typespec: (div_inputs_t), line:389
|vpiTypedef:
\_enum_typespec: (div_type), line:66
|vpiTypedef:
\_enum_typespec: (exception_code_t), line:245
|vpiTypedef:
\_struct_typespec: (exception_packet_t), line:263
|vpiTypedef:
\_struct_typespec: (fetch_buffer_packet_t), line:276
|vpiTypedef:
\_enum_typespec: (fifo_type_t), line:440
|vpiTypedef:
\_enum_typespec: (fn3_arith_t), line:76
|vpiTypedef:
\_enum_typespec: (fn3_branch_t), line:126
|vpiTypedef:
\_enum_typespec: (fn3_csr_t), line:212
|vpiTypedef:
\_enum_typespec: (fn3_ls_t), line:115
|vpiTypedef:
\_enum_typespec: (fn3_mul_div_t), line:138
|vpiTypedef:
\_struct_typespec: (gc_inputs_t), line:404
|vpiTypedef:
\_struct_typespec: (inflight_instruction_packet), line:271
|vpiTypedef:
\_logic_typespec: (instruction_id_t), line:30
|vpiTypedef:
\_enum_typespec: (interrupt_code_t), line:261
|vpiTypedef:
\_struct_typespec: (l2_data_attributes_t), line:68
|vpiTypedef:
\_struct_typespec: (l2_mem_request_t), line:58
|vpiTypedef:
\_struct_typespec: (l2_mem_return_data_t), line:75
|vpiTypedef:
\_struct_typespec: (l2_request_t), line:49
|vpiTypedef:
\_struct_typespec: (l2_return_data_t), line:81
|vpiTypedef:
\_struct_typespec: (load_store_inputs_t), line:369
|vpiTypedef:
\_struct_typespec: (mul_inputs_t), line:383
|vpiTypedef:
\_enum_typespec: (opcodes_t), line:48
|vpiTypedef:
\_enum_typespec: (opcodes_trimmed_t), line:65
|vpiTypedef:
\_struct_typespec: (simulation_named_regfile), line:476
|vpiTypedef:
\_struct_typespec: (taiga_trace_events_t), line:442
|vpiTypedef:
\_struct_typespec: (to_l1_arbiter_packet), line:418
|vpiTypedef:
\_struct_typespec: (trace_outputs_t), line:469
|vpiTypedef:
\_logic_typespec: (unit_id_t), line:31
|vpiTypedef:
\_struct_typespec: (unit_writeback_t), line:295
|vpiTypedef:
\_enum_typespec: (vm_t), line:223
|uhdmallInterfaces:
\_interface: work@fetch_sub_unit_interface, file:third_party/cores/taiga/core/interfaces.sv, line:227, parent:work@div_unit_core_wrapper
|vpiDefName:work@fetch_sub_unit_interface
|vpiFullName:work@fetch_sub_unit_interface
|vpiModport:
\_modport: (fetch)
|vpiName:fetch
|vpiIODecl:
\_io_decl: (stage1_addr)
|vpiName:stage1_addr
|vpiDirection:2
|vpiIODecl:
\_io_decl: (stage2_addr)
|vpiName:stage2_addr
|vpiDirection:2
|vpiIODecl:
\_io_decl: (new_request)
|vpiName:new_request
|vpiDirection:2
|vpiIODecl:
\_io_decl: (flush)
|vpiName:flush
|vpiDirection:2
|vpiIODecl:
\_io_decl: (data_out)
|vpiName:data_out
|vpiDirection:1
|vpiIODecl:
\_io_decl: (data_valid)
|vpiName:data_valid
|vpiDirection:1
|vpiIODecl:
\_io_decl: (ready)
|vpiName:ready
|vpiDirection:1
|vpiModport:
\_modport: (sub_unit)
|vpiName:sub_unit
|vpiIODecl:
\_io_decl: (stage1_addr)
|vpiName:stage1_addr
|vpiDirection:1
|vpiIODecl:
\_io_decl: (stage2_addr)
|vpiName:stage2_addr
|vpiDirection:1
|vpiIODecl:
\_io_decl: (new_request)
|vpiName:new_request
|vpiDirection:1
|vpiIODecl:
\_io_decl: (flush)
|vpiName:flush
|vpiDirection:1
|vpiIODecl:
\_io_decl: (data_out)
|vpiName:data_out
|vpiDirection:2
|vpiIODecl:
\_io_decl: (data_valid)
|vpiName:data_valid
|vpiDirection:2
|vpiIODecl:
\_io_decl: (ready)
|vpiName:ready
|vpiDirection:2
|vpiNet:
\_logic_net: (stage1_addr), line:228
|vpiName:stage1_addr
|vpiFullName:work@fetch_sub_unit_interface.stage1_addr
|vpiNetType:36
|vpiNet:
\_logic_net: (stage2_addr), line:229
|vpiName:stage2_addr
|vpiFullName:work@fetch_sub_unit_interface.stage2_addr
|vpiNetType:36
|vpiNet:
\_logic_net: (data_out), line:231
|vpiName:data_out
|vpiFullName:work@fetch_sub_unit_interface.data_out
|vpiNetType:36
|vpiNet:
\_logic_net: (data_valid), line:232
|vpiName:data_valid
|vpiFullName:work@fetch_sub_unit_interface.data_valid
|vpiNetType:36
|vpiNet:
\_logic_net: (ready), line:233
|vpiName:ready
|vpiFullName:work@fetch_sub_unit_interface.ready
|vpiNetType:36
|vpiNet:
\_logic_net: (new_request), line:234
|vpiName:new_request
|vpiFullName:work@fetch_sub_unit_interface.new_request
|vpiNetType:36
|vpiNet:
\_logic_net: (flush), line:235
|vpiName:flush
|vpiFullName:work@fetch_sub_unit_interface.flush
|vpiNetType:36
|vpiTypedef:
\_struct_typespec: (alu_inputs_t), line:301
|vpiTypedef:
\_enum_typespec: (alu_logic_op_t), line:84
|vpiTypedef:
\_enum_typespec: (alu_op_t), line:91
|vpiTypedef:
\_enum_typespec: (alu_rs1_op_t), line:97
|vpiTypedef:
\_enum_typespec: (alu_rs2_op_t), line:104
|vpiTypedef:
\_struct_typespec: (amo_alu_inputs_t), line:356
|vpiTypedef:
\_struct_typespec: (amo_details_t), line:362
|vpiTypedef:
\_enum_typespec: (amo_t), line:354
|vpiTypedef:
\_struct_typespec: (branch_inputs_t), line:313
|vpiTypedef:
\_logic_typespec: (branch_predictor_metadata_t), line:32
|vpiTypedef:
\_struct_typespec: (branch_results_t), line:330
|vpiTypedef:
\_enum_typespec: (bus_type_t), line:86
|vpiTypedef:
\_struct_typespec: (csr_inputs_t), line:396
|vpiTypedef:
\_enum_typespec: (csr_op_t), line:218
|vpiTypedef:
\_enum_typespec: (csr_t), line:201
|vpiTypedef:
\_struct_typespec: (data_access_shared_inputs_t), line:427
|vpiTypedef:
\_struct_typespec: (div_inputs_t), line:389
|vpiTypedef:
\_enum_typespec: (div_type), line:66
|vpiTypedef:
\_enum_typespec: (exception_code_t), line:245
|vpiTypedef:
\_struct_typespec: (exception_packet_t), line:263
|vpiTypedef:
\_struct_typespec: (fetch_buffer_packet_t), line:276
|vpiTypedef:
\_enum_typespec: (fifo_type_t), line:440
|vpiTypedef:
\_enum_typespec: (fn3_arith_t), line:76
|vpiTypedef:
\_enum_typespec: (fn3_branch_t), line:126
|vpiTypedef:
\_enum_typespec: (fn3_csr_t), line:212
|vpiTypedef:
\_enum_typespec: (fn3_ls_t), line:115
|vpiTypedef:
\_enum_typespec: (fn3_mul_div_t), line:138
|vpiTypedef:
\_struct_typespec: (gc_inputs_t), line:404
|vpiTypedef:
\_struct_typespec: (inflight_instruction_packet), line:271
|vpiTypedef:
\_logic_typespec: (instruction_id_t), line:30
|vpiTypedef:
\_enum_typespec: (interrupt_code_t), line:261
|vpiTypedef:
\_struct_typespec: (l2_data_attributes_t), line:68
|vpiTypedef:
\_struct_typespec: (l2_mem_request_t), line:58
|vpiTypedef:
\_struct_typespec: (l2_mem_return_data_t), line:75
|vpiTypedef:
\_struct_typespec: (l2_request_t), line:49
|vpiTypedef:
\_struct_typespec: (l2_return_data_t), line:81
|vpiTypedef:
\_struct_typespec: (load_store_inputs_t), line:369
|vpiTypedef:
\_struct_typespec: (mul_inputs_t), line:383
|vpiTypedef:
\_enum_typespec: (opcodes_t), line:48
|vpiTypedef:
\_enum_typespec: (opcodes_trimmed_t), line:65
|vpiTypedef:
\_struct_typespec: (simulation_named_regfile), line:476
|vpiTypedef:
\_struct_typespec: (taiga_trace_events_t), line:442
|vpiTypedef:
\_struct_typespec: (to_l1_arbiter_packet), line:418
|vpiTypedef:
\_struct_typespec: (trace_outputs_t), line:469
|vpiTypedef:
\_logic_typespec: (unit_id_t), line:31
|vpiTypedef:
\_struct_typespec: (unit_writeback_t), line:295
|vpiTypedef:
\_enum_typespec: (vm_t), line:223
|uhdmallInterfaces:
\_interface: work@fifo_interface, file:third_party/cores/taiga/core/interfaces.sv, line:157, parent:work@div_unit_core_wrapper
|vpiDefName:work@fifo_interface
|vpiFullName:work@fifo_interface
|vpiModport:
\_modport: (dequeue)
|vpiName:dequeue
|vpiIODecl:
\_io_decl: (valid)
|vpiName:valid
|vpiDirection:1
|vpiIODecl:
\_io_decl: (data_out)
|vpiName:data_out
|vpiDirection:1
|vpiIODecl:
\_io_decl: (pop)
|vpiName:pop
|vpiDirection:2
|vpiModport:
\_modport: (enqueue)
|vpiName:enqueue
|vpiIODecl:
\_io_decl: (full)
|vpiName:full
|vpiDirection:1
|vpiIODecl:
\_io_decl: (data_in)
|vpiName:data_in
|vpiDirection:2
|vpiIODecl:
\_io_decl: (push)
|vpiName:push
|vpiDirection:2
|vpiIODecl:
\_io_decl: (supress_push)
|vpiName:supress_push
|vpiDirection:2
|vpiModport:
\_modport: (structure)
|vpiName:structure
|vpiIODecl:
\_io_decl: (push)
|vpiName:push
|vpiDirection:1
|vpiIODecl:
\_io_decl: (pop)
|vpiName:pop
|vpiDirection:1
|vpiIODecl:
\_io_decl: (data_in)
|vpiName:data_in
|vpiDirection:1
|vpiIODecl:
\_io_decl: (supress_push)
|vpiName:supress_push
|vpiDirection:1
|vpiIODecl:
\_io_decl: (data_out)
|vpiName:data_out
|vpiDirection:2
|vpiIODecl:
\_io_decl: (valid)
|vpiName:valid
|vpiDirection:2
|vpiIODecl:
\_io_decl: (full)
|vpiName:full
|vpiDirection:2
|vpiNet:
\_logic_net: (push), line:158
|vpiName:push
|vpiFullName:work@fifo_interface.push
|vpiNetType:36
|vpiNet:
\_logic_net: (pop), line:159
|vpiName:pop
|vpiFullName:work@fifo_interface.pop
|vpiNetType:36
|vpiNet:
\_logic_net: (data_in), line:160
|vpiName:data_in
|vpiFullName:work@fifo_interface.data_in
|vpiNetType:36
|vpiNet:
\_logic_net: (data_out), line:161
|vpiName:data_out
|vpiFullName:work@fifo_interface.data_out
|vpiNetType:36
|vpiNet:
\_logic_net: (valid), line:162
|vpiName:valid
|vpiFullName:work@fifo_interface.valid
|vpiNetType:36
|vpiNet:
\_logic_net: (full), line:163
|vpiName:full
|vpiFullName:work@fifo_interface.full
|vpiNetType:36
|vpiNet:
\_logic_net: (supress_push), line:164
|vpiName:supress_push
|vpiFullName:work@fifo_interface.supress_push
|vpiNetType:36
|vpiTypedef:
\_struct_typespec: (alu_inputs_t), line:301
|vpiTypedef:
\_enum_typespec: (alu_logic_op_t), line:84
|vpiTypedef:
\_enum_typespec: (alu_op_t), line:91
|vpiTypedef:
\_enum_typespec: (alu_rs1_op_t), line:97
|vpiTypedef:
\_enum_typespec: (alu_rs2_op_t), line:104
|vpiTypedef:
\_struct_typespec: (amo_alu_inputs_t), line:356
|vpiTypedef:
\_struct_typespec: (amo_details_t), line:362
|vpiTypedef:
\_enum_typespec: (amo_t), line:354
|vpiTypedef:
\_struct_typespec: (branch_inputs_t), line:313
|vpiTypedef:
\_logic_typespec: (branch_predictor_metadata_t), line:32
|vpiTypedef:
\_struct_typespec: (branch_results_t), line:330
|vpiTypedef:
\_enum_typespec: (bus_type_t), line:86
|vpiTypedef:
\_struct_typespec: (csr_inputs_t), line:396
|vpiTypedef:
\_enum_typespec: (csr_op_t), line:218
|vpiTypedef:
\_enum_typespec: (csr_t), line:201
|vpiTypedef:
\_struct_typespec: (data_access_shared_inputs_t), line:427
|vpiTypedef:
\_struct_typespec: (div_inputs_t), line:389
|vpiTypedef:
\_enum_typespec: (div_type), line:66
|vpiTypedef:
\_enum_typespec: (exception_code_t), line:245
|vpiTypedef:
\_struct_typespec: (exception_packet_t), line:263
|vpiTypedef:
\_struct_typespec: (fetch_buffer_packet_t), line:276
|vpiTypedef:
\_enum_typespec: (fifo_type_t), line:440
|vpiTypedef:
\_enum_typespec: (fn3_arith_t), line:76
|vpiTypedef:
\_enum_typespec: (fn3_branch_t), line:126
|vpiTypedef:
\_enum_typespec: (fn3_csr_t), line:212
|vpiTypedef:
\_enum_typespec: (fn3_ls_t), line:115
|vpiTypedef:
\_enum_typespec: (fn3_mul_div_t), line:138
|vpiTypedef:
\_struct_typespec: (gc_inputs_t), line:404
|vpiTypedef:
\_struct_typespec: (inflight_instruction_packet), line:271
|vpiTypedef:
\_logic_typespec: (instruction_id_t), line:30
|vpiTypedef:
\_enum_typespec: (interrupt_code_t), line:261
|vpiTypedef:
\_struct_typespec: (l2_data_attributes_t), line:68
|vpiTypedef:
\_struct_typespec: (l2_mem_request_t), line:58
|vpiTypedef:
\_struct_typespec: (l2_mem_return_data_t), line:75
|vpiTypedef:
\_struct_typespec: (l2_request_t), line:49
|vpiTypedef:
\_struct_typespec: (l2_return_data_t), line:81
|vpiTypedef:
\_struct_typespec: (load_store_inputs_t), line:369
|vpiTypedef:
\_struct_typespec: (mul_inputs_t), line:383
|vpiTypedef:
\_enum_typespec: (opcodes_t), line:48
|vpiTypedef:
\_enum_typespec: (opcodes_trimmed_t), line:65
|vpiTypedef:
\_struct_typespec: (simulation_named_regfile), line:476
|vpiTypedef:
\_struct_typespec: (taiga_trace_events_t), line:442
|vpiTypedef:
\_struct_typespec: (to_l1_arbiter_packet), line:418
|vpiTypedef:
\_struct_typespec: (trace_outputs_t), line:469
|vpiTypedef:
\_logic_typespec: (unit_id_t), line:31
|vpiTypedef:
\_struct_typespec: (unit_writeback_t), line:295
|vpiTypedef:
\_enum_typespec: (vm_t), line:223
|uhdmallInterfaces:
\_interface: work@l1_arbiter_request_interface, file:third_party/cores/taiga/core/external_interfaces.sv, line:122, parent:work@div_unit_core_wrapper
|vpiDefName:work@l1_arbiter_request_interface
|vpiFullName:work@l1_arbiter_request_interface
|vpiModport:
\_modport: (master)
|vpiName:master
|vpiIODecl:
\_io_decl: (addr)
|vpiName:addr
|vpiDirection:2
|vpiIODecl:
\_io_decl: (data)
|vpiName:data
|vpiDirection:2
|vpiIODecl:
\_io_decl: (rnw)
|vpiName:rnw
|vpiDirection:2
|vpiIODecl:
\_io_decl: (be)
|vpiName:be
|vpiDirection:2
|vpiIODecl:
\_io_decl: (size)
|vpiName:size
|vpiDirection:2
|vpiIODecl:
\_io_decl: (is_amo)
|vpiName:is_amo
|vpiDirection:2
|vpiIODecl:
\_io_decl: (amo)
|vpiName:amo
|vpiDirection:2
|vpiIODecl:
\_io_decl: (request)
|vpiName:request
|vpiDirection:2
|vpiIODecl:
\_io_decl: (ack)
|vpiName:ack
|vpiDirection:1
|vpiModport:
\_modport: (slave)
|vpiName:slave
|vpiIODecl:
\_io_decl: (addr)
|vpiName:addr
|vpiDirection:1
|vpiIODecl:
\_io_decl: (data)
|vpiName:data
|vpiDirection:1
|vpiIODecl:
\_io_decl: (rnw)
|vpiName:rnw
|vpiDirection:1
|vpiIODecl:
\_io_decl: (be)
|vpiName:be
|vpiDirection:1
|vpiIODecl:
\_io_decl: (size)
|vpiName:size
|vpiDirection:1
|vpiIODecl:
\_io_decl: (is_amo)
|vpiName:is_amo
|vpiDirection:1
|vpiIODecl:
\_io_decl: (amo)
|vpiName:amo
|vpiDirection:1
|vpiIODecl:
\_io_decl: (request)
|vpiName:request
|vpiDirection:1
|vpiIODecl:
\_io_decl: (ack)
|vpiName:ack
|vpiDirection:2
|vpiTaskFunc:
\_function: (to_l2), line:134
|vpiName:to_l2
|vpiFullName:work@l1_arbiter_request_interface.to_l2
|vpiReturn:
\_chandle_var: (l2_request_t), line:134
|vpiName:l2_request_t
|vpiIODecl:
\_io_decl: (sub_id)
|vpiName:sub_id
|vpiDirection:1
|vpiExpr:
\_bit_var: , line:134, parent:sub_id
|vpiFullName:sub_id
|vpiRange:
\_range: , line:134
|vpiLeftRange:
\_operation: , line:134
|vpiOpType:11
|vpiOperand:
\_ref_obj: (L2_SUB_ID_W), line:134
|vpiName:L2_SUB_ID_W
|vpiOperand:
\_constant: , line:134
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:134
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiStmt:
\_begin: , parent:to_l2
|vpiFullName:work@l1_arbiter_request_interface.to_l2
|vpiStmt:
\_assignment: , line:135
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (to_l2.addr), line:135
|vpiName:to_l2.addr
|vpiFullName:work@l1_arbiter_request_interface.to_l2.to_l2.addr
|vpiRhs:
\_part_select: , line:135, parent:addr
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (addr)
|vpiLeftRange:
\_constant: , line:135
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:135
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiStmt:
\_assignment: , line:136
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (to_l2.rnw), line:136
|vpiName:to_l2.rnw
|vpiFullName:work@l1_arbiter_request_interface.to_l2.to_l2.rnw
|vpiRhs:
\_ref_obj: (rnw), line:136
|vpiName:rnw
|vpiFullName:work@l1_arbiter_request_interface.to_l2.rnw
|vpiStmt:
\_assignment: , line:137
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (to_l2.be), line:137
|vpiName:to_l2.be
|vpiFullName:work@l1_arbiter_request_interface.to_l2.to_l2.be
|vpiRhs:
\_ref_obj: (be), line:137
|vpiName:be
|vpiFullName:work@l1_arbiter_request_interface.to_l2.be
|vpiStmt:
\_assignment: , line:138
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (to_l2.is_amo), line:138
|vpiName:to_l2.is_amo
|vpiFullName:work@l1_arbiter_request_interface.to_l2.to_l2.is_amo
|vpiRhs:
\_ref_obj: (is_amo), line:138
|vpiName:is_amo
|vpiFullName:work@l1_arbiter_request_interface.to_l2.is_amo
|vpiStmt:
\_assignment: , line:139
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (to_l2.amo_type_or_burst_size), line:139
|vpiName:to_l2.amo_type_or_burst_size
|vpiFullName:work@l1_arbiter_request_interface.to_l2.to_l2.amo_type_or_burst_size
|vpiRhs:
\_operation: , line:139
|vpiOpType:32
|vpiOperand:
\_ref_obj: (is_amo), line:139
|vpiName:is_amo
|vpiFullName:work@l1_arbiter_request_interface.to_l2.is_amo
|vpiOperand:
\_ref_obj: (amo), line:139
|vpiName:amo
|vpiFullName:work@l1_arbiter_request_interface.to_l2.amo
|vpiOperand:
\_ref_obj: (size), line:139
|vpiName:size
|vpiFullName:work@l1_arbiter_request_interface.to_l2.size
|vpiStmt:
\_assignment: , line:140
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (to_l2.sub_id), line:140
|vpiName:to_l2.sub_id
|vpiFullName:work@l1_arbiter_request_interface.to_l2.to_l2.sub_id
|vpiRhs:
\_ref_obj: (sub_id), line:140
|vpiName:sub_id
|vpiFullName:work@l1_arbiter_request_interface.to_l2.sub_id
|vpiNet:
\_logic_net: (addr), line:123
|vpiName:addr
|vpiFullName:work@l1_arbiter_request_interface.addr
|vpiNetType:36
|vpiNet:
\_logic_net: (data), line:124
|vpiName:data
|vpiFullName:work@l1_arbiter_request_interface.data
|vpiNetType:36
|vpiNet:
\_logic_net: (rnw), line:125
|vpiName:rnw
|vpiFullName:work@l1_arbiter_request_interface.rnw
|vpiNetType:36
|vpiNet:
\_logic_net: (be), line:126
|vpiName:be
|vpiFullName:work@l1_arbiter_request_interface.be
|vpiNetType:36
|vpiNet:
\_logic_net: (size), line:127
|vpiName:size
|vpiFullName:work@l1_arbiter_request_interface.size
|vpiNetType:36
|vpiNet:
\_logic_net: (is_amo), line:128
|vpiName:is_amo
|vpiFullName:work@l1_arbiter_request_interface.is_amo
|vpiNetType:36
|vpiNet:
\_logic_net: (amo), line:129
|vpiName:amo
|vpiFullName:work@l1_arbiter_request_interface.amo
|vpiNetType:36
|vpiNet:
\_logic_net: (request), line:131
|vpiName:request
|vpiFullName:work@l1_arbiter_request_interface.request
|vpiNetType:36
|vpiNet:
\_logic_net: (ack), line:132
|vpiName:ack
|vpiFullName:work@l1_arbiter_request_interface.ack
|vpiNetType:36
|vpiTypedef:
\_struct_typespec: (alu_inputs_t), line:301
|vpiTypedef:
\_enum_typespec: (alu_logic_op_t), line:84
|vpiTypedef:
\_enum_typespec: (alu_op_t), line:91
|vpiTypedef:
\_enum_typespec: (alu_rs1_op_t), line:97
|vpiTypedef:
\_enum_typespec: (alu_rs2_op_t), line:104
|vpiTypedef:
\_struct_typespec: (amo_alu_inputs_t), line:356
|vpiTypedef:
\_struct_typespec: (amo_details_t), line:362
|vpiTypedef:
\_enum_typespec: (amo_t), line:354
|vpiTypedef:
\_struct_typespec: (branch_inputs_t), line:313
|vpiTypedef:
\_logic_typespec: (branch_predictor_metadata_t), line:32
|vpiTypedef:
\_struct_typespec: (branch_results_t), line:330
|vpiTypedef:
\_enum_typespec: (bus_type_t), line:86
|vpiTypedef:
\_struct_typespec: (csr_inputs_t), line:396
|vpiTypedef:
\_enum_typespec: (csr_op_t), line:218
|vpiTypedef:
\_enum_typespec: (csr_t), line:201
|vpiTypedef:
\_struct_typespec: (data_access_shared_inputs_t), line:427
|vpiTypedef:
\_struct_typespec: (div_inputs_t), line:389
|vpiTypedef:
\_enum_typespec: (div_type), line:66
|vpiTypedef:
\_enum_typespec: (exception_code_t), line:245
|vpiTypedef:
\_struct_typespec: (exception_packet_t), line:263
|vpiTypedef:
\_struct_typespec: (fetch_buffer_packet_t), line:276
|vpiTypedef:
\_enum_typespec: (fifo_type_t), line:440
|vpiTypedef:
\_enum_typespec: (fn3_arith_t), line:76
|vpiTypedef:
\_enum_typespec: (fn3_branch_t), line:126
|vpiTypedef:
\_enum_typespec: (fn3_csr_t), line:212
|vpiTypedef:
\_enum_typespec: (fn3_ls_t), line:115
|vpiTypedef:
\_enum_typespec: (fn3_mul_div_t), line:138
|vpiTypedef:
\_struct_typespec: (gc_inputs_t), line:404
|vpiTypedef:
\_struct_typespec: (inflight_instruction_packet), line:271
|vpiTypedef:
\_logic_typespec: (instruction_id_t), line:30
|vpiTypedef:
\_enum_typespec: (interrupt_code_t), line:261
|vpiTypedef:
\_struct_typespec: (l2_data_attributes_t), line:68
|vpiTypedef:
\_struct_typespec: (l2_mem_request_t), line:58
|vpiTypedef:
\_struct_typespec: (l2_mem_return_data_t), line:75
|vpiTypedef:
\_struct_typespec: (l2_request_t), line:49
|vpiTypedef:
\_struct_typespec: (l2_return_data_t), line:81
|vpiTypedef:
\_struct_typespec: (load_store_inputs_t), line:369
|vpiTypedef:
\_struct_typespec: (mul_inputs_t), line:383
|vpiTypedef:
\_enum_typespec: (opcodes_t), line:48
|vpiTypedef:
\_enum_typespec: (opcodes_trimmed_t), line:65
|vpiTypedef:
\_struct_typespec: (simulation_named_regfile), line:476
|vpiTypedef:
\_struct_typespec: (taiga_trace_events_t), line:442
|vpiTypedef:
\_struct_typespec: (to_l1_arbiter_packet), line:418
|vpiTypedef:
\_struct_typespec: (trace_outputs_t), line:469
|vpiTypedef:
\_logic_typespec: (unit_id_t), line:31
|vpiTypedef:
\_struct_typespec: (unit_writeback_t), line:295
|vpiTypedef:
\_enum_typespec: (vm_t), line:223
|uhdmallInterfaces:
\_interface: work@l1_arbiter_return_interface, file:third_party/cores/taiga/core/external_interfaces.sv, line:148, parent:work@div_unit_core_wrapper
|vpiDefName:work@l1_arbiter_return_interface
|vpiFullName:work@l1_arbiter_return_interface
|vpiModport:
\_modport: (master)
|vpiName:master
|vpiIODecl:
\_io_decl: (inv_addr)
|vpiName:inv_addr
|vpiDirection:1
|vpiIODecl:
\_io_decl: (inv_valid)
|vpiName:inv_valid
|vpiDirection:1
|vpiIODecl:
\_io_decl: (data)
|vpiName:data
|vpiDirection:1
|vpiIODecl:
\_io_decl: (data_valid)
|vpiName:data_valid
|vpiDirection:1
|vpiIODecl:
\_io_decl: (inv_ack)
|vpiName:inv_ack
|vpiDirection:2
|vpiModport:
\_modport: (slave)
|vpiName:slave
|vpiIODecl:
\_io_decl: (inv_addr)
|vpiName:inv_addr
|vpiDirection:2
|vpiIODecl:
\_io_decl: (inv_valid)
|vpiName:inv_valid
|vpiDirection:2
|vpiIODecl:
\_io_decl: (data)
|vpiName:data
|vpiDirection:2
|vpiIODecl:
\_io_decl: (data_valid)
|vpiName:data_valid
|vpiDirection:2
|vpiIODecl:
\_io_decl: (inv_ack)
|vpiName:inv_ack
|vpiDirection:1
|vpiNet:
\_logic_net: (inv_addr), line:149
|vpiName:inv_addr
|vpiFullName:work@l1_arbiter_return_interface.inv_addr
|vpiNetType:36
|vpiNet:
\_logic_net: (inv_valid), line:150
|vpiName:inv_valid
|vpiFullName:work@l1_arbiter_return_interface.inv_valid
|vpiNetType:36
|vpiNet:
\_logic_net: (inv_ack), line:151
|vpiName:inv_ack
|vpiFullName:work@l1_arbiter_return_interface.inv_ack
|vpiNetType:36
|vpiNet:
\_logic_net: (data), line:152
|vpiName:data
|vpiFullName:work@l1_arbiter_return_interface.data
|vpiNetType:36
|vpiNet:
\_logic_net: (data_valid), line:153
|vpiName:data_valid
|vpiFullName:work@l1_arbiter_return_interface.data_valid
|vpiNetType:36
|vpiTypedef:
\_struct_typespec: (alu_inputs_t), line:301
|vpiTypedef:
\_enum_typespec: (alu_logic_op_t), line:84
|vpiTypedef:
\_enum_typespec: (alu_op_t), line:91
|vpiTypedef:
\_enum_typespec: (alu_rs1_op_t), line:97
|vpiTypedef:
\_enum_typespec: (alu_rs2_op_t), line:104
|vpiTypedef:
\_struct_typespec: (amo_alu_inputs_t), line:356
|vpiTypedef:
\_struct_typespec: (amo_details_t), line:362
|vpiTypedef:
\_enum_typespec: (amo_t), line:354
|vpiTypedef:
\_struct_typespec: (branch_inputs_t), line:313
|vpiTypedef:
\_logic_typespec: (branch_predictor_metadata_t), line:32
|vpiTypedef:
\_struct_typespec: (branch_results_t), line:330
|vpiTypedef:
\_enum_typespec: (bus_type_t), line:86
|vpiTypedef:
\_struct_typespec: (csr_inputs_t), line:396
|vpiTypedef:
\_enum_typespec: (csr_op_t), line:218
|vpiTypedef:
\_enum_typespec: (csr_t), line:201
|vpiTypedef:
\_struct_typespec: (data_access_shared_inputs_t), line:427
|vpiTypedef:
\_struct_typespec: (div_inputs_t), line:389
|vpiTypedef:
\_enum_typespec: (div_type), line:66
|vpiTypedef:
\_enum_typespec: (exception_code_t), line:245
|vpiTypedef:
\_struct_typespec: (exception_packet_t), line:263
|vpiTypedef:
\_struct_typespec: (fetch_buffer_packet_t), line:276
|vpiTypedef:
\_enum_typespec: (fifo_type_t), line:440
|vpiTypedef:
\_enum_typespec: (fn3_arith_t), line:76
|vpiTypedef:
\_enum_typespec: (fn3_branch_t), line:126
|vpiTypedef:
\_enum_typespec: (fn3_csr_t), line:212
|vpiTypedef:
\_enum_typespec: (fn3_ls_t), line:115
|vpiTypedef:
\_enum_typespec: (fn3_mul_div_t), line:138
|vpiTypedef:
\_struct_typespec: (gc_inputs_t), line:404
|vpiTypedef:
\_struct_typespec: (inflight_instruction_packet), line:271
|vpiTypedef:
\_logic_typespec: (instruction_id_t), line:30
|vpiTypedef:
\_enum_typespec: (interrupt_code_t), line:261
|vpiTypedef:
\_struct_typespec: (l2_data_attributes_t), line:68
|vpiTypedef:
\_struct_typespec: (l2_mem_request_t), line:58
|vpiTypedef:
\_struct_typespec: (l2_mem_return_data_t), line:75
|vpiTypedef:
\_struct_typespec: (l2_request_t), line:49
|vpiTypedef:
\_struct_typespec: (l2_return_data_t), line:81
|vpiTypedef:
\_struct_typespec: (load_store_inputs_t), line:369
|vpiTypedef:
\_struct_typespec: (mul_inputs_t), line:383
|vpiTypedef:
\_enum_typespec: (opcodes_t), line:48
|vpiTypedef:
\_enum_typespec: (opcodes_trimmed_t), line:65
|vpiTypedef:
\_struct_typespec: (simulation_named_regfile), line:476
|vpiTypedef:
\_struct_typespec: (taiga_trace_events_t), line:442
|vpiTypedef:
\_struct_typespec: (to_l1_arbiter_packet), line:418
|vpiTypedef:
\_struct_typespec: (trace_outputs_t), line:469
|vpiTypedef:
\_logic_typespec: (unit_id_t), line:31
|vpiTypedef:
\_struct_typespec: (unit_writeback_t), line:295
|vpiTypedef:
\_enum_typespec: (vm_t), line:223
|uhdmallInterfaces:
\_interface: work@l2_arbitration_interface, file:third_party/cores/taiga/l2_arbiter/l2_interfaces.sv, line:38, parent:work@div_unit_core_wrapper
|vpiDefName:work@l2_arbitration_interface
|vpiFullName:work@l2_arbitration_interface
|vpiModport:
\_modport: (master)
|vpiName:master
|vpiIODecl:
\_io_decl: (requests)
|vpiName:requests
|vpiDirection:2
|vpiIODecl:
\_io_decl: (strobe)
|vpiName:strobe
|vpiDirection:2
|vpiIODecl:
\_io_decl: (grantee_i)
|vpiName:grantee_i
|vpiDirection:1
|vpiIODecl:
\_io_decl: (grantee_v)
|vpiName:grantee_v
|vpiDirection:1
|vpiIODecl:
\_io_decl: (grantee_valid)
|vpiName:grantee_valid
|vpiDirection:1
|vpiModport:
\_modport: (slave)
|vpiName:slave
|vpiIODecl:
\_io_decl: (requests)
|vpiName:requests
|vpiDirection:1
|vpiIODecl:
\_io_decl: (strobe)
|vpiName:strobe
|vpiDirection:1
|vpiIODecl:
\_io_decl: (grantee_i)
|vpiName:grantee_i
|vpiDirection:2
|vpiIODecl:
\_io_decl: (grantee_v)
|vpiName:grantee_v
|vpiDirection:2
|vpiIODecl:
\_io_decl: (grantee_valid)
|vpiName:grantee_valid
|vpiDirection:2
|vpiNet:
\_logic_net: (requests), line:39
|vpiName:requests
|vpiFullName:work@l2_arbitration_interface.requests
|vpiNetType:36
|vpiNet:
\_logic_net: (grantee_i), line:40
|vpiName:grantee_i
|vpiFullName:work@l2_arbitration_interface.grantee_i
|vpiNetType:36
|vpiNet:
\_logic_net: (grantee_v), line:41
|vpiName:grantee_v
|vpiFullName:work@l2_arbitration_interface.grantee_v
|vpiNetType:36
|vpiNet:
\_logic_net: (grantee_valid), line:42
|vpiName:grantee_valid
|vpiFullName:work@l2_arbitration_interface.grantee_valid
|vpiNetType:36
|vpiNet:
\_logic_net: (strobe), line:43
|vpiName:strobe
|vpiFullName:work@l2_arbitration_interface.strobe
|vpiNetType:36
|vpiTypedef:
\_struct_typespec: (l2_data_attributes_t), line:68
|vpiTypedef:
\_struct_typespec: (l2_mem_request_t), line:58
|vpiTypedef:
\_struct_typespec: (l2_mem_return_data_t), line:75
|vpiTypedef:
\_struct_typespec: (l2_request_t), line:49
|vpiTypedef:
\_struct_typespec: (l2_return_data_t), line:81
|uhdmallInterfaces:
\_interface: work@l2_fifo_interface, file:third_party/cores/taiga/l2_arbiter/l2_interfaces.sv, line:25, parent:work@div_unit_core_wrapper
|vpiDefName:work@l2_fifo_interface
|vpiFullName:work@l2_fifo_interface
|vpiModport:
\_modport: (dequeue)
|vpiName:dequeue
|vpiIODecl:
\_io_decl: (valid)
|vpiName:valid
|vpiDirection:1
|vpiIODecl:
\_io_decl: (data_out)
|vpiName:data_out
|vpiDirection:1
|vpiIODecl:
\_io_decl: (pop)
|vpiName:pop
|vpiDirection:2
|vpiModport:
\_modport: (enqueue)
|vpiName:enqueue
|vpiIODecl:
\_io_decl: (full)
|vpiName:full
|vpiDirection:1
|vpiIODecl:
\_io_decl: (empty)
|vpiName:empty
|vpiDirection:1
|vpiIODecl:
\_io_decl: (data_in)
|vpiName:data_in
|vpiDirection:2
|vpiIODecl:
\_io_decl: (push)
|vpiName:push
|vpiDirection:2
|vpiModport:
\_modport: (structure)
|vpiName:structure
|vpiIODecl:
\_io_decl: (push)
|vpiName:push
|vpiDirection:1
|vpiIODecl:
\_io_decl: (pop)
|vpiName:pop
|vpiDirection:1
|vpiIODecl:
\_io_decl: (data_in)
|vpiName:data_in
|vpiDirection:1
|vpiIODecl:
\_io_decl: (data_out)
|vpiName:data_out
|vpiDirection:2
|vpiIODecl:
\_io_decl: (valid)
|vpiName:valid
|vpiDirection:2
|vpiIODecl:
\_io_decl: (full)
|vpiName:full
|vpiDirection:2
|vpiIODecl:
\_io_decl: (empty)
|vpiName:empty
|vpiDirection:2
|vpiNet:
\_logic_net: (push), line:26
|vpiName:push
|vpiFullName:work@l2_fifo_interface.push
|vpiNetType:36
|vpiNet:
\_logic_net: (pop), line:27
|vpiName:pop
|vpiFullName:work@l2_fifo_interface.pop
|vpiNetType:36
|vpiNet:
\_logic_net: (data_in), line:28
|vpiName:data_in
|vpiFullName:work@l2_fifo_interface.data_in
|vpiNetType:36
|vpiNet:
\_logic_net: (data_out), line:29
|vpiName:data_out
|vpiFullName:work@l2_fifo_interface.data_out
|vpiNetType:36
|vpiNet:
\_logic_net: (valid), line:30
|vpiName:valid
|vpiFullName:work@l2_fifo_interface.valid
|vpiNetType:36
|vpiNet:
\_logic_net: (full), line:31
|vpiName:full
|vpiFullName:work@l2_fifo_interface.full
|vpiNetType:36
|vpiNet:
\_logic_net: (empty), line:32
|vpiName:empty
|vpiFullName:work@l2_fifo_interface.empty
|vpiNetType:36
|vpiTypedef:
\_struct_typespec: (l2_data_attributes_t), line:68
|vpiTypedef:
\_struct_typespec: (l2_mem_request_t), line:58
|vpiTypedef:
\_struct_typespec: (l2_mem_return_data_t), line:75
|vpiTypedef:
\_struct_typespec: (l2_request_t), line:49
|vpiTypedef:
\_struct_typespec: (l2_return_data_t), line:81
|uhdmallInterfaces:
\_interface: work@l2_memory_interface, file:third_party/cores/taiga/l2_arbiter/l2_external_interfaces.sv, line:69, parent:work@div_unit_core_wrapper
|vpiDefName:work@l2_memory_interface
|vpiFullName:work@l2_memory_interface
|vpiModport:
\_modport: (master)
|vpiName:master
|vpiIODecl:
\_io_decl: (addr)
|vpiName:addr
|vpiDirection:2
|vpiIODecl:
\_io_decl: (be)
|vpiName:be
|vpiDirection:2
|vpiIODecl:
\_io_decl: (rnw)
|vpiName:rnw
|vpiDirection:2
|vpiIODecl:
\_io_decl: (is_amo)
|vpiName:is_amo
|vpiDirection:2
|vpiIODecl:
\_io_decl: (amo_type_or_burst_size)
|vpiName:amo_type_or_burst_size
|vpiDirection:2
|vpiIODecl:
\_io_decl: (id)
|vpiName:id
|vpiDirection:2
|vpiIODecl:
\_io_decl: (request_valid)
|vpiName:request_valid
|vpiDirection:2
|vpiIODecl:
\_io_decl: (abort)
|vpiName:abort
|vpiDirection:2
|vpiIODecl:
\_io_decl: (request_pop)
|vpiName:request_pop
|vpiDirection:1
|vpiIODecl:
\_io_decl: (wr_data)
|vpiName:wr_data
|vpiDirection:2
|vpiIODecl:
\_io_decl: (wr_data_valid)
|vpiName:wr_data_valid
|vpiDirection:2
|vpiIODecl:
\_io_decl: (wr_data_read)
|vpiName:wr_data_read
|vpiDirection:1
|vpiIODecl:
\_io_decl: (rd_data)
|vpiName:rd_data
|vpiDirection:1
|vpiIODecl:
\_io_decl: (rd_id)
|vpiName:rd_id
|vpiDirection:1
|vpiIODecl:
\_io_decl: (rd_data_valid)
|vpiName:rd_data_valid
|vpiDirection:1
|vpiModport:
\_modport: (slave)
|vpiName:slave
|vpiIODecl:
\_io_decl: (addr)
|vpiName:addr
|vpiDirection:1
|vpiIODecl:
\_io_decl: (be)
|vpiName:be
|vpiDirection:1
|vpiIODecl:
\_io_decl: (rnw)
|vpiName:rnw
|vpiDirection:1
|vpiIODecl:
\_io_decl: (is_amo)
|vpiName:is_amo
|vpiDirection:1
|vpiIODecl:
\_io_decl: (amo_type_or_burst_size)
|vpiName:amo_type_or_burst_size
|vpiDirection:1
|vpiIODecl:
\_io_decl: (id)
|vpiName:id
|vpiDirection:1
|vpiIODecl:
\_io_decl: (request_valid)
|vpiName:request_valid
|vpiDirection:1
|vpiIODecl:
\_io_decl: (abort)
|vpiName:abort
|vpiDirection:1
|vpiIODecl:
\_io_decl: (request_pop)
|vpiName:request_pop
|vpiDirection:2
|vpiIODecl:
\_io_decl: (wr_data)
|vpiName:wr_data
|vpiDirection:1
|vpiIODecl:
\_io_decl: (wr_data_valid)
|vpiName:wr_data_valid
|vpiDirection:1
|vpiIODecl:
\_io_decl: (wr_data_read)
|vpiName:wr_data_read
|vpiDirection:2
|vpiIODecl:
\_io_decl: (rd_data)
|vpiName:rd_data
|vpiDirection:2
|vpiIODecl:
\_io_decl: (rd_id)
|vpiName:rd_id
|vpiDirection:2
|vpiIODecl:
\_io_decl: (rd_data_valid)
|vpiName:rd_data_valid
|vpiDirection:2
|vpiNet:
\_logic_net: (addr), line:70
|vpiName:addr
|vpiFullName:work@l2_memory_interface.addr
|vpiNetType:36
|vpiNet:
\_logic_net: (be), line:71
|vpiName:be
|vpiFullName:work@l2_memory_interface.be
|vpiNetType:36
|vpiNet:
\_logic_net: (rnw), line:72
|vpiName:rnw
|vpiFullName:work@l2_memory_interface.rnw
|vpiNetType:36
|vpiNet:
\_logic_net: (is_amo), line:73
|vpiName:is_amo
|vpiFullName:work@l2_memory_interface.is_amo
|vpiNetType:36
|vpiNet:
\_logic_net: (amo_type_or_burst_size), line:74
|vpiName:amo_type_or_burst_size
|vpiFullName:work@l2_memory_interface.amo_type_or_burst_size
|vpiNetType:36
|vpiNet:
\_logic_net: (id), line:75
|vpiName:id
|vpiFullName:work@l2_memory_interface.id
|vpiNetType:36
|vpiNet:
\_logic_net: (request_pop), line:77
|vpiName:request_pop
|vpiFullName:work@l2_memory_interface.request_pop
|vpiNetType:36
|vpiNet:
\_logic_net: (request_valid), line:78
|vpiName:request_valid
|vpiFullName:work@l2_memory_interface.request_valid
|vpiNetType:36
|vpiNet:
\_logic_net: (abort), line:80
|vpiName:abort
|vpiFullName:work@l2_memory_interface.abort
|vpiNetType:36
|vpiNet:
\_logic_net: (wr_data), line:82
|vpiName:wr_data
|vpiFullName:work@l2_memory_interface.wr_data
|vpiNetType:36
|vpiNet:
\_logic_net: (wr_data_valid), line:83
|vpiName:wr_data_valid
|vpiFullName:work@l2_memory_interface.wr_data_valid
|vpiNetType:36
|vpiNet:
\_logic_net: (wr_data_read), line:84
|vpiName:wr_data_read
|vpiFullName:work@l2_memory_interface.wr_data_read
|vpiNetType:36
|vpiNet:
\_logic_net: (rd_data), line:86
|vpiName:rd_data
|vpiFullName:work@l2_memory_interface.rd_data
|vpiNetType:36
|vpiNet:
\_logic_net: (rd_id), line:87
|vpiName:rd_id
|vpiFullName:work@l2_memory_interface.rd_id
|vpiNetType:36
|vpiNet:
\_logic_net: (rd_data_valid), line:88
|vpiName:rd_data_valid
|vpiFullName:work@l2_memory_interface.rd_data_valid
|vpiNetType:36
|vpiTypedef:
\_struct_typespec: (l2_data_attributes_t), line:68
|vpiTypedef:
\_struct_typespec: (l2_mem_request_t), line:58
|vpiTypedef:
\_struct_typespec: (l2_mem_return_data_t), line:75
|vpiTypedef:
\_struct_typespec: (l2_request_t), line:49
|vpiTypedef:
\_struct_typespec: (l2_return_data_t), line:81
|uhdmallInterfaces:
\_interface: work@l2_requester_interface, file:third_party/cores/taiga/l2_arbiter/l2_external_interfaces.sv, line:25, parent:work@div_unit_core_wrapper
|vpiDefName:work@l2_requester_interface
|vpiFullName:work@l2_requester_interface
|vpiModport:
\_modport: (master)
|vpiName:master
|vpiIODecl:
\_io_decl: (addr)
|vpiName:addr
|vpiDirection:2
|vpiIODecl:
\_io_decl: (be)
|vpiName:be
|vpiDirection:2
|vpiIODecl:
\_io_decl: (rnw)
|vpiName:rnw
|vpiDirection:2
|vpiIODecl:
\_io_decl: (is_amo)
|vpiName:is_amo
|vpiDirection:2
|vpiIODecl:
\_io_decl: (amo_type_or_burst_size)
|vpiName:amo_type_or_burst_size
|vpiDirection:2
|vpiIODecl:
\_io_decl: (sub_id)
|vpiName:sub_id
|vpiDirection:2
|vpiIODecl:
\_io_decl: (request_push)
|vpiName:request_push
|vpiDirection:2
|vpiIODecl:
\_io_decl: (request_full)
|vpiName:request_full
|vpiDirection:1
|vpiIODecl:
\_io_decl: (inv_addr)
|vpiName:inv_addr
|vpiDirection:1
|vpiIODecl:
\_io_decl: (inv_valid)
|vpiName:inv_valid
|vpiDirection:1
|vpiIODecl:
\_io_decl: (inv_ack)
|vpiName:inv_ack
|vpiDirection:2
|vpiIODecl:
\_io_decl: (con_result)
|vpiName:con_result
|vpiDirection:1
|vpiIODecl:
\_io_decl: (con_valid)
|vpiName:con_valid
|vpiDirection:1
|vpiIODecl:
\_io_decl: (wr_data)
|vpiName:wr_data
|vpiDirection:2
|vpiIODecl:
\_io_decl: (wr_data_push)
|vpiName:wr_data_push
|vpiDirection:2
|vpiIODecl:
\_io_decl: (data_full)
|vpiName:data_full
|vpiDirection:1
|vpiIODecl:
\_io_decl: (rd_data)
|vpiName:rd_data
|vpiDirection:1
|vpiIODecl:
\_io_decl: (rd_sub_id)
|vpiName:rd_sub_id
|vpiDirection:1
|vpiIODecl:
\_io_decl: (rd_data_valid)
|vpiName:rd_data_valid
|vpiDirection:1
|vpiIODecl:
\_io_decl: (rd_data_ack)
|vpiName:rd_data_ack
|vpiDirection:2
|vpiModport:
\_modport: (slave)
|vpiName:slave
|vpiIODecl:
\_io_decl: (addr)
|vpiName:addr
|vpiDirection:1
|vpiIODecl:
\_io_decl: (be)
|vpiName:be
|vpiDirection:1
|vpiIODecl:
\_io_decl: (rnw)
|vpiName:rnw
|vpiDirection:1
|vpiIODecl:
\_io_decl: (is_amo)
|vpiName:is_amo
|vpiDirection:1
|vpiIODecl:
\_io_decl: (amo_type_or_burst_size)
|vpiName:amo_type_or_burst_size
|vpiDirection:1
|vpiIODecl:
\_io_decl: (sub_id)
|vpiName:sub_id
|vpiDirection:1
|vpiIODecl:
\_io_decl: (request_push)
|vpiName:request_push
|vpiDirection:1
|vpiIODecl:
\_io_decl: (request_full)
|vpiName:request_full
|vpiDirection:2
|vpiIODecl:
\_io_decl: (inv_addr)
|vpiName:inv_addr
|vpiDirection:2
|vpiIODecl:
\_io_decl: (inv_valid)
|vpiName:inv_valid
|vpiDirection:2
|vpiIODecl:
\_io_decl: (inv_ack)
|vpiName:inv_ack
|vpiDirection:1
|vpiIODecl:
\_io_decl: (con_result)
|vpiName:con_result
|vpiDirection:2
|vpiIODecl:
\_io_decl: (con_valid)
|vpiName:con_valid
|vpiDirection:2
|vpiIODecl:
\_io_decl: (wr_data)
|vpiName:wr_data
|vpiDirection:1
|vpiIODecl:
\_io_decl: (wr_data_push)
|vpiName:wr_data_push
|vpiDirection:1
|vpiIODecl:
\_io_decl: (data_full)
|vpiName:data_full
|vpiDirection:2
|vpiIODecl:
\_io_decl: (rd_data)
|vpiName:rd_data
|vpiDirection:2
|vpiIODecl:
\_io_decl: (rd_sub_id)
|vpiName:rd_sub_id
|vpiDirection:2
|vpiIODecl:
\_io_decl: (rd_data_valid)
|vpiName:rd_data_valid
|vpiDirection:2
|vpiIODecl:
\_io_decl: (rd_data_ack)
|vpiName:rd_data_ack
|vpiDirection:1
|vpiNet:
\_logic_net: (addr), line:27
|vpiName:addr
|vpiFullName:work@l2_requester_interface.addr
|vpiNetType:36
|vpiNet:
\_logic_net: (be), line:28
|vpiName:be
|vpiFullName:work@l2_requester_interface.be
|vpiNetType:36
|vpiNet:
\_logic_net: (rnw), line:29
|vpiName:rnw
|vpiFullName:work@l2_requester_interface.rnw
|vpiNetType:36
|vpiNet:
\_logic_net: (is_amo), line:30
|vpiName:is_amo
|vpiFullName:work@l2_requester_interface.is_amo
|vpiNetType:36
|vpiNet:
\_logic_net: (amo_type_or_burst_size), line:31
|vpiName:amo_type_or_burst_size
|vpiFullName:work@l2_requester_interface.amo_type_or_burst_size
|vpiNetType:36
|vpiNet:
\_logic_net: (sub_id), line:32
|vpiName:sub_id
|vpiFullName:work@l2_requester_interface.sub_id
|vpiNetType:36
|vpiNet:
\_logic_net: (request_push), line:34
|vpiName:request_push
|vpiFullName:work@l2_requester_interface.request_push
|vpiNetType:36
|vpiNet:
\_logic_net: (request_full), line:35
|vpiName:request_full
|vpiFullName:work@l2_requester_interface.request_full
|vpiNetType:36
|vpiNet:
\_logic_net: (inv_addr), line:37
|vpiName:inv_addr
|vpiFullName:work@l2_requester_interface.inv_addr
|vpiNetType:36
|vpiNet:
\_logic_net: (inv_valid), line:38
|vpiName:inv_valid
|vpiFullName:work@l2_requester_interface.inv_valid
|vpiNetType:36
|vpiNet:
\_logic_net: (inv_ack), line:39
|vpiName:inv_ack
|vpiFullName:work@l2_requester_interface.inv_ack
|vpiNetType:36
|vpiNet:
\_logic_net: (con_result), line:41
|vpiName:con_result
|vpiFullName:work@l2_requester_interface.con_result
|vpiNetType:36
|vpiNet:
\_logic_net: (con_valid), line:42
|vpiName:con_valid
|vpiFullName:work@l2_requester_interface.con_valid
|vpiNetType:36
|vpiNet:
\_logic_net: (wr_data), line:44
|vpiName:wr_data
|vpiFullName:work@l2_requester_interface.wr_data
|vpiNetType:36
|vpiNet:
\_logic_net: (wr_data_push), line:45
|vpiName:wr_data_push
|vpiFullName:work@l2_requester_interface.wr_data_push
|vpiNetType:36
|vpiNet:
\_logic_net: (data_full), line:46
|vpiName:data_full
|vpiFullName:work@l2_requester_interface.data_full
|vpiNetType:36
|vpiNet:
\_logic_net: (rd_data), line:48
|vpiName:rd_data
|vpiFullName:work@l2_requester_interface.rd_data
|vpiNetType:36
|vpiNet:
\_logic_net: (rd_sub_id), line:49
|vpiName:rd_sub_id
|vpiFullName:work@l2_requester_interface.rd_sub_id
|vpiNetType:36
|vpiNet:
\_logic_net: (rd_data_valid), line:50
|vpiName:rd_data_valid
|vpiFullName:work@l2_requester_interface.rd_data_valid
|vpiNetType:36
|vpiNet:
\_logic_net: (rd_data_ack), line:51
|vpiName:rd_data_ack
|vpiFullName:work@l2_requester_interface.rd_data_ack
|vpiNetType:36
|vpiTypedef:
\_struct_typespec: (l2_data_attributes_t), line:68
|vpiTypedef:
\_struct_typespec: (l2_mem_request_t), line:58
|vpiTypedef:
\_struct_typespec: (l2_mem_return_data_t), line:75
|vpiTypedef:
\_struct_typespec: (l2_request_t), line:49
|vpiTypedef:
\_struct_typespec: (l2_return_data_t), line:81
|uhdmallInterfaces:
\_interface: work@local_memory_interface, file:third_party/cores/taiga/local_memory/local_memory_interface.sv, line:24, parent:work@div_unit_core_wrapper
|vpiDefName:work@local_memory_interface
|vpiFullName:work@local_memory_interface
|vpiModport:
\_modport: (master)
|vpiName:master
|vpiIODecl:
\_io_decl: (addr)
|vpiName:addr
|vpiDirection:2
|vpiIODecl:
\_io_decl: (en)
|vpiName:en
|vpiDirection:2
|vpiIODecl:
\_io_decl: (be)
|vpiName:be
|vpiDirection:2
|vpiIODecl:
\_io_decl: (data_in)
|vpiName:data_in
|vpiDirection:2
|vpiIODecl:
\_io_decl: (data_out)
|vpiName:data_out
|vpiDirection:1
|vpiModport:
\_modport: (slave)
|vpiName:slave
|vpiIODecl:
\_io_decl: (addr)
|vpiName:addr
|vpiDirection:1
|vpiIODecl:
\_io_decl: (en)
|vpiName:en
|vpiDirection:1
|vpiIODecl:
\_io_decl: (be)
|vpiName:be
|vpiDirection:1
|vpiIODecl:
\_io_decl: (data_in)
|vpiName:data_in
|vpiDirection:1
|vpiIODecl:
\_io_decl: (data_out)
|vpiName:data_out
|vpiDirection:2
|vpiNet:
\_logic_net: (addr), line:25
|vpiName:addr
|vpiFullName:work@local_memory_interface.addr
|vpiNetType:36
|vpiNet:
\_logic_net: (en), line:26
|vpiName:en
|vpiFullName:work@local_memory_interface.en
|vpiNetType:36
|vpiNet:
\_logic_net: (be), line:27
|vpiName:be
|vpiFullName:work@local_memory_interface.be
|vpiNetType:36
|vpiNet:
\_logic_net: (data_in), line:28
|vpiName:data_in
|vpiFullName:work@local_memory_interface.data_in
|vpiNetType:36
|vpiNet:
\_logic_net: (data_out), line:29
|vpiName:data_out
|vpiFullName:work@local_memory_interface.data_out
|vpiNetType:36
|uhdmallInterfaces:
\_interface: work@ls_sub_unit_interface, file:third_party/cores/taiga/core/interfaces.sv, line:212, parent:work@div_unit_core_wrapper
|vpiDefName:work@ls_sub_unit_interface
|vpiFullName:work@ls_sub_unit_interface
|vpiModport:
\_modport: (ls)
|vpiName:ls
|vpiIODecl:
\_io_decl: (new_request)
|vpiName:new_request
|vpiDirection:2
|vpiIODecl:
\_io_decl: (data_valid)
|vpiName:data_valid
|vpiDirection:1
|vpiIODecl:
\_io_decl: (ready)
|vpiName:ready
|vpiDirection:1
|vpiModport:
\_modport: (sub_unit)
|vpiName:sub_unit
|vpiIODecl:
\_io_decl: (new_request)
|vpiName:new_request
|vpiDirection:1
|vpiIODecl:
\_io_decl: (data_valid)
|vpiName:data_valid
|vpiDirection:2
|vpiIODecl:
\_io_decl: (ready)
|vpiName:ready
|vpiDirection:2
|vpiTaskFunc:
\_function: (address_range_check), line:217
|vpiName:address_range_check
|vpiFullName:work@ls_sub_unit_interface.address_range_check
|vpiIODecl:
\_io_decl: (addr)
|vpiName:addr
|vpiDirection:1
|vpiExpr:
\_logic_var: , line:217, parent:addr
|vpiFullName:addr
|vpiRange:
\_range: , line:217
|vpiLeftRange:
\_constant: , line:217
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:217
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiStmt:
\_return_stmt: , line:218, parent:address_range_check
|vpiCondition:
\_operation: , line:218
|vpiOpType:14
|vpiOperand:
\_part_select: , line:218, parent:addr
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (addr)
|vpiLeftRange:
\_constant: , line:218
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_operation: , line:218
|vpiOpType:11
|vpiOperand:
\_constant: , line:218
|vpiConstType:7
|vpiDecompile:32
|vpiSize:32
|INT:32
|vpiOperand:
\_ref_obj: (BIT_CHECK), line:218
|vpiName:BIT_CHECK
|vpiOperand:
\_part_select: , line:218, parent:BASE_ADDR
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (BASE_ADDR)
|vpiLeftRange:
\_constant: , line:218
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_operation: , line:218
|vpiOpType:11
|vpiOperand:
\_constant: , line:218
|vpiConstType:7
|vpiDecompile:32
|vpiSize:32
|INT:32
|vpiOperand:
\_ref_obj: (BIT_CHECK), line:218
|vpiName:BIT_CHECK
|vpiFullName:work@ls_sub_unit_interface.address_range_check.BIT_CHECK
|vpiNet:
\_logic_net: (data_valid), line:213
|vpiName:data_valid
|vpiFullName:work@ls_sub_unit_interface.data_valid
|vpiNetType:36
|vpiNet:
\_logic_net: (ready), line:214
|vpiName:ready
|vpiFullName:work@ls_sub_unit_interface.ready
|vpiNetType:36
|vpiNet:
\_logic_net: (new_request), line:215
|vpiName:new_request
|vpiFullName:work@ls_sub_unit_interface.new_request
|vpiNetType:36
|vpiTypedef:
\_struct_typespec: (alu_inputs_t), line:301
|vpiTypedef:
\_enum_typespec: (alu_logic_op_t), line:84
|vpiTypedef:
\_enum_typespec: (alu_op_t), line:91
|vpiTypedef:
\_enum_typespec: (alu_rs1_op_t), line:97
|vpiTypedef:
\_enum_typespec: (alu_rs2_op_t), line:104
|vpiTypedef:
\_struct_typespec: (amo_alu_inputs_t), line:356
|vpiTypedef:
\_struct_typespec: (amo_details_t), line:362
|vpiTypedef:
\_enum_typespec: (amo_t), line:354
|vpiTypedef:
\_struct_typespec: (branch_inputs_t), line:313
|vpiTypedef:
\_logic_typespec: (branch_predictor_metadata_t), line:32
|vpiTypedef:
\_struct_typespec: (branch_results_t), line:330
|vpiTypedef:
\_enum_typespec: (bus_type_t), line:86
|vpiTypedef:
\_struct_typespec: (csr_inputs_t), line:396
|vpiTypedef:
\_enum_typespec: (csr_op_t), line:218
|vpiTypedef:
\_enum_typespec: (csr_t), line:201
|vpiTypedef:
\_struct_typespec: (data_access_shared_inputs_t), line:427
|vpiTypedef:
\_struct_typespec: (div_inputs_t), line:389
|vpiTypedef:
\_enum_typespec: (div_type), line:66
|vpiTypedef:
\_enum_typespec: (exception_code_t), line:245
|vpiTypedef:
\_struct_typespec: (exception_packet_t), line:263
|vpiTypedef:
\_struct_typespec: (fetch_buffer_packet_t), line:276
|vpiTypedef:
\_enum_typespec: (fifo_type_t), line:440
|vpiTypedef:
\_enum_typespec: (fn3_arith_t), line:76
|vpiTypedef:
\_enum_typespec: (fn3_branch_t), line:126
|vpiTypedef:
\_enum_typespec: (fn3_csr_t), line:212
|vpiTypedef:
\_enum_typespec: (fn3_ls_t), line:115
|vpiTypedef:
\_enum_typespec: (fn3_mul_div_t), line:138
|vpiTypedef:
\_struct_typespec: (gc_inputs_t), line:404
|vpiTypedef:
\_struct_typespec: (inflight_instruction_packet), line:271
|vpiTypedef:
\_logic_typespec: (instruction_id_t), line:30
|vpiTypedef:
\_enum_typespec: (interrupt_code_t), line:261
|vpiTypedef:
\_struct_typespec: (l2_data_attributes_t), line:68
|vpiTypedef:
\_struct_typespec: (l2_mem_request_t), line:58
|vpiTypedef:
\_struct_typespec: (l2_mem_return_data_t), line:75
|vpiTypedef:
\_struct_typespec: (l2_request_t), line:49
|vpiTypedef:
\_struct_typespec: (l2_return_data_t), line:81
|vpiTypedef:
\_struct_typespec: (load_store_inputs_t), line:369
|vpiTypedef:
\_struct_typespec: (mul_inputs_t), line:383
|vpiTypedef:
\_enum_typespec: (opcodes_t), line:48
|vpiTypedef:
\_enum_typespec: (opcodes_trimmed_t), line:65
|vpiTypedef:
\_struct_typespec: (simulation_named_regfile), line:476
|vpiTypedef:
\_struct_typespec: (taiga_trace_events_t), line:442
|vpiTypedef:
\_struct_typespec: (to_l1_arbiter_packet), line:418
|vpiTypedef:
\_struct_typespec: (trace_outputs_t), line:469
|vpiTypedef:
\_logic_typespec: (unit_id_t), line:31
|vpiTypedef:
\_struct_typespec: (unit_writeback_t), line:295
|vpiTypedef:
\_enum_typespec: (vm_t), line:223
|uhdmallInterfaces:
\_interface: work@mmu_interface, file:third_party/cores/taiga/core/interfaces.sv, line:170, parent:work@div_unit_core_wrapper
|vpiDefName:work@mmu_interface
|vpiFullName:work@mmu_interface
|vpiModport:
\_modport: (csr)
|vpiName:csr
|vpiIODecl:
\_io_decl: (ppn)
|vpiName:ppn
|vpiDirection:2
|vpiIODecl:
\_io_decl: (mxr)
|vpiName:mxr
|vpiDirection:2
|vpiIODecl:
\_io_decl: (pum)
|vpiName:pum
|vpiDirection:2
|vpiIODecl:
\_io_decl: (privilege)
|vpiName:privilege
|vpiDirection:2
|vpiModport:
\_modport: (mmu)
|vpiName:mmu
|vpiIODecl:
\_io_decl: (virtual_address)
|vpiName:virtual_address
|vpiDirection:1
|vpiIODecl:
\_io_decl: (new_request)
|vpiName:new_request
|vpiDirection:1
|vpiIODecl:
\_io_decl: (execute)
|vpiName:execute
|vpiDirection:1
|vpiIODecl:
\_io_decl: (rnw)
|vpiName:rnw
|vpiDirection:1
|vpiIODecl:
\_io_decl: (ppn)
|vpiName:ppn
|vpiDirection:1
|vpiIODecl:
\_io_decl: (mxr)
|vpiName:mxr
|vpiDirection:1
|vpiIODecl:
\_io_decl: (pum)
|vpiName:pum
|vpiDirection:1
|vpiIODecl:
\_io_decl: (privilege)
|vpiName:privilege
|vpiDirection:1
|vpiIODecl:
\_io_decl: (write_entry)
|vpiName:write_entry
|vpiDirection:2
|vpiIODecl:
\_io_decl: (new_phys_addr)
|vpiName:new_phys_addr
|vpiDirection:2
|vpiModport:
\_modport: (tlb)
|vpiName:tlb
|vpiIODecl:
\_io_decl: (write_entry)
|vpiName:write_entry
|vpiDirection:1
|vpiIODecl:
\_io_decl: (new_phys_addr)
|vpiName:new_phys_addr
|vpiDirection:1
|vpiIODecl:
\_io_decl: (new_request)
|vpiName:new_request
|vpiDirection:2
|vpiIODecl:
\_io_decl: (virtual_address)
|vpiName:virtual_address
|vpiDirection:2
|vpiIODecl:
\_io_decl: (execute)
|vpiName:execute
|vpiDirection:2
|vpiIODecl:
\_io_decl: (rnw)
|vpiName:rnw
|vpiDirection:2
|vpiNet:
\_logic_net: (new_request), line:172
|vpiName:new_request
|vpiFullName:work@mmu_interface.new_request
|vpiNetType:36
|vpiNet:
\_logic_net: (execute), line:173
|vpiName:execute
|vpiFullName:work@mmu_interface.execute
|vpiNetType:36
|vpiNet:
\_logic_net: (rnw), line:174
|vpiName:rnw
|vpiFullName:work@mmu_interface.rnw
|vpiNetType:36
|vpiNet:
\_logic_net: (virtual_address), line:175
|vpiName:virtual_address
|vpiFullName:work@mmu_interface.virtual_address
|vpiNetType:36
|vpiNet:
\_logic_net: (write_entry), line:178
|vpiName:write_entry
|vpiFullName:work@mmu_interface.write_entry
|vpiNetType:36
|vpiNet:
\_logic_net: (new_phys_addr), line:179
|vpiName:new_phys_addr
|vpiFullName:work@mmu_interface.new_phys_addr
|vpiNetType:36
|vpiNet:
\_logic_net: (ppn), line:182
|vpiName:ppn
|vpiFullName:work@mmu_interface.ppn
|vpiNetType:36
|vpiNet:
\_logic_net: (mxr), line:183
|vpiName:mxr
|vpiFullName:work@mmu_interface.mxr
|vpiNetType:36
|vpiNet:
\_logic_net: (pum), line:184
|vpiName:pum
|vpiFullName:work@mmu_interface.pum
|vpiNetType:36
|vpiNet:
\_logic_net: (privilege), line:185
|vpiName:privilege
|vpiFullName:work@mmu_interface.privilege
|vpiNetType:36
|vpiTypedef:
\_struct_typespec: (alu_inputs_t), line:301
|vpiTypedef:
\_enum_typespec: (alu_logic_op_t), line:84
|vpiTypedef:
\_enum_typespec: (alu_op_t), line:91
|vpiTypedef:
\_enum_typespec: (alu_rs1_op_t), line:97
|vpiTypedef:
\_enum_typespec: (alu_rs2_op_t), line:104
|vpiTypedef:
\_struct_typespec: (amo_alu_inputs_t), line:356
|vpiTypedef:
\_struct_typespec: (amo_details_t), line:362
|vpiTypedef:
\_enum_typespec: (amo_t), line:354
|vpiTypedef:
\_struct_typespec: (branch_inputs_t), line:313
|vpiTypedef:
\_logic_typespec: (branch_predictor_metadata_t), line:32
|vpiTypedef:
\_struct_typespec: (branch_results_t), line:330
|vpiTypedef:
\_enum_typespec: (bus_type_t), line:86
|vpiTypedef:
\_struct_typespec: (csr_inputs_t), line:396
|vpiTypedef:
\_enum_typespec: (csr_op_t), line:218
|vpiTypedef:
\_enum_typespec: (csr_t), line:201
|vpiTypedef:
\_struct_typespec: (data_access_shared_inputs_t), line:427
|vpiTypedef:
\_struct_typespec: (div_inputs_t), line:389
|vpiTypedef:
\_enum_typespec: (div_type), line:66
|vpiTypedef:
\_enum_typespec: (exception_code_t), line:245
|vpiTypedef:
\_struct_typespec: (exception_packet_t), line:263
|vpiTypedef:
\_struct_typespec: (fetch_buffer_packet_t), line:276
|vpiTypedef:
\_enum_typespec: (fifo_type_t), line:440
|vpiTypedef:
\_enum_typespec: (fn3_arith_t), line:76
|vpiTypedef:
\_enum_typespec: (fn3_branch_t), line:126
|vpiTypedef:
\_enum_typespec: (fn3_csr_t), line:212
|vpiTypedef:
\_enum_typespec: (fn3_ls_t), line:115
|vpiTypedef:
\_enum_typespec: (fn3_mul_div_t), line:138
|vpiTypedef:
\_struct_typespec: (gc_inputs_t), line:404
|vpiTypedef:
\_struct_typespec: (inflight_instruction_packet), line:271
|vpiTypedef:
\_logic_typespec: (instruction_id_t), line:30
|vpiTypedef:
\_enum_typespec: (interrupt_code_t), line:261
|vpiTypedef:
\_struct_typespec: (l2_data_attributes_t), line:68
|vpiTypedef:
\_struct_typespec: (l2_mem_request_t), line:58
|vpiTypedef:
\_struct_typespec: (l2_mem_return_data_t), line:75
|vpiTypedef:
\_struct_typespec: (l2_request_t), line:49
|vpiTypedef:
\_struct_typespec: (l2_return_data_t), line:81
|vpiTypedef:
\_struct_typespec: (load_store_inputs_t), line:369
|vpiTypedef:
\_struct_typespec: (mul_inputs_t), line:383
|vpiTypedef:
\_enum_typespec: (opcodes_t), line:48
|vpiTypedef:
\_enum_typespec: (opcodes_trimmed_t), line:65
|vpiTypedef:
\_struct_typespec: (simulation_named_regfile), line:476
|vpiTypedef:
\_struct_typespec: (taiga_trace_events_t), line:442
|vpiTypedef:
\_struct_typespec: (to_l1_arbiter_packet), line:418
|vpiTypedef:
\_struct_typespec: (trace_outputs_t), line:469
|vpiTypedef:
\_logic_typespec: (unit_id_t), line:31
|vpiTypedef:
\_struct_typespec: (unit_writeback_t), line:295
|vpiTypedef:
\_enum_typespec: (vm_t), line:223
|uhdmallInterfaces:
\_interface: work@post_issue_forwarding_interface, file:third_party/cores/taiga/core/interfaces.sv, line:257, parent:work@div_unit_core_wrapper
|vpiDefName:work@post_issue_forwarding_interface
|vpiFullName:work@post_issue_forwarding_interface
|vpiModport:
\_modport: (unit)
|vpiName:unit
|vpiIODecl:
\_io_decl: (data)
|vpiName:data
|vpiDirection:1
|vpiIODecl:
\_io_decl: (data_valid)
|vpiName:data_valid
|vpiDirection:1
|vpiIODecl:
\_io_decl: (id)
|vpiName:id
|vpiDirection:2
|vpiModport:
\_modport: (wb)
|vpiName:wb
|vpiIODecl:
\_io_decl: (data)
|vpiName:data
|vpiDirection:2
|vpiIODecl:
\_io_decl: (data_valid)
|vpiName:data_valid
|vpiDirection:2
|vpiIODecl:
\_io_decl: (id)
|vpiName:id
|vpiDirection:1
|vpiNet:
\_logic_net: (id), line:258
|vpiName:id
|vpiFullName:work@post_issue_forwarding_interface.id
|vpiNet:
\_logic_net: (data), line:260
|vpiName:data
|vpiFullName:work@post_issue_forwarding_interface.data
|vpiNetType:36
|vpiNet:
\_logic_net: (data_valid), line:261
|vpiName:data_valid
|vpiFullName:work@post_issue_forwarding_interface.data_valid
|vpiNetType:36
|vpiTypedef:
\_struct_typespec: (alu_inputs_t), line:301
|vpiTypedef:
\_enum_typespec: (alu_logic_op_t), line:84
|vpiTypedef:
\_enum_typespec: (alu_op_t), line:91
|vpiTypedef:
\_enum_typespec: (alu_rs1_op_t), line:97
|vpiTypedef:
\_enum_typespec: (alu_rs2_op_t), line:104
|vpiTypedef:
\_struct_typespec: (amo_alu_inputs_t), line:356
|vpiTypedef:
\_struct_typespec: (amo_details_t), line:362
|vpiTypedef:
\_enum_typespec: (amo_t), line:354
|vpiTypedef:
\_struct_typespec: (branch_inputs_t), line:313
|vpiTypedef:
\_logic_typespec: (branch_predictor_metadata_t), line:32
|vpiTypedef:
\_struct_typespec: (branch_results_t), line:330
|vpiTypedef:
\_enum_typespec: (bus_type_t), line:86
|vpiTypedef:
\_struct_typespec: (csr_inputs_t), line:396
|vpiTypedef:
\_enum_typespec: (csr_op_t), line:218
|vpiTypedef:
\_enum_typespec: (csr_t), line:201
|vpiTypedef:
\_struct_typespec: (data_access_shared_inputs_t), line:427
|vpiTypedef:
\_struct_typespec: (div_inputs_t), line:389
|vpiTypedef:
\_enum_typespec: (div_type), line:66
|vpiTypedef:
\_enum_typespec: (exception_code_t), line:245
|vpiTypedef:
\_struct_typespec: (exception_packet_t), line:263
|vpiTypedef:
\_struct_typespec: (fetch_buffer_packet_t), line:276
|vpiTypedef:
\_enum_typespec: (fifo_type_t), line:440
|vpiTypedef:
\_enum_typespec: (fn3_arith_t), line:76
|vpiTypedef:
\_enum_typespec: (fn3_branch_t), line:126
|vpiTypedef:
\_enum_typespec: (fn3_csr_t), line:212
|vpiTypedef:
\_enum_typespec: (fn3_ls_t), line:115
|vpiTypedef:
\_enum_typespec: (fn3_mul_div_t), line:138
|vpiTypedef:
\_struct_typespec: (gc_inputs_t), line:404
|vpiTypedef:
\_struct_typespec: (inflight_instruction_packet), line:271
|vpiTypedef:
\_logic_typespec: (instruction_id_t), line:30
|vpiTypedef:
\_enum_typespec: (interrupt_code_t), line:261
|vpiTypedef:
\_struct_typespec: (l2_data_attributes_t), line:68
|vpiTypedef:
\_struct_typespec: (l2_mem_request_t), line:58
|vpiTypedef:
\_struct_typespec: (l2_mem_return_data_t), line:75
|vpiTypedef:
\_struct_typespec: (l2_request_t), line:49
|vpiTypedef:
\_struct_typespec: (l2_return_data_t), line:81
|vpiTypedef:
\_struct_typespec: (load_store_inputs_t), line:369
|vpiTypedef:
\_struct_typespec: (mul_inputs_t), line:383
|vpiTypedef:
\_enum_typespec: (opcodes_t), line:48
|vpiTypedef:
\_enum_typespec: (opcodes_trimmed_t), line:65
|vpiTypedef:
\_struct_typespec: (simulation_named_regfile), line:476
|vpiTypedef:
\_struct_typespec: (taiga_trace_events_t), line:442
|vpiTypedef:
\_struct_typespec: (to_l1_arbiter_packet), line:418
|vpiTypedef:
\_struct_typespec: (trace_outputs_t), line:469
|vpiTypedef:
\_logic_typespec: (unit_id_t), line:31
|vpiTypedef:
\_struct_typespec: (unit_writeback_t), line:295
|vpiTypedef:
\_enum_typespec: (vm_t), line:223
|uhdmallInterfaces:
\_interface: work@ras_interface, file:third_party/cores/taiga/core/interfaces.sv, line:64, parent:work@div_unit_core_wrapper
|vpiDefName:work@ras_interface
|vpiFullName:work@ras_interface
|vpiModport:
\_modport: (branch_unit)
|vpiName:branch_unit
|vpiIODecl:
\_io_decl: (push)
|vpiName:push
|vpiDirection:2
|vpiIODecl:
\_io_decl: (pop)
|vpiName:pop
|vpiDirection:2
|vpiIODecl:
\_io_decl: (new_addr)
|vpiName:new_addr
|vpiDirection:2
|vpiModport:
\_modport: (fetch)
|vpiName:fetch
|vpiIODecl:
\_io_decl: (addr)
|vpiName:addr
|vpiDirection:1
|vpiIODecl:
\_io_decl: (valid)
|vpiName:valid
|vpiDirection:1
|vpiModport:
\_modport: (self)
|vpiName:self
|vpiIODecl:
\_io_decl: (push)
|vpiName:push
|vpiDirection:1
|vpiIODecl:
\_io_decl: (pop)
|vpiName:pop
|vpiDirection:1
|vpiIODecl:
\_io_decl: (new_addr)
|vpiName:new_addr
|vpiDirection:1
|vpiIODecl:
\_io_decl: (addr)
|vpiName:addr
|vpiDirection:2
|vpiIODecl:
\_io_decl: (valid)
|vpiName:valid
|vpiDirection:2
|vpiNet:
\_logic_net: (push), line:65
|vpiName:push
|vpiFullName:work@ras_interface.push
|vpiNetType:36
|vpiNet:
\_logic_net: (pop), line:66
|vpiName:pop
|vpiFullName:work@ras_interface.pop
|vpiNetType:36
|vpiNet:
\_logic_net: (new_addr), line:67
|vpiName:new_addr
|vpiFullName:work@ras_interface.new_addr
|vpiNetType:36
|vpiNet:
\_logic_net: (addr), line:68
|vpiName:addr
|vpiFullName:work@ras_interface.addr
|vpiNetType:36
|vpiNet:
\_logic_net: (valid), line:69
|vpiName:valid
|vpiFullName:work@ras_interface.valid
|vpiNetType:36
|vpiTypedef:
\_struct_typespec: (alu_inputs_t), line:301
|vpiTypedef:
\_enum_typespec: (alu_logic_op_t), line:84
|vpiTypedef:
\_enum_typespec: (alu_op_t), line:91
|vpiTypedef:
\_enum_typespec: (alu_rs1_op_t), line:97
|vpiTypedef:
\_enum_typespec: (alu_rs2_op_t), line:104
|vpiTypedef:
\_struct_typespec: (amo_alu_inputs_t), line:356
|vpiTypedef:
\_struct_typespec: (amo_details_t), line:362
|vpiTypedef:
\_enum_typespec: (amo_t), line:354
|vpiTypedef:
\_struct_typespec: (branch_inputs_t), line:313
|vpiTypedef:
\_logic_typespec: (branch_predictor_metadata_t), line:32
|vpiTypedef:
\_struct_typespec: (branch_results_t), line:330
|vpiTypedef:
\_enum_typespec: (bus_type_t), line:86
|vpiTypedef:
\_struct_typespec: (csr_inputs_t), line:396
|vpiTypedef:
\_enum_typespec: (csr_op_t), line:218
|vpiTypedef:
\_enum_typespec: (csr_t), line:201
|vpiTypedef:
\_struct_typespec: (data_access_shared_inputs_t), line:427
|vpiTypedef:
\_struct_typespec: (div_inputs_t), line:389
|vpiTypedef:
\_enum_typespec: (div_type), line:66
|vpiTypedef:
\_enum_typespec: (exception_code_t), line:245
|vpiTypedef:
\_struct_typespec: (exception_packet_t), line:263
|vpiTypedef:
\_struct_typespec: (fetch_buffer_packet_t), line:276
|vpiTypedef:
\_enum_typespec: (fifo_type_t), line:440
|vpiTypedef:
\_enum_typespec: (fn3_arith_t), line:76
|vpiTypedef:
\_enum_typespec: (fn3_branch_t), line:126
|vpiTypedef:
\_enum_typespec: (fn3_csr_t), line:212
|vpiTypedef:
\_enum_typespec: (fn3_ls_t), line:115
|vpiTypedef:
\_enum_typespec: (fn3_mul_div_t), line:138
|vpiTypedef:
\_struct_typespec: (gc_inputs_t), line:404
|vpiTypedef:
\_struct_typespec: (inflight_instruction_packet), line:271
|vpiTypedef:
\_logic_typespec: (instruction_id_t), line:30
|vpiTypedef:
\_enum_typespec: (interrupt_code_t), line:261
|vpiTypedef:
\_struct_typespec: (l2_data_attributes_t), line:68
|vpiTypedef:
\_struct_typespec: (l2_mem_request_t), line:58
|vpiTypedef:
\_struct_typespec: (l2_mem_return_data_t), line:75
|vpiTypedef:
\_struct_typespec: (l2_request_t), line:49
|vpiTypedef:
\_struct_typespec: (l2_return_data_t), line:81
|vpiTypedef:
\_struct_typespec: (load_store_inputs_t), line:369
|vpiTypedef:
\_struct_typespec: (mul_inputs_t), line:383
|vpiTypedef:
\_enum_typespec: (opcodes_t), line:48
|vpiTypedef:
\_enum_typespec: (opcodes_trimmed_t), line:65
|vpiTypedef:
\_struct_typespec: (simulation_named_regfile), line:476
|vpiTypedef:
\_struct_typespec: (taiga_trace_events_t), line:442
|vpiTypedef:
\_struct_typespec: (to_l1_arbiter_packet), line:418
|vpiTypedef:
\_struct_typespec: (trace_outputs_t), line:469
|vpiTypedef:
\_logic_typespec: (unit_id_t), line:31
|vpiTypedef:
\_struct_typespec: (unit_writeback_t), line:295
|vpiTypedef:
\_enum_typespec: (vm_t), line:223
|uhdmallInterfaces:
\_interface: work@register_file_decode_interface, file:third_party/cores/taiga/core/interfaces.sv, line:103, parent:work@div_unit_core_wrapper
|vpiDefName:work@register_file_decode_interface
|vpiFullName:work@register_file_decode_interface
|vpiModport:
\_modport: (decode)
|vpiName:decode
|vpiIODecl:
\_io_decl: (future_rd_addr)
|vpiName:future_rd_addr
|vpiDirection:2
|vpiIODecl:
\_io_decl: (rs1_addr)
|vpiName:rs1_addr
|vpiDirection:2
|vpiIODecl:
\_io_decl: (rs2_addr)
|vpiName:rs2_addr
|vpiDirection:2
|vpiIODecl:
\_io_decl: (instruction_issued)
|vpiName:instruction_issued
|vpiDirection:2
|vpiIODecl:
\_io_decl: (id)
|vpiName:id
|vpiDirection:2
|vpiIODecl:
\_io_decl: (uses_rs1)
|vpiName:uses_rs1
|vpiDirection:2
|vpiIODecl:
\_io_decl: (uses_rs2)
|vpiName:uses_rs2
|vpiDirection:2
|vpiIODecl:
\_io_decl: (rs1_conflict)
|vpiName:rs1_conflict
|vpiDirection:1
|vpiIODecl:
\_io_decl: (rs2_conflict)
|vpiName:rs2_conflict
|vpiDirection:1
|vpiIODecl:
\_io_decl: (rs1_data)
|vpiName:rs1_data
|vpiDirection:1
|vpiIODecl:
\_io_decl: (rs2_data)
|vpiName:rs2_data
|vpiDirection:1
|vpiIODecl:
\_io_decl: (rs2_id)
|vpiName:rs2_id
|vpiDirection:1
|vpiModport:
\_modport: (unit)
|vpiName:unit
|vpiIODecl:
\_io_decl: (future_rd_addr)
|vpiName:future_rd_addr
|vpiDirection:1
|vpiIODecl:
\_io_decl: (rs1_addr)
|vpiName:rs1_addr
|vpiDirection:1
|vpiIODecl:
\_io_decl: (rs2_addr)
|vpiName:rs2_addr
|vpiDirection:1
|vpiIODecl:
\_io_decl: (instruction_issued)
|vpiName:instruction_issued
|vpiDirection:1
|vpiIODecl:
\_io_decl: (id)
|vpiName:id
|vpiDirection:1
|vpiIODecl:
\_io_decl: (uses_rs1)
|vpiName:uses_rs1
|vpiDirection:1
|vpiIODecl:
\_io_decl: (uses_rs2)
|vpiName:uses_rs2
|vpiDirection:1
|vpiIODecl:
\_io_decl: (rs1_conflict)
|vpiName:rs1_conflict
|vpiDirection:2
|vpiIODecl:
\_io_decl: (rs2_conflict)
|vpiName:rs2_conflict
|vpiDirection:2
|vpiIODecl:
\_io_decl: (rs1_data)
|vpiName:rs1_data
|vpiDirection:2
|vpiIODecl:
\_io_decl: (rs2_data)
|vpiName:rs2_data
|vpiDirection:2
|vpiIODecl:
\_io_decl: (rs2_id)
|vpiName:rs2_id
|vpiDirection:2
|vpiNet:
\_logic_net: (future_rd_addr), line:104
|vpiName:future_rd_addr
|vpiFullName:work@register_file_decode_interface.future_rd_addr
|vpiNetType:36
|vpiNet:
\_logic_net: (rs1_addr), line:105
|vpiName:rs1_addr
|vpiFullName:work@register_file_decode_interface.rs1_addr
|vpiNetType:36
|vpiNet:
\_logic_net: (rs1_data), line:106
|vpiName:rs1_data
|vpiFullName:work@register_file_decode_interface.rs1_data
|vpiNetType:36
|vpiNet:
\_logic_net: (rs2_addr), line:107
|vpiName:rs2_addr
|vpiFullName:work@register_file_decode_interface.rs2_addr
|vpiNetType:36
|vpiNet:
\_logic_net: (rs2_data), line:108
|vpiName:rs2_data
|vpiFullName:work@register_file_decode_interface.rs2_data
|vpiNetType:36
|vpiNet:
\_logic_net: (id), line:109
|vpiName:id
|vpiFullName:work@register_file_decode_interface.id
|vpiNet:
\_logic_net: (uses_rs1), line:111
|vpiName:uses_rs1
|vpiFullName:work@register_file_decode_interface.uses_rs1
|vpiNetType:36
|vpiNet:
\_logic_net: (uses_rs2), line:112
|vpiName:uses_rs2
|vpiFullName:work@register_file_decode_interface.uses_rs2
|vpiNetType:36
|vpiNet:
\_logic_net: (rs1_conflict), line:113
|vpiName:rs1_conflict
|vpiFullName:work@register_file_decode_interface.rs1_conflict
|vpiNetType:36
|vpiNet:
\_logic_net: (rs2_conflict), line:114
|vpiName:rs2_conflict
|vpiFullName:work@register_file_decode_interface.rs2_conflict
|vpiNetType:36
|vpiNet:
\_logic_net: (rs2_id), line:115
|vpiName:rs2_id
|vpiFullName:work@register_file_decode_interface.rs2_id
|vpiNet:
\_logic_net: (instruction_issued), line:116
|vpiName:instruction_issued
|vpiFullName:work@register_file_decode_interface.instruction_issued
|vpiNetType:36
|vpiTypedef:
\_struct_typespec: (alu_inputs_t), line:301
|vpiTypedef:
\_enum_typespec: (alu_logic_op_t), line:84
|vpiTypedef:
\_enum_typespec: (alu_op_t), line:91
|vpiTypedef:
\_enum_typespec: (alu_rs1_op_t), line:97
|vpiTypedef:
\_enum_typespec: (alu_rs2_op_t), line:104
|vpiTypedef:
\_struct_typespec: (amo_alu_inputs_t), line:356
|vpiTypedef:
\_struct_typespec: (amo_details_t), line:362
|vpiTypedef:
\_enum_typespec: (amo_t), line:354
|vpiTypedef:
\_struct_typespec: (branch_inputs_t), line:313
|vpiTypedef:
\_logic_typespec: (branch_predictor_metadata_t), line:32
|vpiTypedef:
\_struct_typespec: (branch_results_t), line:330
|vpiTypedef:
\_enum_typespec: (bus_type_t), line:86
|vpiTypedef:
\_struct_typespec: (csr_inputs_t), line:396
|vpiTypedef:
\_enum_typespec: (csr_op_t), line:218
|vpiTypedef:
\_enum_typespec: (csr_t), line:201
|vpiTypedef:
\_struct_typespec: (data_access_shared_inputs_t), line:427
|vpiTypedef:
\_struct_typespec: (div_inputs_t), line:389
|vpiTypedef:
\_enum_typespec: (div_type), line:66
|vpiTypedef:
\_enum_typespec: (exception_code_t), line:245
|vpiTypedef:
\_struct_typespec: (exception_packet_t), line:263
|vpiTypedef:
\_struct_typespec: (fetch_buffer_packet_t), line:276
|vpiTypedef:
\_enum_typespec: (fifo_type_t), line:440
|vpiTypedef:
\_enum_typespec: (fn3_arith_t), line:76
|vpiTypedef:
\_enum_typespec: (fn3_branch_t), line:126
|vpiTypedef:
\_enum_typespec: (fn3_csr_t), line:212
|vpiTypedef:
\_enum_typespec: (fn3_ls_t), line:115
|vpiTypedef:
\_enum_typespec: (fn3_mul_div_t), line:138
|vpiTypedef:
\_struct_typespec: (gc_inputs_t), line:404
|vpiTypedef:
\_struct_typespec: (inflight_instruction_packet), line:271
|vpiTypedef:
\_logic_typespec: (instruction_id_t), line:30
|vpiTypedef:
\_enum_typespec: (interrupt_code_t), line:261
|vpiTypedef:
\_struct_typespec: (l2_data_attributes_t), line:68
|vpiTypedef:
\_struct_typespec: (l2_mem_request_t), line:58
|vpiTypedef:
\_struct_typespec: (l2_mem_return_data_t), line:75
|vpiTypedef:
\_struct_typespec: (l2_request_t), line:49
|vpiTypedef:
\_struct_typespec: (l2_return_data_t), line:81
|vpiTypedef:
\_struct_typespec: (load_store_inputs_t), line:369
|vpiTypedef:
\_struct_typespec: (mul_inputs_t), line:383
|vpiTypedef:
\_enum_typespec: (opcodes_t), line:48
|vpiTypedef:
\_enum_typespec: (opcodes_trimmed_t), line:65
|vpiTypedef:
\_struct_typespec: (simulation_named_regfile), line:476
|vpiTypedef:
\_struct_typespec: (taiga_trace_events_t), line:442
|vpiTypedef:
\_struct_typespec: (to_l1_arbiter_packet), line:418
|vpiTypedef:
\_struct_typespec: (trace_outputs_t), line:469
|vpiTypedef:
\_logic_typespec: (unit_id_t), line:31
|vpiTypedef:
\_struct_typespec: (unit_writeback_t), line:295
|vpiTypedef:
\_enum_typespec: (vm_t), line:223
|uhdmallInterfaces:
\_interface: work@register_file_writeback_interface, file:third_party/cores/taiga/core/interfaces.sv, line:123, parent:work@div_unit_core_wrapper
|vpiDefName:work@register_file_writeback_interface
|vpiFullName:work@register_file_writeback_interface
|vpiModport:
\_modport: (unit)
|vpiName:unit
|vpiIODecl:
\_io_decl: (rd_addr)
|vpiName:rd_addr
|vpiDirection:1
|vpiIODecl:
\_io_decl: (retiring)
|vpiName:retiring
|vpiDirection:1
|vpiIODecl:
\_io_decl: (rd_nzero)
|vpiName:rd_nzero
|vpiDirection:1
|vpiIODecl:
\_io_decl: (rd_data)
|vpiName:rd_data
|vpiDirection:1
|vpiIODecl:
\_io_decl: (id)
|vpiName:id
|vpiDirection:1
|vpiIODecl:
\_io_decl: (rs1_data)
|vpiName:rs1_data
|vpiDirection:1
|vpiIODecl:
\_io_decl: (rs2_data)
|vpiName:rs2_data
|vpiDirection:1
|vpiIODecl:
\_io_decl: (rs1_valid)
|vpiName:rs1_valid
|vpiDirection:1
|vpiIODecl:
\_io_decl: (rs2_valid)
|vpiName:rs2_valid
|vpiDirection:1
|vpiIODecl:
\_io_decl: (rs1_id)
|vpiName:rs1_id
|vpiDirection:2
|vpiIODecl:
\_io_decl: (rs2_id)
|vpiName:rs2_id
|vpiDirection:2
|vpiModport:
\_modport: (writeback)
|vpiName:writeback
|vpiIODecl:
\_io_decl: (rd_addr)
|vpiName:rd_addr
|vpiDirection:2
|vpiIODecl:
\_io_decl: (retiring)
|vpiName:retiring
|vpiDirection:2
|vpiIODecl:
\_io_decl: (rd_nzero)
|vpiName:rd_nzero
|vpiDirection:2
|vpiIODecl:
\_io_decl: (rd_data)
|vpiName:rd_data
|vpiDirection:2
|vpiIODecl:
\_io_decl: (id)
|vpiName:id
|vpiDirection:2
|vpiIODecl:
\_io_decl: (rs1_data)
|vpiName:rs1_data
|vpiDirection:2
|vpiIODecl:
\_io_decl: (rs2_data)
|vpiName:rs2_data
|vpiDirection:2
|vpiIODecl:
\_io_decl: (rs1_valid)
|vpiName:rs1_valid
|vpiDirection:2
|vpiIODecl:
\_io_decl: (rs2_valid)
|vpiName:rs2_valid
|vpiDirection:2
|vpiIODecl:
\_io_decl: (rs1_id)
|vpiName:rs1_id
|vpiDirection:1
|vpiIODecl:
\_io_decl: (rs2_id)
|vpiName:rs2_id
|vpiDirection:1
|vpiNet:
\_logic_net: (rd_addr), line:124
|vpiName:rd_addr
|vpiFullName:work@register_file_writeback_interface.rd_addr
|vpiNetType:36
|vpiNet:
\_logic_net: (retiring), line:125
|vpiName:retiring
|vpiFullName:work@register_file_writeback_interface.retiring
|vpiNetType:36
|vpiNet:
\_logic_net: (rd_nzero), line:126
|vpiName:rd_nzero
|vpiFullName:work@register_file_writeback_interface.rd_nzero
|vpiNetType:36
|vpiNet:
\_logic_net: (rd_data), line:128
|vpiName:rd_data
|vpiFullName:work@register_file_writeback_interface.rd_data
|vpiNetType:36
|vpiNet:
\_logic_net: (id), line:129
|vpiName:id
|vpiFullName:work@register_file_writeback_interface.id
|vpiNet:
\_logic_net: (rs1_id), line:131
|vpiName:rs1_id
|vpiFullName:work@register_file_writeback_interface.rs1_id
|vpiNet:
\_logic_net: (rs2_id), line:132
|vpiName:rs2_id
|vpiFullName:work@register_file_writeback_interface.rs2_id
|vpiNet:
\_logic_net: (rs1_data), line:134
|vpiName:rs1_data
|vpiFullName:work@register_file_writeback_interface.rs1_data
|vpiNetType:36
|vpiNet:
\_logic_net: (rs2_data), line:135
|vpiName:rs2_data
|vpiFullName:work@register_file_writeback_interface.rs2_data
|vpiNetType:36
|vpiNet:
\_logic_net: (rs1_valid), line:136
|vpiName:rs1_valid
|vpiFullName:work@register_file_writeback_interface.rs1_valid
|vpiNetType:36
|vpiNet:
\_logic_net: (rs2_valid), line:137
|vpiName:rs2_valid
|vpiFullName:work@register_file_writeback_interface.rs2_valid
|vpiNetType:36
|vpiTypedef:
\_struct_typespec: (alu_inputs_t), line:301
|vpiTypedef:
\_enum_typespec: (alu_logic_op_t), line:84
|vpiTypedef:
\_enum_typespec: (alu_op_t), line:91
|vpiTypedef:
\_enum_typespec: (alu_rs1_op_t), line:97
|vpiTypedef:
\_enum_typespec: (alu_rs2_op_t), line:104
|vpiTypedef:
\_struct_typespec: (amo_alu_inputs_t), line:356
|vpiTypedef:
\_struct_typespec: (amo_details_t), line:362
|vpiTypedef:
\_enum_typespec: (amo_t), line:354
|vpiTypedef:
\_struct_typespec: (branch_inputs_t), line:313
|vpiTypedef:
\_logic_typespec: (branch_predictor_metadata_t), line:32
|vpiTypedef:
\_struct_typespec: (branch_results_t), line:330
|vpiTypedef:
\_enum_typespec: (bus_type_t), line:86
|vpiTypedef:
\_struct_typespec: (csr_inputs_t), line:396
|vpiTypedef:
\_enum_typespec: (csr_op_t), line:218
|vpiTypedef:
\_enum_typespec: (csr_t), line:201
|vpiTypedef:
\_struct_typespec: (data_access_shared_inputs_t), line:427
|vpiTypedef:
\_struct_typespec: (div_inputs_t), line:389
|vpiTypedef:
\_enum_typespec: (div_type), line:66
|vpiTypedef:
\_enum_typespec: (exception_code_t), line:245
|vpiTypedef:
\_struct_typespec: (exception_packet_t), line:263
|vpiTypedef:
\_struct_typespec: (fetch_buffer_packet_t), line:276
|vpiTypedef:
\_enum_typespec: (fifo_type_t), line:440
|vpiTypedef:
\_enum_typespec: (fn3_arith_t), line:76
|vpiTypedef:
\_enum_typespec: (fn3_branch_t), line:126
|vpiTypedef:
\_enum_typespec: (fn3_csr_t), line:212
|vpiTypedef:
\_enum_typespec: (fn3_ls_t), line:115
|vpiTypedef:
\_enum_typespec: (fn3_mul_div_t), line:138
|vpiTypedef:
\_struct_typespec: (gc_inputs_t), line:404
|vpiTypedef:
\_struct_typespec: (inflight_instruction_packet), line:271
|vpiTypedef:
\_logic_typespec: (instruction_id_t), line:30
|vpiTypedef:
\_enum_typespec: (interrupt_code_t), line:261
|vpiTypedef:
\_struct_typespec: (l2_data_attributes_t), line:68
|vpiTypedef:
\_struct_typespec: (l2_mem_request_t), line:58
|vpiTypedef:
\_struct_typespec: (l2_mem_return_data_t), line:75
|vpiTypedef:
\_struct_typespec: (l2_request_t), line:49
|vpiTypedef:
\_struct_typespec: (l2_return_data_t), line:81
|vpiTypedef:
\_struct_typespec: (load_store_inputs_t), line:369
|vpiTypedef:
\_struct_typespec: (mul_inputs_t), line:383
|vpiTypedef:
\_enum_typespec: (opcodes_t), line:48
|vpiTypedef:
\_enum_typespec: (opcodes_trimmed_t), line:65
|vpiTypedef:
\_struct_typespec: (simulation_named_regfile), line:476
|vpiTypedef:
\_struct_typespec: (taiga_trace_events_t), line:442
|vpiTypedef:
\_struct_typespec: (to_l1_arbiter_packet), line:418
|vpiTypedef:
\_struct_typespec: (trace_outputs_t), line:469
|vpiTypedef:
\_logic_typespec: (unit_id_t), line:31
|vpiTypedef:
\_struct_typespec: (unit_writeback_t), line:295
|vpiTypedef:
\_enum_typespec: (vm_t), line:223
|uhdmallInterfaces:
\_interface: work@tlb_interface, file:third_party/cores/taiga/core/interfaces.sv, line:193, parent:work@div_unit_core_wrapper
|vpiDefName:work@tlb_interface
|vpiFullName:work@tlb_interface
|vpiModport:
\_modport: (fence)
|vpiName:fence
|vpiIODecl:
\_io_decl: (flush)
|vpiName:flush
|vpiDirection:2
|vpiIODecl:
\_io_decl: (flush_complete)
|vpiName:flush_complete
|vpiDirection:1
|vpiModport:
\_modport: (mem)
|vpiName:mem
|vpiIODecl:
\_io_decl: (new_request)
|vpiName:new_request
|vpiDirection:2
|vpiIODecl:
\_io_decl: (virtual_address)
|vpiName:virtual_address
|vpiDirection:2
|vpiIODecl:
\_io_decl: (rnw)
|vpiName:rnw
|vpiDirection:2
|vpiIODecl:
\_io_decl: (execute)
|vpiName:execute
|vpiDirection:2
|vpiIODecl:
\_io_decl: (complete)
|vpiName:complete
|vpiDirection:1
|vpiIODecl:
\_io_decl: (physical_address)
|vpiName:physical_address
|vpiDirection:1
|vpiModport:
\_modport: (tlb)
|vpiName:tlb
|vpiIODecl:
\_io_decl: (virtual_address)
|vpiName:virtual_address
|vpiDirection:1
|vpiIODecl:
\_io_decl: (new_request)
|vpiName:new_request
|vpiDirection:1
|vpiIODecl:
\_io_decl: (flush)
|vpiName:flush
|vpiDirection:1
|vpiIODecl:
\_io_decl: (rnw)
|vpiName:rnw
|vpiDirection:1
|vpiIODecl:
\_io_decl: (execute)
|vpiName:execute
|vpiDirection:1
|vpiIODecl:
\_io_decl: (complete)
|vpiName:complete
|vpiDirection:2
|vpiIODecl:
\_io_decl: (physical_address)
|vpiName:physical_address
|vpiDirection:2
|vpiIODecl:
\_io_decl: (flush_complete)
|vpiName:flush_complete
|vpiDirection:2
|vpiNet:
\_logic_net: (virtual_address), line:194
|vpiName:virtual_address
|vpiFullName:work@tlb_interface.virtual_address
|vpiNetType:36
|vpiNet:
\_logic_net: (new_request), line:195
|vpiName:new_request
|vpiFullName:work@tlb_interface.new_request
|vpiNetType:36
|vpiNet:
\_logic_net: (rnw), line:196
|vpiName:rnw
|vpiFullName:work@tlb_interface.rnw
|vpiNetType:36
|vpiNet:
\_logic_net: (execute), line:197
|vpiName:execute
|vpiFullName:work@tlb_interface.execute
|vpiNetType:36
|vpiNet:
\_logic_net: (complete), line:199
|vpiName:complete
|vpiFullName:work@tlb_interface.complete
|vpiNetType:36
|vpiNet:
\_logic_net: (physical_address), line:200
|vpiName:physical_address
|vpiFullName:work@tlb_interface.physical_address
|vpiNetType:36
|vpiNet:
\_logic_net: (flush), line:202
|vpiName:flush
|vpiFullName:work@tlb_interface.flush
|vpiNetType:36
|vpiNet:
\_logic_net: (flush_complete), line:203
|vpiName:flush_complete
|vpiFullName:work@tlb_interface.flush_complete
|vpiNetType:36
|vpiTypedef:
\_struct_typespec: (alu_inputs_t), line:301
|vpiTypedef:
\_enum_typespec: (alu_logic_op_t), line:84
|vpiTypedef:
\_enum_typespec: (alu_op_t), line:91
|vpiTypedef:
\_enum_typespec: (alu_rs1_op_t), line:97
|vpiTypedef:
\_enum_typespec: (alu_rs2_op_t), line:104
|vpiTypedef:
\_struct_typespec: (amo_alu_inputs_t), line:356
|vpiTypedef:
\_struct_typespec: (amo_details_t), line:362
|vpiTypedef:
\_enum_typespec: (amo_t), line:354
|vpiTypedef:
\_struct_typespec: (branch_inputs_t), line:313
|vpiTypedef:
\_logic_typespec: (branch_predictor_metadata_t), line:32
|vpiTypedef:
\_struct_typespec: (branch_results_t), line:330
|vpiTypedef:
\_enum_typespec: (bus_type_t), line:86
|vpiTypedef:
\_struct_typespec: (csr_inputs_t), line:396
|vpiTypedef:
\_enum_typespec: (csr_op_t), line:218
|vpiTypedef:
\_enum_typespec: (csr_t), line:201
|vpiTypedef:
\_struct_typespec: (data_access_shared_inputs_t), line:427
|vpiTypedef:
\_struct_typespec: (div_inputs_t), line:389
|vpiTypedef:
\_enum_typespec: (div_type), line:66
|vpiTypedef:
\_enum_typespec: (exception_code_t), line:245
|vpiTypedef:
\_struct_typespec: (exception_packet_t), line:263
|vpiTypedef:
\_struct_typespec: (fetch_buffer_packet_t), line:276
|vpiTypedef:
\_enum_typespec: (fifo_type_t), line:440
|vpiTypedef:
\_enum_typespec: (fn3_arith_t), line:76
|vpiTypedef:
\_enum_typespec: (fn3_branch_t), line:126
|vpiTypedef:
\_enum_typespec: (fn3_csr_t), line:212
|vpiTypedef:
\_enum_typespec: (fn3_ls_t), line:115
|vpiTypedef:
\_enum_typespec: (fn3_mul_div_t), line:138
|vpiTypedef:
\_struct_typespec: (gc_inputs_t), line:404
|vpiTypedef:
\_struct_typespec: (inflight_instruction_packet), line:271
|vpiTypedef:
\_logic_typespec: (instruction_id_t), line:30
|vpiTypedef:
\_enum_typespec: (interrupt_code_t), line:261
|vpiTypedef:
\_struct_typespec: (l2_data_attributes_t), line:68
|vpiTypedef:
\_struct_typespec: (l2_mem_request_t), line:58
|vpiTypedef:
\_struct_typespec: (l2_mem_return_data_t), line:75
|vpiTypedef:
\_struct_typespec: (l2_request_t), line:49
|vpiTypedef:
\_struct_typespec: (l2_return_data_t), line:81
|vpiTypedef:
\_struct_typespec: (load_store_inputs_t), line:369
|vpiTypedef:
\_struct_typespec: (mul_inputs_t), line:383
|vpiTypedef:
\_enum_typespec: (opcodes_t), line:48
|vpiTypedef:
\_enum_typespec: (opcodes_trimmed_t), line:65
|vpiTypedef:
\_struct_typespec: (simulation_named_regfile), line:476
|vpiTypedef:
\_struct_typespec: (taiga_trace_events_t), line:442
|vpiTypedef:
\_struct_typespec: (to_l1_arbiter_packet), line:418
|vpiTypedef:
\_struct_typespec: (trace_outputs_t), line:469
|vpiTypedef:
\_logic_typespec: (unit_id_t), line:31
|vpiTypedef:
\_struct_typespec: (unit_writeback_t), line:295
|vpiTypedef:
\_enum_typespec: (vm_t), line:223
|uhdmallInterfaces:
\_interface: work@tracking_interface, file:third_party/cores/taiga/core/interfaces.sv, line:145, parent:work@div_unit_core_wrapper
|vpiDefName:work@tracking_interface
|vpiFullName:work@tracking_interface
|vpiModport:
\_modport: (decode)
|vpiName:decode
|vpiIODecl:
\_io_decl: (issue_id)
|vpiName:issue_id
|vpiDirection:1
|vpiIODecl:
\_io_decl: (id_available)
|vpiName:id_available
|vpiDirection:1
|vpiIODecl:
\_io_decl: (inflight_packet)
|vpiName:inflight_packet
|vpiDirection:2
|vpiIODecl:
\_io_decl: (issued)
|vpiName:issued
|vpiDirection:2
|vpiIODecl:
\_io_decl: (issue_unit_id)
|vpiName:issue_unit_id
|vpiDirection:2
|vpiModport:
\_modport: (wb)
|vpiName:wb
|vpiIODecl:
\_io_decl: (issue_id)
|vpiName:issue_id
|vpiDirection:2
|vpiIODecl:
\_io_decl: (id_available)
|vpiName:id_available
|vpiDirection:2
|vpiIODecl:
\_io_decl: (inflight_packet)
|vpiName:inflight_packet
|vpiDirection:1
|vpiIODecl:
\_io_decl: (issued)
|vpiName:issued
|vpiDirection:1
|vpiIODecl:
\_io_decl: (issue_unit_id)
|vpiName:issue_unit_id
|vpiDirection:1
|vpiNet:
\_logic_net: (issue_id), line:146
|vpiName:issue_id
|vpiFullName:work@tracking_interface.issue_id
|vpiNet:
\_logic_net: (id_available), line:147
|vpiName:id_available
|vpiFullName:work@tracking_interface.id_available
|vpiNetType:36
|vpiNet:
\_logic_net: (inflight_packet), line:149
|vpiName:inflight_packet
|vpiFullName:work@tracking_interface.inflight_packet
|vpiNet:
\_logic_net: (issued), line:150
|vpiName:issued
|vpiFullName:work@tracking_interface.issued
|vpiNetType:36
|vpiNet:
\_logic_net: (issue_unit_id), line:151
|vpiName:issue_unit_id
|vpiFullName:work@tracking_interface.issue_unit_id
|vpiNetType:36
|vpiTypedef:
\_struct_typespec: (alu_inputs_t), line:301
|vpiTypedef:
\_enum_typespec: (alu_logic_op_t), line:84
|vpiTypedef:
\_enum_typespec: (alu_op_t), line:91
|vpiTypedef:
\_enum_typespec: (alu_rs1_op_t), line:97
|vpiTypedef:
\_enum_typespec: (alu_rs2_op_t), line:104
|vpiTypedef:
\_struct_typespec: (amo_alu_inputs_t), line:356
|vpiTypedef:
\_struct_typespec: (amo_details_t), line:362
|vpiTypedef:
\_enum_typespec: (amo_t), line:354
|vpiTypedef:
\_struct_typespec: (branch_inputs_t), line:313
|vpiTypedef:
\_logic_typespec: (branch_predictor_metadata_t), line:32
|vpiTypedef:
\_struct_typespec: (branch_results_t), line:330
|vpiTypedef:
\_enum_typespec: (bus_type_t), line:86
|vpiTypedef:
\_struct_typespec: (csr_inputs_t), line:396
|vpiTypedef:
\_enum_typespec: (csr_op_t), line:218
|vpiTypedef:
\_enum_typespec: (csr_t), line:201
|vpiTypedef:
\_struct_typespec: (data_access_shared_inputs_t), line:427
|vpiTypedef:
\_struct_typespec: (div_inputs_t), line:389
|vpiTypedef:
\_enum_typespec: (div_type), line:66
|vpiTypedef:
\_enum_typespec: (exception_code_t), line:245
|vpiTypedef:
\_struct_typespec: (exception_packet_t), line:263
|vpiTypedef:
\_struct_typespec: (fetch_buffer_packet_t), line:276
|vpiTypedef:
\_enum_typespec: (fifo_type_t), line:440
|vpiTypedef:
\_enum_typespec: (fn3_arith_t), line:76
|vpiTypedef:
\_enum_typespec: (fn3_branch_t), line:126
|vpiTypedef:
\_enum_typespec: (fn3_csr_t), line:212
|vpiTypedef:
\_enum_typespec: (fn3_ls_t), line:115
|vpiTypedef:
\_enum_typespec: (fn3_mul_div_t), line:138
|vpiTypedef:
\_struct_typespec: (gc_inputs_t), line:404
|vpiTypedef:
\_struct_typespec: (inflight_instruction_packet), line:271
|vpiTypedef:
\_logic_typespec: (instruction_id_t), line:30
|vpiTypedef:
\_enum_typespec: (interrupt_code_t), line:261
|vpiTypedef:
\_struct_typespec: (l2_data_attributes_t), line:68
|vpiTypedef:
\_struct_typespec: (l2_mem_request_t), line:58
|vpiTypedef:
\_struct_typespec: (l2_mem_return_data_t), line:75
|vpiTypedef:
\_struct_typespec: (l2_request_t), line:49
|vpiTypedef:
\_struct_typespec: (l2_return_data_t), line:81
|vpiTypedef:
\_struct_typespec: (load_store_inputs_t), line:369
|vpiTypedef:
\_struct_typespec: (mul_inputs_t), line:383
|vpiTypedef:
\_enum_typespec: (opcodes_t), line:48
|vpiTypedef:
\_enum_typespec: (opcodes_trimmed_t), line:65
|vpiTypedef:
\_struct_typespec: (simulation_named_regfile), line:476
|vpiTypedef:
\_struct_typespec: (taiga_trace_events_t), line:442
|vpiTypedef:
\_struct_typespec: (to_l1_arbiter_packet), line:418
|vpiTypedef:
\_struct_typespec: (trace_outputs_t), line:469
|vpiTypedef:
\_logic_typespec: (unit_id_t), line:31
|vpiTypedef:
\_struct_typespec: (unit_writeback_t), line:295
|vpiTypedef:
\_enum_typespec: (vm_t), line:223
|uhdmallInterfaces:
\_interface: work@unit_issue_interface, file:third_party/cores/taiga/core/interfaces.sv, line:52, parent:work@div_unit_core_wrapper
|vpiDefName:work@unit_issue_interface
|vpiFullName:work@unit_issue_interface
|vpiModport:
\_modport: (decode)
|vpiName:decode
|vpiIODecl:
\_io_decl: (ready)
|vpiName:ready
|vpiDirection:1
|vpiIODecl:
\_io_decl: (possible_issue)
|vpiName:possible_issue
|vpiDirection:2
|vpiIODecl:
\_io_decl: (new_request)
|vpiName:new_request
|vpiDirection:2
|vpiIODecl:
\_io_decl: (new_request_r)
|vpiName:new_request_r
|vpiDirection:2
|vpiIODecl:
\_io_decl: (instruction_id)
|vpiName:instruction_id
|vpiDirection:2
|vpiModport:
\_modport: (unit)
|vpiName:unit
|vpiIODecl:
\_io_decl: (ready)
|vpiName:ready
|vpiDirection:2
|vpiIODecl:
\_io_decl: (possible_issue)
|vpiName:possible_issue
|vpiDirection:1
|vpiIODecl:
\_io_decl: (new_request)
|vpiName:new_request
|vpiDirection:1
|vpiIODecl:
\_io_decl: (new_request_r)
|vpiName:new_request_r
|vpiDirection:1
|vpiIODecl:
\_io_decl: (instruction_id)
|vpiName:instruction_id
|vpiDirection:1
|vpiNet:
\_logic_net: (possible_issue), line:53
|vpiName:possible_issue
|vpiFullName:work@unit_issue_interface.possible_issue
|vpiNetType:36
|vpiNet:
\_logic_net: (new_request), line:54
|vpiName:new_request
|vpiFullName:work@unit_issue_interface.new_request
|vpiNetType:36
|vpiNet:
\_logic_net: (new_request_r), line:55
|vpiName:new_request_r
|vpiFullName:work@unit_issue_interface.new_request_r
|vpiNetType:36
|vpiNet:
\_logic_net: (instruction_id), line:56
|vpiName:instruction_id
|vpiFullName:work@unit_issue_interface.instruction_id
|vpiNet:
\_logic_net: (ready), line:58
|vpiName:ready
|vpiFullName:work@unit_issue_interface.ready
|vpiNetType:36
|vpiTypedef:
\_struct_typespec: (alu_inputs_t), line:301
|vpiTypedef:
\_enum_typespec: (alu_logic_op_t), line:84
|vpiTypedef:
\_enum_typespec: (alu_op_t), line:91
|vpiTypedef:
\_enum_typespec: (alu_rs1_op_t), line:97
|vpiTypedef:
\_enum_typespec: (alu_rs2_op_t), line:104
|vpiTypedef:
\_struct_typespec: (amo_alu_inputs_t), line:356
|vpiTypedef:
\_struct_typespec: (amo_details_t), line:362
|vpiTypedef:
\_enum_typespec: (amo_t), line:354
|vpiTypedef:
\_struct_typespec: (branch_inputs_t), line:313
|vpiTypedef:
\_logic_typespec: (branch_predictor_metadata_t), line:32
|vpiTypedef:
\_struct_typespec: (branch_results_t), line:330
|vpiTypedef:
\_enum_typespec: (bus_type_t), line:86
|vpiTypedef:
\_struct_typespec: (csr_inputs_t), line:396
|vpiTypedef:
\_enum_typespec: (csr_op_t), line:218
|vpiTypedef:
\_enum_typespec: (csr_t), line:201
|vpiTypedef:
\_struct_typespec: (data_access_shared_inputs_t), line:427
|vpiTypedef:
\_struct_typespec: (div_inputs_t), line:389
|vpiTypedef:
\_enum_typespec: (div_type), line:66
|vpiTypedef:
\_enum_typespec: (exception_code_t), line:245
|vpiTypedef:
\_struct_typespec: (exception_packet_t), line:263
|vpiTypedef:
\_struct_typespec: (fetch_buffer_packet_t), line:276
|vpiTypedef:
\_enum_typespec: (fifo_type_t), line:440
|vpiTypedef:
\_enum_typespec: (fn3_arith_t), line:76
|vpiTypedef:
\_enum_typespec: (fn3_branch_t), line:126
|vpiTypedef:
\_enum_typespec: (fn3_csr_t), line:212
|vpiTypedef:
\_enum_typespec: (fn3_ls_t), line:115
|vpiTypedef:
\_enum_typespec: (fn3_mul_div_t), line:138
|vpiTypedef:
\_struct_typespec: (gc_inputs_t), line:404
|vpiTypedef:
\_struct_typespec: (inflight_instruction_packet), line:271
|vpiTypedef:
\_logic_typespec: (instruction_id_t), line:30
|vpiTypedef:
\_enum_typespec: (interrupt_code_t), line:261
|vpiTypedef:
\_struct_typespec: (l2_data_attributes_t), line:68
|vpiTypedef:
\_struct_typespec: (l2_mem_request_t), line:58
|vpiTypedef:
\_struct_typespec: (l2_mem_return_data_t), line:75
|vpiTypedef:
\_struct_typespec: (l2_request_t), line:49
|vpiTypedef:
\_struct_typespec: (l2_return_data_t), line:81
|vpiTypedef:
\_struct_typespec: (load_store_inputs_t), line:369
|vpiTypedef:
\_struct_typespec: (mul_inputs_t), line:383
|vpiTypedef:
\_enum_typespec: (opcodes_t), line:48
|vpiTypedef:
\_enum_typespec: (opcodes_trimmed_t), line:65
|vpiTypedef:
\_struct_typespec: (simulation_named_regfile), line:476
|vpiTypedef:
\_struct_typespec: (taiga_trace_events_t), line:442
|vpiTypedef:
\_struct_typespec: (to_l1_arbiter_packet), line:418
|vpiTypedef:
\_struct_typespec: (trace_outputs_t), line:469
|vpiTypedef:
\_logic_typespec: (unit_id_t), line:31
|vpiTypedef:
\_struct_typespec: (unit_writeback_t), line:295
|vpiTypedef:
\_enum_typespec: (vm_t), line:223
|uhdmallInterfaces:
\_interface: work@unsigned_division_interface, file:third_party/cores/taiga/core/interfaces.sv, line:243, parent:work@div_unit_core_wrapper
|vpiDefName:work@unsigned_division_interface
|vpiFullName:work@unsigned_division_interface
|vpiModport:
\_modport: (divider)
|vpiName:divider
|vpiIODecl:
\_io_decl: (remainder)
|vpiName:remainder
|vpiDirection:2
|vpiIODecl:
\_io_decl: (quotient)
|vpiName:quotient
|vpiDirection:2
|vpiIODecl:
\_io_decl: (done)
|vpiName:done
|vpiDirection:2
|vpiIODecl:
\_io_decl: (divisor_is_zero)
|vpiName:divisor_is_zero
|vpiDirection:2
|vpiIODecl:
\_io_decl: (dividend)
|vpiName:dividend
|vpiDirection:1
|vpiIODecl:
\_io_decl: (divisor)
|vpiName:divisor
|vpiDirection:1
|vpiIODecl:
\_io_decl: (start)
|vpiName:start
|vpiDirection:1
|vpiModport:
\_modport: (requester)
|vpiName:requester
|vpiIODecl:
\_io_decl: (remainder)
|vpiName:remainder
|vpiDirection:1
|vpiIODecl:
\_io_decl: (quotient)
|vpiName:quotient
|vpiDirection:1
|vpiIODecl:
\_io_decl: (done)
|vpiName:done
|vpiDirection:1
|vpiIODecl:
\_io_decl: (divisor_is_zero)
|vpiName:divisor_is_zero
|vpiDirection:1
|vpiIODecl:
\_io_decl: (dividend)
|vpiName:dividend
|vpiDirection:2
|vpiIODecl:
\_io_decl: (divisor)
|vpiName:divisor
|vpiDirection:2
|vpiIODecl:
\_io_decl: (start)
|vpiName:start
|vpiDirection:2
|vpiNet:
\_logic_net: (start), line:244
|vpiName:start
|vpiFullName:work@unsigned_division_interface.start
|vpiNetType:36
|vpiNet:
\_logic_net: (dividend), line:245
|vpiName:dividend
|vpiFullName:work@unsigned_division_interface.dividend
|vpiNetType:36
|vpiNet:
\_logic_net: (divisor), line:246
|vpiName:divisor
|vpiFullName:work@unsigned_division_interface.divisor
|vpiNetType:36
|vpiNet:
\_logic_net: (remainder), line:247
|vpiName:remainder
|vpiFullName:work@unsigned_division_interface.remainder
|vpiNetType:36
|vpiNet:
\_logic_net: (quotient), line:248
|vpiName:quotient
|vpiFullName:work@unsigned_division_interface.quotient
|vpiNetType:36
|vpiNet:
\_logic_net: (done), line:249
|vpiName:done
|vpiFullName:work@unsigned_division_interface.done
|vpiNetType:36
|vpiNet:
\_logic_net: (divisor_is_zero), line:250
|vpiName:divisor_is_zero
|vpiFullName:work@unsigned_division_interface.divisor_is_zero
|vpiNetType:36
|vpiTypedef:
\_struct_typespec: (alu_inputs_t), line:301
|vpiTypedef:
\_enum_typespec: (alu_logic_op_t), line:84
|vpiTypedef:
\_enum_typespec: (alu_op_t), line:91
|vpiTypedef:
\_enum_typespec: (alu_rs1_op_t), line:97
|vpiTypedef:
\_enum_typespec: (alu_rs2_op_t), line:104
|vpiTypedef:
\_struct_typespec: (amo_alu_inputs_t), line:356
|vpiTypedef:
\_struct_typespec: (amo_details_t), line:362
|vpiTypedef:
\_enum_typespec: (amo_t), line:354
|vpiTypedef:
\_struct_typespec: (branch_inputs_t), line:313
|vpiTypedef:
\_logic_typespec: (branch_predictor_metadata_t), line:32
|vpiTypedef:
\_struct_typespec: (branch_results_t), line:330
|vpiTypedef:
\_enum_typespec: (bus_type_t), line:86
|vpiTypedef:
\_struct_typespec: (csr_inputs_t), line:396
|vpiTypedef:
\_enum_typespec: (csr_op_t), line:218
|vpiTypedef:
\_enum_typespec: (csr_t), line:201
|vpiTypedef:
\_struct_typespec: (data_access_shared_inputs_t), line:427
|vpiTypedef:
\_struct_typespec: (div_inputs_t), line:389
|vpiTypedef:
\_enum_typespec: (div_type), line:66
|vpiTypedef:
\_enum_typespec: (exception_code_t), line:245
|vpiTypedef:
\_struct_typespec: (exception_packet_t), line:263
|vpiTypedef:
\_struct_typespec: (fetch_buffer_packet_t), line:276
|vpiTypedef:
\_enum_typespec: (fifo_type_t), line:440
|vpiTypedef:
\_enum_typespec: (fn3_arith_t), line:76
|vpiTypedef:
\_enum_typespec: (fn3_branch_t), line:126
|vpiTypedef:
\_enum_typespec: (fn3_csr_t), line:212
|vpiTypedef:
\_enum_typespec: (fn3_ls_t), line:115
|vpiTypedef:
\_enum_typespec: (fn3_mul_div_t), line:138
|vpiTypedef:
\_struct_typespec: (gc_inputs_t), line:404
|vpiTypedef:
\_struct_typespec: (inflight_instruction_packet), line:271
|vpiTypedef:
\_logic_typespec: (instruction_id_t), line:30
|vpiTypedef:
\_enum_typespec: (interrupt_code_t), line:261
|vpiTypedef:
\_struct_typespec: (l2_data_attributes_t), line:68
|vpiTypedef:
\_struct_typespec: (l2_mem_request_t), line:58
|vpiTypedef:
\_struct_typespec: (l2_mem_return_data_t), line:75
|vpiTypedef:
\_struct_typespec: (l2_request_t), line:49
|vpiTypedef:
\_struct_typespec: (l2_return_data_t), line:81
|vpiTypedef:
\_struct_typespec: (load_store_inputs_t), line:369
|vpiTypedef:
\_struct_typespec: (mul_inputs_t), line:383
|vpiTypedef:
\_enum_typespec: (opcodes_t), line:48
|vpiTypedef:
\_enum_typespec: (opcodes_trimmed_t), line:65
|vpiTypedef:
\_struct_typespec: (simulation_named_regfile), line:476
|vpiTypedef:
\_struct_typespec: (taiga_trace_events_t), line:442
|vpiTypedef:
\_struct_typespec: (to_l1_arbiter_packet), line:418
|vpiTypedef:
\_struct_typespec: (trace_outputs_t), line:469
|vpiTypedef:
\_logic_typespec: (unit_id_t), line:31
|vpiTypedef:
\_struct_typespec: (unit_writeback_t), line:295
|vpiTypedef:
\_enum_typespec: (vm_t), line:223
|uhdmallInterfaces:
\_interface: work@wishbone_interface, file:third_party/cores/taiga/core/external_interfaces.sv, line:105, parent:work@div_unit_core_wrapper
|vpiDefName:work@wishbone_interface
|vpiFullName:work@wishbone_interface
|vpiModport:
\_modport: (master)
|vpiName:master
|vpiIODecl:
\_io_decl: (readdata)
|vpiName:readdata
|vpiDirection:1
|vpiIODecl:
\_io_decl: (ack)
|vpiName:ack
|vpiDirection:1
|vpiIODecl:
\_io_decl: (addr)
|vpiName:addr
|vpiDirection:2
|vpiIODecl:
\_io_decl: (we)
|vpiName:we
|vpiDirection:2
|vpiIODecl:
\_io_decl: (sel)
|vpiName:sel
|vpiDirection:2
|vpiIODecl:
\_io_decl: (writedata)
|vpiName:writedata
|vpiDirection:2
|vpiIODecl:
\_io_decl: (stb)
|vpiName:stb
|vpiDirection:2
|vpiIODecl:
\_io_decl: (cyc)
|vpiName:cyc
|vpiDirection:2
|vpiModport:
\_modport: (slave)
|vpiName:slave
|vpiIODecl:
\_io_decl: (readdata)
|vpiName:readdata
|vpiDirection:2
|vpiIODecl:
\_io_decl: (ack)
|vpiName:ack
|vpiDirection:2
|vpiIODecl:
\_io_decl: (addr)
|vpiName:addr
|vpiDirection:1
|vpiIODecl:
\_io_decl: (we)
|vpiName:we
|vpiDirection:1
|vpiIODecl:
\_io_decl: (sel)
|vpiName:sel
|vpiDirection:1
|vpiIODecl:
\_io_decl: (writedata)
|vpiName:writedata
|vpiDirection:1
|vpiIODecl:
\_io_decl: (stb)
|vpiName:stb
|vpiDirection:1
|vpiIODecl:
\_io_decl: (cyc)
|vpiName:cyc
|vpiDirection:1
|vpiNet:
\_logic_net: (addr), line:106
|vpiName:addr
|vpiFullName:work@wishbone_interface.addr
|vpiNetType:36
|vpiNet:
\_logic_net: (we), line:107
|vpiName:we
|vpiFullName:work@wishbone_interface.we
|vpiNetType:36
|vpiNet:
\_logic_net: (sel), line:108
|vpiName:sel
|vpiFullName:work@wishbone_interface.sel
|vpiNetType:36
|vpiNet:
\_logic_net: (readdata), line:109
|vpiName:readdata
|vpiFullName:work@wishbone_interface.readdata
|vpiNetType:36
|vpiNet:
\_logic_net: (writedata), line:110
|vpiName:writedata
|vpiFullName:work@wishbone_interface.writedata
|vpiNetType:36
|vpiNet:
\_logic_net: (stb), line:111
|vpiName:stb
|vpiFullName:work@wishbone_interface.stb
|vpiNetType:36
|vpiNet:
\_logic_net: (cyc), line:112
|vpiName:cyc
|vpiFullName:work@wishbone_interface.cyc
|vpiNetType:36
|vpiNet:
\_logic_net: (ack), line:113
|vpiName:ack
|vpiFullName:work@wishbone_interface.ack
|vpiNetType:36
|vpiTypedef:
\_struct_typespec: (alu_inputs_t), line:301
|vpiTypedef:
\_enum_typespec: (alu_logic_op_t), line:84
|vpiTypedef:
\_enum_typespec: (alu_op_t), line:91
|vpiTypedef:
\_enum_typespec: (alu_rs1_op_t), line:97
|vpiTypedef:
\_enum_typespec: (alu_rs2_op_t), line:104
|vpiTypedef:
\_struct_typespec: (amo_alu_inputs_t), line:356
|vpiTypedef:
\_struct_typespec: (amo_details_t), line:362
|vpiTypedef:
\_enum_typespec: (amo_t), line:354
|vpiTypedef:
\_struct_typespec: (branch_inputs_t), line:313
|vpiTypedef:
\_logic_typespec: (branch_predictor_metadata_t), line:32
|vpiTypedef:
\_struct_typespec: (branch_results_t), line:330
|vpiTypedef:
\_enum_typespec: (bus_type_t), line:86
|vpiTypedef:
\_struct_typespec: (csr_inputs_t), line:396
|vpiTypedef:
\_enum_typespec: (csr_op_t), line:218
|vpiTypedef:
\_enum_typespec: (csr_t), line:201
|vpiTypedef:
\_struct_typespec: (data_access_shared_inputs_t), line:427
|vpiTypedef:
\_struct_typespec: (div_inputs_t), line:389
|vpiTypedef:
\_enum_typespec: (div_type), line:66
|vpiTypedef:
\_enum_typespec: (exception_code_t), line:245
|vpiTypedef:
\_struct_typespec: (exception_packet_t), line:263
|vpiTypedef:
\_struct_typespec: (fetch_buffer_packet_t), line:276
|vpiTypedef:
\_enum_typespec: (fifo_type_t), line:440
|vpiTypedef:
\_enum_typespec: (fn3_arith_t), line:76
|vpiTypedef:
\_enum_typespec: (fn3_branch_t), line:126
|vpiTypedef:
\_enum_typespec: (fn3_csr_t), line:212
|vpiTypedef:
\_enum_typespec: (fn3_ls_t), line:115
|vpiTypedef:
\_enum_typespec: (fn3_mul_div_t), line:138
|vpiTypedef:
\_struct_typespec: (gc_inputs_t), line:404
|vpiTypedef:
\_struct_typespec: (inflight_instruction_packet), line:271
|vpiTypedef:
\_logic_typespec: (instruction_id_t), line:30
|vpiTypedef:
\_enum_typespec: (interrupt_code_t), line:261
|vpiTypedef:
\_struct_typespec: (l2_data_attributes_t), line:68
|vpiTypedef:
\_struct_typespec: (l2_mem_request_t), line:58
|vpiTypedef:
\_struct_typespec: (l2_mem_return_data_t), line:75
|vpiTypedef:
\_struct_typespec: (l2_request_t), line:49
|vpiTypedef:
\_struct_typespec: (l2_return_data_t), line:81
|vpiTypedef:
\_struct_typespec: (load_store_inputs_t), line:369
|vpiTypedef:
\_struct_typespec: (mul_inputs_t), line:383
|vpiTypedef:
\_enum_typespec: (opcodes_t), line:48
|vpiTypedef:
\_enum_typespec: (opcodes_trimmed_t), line:65
|vpiTypedef:
\_struct_typespec: (simulation_named_regfile), line:476
|vpiTypedef:
\_struct_typespec: (taiga_trace_events_t), line:442
|vpiTypedef:
\_struct_typespec: (to_l1_arbiter_packet), line:418
|vpiTypedef:
\_struct_typespec: (trace_outputs_t), line:469
|vpiTypedef:
\_logic_typespec: (unit_id_t), line:31
|vpiTypedef:
\_struct_typespec: (unit_writeback_t), line:295
|vpiTypedef:
\_enum_typespec: (vm_t), line:223
|uhdmallModules:
\_module: work@alu_unit, file:third_party/cores/taiga/core/alu_unit.sv, line:26, parent:work@div_unit_core_wrapper
|vpiDefName:work@alu_unit
|vpiFullName:work@alu_unit
|vpiProcess:
\_always: , line:47
|vpiAlwaysType:2
|vpiStmt:
\_begin: , line:47
|vpiFullName:work@alu_unit
|vpiStmt:
\_case_stmt: , line:48
|vpiCaseType:1
|vpiCondition:
\_ref_obj: (alu_inputs.logic_op), line:48
|vpiName:alu_inputs.logic_op
|vpiFullName:work@alu_unit.alu_inputs.logic_op
|vpiCaseItem:
\_case_item: , line:49
|vpiExpr:
\_ref_obj: (ALU_LOGIC_XOR), line:49
|vpiName:ALU_LOGIC_XOR
|vpiFullName:work@alu_unit.ALU_LOGIC_XOR
|vpiStmt:
\_assignment: , line:49
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (adder_in1), line:49
|vpiName:adder_in1
|vpiFullName:work@alu_unit.adder_in1
|vpiRhs:
\_operation: , line:49
|vpiOpType:30
|vpiOperand:
\_ref_obj: (alu_inputs.in1), line:49
|vpiName:alu_inputs.in1
|vpiFullName:work@alu_unit.alu_inputs.in1
|vpiOperand:
\_ref_obj: (alu_inputs.in2), line:49
|vpiName:alu_inputs.in2
|vpiFullName:work@alu_unit.alu_inputs.in2
|vpiCaseItem:
\_case_item: , line:50
|vpiExpr:
\_ref_obj: (ALU_LOGIC_OR), line:50
|vpiName:ALU_LOGIC_OR
|vpiFullName:work@alu_unit.ALU_LOGIC_OR
|vpiStmt:
\_assignment: , line:50
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (adder_in1), line:50
|vpiName:adder_in1
|vpiFullName:work@alu_unit.adder_in1
|vpiRhs:
\_operation: , line:50
|vpiOpType:29
|vpiOperand:
\_ref_obj: (alu_inputs.in1), line:50
|vpiName:alu_inputs.in1
|vpiFullName:work@alu_unit.alu_inputs.in1
|vpiOperand:
\_ref_obj: (alu_inputs.in2), line:50
|vpiName:alu_inputs.in2
|vpiFullName:work@alu_unit.alu_inputs.in2
|vpiCaseItem:
\_case_item: , line:51
|vpiExpr:
\_ref_obj: (ALU_LOGIC_AND), line:51
|vpiName:ALU_LOGIC_AND
|vpiFullName:work@alu_unit.ALU_LOGIC_AND
|vpiStmt:
\_assignment: , line:51
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (adder_in1), line:51
|vpiName:adder_in1
|vpiFullName:work@alu_unit.adder_in1
|vpiRhs:
\_operation: , line:51
|vpiOpType:28
|vpiOperand:
\_ref_obj: (alu_inputs.in1), line:51
|vpiName:alu_inputs.in1
|vpiFullName:work@alu_unit.alu_inputs.in1
|vpiOperand:
\_ref_obj: (alu_inputs.in2), line:51
|vpiName:alu_inputs.in2
|vpiFullName:work@alu_unit.alu_inputs.in2
|vpiCaseItem:
\_case_item: , line:52
|vpiExpr:
\_ref_obj: (ALU_LOGIC_ADD), line:52
|vpiName:ALU_LOGIC_ADD
|vpiFullName:work@alu_unit.ALU_LOGIC_ADD
|vpiStmt:
\_assignment: , line:52
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (adder_in1), line:52
|vpiName:adder_in1
|vpiFullName:work@alu_unit.adder_in1
|vpiRhs:
\_ref_obj: (alu_inputs.in1), line:52
|vpiName:alu_inputs.in1
|vpiFullName:work@alu_unit.alu_inputs.in1
|vpiStmt:
\_case_stmt: , line:54
|vpiCaseType:1
|vpiCondition:
\_ref_obj: (alu_inputs.logic_op), line:54
|vpiName:alu_inputs.logic_op
|vpiFullName:work@alu_unit.alu_inputs.logic_op
|vpiCaseItem:
\_case_item: , line:55
|vpiExpr:
\_ref_obj: (ALU_LOGIC_XOR), line:55
|vpiName:ALU_LOGIC_XOR
|vpiFullName:work@alu_unit.ALU_LOGIC_XOR
|vpiStmt:
\_assignment: , line:55
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (adder_in2), line:55
|vpiName:adder_in2
|vpiFullName:work@alu_unit.adder_in2
|vpiRhs:
\_constant: , line:55
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiCaseItem:
\_case_item: , line:56
|vpiExpr:
\_ref_obj: (ALU_LOGIC_OR), line:56
|vpiName:ALU_LOGIC_OR
|vpiFullName:work@alu_unit.ALU_LOGIC_OR
|vpiStmt:
\_assignment: , line:56
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (adder_in2), line:56
|vpiName:adder_in2
|vpiFullName:work@alu_unit.adder_in2
|vpiRhs:
\_constant: , line:56
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiCaseItem:
\_case_item: , line:57
|vpiExpr:
\_ref_obj: (ALU_LOGIC_AND), line:57
|vpiName:ALU_LOGIC_AND
|vpiFullName:work@alu_unit.ALU_LOGIC_AND
|vpiStmt:
\_assignment: , line:57
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (adder_in2), line:57
|vpiName:adder_in2
|vpiFullName:work@alu_unit.adder_in2
|vpiRhs:
\_constant: , line:57
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiCaseItem:
\_case_item: , line:58
|vpiExpr:
\_ref_obj: (ALU_LOGIC_ADD), line:58
|vpiName:ALU_LOGIC_ADD
|vpiFullName:work@alu_unit.ALU_LOGIC_ADD
|vpiStmt:
\_assignment: , line:58
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (adder_in2), line:58
|vpiName:adder_in2
|vpiFullName:work@alu_unit.adder_in2
|vpiRhs:
\_operation: , line:58
|vpiOpType:30
|vpiOperand:
\_ref_obj: (alu_inputs.in2), line:58
|vpiName:alu_inputs.in2
|vpiFullName:work@alu_unit.alu_inputs.in2
|vpiOperand:
\_operation: , line:58
|vpiOpType:34
|vpiOperand:
\_constant: , line:58
|vpiConstType:7
|vpiDecompile:33
|vpiSize:32
|INT:33
|vpiOperand:
\_operation:
|vpiOpType:33
|vpiOperand:
\_ref_obj: (alu_inputs.subtract), line:58
|vpiName:alu_inputs.subtract
|vpiFullName:work@alu_unit.alu_inputs.subtract
|vpiProcess:
\_always: , line:74
|vpiAlwaysType:2
|vpiStmt:
\_begin: , line:74
|vpiFullName:work@alu_unit
|vpiStmt:
\_case_stmt: , line:75
|vpiCaseType:1
|vpiCondition:
\_ref_obj: (alu_inputs.op), line:75
|vpiName:alu_inputs.op
|vpiFullName:work@alu_unit.alu_inputs.op
|vpiCaseItem:
\_case_item: , line:76
|vpiExpr:
\_ref_obj: (ALU_ADD_SUB), line:76
|vpiName:ALU_ADD_SUB
|vpiFullName:work@alu_unit.ALU_ADD_SUB
|vpiStmt:
\_assignment: , line:76
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (result), line:76
|vpiName:result
|vpiFullName:work@alu_unit.result
|vpiRhs:
\_part_select: , line:76, parent:add_sub_result
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (add_sub_result)
|vpiLeftRange:
\_operation: , line:76
|vpiOpType:11
|vpiOperand:
\_ref_obj: (XLEN), line:76
|vpiName:XLEN
|vpiOperand:
\_constant: , line:76
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:76
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiCaseItem:
\_case_item: , line:77
|vpiExpr:
\_ref_obj: (ALU_SLT), line:77
|vpiName:ALU_SLT
|vpiFullName:work@alu_unit.ALU_SLT
|vpiStmt:
\_assignment: , line:77
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (result), line:77
|vpiName:result
|vpiFullName:work@alu_unit.result
|vpiRhs:
\_operation: , line:77
|vpiOpType:33
|vpiOperand:
\_constant: , line:77
|vpiConstType:3
|vpiDecompile:31'b0
|vpiSize:31
|BIN:31'b0
|vpiOperand:
\_bit_select: (add_sub_result), line:77
|vpiName:add_sub_result
|vpiIndex:
\_ref_obj: (XLEN), line:77
|vpiName:XLEN
|vpiCaseItem:
\_case_item: , line:78
|vpiExpr:
\_ref_obj: (ALU_RSHIFT), line:78
|vpiName:ALU_RSHIFT
|vpiFullName:work@alu_unit.ALU_RSHIFT
|vpiStmt:
\_assignment: , line:78
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (result), line:78
|vpiName:result
|vpiFullName:work@alu_unit.result
|vpiRhs:
\_ref_obj: (rshift_result), line:78
|vpiName:rshift_result
|vpiFullName:work@alu_unit.rshift_result
|vpiCaseItem:
\_case_item: , line:79
|vpiExpr:
\_ref_obj: (ALU_LSHIFT), line:79
|vpiName:ALU_LSHIFT
|vpiFullName:work@alu_unit.ALU_LSHIFT
|vpiStmt:
\_assignment: , line:79
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (result), line:79
|vpiName:result
|vpiFullName:work@alu_unit.result
|vpiRhs:
\_ref_obj: (lshift_result), line:79
|vpiName:lshift_result
|vpiFullName:work@alu_unit.lshift_result
|vpiPort:
\_port: (clk), line:27
|vpiName:clk
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (clk), line:27
|vpiName:clk
|vpiFullName:work@alu_unit.clk
|vpiNetType:36
|vpiPort:
\_port: (rst), line:28
|vpiName:rst
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (rst), line:28
|vpiName:rst
|vpiFullName:work@alu_unit.rst
|vpiNetType:36
|vpiPort:
\_port: (issue), line:29
|vpiName:issue
|vpiDirection:5
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_modport: (unit)
|vpiPort:
\_port: (alu_inputs), line:30
|vpiName:alu_inputs
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (alu_inputs), line:30
|vpiName:alu_inputs
|vpiFullName:work@alu_unit.alu_inputs
|vpiPort:
\_port: (wb), line:31
|vpiName:wb
|vpiDirection:2
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (wb), line:31
|vpiName:wb
|vpiFullName:work@alu_unit.wb
|vpiContAssign:
\_cont_assign: , line:62
|vpiRhs:
\_operation: , line:62
|vpiOpType:24
|vpiOperand:
\_operation: , line:62
|vpiOpType:33
|vpiOperand:
\_ref_obj: (adder_in1), line:62
|vpiName:adder_in1
|vpiOperand:
\_ref_obj: (alu_inputs.subtract), line:62
|vpiName:alu_inputs.subtract
|vpiOperand:
\_operation: , line:62
|vpiOpType:33
|vpiOperand:
\_ref_obj: (adder_in2), line:62
|vpiName:adder_in2
|vpiFullName:work@alu_unit.adder_in2
|vpiOperand:
\_ref_obj: (alu_inputs.subtract), line:62
|vpiName:alu_inputs.subtract
|vpiFullName:work@alu_unit.alu_inputs.subtract
|vpiLhs:
\_operation: , line:62
|vpiOpType:33
|vpiOperand:
\_ref_obj: (add_sub_result), line:62
|vpiName:add_sub_result
|vpiFullName:work@alu_unit.add_sub_result
|vpiOperand:
\_ref_obj: (add_sub_carry_in), line:62
|vpiName:add_sub_carry_in
|vpiFullName:work@alu_unit.add_sub_carry_in
|vpiContAssign:
\_cont_assign: , line:85
|vpiRhs:
\_constant: , line:85
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiLhs:
\_ref_obj: (issue.ready), line:85
|vpiName:issue.ready
|vpiFullName:work@alu_unit.issue.ready
|vpiContAssign:
\_cont_assign: , line:86
|vpiRhs:
\_ref_obj: (result), line:86
|vpiName:result
|vpiFullName:work@alu_unit.result
|vpiLhs:
\_ref_obj: (wb.rd), line:86
|vpiName:wb.rd
|vpiFullName:work@alu_unit.wb.rd
|vpiContAssign:
\_cont_assign: , line:87
|vpiRhs:
\_ref_obj: (issue.new_request), line:87
|vpiName:issue.new_request
|vpiFullName:work@alu_unit.issue.new_request
|vpiLhs:
\_ref_obj: (wb.done), line:87
|vpiName:wb.done
|vpiFullName:work@alu_unit.wb.done
|vpiContAssign:
\_cont_assign: , line:88
|vpiRhs:
\_ref_obj: (issue.instruction_id), line:88
|vpiName:issue.instruction_id
|vpiFullName:work@alu_unit.issue.instruction_id
|vpiLhs:
\_ref_obj: (wb.id), line:88
|vpiName:wb.id
|vpiFullName:work@alu_unit.wb.id
|vpiNet:
\_logic_net: (clk), line:27
|vpiNet:
\_logic_net: (rst), line:28
|vpiNet:
\_logic_net: (alu_inputs), line:30
|vpiNet:
\_logic_net: (wb), line:31
|vpiNet:
\_logic_net: (add_sub_result), line:34
|vpiName:add_sub_result
|vpiFullName:work@alu_unit.add_sub_result
|vpiNetType:36
|vpiNet:
\_logic_net: (add_sub_carry_in), line:35
|vpiName:add_sub_carry_in
|vpiFullName:work@alu_unit.add_sub_carry_in
|vpiNetType:36
|vpiNet:
\_logic_net: (rshift_result), line:36
|vpiName:rshift_result
|vpiFullName:work@alu_unit.rshift_result
|vpiNetType:36
|vpiNet:
\_logic_net: (lshift_result), line:37
|vpiName:lshift_result
|vpiFullName:work@alu_unit.lshift_result
|vpiNetType:36
|vpiNet:
\_logic_net: (adder_in1), line:39
|vpiName:adder_in1
|vpiFullName:work@alu_unit.adder_in1
|vpiNetType:36
|vpiNet:
\_logic_net: (adder_in2), line:40
|vpiName:adder_in2
|vpiFullName:work@alu_unit.adder_in2
|vpiNetType:36
|vpiNet:
\_logic_net: (result), line:42
|vpiName:result
|vpiFullName:work@alu_unit.result
|vpiNetType:36
|vpiNet:
\_logic_net: (issue), line:29
|vpiName:issue
|vpiFullName:work@alu_unit.issue
|vpiTypedef:
\_struct_typespec: (alu_inputs_t), line:301
|vpiTypedef:
\_enum_typespec: (alu_logic_op_t), line:84
|vpiTypedef:
\_enum_typespec: (alu_op_t), line:91
|vpiTypedef:
\_enum_typespec: (alu_rs1_op_t), line:97
|vpiTypedef:
\_enum_typespec: (alu_rs2_op_t), line:104
|vpiTypedef:
\_struct_typespec: (amo_alu_inputs_t), line:356
|vpiTypedef:
\_struct_typespec: (amo_details_t), line:362
|vpiTypedef:
\_enum_typespec: (amo_t), line:354
|vpiTypedef:
\_struct_typespec: (branch_inputs_t), line:313
|vpiTypedef:
\_logic_typespec: (branch_predictor_metadata_t), line:32
|vpiTypedef:
\_struct_typespec: (branch_results_t), line:330
|vpiTypedef:
\_enum_typespec: (bus_type_t), line:86
|vpiTypedef:
\_struct_typespec: (csr_inputs_t), line:396
|vpiTypedef:
\_enum_typespec: (csr_op_t), line:218
|vpiTypedef:
\_enum_typespec: (csr_t), line:201
|vpiTypedef:
\_struct_typespec: (data_access_shared_inputs_t), line:427
|vpiTypedef:
\_struct_typespec: (div_inputs_t), line:389
|vpiTypedef:
\_enum_typespec: (div_type), line:66
|vpiTypedef:
\_enum_typespec: (exception_code_t), line:245
|vpiTypedef:
\_struct_typespec: (exception_packet_t), line:263
|vpiTypedef:
\_struct_typespec: (fetch_buffer_packet_t), line:276
|vpiTypedef:
\_enum_typespec: (fifo_type_t), line:440
|vpiTypedef:
\_enum_typespec: (fn3_arith_t), line:76
|vpiTypedef:
\_enum_typespec: (fn3_branch_t), line:126
|vpiTypedef:
\_enum_typespec: (fn3_csr_t), line:212
|vpiTypedef:
\_enum_typespec: (fn3_ls_t), line:115
|vpiTypedef:
\_enum_typespec: (fn3_mul_div_t), line:138
|vpiTypedef:
\_struct_typespec: (gc_inputs_t), line:404
|vpiTypedef:
\_struct_typespec: (inflight_instruction_packet), line:271
|vpiTypedef:
\_logic_typespec: (instruction_id_t), line:30
|vpiTypedef:
\_enum_typespec: (interrupt_code_t), line:261
|vpiTypedef:
\_struct_typespec: (load_store_inputs_t), line:369
|vpiTypedef:
\_struct_typespec: (mul_inputs_t), line:383
|vpiTypedef:
\_enum_typespec: (opcodes_t), line:48
|vpiTypedef:
\_enum_typespec: (opcodes_trimmed_t), line:65
|vpiTypedef:
\_struct_typespec: (simulation_named_regfile), line:476
|vpiTypedef:
\_struct_typespec: (taiga_trace_events_t), line:442
|vpiTypedef:
\_struct_typespec: (to_l1_arbiter_packet), line:418
|vpiTypedef:
\_struct_typespec: (trace_outputs_t), line:469
|vpiTypedef:
\_logic_typespec: (unit_id_t), line:31
|vpiTypedef:
\_struct_typespec: (unit_writeback_t), line:295
|vpiTypedef:
\_enum_typespec: (vm_t), line:223
|uhdmallModules:
\_module: work@amo_alu, file:third_party/cores/taiga/core/amo_alu.sv, line:26, parent:work@div_unit_core_wrapper
|vpiDefName:work@amo_alu
|vpiFullName:work@amo_alu
|vpiProcess:
\_always: , line:41
|vpiAlwaysType:2
|vpiStmt:
\_begin: , line:41
|vpiFullName:work@amo_alu
|vpiStmt:
\_case_stmt: , line:42
|vpiCaseType:1
|vpiQualifier:1
|vpiCondition:
\_ref_obj: (amo_alu_inputs.op), line:42
|vpiName:amo_alu_inputs.op
|vpiFullName:work@amo_alu.amo_alu_inputs.op
|vpiCaseItem:
\_case_item: , line:43
|vpiExpr:
\_ref_obj: (AMO_SWAP), line:43
|vpiName:AMO_SWAP
|vpiFullName:work@amo_alu.AMO_SWAP
|vpiStmt:
\_assignment: , line:43
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (result), line:43
|vpiName:result
|vpiFullName:work@amo_alu.result
|vpiRhs:
\_ref_obj: (amo_alu_inputs.rs2), line:43
|vpiName:amo_alu_inputs.rs2
|vpiFullName:work@amo_alu.amo_alu_inputs.rs2
|vpiCaseItem:
\_case_item: , line:44
|vpiExpr:
\_ref_obj: (AMO_ADD), line:44
|vpiName:AMO_ADD
|vpiFullName:work@amo_alu.AMO_ADD
|vpiStmt:
\_assignment: , line:44
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (result), line:44
|vpiName:result
|vpiFullName:work@amo_alu.result
|vpiRhs:
\_operation: , line:44
|vpiOpType:24
|vpiOperand:
\_ref_obj: (amo_alu_inputs.rs1_load), line:44
|vpiName:amo_alu_inputs.rs1_load
|vpiFullName:work@amo_alu.amo_alu_inputs.rs1_load
|vpiOperand:
\_ref_obj: (amo_alu_inputs.rs2), line:44
|vpiName:amo_alu_inputs.rs2
|vpiFullName:work@amo_alu.amo_alu_inputs.rs2
|vpiCaseItem:
\_case_item: , line:45
|vpiExpr:
\_ref_obj: (AMO_XOR), line:45
|vpiName:AMO_XOR
|vpiFullName:work@amo_alu.AMO_XOR
|vpiStmt:
\_assignment: , line:45
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (result), line:45
|vpiName:result
|vpiFullName:work@amo_alu.result
|vpiRhs:
\_operation: , line:45
|vpiOpType:30
|vpiOperand:
\_ref_obj: (amo_alu_inputs.rs1_load), line:45
|vpiName:amo_alu_inputs.rs1_load
|vpiFullName:work@amo_alu.amo_alu_inputs.rs1_load
|vpiOperand:
\_ref_obj: (amo_alu_inputs.rs2), line:45
|vpiName:amo_alu_inputs.rs2
|vpiFullName:work@amo_alu.amo_alu_inputs.rs2
|vpiCaseItem:
\_case_item: , line:46
|vpiExpr:
\_ref_obj: (AMO_AND), line:46
|vpiName:AMO_AND
|vpiFullName:work@amo_alu.AMO_AND
|vpiStmt:
\_assignment: , line:46
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (result), line:46
|vpiName:result
|vpiFullName:work@amo_alu.result
|vpiRhs:
\_operation: , line:46
|vpiOpType:28
|vpiOperand:
\_ref_obj: (amo_alu_inputs.rs1_load), line:46
|vpiName:amo_alu_inputs.rs1_load
|vpiFullName:work@amo_alu.amo_alu_inputs.rs1_load
|vpiOperand:
\_ref_obj: (amo_alu_inputs.rs2), line:46
|vpiName:amo_alu_inputs.rs2
|vpiFullName:work@amo_alu.amo_alu_inputs.rs2
|vpiCaseItem:
\_case_item: , line:47
|vpiExpr:
\_ref_obj: (AMO_OR), line:47
|vpiName:AMO_OR
|vpiFullName:work@amo_alu.AMO_OR
|vpiStmt:
\_assignment: , line:47
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (result), line:47
|vpiName:result
|vpiFullName:work@amo_alu.result
|vpiRhs:
\_operation: , line:47
|vpiOpType:29
|vpiOperand:
\_ref_obj: (amo_alu_inputs.rs1_load), line:47
|vpiName:amo_alu_inputs.rs1_load
|vpiFullName:work@amo_alu.amo_alu_inputs.rs1_load
|vpiOperand:
\_ref_obj: (amo_alu_inputs.rs2), line:47
|vpiName:amo_alu_inputs.rs2
|vpiFullName:work@amo_alu.amo_alu_inputs.rs2
|vpiCaseItem:
\_case_item: , line:48
|vpiExpr:
\_ref_obj: (AMO_MIN), line:48
|vpiName:AMO_MIN
|vpiFullName:work@amo_alu.AMO_MIN
|vpiStmt:
\_assignment: , line:48
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (result), line:48
|vpiName:result
|vpiFullName:work@amo_alu.result
|vpiRhs:
\_operation: , line:48
|vpiOpType:32
|vpiOperand:
\_ref_obj: (rs1_smaller_than_rs2), line:48
|vpiName:rs1_smaller_than_rs2
|vpiFullName:work@amo_alu.rs1_smaller_than_rs2
|vpiOperand:
\_ref_obj: (amo_alu_inputs.rs1_load), line:48
|vpiName:amo_alu_inputs.rs1_load
|vpiFullName:work@amo_alu.amo_alu_inputs.rs1_load
|vpiOperand:
\_ref_obj: (amo_alu_inputs.rs2), line:48
|vpiName:amo_alu_inputs.rs2
|vpiFullName:work@amo_alu.amo_alu_inputs.rs2
|vpiCaseItem:
\_case_item: , line:49
|vpiExpr:
\_ref_obj: (AMO_MAX), line:49
|vpiName:AMO_MAX
|vpiFullName:work@amo_alu.AMO_MAX
|vpiStmt:
\_assignment: , line:49
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (result), line:49
|vpiName:result
|vpiFullName:work@amo_alu.result
|vpiRhs:
\_operation: , line:49
|vpiOpType:32
|vpiOperand:
\_ref_obj: (rs1_smaller_than_rs2), line:49
|vpiName:rs1_smaller_than_rs2
|vpiFullName:work@amo_alu.rs1_smaller_than_rs2
|vpiOperand:
\_ref_obj: (amo_alu_inputs.rs2), line:49
|vpiName:amo_alu_inputs.rs2
|vpiFullName:work@amo_alu.amo_alu_inputs.rs2
|vpiOperand:
\_ref_obj: (amo_alu_inputs.rs1_load), line:49
|vpiName:amo_alu_inputs.rs1_load
|vpiFullName:work@amo_alu.amo_alu_inputs.rs1_load
|vpiCaseItem:
\_case_item: , line:50
|vpiExpr:
\_ref_obj: (AMO_MINU), line:50
|vpiName:AMO_MINU
|vpiFullName:work@amo_alu.AMO_MINU
|vpiStmt:
\_assignment: , line:50
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (result), line:50
|vpiName:result
|vpiFullName:work@amo_alu.result
|vpiRhs:
\_operation: , line:50
|vpiOpType:32
|vpiOperand:
\_ref_obj: (rs1_smaller_than_rs2), line:50
|vpiName:rs1_smaller_than_rs2
|vpiFullName:work@amo_alu.rs1_smaller_than_rs2
|vpiOperand:
\_ref_obj: (amo_alu_inputs.rs1_load), line:50
|vpiName:amo_alu_inputs.rs1_load
|vpiFullName:work@amo_alu.amo_alu_inputs.rs1_load
|vpiOperand:
\_ref_obj: (amo_alu_inputs.rs2), line:50
|vpiName:amo_alu_inputs.rs2
|vpiFullName:work@amo_alu.amo_alu_inputs.rs2
|vpiCaseItem:
\_case_item: , line:51
|vpiExpr:
\_ref_obj: (AMO_MAXU), line:51
|vpiName:AMO_MAXU
|vpiFullName:work@amo_alu.AMO_MAXU
|vpiStmt:
\_assignment: , line:51
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (result), line:51
|vpiName:result
|vpiFullName:work@amo_alu.result
|vpiRhs:
\_operation: , line:51
|vpiOpType:32
|vpiOperand:
\_ref_obj: (rs1_smaller_than_rs2), line:51
|vpiName:rs1_smaller_than_rs2
|vpiFullName:work@amo_alu.rs1_smaller_than_rs2
|vpiOperand:
\_ref_obj: (amo_alu_inputs.rs2), line:51
|vpiName:amo_alu_inputs.rs2
|vpiFullName:work@amo_alu.amo_alu_inputs.rs2
|vpiOperand:
\_ref_obj: (amo_alu_inputs.rs1_load), line:51
|vpiName:amo_alu_inputs.rs1_load
|vpiFullName:work@amo_alu.amo_alu_inputs.rs1_load
|vpiPort:
\_port: (amo_alu_inputs), line:27
|vpiName:amo_alu_inputs
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (amo_alu_inputs), line:27
|vpiName:amo_alu_inputs
|vpiFullName:work@amo_alu.amo_alu_inputs
|vpiPort:
\_port: (result), line:28
|vpiName:result
|vpiDirection:2
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (result), line:28
|vpiName:result
|vpiFullName:work@amo_alu.result
|vpiNetType:36
|vpiContAssign:
\_cont_assign: , line:36
|vpiRhs:
\_operation: , line:36
|vpiOpType:33
|vpiOperand:
\_operation: , line:36
|vpiOpType:28
|vpiOperand:
\_operation: , line:36
|vpiOpType:4
|vpiOperand:
\_ref_obj: (amo_alu_inputs.op), line:36
|vpiName:amo_alu_inputs.op
|vpiOperand:
\_ref_obj: (amo_alu_inputs.rs1_load), line:36
|vpiName:amo_alu_inputs.rs1_load
|vpiOperand:
\_ref_obj: (amo_alu_inputs.rs1_load), line:36
|vpiName:amo_alu_inputs.rs1_load
|vpiLhs:
\_ref_obj: (rs1_ext), line:36
|vpiName:rs1_ext
|vpiFullName:work@amo_alu.rs1_ext
|vpiContAssign:
\_cont_assign: , line:37
|vpiRhs:
\_operation: , line:37
|vpiOpType:33
|vpiOperand:
\_operation: , line:37
|vpiOpType:28
|vpiOperand:
\_operation: , line:37
|vpiOpType:4
|vpiOperand:
\_ref_obj: (amo_alu_inputs.op), line:37
|vpiName:amo_alu_inputs.op
|vpiOperand:
\_ref_obj: (amo_alu_inputs.rs2), line:37
|vpiName:amo_alu_inputs.rs2
|vpiOperand:
\_ref_obj: (amo_alu_inputs.rs2), line:37
|vpiName:amo_alu_inputs.rs2
|vpiLhs:
\_ref_obj: (rs2_ext), line:37
|vpiName:rs2_ext
|vpiFullName:work@amo_alu.rs2_ext
|vpiContAssign:
\_cont_assign: , line:39
|vpiRhs:
\_operation: , line:39
|vpiOpType:20
|vpiOperand:
\_ref_obj: (rs1_ext), line:39
|vpiName:rs1_ext
|vpiFullName:work@amo_alu.rs1_ext
|vpiOperand:
\_ref_obj: (rs2_ext), line:39
|vpiName:rs2_ext
|vpiFullName:work@amo_alu.rs2_ext
|vpiLhs:
\_ref_obj: (rs1_smaller_than_rs2), line:39
|vpiName:rs1_smaller_than_rs2
|vpiFullName:work@amo_alu.rs1_smaller_than_rs2
|vpiNet:
\_logic_net: (amo_alu_inputs), line:27
|vpiNet:
\_logic_net: (result), line:28
|vpiNet:
\_logic_net: (rs1_smaller_than_rs2), line:31
|vpiName:rs1_smaller_than_rs2
|vpiFullName:work@amo_alu.rs1_smaller_than_rs2
|vpiNetType:36
|vpiNet:
\_logic_net: (rs1_ext), line:32
|vpiName:rs1_ext
|vpiFullName:work@amo_alu.rs1_ext
|vpiNetType:36
|vpiNet:
\_logic_net: (rs2_ext), line:33
|vpiName:rs2_ext
|vpiFullName:work@amo_alu.rs2_ext
|vpiNetType:36
|vpiTypedef:
\_struct_typespec: (alu_inputs_t), line:301
|vpiTypedef:
\_enum_typespec: (alu_logic_op_t), line:84
|vpiTypedef:
\_enum_typespec: (alu_op_t), line:91
|vpiTypedef:
\_enum_typespec: (alu_rs1_op_t), line:97
|vpiTypedef:
\_enum_typespec: (alu_rs2_op_t), line:104
|vpiTypedef:
\_struct_typespec: (amo_alu_inputs_t), line:356
|vpiTypedef:
\_struct_typespec: (amo_details_t), line:362
|vpiTypedef:
\_enum_typespec: (amo_t), line:354
|vpiTypedef:
\_struct_typespec: (branch_inputs_t), line:313
|vpiTypedef:
\_logic_typespec: (branch_predictor_metadata_t), line:32
|vpiTypedef:
\_struct_typespec: (branch_results_t), line:330
|vpiTypedef:
\_enum_typespec: (bus_type_t), line:86
|vpiTypedef:
\_struct_typespec: (csr_inputs_t), line:396
|vpiTypedef:
\_enum_typespec: (csr_op_t), line:218
|vpiTypedef:
\_enum_typespec: (csr_t), line:201
|vpiTypedef:
\_struct_typespec: (data_access_shared_inputs_t), line:427
|vpiTypedef:
\_struct_typespec: (div_inputs_t), line:389
|vpiTypedef:
\_enum_typespec: (div_type), line:66
|vpiTypedef:
\_enum_typespec: (exception_code_t), line:245
|vpiTypedef:
\_struct_typespec: (exception_packet_t), line:263
|vpiTypedef:
\_struct_typespec: (fetch_buffer_packet_t), line:276
|vpiTypedef:
\_enum_typespec: (fifo_type_t), line:440
|vpiTypedef:
\_enum_typespec: (fn3_arith_t), line:76
|vpiTypedef:
\_enum_typespec: (fn3_branch_t), line:126
|vpiTypedef:
\_enum_typespec: (fn3_csr_t), line:212
|vpiTypedef:
\_enum_typespec: (fn3_ls_t), line:115
|vpiTypedef:
\_enum_typespec: (fn3_mul_div_t), line:138
|vpiTypedef:
\_struct_typespec: (gc_inputs_t), line:404
|vpiTypedef:
\_struct_typespec: (inflight_instruction_packet), line:271
|vpiTypedef:
\_logic_typespec: (instruction_id_t), line:30
|vpiTypedef:
\_enum_typespec: (interrupt_code_t), line:261
|vpiTypedef:
\_struct_typespec: (load_store_inputs_t), line:369
|vpiTypedef:
\_struct_typespec: (mul_inputs_t), line:383
|vpiTypedef:
\_enum_typespec: (opcodes_t), line:48
|vpiTypedef:
\_enum_typespec: (opcodes_trimmed_t), line:65
|vpiTypedef:
\_struct_typespec: (simulation_named_regfile), line:476
|vpiTypedef:
\_struct_typespec: (taiga_trace_events_t), line:442
|vpiTypedef:
\_struct_typespec: (to_l1_arbiter_packet), line:418
|vpiTypedef:
\_struct_typespec: (trace_outputs_t), line:469
|vpiTypedef:
\_logic_typespec: (unit_id_t), line:31
|vpiTypedef:
\_struct_typespec: (unit_writeback_t), line:295
|vpiTypedef:
\_enum_typespec: (vm_t), line:223
|uhdmallModules:
\_module: work@avalon_master, file:third_party/cores/taiga/core/avalon_master.sv, line:27, parent:work@div_unit_core_wrapper
|vpiDefName:work@avalon_master
|vpiFullName:work@avalon_master
|vpiProcess:
\_always: , line:42
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:42
|vpiCondition:
\_operation: , line:42
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:42
|vpiName:clk
|vpiFullName:work@avalon_master.clk
|vpiStmt:
\_begin: , line:42
|vpiFullName:work@avalon_master
|vpiStmt:
\_if_stmt: , line:43
|vpiCondition:
\_ref_obj: (ls.new_request), line:43
|vpiName:ls.new_request
|vpiFullName:work@avalon_master.ls.new_request
|vpiStmt:
\_begin: , line:43
|vpiFullName:work@avalon_master
|vpiStmt:
\_assignment: , line:44
|vpiOpType:82
|vpiLhs:
\_ref_obj: (m_avalon.addr), line:44
|vpiName:m_avalon.addr
|vpiFullName:work@avalon_master.m_avalon.addr
|vpiRhs:
\_ref_obj: (ls_inputs.addr), line:44
|vpiName:ls_inputs.addr
|vpiFullName:work@avalon_master.ls_inputs.addr
|vpiStmt:
\_assignment: , line:45
|vpiOpType:82
|vpiLhs:
\_ref_obj: (m_avalon.byteenable), line:45
|vpiName:m_avalon.byteenable
|vpiFullName:work@avalon_master.m_avalon.byteenable
|vpiRhs:
\_ref_obj: (ls_inputs.be), line:45
|vpiName:ls_inputs.be
|vpiFullName:work@avalon_master.ls_inputs.be
|vpiStmt:
\_assignment: , line:46
|vpiOpType:82
|vpiLhs:
\_ref_obj: (m_avalon.writedata), line:46
|vpiName:m_avalon.writedata
|vpiFullName:work@avalon_master.m_avalon.writedata
|vpiRhs:
\_ref_obj: (ls_inputs.data_in), line:46
|vpiName:ls_inputs.data_in
|vpiFullName:work@avalon_master.ls_inputs.data_in
|vpiProcess:
\_always: , line:50
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:50
|vpiCondition:
\_operation: , line:50
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:50
|vpiName:clk
|vpiFullName:work@avalon_master.clk
|vpiStmt:
\_begin: , line:50
|vpiFullName:work@avalon_master
|vpiStmt:
\_if_else: , line:51
|vpiCondition:
\_ref_obj: (rst), line:51
|vpiName:rst
|vpiFullName:work@avalon_master.rst
|vpiStmt:
\_assignment: , line:52
|vpiOpType:82
|vpiLhs:
\_ref_obj: (ls.ready), line:52
|vpiName:ls.ready
|vpiFullName:work@avalon_master.ls.ready
|vpiRhs:
\_constant: , line:52
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiElseStmt:
\_if_else: , line:53
|vpiCondition:
\_ref_obj: (ls.new_request), line:53
|vpiName:ls.new_request
|vpiFullName:work@avalon_master.ls.new_request
|vpiStmt:
\_assignment: , line:54
|vpiOpType:82
|vpiLhs:
\_ref_obj: (ls.ready), line:54
|vpiName:ls.ready
|vpiFullName:work@avalon_master.ls.ready
|vpiRhs:
\_constant: , line:54
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiElseStmt:
\_if_stmt: , line:55
|vpiCondition:
\_operation: , line:55
|vpiOpType:28
|vpiOperand:
\_operation: , line:55
|vpiOpType:4
|vpiOperand:
\_ref_obj: (ls.ready), line:55
|vpiName:ls.ready
|vpiFullName:work@avalon_master.ls.ready
|vpiOperand:
\_operation: , line:55
|vpiOpType:4
|vpiOperand:
\_ref_obj: (m_avalon.waitrequest), line:55
|vpiName:m_avalon.waitrequest
|vpiFullName:work@avalon_master.m_avalon.waitrequest
|vpiStmt:
\_assignment: , line:56
|vpiOpType:82
|vpiLhs:
\_ref_obj: (ls.ready), line:56
|vpiName:ls.ready
|vpiFullName:work@avalon_master.ls.ready
|vpiRhs:
\_constant: , line:56
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiProcess:
\_always: , line:59
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:59
|vpiCondition:
\_operation: , line:59
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:59
|vpiName:clk
|vpiFullName:work@avalon_master.clk
|vpiStmt:
\_begin: , line:59
|vpiFullName:work@avalon_master
|vpiStmt:
\_if_else: , line:60
|vpiCondition:
\_ref_obj: (rst), line:60
|vpiName:rst
|vpiFullName:work@avalon_master.rst
|vpiStmt:
\_assignment: , line:61
|vpiOpType:82
|vpiLhs:
\_ref_obj: (ls.data_valid), line:61
|vpiName:ls.data_valid
|vpiFullName:work@avalon_master.ls.data_valid
|vpiRhs:
\_constant: , line:61
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiElseStmt:
\_if_else: , line:62
|vpiCondition:
\_operation: , line:62
|vpiOpType:28
|vpiOperand:
\_ref_obj: (m_avalon.read), line:62
|vpiName:m_avalon.read
|vpiFullName:work@avalon_master.m_avalon.read
|vpiOperand:
\_operation: , line:62
|vpiOpType:4
|vpiOperand:
\_ref_obj: (m_avalon.waitrequest), line:62
|vpiName:m_avalon.waitrequest
|vpiFullName:work@avalon_master.m_avalon.waitrequest
|vpiStmt:
\_assignment: , line:63
|vpiOpType:82
|vpiLhs:
\_ref_obj: (ls.data_valid), line:63
|vpiName:ls.data_valid
|vpiFullName:work@avalon_master.ls.data_valid
|vpiRhs:
\_constant: , line:63
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiElseStmt:
\_assignment: , line:65
|vpiOpType:82
|vpiLhs:
\_ref_obj: (ls.data_valid), line:65
|vpiName:ls.data_valid
|vpiFullName:work@avalon_master.ls.data_valid
|vpiRhs:
\_constant: , line:65
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiProcess:
\_always: , line:68
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:68
|vpiCondition:
\_operation: , line:68
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:68
|vpiName:clk
|vpiFullName:work@avalon_master.clk
|vpiStmt:
\_begin: , line:68
|vpiFullName:work@avalon_master
|vpiStmt:
\_if_else: , line:69
|vpiCondition:
\_operation: , line:69
|vpiOpType:28
|vpiOperand:
\_ref_obj: (m_avalon.read), line:69
|vpiName:m_avalon.read
|vpiFullName:work@avalon_master.m_avalon.read
|vpiOperand:
\_operation: , line:69
|vpiOpType:4
|vpiOperand:
\_ref_obj: (m_avalon.waitrequest), line:69
|vpiName:m_avalon.waitrequest
|vpiFullName:work@avalon_master.m_avalon.waitrequest
|vpiStmt:
\_assignment: , line:70
|vpiOpType:82
|vpiLhs:
\_ref_obj: (data_out), line:70
|vpiName:data_out
|vpiFullName:work@avalon_master.data_out
|vpiRhs:
\_ref_obj: (m_avalon.readdata), line:70
|vpiName:m_avalon.readdata
|vpiFullName:work@avalon_master.m_avalon.readdata
|vpiElseStmt:
\_assignment: , line:72
|vpiOpType:82
|vpiLhs:
\_ref_obj: (data_out), line:72
|vpiName:data_out
|vpiFullName:work@avalon_master.data_out
|vpiRhs:
\_constant: , line:72
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiProcess:
\_always: , line:75
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:75
|vpiCondition:
\_operation: , line:75
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:75
|vpiName:clk
|vpiFullName:work@avalon_master.clk
|vpiStmt:
\_begin: , line:75
|vpiFullName:work@avalon_master
|vpiStmt:
\_if_else: , line:76
|vpiCondition:
\_ref_obj: (rst), line:76
|vpiName:rst
|vpiFullName:work@avalon_master.rst
|vpiStmt:
\_assignment: , line:77
|vpiOpType:82
|vpiLhs:
\_ref_obj: (m_avalon.read), line:77
|vpiName:m_avalon.read
|vpiFullName:work@avalon_master.m_avalon.read
|vpiRhs:
\_constant: , line:77
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiElseStmt:
\_if_else: , line:78
|vpiCondition:
\_operation: , line:78
|vpiOpType:28
|vpiOperand:
\_ref_obj: (ls.new_request), line:78
|vpiName:ls.new_request
|vpiFullName:work@avalon_master.ls.new_request
|vpiOperand:
\_ref_obj: (ls_inputs.load), line:78
|vpiName:ls_inputs.load
|vpiFullName:work@avalon_master.ls_inputs.load
|vpiStmt:
\_assignment: , line:79
|vpiOpType:82
|vpiLhs:
\_ref_obj: (m_avalon.read), line:79
|vpiName:m_avalon.read
|vpiFullName:work@avalon_master.m_avalon.read
|vpiRhs:
\_constant: , line:79
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiElseStmt:
\_if_stmt: , line:80
|vpiCondition:
\_operation: , line:80
|vpiOpType:4
|vpiOperand:
\_ref_obj: (m_avalon.waitrequest), line:80
|vpiName:m_avalon.waitrequest
|vpiFullName:work@avalon_master.m_avalon.waitrequest
|vpiStmt:
\_assignment: , line:81
|vpiOpType:82
|vpiLhs:
\_ref_obj: (m_avalon.read), line:81
|vpiName:m_avalon.read
|vpiFullName:work@avalon_master.m_avalon.read
|vpiRhs:
\_constant: , line:81
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiProcess:
\_always: , line:84
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:84
|vpiCondition:
\_operation: , line:84
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:84
|vpiName:clk
|vpiFullName:work@avalon_master.clk
|vpiStmt:
\_begin: , line:84
|vpiFullName:work@avalon_master
|vpiStmt:
\_if_else: , line:85
|vpiCondition:
\_ref_obj: (rst), line:85
|vpiName:rst
|vpiFullName:work@avalon_master.rst
|vpiStmt:
\_assignment: , line:86
|vpiOpType:82
|vpiLhs:
\_ref_obj: (m_avalon.write), line:86
|vpiName:m_avalon.write
|vpiFullName:work@avalon_master.m_avalon.write
|vpiRhs:
\_constant: , line:86
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiElseStmt:
\_if_else: , line:87
|vpiCondition:
\_operation: , line:87
|vpiOpType:28
|vpiOperand:
\_ref_obj: (ls.new_request), line:87
|vpiName:ls.new_request
|vpiFullName:work@avalon_master.ls.new_request
|vpiOperand:
\_ref_obj: (ls_inputs.store), line:87
|vpiName:ls_inputs.store
|vpiFullName:work@avalon_master.ls_inputs.store
|vpiStmt:
\_assignment: , line:88
|vpiOpType:82
|vpiLhs:
\_ref_obj: (m_avalon.write), line:88
|vpiName:m_avalon.write
|vpiFullName:work@avalon_master.m_avalon.write
|vpiRhs:
\_constant: , line:88
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiElseStmt:
\_if_stmt: , line:89
|vpiCondition:
\_operation: , line:89
|vpiOpType:4
|vpiOperand:
\_ref_obj: (m_avalon.waitrequest), line:89
|vpiName:m_avalon.waitrequest
|vpiFullName:work@avalon_master.m_avalon.waitrequest
|vpiStmt:
\_assignment: , line:90
|vpiOpType:82
|vpiLhs:
\_ref_obj: (m_avalon.write), line:90
|vpiName:m_avalon.write
|vpiFullName:work@avalon_master.m_avalon.write
|vpiRhs:
\_constant: , line:90
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiPort:
\_port: (clk), line:29
|vpiName:clk
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (clk), line:29
|vpiName:clk
|vpiFullName:work@avalon_master.clk
|vpiNetType:36
|vpiPort:
\_port: (rst), line:30
|vpiName:rst
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (rst), line:30
|vpiName:rst
|vpiFullName:work@avalon_master.rst
|vpiNetType:36
|vpiPort:
\_port: (m_avalon), line:32
|vpiName:m_avalon
|vpiDirection:5
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_modport: (master)
|vpiPort:
\_port: (data_out), line:33
|vpiName:data_out
|vpiDirection:2
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (data_out), line:33
|vpiName:data_out
|vpiFullName:work@avalon_master.data_out
|vpiNetType:36
|vpiPort:
\_port: (ls_inputs), line:35
|vpiName:ls_inputs
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (ls_inputs), line:35
|vpiName:ls_inputs
|vpiFullName:work@avalon_master.ls_inputs
|vpiPort:
\_port: (ls), line:36
|vpiName:ls
|vpiDirection:5
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_modport: (sub_unit)
|vpiNet:
\_logic_net: (clk), line:29
|vpiNet:
\_logic_net: (rst), line:30
|vpiNet:
\_logic_net: (data_out), line:33
|vpiNet:
\_logic_net: (ls_inputs), line:35
|vpiNet:
\_logic_net: (m_avalon), line:32
|vpiName:m_avalon
|vpiFullName:work@avalon_master.m_avalon
|vpiNet:
\_logic_net: (ls), line:36
|vpiName:ls
|vpiFullName:work@avalon_master.ls
|vpiTypedef:
\_struct_typespec: (alu_inputs_t), line:301
|vpiTypedef:
\_enum_typespec: (alu_logic_op_t), line:84
|vpiTypedef:
\_enum_typespec: (alu_op_t), line:91
|vpiTypedef:
\_enum_typespec: (alu_rs1_op_t), line:97
|vpiTypedef:
\_enum_typespec: (alu_rs2_op_t), line:104
|vpiTypedef:
\_struct_typespec: (amo_alu_inputs_t), line:356
|vpiTypedef:
\_struct_typespec: (amo_details_t), line:362
|vpiTypedef:
\_enum_typespec: (amo_t), line:354
|vpiTypedef:
\_struct_typespec: (branch_inputs_t), line:313
|vpiTypedef:
\_logic_typespec: (branch_predictor_metadata_t), line:32
|vpiTypedef:
\_struct_typespec: (branch_results_t), line:330
|vpiTypedef:
\_enum_typespec: (bus_type_t), line:86
|vpiTypedef:
\_struct_typespec: (csr_inputs_t), line:396
|vpiTypedef:
\_enum_typespec: (csr_op_t), line:218
|vpiTypedef:
\_enum_typespec: (csr_t), line:201
|vpiTypedef:
\_struct_typespec: (data_access_shared_inputs_t), line:427
|vpiTypedef:
\_struct_typespec: (div_inputs_t), line:389
|vpiTypedef:
\_enum_typespec: (div_type), line:66
|vpiTypedef:
\_enum_typespec: (exception_code_t), line:245
|vpiTypedef:
\_struct_typespec: (exception_packet_t), line:263
|vpiTypedef:
\_struct_typespec: (fetch_buffer_packet_t), line:276
|vpiTypedef:
\_enum_typespec: (fifo_type_t), line:440
|vpiTypedef:
\_enum_typespec: (fn3_arith_t), line:76
|vpiTypedef:
\_enum_typespec: (fn3_branch_t), line:126
|vpiTypedef:
\_enum_typespec: (fn3_csr_t), line:212
|vpiTypedef:
\_enum_typespec: (fn3_ls_t), line:115
|vpiTypedef:
\_enum_typespec: (fn3_mul_div_t), line:138
|vpiTypedef:
\_struct_typespec: (gc_inputs_t), line:404
|vpiTypedef:
\_struct_typespec: (inflight_instruction_packet), line:271
|vpiTypedef:
\_logic_typespec: (instruction_id_t), line:30
|vpiTypedef:
\_enum_typespec: (interrupt_code_t), line:261
|vpiTypedef:
\_struct_typespec: (load_store_inputs_t), line:369
|vpiTypedef:
\_struct_typespec: (mul_inputs_t), line:383
|vpiTypedef:
\_enum_typespec: (opcodes_t), line:48
|vpiTypedef:
\_enum_typespec: (opcodes_trimmed_t), line:65
|vpiTypedef:
\_struct_typespec: (simulation_named_regfile), line:476
|vpiTypedef:
\_struct_typespec: (taiga_trace_events_t), line:442
|vpiTypedef:
\_struct_typespec: (to_l1_arbiter_packet), line:418
|vpiTypedef:
\_struct_typespec: (trace_outputs_t), line:469
|vpiTypedef:
\_logic_typespec: (unit_id_t), line:31
|vpiTypedef:
\_struct_typespec: (unit_writeback_t), line:295
|vpiTypedef:
\_enum_typespec: (vm_t), line:223
|uhdmallModules:
\_module: work@axi_master, file:third_party/cores/taiga/core/axi_master.sv, line:27, parent:work@div_unit_core_wrapper
|vpiDefName:work@axi_master
|vpiFullName:work@axi_master
|vpiProcess:
\_always: , line:48
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:48
|vpiCondition:
\_operation: , line:48
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:48
|vpiName:clk
|vpiFullName:work@axi_master.clk
|vpiStmt:
\_begin: , line:48
|vpiFullName:work@axi_master
|vpiStmt:
\_if_stmt: , line:49
|vpiCondition:
\_ref_obj: (ls.new_request), line:49
|vpiName:ls.new_request
|vpiFullName:work@axi_master.ls.new_request
|vpiStmt:
\_begin: , line:49
|vpiFullName:work@axi_master
|vpiStmt:
\_assignment: , line:50
|vpiOpType:82
|vpiLhs:
\_ref_obj: (m_axi.araddr), line:50
|vpiName:m_axi.araddr
|vpiFullName:work@axi_master.m_axi.araddr
|vpiRhs:
\_ref_obj: (ls_inputs.addr), line:50
|vpiName:ls_inputs.addr
|vpiFullName:work@axi_master.ls_inputs.addr
|vpiStmt:
\_assignment: , line:51
|vpiOpType:82
|vpiLhs:
\_ref_obj: (m_axi.arsize), line:51
|vpiName:m_axi.arsize
|vpiFullName:work@axi_master.m_axi.arsize
|vpiRhs:
\_ref_obj: (size), line:51
|vpiName:size
|vpiFullName:work@axi_master.size
|vpiStmt:
\_assignment: , line:52
|vpiOpType:82
|vpiLhs:
\_ref_obj: (m_axi.awsize), line:52
|vpiName:m_axi.awsize
|vpiFullName:work@axi_master.m_axi.awsize
|vpiRhs:
\_ref_obj: (size), line:52
|vpiName:size
|vpiFullName:work@axi_master.size
|vpiStmt:
\_assignment: , line:53
|vpiOpType:82
|vpiLhs:
\_ref_obj: (m_axi.awaddr), line:53
|vpiName:m_axi.awaddr
|vpiFullName:work@axi_master.m_axi.awaddr
|vpiRhs:
\_ref_obj: (ls_inputs.addr), line:53
|vpiName:ls_inputs.addr
|vpiFullName:work@axi_master.ls_inputs.addr
|vpiStmt:
\_assignment: , line:54
|vpiOpType:82
|vpiLhs:
\_ref_obj: (m_axi.wdata), line:54
|vpiName:m_axi.wdata
|vpiFullName:work@axi_master.m_axi.wdata
|vpiRhs:
\_ref_obj: (ls_inputs.data_in), line:54
|vpiName:ls_inputs.data_in
|vpiFullName:work@axi_master.ls_inputs.data_in
|vpiStmt:
\_assignment: , line:55
|vpiOpType:82
|vpiLhs:
\_ref_obj: (m_axi.wstrb), line:55
|vpiName:m_axi.wstrb
|vpiFullName:work@axi_master.m_axi.wstrb
|vpiRhs:
\_ref_obj: (ls_inputs.be), line:55
|vpiName:ls_inputs.be
|vpiFullName:work@axi_master.ls_inputs.be
|vpiProcess:
\_always: , line:64
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:64
|vpiCondition:
\_operation: , line:64
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:64
|vpiName:clk
|vpiFullName:work@axi_master.clk
|vpiStmt:
\_begin: , line:64
|vpiFullName:work@axi_master
|vpiStmt:
\_if_else: , line:65
|vpiCondition:
\_ref_obj: (rst), line:65
|vpiName:rst
|vpiFullName:work@axi_master.rst
|vpiStmt:
\_assignment: , line:66
|vpiOpType:82
|vpiLhs:
\_ref_obj: (ready), line:66
|vpiName:ready
|vpiFullName:work@axi_master.ready
|vpiRhs:
\_constant: , line:66
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiElseStmt:
\_if_else: , line:67
|vpiCondition:
\_ref_obj: (ls.new_request), line:67
|vpiName:ls.new_request
|vpiFullName:work@axi_master.ls.new_request
|vpiStmt:
\_assignment: , line:68
|vpiOpType:82
|vpiLhs:
\_ref_obj: (ready), line:68
|vpiName:ready
|vpiFullName:work@axi_master.ready
|vpiRhs:
\_constant: , line:68
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiElseStmt:
\_if_stmt: , line:69
|vpiCondition:
\_operation: , line:69
|vpiOpType:29
|vpiOperand:
\_ref_obj: (m_axi.rvalid), line:69
|vpiName:m_axi.rvalid
|vpiFullName:work@axi_master.m_axi.rvalid
|vpiOperand:
\_ref_obj: (m_axi.bvalid), line:69
|vpiName:m_axi.bvalid
|vpiFullName:work@axi_master.m_axi.bvalid
|vpiStmt:
\_assignment: , line:70
|vpiOpType:82
|vpiLhs:
\_ref_obj: (ready), line:70
|vpiName:ready
|vpiFullName:work@axi_master.ready
|vpiRhs:
\_constant: , line:70
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiProcess:
\_always: , line:74
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:74
|vpiCondition:
\_operation: , line:74
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:74
|vpiName:clk
|vpiFullName:work@axi_master.clk
|vpiStmt:
\_begin: , line:74
|vpiFullName:work@axi_master
|vpiStmt:
\_if_else: , line:75
|vpiCondition:
\_ref_obj: (rst), line:75
|vpiName:rst
|vpiFullName:work@axi_master.rst
|vpiStmt:
\_assignment: , line:76
|vpiOpType:82
|vpiLhs:
\_ref_obj: (ls.data_valid), line:76
|vpiName:ls.data_valid
|vpiFullName:work@axi_master.ls.data_valid
|vpiRhs:
\_constant: , line:76
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiElseStmt:
\_assignment: , line:78
|vpiOpType:82
|vpiLhs:
\_ref_obj: (ls.data_valid), line:78
|vpiName:ls.data_valid
|vpiFullName:work@axi_master.ls.data_valid
|vpiRhs:
\_ref_obj: (m_axi.rvalid), line:78
|vpiName:m_axi.rvalid
|vpiFullName:work@axi_master.m_axi.rvalid
|vpiProcess:
\_always: , line:82
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:82
|vpiCondition:
\_operation: , line:82
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:82
|vpiName:clk
|vpiFullName:work@axi_master.clk
|vpiStmt:
\_begin: , line:82
|vpiFullName:work@axi_master
|vpiStmt:
\_if_else: , line:83
|vpiCondition:
\_ref_obj: (rst), line:83
|vpiName:rst
|vpiFullName:work@axi_master.rst
|vpiStmt:
\_assignment: , line:84
|vpiOpType:82
|vpiLhs:
\_ref_obj: (m_axi.arvalid), line:84
|vpiName:m_axi.arvalid
|vpiFullName:work@axi_master.m_axi.arvalid
|vpiRhs:
\_constant: , line:84
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiElseStmt:
\_if_else: , line:85
|vpiCondition:
\_operation: , line:85
|vpiOpType:28
|vpiOperand:
\_ref_obj: (ls.new_request), line:85
|vpiName:ls.new_request
|vpiFullName:work@axi_master.ls.new_request
|vpiOperand:
\_ref_obj: (ls_inputs.load), line:85
|vpiName:ls_inputs.load
|vpiFullName:work@axi_master.ls_inputs.load
|vpiStmt:
\_assignment: , line:86
|vpiOpType:82
|vpiLhs:
\_ref_obj: (m_axi.arvalid), line:86
|vpiName:m_axi.arvalid
|vpiFullName:work@axi_master.m_axi.arvalid
|vpiRhs:
\_constant: , line:86
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiElseStmt:
\_if_stmt: , line:87
|vpiCondition:
\_ref_obj: (m_axi.arready), line:87
|vpiName:m_axi.arready
|vpiFullName:work@axi_master.m_axi.arready
|vpiStmt:
\_assignment: , line:88
|vpiOpType:82
|vpiLhs:
\_ref_obj: (m_axi.arvalid), line:88
|vpiName:m_axi.arvalid
|vpiFullName:work@axi_master.m_axi.arvalid
|vpiRhs:
\_constant: , line:88
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiProcess:
\_always: , line:91
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:91
|vpiCondition:
\_operation: , line:91
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:91
|vpiName:clk
|vpiFullName:work@axi_master.clk
|vpiStmt:
\_begin: , line:91
|vpiFullName:work@axi_master
|vpiStmt:
\_if_stmt: , line:92
|vpiCondition:
\_ref_obj: (m_axi.rvalid), line:92
|vpiName:m_axi.rvalid
|vpiFullName:work@axi_master.m_axi.rvalid
|vpiStmt:
\_assignment: , line:93
|vpiOpType:82
|vpiLhs:
\_ref_obj: (data_out), line:93
|vpiName:data_out
|vpiFullName:work@axi_master.data_out
|vpiRhs:
\_ref_obj: (m_axi.rdata), line:93
|vpiName:m_axi.rdata
|vpiFullName:work@axi_master.m_axi.rdata
|vpiProcess:
\_always: , line:97
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:97
|vpiCondition:
\_operation: , line:97
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:97
|vpiName:clk
|vpiFullName:work@axi_master.clk
|vpiStmt:
\_begin: , line:97
|vpiFullName:work@axi_master
|vpiStmt:
\_if_else: , line:98
|vpiCondition:
\_ref_obj: (rst), line:98
|vpiName:rst
|vpiFullName:work@axi_master.rst
|vpiStmt:
\_assignment: , line:99
|vpiOpType:82
|vpiLhs:
\_ref_obj: (m_axi.awvalid), line:99
|vpiName:m_axi.awvalid
|vpiFullName:work@axi_master.m_axi.awvalid
|vpiRhs:
\_constant: , line:99
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiElseStmt:
\_if_else: , line:100
|vpiCondition:
\_operation: , line:100
|vpiOpType:28
|vpiOperand:
\_ref_obj: (ls.new_request), line:100
|vpiName:ls.new_request
|vpiFullName:work@axi_master.ls.new_request
|vpiOperand:
\_ref_obj: (ls_inputs.store), line:100
|vpiName:ls_inputs.store
|vpiFullName:work@axi_master.ls_inputs.store
|vpiStmt:
\_assignment: , line:101
|vpiOpType:82
|vpiLhs:
\_ref_obj: (m_axi.awvalid), line:101
|vpiName:m_axi.awvalid
|vpiFullName:work@axi_master.m_axi.awvalid
|vpiRhs:
\_constant: , line:101
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiElseStmt:
\_if_stmt: , line:102
|vpiCondition:
\_ref_obj: (m_axi.awready), line:102
|vpiName:m_axi.awready
|vpiFullName:work@axi_master.m_axi.awready
|vpiStmt:
\_assignment: , line:103
|vpiOpType:82
|vpiLhs:
\_ref_obj: (m_axi.awvalid), line:103
|vpiName:m_axi.awvalid
|vpiFullName:work@axi_master.m_axi.awvalid
|vpiRhs:
\_constant: , line:103
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiProcess:
\_always: , line:106
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:106
|vpiCondition:
\_operation: , line:106
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:106
|vpiName:clk
|vpiFullName:work@axi_master.clk
|vpiStmt:
\_begin: , line:106
|vpiFullName:work@axi_master
|vpiStmt:
\_if_else: , line:107
|vpiCondition:
\_ref_obj: (rst), line:107
|vpiName:rst
|vpiFullName:work@axi_master.rst
|vpiStmt:
\_assignment: , line:108
|vpiOpType:82
|vpiLhs:
\_ref_obj: (m_axi.wvalid), line:108
|vpiName:m_axi.wvalid
|vpiFullName:work@axi_master.m_axi.wvalid
|vpiRhs:
\_constant: , line:108
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiElseStmt:
\_if_else: , line:109
|vpiCondition:
\_operation: , line:109
|vpiOpType:28
|vpiOperand:
\_ref_obj: (ls.new_request), line:109
|vpiName:ls.new_request
|vpiFullName:work@axi_master.ls.new_request
|vpiOperand:
\_ref_obj: (ls_inputs.store), line:109
|vpiName:ls_inputs.store
|vpiFullName:work@axi_master.ls_inputs.store
|vpiStmt:
\_assignment: , line:110
|vpiOpType:82
|vpiLhs:
\_ref_obj: (m_axi.wvalid), line:110
|vpiName:m_axi.wvalid
|vpiFullName:work@axi_master.m_axi.wvalid
|vpiRhs:
\_constant: , line:110
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiElseStmt:
\_if_stmt: , line:111
|vpiCondition:
\_ref_obj: (m_axi.wready), line:111
|vpiName:m_axi.wready
|vpiFullName:work@axi_master.m_axi.wready
|vpiStmt:
\_assignment: , line:112
|vpiOpType:82
|vpiLhs:
\_ref_obj: (m_axi.wvalid), line:112
|vpiName:m_axi.wvalid
|vpiFullName:work@axi_master.m_axi.wvalid
|vpiRhs:
\_constant: , line:112
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiPort:
\_port: (clk), line:29
|vpiName:clk
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (clk), line:29
|vpiName:clk
|vpiFullName:work@axi_master.clk
|vpiNetType:36
|vpiPort:
\_port: (rst), line:30
|vpiName:rst
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (rst), line:30
|vpiName:rst
|vpiFullName:work@axi_master.rst
|vpiNetType:36
|vpiPort:
\_port: (m_axi), line:32
|vpiName:m_axi
|vpiDirection:5
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_modport: (master)
|vpiPort:
\_port: (size), line:33
|vpiName:size
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (size), line:33
|vpiName:size
|vpiFullName:work@axi_master.size
|vpiNetType:36
|vpiPort:
\_port: (data_out), line:34
|vpiName:data_out
|vpiDirection:2
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (data_out), line:34
|vpiName:data_out
|vpiFullName:work@axi_master.data_out
|vpiNetType:36
|vpiPort:
\_port: (ls_inputs), line:36
|vpiName:ls_inputs
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (ls_inputs), line:36
|vpiName:ls_inputs
|vpiFullName:work@axi_master.ls_inputs
|vpiPort:
\_port: (ls), line:37
|vpiName:ls
|vpiDirection:5
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_modport: (sub_unit)
|vpiContAssign:
\_cont_assign: , line:44
|vpiRhs:
\_constant: , line:44
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiLhs:
\_ref_obj: (m_axi.arlen), line:44
|vpiName:m_axi.arlen
|vpiFullName:work@axi_master.m_axi.arlen
|vpiContAssign:
\_cont_assign: , line:45
|vpiRhs:
\_constant: , line:45
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiLhs:
\_ref_obj: (m_axi.arburst), line:45
|vpiName:m_axi.arburst
|vpiFullName:work@axi_master.m_axi.arburst
|vpiContAssign:
\_cont_assign: , line:46
|vpiRhs:
\_constant: , line:46
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiLhs:
\_ref_obj: (m_axi.rready), line:46
|vpiName:m_axi.rready
|vpiFullName:work@axi_master.m_axi.rready
|vpiContAssign:
\_cont_assign: , line:60
|vpiRhs:
\_constant: , line:60
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiLhs:
\_ref_obj: (m_axi.awlen), line:60
|vpiName:m_axi.awlen
|vpiFullName:work@axi_master.m_axi.awlen
|vpiContAssign:
\_cont_assign: , line:61
|vpiRhs:
\_constant: , line:61
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiLhs:
\_ref_obj: (m_axi.awburst), line:61
|vpiName:m_axi.awburst
|vpiFullName:work@axi_master.m_axi.awburst
|vpiContAssign:
\_cont_assign: , line:62
|vpiRhs:
\_constant: , line:62
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiLhs:
\_ref_obj: (m_axi.bready), line:62
|vpiName:m_axi.bready
|vpiFullName:work@axi_master.m_axi.bready
|vpiContAssign:
\_cont_assign: , line:72
|vpiRhs:
\_ref_obj: (ready), line:72
|vpiName:ready
|vpiFullName:work@axi_master.ready
|vpiLhs:
\_ref_obj: (ls.ready), line:72
|vpiName:ls.ready
|vpiFullName:work@axi_master.ls.ready
|vpiContAssign:
\_cont_assign: , line:114
|vpiRhs:
\_ref_obj: (m_axi.wvalid), line:114
|vpiName:m_axi.wvalid
|vpiFullName:work@axi_master.m_axi.wvalid
|vpiLhs:
\_ref_obj: (m_axi.wlast), line:114
|vpiName:m_axi.wlast
|vpiFullName:work@axi_master.m_axi.wlast
|vpiNet:
\_logic_net: (clk), line:29
|vpiNet:
\_logic_net: (rst), line:30
|vpiNet:
\_logic_net: (size), line:33
|vpiNet:
\_logic_net: (data_out), line:34
|vpiNet:
\_logic_net: (ls_inputs), line:36
|vpiNet:
\_logic_net: (ready), line:40
|vpiName:ready
|vpiFullName:work@axi_master.ready
|vpiNetType:36
|vpiNet:
\_logic_net: (m_axi), line:32
|vpiName:m_axi
|vpiFullName:work@axi_master.m_axi
|vpiNet:
\_logic_net: (ls), line:37
|vpiName:ls
|vpiFullName:work@axi_master.ls
|vpiTypedef:
\_struct_typespec: (alu_inputs_t), line:301
|vpiTypedef:
\_enum_typespec: (alu_logic_op_t), line:84
|vpiTypedef:
\_enum_typespec: (alu_op_t), line:91
|vpiTypedef:
\_enum_typespec: (alu_rs1_op_t), line:97
|vpiTypedef:
\_enum_typespec: (alu_rs2_op_t), line:104
|vpiTypedef:
\_struct_typespec: (amo_alu_inputs_t), line:356
|vpiTypedef:
\_struct_typespec: (amo_details_t), line:362
|vpiTypedef:
\_enum_typespec: (amo_t), line:354
|vpiTypedef:
\_struct_typespec: (branch_inputs_t), line:313
|vpiTypedef:
\_logic_typespec: (branch_predictor_metadata_t), line:32
|vpiTypedef:
\_struct_typespec: (branch_results_t), line:330
|vpiTypedef:
\_enum_typespec: (bus_type_t), line:86
|vpiTypedef:
\_struct_typespec: (csr_inputs_t), line:396
|vpiTypedef:
\_enum_typespec: (csr_op_t), line:218
|vpiTypedef:
\_enum_typespec: (csr_t), line:201
|vpiTypedef:
\_struct_typespec: (data_access_shared_inputs_t), line:427
|vpiTypedef:
\_struct_typespec: (div_inputs_t), line:389
|vpiTypedef:
\_enum_typespec: (div_type), line:66
|vpiTypedef:
\_enum_typespec: (exception_code_t), line:245
|vpiTypedef:
\_struct_typespec: (exception_packet_t), line:263
|vpiTypedef:
\_struct_typespec: (fetch_buffer_packet_t), line:276
|vpiTypedef:
\_enum_typespec: (fifo_type_t), line:440
|vpiTypedef:
\_enum_typespec: (fn3_arith_t), line:76
|vpiTypedef:
\_enum_typespec: (fn3_branch_t), line:126
|vpiTypedef:
\_enum_typespec: (fn3_csr_t), line:212
|vpiTypedef:
\_enum_typespec: (fn3_ls_t), line:115
|vpiTypedef:
\_enum_typespec: (fn3_mul_div_t), line:138
|vpiTypedef:
\_struct_typespec: (gc_inputs_t), line:404
|vpiTypedef:
\_struct_typespec: (inflight_instruction_packet), line:271
|vpiTypedef:
\_logic_typespec: (instruction_id_t), line:30
|vpiTypedef:
\_enum_typespec: (interrupt_code_t), line:261
|vpiTypedef:
\_struct_typespec: (load_store_inputs_t), line:369
|vpiTypedef:
\_struct_typespec: (mul_inputs_t), line:383
|vpiTypedef:
\_enum_typespec: (opcodes_t), line:48
|vpiTypedef:
\_enum_typespec: (opcodes_trimmed_t), line:65
|vpiTypedef:
\_struct_typespec: (simulation_named_regfile), line:476
|vpiTypedef:
\_struct_typespec: (taiga_trace_events_t), line:442
|vpiTypedef:
\_struct_typespec: (to_l1_arbiter_packet), line:418
|vpiTypedef:
\_struct_typespec: (trace_outputs_t), line:469
|vpiTypedef:
\_logic_typespec: (unit_id_t), line:31
|vpiTypedef:
\_struct_typespec: (unit_writeback_t), line:295
|vpiTypedef:
\_enum_typespec: (vm_t), line:223
|uhdmallModules:
\_module: work@axi_to_arb, file:third_party/cores/taiga/core/axi_to_arb.sv, line:28, parent:work@div_unit_core_wrapper
|vpiDefName:work@axi_to_arb
|vpiFullName:work@axi_to_arb
|vpiProcess:
\_always: , line:109
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:109
|vpiCondition:
\_operation: , line:109
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:109
|vpiName:clk
|vpiFullName:work@axi_to_arb.clk
|vpiStmt:
\_begin: , line:109
|vpiFullName:work@axi_to_arb
|vpiStmt:
\_if_else: , line:110
|vpiCondition:
\_ref_obj: (rst), line:110
|vpiName:rst
|vpiFullName:work@axi_to_arb.rst
|vpiStmt:
\_assignment: , line:111
|vpiOpType:82
|vpiLhs:
\_ref_obj: (read_modify_write_in_progress), line:111
|vpiName:read_modify_write_in_progress
|vpiFullName:work@axi_to_arb.read_modify_write_in_progress
|vpiRhs:
\_constant: , line:111
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiElseStmt:
\_if_else: , line:112
|vpiCondition:
\_ref_obj: (axi_bvalid), line:112
|vpiName:axi_bvalid
|vpiFullName:work@axi_to_arb.axi_bvalid
|vpiStmt:
\_assignment: , line:113
|vpiOpType:82
|vpiLhs:
\_ref_obj: (read_modify_write_in_progress), line:113
|vpiName:read_modify_write_in_progress
|vpiFullName:work@axi_to_arb.read_modify_write_in_progress
|vpiRhs:
\_constant: , line:113
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiElseStmt:
\_if_stmt: , line:114
|vpiCondition:
\_operation: , line:114
|vpiOpType:28
|vpiOperand:
\_ref_obj: (l2.request_valid), line:114
|vpiName:l2.request_valid
|vpiFullName:work@axi_to_arb.l2.request_valid
|vpiOperand:
\_ref_obj: (read_modify_write), line:114
|vpiName:read_modify_write
|vpiFullName:work@axi_to_arb.read_modify_write
|vpiStmt:
\_assignment: , line:115
|vpiOpType:82
|vpiLhs:
\_ref_obj: (read_modify_write_in_progress), line:115
|vpiName:read_modify_write_in_progress
|vpiFullName:work@axi_to_arb.read_modify_write_in_progress
|vpiRhs:
\_constant: , line:115
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiProcess:
\_always: , line:118
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:118
|vpiCondition:
\_operation: , line:118
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:118
|vpiName:clk
|vpiFullName:work@axi_to_arb.clk
|vpiStmt:
\_begin: , line:118
|vpiFullName:work@axi_to_arb
|vpiStmt:
\_if_else: , line:119
|vpiCondition:
\_ref_obj: (rst), line:119
|vpiName:rst
|vpiFullName:work@axi_to_arb.rst
|vpiStmt:
\_assignment: , line:120
|vpiOpType:82
|vpiLhs:
\_ref_obj: (address_phase_complete), line:120
|vpiName:address_phase_complete
|vpiFullName:work@axi_to_arb.address_phase_complete
|vpiRhs:
\_constant: , line:120
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiElseStmt:
\_if_else: , line:121
|vpiCondition:
\_ref_obj: (pop), line:121
|vpiName:pop
|vpiFullName:work@axi_to_arb.pop
|vpiStmt:
\_assignment: , line:122
|vpiOpType:82
|vpiLhs:
\_ref_obj: (address_phase_complete), line:122
|vpiName:address_phase_complete
|vpiFullName:work@axi_to_arb.address_phase_complete
|vpiRhs:
\_constant: , line:122
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiElseStmt:
\_if_stmt: , line:123
|vpiCondition:
\_operation: , line:123
|vpiOpType:28
|vpiOperand:
\_ref_obj: (axi_arvalid), line:123
|vpiName:axi_arvalid
|vpiFullName:work@axi_to_arb.axi_arvalid
|vpiOperand:
\_ref_obj: (axi_arready), line:123
|vpiName:axi_arready
|vpiFullName:work@axi_to_arb.axi_arready
|vpiStmt:
\_assignment: , line:124
|vpiOpType:82
|vpiLhs:
\_ref_obj: (address_phase_complete), line:124
|vpiName:address_phase_complete
|vpiFullName:work@axi_to_arb.address_phase_complete
|vpiRhs:
\_constant: , line:124
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiProcess:
\_always: , line:129
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:129
|vpiCondition:
\_operation: , line:129
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:129
|vpiName:clk
|vpiFullName:work@axi_to_arb.clk
|vpiStmt:
\_begin: , line:129
|vpiFullName:work@axi_to_arb
|vpiStmt:
\_if_else: , line:130
|vpiCondition:
\_ref_obj: (rst), line:130
|vpiName:rst
|vpiFullName:work@axi_to_arb.rst
|vpiStmt:
\_assignment: , line:131
|vpiOpType:82
|vpiLhs:
\_ref_obj: (read_count), line:131
|vpiName:read_count
|vpiFullName:work@axi_to_arb.read_count
|vpiRhs:
\_constant: , line:131
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiElseStmt:
\_if_stmt: , line:132
|vpiCondition:
\_operation: , line:132
|vpiOpType:26
|vpiOperand:
\_ref_obj: (axi_rvalid), line:132
|vpiName:axi_rvalid
|vpiFullName:work@axi_to_arb.axi_rvalid
|vpiOperand:
\_operation: , line:132
|vpiOpType:14
|vpiOperand:
\_ref_obj: (axi_rid), line:132
|vpiName:axi_rid
|vpiFullName:work@axi_to_arb.axi_rid
|vpiOperand:
\_ref_obj: (l2.id), line:132
|vpiName:l2.id
|vpiFullName:work@axi_to_arb.l2.id
|vpiStmt:
\_assignment: , line:133
|vpiOpType:82
|vpiLhs:
\_ref_obj: (read_count), line:133
|vpiName:read_count
|vpiFullName:work@axi_to_arb.read_count
|vpiRhs:
\_operation: , line:133
|vpiOpType:24
|vpiOperand:
\_ref_obj: (read_count), line:133
|vpiName:read_count
|vpiFullName:work@axi_to_arb.read_count
|vpiOperand:
\_constant: , line:133
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiProcess:
\_always: , line:144
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:144
|vpiCondition:
\_operation: , line:144
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:144
|vpiName:clk
|vpiFullName:work@axi_to_arb.clk
|vpiStmt:
\_begin: , line:144
|vpiFullName:work@axi_to_arb
|vpiStmt:
\_if_stmt: , line:145
|vpiCondition:
\_operation: , line:145
|vpiOpType:26
|vpiOperand:
\_ref_obj: (axi_rvalid), line:145
|vpiName:axi_rvalid
|vpiFullName:work@axi_to_arb.axi_rvalid
|vpiOperand:
\_operation: , line:145
|vpiOpType:14
|vpiOperand:
\_ref_obj: (read_count), line:145
|vpiName:read_count
|vpiFullName:work@axi_to_arb.read_count
|vpiOperand:
\_ref_obj: (l2.addr), line:145
|vpiName:l2.addr
|vpiFullName:work@axi_to_arb.l2.addr
|vpiStmt:
\_assignment: , line:146
|vpiOpType:82
|vpiLhs:
\_ref_obj: (amo_result_r), line:146
|vpiName:amo_result_r
|vpiFullName:work@axi_to_arb.amo_result_r
|vpiRhs:
\_ref_obj: (amo_result), line:146
|vpiName:amo_result
|vpiFullName:work@axi_to_arb.amo_result
|vpiProcess:
\_always: , line:149
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:149
|vpiCondition:
\_operation: , line:149
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:149
|vpiName:clk
|vpiFullName:work@axi_to_arb.clk
|vpiStmt:
\_begin: , line:149
|vpiFullName:work@axi_to_arb
|vpiStmt:
\_if_else: , line:150
|vpiCondition:
\_ref_obj: (rst), line:150
|vpiName:rst
|vpiFullName:work@axi_to_arb.rst
|vpiStmt:
\_assignment: , line:151
|vpiOpType:82
|vpiLhs:
\_ref_obj: (amo_write_ready), line:151
|vpiName:amo_write_ready
|vpiFullName:work@axi_to_arb.amo_write_ready
|vpiRhs:
\_constant: , line:151
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiElseStmt:
\_if_else: , line:152
|vpiCondition:
\_ref_obj: (pop), line:152
|vpiName:pop
|vpiFullName:work@axi_to_arb.pop
|vpiStmt:
\_assignment: , line:153
|vpiOpType:82
|vpiLhs:
\_ref_obj: (amo_write_ready), line:153
|vpiName:amo_write_ready
|vpiFullName:work@axi_to_arb.amo_write_ready
|vpiRhs:
\_constant: , line:153
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiElseStmt:
\_if_stmt: , line:154
|vpiCondition:
\_operation: , line:154
|vpiOpType:26
|vpiOperand:
\_operation: , line:154
|vpiOpType:26
|vpiOperand:
\_ref_obj: (l2.is_amo), line:154
|vpiName:l2.is_amo
|vpiFullName:work@axi_to_arb.l2.is_amo
|vpiOperand:
\_ref_obj: (axi_rvalid), line:154
|vpiName:axi_rvalid
|vpiFullName:work@axi_to_arb.axi_rvalid
|vpiOperand:
\_operation: , line:154
|vpiOpType:14
|vpiOperand:
\_ref_obj: (read_count), line:154
|vpiName:read_count
|vpiFullName:work@axi_to_arb.read_count
|vpiOperand:
\_ref_obj: (l2.addr), line:154
|vpiName:l2.addr
|vpiFullName:work@axi_to_arb.l2.addr
|vpiStmt:
\_assignment: , line:155
|vpiOpType:82
|vpiLhs:
\_ref_obj: (amo_write_ready), line:155
|vpiName:amo_write_ready
|vpiFullName:work@axi_to_arb.amo_write_ready
|vpiRhs:
\_constant: , line:155
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiProcess:
\_always: , line:194
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:194
|vpiCondition:
\_operation: , line:194
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:194
|vpiName:clk
|vpiFullName:work@axi_to_arb.clk
|vpiStmt:
\_begin: , line:194
|vpiFullName:work@axi_to_arb
|vpiStmt:
\_if_else: , line:195
|vpiCondition:
\_ref_obj: (rst), line:195
|vpiName:rst
|vpiFullName:work@axi_to_arb.rst
|vpiStmt:
\_assignment: , line:196
|vpiOpType:82
|vpiLhs:
\_ref_obj: (axi_arvalid), line:196
|vpiName:axi_arvalid
|vpiFullName:work@axi_to_arb.axi_arvalid
|vpiRhs:
\_constant: , line:196
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiElseStmt:
\_if_else: , line:197
|vpiCondition:
\_operation: , line:197
|vpiOpType:28
|vpiOperand:
\_ref_obj: (axi_arvalid), line:197
|vpiName:axi_arvalid
|vpiFullName:work@axi_to_arb.axi_arvalid
|vpiOperand:
\_ref_obj: (axi_arready), line:197
|vpiName:axi_arready
|vpiFullName:work@axi_to_arb.axi_arready
|vpiStmt:
\_assignment: , line:198
|vpiOpType:82
|vpiLhs:
\_ref_obj: (axi_arvalid), line:198
|vpiName:axi_arvalid
|vpiFullName:work@axi_to_arb.axi_arvalid
|vpiRhs:
\_constant: , line:198
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiElseStmt:
\_if_stmt: , line:199
|vpiCondition:
\_operation: , line:199
|vpiOpType:28
|vpiOperand:
\_operation: , line:199
|vpiOpType:28
|vpiOperand:
\_ref_obj: (l2.request_valid), line:199
|vpiName:l2.request_valid
|vpiFullName:work@axi_to_arb.l2.request_valid
|vpiOperand:
\_ref_obj: (l2.rnw), line:199
|vpiName:l2.rnw
|vpiFullName:work@axi_to_arb.l2.rnw
|vpiOperand:
\_operation: , line:199
|vpiOpType:4
|vpiOperand:
\_ref_obj: (address_phase_complete), line:199
|vpiName:address_phase_complete
|vpiFullName:work@axi_to_arb.address_phase_complete
|vpiStmt:
\_assignment: , line:200
|vpiOpType:82
|vpiLhs:
\_ref_obj: (axi_arvalid), line:200
|vpiName:axi_arvalid
|vpiFullName:work@axi_to_arb.axi_arvalid
|vpiRhs:
\_constant: , line:200
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiProcess:
\_always: , line:204
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:204
|vpiCondition:
\_operation: , line:204
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:204
|vpiName:clk
|vpiFullName:work@axi_to_arb.clk
|vpiStmt:
\_begin: , line:204
|vpiFullName:work@axi_to_arb
|vpiStmt:
\_if_else: , line:205
|vpiCondition:
\_ref_obj: (rst), line:205
|vpiName:rst
|vpiFullName:work@axi_to_arb.rst
|vpiStmt:
\_assignment: , line:206
|vpiOpType:82
|vpiLhs:
\_ref_obj: (axi_awvalid), line:206
|vpiName:axi_awvalid
|vpiFullName:work@axi_to_arb.axi_awvalid
|vpiRhs:
\_constant: , line:206
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiElseStmt:
\_if_else: , line:207
|vpiCondition:
\_operation: , line:207
|vpiOpType:28
|vpiOperand:
\_operation: , line:207
|vpiOpType:28
|vpiOperand:
\_operation: , line:207
|vpiOpType:28
|vpiOperand:
\_ref_obj: (l2.wr_data_valid), line:207
|vpiName:l2.wr_data_valid
|vpiFullName:work@axi_to_arb.l2.wr_data_valid
|vpiOperand:
\_ref_obj: (l2.request_valid), line:207
|vpiName:l2.request_valid
|vpiFullName:work@axi_to_arb.l2.request_valid
|vpiOperand:
\_operation: , line:207
|vpiOpType:29
|vpiOperand:
\_operation: , line:207
|vpiOpType:4
|vpiOperand:
\_ref_obj: (l2.rnw), line:207
|vpiName:l2.rnw
|vpiFullName:work@axi_to_arb.l2.rnw
|vpiOperand:
\_ref_obj: (amo_write_ready), line:207
|vpiName:amo_write_ready
|vpiFullName:work@axi_to_arb.amo_write_ready
|vpiOperand:
\_operation: , line:207
|vpiOpType:4
|vpiOperand:
\_ref_obj: (write_in_progress), line:207
|vpiName:write_in_progress
|vpiFullName:work@axi_to_arb.write_in_progress
|vpiStmt:
\_assignment: , line:208
|vpiOpType:82
|vpiLhs:
\_ref_obj: (axi_awvalid), line:208
|vpiName:axi_awvalid
|vpiFullName:work@axi_to_arb.axi_awvalid
|vpiRhs:
\_constant: , line:208
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiElseStmt:
\_if_stmt: , line:209
|vpiCondition:
\_ref_obj: (axi_awready), line:209
|vpiName:axi_awready
|vpiFullName:work@axi_to_arb.axi_awready
|vpiStmt:
\_assignment: , line:210
|vpiOpType:82
|vpiLhs:
\_ref_obj: (axi_awvalid), line:210
|vpiName:axi_awvalid
|vpiFullName:work@axi_to_arb.axi_awvalid
|vpiRhs:
\_constant: , line:210
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiProcess:
\_always: , line:213
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:213
|vpiCondition:
\_operation: , line:213
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:213
|vpiName:clk
|vpiFullName:work@axi_to_arb.clk
|vpiStmt:
\_begin: , line:213
|vpiFullName:work@axi_to_arb
|vpiStmt:
\_if_else: , line:214
|vpiCondition:
\_ref_obj: (rst), line:214
|vpiName:rst
|vpiFullName:work@axi_to_arb.rst
|vpiStmt:
\_assignment: , line:215
|vpiOpType:82
|vpiLhs:
\_ref_obj: (write_in_progress), line:215
|vpiName:write_in_progress
|vpiFullName:work@axi_to_arb.write_in_progress
|vpiRhs:
\_constant: , line:215
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiElseStmt:
\_if_else: , line:216
|vpiCondition:
\_ref_obj: (axi_bvalid), line:216
|vpiName:axi_bvalid
|vpiFullName:work@axi_to_arb.axi_bvalid
|vpiStmt:
\_assignment: , line:217
|vpiOpType:82
|vpiLhs:
\_ref_obj: (write_in_progress), line:217
|vpiName:write_in_progress
|vpiFullName:work@axi_to_arb.write_in_progress
|vpiRhs:
\_constant: , line:217
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiElseStmt:
\_if_stmt: , line:218
|vpiCondition:
\_operation: , line:218
|vpiOpType:28
|vpiOperand:
\_operation: , line:218
|vpiOpType:28
|vpiOperand:
\_ref_obj: (l2.wr_data_valid), line:218
|vpiName:l2.wr_data_valid
|vpiFullName:work@axi_to_arb.l2.wr_data_valid
|vpiOperand:
\_ref_obj: (l2.request_valid), line:218
|vpiName:l2.request_valid
|vpiFullName:work@axi_to_arb.l2.request_valid
|vpiOperand:
\_operation: , line:218
|vpiOpType:29
|vpiOperand:
\_operation: , line:218
|vpiOpType:4
|vpiOperand:
\_ref_obj: (l2.rnw), line:218
|vpiName:l2.rnw
|vpiFullName:work@axi_to_arb.l2.rnw
|vpiOperand:
\_ref_obj: (amo_write_ready), line:218
|vpiName:amo_write_ready
|vpiFullName:work@axi_to_arb.amo_write_ready
|vpiStmt:
\_assignment: , line:219
|vpiOpType:82
|vpiLhs:
\_ref_obj: (write_in_progress), line:219
|vpiName:write_in_progress
|vpiFullName:work@axi_to_arb.write_in_progress
|vpiRhs:
\_constant: , line:219
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiProcess:
\_always: , line:223
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:223
|vpiCondition:
\_operation: , line:223
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:223
|vpiName:clk
|vpiFullName:work@axi_to_arb.clk
|vpiStmt:
\_begin: , line:223
|vpiFullName:work@axi_to_arb
|vpiStmt:
\_if_else: , line:224
|vpiCondition:
\_ref_obj: (rst), line:224
|vpiName:rst
|vpiFullName:work@axi_to_arb.rst
|vpiStmt:
\_assignment: , line:225
|vpiOpType:82
|vpiLhs:
\_ref_obj: (write_burst_count), line:225
|vpiName:write_burst_count
|vpiFullName:work@axi_to_arb.write_burst_count
|vpiRhs:
\_constant: , line:225
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiElseStmt:
\_if_else: , line:226
|vpiCondition:
\_ref_obj: (axi_bvalid), line:226
|vpiName:axi_bvalid
|vpiFullName:work@axi_to_arb.axi_bvalid
|vpiStmt:
\_assignment: , line:227
|vpiOpType:82
|vpiLhs:
\_ref_obj: (write_burst_count), line:227
|vpiName:write_burst_count
|vpiFullName:work@axi_to_arb.write_burst_count
|vpiRhs:
\_constant: , line:227
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiElseStmt:
\_if_stmt: , line:228
|vpiCondition:
\_operation: , line:228
|vpiOpType:26
|vpiOperand:
\_operation: , line:228
|vpiOpType:26
|vpiOperand:
\_ref_obj: (axi_wvalid), line:228
|vpiName:axi_wvalid
|vpiFullName:work@axi_to_arb.axi_wvalid
|vpiOperand:
\_ref_obj: (axi_wready), line:228
|vpiName:axi_wready
|vpiFullName:work@axi_to_arb.axi_wready
|vpiOperand:
\_operation: , line:228
|vpiOpType:15
|vpiOperand:
\_ref_obj: (write_reference_burst_count), line:228
|vpiName:write_reference_burst_count
|vpiFullName:work@axi_to_arb.write_reference_burst_count
|vpiOperand:
\_ref_obj: (write_burst_count), line:228
|vpiName:write_burst_count
|vpiFullName:work@axi_to_arb.write_burst_count
|vpiStmt:
\_assignment: , line:229
|vpiOpType:82
|vpiLhs:
\_ref_obj: (write_burst_count), line:229
|vpiName:write_burst_count
|vpiFullName:work@axi_to_arb.write_burst_count
|vpiRhs:
\_operation: , line:229
|vpiOpType:24
|vpiOperand:
\_ref_obj: (write_burst_count), line:229
|vpiName:write_burst_count
|vpiFullName:work@axi_to_arb.write_burst_count
|vpiOperand:
\_constant: , line:229
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiProcess:
\_always: , line:232
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:232
|vpiCondition:
\_operation: , line:232
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:232
|vpiName:clk
|vpiFullName:work@axi_to_arb.clk
|vpiStmt:
\_begin: , line:232
|vpiFullName:work@axi_to_arb
|vpiStmt:
\_if_else: , line:233
|vpiCondition:
\_ref_obj: (rst), line:233
|vpiName:rst
|vpiFullName:work@axi_to_arb.rst
|vpiStmt:
\_assignment: , line:234
|vpiOpType:82
|vpiLhs:
\_ref_obj: (on_last_burst), line:234
|vpiName:on_last_burst
|vpiFullName:work@axi_to_arb.on_last_burst
|vpiRhs:
\_constant: , line:234
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiElseStmt:
\_if_else: , line:235
|vpiCondition:
\_ref_obj: (axi_bvalid), line:235
|vpiName:axi_bvalid
|vpiFullName:work@axi_to_arb.axi_bvalid
|vpiStmt:
\_assignment: , line:236
|vpiOpType:82
|vpiLhs:
\_ref_obj: (on_last_burst), line:236
|vpiName:on_last_burst
|vpiFullName:work@axi_to_arb.on_last_burst
|vpiRhs:
\_constant: , line:236
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiElseStmt:
\_if_stmt: , line:237
|vpiCondition:
\_operation: , line:237
|vpiOpType:27
|vpiOperand:
\_operation: , line:237
|vpiOpType:26
|vpiOperand:
\_operation: , line:237
|vpiOpType:4
|vpiOperand:
\_ref_obj: (write_in_progress), line:237
|vpiName:write_in_progress
|vpiFullName:work@axi_to_arb.write_in_progress
|vpiOperand:
\_operation: , line:237
|vpiOpType:14
|vpiOperand:
\_ref_obj: (write_reference_burst_count), line:237
|vpiName:write_reference_burst_count
|vpiFullName:work@axi_to_arb.write_reference_burst_count
|vpiOperand:
\_constant: , line:237
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiOperand:
\_operation: , line:237
|vpiOpType:26
|vpiOperand:
\_ref_obj: (write_in_progress), line:237
|vpiName:write_in_progress
|vpiFullName:work@axi_to_arb.write_in_progress
|vpiOperand:
\_operation: , line:237
|vpiOpType:14
|vpiOperand:
\_ref_obj: (write_reference_burst_count), line:237
|vpiName:write_reference_burst_count
|vpiFullName:work@axi_to_arb.write_reference_burst_count
|vpiOperand:
\_ref_obj: (write_burst_count), line:237
|vpiName:write_burst_count
|vpiFullName:work@axi_to_arb.write_burst_count
|vpiStmt:
\_assignment: , line:238
|vpiOpType:82
|vpiLhs:
\_ref_obj: (on_last_burst), line:238
|vpiName:on_last_burst
|vpiFullName:work@axi_to_arb.on_last_burst
|vpiRhs:
\_constant: , line:238
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiProcess:
\_always: , line:241
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:241
|vpiCondition:
\_operation: , line:241
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:241
|vpiName:clk
|vpiFullName:work@axi_to_arb.clk
|vpiStmt:
\_begin: , line:241
|vpiFullName:work@axi_to_arb
|vpiStmt:
\_if_else: , line:242
|vpiCondition:
\_ref_obj: (rst), line:242
|vpiName:rst
|vpiFullName:work@axi_to_arb.rst
|vpiStmt:
\_assignment: , line:243
|vpiOpType:82
|vpiLhs:
\_ref_obj: (write_transfer_complete), line:243
|vpiName:write_transfer_complete
|vpiFullName:work@axi_to_arb.write_transfer_complete
|vpiRhs:
\_constant: , line:243
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiElseStmt:
\_if_else: , line:244
|vpiCondition:
\_ref_obj: (axi_bvalid), line:244
|vpiName:axi_bvalid
|vpiFullName:work@axi_to_arb.axi_bvalid
|vpiStmt:
\_assignment: , line:245
|vpiOpType:82
|vpiLhs:
\_ref_obj: (write_transfer_complete), line:245
|vpiName:write_transfer_complete
|vpiFullName:work@axi_to_arb.write_transfer_complete
|vpiRhs:
\_constant: , line:245
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiElseStmt:
\_if_stmt: , line:246
|vpiCondition:
\_operation: , line:246
|vpiOpType:26
|vpiOperand:
\_ref_obj: (axi_wlast), line:246
|vpiName:axi_wlast
|vpiFullName:work@axi_to_arb.axi_wlast
|vpiOperand:
\_ref_obj: (axi_wready), line:246
|vpiName:axi_wready
|vpiFullName:work@axi_to_arb.axi_wready
|vpiStmt:
\_assignment: , line:247
|vpiOpType:82
|vpiLhs:
\_ref_obj: (write_transfer_complete), line:247
|vpiName:write_transfer_complete
|vpiFullName:work@axi_to_arb.write_transfer_complete
|vpiRhs:
\_constant: , line:247
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiPort:
\_port: (clk), line:30
|vpiName:clk
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (clk), line:30
|vpiName:clk
|vpiFullName:work@axi_to_arb.clk
|vpiNetType:36
|vpiPort:
\_port: (rst), line:31
|vpiName:rst
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (rst), line:31
|vpiName:rst
|vpiFullName:work@axi_to_arb.rst
|vpiNetType:36
|vpiPort:
\_port: (axi_arready), line:34
|vpiName:axi_arready
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (axi_arready), line:34
|vpiName:axi_arready
|vpiFullName:work@axi_to_arb.axi_arready
|vpiNetType:36
|vpiPort:
\_port: (axi_arvalid), line:35
|vpiName:axi_arvalid
|vpiDirection:2
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (axi_arvalid), line:35
|vpiName:axi_arvalid
|vpiFullName:work@axi_to_arb.axi_arvalid
|vpiNetType:36
|vpiPort:
\_port: (axi_araddr), line:36
|vpiName:axi_araddr
|vpiDirection:2
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (axi_araddr), line:36
|vpiName:axi_araddr
|vpiFullName:work@axi_to_arb.axi_araddr
|vpiNetType:36
|vpiPort:
\_port: (axi_arlen), line:37
|vpiName:axi_arlen
|vpiDirection:2
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (axi_arlen), line:37
|vpiName:axi_arlen
|vpiFullName:work@axi_to_arb.axi_arlen
|vpiNetType:36
|vpiPort:
\_port: (axi_arsize), line:38
|vpiName:axi_arsize
|vpiDirection:2
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (axi_arsize), line:38
|vpiName:axi_arsize
|vpiFullName:work@axi_to_arb.axi_arsize
|vpiNetType:36
|vpiPort:
\_port: (axi_arburst), line:39
|vpiName:axi_arburst
|vpiDirection:2
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (axi_arburst), line:39
|vpiName:axi_arburst
|vpiFullName:work@axi_to_arb.axi_arburst
|vpiNetType:36
|vpiPort:
\_port: (axi_arprot), line:40
|vpiName:axi_arprot
|vpiDirection:2
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (axi_arprot), line:40
|vpiName:axi_arprot
|vpiFullName:work@axi_to_arb.axi_arprot
|vpiNetType:36
|vpiPort:
\_port: (axi_arcache), line:41
|vpiName:axi_arcache
|vpiDirection:2
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (axi_arcache), line:41
|vpiName:axi_arcache
|vpiFullName:work@axi_to_arb.axi_arcache
|vpiNetType:36
|vpiPort:
\_port: (axi_arid), line:42
|vpiName:axi_arid
|vpiDirection:2
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (axi_arid), line:42
|vpiName:axi_arid
|vpiFullName:work@axi_to_arb.axi_arid
|vpiNetType:36
|vpiPort:
\_port: (axi_rready), line:45
|vpiName:axi_rready
|vpiDirection:2
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (axi_rready), line:45
|vpiName:axi_rready
|vpiFullName:work@axi_to_arb.axi_rready
|vpiNetType:36
|vpiPort:
\_port: (axi_rvalid), line:46
|vpiName:axi_rvalid
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (axi_rvalid), line:46
|vpiName:axi_rvalid
|vpiFullName:work@axi_to_arb.axi_rvalid
|vpiNetType:36
|vpiPort:
\_port: (axi_rdata), line:47
|vpiName:axi_rdata
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (axi_rdata), line:47
|vpiName:axi_rdata
|vpiFullName:work@axi_to_arb.axi_rdata
|vpiNetType:36
|vpiPort:
\_port: (axi_rresp), line:48
|vpiName:axi_rresp
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (axi_rresp), line:48
|vpiName:axi_rresp
|vpiFullName:work@axi_to_arb.axi_rresp
|vpiNetType:36
|vpiPort:
\_port: (axi_rlast), line:49
|vpiName:axi_rlast
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (axi_rlast), line:49
|vpiName:axi_rlast
|vpiFullName:work@axi_to_arb.axi_rlast
|vpiNetType:36
|vpiPort:
\_port: (axi_rid), line:50
|vpiName:axi_rid
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (axi_rid), line:50
|vpiName:axi_rid
|vpiFullName:work@axi_to_arb.axi_rid
|vpiNetType:36
|vpiPort:
\_port: (axi_awready), line:53
|vpiName:axi_awready
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (axi_awready), line:53
|vpiName:axi_awready
|vpiFullName:work@axi_to_arb.axi_awready
|vpiNetType:36
|vpiPort:
\_port: (axi_awvalid), line:54
|vpiName:axi_awvalid
|vpiDirection:2
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (axi_awvalid), line:54
|vpiName:axi_awvalid
|vpiFullName:work@axi_to_arb.axi_awvalid
|vpiNetType:36
|vpiPort:
\_port: (axi_awaddr), line:55
|vpiName:axi_awaddr
|vpiDirection:2
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (axi_awaddr), line:55
|vpiName:axi_awaddr
|vpiFullName:work@axi_to_arb.axi_awaddr
|vpiNetType:36
|vpiPort:
\_port: (axi_awlen), line:56
|vpiName:axi_awlen
|vpiDirection:2
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (axi_awlen), line:56
|vpiName:axi_awlen
|vpiFullName:work@axi_to_arb.axi_awlen
|vpiNetType:36
|vpiPort:
\_port: (axi_awsize), line:57
|vpiName:axi_awsize
|vpiDirection:2
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (axi_awsize), line:57
|vpiName:axi_awsize
|vpiFullName:work@axi_to_arb.axi_awsize
|vpiNetType:36
|vpiPort:
\_port: (axi_awburst), line:58
|vpiName:axi_awburst
|vpiDirection:2
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (axi_awburst), line:58
|vpiName:axi_awburst
|vpiFullName:work@axi_to_arb.axi_awburst
|vpiNetType:36
|vpiPort:
\_port: (axi_awcache), line:60
|vpiName:axi_awcache
|vpiDirection:2
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (axi_awcache), line:60
|vpiName:axi_awcache
|vpiFullName:work@axi_to_arb.axi_awcache
|vpiNetType:36
|vpiPort:
\_port: (axi_awprot), line:61
|vpiName:axi_awprot
|vpiDirection:2
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (axi_awprot), line:61
|vpiName:axi_awprot
|vpiFullName:work@axi_to_arb.axi_awprot
|vpiNetType:36
|vpiPort:
\_port: (axi_wready), line:64
|vpiName:axi_wready
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (axi_wready), line:64
|vpiName:axi_wready
|vpiFullName:work@axi_to_arb.axi_wready
|vpiNetType:36
|vpiPort:
\_port: (axi_wvalid), line:65
|vpiName:axi_wvalid
|vpiDirection:2
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (axi_wvalid), line:65
|vpiName:axi_wvalid
|vpiFullName:work@axi_to_arb.axi_wvalid
|vpiNetType:36
|vpiPort:
\_port: (axi_wdata), line:66
|vpiName:axi_wdata
|vpiDirection:2
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (axi_wdata), line:66
|vpiName:axi_wdata
|vpiFullName:work@axi_to_arb.axi_wdata
|vpiNetType:36
|vpiPort:
\_port: (axi_wstrb), line:67
|vpiName:axi_wstrb
|vpiDirection:2
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (axi_wstrb), line:67
|vpiName:axi_wstrb
|vpiFullName:work@axi_to_arb.axi_wstrb
|vpiNetType:36
|vpiPort:
\_port: (axi_wlast), line:68
|vpiName:axi_wlast
|vpiDirection:2
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (axi_wlast), line:68
|vpiName:axi_wlast
|vpiFullName:work@axi_to_arb.axi_wlast
|vpiNetType:36
|vpiPort:
\_port: (axi_bready), line:71
|vpiName:axi_bready
|vpiDirection:2
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (axi_bready), line:71
|vpiName:axi_bready
|vpiFullName:work@axi_to_arb.axi_bready
|vpiNetType:36
|vpiPort:
\_port: (axi_bvalid), line:72
|vpiName:axi_bvalid
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (axi_bvalid), line:72
|vpiName:axi_bvalid
|vpiFullName:work@axi_to_arb.axi_bvalid
|vpiNetType:36
|vpiPort:
\_port: (axi_bresp), line:73
|vpiName:axi_bresp
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (axi_bresp), line:73
|vpiName:axi_bresp
|vpiFullName:work@axi_to_arb.axi_bresp
|vpiNetType:36
|vpiPort:
\_port: (l2), line:78
|vpiName:l2
|vpiDirection:5
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_modport: (slave)
|vpiContAssign:
\_cont_assign: , line:107
|vpiRhs:
\_operation: , line:107
|vpiOpType:26
|vpiOperand:
\_ref_obj: (l2.is_amo), line:107
|vpiName:l2.is_amo
|vpiFullName:work@axi_to_arb.l2.is_amo
|vpiOperand:
\_operation: , line:107
|vpiOpType:27
|vpiOperand:
\_operation: , line:107
|vpiOpType:15
|vpiOperand:
\_ref_obj: (l2.amo_type_or_burst_size), line:107
|vpiName:l2.amo_type_or_burst_size
|vpiFullName:work@axi_to_arb.l2.amo_type_or_burst_size
|vpiOperand:
\_ref_obj: (AMO_LR), line:107
|vpiName:AMO_LR
|vpiFullName:work@axi_to_arb.AMO_LR
|vpiOperand:
\_operation: , line:107
|vpiOpType:15
|vpiOperand:
\_ref_obj: (l2.amo_type_or_burst_size), line:107
|vpiName:l2.amo_type_or_burst_size
|vpiFullName:work@axi_to_arb.l2.amo_type_or_burst_size
|vpiOperand:
\_ref_obj: (AMO_SC), line:107
|vpiName:AMO_SC
|vpiFullName:work@axi_to_arb.AMO_SC
|vpiLhs:
\_ref_obj: (read_modify_write), line:107
|vpiName:read_modify_write
|vpiFullName:work@axi_to_arb.read_modify_write
|vpiContAssign:
\_cont_assign: , line:136
|vpiRhs:
\_ref_obj: (axi_rdata), line:136
|vpiName:axi_rdata
|vpiFullName:work@axi_to_arb.axi_rdata
|vpiLhs:
\_ref_obj: (amo_alu_inputs.rs1_load), line:136
|vpiName:amo_alu_inputs.rs1_load
|vpiFullName:work@axi_to_arb.amo_alu_inputs.rs1_load
|vpiContAssign:
\_cont_assign: , line:137
|vpiRhs:
\_ref_obj: (l2.wr_data), line:137
|vpiName:l2.wr_data
|vpiFullName:work@axi_to_arb.l2.wr_data
|vpiLhs:
\_ref_obj: (amo_alu_inputs.rs2), line:137
|vpiName:amo_alu_inputs.rs2
|vpiFullName:work@axi_to_arb.amo_alu_inputs.rs2
|vpiContAssign:
\_cont_assign: , line:138
|vpiRhs:
\_ref_obj: (l2.amo_type_or_burst_size), line:138
|vpiName:l2.amo_type_or_burst_size
|vpiFullName:work@axi_to_arb.l2.amo_type_or_burst_size
|vpiLhs:
\_ref_obj: (amo_alu_inputs.op), line:138
|vpiName:amo_alu_inputs.op
|vpiFullName:work@axi_to_arb.amo_alu_inputs.op
|vpiContAssign:
\_cont_assign: , line:159
|vpiRhs:
\_ref_obj: (l2.amo_type_or_burst_size), line:159
|vpiName:l2.amo_type_or_burst_size
|vpiFullName:work@axi_to_arb.l2.amo_type_or_burst_size
|vpiLhs:
\_ref_obj: (burst_count), line:159
|vpiName:burst_count
|vpiFullName:work@axi_to_arb.burst_count
|vpiContAssign:
\_cont_assign: , line:162
|vpiRhs:
\_ref_obj: (burst_count), line:162
|vpiName:burst_count
|vpiFullName:work@axi_to_arb.burst_count
|vpiLhs:
\_ref_obj: (axi_arlen), line:162
|vpiName:axi_arlen
|vpiFullName:work@axi_to_arb.axi_arlen
|vpiContAssign:
\_cont_assign: , line:163
|vpiRhs:
\_constant: , line:163
|vpiConstType:3
|vpiDecompile:2'b01
|vpiSize:2
|BIN:2'b01
|vpiLhs:
\_ref_obj: (axi_arburst), line:163
|vpiName:axi_arburst
|vpiFullName:work@axi_to_arb.axi_arburst
|vpiContAssign:
\_cont_assign: , line:164
|vpiRhs:
\_constant: , line:164
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiLhs:
\_ref_obj: (axi_rready), line:164
|vpiName:axi_rready
|vpiFullName:work@axi_to_arb.axi_rready
|vpiContAssign:
\_cont_assign: , line:165
|vpiRhs:
\_constant: , line:165
|vpiConstType:3
|vpiDecompile:3'b010
|vpiSize:3
|BIN:3'b010
|vpiLhs:
\_ref_obj: (axi_arsize), line:165
|vpiName:axi_arsize
|vpiFullName:work@axi_to_arb.axi_arsize
|vpiContAssign:
\_cont_assign: , line:166
|vpiRhs:
\_constant: , line:166
|vpiConstType:3
|vpiDecompile:4'b0011
|vpiSize:4
|BIN:4'b0011
|vpiLhs:
\_ref_obj: (axi_arcache), line:166
|vpiName:axi_arcache
|vpiFullName:work@axi_to_arb.axi_arcache
|vpiContAssign:
\_cont_assign: , line:167
|vpiRhs:
\_constant: , line:167
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiLhs:
\_ref_obj: (axi_arport), line:167
|vpiName:axi_arport
|vpiFullName:work@axi_to_arb.axi_arport
|vpiContAssign:
\_cont_assign: , line:168
|vpiRhs:
\_ref_obj: (l2.id), line:168
|vpiName:l2.id
|vpiFullName:work@axi_to_arb.l2.id
|vpiLhs:
\_ref_obj: (axi_arid), line:168
|vpiName:axi_arid
|vpiFullName:work@axi_to_arb.axi_arid
|vpiContAssign:
\_cont_assign: , line:170
|vpiRhs:
\_operation: , line:170
|vpiOpType:33
|vpiOperand:
\_ref_obj: (l2.addr), line:170
|vpiName:l2.addr
|vpiOperand:
\_operation: , line:170
|vpiOpType:34
|vpiOperand:
\_ref_obj: (DCACHE_SUB_LINE_ADDR_W), line:170
|vpiName:DCACHE_SUB_LINE_ADDR_W
|vpiOperand:
\_operation:
|vpiOpType:33
|vpiOperand:
\_constant: , line:170
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiOperand:
\_constant: , line:170
|vpiConstType:3
|vpiDecompile:2'b00
|vpiSize:2
|BIN:2'b00
|vpiLhs:
\_ref_obj: (axi_araddr), line:170
|vpiName:axi_araddr
|vpiFullName:work@axi_to_arb.axi_araddr
|vpiContAssign:
\_cont_assign: , line:172
|vpiRhs:
\_operation: , line:172
|vpiOpType:32
|vpiOperand:
\_ref_obj: (read_modify_write), line:172
|vpiName:read_modify_write
|vpiFullName:work@axi_to_arb.read_modify_write
|vpiOperand:
\_constant: , line:172
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiOperand:
\_ref_obj: (burst_count), line:172
|vpiName:burst_count
|vpiFullName:work@axi_to_arb.burst_count
|vpiLhs:
\_ref_obj: (write_reference_burst_count), line:172
|vpiName:write_reference_burst_count
|vpiFullName:work@axi_to_arb.write_reference_burst_count
|vpiContAssign:
\_cont_assign: , line:175
|vpiRhs:
\_ref_obj: (write_reference_burst_count), line:175
|vpiName:write_reference_burst_count
|vpiFullName:work@axi_to_arb.write_reference_burst_count
|vpiLhs:
\_ref_obj: (axi_awlen), line:175
|vpiName:axi_awlen
|vpiFullName:work@axi_to_arb.axi_awlen
|vpiContAssign:
\_cont_assign: , line:176
|vpiRhs:
\_constant: , line:176
|vpiConstType:3
|vpiDecompile:2'b01
|vpiSize:2
|BIN:2'b01
|vpiLhs:
\_ref_obj: (axi_awburst), line:176
|vpiName:axi_awburst
|vpiFullName:work@axi_to_arb.axi_awburst
|vpiContAssign:
\_cont_assign: , line:177
|vpiRhs:
\_constant: , line:177
|vpiConstType:3
|vpiDecompile:3'b010
|vpiSize:3
|BIN:3'b010
|vpiLhs:
\_ref_obj: (axi_awsize), line:177
|vpiName:axi_awsize
|vpiFullName:work@axi_to_arb.axi_awsize
|vpiContAssign:
\_cont_assign: , line:178
|vpiRhs:
\_constant: , line:178
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiLhs:
\_ref_obj: (axi_bready), line:178
|vpiName:axi_bready
|vpiFullName:work@axi_to_arb.axi_bready
|vpiContAssign:
\_cont_assign: , line:179
|vpiRhs:
\_constant: , line:179
|vpiConstType:3
|vpiDecompile:4'b0011
|vpiSize:4
|BIN:4'b0011
|vpiLhs:
\_ref_obj: (axi_awcache), line:179
|vpiName:axi_awcache
|vpiFullName:work@axi_to_arb.axi_awcache
|vpiContAssign:
\_cont_assign: , line:180
|vpiRhs:
\_constant: , line:180
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiLhs:
\_ref_obj: (axi_awport), line:180
|vpiName:axi_awport
|vpiFullName:work@axi_to_arb.axi_awport
|vpiContAssign:
\_cont_assign: , line:182
|vpiRhs:
\_operation: , line:182
|vpiOpType:33
|vpiOperand:
\_ref_obj: (l2.addr), line:182
|vpiName:l2.addr
|vpiOperand:
\_constant: , line:182
|vpiConstType:3
|vpiDecompile:2'b00
|vpiSize:2
|BIN:2'b00
|vpiLhs:
\_ref_obj: (axi_awaddr), line:182
|vpiName:axi_awaddr
|vpiFullName:work@axi_to_arb.axi_awaddr
|vpiContAssign:
\_cont_assign: , line:184
|vpiRhs:
\_operation: , line:184
|vpiOpType:32
|vpiOperand:
\_ref_obj: (read_modify_write), line:184
|vpiName:read_modify_write
|vpiFullName:work@axi_to_arb.read_modify_write
|vpiOperand:
\_ref_obj: (amo_result_r), line:184
|vpiName:amo_result_r
|vpiFullName:work@axi_to_arb.amo_result_r
|vpiOperand:
\_ref_obj: (l2.wr_data), line:184
|vpiName:l2.wr_data
|vpiFullName:work@axi_to_arb.l2.wr_data
|vpiLhs:
\_ref_obj: (axi_wdata), line:184
|vpiName:axi_wdata
|vpiFullName:work@axi_to_arb.axi_wdata
|vpiContAssign:
\_cont_assign: , line:186
|vpiRhs:
\_operation: , line:186
|vpiOpType:32
|vpiOperand:
\_ref_obj: (read_modify_write), line:186
|vpiName:read_modify_write
|vpiFullName:work@axi_to_arb.read_modify_write
|vpiOperand:
\_constant: , line:186
|vpiConstType:3
|vpiDecompile:'b1
|vpiSize:1
|BIN:1
|vpiOperand:
\_ref_obj: (l2.be), line:186
|vpiName:l2.be
|vpiFullName:work@axi_to_arb.l2.be
|vpiLhs:
\_ref_obj: (axi_wstrb), line:186
|vpiName:axi_wstrb
|vpiFullName:work@axi_to_arb.axi_wstrb
|vpiContAssign:
\_cont_assign: , line:190
|vpiRhs:
\_operation: , line:190
|vpiOpType:29
|vpiOperand:
\_operation: , line:190
|vpiOpType:28
|vpiOperand:
\_operation: , line:190
|vpiOpType:28
|vpiOperand:
\_ref_obj: (axi_arvalid), line:190
|vpiName:axi_arvalid
|vpiFullName:work@axi_to_arb.axi_arvalid
|vpiOperand:
\_ref_obj: (axi_arready), line:190
|vpiName:axi_arready
|vpiFullName:work@axi_to_arb.axi_arready
|vpiOperand:
\_operation: , line:190
|vpiOpType:4
|vpiOperand:
\_ref_obj: (read_modify_write), line:190
|vpiName:read_modify_write
|vpiFullName:work@axi_to_arb.read_modify_write
|vpiOperand:
\_operation: , line:190
|vpiOpType:28
|vpiOperand:
\_ref_obj: (axi_awvalid), line:190
|vpiName:axi_awvalid
|vpiFullName:work@axi_to_arb.axi_awvalid
|vpiOperand:
\_ref_obj: (axi_awready), line:190
|vpiName:axi_awready
|vpiFullName:work@axi_to_arb.axi_awready
|vpiLhs:
\_ref_obj: (pop), line:190
|vpiName:pop
|vpiFullName:work@axi_to_arb.pop
|vpiContAssign:
\_cont_assign: , line:191
|vpiRhs:
\_ref_obj: (pop), line:191
|vpiName:pop
|vpiFullName:work@axi_to_arb.pop
|vpiLhs:
\_ref_obj: (l2.request_pop), line:191
|vpiName:l2.request_pop
|vpiFullName:work@axi_to_arb.l2.request_pop
|vpiContAssign:
\_cont_assign: , line:251
|vpiRhs:
\_operation: , line:251
|vpiOpType:28
|vpiOperand:
\_operation: , line:251
|vpiOpType:28
|vpiOperand:
\_ref_obj: (write_in_progress), line:251
|vpiName:write_in_progress
|vpiFullName:work@axi_to_arb.write_in_progress
|vpiOperand:
\_ref_obj: (l2.wr_data_valid), line:251
|vpiName:l2.wr_data_valid
|vpiFullName:work@axi_to_arb.l2.wr_data_valid
|vpiOperand:
\_operation: , line:251
|vpiOpType:4
|vpiOperand:
\_ref_obj: (write_transfer_complete), line:251
|vpiName:write_transfer_complete
|vpiFullName:work@axi_to_arb.write_transfer_complete
|vpiLhs:
\_ref_obj: (axi_wvalid), line:251
|vpiName:axi_wvalid
|vpiFullName:work@axi_to_arb.axi_wvalid
|vpiContAssign:
\_cont_assign: , line:252
|vpiRhs:
\_operation: , line:252
|vpiOpType:28
|vpiOperand:
\_operation: , line:252
|vpiOpType:28
|vpiOperand:
\_operation: , line:252
|vpiOpType:28
|vpiOperand:
\_ref_obj: (on_last_burst), line:252
|vpiName:on_last_burst
|vpiFullName:work@axi_to_arb.on_last_burst
|vpiOperand:
\_ref_obj: (write_in_progress), line:252
|vpiName:write_in_progress
|vpiFullName:work@axi_to_arb.write_in_progress
|vpiOperand:
\_ref_obj: (l2.wr_data_valid), line:252
|vpiName:l2.wr_data_valid
|vpiFullName:work@axi_to_arb.l2.wr_data_valid
|vpiOperand:
\_operation: , line:252
|vpiOpType:4
|vpiOperand:
\_ref_obj: (write_transfer_complete), line:252
|vpiName:write_transfer_complete
|vpiFullName:work@axi_to_arb.write_transfer_complete
|vpiLhs:
\_ref_obj: (axi_wlast), line:252
|vpiName:axi_wlast
|vpiFullName:work@axi_to_arb.axi_wlast
|vpiContAssign:
\_cont_assign: , line:254
|vpiRhs:
\_operation: , line:254
|vpiOpType:28
|vpiOperand:
\_operation: , line:254
|vpiOpType:28
|vpiOperand:
\_ref_obj: (write_in_progress), line:254
|vpiName:write_in_progress
|vpiFullName:work@axi_to_arb.write_in_progress
|vpiOperand:
\_ref_obj: (axi_wready), line:254
|vpiName:axi_wready
|vpiFullName:work@axi_to_arb.axi_wready
|vpiOperand:
\_operation: , line:254
|vpiOpType:4
|vpiOperand:
\_ref_obj: (write_transfer_complete), line:254
|vpiName:write_transfer_complete
|vpiFullName:work@axi_to_arb.write_transfer_complete
|vpiLhs:
\_ref_obj: (l2.wr_data_read), line:254
|vpiName:l2.wr_data_read
|vpiFullName:work@axi_to_arb.l2.wr_data_read
|vpiContAssign:
\_cont_assign: , line:258
|vpiRhs:
\_ref_obj: (axi_rdata), line:258
|vpiName:axi_rdata
|vpiFullName:work@axi_to_arb.axi_rdata
|vpiLhs:
\_ref_obj: (l2.rd_data), line:258
|vpiName:l2.rd_data
|vpiFullName:work@axi_to_arb.l2.rd_data
|vpiContAssign:
\_cont_assign: , line:259
|vpiRhs:
\_ref_obj: (axi_rid), line:259
|vpiName:axi_rid
|vpiFullName:work@axi_to_arb.axi_rid
|vpiLhs:
\_ref_obj: (l2.rd_id), line:259
|vpiName:l2.rd_id
|vpiFullName:work@axi_to_arb.l2.rd_id
|vpiContAssign:
\_cont_assign: , line:260
|vpiRhs:
\_ref_obj: (axi_rvalid), line:260
|vpiName:axi_rvalid
|vpiFullName:work@axi_to_arb.axi_rvalid
|vpiLhs:
\_ref_obj: (l2.rd_data_valid), line:260
|vpiName:l2.rd_data_valid
|vpiFullName:work@axi_to_arb.l2.rd_data_valid
|vpiNet:
\_logic_net: (clk), line:30
|vpiNet:
\_logic_net: (rst), line:31
|vpiNet:
\_logic_net: (axi_arready), line:34
|vpiNet:
\_logic_net: (axi_arvalid), line:35
|vpiNet:
\_logic_net: (axi_araddr), line:36
|vpiNet:
\_logic_net: (axi_arlen), line:37
|vpiNet:
\_logic_net: (axi_arsize), line:38
|vpiNet:
\_logic_net: (axi_arburst), line:39
|vpiNet:
\_logic_net: (axi_arprot), line:40
|vpiNet:
\_logic_net: (axi_arcache), line:41
|vpiNet:
\_logic_net: (axi_arid), line:42
|vpiNet:
\_logic_net: (axi_rready), line:45
|vpiNet:
\_logic_net: (axi_rvalid), line:46
|vpiNet:
\_logic_net: (axi_rdata), line:47
|vpiNet:
\_logic_net: (axi_rresp), line:48
|vpiNet:
\_logic_net: (axi_rlast), line:49
|vpiNet:
\_logic_net: (axi_rid), line:50
|vpiNet:
\_logic_net: (axi_awready), line:53
|vpiNet:
\_logic_net: (axi_awvalid), line:54
|vpiNet:
\_logic_net: (axi_awaddr), line:55
|vpiNet:
\_logic_net: (axi_awlen), line:56
|vpiNet:
\_logic_net: (axi_awsize), line:57
|vpiNet:
\_logic_net: (axi_awburst), line:58
|vpiNet:
\_logic_net: (axi_awcache), line:60
|vpiNet:
\_logic_net: (axi_awprot), line:61
|vpiNet:
\_logic_net: (axi_wready), line:64
|vpiNet:
\_logic_net: (axi_wvalid), line:65
|vpiNet:
\_logic_net: (axi_wdata), line:66
|vpiNet:
\_logic_net: (axi_wstrb), line:67
|vpiNet:
\_logic_net: (axi_wlast), line:68
|vpiNet:
\_logic_net: (axi_bready), line:71
|vpiNet:
\_logic_net: (axi_bvalid), line:72
|vpiNet:
\_logic_net: (axi_bresp), line:73
|vpiNet:
\_logic_net: (pop_request), line:82
|vpiName:pop_request
|vpiFullName:work@axi_to_arb.pop_request
|vpiNetType:36
|vpiNet:
\_logic_net: (read_modify_write), line:84
|vpiName:read_modify_write
|vpiFullName:work@axi_to_arb.read_modify_write
|vpiNetType:36
|vpiNet:
\_logic_net: (read_modify_write_in_progress), line:85
|vpiName:read_modify_write_in_progress
|vpiFullName:work@axi_to_arb.read_modify_write_in_progress
|vpiNetType:36
|vpiNet:
\_logic_net: (address_phase_complete), line:86
|vpiName:address_phase_complete
|vpiFullName:work@axi_to_arb.address_phase_complete
|vpiNetType:36
|vpiNet:
\_logic_net: (amo_result), line:87
|vpiName:amo_result
|vpiFullName:work@axi_to_arb.amo_result
|vpiNetType:36
|vpiNet:
\_logic_net: (amo_result_r), line:88
|vpiName:amo_result_r
|vpiFullName:work@axi_to_arb.amo_result_r
|vpiNetType:36
|vpiNet:
\_logic_net: (read_count), line:89
|vpiName:read_count
|vpiFullName:work@axi_to_arb.read_count
|vpiNetType:36
|vpiNet:
\_logic_net: (amo_write_ready), line:90
|vpiName:amo_write_ready
|vpiFullName:work@axi_to_arb.amo_write_ready
|vpiNetType:36
|vpiNet:
\_logic_net: (write_reference_burst_count), line:91
|vpiName:write_reference_burst_count
|vpiFullName:work@axi_to_arb.write_reference_burst_count
|vpiNetType:36
|vpiNet:
\_logic_net: (amo_alu_inputs), line:93
|vpiName:amo_alu_inputs
|vpiFullName:work@axi_to_arb.amo_alu_inputs
|vpiNet:
\_logic_net: (write_in_progress), line:96
|vpiName:write_in_progress
|vpiFullName:work@axi_to_arb.write_in_progress
|vpiNetType:36
|vpiNet:
\_logic_net: (write_transfer_complete), line:97
|vpiName:write_transfer_complete
|vpiFullName:work@axi_to_arb.write_transfer_complete
|vpiNetType:36
|vpiNet:
\_logic_net: (pop), line:99
|vpiName:pop
|vpiFullName:work@axi_to_arb.pop
|vpiNetType:36
|vpiNet:
\_logic_net: (write_burst_count), line:101
|vpiName:write_burst_count
|vpiFullName:work@axi_to_arb.write_burst_count
|vpiNetType:36
|vpiNet:
\_logic_net: (burst_count), line:102
|vpiName:burst_count
|vpiFullName:work@axi_to_arb.burst_count
|vpiNetType:36
|vpiNet:
\_logic_net: (burst_count_r), line:102
|vpiName:burst_count_r
|vpiFullName:work@axi_to_arb.burst_count_r
|vpiNetType:36
|vpiNet:
\_logic_net: (on_last_burst), line:103
|vpiName:on_last_burst
|vpiFullName:work@axi_to_arb.on_last_burst
|vpiNetType:36
|vpiNet:
\_logic_net: (l2), line:78
|vpiName:l2
|vpiFullName:work@axi_to_arb.l2
|vpiTypedef:
\_struct_typespec: (alu_inputs_t), line:301
|vpiTypedef:
\_enum_typespec: (alu_logic_op_t), line:84
|vpiTypedef:
\_enum_typespec: (alu_op_t), line:91
|vpiTypedef:
\_enum_typespec: (alu_rs1_op_t), line:97
|vpiTypedef:
\_enum_typespec: (alu_rs2_op_t), line:104
|vpiTypedef:
\_struct_typespec: (amo_alu_inputs_t), line:356
|vpiTypedef:
\_struct_typespec: (amo_details_t), line:362
|vpiTypedef:
\_enum_typespec: (amo_t), line:354
|vpiTypedef:
\_struct_typespec: (branch_inputs_t), line:313
|vpiTypedef:
\_logic_typespec: (branch_predictor_metadata_t), line:32
|vpiTypedef:
\_struct_typespec: (branch_results_t), line:330
|vpiTypedef:
\_enum_typespec: (bus_type_t), line:86
|vpiTypedef:
\_struct_typespec: (csr_inputs_t), line:396
|vpiTypedef:
\_enum_typespec: (csr_op_t), line:218
|vpiTypedef:
\_enum_typespec: (csr_t), line:201
|vpiTypedef:
\_struct_typespec: (data_access_shared_inputs_t), line:427
|vpiTypedef:
\_struct_typespec: (div_inputs_t), line:389
|vpiTypedef:
\_enum_typespec: (div_type), line:66
|vpiTypedef:
\_enum_typespec: (exception_code_t), line:245
|vpiTypedef:
\_struct_typespec: (exception_packet_t), line:263
|vpiTypedef:
\_struct_typespec: (fetch_buffer_packet_t), line:276
|vpiTypedef:
\_enum_typespec: (fifo_type_t), line:440
|vpiTypedef:
\_enum_typespec: (fn3_arith_t), line:76
|vpiTypedef:
\_enum_typespec: (fn3_branch_t), line:126
|vpiTypedef:
\_enum_typespec: (fn3_csr_t), line:212
|vpiTypedef:
\_enum_typespec: (fn3_ls_t), line:115
|vpiTypedef:
\_enum_typespec: (fn3_mul_div_t), line:138
|vpiTypedef:
\_struct_typespec: (gc_inputs_t), line:404
|vpiTypedef:
\_struct_typespec: (inflight_instruction_packet), line:271
|vpiTypedef:
\_logic_typespec: (instruction_id_t), line:30
|vpiTypedef:
\_enum_typespec: (interrupt_code_t), line:261
|vpiTypedef:
\_struct_typespec: (l2_data_attributes_t), line:68
|vpiTypedef:
\_struct_typespec: (l2_mem_request_t), line:58
|vpiTypedef:
\_struct_typespec: (l2_mem_return_data_t), line:75
|vpiTypedef:
\_struct_typespec: (l2_request_t), line:49
|vpiTypedef:
\_struct_typespec: (l2_return_data_t), line:81
|vpiTypedef:
\_struct_typespec: (load_store_inputs_t), line:369
|vpiTypedef:
\_struct_typespec: (mul_inputs_t), line:383
|vpiTypedef:
\_enum_typespec: (opcodes_t), line:48
|vpiTypedef:
\_enum_typespec: (opcodes_trimmed_t), line:65
|vpiTypedef:
\_struct_typespec: (simulation_named_regfile), line:476
|vpiTypedef:
\_struct_typespec: (taiga_trace_events_t), line:442
|vpiTypedef:
\_struct_typespec: (to_l1_arbiter_packet), line:418
|vpiTypedef:
\_struct_typespec: (trace_outputs_t), line:469
|vpiTypedef:
\_logic_typespec: (unit_id_t), line:31
|vpiTypedef:
\_struct_typespec: (unit_writeback_t), line:295
|vpiTypedef:
\_enum_typespec: (vm_t), line:223
|uhdmallModules:
\_module: work@barrel_shifter, file:third_party/cores/taiga/core/barrel_shifter.sv, line:26, parent:work@div_unit_core_wrapper
|vpiDefName:work@barrel_shifter
|vpiFullName:work@barrel_shifter
|vpiProcess:
\_always: , line:38
|vpiAlwaysType:2
|vpiStmt:
\_begin: , line:38
|vpiFullName:work@barrel_shifter
|vpiStmt:
\_foreach_stmt: , line:39
|vpiFullName:work@barrel_shifter
|vpiVariables:
\_chandle_var: (shifter_input), line:39
|vpiName:shifter_input
|vpiFullName:work@barrel_shifter.shifter_input
|vpiLoopVars:
\_chandle_var: (i), line:39
|vpiName:i
|vpiFullName:work@barrel_shifter.i
|vpiStmt:
\_assignment: , line:40
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_bit_select: (preshifted_input), line:40
|vpiName:preshifted_input
|vpiFullName:work@barrel_shifter.preshifted_input
|vpiIndex:
\_ref_obj: (i), line:40
|vpiName:i
|vpiRhs:
\_bit_select: (shifter_input), line:40
|vpiName:shifter_input
|vpiFullName:work@barrel_shifter.shifter_input
|vpiIndex:
\_operation: , line:40
|vpiOpType:11
|vpiOperand:
\_constant: , line:40
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiOperand:
\_ref_obj: (i), line:40
|vpiName:i
|vpiProcess:
\_always: , line:43
|vpiAlwaysType:2
|vpiStmt:
\_begin: , line:43
|vpiFullName:work@barrel_shifter
|vpiStmt:
\_case_stmt: , line:44
|vpiCaseType:1
|vpiCondition:
\_operation: , line:44
|vpiOpType:33
|vpiOperand:
\_ref_obj: (lshift), line:44
|vpiName:lshift
|vpiOperand:
\_bit_select: (shift_amount), line:44
|vpiName:shift_amount
|vpiIndex:
\_constant: , line:44
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiCaseItem:
\_case_item: , line:45
|vpiExpr:
\_constant: , line:45
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiStmt:
\_assignment: , line:45
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (shiftx1), line:45
|vpiName:shiftx1
|vpiFullName:work@barrel_shifter.shiftx1
|vpiRhs:
\_part_select: , line:45, parent:shifter_input
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (shifter_input)
|vpiLeftRange:
\_constant: , line:45
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:45
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiCaseItem:
\_case_item: , line:46
|vpiExpr:
\_constant: , line:46
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiStmt:
\_assignment: , line:46
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (shiftx1), line:46
|vpiName:shiftx1
|vpiFullName:work@barrel_shifter.shiftx1
|vpiRhs:
\_operation: , line:46
|vpiOpType:33
|vpiOperand:
\_operation: , line:46
|vpiOpType:34
|vpiOperand:
\_constant: , line:46
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiOperand:
\_operation:
|vpiOpType:33
|vpiOperand:
\_ref_obj: (arith), line:46
|vpiName:arith
|vpiOperand:
\_part_select: , line:46, parent:shifter_input
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (shifter_input)
|vpiLeftRange:
\_constant: , line:46
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:46
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiCaseItem:
\_case_item: , line:47
|vpiExpr:
\_constant: , line:47
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiStmt:
\_assignment: , line:47
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (shiftx1), line:47
|vpiName:shiftx1
|vpiFullName:work@barrel_shifter.shiftx1
|vpiRhs:
\_part_select: , line:47, parent:preshifted_input
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (preshifted_input)
|vpiLeftRange:
\_constant: , line:47
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:47
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiCaseItem:
\_case_item: , line:48
|vpiExpr:
\_constant: , line:48
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiStmt:
\_assignment: , line:48
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (shiftx1), line:48
|vpiName:shiftx1
|vpiFullName:work@barrel_shifter.shiftx1
|vpiRhs:
\_operation: , line:48
|vpiOpType:33
|vpiOperand:
\_operation: , line:48
|vpiOpType:34
|vpiOperand:
\_constant: , line:48
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiOperand:
\_operation:
|vpiOpType:33
|vpiOperand:
\_ref_obj: (arith), line:48
|vpiName:arith
|vpiOperand:
\_part_select: , line:48, parent:preshifted_input
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (preshifted_input)
|vpiLeftRange:
\_constant: , line:48
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:48
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiProcess:
\_always: , line:52
|vpiAlwaysType:2
|vpiStmt:
\_begin: , line:52
|vpiFullName:work@barrel_shifter
|vpiStmt:
\_case_stmt: , line:53
|vpiCaseType:1
|vpiCondition:
\_part_select: , line:53, parent:shift_amount
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (shift_amount)
|vpiLeftRange:
\_constant: , line:53
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiRightRange:
\_constant: , line:53
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiCaseItem:
\_case_item: , line:54
|vpiExpr:
\_constant: , line:54
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiStmt:
\_assignment: , line:54
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (shiftx2), line:54
|vpiName:shiftx2
|vpiFullName:work@barrel_shifter.shiftx2
|vpiRhs:
\_part_select: , line:54, parent:shiftx1
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (shiftx1)
|vpiLeftRange:
\_constant: , line:54
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:54
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiCaseItem:
\_case_item: , line:55
|vpiExpr:
\_constant: , line:55
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiStmt:
\_assignment: , line:55
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (shiftx2), line:55
|vpiName:shiftx2
|vpiFullName:work@barrel_shifter.shiftx2
|vpiRhs:
\_operation: , line:55
|vpiOpType:33
|vpiOperand:
\_operation: , line:55
|vpiOpType:34
|vpiOperand:
\_constant: , line:55
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiOperand:
\_operation:
|vpiOpType:33
|vpiOperand:
\_ref_obj: (arith), line:55
|vpiName:arith
|vpiOperand:
\_part_select: , line:55, parent:shiftx1
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (shiftx1)
|vpiLeftRange:
\_constant: , line:55
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:55
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiCaseItem:
\_case_item: , line:56
|vpiExpr:
\_constant: , line:56
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiStmt:
\_assignment: , line:56
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (shiftx2), line:56
|vpiName:shiftx2
|vpiFullName:work@barrel_shifter.shiftx2
|vpiRhs:
\_operation: , line:56
|vpiOpType:33
|vpiOperand:
\_operation: , line:56
|vpiOpType:34
|vpiOperand:
\_constant: , line:56
|vpiConstType:7
|vpiDecompile:4
|vpiSize:32
|INT:4
|vpiOperand:
\_operation:
|vpiOpType:33
|vpiOperand:
\_ref_obj: (arith), line:56
|vpiName:arith
|vpiOperand:
\_part_select: , line:56, parent:shiftx1
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (shiftx1)
|vpiLeftRange:
\_constant: , line:56
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:56
|vpiConstType:7
|vpiDecompile:4
|vpiSize:32
|INT:4
|vpiCaseItem:
\_case_item: , line:57
|vpiExpr:
\_constant: , line:57
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiStmt:
\_assignment: , line:57
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (shiftx2), line:57
|vpiName:shiftx2
|vpiFullName:work@barrel_shifter.shiftx2
|vpiRhs:
\_operation: , line:57
|vpiOpType:33
|vpiOperand:
\_operation: , line:57
|vpiOpType:34
|vpiOperand:
\_constant: , line:57
|vpiConstType:7
|vpiDecompile:6
|vpiSize:32
|INT:6
|vpiOperand:
\_operation:
|vpiOpType:33
|vpiOperand:
\_ref_obj: (arith), line:57
|vpiName:arith
|vpiOperand:
\_part_select: , line:57, parent:shiftx1
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (shiftx1)
|vpiLeftRange:
\_constant: , line:57
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:57
|vpiConstType:7
|vpiDecompile:6
|vpiSize:32
|INT:6
|vpiProcess:
\_always: , line:61
|vpiAlwaysType:2
|vpiStmt:
\_begin: , line:61
|vpiFullName:work@barrel_shifter
|vpiStmt:
\_case_stmt: , line:62
|vpiCaseType:1
|vpiCondition:
\_part_select: , line:62, parent:shift_amount
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (shift_amount)
|vpiLeftRange:
\_constant: , line:62
|vpiConstType:7
|vpiDecompile:4
|vpiSize:32
|INT:4
|vpiRightRange:
\_constant: , line:62
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiCaseItem:
\_case_item: , line:63
|vpiExpr:
\_constant: , line:63
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiStmt:
\_assignment: , line:63
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (shiftx8), line:63
|vpiName:shiftx8
|vpiFullName:work@barrel_shifter.shiftx8
|vpiRhs:
\_part_select: , line:63, parent:shiftx2
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (shiftx2)
|vpiLeftRange:
\_constant: , line:63
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:63
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiCaseItem:
\_case_item: , line:64
|vpiExpr:
\_constant: , line:64
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiStmt:
\_assignment: , line:64
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (shiftx8), line:64
|vpiName:shiftx8
|vpiFullName:work@barrel_shifter.shiftx8
|vpiRhs:
\_operation: , line:64
|vpiOpType:33
|vpiOperand:
\_operation: , line:64
|vpiOpType:34
|vpiOperand:
\_constant: , line:64
|vpiConstType:7
|vpiDecompile:8
|vpiSize:32
|INT:8
|vpiOperand:
\_operation:
|vpiOpType:33
|vpiOperand:
\_ref_obj: (arith), line:64
|vpiName:arith
|vpiOperand:
\_part_select: , line:64, parent:shiftx2
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (shiftx2)
|vpiLeftRange:
\_constant: , line:64
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:64
|vpiConstType:7
|vpiDecompile:8
|vpiSize:32
|INT:8
|vpiCaseItem:
\_case_item: , line:65
|vpiExpr:
\_constant: , line:65
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiStmt:
\_assignment: , line:65
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (shiftx8), line:65
|vpiName:shiftx8
|vpiFullName:work@barrel_shifter.shiftx8
|vpiRhs:
\_operation: , line:65
|vpiOpType:33
|vpiOperand:
\_operation: , line:65
|vpiOpType:34
|vpiOperand:
\_constant: , line:65
|vpiConstType:7
|vpiDecompile:16
|vpiSize:32
|INT:16
|vpiOperand:
\_operation:
|vpiOpType:33
|vpiOperand:
\_ref_obj: (arith), line:65
|vpiName:arith
|vpiOperand:
\_part_select: , line:65, parent:shiftx2
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (shiftx2)
|vpiLeftRange:
\_constant: , line:65
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:65
|vpiConstType:7
|vpiDecompile:16
|vpiSize:32
|INT:16
|vpiCaseItem:
\_case_item: , line:66
|vpiExpr:
\_constant: , line:66
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiStmt:
\_assignment: , line:66
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (shiftx8), line:66
|vpiName:shiftx8
|vpiFullName:work@barrel_shifter.shiftx8
|vpiRhs:
\_operation: , line:66
|vpiOpType:33
|vpiOperand:
\_operation: , line:66
|vpiOpType:34
|vpiOperand:
\_constant: , line:66
|vpiConstType:7
|vpiDecompile:24
|vpiSize:32
|INT:24
|vpiOperand:
\_operation:
|vpiOpType:33
|vpiOperand:
\_ref_obj: (arith), line:66
|vpiName:arith
|vpiOperand:
\_part_select: , line:66, parent:shiftx2
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (shiftx2)
|vpiLeftRange:
\_constant: , line:66
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:66
|vpiConstType:7
|vpiDecompile:24
|vpiSize:32
|INT:24
|vpiProcess:
\_always: , line:71
|vpiAlwaysType:2
|vpiStmt:
\_begin: , line:71
|vpiFullName:work@barrel_shifter
|vpiStmt:
\_foreach_stmt: , line:72
|vpiFullName:work@barrel_shifter
|vpiVariables:
\_chandle_var: (shifter_input), line:72
|vpiName:shifter_input
|vpiFullName:work@barrel_shifter.shifter_input
|vpiLoopVars:
\_chandle_var: (i), line:72
|vpiName:i
|vpiFullName:work@barrel_shifter.i
|vpiStmt:
\_assignment: , line:73
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_bit_select: (shifted_resultl), line:73
|vpiName:shifted_resultl
|vpiFullName:work@barrel_shifter.shifted_resultl
|vpiIndex:
\_ref_obj: (i), line:73
|vpiName:i
|vpiRhs:
\_bit_select: (shiftx8), line:73
|vpiName:shiftx8
|vpiFullName:work@barrel_shifter.shiftx8
|vpiIndex:
\_operation: , line:73
|vpiOpType:11
|vpiOperand:
\_constant: , line:73
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiOperand:
\_ref_obj: (i), line:73
|vpiName:i
|vpiPort:
\_port: (shifter_input), line:27
|vpiName:shifter_input
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (shifter_input), line:27
|vpiName:shifter_input
|vpiFullName:work@barrel_shifter.shifter_input
|vpiNetType:36
|vpiPort:
\_port: (shift_amount), line:28
|vpiName:shift_amount
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (shift_amount), line:28
|vpiName:shift_amount
|vpiFullName:work@barrel_shifter.shift_amount
|vpiNetType:36
|vpiPort:
\_port: (arith), line:29
|vpiName:arith
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (arith), line:29
|vpiName:arith
|vpiFullName:work@barrel_shifter.arith
|vpiNetType:36
|vpiPort:
\_port: (lshift), line:30
|vpiName:lshift
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (lshift), line:30
|vpiName:lshift
|vpiFullName:work@barrel_shifter.lshift
|vpiNetType:36
|vpiPort:
\_port: (shifted_resultr), line:31
|vpiName:shifted_resultr
|vpiDirection:2
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (shifted_resultr), line:31
|vpiName:shifted_resultr
|vpiFullName:work@barrel_shifter.shifted_resultr
|vpiNetType:36
|vpiPort:
\_port: (shifted_resultl), line:32
|vpiName:shifted_resultl
|vpiDirection:2
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (shifted_resultl), line:32
|vpiName:shifted_resultl
|vpiFullName:work@barrel_shifter.shifted_resultl
|vpiNetType:36
|vpiContAssign:
\_cont_assign: , line:69
|vpiRhs:
\_ref_obj: (shiftx8), line:69
|vpiName:shiftx8
|vpiFullName:work@barrel_shifter.shiftx8
|vpiLhs:
\_ref_obj: (shifted_resultr), line:69
|vpiName:shifted_resultr
|vpiFullName:work@barrel_shifter.shifted_resultr
|vpiNet:
\_logic_net: (shifter_input), line:27
|vpiNet:
\_logic_net: (shift_amount), line:28
|vpiNet:
\_logic_net: (arith), line:29
|vpiNet:
\_logic_net: (lshift), line:30
|vpiNet:
\_logic_net: (shifted_resultr), line:31
|vpiNet:
\_logic_net: (shifted_resultl), line:32
|vpiNet:
\_logic_net: (shiftx8), line:35
|vpiName:shiftx8
|vpiFullName:work@barrel_shifter.shiftx8
|vpiNetType:36
|vpiNet:
\_logic_net: (shiftx2), line:35
|vpiName:shiftx2
|vpiFullName:work@barrel_shifter.shiftx2
|vpiNetType:36
|vpiNet:
\_logic_net: (shiftx1), line:35
|vpiName:shiftx1
|vpiFullName:work@barrel_shifter.shiftx1
|vpiNetType:36
|vpiNet:
\_logic_net: (preshifted_input), line:36
|vpiName:preshifted_input
|vpiFullName:work@barrel_shifter.preshifted_input
|vpiNetType:36
|vpiTypedef:
\_struct_typespec: (alu_inputs_t), line:301
|vpiTypedef:
\_enum_typespec: (alu_logic_op_t), line:84
|vpiTypedef:
\_enum_typespec: (alu_op_t), line:91
|vpiTypedef:
\_enum_typespec: (alu_rs1_op_t), line:97
|vpiTypedef:
\_enum_typespec: (alu_rs2_op_t), line:104
|vpiTypedef:
\_struct_typespec: (amo_alu_inputs_t), line:356
|vpiTypedef:
\_struct_typespec: (amo_details_t), line:362
|vpiTypedef:
\_enum_typespec: (amo_t), line:354
|vpiTypedef:
\_struct_typespec: (branch_inputs_t), line:313
|vpiTypedef:
\_logic_typespec: (branch_predictor_metadata_t), line:32
|vpiTypedef:
\_struct_typespec: (branch_results_t), line:330
|vpiTypedef:
\_enum_typespec: (bus_type_t), line:86
|vpiTypedef:
\_struct_typespec: (csr_inputs_t), line:396
|vpiTypedef:
\_enum_typespec: (csr_op_t), line:218
|vpiTypedef:
\_enum_typespec: (csr_t), line:201
|vpiTypedef:
\_struct_typespec: (data_access_shared_inputs_t), line:427
|vpiTypedef:
\_struct_typespec: (div_inputs_t), line:389
|vpiTypedef:
\_enum_typespec: (div_type), line:66
|vpiTypedef:
\_enum_typespec: (exception_code_t), line:245
|vpiTypedef:
\_struct_typespec: (exception_packet_t), line:263
|vpiTypedef:
\_struct_typespec: (fetch_buffer_packet_t), line:276
|vpiTypedef:
\_enum_typespec: (fifo_type_t), line:440
|vpiTypedef:
\_enum_typespec: (fn3_arith_t), line:76
|vpiTypedef:
\_enum_typespec: (fn3_branch_t), line:126
|vpiTypedef:
\_enum_typespec: (fn3_csr_t), line:212
|vpiTypedef:
\_enum_typespec: (fn3_ls_t), line:115
|vpiTypedef:
\_enum_typespec: (fn3_mul_div_t), line:138
|vpiTypedef:
\_struct_typespec: (gc_inputs_t), line:404
|vpiTypedef:
\_struct_typespec: (inflight_instruction_packet), line:271
|vpiTypedef:
\_logic_typespec: (instruction_id_t), line:30
|vpiTypedef:
\_enum_typespec: (interrupt_code_t), line:261
|vpiTypedef:
\_struct_typespec: (load_store_inputs_t), line:369
|vpiTypedef:
\_struct_typespec: (mul_inputs_t), line:383
|vpiTypedef:
\_enum_typespec: (opcodes_t), line:48
|vpiTypedef:
\_enum_typespec: (opcodes_trimmed_t), line:65
|vpiTypedef:
\_struct_typespec: (simulation_named_regfile), line:476
|vpiTypedef:
\_struct_typespec: (taiga_trace_events_t), line:442
|vpiTypedef:
\_struct_typespec: (to_l1_arbiter_packet), line:418
|vpiTypedef:
\_struct_typespec: (trace_outputs_t), line:469
|vpiTypedef:
\_logic_typespec: (unit_id_t), line:31
|vpiTypedef:
\_struct_typespec: (unit_writeback_t), line:295
|vpiTypedef:
\_enum_typespec: (vm_t), line:223
|uhdmallModules:
\_module: work@binary_occupancy, file:third_party/cores/taiga/core/binary_occupancy.sv, line:26, parent:work@div_unit_core_wrapper
|vpiDefName:work@binary_occupancy
|vpiFullName:work@binary_occupancy
|vpiProcess:
\_always: , line:42
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:42
|vpiCondition:
\_operation: , line:42
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:42
|vpiName:clk
|vpiFullName:work@binary_occupancy.clk
|vpiStmt:
\_begin: , line:42
|vpiFullName:work@binary_occupancy
|vpiStmt:
\_if_else: , line:43
|vpiCondition:
\_ref_obj: (rst), line:43
|vpiName:rst
|vpiFullName:work@binary_occupancy.rst
|vpiStmt:
\_assignment: , line:44
|vpiOpType:82
|vpiLhs:
\_ref_obj: (count), line:44
|vpiName:count
|vpiFullName:work@binary_occupancy.count
|vpiRhs:
\_constant: , line:44
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiElseStmt:
\_begin: , line:45
|vpiFullName:work@binary_occupancy
|vpiStmt:
\_case_stmt: , line:46
|vpiCaseType:1
|vpiCondition:
\_operation: , line:46
|vpiOpType:33
|vpiOperand:
\_ref_obj: (push), line:46
|vpiName:push
|vpiOperand:
\_ref_obj: (pop), line:46
|vpiName:pop
|vpiCaseItem:
\_case_item: , line:47
|vpiExpr:
\_constant: , line:47
|vpiConstType:3
|vpiDecompile:2'b10
|vpiSize:2
|BIN:2'b10
|vpiStmt:
\_assignment: , line:47
|vpiOpType:82
|vpiLhs:
\_ref_obj: (count), line:47
|vpiName:count
|vpiFullName:work@binary_occupancy.count
|vpiRhs:
\_operation: , line:47
|vpiOpType:24
|vpiOperand:
\_ref_obj: (count), line:47
|vpiName:count
|vpiFullName:work@binary_occupancy.count
|vpiOperand:
\_constant: , line:47
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiCaseItem:
\_case_item: , line:48
|vpiExpr:
\_constant: , line:48
|vpiConstType:3
|vpiDecompile:2'b01
|vpiSize:2
|BIN:2'b01
|vpiStmt:
\_assignment: , line:48
|vpiOpType:82
|vpiLhs:
\_ref_obj: (count), line:48
|vpiName:count
|vpiFullName:work@binary_occupancy.count
|vpiRhs:
\_operation: , line:48
|vpiOpType:11
|vpiOperand:
\_ref_obj: (count), line:48
|vpiName:count
|vpiFullName:work@binary_occupancy.count
|vpiOperand:
\_constant: , line:48
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiCaseItem:
\_case_item: , line:49
|vpiStmt:
\_assignment: , line:49
|vpiOpType:82
|vpiLhs:
\_ref_obj: (count), line:49
|vpiName:count
|vpiFullName:work@binary_occupancy.count
|vpiRhs:
\_ref_obj: (count), line:49
|vpiName:count
|vpiFullName:work@binary_occupancy.count
|vpiProcess:
\_always: , line:54
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:54
|vpiCondition:
\_operation: , line:54
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:54
|vpiName:clk
|vpiFullName:work@binary_occupancy.clk
|vpiStmt:
\_begin: , line:54
|vpiFullName:work@binary_occupancy
|vpiStmt:
\_if_else: , line:55
|vpiCondition:
\_ref_obj: (rst), line:55
|vpiName:rst
|vpiFullName:work@binary_occupancy.rst
|vpiStmt:
\_assignment: , line:56
|vpiOpType:82
|vpiLhs:
\_ref_obj: (valid), line:56
|vpiName:valid
|vpiFullName:work@binary_occupancy.valid
|vpiRhs:
\_constant: , line:56
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiElseStmt:
\_begin: , line:57
|vpiFullName:work@binary_occupancy
|vpiStmt:
\_case_stmt: , line:58
|vpiCaseType:1
|vpiCondition:
\_operation: , line:58
|vpiOpType:33
|vpiOperand:
\_ref_obj: (push), line:58
|vpiName:push
|vpiOperand:
\_ref_obj: (pop), line:58
|vpiName:pop
|vpiCaseItem:
\_case_item: , line:59
|vpiExpr:
\_constant: , line:59
|vpiConstType:3
|vpiDecompile:2'b10
|vpiSize:2
|BIN:2'b10
|vpiStmt:
\_assignment: , line:59
|vpiOpType:82
|vpiLhs:
\_ref_obj: (valid), line:59
|vpiName:valid
|vpiFullName:work@binary_occupancy.valid
|vpiRhs:
\_constant: , line:59
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiCaseItem:
\_case_item: , line:60
|vpiExpr:
\_constant: , line:60
|vpiConstType:3
|vpiDecompile:2'b01
|vpiSize:2
|BIN:2'b01
|vpiStmt:
\_assignment: , line:60
|vpiOpType:82
|vpiLhs:
\_ref_obj: (valid), line:60
|vpiName:valid
|vpiFullName:work@binary_occupancy.valid
|vpiRhs:
\_operation: , line:60
|vpiOpType:3
|vpiOperand:
\_operation: , line:60
|vpiOpType:14
|vpiOperand:
\_ref_obj: (count), line:60
|vpiName:count
|vpiFullName:work@binary_occupancy.count
|vpiOperand:
\_constant: , line:60
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiCaseItem:
\_case_item: , line:61
|vpiStmt:
\_assignment: , line:61
|vpiOpType:82
|vpiLhs:
\_ref_obj: (valid), line:61
|vpiName:valid
|vpiFullName:work@binary_occupancy.valid
|vpiRhs:
\_ref_obj: (valid), line:61
|vpiName:valid
|vpiFullName:work@binary_occupancy.valid
|vpiProcess:
\_always: , line:106
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:106
|vpiCondition:
\_operation: , line:106
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:106
|vpiName:clk
|vpiFullName:work@binary_occupancy.clk
|vpiStmt:
\_begin: , line:106
|vpiFullName:work@binary_occupancy
|vpiStmt:
\_immediate_assert: , line:107
|vpiExpr:
\_operation: , line:107
|vpiOpType:3
|vpiOperand:
\_operation: , line:107
|vpiOpType:28
|vpiOperand:
\_operation: , line:107
|vpiOpType:28
|vpiOperand:
\_operation: , line:107
|vpiOpType:4
|vpiOperand:
\_ref_obj: (rst), line:107
|vpiName:rst
|vpiFullName:work@binary_occupancy.rst
|vpiOperand:
\_ref_obj: (full), line:107
|vpiName:full
|vpiFullName:work@binary_occupancy.full
|vpiOperand:
\_ref_obj: (push), line:107
|vpiName:push
|vpiFullName:work@binary_occupancy.push
|vpiElseStmt:
\_sys_func_call: ($error), line:107
|vpiName:$error
|vpiArgument:
\_constant: , line:107
|vpiConstType:6
|vpiDecompile:"overflow"
|vpiSize:10
|STRING:"overflow"
|vpiStmt:
\_immediate_assert: , line:108
|vpiExpr:
\_operation: , line:108
|vpiOpType:3
|vpiOperand:
\_operation: , line:108
|vpiOpType:28
|vpiOperand:
\_operation: , line:108
|vpiOpType:28
|vpiOperand:
\_operation: , line:108
|vpiOpType:4
|vpiOperand:
\_ref_obj: (rst), line:108
|vpiName:rst
|vpiFullName:work@binary_occupancy.rst
|vpiOperand:
\_ref_obj: (empty), line:108
|vpiName:empty
|vpiFullName:work@binary_occupancy.empty
|vpiOperand:
\_ref_obj: (pop), line:108
|vpiName:pop
|vpiFullName:work@binary_occupancy.pop
|vpiElseStmt:
\_sys_func_call: ($error), line:108
|vpiName:$error
|vpiArgument:
\_constant: , line:108
|vpiConstType:6
|vpiDecompile:"underflow"
|vpiSize:11
|STRING:"underflow"
|vpiPort:
\_port: (clk), line:28
|vpiName:clk
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (clk), line:28
|vpiName:clk
|vpiFullName:work@binary_occupancy.clk
|vpiNetType:36
|vpiPort:
\_port: (rst), line:29
|vpiName:rst
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (rst), line:29
|vpiName:rst
|vpiFullName:work@binary_occupancy.rst
|vpiNetType:36
|vpiPort:
\_port: (push), line:30
|vpiName:push
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (push), line:30
|vpiName:push
|vpiFullName:work@binary_occupancy.push
|vpiNetType:36
|vpiPort:
\_port: (pop), line:31
|vpiName:pop
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (pop), line:31
|vpiName:pop
|vpiFullName:work@binary_occupancy.pop
|vpiNetType:36
|vpiPort:
\_port: (almost_full), line:32
|vpiName:almost_full
|vpiDirection:2
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (almost_full), line:32
|vpiName:almost_full
|vpiFullName:work@binary_occupancy.almost_full
|vpiNetType:36
|vpiPort:
\_port: (full), line:33
|vpiName:full
|vpiDirection:2
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (full), line:33
|vpiName:full
|vpiFullName:work@binary_occupancy.full
|vpiNetType:36
|vpiPort:
\_port: (empty), line:34
|vpiName:empty
|vpiDirection:2
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (empty), line:34
|vpiName:empty
|vpiFullName:work@binary_occupancy.empty
|vpiNetType:36
|vpiPort:
\_port: (almost_empty), line:35
|vpiName:almost_empty
|vpiDirection:2
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (almost_empty), line:35
|vpiName:almost_empty
|vpiFullName:work@binary_occupancy.almost_empty
|vpiNetType:36
|vpiPort:
\_port: (valid), line:36
|vpiName:valid
|vpiDirection:2
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (valid), line:36
|vpiName:valid
|vpiFullName:work@binary_occupancy.valid
|vpiNetType:36
|vpiContAssign:
\_cont_assign: , line:102
|vpiRhs:
\_operation: , line:102
|vpiOpType:4
|vpiOperand:
\_ref_obj: (valid), line:102
|vpiName:valid
|vpiFullName:work@binary_occupancy.valid
|vpiLhs:
\_ref_obj: (empty), line:102
|vpiName:empty
|vpiFullName:work@binary_occupancy.empty
|vpiNet:
\_logic_net: (clk), line:28
|vpiNet:
\_logic_net: (rst), line:29
|vpiNet:
\_logic_net: (push), line:30
|vpiNet:
\_logic_net: (pop), line:31
|vpiNet:
\_logic_net: (almost_full), line:32
|vpiNet:
\_logic_net: (full), line:33
|vpiNet:
\_logic_net: (empty), line:34
|vpiNet:
\_logic_net: (almost_empty), line:35
|vpiNet:
\_logic_net: (valid), line:36
|vpiNet:
\_logic_net: (count), line:39
|vpiName:count
|vpiFullName:work@binary_occupancy.count
|vpiNetType:36
|vpiTypedef:
\_struct_typespec: (alu_inputs_t), line:301
|vpiTypedef:
\_enum_typespec: (alu_logic_op_t), line:84
|vpiTypedef:
\_enum_typespec: (alu_op_t), line:91
|vpiTypedef:
\_enum_typespec: (alu_rs1_op_t), line:97
|vpiTypedef:
\_enum_typespec: (alu_rs2_op_t), line:104
|vpiTypedef:
\_struct_typespec: (amo_alu_inputs_t), line:356
|vpiTypedef:
\_struct_typespec: (amo_details_t), line:362
|vpiTypedef:
\_enum_typespec: (amo_t), line:354
|vpiTypedef:
\_struct_typespec: (branch_inputs_t), line:313
|vpiTypedef:
\_logic_typespec: (branch_predictor_metadata_t), line:32
|vpiTypedef:
\_struct_typespec: (branch_results_t), line:330
|vpiTypedef:
\_enum_typespec: (bus_type_t), line:86
|vpiTypedef:
\_struct_typespec: (csr_inputs_t), line:396
|vpiTypedef:
\_enum_typespec: (csr_op_t), line:218
|vpiTypedef:
\_enum_typespec: (csr_t), line:201
|vpiTypedef:
\_struct_typespec: (data_access_shared_inputs_t), line:427
|vpiTypedef:
\_struct_typespec: (div_inputs_t), line:389
|vpiTypedef:
\_enum_typespec: (div_type), line:66
|vpiTypedef:
\_enum_typespec: (exception_code_t), line:245
|vpiTypedef:
\_struct_typespec: (exception_packet_t), line:263
|vpiTypedef:
\_struct_typespec: (fetch_buffer_packet_t), line:276
|vpiTypedef:
\_enum_typespec: (fifo_type_t), line:440
|vpiTypedef:
\_enum_typespec: (fn3_arith_t), line:76
|vpiTypedef:
\_enum_typespec: (fn3_branch_t), line:126
|vpiTypedef:
\_enum_typespec: (fn3_csr_t), line:212
|vpiTypedef:
\_enum_typespec: (fn3_ls_t), line:115
|vpiTypedef:
\_enum_typespec: (fn3_mul_div_t), line:138
|vpiTypedef:
\_struct_typespec: (gc_inputs_t), line:404
|vpiTypedef:
\_struct_typespec: (inflight_instruction_packet), line:271
|vpiTypedef:
\_logic_typespec: (instruction_id_t), line:30
|vpiTypedef:
\_enum_typespec: (interrupt_code_t), line:261
|vpiTypedef:
\_struct_typespec: (load_store_inputs_t), line:369
|vpiTypedef:
\_struct_typespec: (mul_inputs_t), line:383
|vpiTypedef:
\_enum_typespec: (opcodes_t), line:48
|vpiTypedef:
\_enum_typespec: (opcodes_trimmed_t), line:65
|vpiTypedef:
\_struct_typespec: (simulation_named_regfile), line:476
|vpiTypedef:
\_struct_typespec: (taiga_trace_events_t), line:442
|vpiTypedef:
\_struct_typespec: (to_l1_arbiter_packet), line:418
|vpiTypedef:
\_struct_typespec: (trace_outputs_t), line:469
|vpiTypedef:
\_logic_typespec: (unit_id_t), line:31
|vpiTypedef:
\_struct_typespec: (unit_writeback_t), line:295
|vpiTypedef:
\_enum_typespec: (vm_t), line:223
|vpiParamAssign:
\_param_assign: , line:26
|vpiRhs:
\_constant: , line:26
|vpiConstType:7
|vpiDecompile:4
|vpiSize:32
|INT:4
|vpiLhs:
\_parameter: (DEPTH), line:26
|vpiName:DEPTH
|vpiParameter:
\_parameter: (DEPTH), line:26
|uhdmallModules:
\_module: work@branch_comparator, file:third_party/cores/taiga/core/branch_comparator.sv, line:26, parent:work@div_unit_core_wrapper
|vpiDefName:work@branch_comparator
|vpiFullName:work@branch_comparator
|vpiProcess:
\_always: , line:81
|vpiAlwaysType:2
|vpiStmt:
\_begin: , line:81
|vpiFullName:work@branch_comparator
|vpiStmt:
\_foreach_stmt: , line:82
|vpiFullName:work@branch_comparator
|vpiVariables:
\_chandle_var: (sub_ls_a), line:82
|vpiName:sub_ls_a
|vpiFullName:work@branch_comparator.sub_ls_a
|vpiLoopVars:
\_chandle_var: (i), line:82
|vpiName:i
|vpiFullName:work@branch_comparator.i
|vpiStmt:
\_begin: , line:82
|vpiFullName:work@branch_comparator
|vpiStmt:
\_assignment: , line:83
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_bit_select: (sub_ls_a), line:83
|vpiName:sub_ls_a
|vpiFullName:work@branch_comparator.sub_ls_a
|vpiIndex:
\_ref_obj: (i), line:83
|vpiName:i
|vpiRhs:
\_operation: , line:83
|vpiOpType:29
|vpiOperand:
\_operation: , line:83
|vpiOpType:28
|vpiOperand:
\_operation: , line:83
|vpiOpType:28
|vpiOperand:
\_bit_select: (ls_a), line:83
|vpiName:ls_a
|vpiFullName:work@branch_comparator.ls_a
|vpiIndex:
\_operation: , line:83
|vpiOpType:25
|vpiOperand:
\_constant: , line:83
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiOperand:
\_ref_obj: (i), line:83
|vpiName:i
|vpiOperand:
\_bit_select: (ls_b), line:83
|vpiName:ls_b
|vpiFullName:work@branch_comparator.ls_b
|vpiIndex:
\_operation: , line:83
|vpiOpType:25
|vpiOperand:
\_constant: , line:83
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiOperand:
\_ref_obj: (i), line:83
|vpiName:i
|vpiFullName:work@branch_comparator.i
|vpiOperand:
\_operation: , line:83
|vpiOpType:29
|vpiOperand:
\_bit_select: (ls_a), line:83
|vpiName:ls_a
|vpiFullName:work@branch_comparator.ls_a
|vpiIndex:
\_operation: , line:83
|vpiOpType:24
|vpiOperand:
\_operation: , line:83
|vpiOpType:25
|vpiOperand:
\_constant: , line:83
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiOperand:
\_ref_obj: (i), line:83
|vpiName:i
|vpiFullName:work@branch_comparator.i
|vpiOperand:
\_constant: , line:83
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiOperand:
\_bit_select: (ls_b), line:83
|vpiName:ls_b
|vpiFullName:work@branch_comparator.ls_b
|vpiIndex:
\_operation: , line:83
|vpiOpType:24
|vpiOperand:
\_operation: , line:83
|vpiOpType:25
|vpiOperand:
\_constant: , line:83
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiOperand:
\_ref_obj: (i), line:83
|vpiName:i
|vpiFullName:work@branch_comparator.i
|vpiOperand:
\_constant: , line:83
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiOperand:
\_operation: , line:83
|vpiOpType:28
|vpiOperand:
\_bit_select: (ls_a), line:83
|vpiName:ls_a
|vpiFullName:work@branch_comparator.ls_a
|vpiIndex:
\_operation: , line:83
|vpiOpType:24
|vpiOperand:
\_operation: , line:83
|vpiOpType:25
|vpiOperand:
\_constant: , line:83
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiOperand:
\_ref_obj: (i), line:83
|vpiName:i
|vpiFullName:work@branch_comparator.i
|vpiOperand:
\_constant: , line:83
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiOperand:
\_bit_select: (ls_b), line:83
|vpiName:ls_b
|vpiFullName:work@branch_comparator.ls_b
|vpiIndex:
\_operation: , line:83
|vpiOpType:24
|vpiOperand:
\_operation: , line:83
|vpiOpType:25
|vpiOperand:
\_constant: , line:83
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiOperand:
\_ref_obj: (i), line:83
|vpiName:i
|vpiFullName:work@branch_comparator.i
|vpiOperand:
\_constant: , line:83
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiStmt:
\_assignment: , line:84
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_bit_select: (sub_ls_b), line:84
|vpiName:sub_ls_b
|vpiFullName:work@branch_comparator.sub_ls_b
|vpiIndex:
\_ref_obj: (i), line:84
|vpiName:i
|vpiRhs:
\_operation: , line:84
|vpiOpType:29
|vpiOperand:
\_operation: , line:84
|vpiOpType:29
|vpiOperand:
\_operation: , line:84
|vpiOpType:28
|vpiOperand:
\_operation: , line:84
|vpiOpType:28
|vpiOperand:
\_bit_select: (ls_a), line:84
|vpiName:ls_a
|vpiFullName:work@branch_comparator.ls_a
|vpiIndex:
\_operation: , line:84
|vpiOpType:25
|vpiOperand:
\_constant: , line:84
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiOperand:
\_ref_obj: (i), line:84
|vpiName:i
|vpiOperand:
\_bit_select: (ls_b), line:84
|vpiName:ls_b
|vpiFullName:work@branch_comparator.ls_b
|vpiIndex:
\_operation: , line:84
|vpiOpType:25
|vpiOperand:
\_constant: , line:84
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiOperand:
\_ref_obj: (i), line:84
|vpiName:i
|vpiFullName:work@branch_comparator.i
|vpiOperand:
\_operation: , line:84
|vpiOpType:29
|vpiOperand:
\_bit_select: (ls_a), line:84
|vpiName:ls_a
|vpiFullName:work@branch_comparator.ls_a
|vpiIndex:
\_operation: , line:84
|vpiOpType:24
|vpiOperand:
\_operation: , line:84
|vpiOpType:25
|vpiOperand:
\_constant: , line:84
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiOperand:
\_ref_obj: (i), line:84
|vpiName:i
|vpiFullName:work@branch_comparator.i
|vpiOperand:
\_constant: , line:84
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiOperand:
\_bit_select: (ls_b), line:84
|vpiName:ls_b
|vpiFullName:work@branch_comparator.ls_b
|vpiIndex:
\_operation: , line:84
|vpiOpType:24
|vpiOperand:
\_operation: , line:84
|vpiOpType:25
|vpiOperand:
\_constant: , line:84
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiOperand:
\_ref_obj: (i), line:84
|vpiName:i
|vpiFullName:work@branch_comparator.i
|vpiOperand:
\_constant: , line:84
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiOperand:
\_operation: , line:84
|vpiOpType:28
|vpiOperand:
\_bit_select: (ls_a), line:84
|vpiName:ls_a
|vpiFullName:work@branch_comparator.ls_a
|vpiIndex:
\_operation: , line:84
|vpiOpType:24
|vpiOperand:
\_operation: , line:84
|vpiOpType:25
|vpiOperand:
\_constant: , line:84
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiOperand:
\_ref_obj: (i), line:84
|vpiName:i
|vpiFullName:work@branch_comparator.i
|vpiOperand:
\_constant: , line:84
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiOperand:
\_bit_select: (ls_b), line:84
|vpiName:ls_b
|vpiFullName:work@branch_comparator.ls_b
|vpiIndex:
\_operation: , line:84
|vpiOpType:24
|vpiOperand:
\_operation: , line:84
|vpiOpType:25
|vpiOperand:
\_constant: , line:84
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiOperand:
\_ref_obj: (i), line:84
|vpiName:i
|vpiFullName:work@branch_comparator.i
|vpiOperand:
\_constant: , line:84
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiOperand:
\_operation: , line:85
|vpiOpType:28
|vpiOperand:
\_operation: , line:85
|vpiOpType:29
|vpiOperand:
\_bit_select: (ls_a), line:85
|vpiName:ls_a
|vpiFullName:work@branch_comparator.ls_a
|vpiIndex:
\_operation: , line:85
|vpiOpType:25
|vpiOperand:
\_constant: , line:85
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiOperand:
\_ref_obj: (i), line:85
|vpiName:i
|vpiFullName:work@branch_comparator.i
|vpiOperand:
\_bit_select: (ls_b), line:85
|vpiName:ls_b
|vpiFullName:work@branch_comparator.ls_b
|vpiIndex:
\_operation: , line:85
|vpiOpType:25
|vpiOperand:
\_constant: , line:85
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiOperand:
\_ref_obj: (i), line:85
|vpiName:i
|vpiFullName:work@branch_comparator.i
|vpiOperand:
\_operation: , line:85
|vpiOpType:29
|vpiOperand:
\_bit_select: (ls_a), line:85
|vpiName:ls_a
|vpiFullName:work@branch_comparator.ls_a
|vpiIndex:
\_operation: , line:85
|vpiOpType:24
|vpiOperand:
\_operation: , line:85
|vpiOpType:25
|vpiOperand:
\_constant: , line:85
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiOperand:
\_ref_obj: (i), line:85
|vpiName:i
|vpiFullName:work@branch_comparator.i
|vpiOperand:
\_constant: , line:85
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiOperand:
\_bit_select: (ls_b), line:85
|vpiName:ls_b
|vpiFullName:work@branch_comparator.ls_b
|vpiIndex:
\_operation: , line:85
|vpiOpType:24
|vpiOperand:
\_operation: , line:85
|vpiOpType:25
|vpiOperand:
\_constant: , line:85
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiOperand:
\_ref_obj: (i), line:85
|vpiName:i
|vpiFullName:work@branch_comparator.i
|vpiOperand:
\_constant: , line:85
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiStmt:
\_assignment: , line:87
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_bit_select: (sub_eq_a), line:87
|vpiName:sub_eq_a
|vpiFullName:work@branch_comparator.sub_eq_a
|vpiIndex:
\_ref_obj: (i), line:87
|vpiName:i
|vpiRhs:
\_operation: , line:87
|vpiOpType:28
|vpiOperand:
\_operation: , line:87
|vpiOpType:29
|vpiOperand:
\_bit_select: (eq_a), line:87
|vpiName:eq_a
|vpiFullName:work@branch_comparator.eq_a
|vpiIndex:
\_operation: , line:87
|vpiOpType:25
|vpiOperand:
\_constant: , line:87
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiOperand:
\_ref_obj: (i), line:87
|vpiName:i
|vpiOperand:
\_bit_select: (eq_b), line:87
|vpiName:eq_b
|vpiFullName:work@branch_comparator.eq_b
|vpiIndex:
\_operation: , line:87
|vpiOpType:25
|vpiOperand:
\_constant: , line:87
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiOperand:
\_ref_obj: (i), line:87
|vpiName:i
|vpiFullName:work@branch_comparator.i
|vpiOperand:
\_operation: , line:87
|vpiOpType:29
|vpiOperand:
\_bit_select: (eq_a), line:87
|vpiName:eq_a
|vpiFullName:work@branch_comparator.eq_a
|vpiIndex:
\_operation: , line:87
|vpiOpType:24
|vpiOperand:
\_operation: , line:87
|vpiOpType:25
|vpiOperand:
\_constant: , line:87
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiOperand:
\_ref_obj: (i), line:87
|vpiName:i
|vpiFullName:work@branch_comparator.i
|vpiOperand:
\_constant: , line:87
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiOperand:
\_bit_select: (eq_b), line:87
|vpiName:eq_b
|vpiFullName:work@branch_comparator.eq_b
|vpiIndex:
\_operation: , line:87
|vpiOpType:24
|vpiOperand:
\_operation: , line:87
|vpiOpType:25
|vpiOperand:
\_constant: , line:87
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiOperand:
\_ref_obj: (i), line:87
|vpiName:i
|vpiFullName:work@branch_comparator.i
|vpiOperand:
\_constant: , line:87
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiPort:
\_port: (use_signed), line:27
|vpiName:use_signed
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (use_signed), line:27
|vpiName:use_signed
|vpiFullName:work@branch_comparator.use_signed
|vpiNetType:36
|vpiPort:
\_port: (less_than), line:28
|vpiName:less_than
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (less_than), line:28
|vpiName:less_than
|vpiFullName:work@branch_comparator.less_than
|vpiNetType:36
|vpiPort:
\_port: (a), line:29
|vpiName:a
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (a), line:29
|vpiName:a
|vpiFullName:work@branch_comparator.a
|vpiNetType:36
|vpiPort:
\_port: (b), line:30
|vpiName:b
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (b), line:30
|vpiName:b
|vpiFullName:work@branch_comparator.b
|vpiNetType:36
|vpiPort:
\_port: (result), line:31
|vpiName:result
|vpiDirection:2
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (result), line:31
|vpiName:result
|vpiFullName:work@branch_comparator.result
|vpiNetType:36
|vpiContAssign:
\_cont_assign: , line:58
|vpiRhs:
\_operation: , line:58
|vpiOpType:33
|vpiOperand:
\_operation: , line:58
|vpiOpType:28
|vpiOperand:
\_bit_select: (a), line:58
|vpiName:a
|vpiIndex:
\_constant: , line:58
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiOperand:
\_ref_obj: (use_signed), line:58
|vpiName:use_signed
|vpiOperand:
\_ref_obj: (a), line:58
|vpiName:a
|vpiLhs:
\_ref_obj: (sign_extended_a), line:58
|vpiName:sign_extended_a
|vpiFullName:work@branch_comparator.sign_extended_a
|vpiContAssign:
\_cont_assign: , line:59
|vpiRhs:
\_operation: , line:59
|vpiOpType:33
|vpiOperand:
\_operation: , line:59
|vpiOpType:28
|vpiOperand:
\_bit_select: (b), line:59
|vpiName:b
|vpiIndex:
\_constant: , line:59
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiOperand:
\_ref_obj: (use_signed), line:59
|vpiName:use_signed
|vpiOperand:
\_ref_obj: (b), line:59
|vpiName:b
|vpiLhs:
\_ref_obj: (sign_extended_b), line:59
|vpiName:sign_extended_b
|vpiFullName:work@branch_comparator.sign_extended_b
|vpiContAssign:
\_cont_assign: , line:61
|vpiRhs:
\_operation: , line:62
|vpiOpType:28
|vpiOperand:
\_operation: , line:62
|vpiOpType:29
|vpiOperand:
\_operation: , line:62
|vpiOpType:28
|vpiOperand:
\_bit_select: (sign_extended_a), line:62
|vpiName:sign_extended_a
|vpiFullName:work@branch_comparator.sign_extended_a
|vpiIndex:
\_constant: , line:62
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiOperand:
\_bit_select: (sign_extended_b), line:62
|vpiName:sign_extended_b
|vpiFullName:work@branch_comparator.sign_extended_b
|vpiIndex:
\_constant: , line:62
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiOperand:
\_operation: , line:62
|vpiOpType:28
|vpiOperand:
\_operation: , line:62
|vpiOpType:4
|vpiOperand:
\_bit_select: (sign_extended_a), line:62
|vpiName:sign_extended_a
|vpiIndex:
\_constant: , line:62
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiOperand:
\_operation: , line:62
|vpiOpType:4
|vpiOperand:
\_bit_select: (sign_extended_b), line:62
|vpiName:sign_extended_b
|vpiIndex:
\_constant: , line:62
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiOperand:
\_operation: , line:63
|vpiOpType:29
|vpiOperand:
\_operation: , line:63
|vpiOpType:28
|vpiOperand:
\_bit_select: (sign_extended_a), line:63
|vpiName:sign_extended_a
|vpiFullName:work@branch_comparator.sign_extended_a
|vpiIndex:
\_constant: , line:63
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiOperand:
\_bit_select: (sign_extended_b), line:63
|vpiName:sign_extended_b
|vpiFullName:work@branch_comparator.sign_extended_b
|vpiIndex:
\_constant: , line:63
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiOperand:
\_operation: , line:63
|vpiOpType:28
|vpiOperand:
\_operation: , line:63
|vpiOpType:4
|vpiOperand:
\_bit_select: (sign_extended_a), line:63
|vpiName:sign_extended_a
|vpiIndex:
\_constant: , line:63
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiOperand:
\_operation: , line:63
|vpiOpType:4
|vpiOperand:
\_bit_select: (sign_extended_b), line:63
|vpiName:sign_extended_b
|vpiIndex:
\_constant: , line:63
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiLhs:
\_ref_obj: (eq_carry_in), line:61
|vpiName:eq_carry_in
|vpiFullName:work@branch_comparator.eq_carry_in
|vpiContAssign:
\_cont_assign: , line:65
|vpiRhs:
\_operation: , line:66
|vpiOpType:29
|vpiOperand:
\_operation: , line:66
|vpiOpType:28
|vpiOperand:
\_operation: , line:66
|vpiOpType:29
|vpiOperand:
\_bit_select: (sign_extended_a), line:66
|vpiName:sign_extended_a
|vpiFullName:work@branch_comparator.sign_extended_a
|vpiIndex:
\_constant: , line:66
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiOperand:
\_operation: , line:66
|vpiOpType:4
|vpiOperand:
\_bit_select: (sign_extended_b), line:66
|vpiName:sign_extended_b
|vpiIndex:
\_constant: , line:66
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiOperand:
\_operation: , line:66
|vpiOpType:29
|vpiOperand:
\_bit_select: (sign_extended_a), line:66
|vpiName:sign_extended_a
|vpiFullName:work@branch_comparator.sign_extended_a
|vpiIndex:
\_constant: , line:66
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiOperand:
\_operation: , line:66
|vpiOpType:4
|vpiOperand:
\_bit_select: (sign_extended_b), line:66
|vpiName:sign_extended_b
|vpiIndex:
\_constant: , line:66
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiOperand:
\_operation: , line:67
|vpiOpType:28
|vpiOperand:
\_bit_select: (sign_extended_a), line:67
|vpiName:sign_extended_a
|vpiFullName:work@branch_comparator.sign_extended_a
|vpiIndex:
\_constant: , line:67
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiOperand:
\_operation: , line:67
|vpiOpType:4
|vpiOperand:
\_bit_select: (sign_extended_b), line:67
|vpiName:sign_extended_b
|vpiIndex:
\_constant: , line:67
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiLhs:
\_ref_obj: (ls_carry_in), line:65
|vpiName:ls_carry_in
|vpiFullName:work@branch_comparator.ls_carry_in
|vpiContAssign:
\_cont_assign: , line:69
|vpiRhs:
\_operation: , line:69
|vpiOpType:32
|vpiOperand:
\_ref_obj: (less_than), line:69
|vpiName:less_than
|vpiFullName:work@branch_comparator.less_than
|vpiOperand:
\_ref_obj: (ls_carry_in), line:69
|vpiName:ls_carry_in
|vpiFullName:work@branch_comparator.ls_carry_in
|vpiOperand:
\_ref_obj: (eq_carry_in), line:69
|vpiName:eq_carry_in
|vpiFullName:work@branch_comparator.eq_carry_in
|vpiLhs:
\_ref_obj: (carry_in), line:69
|vpiName:carry_in
|vpiFullName:work@branch_comparator.carry_in
|vpiContAssign:
\_cont_assign: , line:72
|vpiRhs:
\_operation: , line:72
|vpiOpType:33
|vpiOperand:
\_constant: , line:72
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiOperand:
\_part_select: , line:72, parent:sign_extended_a
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (sign_extended_a)
|vpiLeftRange:
\_constant: , line:72
|vpiConstType:7
|vpiDecompile:32
|vpiSize:32
|INT:32
|vpiRightRange:
\_constant: , line:72
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiLhs:
\_ref_obj: (ls_a), line:72
|vpiName:ls_a
|vpiFullName:work@branch_comparator.ls_a
|vpiContAssign:
\_cont_assign: , line:73
|vpiRhs:
\_operation: , line:73
|vpiOpType:33
|vpiOperand:
\_constant: , line:73
|vpiConstType:3
|vpiDecompile:'b1
|vpiSize:1
|BIN:1
|vpiOperand:
\_operation: , line:73
|vpiOpType:4
|vpiOperand:
\_part_select: , line:73, parent:sign_extended_b
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (sign_extended_b)
|vpiLeftRange:
\_constant: , line:73
|vpiConstType:7
|vpiDecompile:32
|vpiSize:32
|INT:32
|vpiRightRange:
\_constant: , line:73
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiLhs:
\_ref_obj: (ls_b), line:73
|vpiName:ls_b
|vpiFullName:work@branch_comparator.ls_b
|vpiContAssign:
\_cont_assign: , line:76
|vpiRhs:
\_operation: , line:76
|vpiOpType:28
|vpiOperand:
\_operation: , line:76
|vpiOpType:33
|vpiOperand:
\_constant: , line:76
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiOperand:
\_part_select: , line:76, parent:sign_extended_a
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (sign_extended_a)
|vpiLeftRange:
\_constant: , line:76
|vpiConstType:7
|vpiDecompile:32
|vpiSize:32
|INT:32
|vpiRightRange:
\_constant: , line:76
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiOperand:
\_operation: , line:76
|vpiOpType:33
|vpiOperand:
\_constant: , line:76
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiOperand:
\_part_select: , line:76, parent:sign_extended_b
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (sign_extended_b)
|vpiLeftRange:
\_constant: , line:76
|vpiConstType:7
|vpiDecompile:32
|vpiSize:32
|INT:32
|vpiRightRange:
\_constant: , line:76
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiLhs:
\_ref_obj: (eq_a), line:76
|vpiName:eq_a
|vpiFullName:work@branch_comparator.eq_a
|vpiContAssign:
\_cont_assign: , line:77
|vpiRhs:
\_operation: , line:77
|vpiOpType:28
|vpiOperand:
\_operation: , line:77
|vpiOpType:33
|vpiOperand:
\_constant: , line:77
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiOperand:
\_operation: , line:77
|vpiOpType:4
|vpiOperand:
\_part_select: , line:77, parent:sign_extended_a
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (sign_extended_a)
|vpiLeftRange:
\_constant: , line:77
|vpiConstType:7
|vpiDecompile:32
|vpiSize:32
|INT:32
|vpiRightRange:
\_constant: , line:77
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiOperand:
\_operation: , line:77
|vpiOpType:33
|vpiOperand:
\_constant: , line:77
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiOperand:
\_operation: , line:77
|vpiOpType:4
|vpiOperand:
\_part_select: , line:77, parent:sign_extended_b
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (sign_extended_b)
|vpiLeftRange:
\_constant: , line:77
|vpiConstType:7
|vpiDecompile:32
|vpiSize:32
|INT:32
|vpiRightRange:
\_constant: , line:77
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiLhs:
\_ref_obj: (eq_b), line:77
|vpiName:eq_b
|vpiFullName:work@branch_comparator.eq_b
|vpiContAssign:
\_cont_assign: , line:92
|vpiRhs:
\_operation: , line:92
|vpiOpType:32
|vpiOperand:
\_ref_obj: (less_than), line:92
|vpiName:less_than
|vpiFullName:work@branch_comparator.less_than
|vpiOperand:
\_operation: , line:93
|vpiOpType:24
|vpiOperand:
\_operation: , line:93
|vpiOpType:33
|vpiOperand:
\_ref_obj: (sub_ls_a), line:93
|vpiName:sub_ls_a
|vpiFullName:work@branch_comparator.sub_ls_a
|vpiOperand:
\_ref_obj: (carry_in), line:93
|vpiName:carry_in
|vpiFullName:work@branch_comparator.carry_in
|vpiOperand:
\_operation: , line:94
|vpiOpType:33
|vpiOperand:
\_ref_obj: (sub_ls_b), line:94
|vpiName:sub_ls_b
|vpiFullName:work@branch_comparator.sub_ls_b
|vpiOperand:
\_ref_obj: (carry_in), line:94
|vpiName:carry_in
|vpiFullName:work@branch_comparator.carry_in
|vpiOperand:
\_operation: , line:96
|vpiOpType:24
|vpiOperand:
\_operation: , line:96
|vpiOpType:33
|vpiOperand:
\_ref_obj: (sub_eq_a), line:96
|vpiName:sub_eq_a
|vpiFullName:work@branch_comparator.sub_eq_a
|vpiOperand:
\_ref_obj: (carry_in), line:96
|vpiName:carry_in
|vpiFullName:work@branch_comparator.carry_in
|vpiOperand:
\_operation: , line:97
|vpiOpType:33
|vpiOperand:
\_constant: , line:97
|vpiConstType:5
|vpiDecompile:16'h0000
|vpiSize:16
|HEX:16'h0000
|vpiOperand:
\_ref_obj: (carry_in), line:97
|vpiName:carry_in
|vpiFullName:work@branch_comparator.carry_in
|vpiLhs:
\_operation: , line:92
|vpiOpType:33
|vpiOperand:
\_ref_obj: (result), line:92
|vpiName:result
|vpiFullName:work@branch_comparator.result
|vpiOperand:
\_ref_obj: (sub_toss), line:92
|vpiName:sub_toss
|vpiFullName:work@branch_comparator.sub_toss
|vpiNet:
\_logic_net: (use_signed), line:27
|vpiNet:
\_logic_net: (less_than), line:28
|vpiNet:
\_logic_net: (a), line:29
|vpiNet:
\_logic_net: (b), line:30
|vpiNet:
\_logic_net: (result), line:31
|vpiNet:
\_logic_net: (sign_extended_a), line:34
|vpiName:sign_extended_a
|vpiFullName:work@branch_comparator.sign_extended_a
|vpiNetType:36
|vpiNet:
\_logic_net: (sign_extended_b), line:35
|vpiName:sign_extended_b
|vpiFullName:work@branch_comparator.sign_extended_b
|vpiNetType:36
|vpiNet:
\_logic_net: (eq_a), line:37
|vpiName:eq_a
|vpiFullName:work@branch_comparator.eq_a
|vpiNetType:36
|vpiNet:
\_logic_net: (eq_b), line:38
|vpiName:eq_b
|vpiFullName:work@branch_comparator.eq_b
|vpiNetType:36
|vpiNet:
\_logic_net: (ls_a), line:39
|vpiName:ls_a
|vpiFullName:work@branch_comparator.ls_a
|vpiNetType:36
|vpiNet:
\_logic_net: (ls_b), line:40
|vpiName:ls_b
|vpiFullName:work@branch_comparator.ls_b
|vpiNetType:36
|vpiNet:
\_logic_net: (sub_ls_a), line:42
|vpiName:sub_ls_a
|vpiFullName:work@branch_comparator.sub_ls_a
|vpiNetType:36
|vpiNet:
\_logic_net: (sub_ls_b), line:43
|vpiName:sub_ls_b
|vpiFullName:work@branch_comparator.sub_ls_b
|vpiNetType:36
|vpiNet:
\_logic_net: (sub_eq_a), line:44
|vpiName:sub_eq_a
|vpiFullName:work@branch_comparator.sub_eq_a
|vpiNetType:36
|vpiNet:
\_logic_net: (sub_toss), line:46
|vpiName:sub_toss
|vpiFullName:work@branch_comparator.sub_toss
|vpiNetType:36
|vpiNet:
\_logic_net: (eq_carry_in), line:48
|vpiName:eq_carry_in
|vpiFullName:work@branch_comparator.eq_carry_in
|vpiNetType:36
|vpiNet:
\_logic_net: (ls_carry_in), line:49
|vpiName:ls_carry_in
|vpiFullName:work@branch_comparator.ls_carry_in
|vpiNetType:36
|vpiNet:
\_logic_net: (carry_in), line:50
|vpiName:carry_in
|vpiFullName:work@branch_comparator.carry_in
|vpiNetType:36
|vpiTypedef:
\_struct_typespec: (alu_inputs_t), line:301
|vpiTypedef:
\_enum_typespec: (alu_logic_op_t), line:84
|vpiTypedef:
\_enum_typespec: (alu_op_t), line:91
|vpiTypedef:
\_enum_typespec: (alu_rs1_op_t), line:97
|vpiTypedef:
\_enum_typespec: (alu_rs2_op_t), line:104
|vpiTypedef:
\_struct_typespec: (amo_alu_inputs_t), line:356
|vpiTypedef:
\_struct_typespec: (amo_details_t), line:362
|vpiTypedef:
\_enum_typespec: (amo_t), line:354
|vpiTypedef:
\_struct_typespec: (branch_inputs_t), line:313
|vpiTypedef:
\_logic_typespec: (branch_predictor_metadata_t), line:32
|vpiTypedef:
\_struct_typespec: (branch_results_t), line:330
|vpiTypedef:
\_enum_typespec: (bus_type_t), line:86
|vpiTypedef:
\_struct_typespec: (csr_inputs_t), line:396
|vpiTypedef:
\_enum_typespec: (csr_op_t), line:218
|vpiTypedef:
\_enum_typespec: (csr_t), line:201
|vpiTypedef:
\_struct_typespec: (data_access_shared_inputs_t), line:427
|vpiTypedef:
\_struct_typespec: (div_inputs_t), line:389
|vpiTypedef:
\_enum_typespec: (div_type), line:66
|vpiTypedef:
\_enum_typespec: (exception_code_t), line:245
|vpiTypedef:
\_struct_typespec: (exception_packet_t), line:263
|vpiTypedef:
\_struct_typespec: (fetch_buffer_packet_t), line:276
|vpiTypedef:
\_enum_typespec: (fifo_type_t), line:440
|vpiTypedef:
\_enum_typespec: (fn3_arith_t), line:76
|vpiTypedef:
\_enum_typespec: (fn3_branch_t), line:126
|vpiTypedef:
\_enum_typespec: (fn3_csr_t), line:212
|vpiTypedef:
\_enum_typespec: (fn3_ls_t), line:115
|vpiTypedef:
\_enum_typespec: (fn3_mul_div_t), line:138
|vpiTypedef:
\_struct_typespec: (gc_inputs_t), line:404
|vpiTypedef:
\_struct_typespec: (inflight_instruction_packet), line:271
|vpiTypedef:
\_logic_typespec: (instruction_id_t), line:30
|vpiTypedef:
\_enum_typespec: (interrupt_code_t), line:261
|vpiTypedef:
\_struct_typespec: (load_store_inputs_t), line:369
|vpiTypedef:
\_struct_typespec: (mul_inputs_t), line:383
|vpiTypedef:
\_enum_typespec: (opcodes_t), line:48
|vpiTypedef:
\_enum_typespec: (opcodes_trimmed_t), line:65
|vpiTypedef:
\_struct_typespec: (simulation_named_regfile), line:476
|vpiTypedef:
\_struct_typespec: (taiga_trace_events_t), line:442
|vpiTypedef:
\_struct_typespec: (to_l1_arbiter_packet), line:418
|vpiTypedef:
\_struct_typespec: (trace_outputs_t), line:469
|vpiTypedef:
\_logic_typespec: (unit_id_t), line:31
|vpiTypedef:
\_struct_typespec: (unit_writeback_t), line:295
|vpiTypedef:
\_enum_typespec: (vm_t), line:223
|uhdmallModules:
\_module: work@branch_predictor, file:third_party/cores/taiga/core/branch_predictor.sv, line:26, parent:work@div_unit_core_wrapper
|vpiDefName:work@branch_predictor
|vpiFullName:work@branch_predictor
|vpiProcess:
\_always: , line:104
|vpiAlwaysType:2
|vpiStmt:
\_begin: , line:104
|vpiFullName:work@branch_predictor
|vpiStmt:
\_case_stmt: , line:105
|vpiCaseType:1
|vpiCondition:
\_ref_obj: (br_results.branch_ex_metadata), line:105
|vpiName:br_results.branch_ex_metadata
|vpiFullName:work@branch_predictor.br_results.branch_ex_metadata
|vpiCaseItem:
\_case_item: , line:106
|vpiExpr:
\_constant: , line:106
|vpiConstType:3
|vpiDecompile:2'b00
|vpiSize:2
|BIN:2'b00
|vpiStmt:
\_assignment: , line:106
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (ex_entry.metadata), line:106
|vpiName:ex_entry.metadata
|vpiFullName:work@branch_predictor.ex_entry.metadata
|vpiRhs:
\_operation: , line:106
|vpiOpType:32
|vpiOperand:
\_ref_obj: (br_results.branch_taken), line:106
|vpiName:br_results.branch_taken
|vpiFullName:work@branch_predictor.br_results.branch_taken
|vpiOperand:
\_constant: , line:106
|vpiConstType:3
|vpiDecompile:2'b01
|vpiSize:2
|BIN:2'b01
|vpiOperand:
\_constant: , line:106
|vpiConstType:3
|vpiDecompile:2'b00
|vpiSize:2
|BIN:2'b00
|vpiCaseItem:
\_case_item: , line:107
|vpiExpr:
\_constant: , line:107
|vpiConstType:3
|vpiDecompile:2'b01
|vpiSize:2
|BIN:2'b01
|vpiStmt:
\_assignment: , line:107
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (ex_entry.metadata), line:107
|vpiName:ex_entry.metadata
|vpiFullName:work@branch_predictor.ex_entry.metadata
|vpiRhs:
\_operation: , line:107
|vpiOpType:32
|vpiOperand:
\_ref_obj: (br_results.branch_taken), line:107
|vpiName:br_results.branch_taken
|vpiFullName:work@branch_predictor.br_results.branch_taken
|vpiOperand:
\_constant: , line:107
|vpiConstType:3
|vpiDecompile:2'b10
|vpiSize:2
|BIN:2'b10
|vpiOperand:
\_constant: , line:107
|vpiConstType:3
|vpiDecompile:2'b00
|vpiSize:2
|BIN:2'b00
|vpiCaseItem:
\_case_item: , line:108
|vpiExpr:
\_constant: , line:108
|vpiConstType:3
|vpiDecompile:2'b10
|vpiSize:2
|BIN:2'b10
|vpiStmt:
\_assignment: , line:108
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (ex_entry.metadata), line:108
|vpiName:ex_entry.metadata
|vpiFullName:work@branch_predictor.ex_entry.metadata
|vpiRhs:
\_operation: , line:108
|vpiOpType:32
|vpiOperand:
\_ref_obj: (br_results.branch_taken), line:108
|vpiName:br_results.branch_taken
|vpiFullName:work@branch_predictor.br_results.branch_taken
|vpiOperand:
\_constant: , line:108
|vpiConstType:3
|vpiDecompile:2'b11
|vpiSize:2
|BIN:2'b11
|vpiOperand:
\_constant: , line:108
|vpiConstType:3
|vpiDecompile:2'b01
|vpiSize:2
|BIN:2'b01
|vpiCaseItem:
\_case_item: , line:109
|vpiExpr:
\_constant: , line:109
|vpiConstType:3
|vpiDecompile:2'b11
|vpiSize:2
|BIN:2'b11
|vpiStmt:
\_assignment: , line:109
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (ex_entry.metadata), line:109
|vpiName:ex_entry.metadata
|vpiFullName:work@branch_predictor.ex_entry.metadata
|vpiRhs:
\_operation: , line:109
|vpiOpType:32
|vpiOperand:
\_ref_obj: (br_results.branch_taken), line:109
|vpiName:br_results.branch_taken
|vpiFullName:work@branch_predictor.br_results.branch_taken
|vpiOperand:
\_constant: , line:109
|vpiConstType:3
|vpiDecompile:2'b11
|vpiSize:2
|BIN:2'b11
|vpiOperand:
\_constant: , line:109
|vpiConstType:3
|vpiDecompile:2'b10
|vpiSize:2
|BIN:2'b10
|vpiStmt:
\_if_stmt: , line:111
|vpiCondition:
\_operation: , line:111
|vpiOpType:4
|vpiOperand:
\_ref_obj: (br_results.branch_prediction_used), line:111
|vpiName:br_results.branch_prediction_used
|vpiFullName:work@branch_predictor.br_results.branch_prediction_used
|vpiStmt:
\_assignment: , line:112
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (ex_entry.metadata), line:112
|vpiName:ex_entry.metadata
|vpiFullName:work@branch_predictor.ex_entry.metadata
|vpiRhs:
\_operation: , line:112
|vpiOpType:32
|vpiOperand:
\_ref_obj: (br_results.branch_taken), line:112
|vpiName:br_results.branch_taken
|vpiFullName:work@branch_predictor.br_results.branch_taken
|vpiOperand:
\_constant: , line:112
|vpiConstType:3
|vpiDecompile:2'b11
|vpiSize:2
|BIN:2'b11
|vpiOperand:
\_constant: , line:112
|vpiConstType:3
|vpiDecompile:2'b00
|vpiSize:2
|BIN:2'b00
|vpiPort:
\_port: (clk), line:27
|vpiName:clk
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (clk), line:27
|vpiName:clk
|vpiFullName:work@branch_predictor.clk
|vpiNetType:36
|vpiPort:
\_port: (rst), line:28
|vpiName:rst
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (rst), line:28
|vpiName:rst
|vpiFullName:work@branch_predictor.rst
|vpiNetType:36
|vpiPort:
\_port: (bp), line:29
|vpiName:bp
|vpiDirection:5
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_modport: (branch_predictor)
|vpiPort:
\_port: (br_results), line:30
|vpiName:br_results
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (br_results), line:30
|vpiName:br_results
|vpiFullName:work@branch_predictor.br_results
|vpiContAssign:
\_cont_assign: , line:89
|vpiRhs:
\_operation: , line:89
|vpiOpType:7
|vpiOperand:
\_ref_obj: (tag_matches), line:89
|vpiName:tag_matches
|vpiFullName:work@branch_predictor.tag_matches
|vpiLhs:
\_ref_obj: (tag_match), line:89
|vpiName:tag_match
|vpiFullName:work@branch_predictor.tag_match
|vpiContAssign:
\_cont_assign: , line:91
|vpiRhs:
\_bit_select: (predicted_pc), line:91
|vpiName:predicted_pc
|vpiFullName:work@branch_predictor.predicted_pc
|vpiIndex:
\_ref_obj: (hit_way), line:91
|vpiName:hit_way
|vpiLhs:
\_ref_obj: (bp.predicted_pc), line:91
|vpiName:bp.predicted_pc
|vpiFullName:work@branch_predictor.bp.predicted_pc
|vpiContAssign:
\_cont_assign: , line:92
|vpiRhs:
\_bit_select: (if_entry.metadata), line:92
|vpiName:if_entry.metadata
|vpiFullName:work@branch_predictor.if_entry.metadata
|vpiIndex:
\_ref_obj: (hit_way), line:92
|vpiName:hit_way
|vpiLhs:
\_ref_obj: (bp.metadata), line:92
|vpiName:bp.metadata
|vpiFullName:work@branch_predictor.bp.metadata
|vpiContAssign:
\_cont_assign: , line:93
|vpiRhs:
\_bit_select: (if_entry.use_ras), line:93
|vpiName:if_entry.use_ras
|vpiFullName:work@branch_predictor.if_entry.use_ras
|vpiIndex:
\_ref_obj: (hit_way), line:93
|vpiName:hit_way
|vpiLhs:
\_ref_obj: (bp.use_ras), line:93
|vpiName:bp.use_ras
|vpiFullName:work@branch_predictor.bp.use_ras
|vpiContAssign:
\_cont_assign: , line:94
|vpiRhs:
\_ref_obj: (tag_matches), line:94
|vpiName:tag_matches
|vpiFullName:work@branch_predictor.tag_matches
|vpiLhs:
\_ref_obj: (bp.update_way), line:94
|vpiName:bp.update_way
|vpiFullName:work@branch_predictor.bp.update_way
|vpiContAssign:
\_cont_assign: , line:97
|vpiRhs:
\_constant: , line:97
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiLhs:
\_ref_obj: (ex_entry.valid), line:97
|vpiName:ex_entry.valid
|vpiFullName:work@branch_predictor.ex_entry.valid
|vpiContAssign:
\_cont_assign: , line:98
|vpiRhs:
\_ref_obj: (br_results.pc_ex), line:98
|vpiName:br_results.pc_ex
|vpiFullName:work@branch_predictor.br_results.pc_ex
|vpiLhs:
\_ref_obj: (ex_entry.tag), line:98
|vpiName:ex_entry.tag
|vpiFullName:work@branch_predictor.ex_entry.tag
|vpiContAssign:
\_cont_assign: , line:99
|vpiRhs:
\_ref_obj: (br_results.is_return_ex), line:99
|vpiName:br_results.is_return_ex
|vpiFullName:work@branch_predictor.br_results.is_return_ex
|vpiLhs:
\_ref_obj: (ex_entry.use_ras), line:99
|vpiName:ex_entry.use_ras
|vpiFullName:work@branch_predictor.ex_entry.use_ras
|vpiContAssign:
\_cont_assign: , line:101
|vpiRhs:
\_operation: , line:101
|vpiOpType:32
|vpiOperand:
\_ref_obj: (ex_entry.metadata), line:101
|vpiName:ex_entry.metadata
|vpiFullName:work@branch_predictor.ex_entry.metadata
|vpiOperand:
\_ref_obj: (br_results.jump_pc), line:101
|vpiName:br_results.jump_pc
|vpiFullName:work@branch_predictor.br_results.jump_pc
|vpiOperand:
\_ref_obj: (br_results.njump_pc), line:101
|vpiName:br_results.njump_pc
|vpiFullName:work@branch_predictor.br_results.njump_pc
|vpiLhs:
\_ref_obj: (new_jump_addr), line:101
|vpiName:new_jump_addr
|vpiFullName:work@branch_predictor.new_jump_addr
|vpiContAssign:
\_cont_assign: , line:115
|vpiRhs:
\_operation: , line:115
|vpiOpType:28
|vpiOperand:
\_operation: , line:115
|vpiOpType:34
|vpiOperand:
\_ref_obj: (BRANCH_PREDICTOR_WAYS), line:115
|vpiName:BRANCH_PREDICTOR_WAYS
|vpiOperand:
\_operation:
|vpiOpType:33
|vpiOperand:
\_ref_obj: (br_results.branch_ex), line:115
|vpiName:br_results.branch_ex
|vpiOperand:
\_operation: , line:115
|vpiOpType:32
|vpiOperand:
\_ref_obj: (br_results.branch_prediction_used), line:115
|vpiName:br_results.branch_prediction_used
|vpiFullName:work@branch_predictor.br_results.branch_prediction_used
|vpiOperand:
\_ref_obj: (br_results.bp_update_way), line:115
|vpiName:br_results.bp_update_way
|vpiFullName:work@branch_predictor.br_results.bp_update_way
|vpiOperand:
\_ref_obj: (replacement_way), line:115
|vpiName:replacement_way
|vpiFullName:work@branch_predictor.replacement_way
|vpiLhs:
\_ref_obj: (update_way), line:115
|vpiName:update_way
|vpiFullName:work@branch_predictor.update_way
|vpiContAssign:
\_cont_assign: , line:117
|vpiRhs:
\_operation: , line:117
|vpiOpType:32
|vpiOperand:
\_ref_obj: (br_results.branch_taken), line:117
|vpiName:br_results.branch_taken
|vpiFullName:work@branch_predictor.br_results.branch_taken
|vpiOperand:
\_ref_obj: (br_results.jump_pc), line:117
|vpiName:br_results.jump_pc
|vpiFullName:work@branch_predictor.br_results.jump_pc
|vpiOperand:
\_ref_obj: (br_results.njump_pc), line:117
|vpiName:br_results.njump_pc
|vpiFullName:work@branch_predictor.br_results.njump_pc
|vpiLhs:
\_ref_obj: (bp.branch_flush_pc), line:117
|vpiName:bp.branch_flush_pc
|vpiFullName:work@branch_predictor.bp.branch_flush_pc
|vpiNet:
\_logic_net: (clk), line:27
|vpiNet:
\_logic_net: (rst), line:28
|vpiNet:
\_logic_net: (br_results), line:30
|vpiNet:
\_logic_net: (if_entry), line:44
|vpiName:if_entry
|vpiFullName:work@branch_predictor.if_entry
|vpiNet:
\_logic_net: (ex_entry), line:45
|vpiName:ex_entry
|vpiFullName:work@branch_predictor.ex_entry
|vpiNet:
\_logic_net: (new_jump_addr), line:47
|vpiName:new_jump_addr
|vpiFullName:work@branch_predictor.new_jump_addr
|vpiNetType:36
|vpiNet:
\_logic_net: (predicted_pc), line:48
|vpiName:predicted_pc
|vpiFullName:work@branch_predictor.predicted_pc
|vpiNetType:36
|vpiNet:
\_logic_net: (tag_matches), line:50
|vpiName:tag_matches
|vpiFullName:work@branch_predictor.tag_matches
|vpiNetType:36
|vpiNet:
\_logic_net: (replacement_way), line:51
|vpiName:replacement_way
|vpiFullName:work@branch_predictor.replacement_way
|vpiNetType:36
|vpiNet:
\_logic_net: (update_way), line:52
|vpiName:update_way
|vpiFullName:work@branch_predictor.update_way
|vpiNetType:36
|vpiNet:
\_logic_net: (hit_way), line:53
|vpiName:hit_way
|vpiFullName:work@branch_predictor.hit_way
|vpiNetType:36
|vpiNet:
\_logic_net: (tag_match), line:54
|vpiName:tag_match
|vpiFullName:work@branch_predictor.tag_match
|vpiNetType:36
|vpiNet:
\_logic_net: (bp), line:29
|vpiName:bp
|vpiFullName:work@branch_predictor.bp
|vpiTypedef:
\_struct_typespec: (alu_inputs_t), line:301
|vpiTypedef:
\_enum_typespec: (alu_logic_op_t), line:84
|vpiTypedef:
\_enum_typespec: (alu_op_t), line:91
|vpiTypedef:
\_enum_typespec: (alu_rs1_op_t), line:97
|vpiTypedef:
\_enum_typespec: (alu_rs2_op_t), line:104
|vpiTypedef:
\_struct_typespec: (amo_alu_inputs_t), line:356
|vpiTypedef:
\_struct_typespec: (amo_details_t), line:362
|vpiTypedef:
\_enum_typespec: (amo_t), line:354
|vpiTypedef:
\_struct_typespec: (branch_inputs_t), line:313
|vpiTypedef:
\_logic_typespec: (branch_predictor_metadata_t), line:32
|vpiTypedef:
\_struct_typespec: (branch_results_t), line:330
|vpiTypedef:
\_struct_typespec: (branch_table_entry_t), line:36
|vpiPacked:1
|vpiName:branch_table_entry_t
|vpiTypespecMember:
\_typespec_member: (valid), line:37
|vpiName:valid
|vpiTypespec:
\_logic_typespec: , line:37
|vpiTypespecMember:
\_typespec_member: (tag), line:38
|vpiName:tag
|vpiTypespec:
\_logic_typespec: , line:38
|vpiRange:
\_range: , line:38, parent:branch_table_entry_t
|vpiLeftRange:
\_operation: , line:38
|vpiOpType:11
|vpiOperand:
\_operation: , line:38
|vpiOpType:11
|vpiOperand:
\_constant: , line:34
|vpiConstType:7
|vpiDecompile:30
|vpiSize:32
|INT:30
|vpiOperand:
\_sys_func_call: ($clog2), line:34
|vpiName:$clog2
|vpiArgument:
\_ref_obj: (BRANCH_TABLE_ENTRIES), line:33
|vpiName:BRANCH_TABLE_ENTRIES
|vpiOperand:
\_constant: , line:38
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:38
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiTypespecMember:
\_typespec_member: (use_ras), line:39
|vpiName:use_ras
|vpiTypespec:
\_logic_typespec: , line:39
|vpiTypespecMember:
\_typespec_member: (metadata), line:40
|vpiName:metadata
|vpiTypespec:
\_logic_typespec: (branch_predictor_metadata_t), line:32
|vpiTypedef:
\_enum_typespec: (bus_type_t), line:86
|vpiTypedef:
\_struct_typespec: (csr_inputs_t), line:396
|vpiTypedef:
\_enum_typespec: (csr_op_t), line:218
|vpiTypedef:
\_enum_typespec: (csr_t), line:201
|vpiTypedef:
\_struct_typespec: (data_access_shared_inputs_t), line:427
|vpiTypedef:
\_struct_typespec: (div_inputs_t), line:389
|vpiTypedef:
\_enum_typespec: (div_type), line:66
|vpiTypedef:
\_enum_typespec: (exception_code_t), line:245
|vpiTypedef:
\_struct_typespec: (exception_packet_t), line:263
|vpiTypedef:
\_struct_typespec: (fetch_buffer_packet_t), line:276
|vpiTypedef:
\_enum_typespec: (fifo_type_t), line:440
|vpiTypedef:
\_enum_typespec: (fn3_arith_t), line:76
|vpiTypedef:
\_enum_typespec: (fn3_branch_t), line:126
|vpiTypedef:
\_enum_typespec: (fn3_csr_t), line:212
|vpiTypedef:
\_enum_typespec: (fn3_ls_t), line:115
|vpiTypedef:
\_enum_typespec: (fn3_mul_div_t), line:138
|vpiTypedef:
\_struct_typespec: (gc_inputs_t), line:404
|vpiTypedef:
\_struct_typespec: (inflight_instruction_packet), line:271
|vpiTypedef:
\_logic_typespec: (instruction_id_t), line:30
|vpiTypedef:
\_enum_typespec: (interrupt_code_t), line:261
|vpiTypedef:
\_struct_typespec: (load_store_inputs_t), line:369
|vpiTypedef:
\_struct_typespec: (mul_inputs_t), line:383
|vpiTypedef:
\_enum_typespec: (opcodes_t), line:48
|vpiTypedef:
\_enum_typespec: (opcodes_trimmed_t), line:65
|vpiTypedef:
\_struct_typespec: (simulation_named_regfile), line:476
|vpiTypedef:
\_struct_typespec: (taiga_trace_events_t), line:442
|vpiTypedef:
\_struct_typespec: (to_l1_arbiter_packet), line:418
|vpiTypedef:
\_struct_typespec: (trace_outputs_t), line:469
|vpiTypedef:
\_logic_typespec: (unit_id_t), line:31
|vpiTypedef:
\_struct_typespec: (unit_writeback_t), line:295
|vpiTypedef:
\_enum_typespec: (vm_t), line:223
|vpiParamAssign:
\_param_assign: , line:33
|vpiRhs:
\_sys_func_call: ($clog2), line:33
|vpiName:$clog2
|vpiArgument:
\_ref_obj: (BRANCH_TABLE_ENTRIES), line:33
|vpiName:BRANCH_TABLE_ENTRIES
|vpiLhs:
\_parameter: (BRANCH_ADDR_W), line:33
|vpiName:BRANCH_ADDR_W
|vpiParamAssign:
\_param_assign: , line:34
|vpiRhs:
\_operation: , line:34
|vpiOpType:11
|vpiOperand:
\_constant: , line:34
|vpiConstType:7
|vpiDecompile:30
|vpiSize:32
|INT:30
|vpiOperand:
\_sys_func_call: ($clog2), line:34
|vpiName:$clog2
|vpiArgument:
\_ref_obj: (BRANCH_TABLE_ENTRIES), line:33
|vpiName:BRANCH_TABLE_ENTRIES
|vpiLhs:
\_parameter: (BTAG_W), line:34
|vpiName:BTAG_W
|vpiParameter:
\_parameter: (BRANCH_ADDR_W), line:33
|vpiParameter:
\_parameter: (BTAG_W), line:34
|uhdmallModules:
\_module: work@branch_predictor_ram, file:third_party/cores/taiga/core/branch_predictor_ram.sv, line:26, parent:work@div_unit_core_wrapper
|vpiDefName:work@branch_predictor_ram
|vpiFullName:work@branch_predictor_ram
|vpiProcess:
\_initial:
|vpiStmt:
\_begin: , line:43
|vpiFullName:work@branch_predictor_ram
|vpiStmt:
\_foreach_stmt: , line:44
|vpiFullName:work@branch_predictor_ram
|vpiVariables:
\_chandle_var: (branch_ram), line:44
|vpiName:branch_ram
|vpiFullName:work@branch_predictor_ram.branch_ram
|vpiLoopVars:
\_chandle_var: (i), line:44
|vpiName:i
|vpiFullName:work@branch_predictor_ram.i
|vpiStmt:
\_assignment: , line:45
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_bit_select: (branch_ram), line:45
|vpiName:branch_ram
|vpiFullName:work@branch_predictor_ram.branch_ram
|vpiIndex:
\_ref_obj: (i), line:45
|vpiName:i
|vpiRhs:
\_constant: , line:45
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiProcess:
\_always: , line:48
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:48
|vpiCondition:
\_operation: , line:48
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:48
|vpiName:clk
|vpiFullName:work@branch_predictor_ram.clk
|vpiStmt:
\_begin: , line:48
|vpiFullName:work@branch_predictor_ram
|vpiStmt:
\_if_stmt: , line:49
|vpiCondition:
\_ref_obj: (write_en), line:49
|vpiName:write_en
|vpiFullName:work@branch_predictor_ram.write_en
|vpiStmt:
\_assignment: , line:50
|vpiOpType:82
|vpiLhs:
\_bit_select: (branch_ram), line:50
|vpiName:branch_ram
|vpiFullName:work@branch_predictor_ram.branch_ram
|vpiIndex:
\_ref_obj: (write_addr), line:50
|vpiName:write_addr
|vpiRhs:
\_ref_obj: (write_data), line:50
|vpiName:write_data
|vpiFullName:work@branch_predictor_ram.write_data
|vpiProcess:
\_always: , line:53
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:53
|vpiCondition:
\_operation: , line:53
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:53
|vpiName:clk
|vpiFullName:work@branch_predictor_ram.clk
|vpiStmt:
\_begin: , line:53
|vpiFullName:work@branch_predictor_ram
|vpiStmt:
\_if_stmt: , line:54
|vpiCondition:
\_ref_obj: (read_en), line:54
|vpiName:read_en
|vpiFullName:work@branch_predictor_ram.read_en
|vpiStmt:
\_assignment: , line:55
|vpiOpType:82
|vpiLhs:
\_ref_obj: (read_data), line:55
|vpiName:read_data
|vpiFullName:work@branch_predictor_ram.read_data
|vpiRhs:
\_bit_select: (branch_ram), line:55
|vpiName:branch_ram
|vpiFullName:work@branch_predictor_ram.branch_ram
|vpiIndex:
\_ref_obj: (read_addr), line:55
|vpiName:read_addr
|vpiPort:
\_port: (clk), line:32
|vpiName:clk
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (clk), line:32
|vpiName:clk
|vpiFullName:work@branch_predictor_ram.clk
|vpiNetType:36
|vpiPort:
\_port: (write_addr), line:33
|vpiName:write_addr
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (write_addr), line:33
|vpiName:write_addr
|vpiFullName:work@branch_predictor_ram.write_addr
|vpiNetType:36
|vpiPort:
\_port: (write_en), line:34
|vpiName:write_en
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (write_en), line:34
|vpiName:write_en
|vpiFullName:work@branch_predictor_ram.write_en
|vpiNetType:36
|vpiPort:
\_port: (read_addr), line:35
|vpiName:read_addr
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (read_addr), line:35
|vpiName:read_addr
|vpiFullName:work@branch_predictor_ram.read_addr
|vpiNetType:36
|vpiPort:
\_port: (read_en), line:36
|vpiName:read_en
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (read_en), line:36
|vpiName:read_en
|vpiFullName:work@branch_predictor_ram.read_en
|vpiNetType:36
|vpiPort:
\_port: (write_data), line:37
|vpiName:write_data
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (write_data), line:37
|vpiName:write_data
|vpiFullName:work@branch_predictor_ram.write_data
|vpiNetType:36
|vpiPort:
\_port: (read_data), line:38
|vpiName:read_data
|vpiDirection:2
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (read_data), line:38
|vpiName:read_data
|vpiFullName:work@branch_predictor_ram.read_data
|vpiNetType:36
|vpiNet:
\_logic_net: (clk), line:32
|vpiNet:
\_logic_net: (write_addr), line:33
|vpiNet:
\_logic_net: (write_en), line:34
|vpiNet:
\_logic_net: (read_addr), line:35
|vpiNet:
\_logic_net: (read_en), line:36
|vpiNet:
\_logic_net: (write_data), line:37
|vpiNet:
\_logic_net: (read_data), line:38
|vpiNet:
\_logic_net: (branch_ram), line:40
|vpiName:branch_ram
|vpiFullName:work@branch_predictor_ram.branch_ram
|vpiNetType:36
|vpiTypedef:
\_struct_typespec: (alu_inputs_t), line:301
|vpiTypedef:
\_enum_typespec: (alu_logic_op_t), line:84
|vpiTypedef:
\_enum_typespec: (alu_op_t), line:91
|vpiTypedef:
\_enum_typespec: (alu_rs1_op_t), line:97
|vpiTypedef:
\_enum_typespec: (alu_rs2_op_t), line:104
|vpiTypedef:
\_struct_typespec: (amo_alu_inputs_t), line:356
|vpiTypedef:
\_struct_typespec: (amo_details_t), line:362
|vpiTypedef:
\_enum_typespec: (amo_t), line:354
|vpiTypedef:
\_struct_typespec: (branch_inputs_t), line:313
|vpiTypedef:
\_logic_typespec: (branch_predictor_metadata_t), line:32
|vpiTypedef:
\_struct_typespec: (branch_results_t), line:330
|vpiTypedef:
\_enum_typespec: (bus_type_t), line:86
|vpiTypedef:
\_struct_typespec: (csr_inputs_t), line:396
|vpiTypedef:
\_enum_typespec: (csr_op_t), line:218
|vpiTypedef:
\_enum_typespec: (csr_t), line:201
|vpiTypedef:
\_struct_typespec: (data_access_shared_inputs_t), line:427
|vpiTypedef:
\_struct_typespec: (div_inputs_t), line:389
|vpiTypedef:
\_enum_typespec: (div_type), line:66
|vpiTypedef:
\_enum_typespec: (exception_code_t), line:245
|vpiTypedef:
\_struct_typespec: (exception_packet_t), line:263
|vpiTypedef:
\_struct_typespec: (fetch_buffer_packet_t), line:276
|vpiTypedef:
\_enum_typespec: (fifo_type_t), line:440
|vpiTypedef:
\_enum_typespec: (fn3_arith_t), line:76
|vpiTypedef:
\_enum_typespec: (fn3_branch_t), line:126
|vpiTypedef:
\_enum_typespec: (fn3_csr_t), line:212
|vpiTypedef:
\_enum_typespec: (fn3_ls_t), line:115
|vpiTypedef:
\_enum_typespec: (fn3_mul_div_t), line:138
|vpiTypedef:
\_struct_typespec: (gc_inputs_t), line:404
|vpiTypedef:
\_struct_typespec: (inflight_instruction_packet), line:271
|vpiTypedef:
\_logic_typespec: (instruction_id_t), line:30
|vpiTypedef:
\_enum_typespec: (interrupt_code_t), line:261
|vpiTypedef:
\_struct_typespec: (load_store_inputs_t), line:369
|vpiTypedef:
\_struct_typespec: (mul_inputs_t), line:383
|vpiTypedef:
\_enum_typespec: (opcodes_t), line:48
|vpiTypedef:
\_enum_typespec: (opcodes_trimmed_t), line:65
|vpiTypedef:
\_struct_typespec: (simulation_named_regfile), line:476
|vpiTypedef:
\_struct_typespec: (taiga_trace_events_t), line:442
|vpiTypedef:
\_struct_typespec: (to_l1_arbiter_packet), line:418
|vpiTypedef:
\_struct_typespec: (trace_outputs_t), line:469
|vpiTypedef:
\_logic_typespec: (unit_id_t), line:31
|vpiTypedef:
\_struct_typespec: (unit_writeback_t), line:295
|vpiTypedef:
\_enum_typespec: (vm_t), line:223
|vpiParamAssign:
\_param_assign: , line:28
|vpiRhs:
\_constant: , line:28
|vpiConstType:7
|vpiDecompile:20
|vpiSize:32
|INT:20
|vpiLhs:
\_parameter: (C_DATA_WIDTH), line:28
|vpiName:C_DATA_WIDTH
|vpiParamAssign:
\_param_assign: , line:29
|vpiRhs:
\_constant: , line:29
|vpiConstType:7
|vpiDecompile:512
|vpiSize:32
|INT:512
|vpiLhs:
\_parameter: (C_DEPTH), line:29
|vpiName:C_DEPTH
|vpiParameter:
\_parameter: (C_DATA_WIDTH), line:28
|vpiParameter:
\_parameter: (C_DEPTH), line:29
|uhdmallModules:
\_module: work@branch_unit, file:third_party/cores/taiga/core/branch_unit.sv, line:26, parent:work@div_unit_core_wrapper
|vpiDefName:work@branch_unit
|vpiFullName:work@branch_unit
|vpiProcess:
\_always: , line:85
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:85
|vpiCondition:
\_operation: , line:85
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:85
|vpiName:clk
|vpiFullName:work@branch_unit.clk
|vpiStmt:
\_begin: , line:85
|vpiFullName:work@branch_unit
|vpiStmt:
\_if_else: , line:86
|vpiCondition:
\_ref_obj: (rst), line:86
|vpiName:rst
|vpiFullName:work@branch_unit.rst
|vpiStmt:
\_assignment: , line:87
|vpiOpType:82
|vpiLhs:
\_ref_obj: (branch_issued_r), line:87
|vpiName:branch_issued_r
|vpiFullName:work@branch_unit.branch_issued_r
|vpiRhs:
\_constant: , line:87
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiElseStmt:
\_if_else: , line:88
|vpiCondition:
\_ref_obj: (issue.new_request), line:88
|vpiName:issue.new_request
|vpiFullName:work@branch_unit.issue.new_request
|vpiStmt:
\_assignment: , line:89
|vpiOpType:82
|vpiLhs:
\_ref_obj: (branch_issued_r), line:89
|vpiName:branch_issued_r
|vpiFullName:work@branch_unit.branch_issued_r
|vpiRhs:
\_constant: , line:89
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiElseStmt:
\_if_stmt: , line:90
|vpiCondition:
\_ref_obj: (branch_inputs.dec_pc_valid), line:90
|vpiName:branch_inputs.dec_pc_valid
|vpiFullName:work@branch_unit.branch_inputs.dec_pc_valid
|vpiStmt:
\_assignment: , line:91
|vpiOpType:82
|vpiLhs:
\_ref_obj: (branch_issued_r), line:91
|vpiName:branch_issued_r
|vpiFullName:work@branch_unit.branch_issued_r
|vpiRhs:
\_constant: , line:91
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiProcess:
\_always: , line:110
|vpiAlwaysType:2
|vpiStmt:
\_begin: , line:110
|vpiFullName:work@branch_unit
|vpiStmt:
\_if_else: , line:111
|vpiCondition:
\_unsupported_expr: , line:111
|STRING: unique if (branch_inputs.jalr)
|vpiStmt:
\_if_else: , line:111
|vpiCondition:
\_ref_obj: (branch_inputs.jalr), line:111
|vpiName:branch_inputs.jalr
|vpiFullName:work@branch_unit.branch_inputs.jalr
|vpiStmt:
\_assignment: , line:112
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (pc_offset), line:112
|vpiName:pc_offset
|vpiFullName:work@branch_unit.pc_offset
|vpiRhs:
\_operation: , line:112
|vpiOpType:67
|vpiOperand:
\_operation: , line:112
|vpiOpType:67
|vpiOperand:
\_ref_obj: (jalr_imm), line:112
|vpiName:jalr_imm
|vpiTypespec:
\_integer_typespec: , line:112
|INT:32
|vpiElseStmt:
\_if_else: , line:113
|vpiCondition:
\_ref_obj: (branch_inputs.jal), line:113
|vpiName:branch_inputs.jal
|vpiFullName:work@branch_unit.branch_inputs.jal
|vpiStmt:
\_assignment: , line:114
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (pc_offset), line:114
|vpiName:pc_offset
|vpiFullName:work@branch_unit.pc_offset
|vpiRhs:
\_operation: , line:114
|vpiOpType:67
|vpiOperand:
\_operation: , line:114
|vpiOpType:67
|vpiOperand:
\_operation: , line:114
|vpiOpType:33
|vpiOperand:
\_ref_obj: (jal_imm), line:114
|vpiName:jal_imm
|vpiOperand:
\_constant: , line:114
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiTypespec:
\_integer_typespec: , line:114
|INT:32
|vpiElseStmt:
\_assignment: , line:116
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (pc_offset), line:116
|vpiName:pc_offset
|vpiFullName:work@branch_unit.pc_offset
|vpiRhs:
\_operation: , line:116
|vpiOpType:67
|vpiOperand:
\_operation: , line:116
|vpiOpType:67
|vpiOperand:
\_operation: , line:116
|vpiOpType:33
|vpiOperand:
\_ref_obj: (br_imm), line:116
|vpiName:br_imm
|vpiOperand:
\_constant: , line:116
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiTypespec:
\_integer_typespec: , line:116
|INT:32
|vpiElseStmt:
\_assignment: , line:112
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (pc_offset), line:112
|vpiName:pc_offset
|vpiFullName:work@branch_unit.pc_offset
|vpiRhs:
\_operation: , line:112
|vpiOpType:67
|vpiOperand:
\_operation: , line:112
|vpiOpType:67
|vpiOperand:
\_ref_obj: (jalr_imm), line:112
|vpiName:jalr_imm
|vpiTypespec:
\_integer_typespec: , line:112
|INT:32
|vpiProcess:
\_always: , line:119
|vpiAlwaysType:2
|vpiStmt:
\_begin: , line:119
|vpiFullName:work@branch_unit
|vpiStmt:
\_if_else: , line:120
|vpiCondition:
\_ref_obj: (branch_inputs.jalr), line:120
|vpiName:branch_inputs.jalr
|vpiFullName:work@branch_unit.branch_inputs.jalr
|vpiStmt:
\_assignment: , line:121
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (jump_base), line:121
|vpiName:jump_base
|vpiFullName:work@branch_unit.jump_base
|vpiRhs:
\_ref_obj: (branch_inputs.rs1), line:121
|vpiName:branch_inputs.rs1
|vpiFullName:work@branch_unit.branch_inputs.rs1
|vpiElseStmt:
\_assignment: , line:123
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (jump_base), line:123
|vpiName:jump_base
|vpiFullName:work@branch_unit.jump_base
|vpiRhs:
\_ref_obj: (branch_inputs.dec_pc), line:123
|vpiName:branch_inputs.dec_pc
|vpiFullName:work@branch_unit.branch_inputs.dec_pc
|vpiProcess:
\_always: , line:128
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:128
|vpiCondition:
\_operation: , line:128
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:128
|vpiName:clk
|vpiFullName:work@branch_unit.clk
|vpiStmt:
\_begin: , line:128
|vpiFullName:work@branch_unit
|vpiStmt:
\_if_stmt: , line:129
|vpiCondition:
\_operation: , line:129
|vpiOpType:29
|vpiOperand:
\_ref_obj: (instruction_is_completing), line:129
|vpiName:instruction_is_completing
|vpiFullName:work@branch_unit.instruction_is_completing
|vpiOperand:
\_operation: , line:129
|vpiOpType:4
|vpiOperand:
\_ref_obj: (branch_issued_r), line:129
|vpiName:branch_issued_r
|vpiFullName:work@branch_unit.branch_issued_r
|vpiStmt:
\_begin: , line:129
|vpiFullName:work@branch_unit
|vpiStmt:
\_assignment: , line:130
|vpiOpType:82
|vpiLhs:
\_ref_obj: (fn3_ex), line:130
|vpiName:fn3_ex
|vpiFullName:work@branch_unit.fn3_ex
|vpiRhs:
\_ref_obj: (branch_inputs.fn3), line:130
|vpiName:branch_inputs.fn3
|vpiFullName:work@branch_unit.branch_inputs.fn3
|vpiStmt:
\_assignment: , line:131
|vpiOpType:82
|vpiLhs:
\_ref_obj: (result_ex), line:131
|vpiName:result_ex
|vpiFullName:work@branch_unit.result_ex
|vpiRhs:
\_ref_obj: (result), line:131
|vpiName:result
|vpiFullName:work@branch_unit.result
|vpiStmt:
\_assignment: , line:132
|vpiOpType:82
|vpiLhs:
\_ref_obj: (jump_ex), line:132
|vpiName:jump_ex
|vpiFullName:work@branch_unit.jump_ex
|vpiRhs:
\_operation: , line:132
|vpiOpType:29
|vpiOperand:
\_ref_obj: (branch_inputs.jal), line:132
|vpiName:branch_inputs.jal
|vpiFullName:work@branch_unit.branch_inputs.jal
|vpiOperand:
\_ref_obj: (branch_inputs.jalr), line:132
|vpiName:branch_inputs.jalr
|vpiFullName:work@branch_unit.branch_inputs.jalr
|vpiProcess:
\_always: , line:138
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:138
|vpiCondition:
\_operation: , line:138
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:138
|vpiName:clk
|vpiFullName:work@branch_unit.clk
|vpiStmt:
\_begin: , line:138
|vpiFullName:work@branch_unit
|vpiStmt:
\_if_stmt: , line:139
|vpiCondition:
\_operation: , line:139
|vpiOpType:29
|vpiOperand:
\_ref_obj: (instruction_is_completing), line:139
|vpiName:instruction_is_completing
|vpiFullName:work@branch_unit.instruction_is_completing
|vpiOperand:
\_operation: , line:139
|vpiOpType:4
|vpiOperand:
\_ref_obj: (branch_issued_r), line:139
|vpiName:branch_issued_r
|vpiFullName:work@branch_unit.branch_issued_r
|vpiStmt:
\_begin: , line:139
|vpiFullName:work@branch_unit
|vpiStmt:
\_assignment: , line:140
|vpiOpType:82
|vpiLhs:
\_ref_obj: (pc_ex), line:140
|vpiName:pc_ex
|vpiFullName:work@branch_unit.pc_ex
|vpiRhs:
\_ref_obj: (branch_inputs.dec_pc), line:140
|vpiName:branch_inputs.dec_pc
|vpiFullName:work@branch_unit.branch_inputs.dec_pc
|vpiStmt:
\_assignment: , line:141
|vpiOpType:82
|vpiLhs:
\_ref_obj: (jump_pc), line:141
|vpiName:jump_pc
|vpiFullName:work@branch_unit.jump_pc
|vpiRhs:
\_operation: , line:141
|vpiOpType:33
|vpiOperand:
\_part_select: , line:141, parent:jump_pc_dec
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (jump_pc_dec)
|vpiLeftRange:
\_constant: , line:141
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:141
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiOperand:
\_constant: , line:141
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiStmt:
\_assignment: , line:142
|vpiOpType:82
|vpiLhs:
\_ref_obj: (njump_pc), line:142
|vpiName:njump_pc
|vpiFullName:work@branch_unit.njump_pc
|vpiRhs:
\_operation: , line:142
|vpiOpType:24
|vpiOperand:
\_ref_obj: (branch_inputs.dec_pc), line:142
|vpiName:branch_inputs.dec_pc
|vpiFullName:work@branch_unit.branch_inputs.dec_pc
|vpiOperand:
\_constant: , line:142
|vpiConstType:7
|vpiDecompile:4
|vpiSize:32
|INT:4
|vpiStmt:
\_assignment: , line:143
|vpiOpType:82
|vpiLhs:
\_ref_obj: (branch_metadata), line:143
|vpiName:branch_metadata
|vpiFullName:work@branch_unit.branch_metadata
|vpiRhs:
\_ref_obj: (branch_inputs.branch_metadata), line:143
|vpiName:branch_inputs.branch_metadata
|vpiFullName:work@branch_unit.branch_inputs.branch_metadata
|vpiStmt:
\_assignment: , line:144
|vpiOpType:82
|vpiLhs:
\_ref_obj: (branch_prediction_used), line:144
|vpiName:branch_prediction_used
|vpiFullName:work@branch_unit.branch_prediction_used
|vpiRhs:
\_ref_obj: (branch_inputs.branch_prediction_used), line:144
|vpiName:branch_inputs.branch_prediction_used
|vpiFullName:work@branch_unit.branch_inputs.branch_prediction_used
|vpiStmt:
\_assignment: , line:145
|vpiOpType:82
|vpiLhs:
\_ref_obj: (bp_update_way), line:145
|vpiName:bp_update_way
|vpiFullName:work@branch_unit.bp_update_way
|vpiRhs:
\_ref_obj: (branch_inputs.bp_update_way), line:145
|vpiName:branch_inputs.bp_update_way
|vpiFullName:work@branch_unit.branch_inputs.bp_update_way
|vpiPort:
\_port: (clk), line:27
|vpiName:clk
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (clk), line:27
|vpiName:clk
|vpiFullName:work@branch_unit.clk
|vpiNetType:36
|vpiPort:
\_port: (rst), line:28
|vpiName:rst
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (rst), line:28
|vpiName:rst
|vpiFullName:work@branch_unit.rst
|vpiNetType:36
|vpiPort:
\_port: (issue), line:30
|vpiName:issue
|vpiDirection:5
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_modport: (unit)
|vpiPort:
\_port: (branch_inputs), line:31
|vpiName:branch_inputs
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (branch_inputs), line:31
|vpiName:branch_inputs
|vpiFullName:work@branch_unit.branch_inputs
|vpiPort:
\_port: (br_results), line:32
|vpiName:br_results
|vpiDirection:2
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (br_results), line:32
|vpiName:br_results
|vpiFullName:work@branch_unit.br_results
|vpiPort:
\_port: (ras), line:33
|vpiName:ras
|vpiDirection:5
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_modport: (branch_unit)
|vpiPort:
\_port: (branch_flush), line:34
|vpiName:branch_flush
|vpiDirection:2
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (branch_flush), line:34
|vpiName:branch_flush
|vpiFullName:work@branch_unit.branch_flush
|vpiPort:
\_port: (tr_branch_correct), line:37
|vpiName:tr_branch_correct
|vpiDirection:2
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (tr_branch_correct), line:37
|vpiName:tr_branch_correct
|vpiFullName:work@branch_unit.tr_branch_correct
|vpiNetType:36
|vpiPort:
\_port: (tr_branch_misspredict), line:38
|vpiName:tr_branch_misspredict
|vpiDirection:2
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (tr_branch_misspredict), line:38
|vpiName:tr_branch_misspredict
|vpiFullName:work@branch_unit.tr_branch_misspredict
|vpiNetType:36
|vpiPort:
\_port: (tr_return_misspredict), line:39
|vpiName:tr_return_misspredict
|vpiDirection:2
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (tr_return_misspredict), line:39
|vpiName:tr_return_misspredict
|vpiFullName:work@branch_unit.tr_return_misspredict
|vpiNetType:36
|vpiContAssign:
\_cont_assign: , line:82
|vpiRhs:
\_constant: , line:82
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiLhs:
\_ref_obj: (issue.ready), line:82
|vpiName:issue.ready
|vpiFullName:work@branch_unit.issue.ready
|vpiContAssign:
\_cont_assign: , line:94
|vpiRhs:
\_operation: , line:94
|vpiOpType:28
|vpiOperand:
\_ref_obj: (branch_issued_r), line:94
|vpiName:branch_issued_r
|vpiFullName:work@branch_unit.branch_issued_r
|vpiOperand:
\_ref_obj: (branch_inputs.dec_pc_valid), line:94
|vpiName:branch_inputs.dec_pc_valid
|vpiFullName:work@branch_unit.branch_inputs.dec_pc_valid
|vpiLhs:
\_ref_obj: (instruction_is_completing), line:94
|vpiName:instruction_is_completing
|vpiFullName:work@branch_unit.instruction_is_completing
|vpiContAssign:
\_cont_assign: , line:104
|vpiRhs:
\_operation: , line:104
|vpiOpType:29
|vpiOperand:
\_operation: , line:104
|vpiOpType:28
|vpiOperand:
\_operation: , line:104
|vpiOpType:4
|vpiOperand:
\_ref_obj: (jump_ex), line:104
|vpiName:jump_ex
|vpiFullName:work@branch_unit.jump_ex
|vpiOperand:
\_operation: , line:104
|vpiOpType:30
|vpiOperand:
\_ref_obj: (result_ex), line:104
|vpiName:result_ex
|vpiFullName:work@branch_unit.result_ex
|vpiOperand:
\_bit_select: (fn3_ex), line:104
|vpiName:fn3_ex
|vpiFullName:work@branch_unit.fn3_ex
|vpiIndex:
\_constant: , line:104
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiOperand:
\_ref_obj: (jump_ex), line:104
|vpiName:jump_ex
|vpiFullName:work@branch_unit.jump_ex
|vpiLhs:
\_ref_obj: (branch_taken), line:104
|vpiName:branch_taken
|vpiFullName:work@branch_unit.branch_taken
|vpiContAssign:
\_cont_assign: , line:106
|vpiRhs:
\_operation: , line:106
|vpiOpType:33
|vpiOperand:
\_ref_obj: (branch_inputs.instruction), line:106
|vpiName:branch_inputs.instruction
|vpiOperand:
\_ref_obj: (branch_inputs.instruction), line:106
|vpiName:branch_inputs.instruction
|vpiOperand:
\_ref_obj: (branch_inputs.instruction), line:106
|vpiName:branch_inputs.instruction
|vpiOperand:
\_ref_obj: (branch_inputs.instruction), line:106
|vpiName:branch_inputs.instruction
|vpiLhs:
\_ref_obj: (jal_imm), line:106
|vpiName:jal_imm
|vpiFullName:work@branch_unit.jal_imm
|vpiContAssign:
\_cont_assign: , line:107
|vpiRhs:
\_ref_obj: (branch_inputs.instruction), line:107
|vpiName:branch_inputs.instruction
|vpiFullName:work@branch_unit.branch_inputs.instruction
|vpiLhs:
\_ref_obj: (jalr_imm), line:107
|vpiName:jalr_imm
|vpiFullName:work@branch_unit.jalr_imm
|vpiContAssign:
\_cont_assign: , line:108
|vpiRhs:
\_operation: , line:108
|vpiOpType:33
|vpiOperand:
\_ref_obj: (branch_inputs.instruction), line:108
|vpiName:branch_inputs.instruction
|vpiOperand:
\_ref_obj: (branch_inputs.instruction), line:108
|vpiName:branch_inputs.instruction
|vpiOperand:
\_ref_obj: (branch_inputs.instruction), line:108
|vpiName:branch_inputs.instruction
|vpiOperand:
\_ref_obj: (branch_inputs.instruction), line:108
|vpiName:branch_inputs.instruction
|vpiLhs:
\_ref_obj: (br_imm), line:108
|vpiName:br_imm
|vpiFullName:work@branch_unit.br_imm
|vpiContAssign:
\_cont_assign: , line:126
|vpiRhs:
\_operation: , line:126
|vpiOpType:24
|vpiOperand:
\_ref_obj: (jump_base), line:126
|vpiName:jump_base
|vpiFullName:work@branch_unit.jump_base
|vpiOperand:
\_ref_obj: (pc_offset), line:126
|vpiName:pc_offset
|vpiFullName:work@branch_unit.pc_offset
|vpiLhs:
\_ref_obj: (jump_pc_dec), line:126
|vpiName:jump_pc_dec
|vpiFullName:work@branch_unit.jump_pc_dec
|vpiContAssign:
\_cont_assign: , line:149
|vpiRhs:
\_ref_obj: (pc_ex), line:149
|vpiName:pc_ex
|vpiFullName:work@branch_unit.pc_ex
|vpiLhs:
\_ref_obj: (br_results.pc_ex), line:149
|vpiName:br_results.pc_ex
|vpiFullName:work@branch_unit.br_results.pc_ex
|vpiContAssign:
\_cont_assign: , line:150
|vpiRhs:
\_ref_obj: (jump_pc), line:150
|vpiName:jump_pc
|vpiFullName:work@branch_unit.jump_pc
|vpiLhs:
\_ref_obj: (br_results.jump_pc), line:150
|vpiName:br_results.jump_pc
|vpiFullName:work@branch_unit.br_results.jump_pc
|vpiContAssign:
\_cont_assign: , line:151
|vpiRhs:
\_ref_obj: (njump_pc), line:151
|vpiName:njump_pc
|vpiFullName:work@branch_unit.njump_pc
|vpiLhs:
\_ref_obj: (br_results.njump_pc), line:151
|vpiName:br_results.njump_pc
|vpiFullName:work@branch_unit.br_results.njump_pc
|vpiContAssign:
\_cont_assign: , line:152
|vpiRhs:
\_ref_obj: (branch_metadata), line:152
|vpiName:branch_metadata
|vpiFullName:work@branch_unit.branch_metadata
|vpiLhs:
\_ref_obj: (br_results.branch_ex_metadata), line:152
|vpiName:br_results.branch_ex_metadata
|vpiFullName:work@branch_unit.br_results.branch_ex_metadata
|vpiContAssign:
\_cont_assign: , line:154
|vpiRhs:
\_ref_obj: (branch_taken), line:154
|vpiName:branch_taken
|vpiFullName:work@branch_unit.branch_taken
|vpiLhs:
\_ref_obj: (br_results.branch_taken), line:154
|vpiName:br_results.branch_taken
|vpiFullName:work@branch_unit.br_results.branch_taken
|vpiContAssign:
\_cont_assign: , line:155
|vpiRhs:
\_ref_obj: (instruction_is_completing), line:155
|vpiName:instruction_is_completing
|vpiFullName:work@branch_unit.instruction_is_completing
|vpiLhs:
\_ref_obj: (br_results.branch_ex), line:155
|vpiName:br_results.branch_ex
|vpiFullName:work@branch_unit.br_results.branch_ex
|vpiContAssign:
\_cont_assign: , line:156
|vpiRhs:
\_ref_obj: (is_return), line:156
|vpiName:is_return
|vpiFullName:work@branch_unit.is_return
|vpiLhs:
\_ref_obj: (br_results.is_return_ex), line:156
|vpiName:br_results.is_return_ex
|vpiFullName:work@branch_unit.br_results.is_return_ex
|vpiContAssign:
\_cont_assign: , line:157
|vpiRhs:
\_ref_obj: (branch_prediction_used), line:157
|vpiName:branch_prediction_used
|vpiFullName:work@branch_unit.branch_prediction_used
|vpiLhs:
\_ref_obj: (br_results.branch_prediction_used), line:157
|vpiName:br_results.branch_prediction_used
|vpiFullName:work@branch_unit.br_results.branch_prediction_used
|vpiContAssign:
\_cont_assign: , line:158
|vpiRhs:
\_ref_obj: (bp_update_way), line:158
|vpiName:bp_update_way
|vpiFullName:work@branch_unit.bp_update_way
|vpiLhs:
\_ref_obj: (br_results.bp_update_way), line:158
|vpiName:br_results.bp_update_way
|vpiFullName:work@branch_unit.br_results.bp_update_way
|vpiContAssign:
\_cont_assign: , line:161
|vpiRhs:
\_operation: , line:161
|vpiOpType:14
|vpiOperand:
\_operation: , line:161
|vpiOpType:33
|vpiOperand:
\_ref_obj: (branch_taken), line:161
|vpiName:branch_taken
|vpiOperand:
\_ref_obj: (branch_inputs.dec_pc), line:161
|vpiName:branch_inputs.dec_pc
|vpiOperand:
\_operation: , line:161
|vpiOpType:33
|vpiOperand:
\_constant: , line:161
|vpiConstType:3
|vpiDecompile:'b1
|vpiSize:1
|BIN:1
|vpiOperand:
\_part_select: , line:161, parent:jump_pc
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (jump_pc)
|vpiLeftRange:
\_constant: , line:161
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:161
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiLhs:
\_ref_obj: (branch_correctly_taken), line:161
|vpiName:branch_correctly_taken
|vpiFullName:work@branch_unit.branch_correctly_taken
|vpiContAssign:
\_cont_assign: , line:162
|vpiRhs:
\_operation: , line:162
|vpiOpType:14
|vpiOperand:
\_operation: , line:162
|vpiOpType:33
|vpiOperand:
\_ref_obj: (branch_taken), line:162
|vpiName:branch_taken
|vpiOperand:
\_ref_obj: (branch_inputs.dec_pc), line:162
|vpiName:branch_inputs.dec_pc
|vpiOperand:
\_operation: , line:162
|vpiOpType:33
|vpiOperand:
\_constant: , line:162
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiOperand:
\_part_select: , line:162, parent:njump_pc
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (njump_pc)
|vpiLeftRange:
\_constant: , line:162
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:162
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiLhs:
\_ref_obj: (branch_correclty_not_taken), line:162
|vpiName:branch_correclty_not_taken
|vpiFullName:work@branch_unit.branch_correclty_not_taken
|vpiContAssign:
\_cont_assign: , line:163
|vpiRhs:
\_operation: , line:163
|vpiOpType:4
|vpiOperand:
\_operation: , line:163
|vpiOpType:29
|vpiOperand:
\_ref_obj: (branch_correctly_taken), line:163
|vpiName:branch_correctly_taken
|vpiFullName:work@branch_unit.branch_correctly_taken
|vpiOperand:
\_ref_obj: (branch_correclty_not_taken), line:163
|vpiName:branch_correclty_not_taken
|vpiFullName:work@branch_unit.branch_correclty_not_taken
|vpiLhs:
\_ref_obj: (miss_predict), line:163
|vpiName:miss_predict
|vpiFullName:work@branch_unit.miss_predict
|vpiContAssign:
\_cont_assign: , line:165
|vpiRhs:
\_operation: , line:165
|vpiOpType:32
|vpiOperand:
\_ref_obj: (USE_BRANCH_PREDICTOR), line:165
|vpiName:USE_BRANCH_PREDICTOR
|vpiFullName:work@branch_unit.USE_BRANCH_PREDICTOR
|vpiOperand:
\_operation: , line:166
|vpiOpType:28
|vpiOperand:
\_ref_obj: (instruction_is_completing), line:166
|vpiName:instruction_is_completing
|vpiFullName:work@branch_unit.instruction_is_completing
|vpiOperand:
\_ref_obj: (miss_predict), line:166
|vpiName:miss_predict
|vpiFullName:work@branch_unit.miss_predict
|vpiOperand:
\_operation: , line:167
|vpiOpType:28
|vpiOperand:
\_ref_obj: (instruction_is_completing), line:167
|vpiName:instruction_is_completing
|vpiFullName:work@branch_unit.instruction_is_completing
|vpiOperand:
\_ref_obj: (branch_taken), line:167
|vpiName:branch_taken
|vpiFullName:work@branch_unit.branch_taken
|vpiLhs:
\_ref_obj: (branch_flush), line:165
|vpiName:branch_flush
|vpiFullName:work@branch_unit.branch_flush
|vpiNet:
\_logic_net: (clk), line:27
|vpiNet:
\_logic_net: (rst), line:28
|vpiNet:
\_logic_net: (branch_inputs), line:31
|vpiNet:
\_logic_net: (br_results), line:32
|vpiNet:
\_logic_net: (branch_flush), line:34
|vpiNet:
\_logic_net: (tr_branch_correct), line:37
|vpiNet:
\_logic_net: (tr_branch_misspredict), line:38
|vpiNet:
\_logic_net: (tr_return_misspredict), line:39
|vpiNet:
\_logic_net: (branch_issued_r), line:42
|vpiName:branch_issued_r
|vpiFullName:work@branch_unit.branch_issued_r
|vpiNetType:36
|vpiNet:
\_logic_net: (jal_imm), line:44
|vpiName:jal_imm
|vpiFullName:work@branch_unit.jal_imm
|vpiNetType:36
|vpiNet:
\_logic_net: (jalr_imm), line:45
|vpiName:jalr_imm
|vpiFullName:work@branch_unit.jalr_imm
|vpiNetType:36
|vpiNet:
\_logic_net: (br_imm), line:46
|vpiName:br_imm
|vpiFullName:work@branch_unit.br_imm
|vpiNetType:36
|vpiNet:
\_logic_net: (pc_offset), line:48
|vpiName:pc_offset
|vpiFullName:work@branch_unit.pc_offset
|vpiNetType:36
|vpiNet:
\_logic_net: (jump_base), line:49
|vpiName:jump_base
|vpiFullName:work@branch_unit.jump_base
|vpiNetType:36
|vpiNet:
\_logic_net: (jump_pc_dec), line:50
|vpiName:jump_pc_dec
|vpiFullName:work@branch_unit.jump_pc_dec
|vpiNetType:36
|vpiNet:
\_logic_net: (result), line:52
|vpiName:result
|vpiFullName:work@branch_unit.result
|vpiNetType:36
|vpiNet:
\_logic_net: (result_ex), line:53
|vpiName:result_ex
|vpiFullName:work@branch_unit.result_ex
|vpiNetType:36
|vpiNet:
\_logic_net: (fn3_ex), line:55
|vpiName:fn3_ex
|vpiFullName:work@branch_unit.fn3_ex
|vpiNetType:36
|vpiNet:
\_logic_net: (jump_ex), line:56
|vpiName:jump_ex
|vpiFullName:work@branch_unit.jump_ex
|vpiNetType:36
|vpiNet:
\_logic_net: (branch_taken), line:59
|vpiName:branch_taken
|vpiFullName:work@branch_unit.branch_taken
|vpiNetType:36
|vpiNet:
\_logic_net: (branch_correctly_taken), line:60
|vpiName:branch_correctly_taken
|vpiFullName:work@branch_unit.branch_correctly_taken
|vpiNetType:36
|vpiNet:
\_logic_net: (branch_correclty_not_taken), line:61
|vpiName:branch_correclty_not_taken
|vpiFullName:work@branch_unit.branch_correclty_not_taken
|vpiNetType:36
|vpiNet:
\_logic_net: (miss_predict), line:62
|vpiName:miss_predict
|vpiFullName:work@branch_unit.miss_predict
|vpiNetType:36
|vpiNet:
\_logic_net: (pc_ex), line:64
|vpiName:pc_ex
|vpiFullName:work@branch_unit.pc_ex
|vpiNetType:36
|vpiNet:
\_logic_net: (jump_pc), line:65
|vpiName:jump_pc
|vpiFullName:work@branch_unit.jump_pc
|vpiNetType:36
|vpiNet:
\_logic_net: (njump_pc), line:66
|vpiName:njump_pc
|vpiFullName:work@branch_unit.njump_pc
|vpiNetType:36
|vpiNet:
\_logic_net: (branch_metadata), line:67
|vpiName:branch_metadata
|vpiFullName:work@branch_unit.branch_metadata
|vpiNetType:36
|vpiNet:
\_logic_net: (branch_prediction_used), line:68
|vpiName:branch_prediction_used
|vpiFullName:work@branch_unit.branch_prediction_used
|vpiNetType:36
|vpiNet:
\_logic_net: (bp_update_way), line:69
|vpiName:bp_update_way
|vpiFullName:work@branch_unit.bp_update_way
|vpiNetType:36
|vpiNet:
\_logic_net: (instruction_is_completing), line:71
|vpiName:instruction_is_completing
|vpiFullName:work@branch_unit.instruction_is_completing
|vpiNetType:36
|vpiNet:
\_logic_net: (is_call), line:74
|vpiName:is_call
|vpiFullName:work@branch_unit.is_call
|vpiNetType:36
|vpiNet:
\_logic_net: (is_return), line:75
|vpiName:is_return
|vpiFullName:work@branch_unit.is_return
|vpiNetType:36
|vpiNet:
\_logic_net: (issue), line:30
|vpiName:issue
|vpiFullName:work@branch_unit.issue
|vpiNet:
\_logic_net: (ras), line:33
|vpiName:ras
|vpiFullName:work@branch_unit.ras
|vpiTypedef:
\_struct_typespec: (alu_inputs_t), line:301
|vpiTypedef:
\_enum_typespec: (alu_logic_op_t), line:84
|vpiTypedef:
\_enum_typespec: (alu_op_t), line:91
|vpiTypedef:
\_enum_typespec: (alu_rs1_op_t), line:97
|vpiTypedef:
\_enum_typespec: (alu_rs2_op_t), line:104
|vpiTypedef:
\_struct_typespec: (amo_alu_inputs_t), line:356
|vpiTypedef:
\_struct_typespec: (amo_details_t), line:362
|vpiTypedef:
\_enum_typespec: (amo_t), line:354
|vpiTypedef:
\_struct_typespec: (branch_inputs_t), line:313
|vpiTypedef:
\_logic_typespec: (branch_predictor_metadata_t), line:32
|vpiTypedef:
\_struct_typespec: (branch_results_t), line:330
|vpiTypedef:
\_enum_typespec: (bus_type_t), line:86
|vpiTypedef:
\_struct_typespec: (csr_inputs_t), line:396
|vpiTypedef:
\_enum_typespec: (csr_op_t), line:218
|vpiTypedef:
\_enum_typespec: (csr_t), line:201
|vpiTypedef:
\_struct_typespec: (data_access_shared_inputs_t), line:427
|vpiTypedef:
\_struct_typespec: (div_inputs_t), line:389
|vpiTypedef:
\_enum_typespec: (div_type), line:66
|vpiTypedef:
\_enum_typespec: (exception_code_t), line:245
|vpiTypedef:
\_struct_typespec: (exception_packet_t), line:263
|vpiTypedef:
\_struct_typespec: (fetch_buffer_packet_t), line:276
|vpiTypedef:
\_enum_typespec: (fifo_type_t), line:440
|vpiTypedef:
\_enum_typespec: (fn3_arith_t), line:76
|vpiTypedef:
\_enum_typespec: (fn3_branch_t), line:126
|vpiTypedef:
\_enum_typespec: (fn3_csr_t), line:212
|vpiTypedef:
\_enum_typespec: (fn3_ls_t), line:115
|vpiTypedef:
\_enum_typespec: (fn3_mul_div_t), line:138
|vpiTypedef:
\_struct_typespec: (gc_inputs_t), line:404
|vpiTypedef:
\_struct_typespec: (inflight_instruction_packet), line:271
|vpiTypedef:
\_logic_typespec: (instruction_id_t), line:30
|vpiTypedef:
\_enum_typespec: (interrupt_code_t), line:261
|vpiTypedef:
\_struct_typespec: (load_store_inputs_t), line:369
|vpiTypedef:
\_struct_typespec: (mul_inputs_t), line:383
|vpiTypedef:
\_enum_typespec: (opcodes_t), line:48
|vpiTypedef:
\_enum_typespec: (opcodes_trimmed_t), line:65
|vpiTypedef:
\_struct_typespec: (simulation_named_regfile), line:476
|vpiTypedef:
\_struct_typespec: (taiga_trace_events_t), line:442
|vpiTypedef:
\_struct_typespec: (to_l1_arbiter_packet), line:418
|vpiTypedef:
\_struct_typespec: (trace_outputs_t), line:469
|vpiTypedef:
\_logic_typespec: (unit_id_t), line:31
|vpiTypedef:
\_struct_typespec: (unit_writeback_t), line:295
|vpiTypedef:
\_enum_typespec: (vm_t), line:223
|uhdmallModules:
\_module: work@byte_en_BRAM, file:third_party/cores/taiga/core/byte_en_BRAM.sv, line:26, parent:work@div_unit_core_wrapper
|vpiDefName:work@byte_en_BRAM
|vpiFullName:work@byte_en_BRAM
|vpiPort:
\_port: (clk), line:32
|vpiName:clk
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (clk), line:32
|vpiName:clk
|vpiFullName:work@byte_en_BRAM.clk
|vpiNetType:36
|vpiPort:
\_port: (addr_a), line:33
|vpiName:addr_a
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (addr_a), line:33
|vpiName:addr_a
|vpiFullName:work@byte_en_BRAM.addr_a
|vpiNetType:36
|vpiPort:
\_port: (en_a), line:34
|vpiName:en_a
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (en_a), line:34
|vpiName:en_a
|vpiFullName:work@byte_en_BRAM.en_a
|vpiNetType:36
|vpiPort:
\_port: (be_a), line:35
|vpiName:be_a
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (be_a), line:35
|vpiName:be_a
|vpiFullName:work@byte_en_BRAM.be_a
|vpiNetType:36
|vpiPort:
\_port: (data_in_a), line:36
|vpiName:data_in_a
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (data_in_a), line:36
|vpiName:data_in_a
|vpiFullName:work@byte_en_BRAM.data_in_a
|vpiNetType:36
|vpiPort:
\_port: (data_out_a), line:37
|vpiName:data_out_a
|vpiDirection:2
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (data_out_a), line:37
|vpiName:data_out_a
|vpiFullName:work@byte_en_BRAM.data_out_a
|vpiNetType:36
|vpiPort:
\_port: (addr_b), line:39
|vpiName:addr_b
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (addr_b), line:39
|vpiName:addr_b
|vpiFullName:work@byte_en_BRAM.addr_b
|vpiNetType:36
|vpiPort:
\_port: (en_b), line:40
|vpiName:en_b
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (en_b), line:40
|vpiName:en_b
|vpiFullName:work@byte_en_BRAM.en_b
|vpiNetType:36
|vpiPort:
\_port: (be_b), line:41
|vpiName:be_b
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (be_b), line:41
|vpiName:be_b
|vpiFullName:work@byte_en_BRAM.be_b
|vpiNetType:36
|vpiPort:
\_port: (data_in_b), line:42
|vpiName:data_in_b
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (data_in_b), line:42
|vpiName:data_in_b
|vpiFullName:work@byte_en_BRAM.data_in_b
|vpiNetType:36
|vpiPort:
\_port: (data_out_b), line:43
|vpiName:data_out_b
|vpiDirection:2
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (data_out_b), line:43
|vpiName:data_out_b
|vpiFullName:work@byte_en_BRAM.data_out_b
|vpiNetType:36
|vpiNet:
\_logic_net: (clk), line:32
|vpiNet:
\_logic_net: (addr_a), line:33
|vpiNet:
\_logic_net: (en_a), line:34
|vpiNet:
\_logic_net: (be_a), line:35
|vpiNet:
\_logic_net: (data_in_a), line:36
|vpiNet:
\_logic_net: (data_out_a), line:37
|vpiNet:
\_logic_net: (addr_b), line:39
|vpiNet:
\_logic_net: (en_b), line:40
|vpiNet:
\_logic_net: (be_b), line:41
|vpiNet:
\_logic_net: (data_in_b), line:42
|vpiNet:
\_logic_net: (data_out_b), line:43
|vpiTypedef:
\_struct_typespec: (alu_inputs_t), line:301
|vpiTypedef:
\_enum_typespec: (alu_logic_op_t), line:84
|vpiTypedef:
\_enum_typespec: (alu_op_t), line:91
|vpiTypedef:
\_enum_typespec: (alu_rs1_op_t), line:97
|vpiTypedef:
\_enum_typespec: (alu_rs2_op_t), line:104
|vpiTypedef:
\_struct_typespec: (amo_alu_inputs_t), line:356
|vpiTypedef:
\_struct_typespec: (amo_details_t), line:362
|vpiTypedef:
\_enum_typespec: (amo_t), line:354
|vpiTypedef:
\_struct_typespec: (branch_inputs_t), line:313
|vpiTypedef:
\_logic_typespec: (branch_predictor_metadata_t), line:32
|vpiTypedef:
\_struct_typespec: (branch_results_t), line:330
|vpiTypedef:
\_enum_typespec: (bus_type_t), line:86
|vpiTypedef:
\_struct_typespec: (csr_inputs_t), line:396
|vpiTypedef:
\_enum_typespec: (csr_op_t), line:218
|vpiTypedef:
\_enum_typespec: (csr_t), line:201
|vpiTypedef:
\_struct_typespec: (data_access_shared_inputs_t), line:427
|vpiTypedef:
\_struct_typespec: (div_inputs_t), line:389
|vpiTypedef:
\_enum_typespec: (div_type), line:66
|vpiTypedef:
\_enum_typespec: (exception_code_t), line:245
|vpiTypedef:
\_struct_typespec: (exception_packet_t), line:263
|vpiTypedef:
\_struct_typespec: (fetch_buffer_packet_t), line:276
|vpiTypedef:
\_enum_typespec: (fifo_type_t), line:440
|vpiTypedef:
\_enum_typespec: (fn3_arith_t), line:76
|vpiTypedef:
\_enum_typespec: (fn3_branch_t), line:126
|vpiTypedef:
\_enum_typespec: (fn3_csr_t), line:212
|vpiTypedef:
\_enum_typespec: (fn3_ls_t), line:115
|vpiTypedef:
\_enum_typespec: (fn3_mul_div_t), line:138
|vpiTypedef:
\_struct_typespec: (gc_inputs_t), line:404
|vpiTypedef:
\_struct_typespec: (inflight_instruction_packet), line:271
|vpiTypedef:
\_logic_typespec: (instruction_id_t), line:30
|vpiTypedef:
\_enum_typespec: (interrupt_code_t), line:261
|vpiTypedef:
\_struct_typespec: (load_store_inputs_t), line:369
|vpiTypedef:
\_struct_typespec: (mul_inputs_t), line:383
|vpiTypedef:
\_enum_typespec: (opcodes_t), line:48
|vpiTypedef:
\_enum_typespec: (opcodes_trimmed_t), line:65
|vpiTypedef:
\_struct_typespec: (simulation_named_regfile), line:476
|vpiTypedef:
\_struct_typespec: (taiga_trace_events_t), line:442
|vpiTypedef:
\_struct_typespec: (to_l1_arbiter_packet), line:418
|vpiTypedef:
\_struct_typespec: (trace_outputs_t), line:469
|vpiTypedef:
\_logic_typespec: (unit_id_t), line:31
|vpiTypedef:
\_struct_typespec: (unit_writeback_t), line:295
|vpiTypedef:
\_enum_typespec: (vm_t), line:223
|vpiParamAssign:
\_param_assign: , line:27
|vpiRhs:
\_constant: , line:27
|vpiConstType:7
|vpiDecompile:4096
|vpiSize:32
|INT:4096
|vpiLhs:
\_parameter: (LINES), line:27
|vpiName:LINES
|vpiParamAssign:
\_param_assign: , line:28
|vpiRhs:
\_constant: , line:28
|vpiConstType:6
|vpiDecompile:""
|vpiSize:2
|STRING:""
|vpiLhs:
\_parameter: (preload_file), line:28
|vpiName:preload_file
|vpiParamAssign:
\_param_assign: , line:29
|vpiRhs:
\_constant: , line:29
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiLhs:
\_parameter: (USE_PRELOAD_FILE), line:29
|vpiName:USE_PRELOAD_FILE
|vpiParameter:
\_parameter: (LINES), line:27
|vpiParameter:
\_parameter: (preload_file), line:28
|vpiParameter:
\_parameter: (USE_PRELOAD_FILE), line:29
|uhdmallModules:
\_module: work@clz, file:third_party/cores/taiga/core/clz.sv, line:23, parent:work@div_unit_core_wrapper
|vpiDefName:work@clz
|vpiFullName:work@clz
|vpiProcess:
\_always: , line:42
|vpiAlwaysType:2
|vpiStmt:
\_begin: , line:42
|vpiFullName:work@clz
|vpiStmt:
\_for_stmt: , line:43
|vpiFullName:work@clz
|vpiCondition:
\_operation: , line:43
|vpiOpType:20
|vpiOperand:
\_ref_obj: (i), line:43
|vpiName:i
|vpiFullName:work@clz.i
|vpiOperand:
\_constant: , line:43
|vpiConstType:7
|vpiDecompile:8
|vpiSize:32
|INT:8
|vpiForInitStmt:
\_assign_stmt:
|vpiRhs:
\_constant: , line:43
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiLhs:
\_int_var: (i), line:43
|vpiName:i
|vpiFullName:work@clz.i
|vpiForIncStmt:
\_operation: , line:43
|vpiOpType:62
|vpiOperand:
\_ref_obj: (i), line:43
|vpiName:i
|vpiStmt:
\_begin: , line:43
|vpiFullName:work@clz
|vpiStmt:
\_assignment: , line:44
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_bit_select: (sub_clz), line:44
|vpiName:sub_clz
|vpiFullName:work@clz.sub_clz
|vpiIndex:
\_operation: , line:44
|vpiOpType:11
|vpiOperand:
\_constant: , line:44
|vpiConstType:7
|vpiDecompile:7
|vpiSize:32
|INT:7
|vpiOperand:
\_ref_obj: (i), line:44
|vpiName:i
|vpiRhs:
\_operation: , line:44
|vpiOpType:8
|vpiOperand:
\_indexed_part_select: , line:44, parent:clz_input
|vpiConstantSelect:1
|vpiIndexedPartSelectType:1
|vpiBaseExpr:
\_operation: , line:44
|vpiOpType:25
|vpiOperand:
\_ref_obj: (i), line:44
|vpiName:i
|vpiFullName:work@clz.i
|vpiOperand:
\_constant: , line:44
|vpiConstType:7
|vpiDecompile:4
|vpiSize:32
|INT:4
|vpiWidthExpr:
\_constant: , line:44
|vpiConstType:7
|vpiDecompile:4
|vpiSize:32
|INT:4
|vpiStmt:
\_assignment: , line:45
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_bit_select: (low_order_clz), line:45
|vpiName:low_order_clz
|vpiFullName:work@clz.low_order_clz
|vpiIndex:
\_operation: , line:45
|vpiOpType:11
|vpiOperand:
\_constant: , line:45
|vpiConstType:7
|vpiDecompile:7
|vpiSize:32
|INT:7
|vpiOperand:
\_ref_obj: (i), line:45
|vpiName:i
|vpiRhs:
\_operation: , line:45
|vpiOpType:4
|vpiOperand:
\_operation: , line:45
|vpiOpType:29
|vpiOperand:
\_bit_select: (clz_input), line:45
|vpiName:clz_input
|vpiFullName:work@clz.clz_input
|vpiIndex:
\_operation: , line:45
|vpiOpType:24
|vpiOperand:
\_operation: , line:45
|vpiOpType:25
|vpiOperand:
\_ref_obj: (i), line:45
|vpiName:i
|vpiFullName:work@clz.i
|vpiOperand:
\_constant: , line:45
|vpiConstType:7
|vpiDecompile:4
|vpiSize:32
|INT:4
|vpiOperand:
\_constant: , line:45
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiOperand:
\_bit_select: (clz_input), line:45
|vpiName:clz_input
|vpiFullName:work@clz.clz_input
|vpiIndex:
\_operation: , line:45
|vpiOpType:24
|vpiOperand:
\_operation: , line:45
|vpiOpType:25
|vpiOperand:
\_ref_obj: (i), line:45
|vpiName:i
|vpiFullName:work@clz.i
|vpiOperand:
\_constant: , line:45
|vpiConstType:7
|vpiDecompile:4
|vpiSize:32
|INT:4
|vpiOperand:
\_constant: , line:45
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiStmt:
\_assignment: , line:46
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_bit_select: (low_order_clz), line:46
|vpiName:low_order_clz
|vpiFullName:work@clz.low_order_clz
|vpiIndex:
\_operation: , line:46
|vpiOpType:11
|vpiOperand:
\_constant: , line:46
|vpiConstType:7
|vpiDecompile:7
|vpiSize:32
|INT:7
|vpiOperand:
\_ref_obj: (i), line:46
|vpiName:i
|vpiRhs:
\_operation: , line:46
|vpiOpType:4
|vpiOperand:
\_operation: , line:46
|vpiOpType:29
|vpiOperand:
\_bit_select: (clz_input), line:46
|vpiName:clz_input
|vpiFullName:work@clz.clz_input
|vpiIndex:
\_operation: , line:46
|vpiOpType:24
|vpiOperand:
\_operation: , line:46
|vpiOpType:25
|vpiOperand:
\_ref_obj: (i), line:46
|vpiName:i
|vpiFullName:work@clz.i
|vpiOperand:
\_constant: , line:46
|vpiConstType:7
|vpiDecompile:4
|vpiSize:32
|INT:4
|vpiOperand:
\_constant: , line:46
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiOperand:
\_operation: , line:46
|vpiOpType:28
|vpiOperand:
\_operation: , line:46
|vpiOpType:4
|vpiOperand:
\_bit_select: (clz_input), line:46
|vpiName:clz_input
|vpiIndex:
\_operation: , line:46
|vpiOpType:24
|vpiOperand:
\_operation: , line:46
|vpiOpType:25
|vpiOperand:
\_ref_obj: (i), line:46
|vpiName:i
|vpiFullName:work@clz.i
|vpiOperand:
\_constant: , line:46
|vpiConstType:7
|vpiDecompile:4
|vpiSize:32
|INT:4
|vpiOperand:
\_constant: , line:46
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiOperand:
\_bit_select: (clz_input), line:46
|vpiName:clz_input
|vpiFullName:work@clz.clz_input
|vpiIndex:
\_operation: , line:46
|vpiOpType:24
|vpiOperand:
\_operation: , line:46
|vpiOpType:25
|vpiOperand:
\_ref_obj: (i), line:46
|vpiName:i
|vpiFullName:work@clz.i
|vpiOperand:
\_constant: , line:46
|vpiConstType:7
|vpiDecompile:4
|vpiSize:32
|INT:4
|vpiOperand:
\_constant: , line:46
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiStmt:
\_assignment: , line:49
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_bit_select: (clz), line:49
|vpiName:clz
|vpiFullName:work@clz.clz
|vpiIndex:
\_constant: , line:49
|vpiConstType:7
|vpiDecompile:4
|vpiSize:32
|INT:4
|vpiRhs:
\_operation: , line:49
|vpiOpType:5
|vpiOperand:
\_part_select: , line:49, parent:sub_clz
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (sub_clz)
|vpiLeftRange:
\_constant: , line:49
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiRightRange:
\_constant: , line:49
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiStmt:
\_assignment: , line:50
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_bit_select: (clz), line:50
|vpiName:clz
|vpiFullName:work@clz.clz
|vpiIndex:
\_constant: , line:50
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiRhs:
\_operation: , line:50
|vpiOpType:28
|vpiOperand:
\_operation: , line:50
|vpiOpType:5
|vpiOperand:
\_part_select: , line:50, parent:sub_clz
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (sub_clz)
|vpiLeftRange:
\_constant: , line:50
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:50
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiOperand:
\_operation: , line:50
|vpiOpType:29
|vpiOperand:
\_operation: , line:50
|vpiOpType:6
|vpiOperand:
\_part_select: , line:50, parent:sub_clz
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (sub_clz)
|vpiLeftRange:
\_constant: , line:50
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiRightRange:
\_constant: , line:50
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiOperand:
\_operation: , line:50
|vpiOpType:5
|vpiOperand:
\_part_select: , line:50, parent:sub_clz
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (sub_clz)
|vpiLeftRange:
\_constant: , line:50
|vpiConstType:7
|vpiDecompile:5
|vpiSize:32
|INT:5
|vpiRightRange:
\_constant: , line:50
|vpiConstType:7
|vpiDecompile:4
|vpiSize:32
|INT:4
|vpiStmt:
\_assignment: , line:51
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_bit_select: (clz), line:51
|vpiName:clz
|vpiFullName:work@clz.clz
|vpiIndex:
\_constant: , line:51
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiRhs:
\_operation: , line:52
|vpiOpType:29
|vpiOperand:
\_operation: , line:52
|vpiOpType:29
|vpiOperand:
\_operation: , line:52
|vpiOpType:29
|vpiOperand:
\_operation: , line:52
|vpiOpType:28
|vpiOperand:
\_bit_select: (sub_clz), line:52
|vpiName:sub_clz
|vpiFullName:work@clz.sub_clz
|vpiIndex:
\_constant: , line:52
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiOperand:
\_operation: , line:52
|vpiOpType:4
|vpiOperand:
\_bit_select: (sub_clz), line:52
|vpiName:sub_clz
|vpiIndex:
\_constant: , line:52
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiOperand:
\_operation: , line:53
|vpiOpType:28
|vpiOperand:
\_operation: , line:53
|vpiOpType:5
|vpiOperand:
\_part_select: , line:53, parent:sub_clz
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (sub_clz)
|vpiLeftRange:
\_constant: , line:53
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiRightRange:
\_constant: , line:53
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiOperand:
\_operation: , line:53
|vpiOpType:4
|vpiOperand:
\_bit_select: (sub_clz), line:53
|vpiName:sub_clz
|vpiIndex:
\_constant: , line:53
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiOperand:
\_operation: , line:54
|vpiOpType:28
|vpiOperand:
\_operation: , line:54
|vpiOpType:5
|vpiOperand:
\_part_select: , line:54, parent:sub_clz
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (sub_clz)
|vpiLeftRange:
\_constant: , line:54
|vpiConstType:7
|vpiDecompile:4
|vpiSize:32
|INT:4
|vpiRightRange:
\_constant: , line:54
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiOperand:
\_operation: , line:54
|vpiOpType:4
|vpiOperand:
\_bit_select: (sub_clz), line:54
|vpiName:sub_clz
|vpiIndex:
\_constant: , line:54
|vpiConstType:7
|vpiDecompile:5
|vpiSize:32
|INT:5
|vpiOperand:
\_operation: , line:55
|vpiOpType:5
|vpiOperand:
\_part_select: , line:55, parent:sub_clz
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (sub_clz)
|vpiLeftRange:
\_constant: , line:55
|vpiConstType:7
|vpiDecompile:6
|vpiSize:32
|INT:6
|vpiRightRange:
\_constant: , line:55
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiStmt:
\_for_stmt: , line:57
|vpiFullName:work@clz
|vpiCondition:
\_operation: , line:57
|vpiOpType:20
|vpiOperand:
\_ref_obj: (i), line:57
|vpiName:i
|vpiFullName:work@clz.i
|vpiOperand:
\_constant: , line:57
|vpiConstType:7
|vpiDecompile:4
|vpiSize:32
|INT:4
|vpiForInitStmt:
\_assign_stmt:
|vpiRhs:
\_constant: , line:57
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiLhs:
\_int_var: (i), line:57
|vpiName:i
|vpiFullName:work@clz.i
|vpiForIncStmt:
\_operation: , line:57
|vpiOpType:62
|vpiOperand:
\_ref_obj: (i), line:57
|vpiName:i
|vpiStmt:
\_begin: , line:57
|vpiFullName:work@clz
|vpiStmt:
\_assignment: , line:58
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_bit_select: (upper_lower), line:58
|vpiName:upper_lower
|vpiFullName:work@clz.upper_lower
|vpiIndex:
\_ref_obj: (i), line:58
|vpiName:i
|vpiRhs:
\_operation: , line:58
|vpiOpType:32
|vpiOperand:
\_bit_select: (sub_clz), line:58
|vpiName:sub_clz
|vpiFullName:work@clz.sub_clz
|vpiIndex:
\_operation: , line:58
|vpiOpType:25
|vpiOperand:
\_constant: , line:58
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiOperand:
\_ref_obj: (i), line:58
|vpiName:i
|vpiOperand:
\_bit_select: (low_order_clz), line:58
|vpiName:low_order_clz
|vpiFullName:work@clz.low_order_clz
|vpiIndex:
\_operation: , line:58
|vpiOpType:24
|vpiOperand:
\_operation: , line:58
|vpiOpType:25
|vpiOperand:
\_constant: , line:58
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiOperand:
\_ref_obj: (i), line:58
|vpiName:i
|vpiFullName:work@clz.i
|vpiOperand:
\_constant: , line:58
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiOperand:
\_bit_select: (low_order_clz), line:58
|vpiName:low_order_clz
|vpiFullName:work@clz.low_order_clz
|vpiIndex:
\_operation: , line:58
|vpiOpType:25
|vpiOperand:
\_constant: , line:58
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiOperand:
\_ref_obj: (i), line:58
|vpiName:i
|vpiFullName:work@clz.i
|vpiStmt:
\_assignment: , line:61
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_part_select: , line:61, parent:clz
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (clz)
|vpiLeftRange:
\_constant: , line:61
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:61
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiRhs:
\_bit_select: (upper_lower), line:61
|vpiName:upper_lower
|vpiFullName:work@clz.upper_lower
|vpiIndex:
\_part_select: , line:61, parent:clz
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (clz)
|vpiLeftRange:
\_constant: , line:61
|vpiConstType:7
|vpiDecompile:4
|vpiSize:32
|INT:4
|vpiRightRange:
\_constant: , line:61
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiPort:
\_port: (clz_input), line:25
|vpiName:clz_input
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (clz_input), line:25
|vpiName:clz_input
|vpiFullName:work@clz.clz_input
|vpiNetType:36
|vpiPort:
\_port: (clz), line:26
|vpiName:clz
|vpiDirection:2
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (clz), line:26
|vpiName:clz
|vpiFullName:work@clz.clz
|vpiNetType:36
|vpiNet:
\_logic_net: (clz_input), line:25
|vpiNet:
\_logic_net: (clz), line:26
|vpiNet:
\_logic_net: (low_order_clz), line:29
|vpiName:low_order_clz
|vpiFullName:work@clz.low_order_clz
|vpiNetType:36
|vpiNet:
\_logic_net: (sub_clz), line:30
|vpiName:sub_clz
|vpiFullName:work@clz.sub_clz
|vpiNetType:36
|vpiNet:
\_logic_net: (upper_lower), line:32
|vpiName:upper_lower
|vpiFullName:work@clz.upper_lower
|vpiNetType:36
|uhdmallModules:
\_module: work@csr_regs, file:third_party/cores/taiga/core/csr_regs.sv, line:27, parent:work@div_unit_core_wrapper
|vpiDefName:work@csr_regs
|vpiFullName:work@csr_regs
|vpiProcess:
\_always: , line:161
|vpiAlwaysType:2
|vpiStmt:
\_begin: , line:161
|vpiFullName:work@csr_regs
|vpiStmt:
\_assignment: , line:162
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (swrite_decoder), line:162
|vpiName:swrite_decoder
|vpiFullName:work@csr_regs.swrite_decoder
|vpiRhs:
\_constant: , line:162
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiStmt:
\_assignment: , line:163
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_bit_select: (swrite_decoder), line:163
|vpiName:swrite_decoder
|vpiFullName:work@csr_regs.swrite_decoder
|vpiIndex:
\_ref_obj: (csr_addr.sub_addr), line:163
|vpiName:csr_addr.sub_addr
|vpiRhs:
\_ref_obj: (supervisor_write), line:163
|vpiName:supervisor_write
|vpiFullName:work@csr_regs.supervisor_write
|vpiStmt:
\_assignment: , line:164
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (mwrite_decoder), line:164
|vpiName:mwrite_decoder
|vpiFullName:work@csr_regs.mwrite_decoder
|vpiRhs:
\_constant: , line:164
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiStmt:
\_assignment: , line:165
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_bit_select: (mwrite_decoder), line:165
|vpiName:mwrite_decoder
|vpiFullName:work@csr_regs.mwrite_decoder
|vpiIndex:
\_ref_obj: (csr_addr.sub_addr), line:165
|vpiName:csr_addr.sub_addr
|vpiRhs:
\_ref_obj: (machine_write), line:165
|vpiName:machine_write
|vpiFullName:work@csr_regs.machine_write
|vpiProcess:
\_always: , line:182
|vpiAlwaysType:2
|vpiStmt:
\_begin: , line:182
|vpiFullName:work@csr_regs
|vpiStmt:
\_case_stmt: , line:183
|vpiCaseType:1
|vpiCondition:
\_ref_obj: (csr_inputs.csr_op), line:183
|vpiName:csr_inputs.csr_op
|vpiFullName:work@csr_regs.csr_inputs.csr_op
|vpiCaseItem:
\_case_item: , line:184
|vpiExpr:
\_ref_obj: (CSR_RW), line:184
|vpiName:CSR_RW
|vpiFullName:work@csr_regs.CSR_RW
|vpiStmt:
\_assignment: , line:184
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (updated_csr), line:184
|vpiName:updated_csr
|vpiFullName:work@csr_regs.updated_csr
|vpiRhs:
\_ref_obj: (csr_inputs.rs1), line:184
|vpiName:csr_inputs.rs1
|vpiFullName:work@csr_regs.csr_inputs.rs1
|vpiCaseItem:
\_case_item: , line:185
|vpiExpr:
\_ref_obj: (CSR_RS), line:185
|vpiName:CSR_RS
|vpiFullName:work@csr_regs.CSR_RS
|vpiStmt:
\_assignment: , line:185
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (updated_csr), line:185
|vpiName:updated_csr
|vpiFullName:work@csr_regs.updated_csr
|vpiRhs:
\_operation: , line:185
|vpiOpType:29
|vpiOperand:
\_ref_obj: (selected_csr_r), line:185
|vpiName:selected_csr_r
|vpiFullName:work@csr_regs.selected_csr_r
|vpiOperand:
\_ref_obj: (csr_inputs.rs1), line:185
|vpiName:csr_inputs.rs1
|vpiFullName:work@csr_regs.csr_inputs.rs1
|vpiCaseItem:
\_case_item: , line:186
|vpiExpr:
\_ref_obj: (CSR_RC), line:186
|vpiName:CSR_RC
|vpiFullName:work@csr_regs.CSR_RC
|vpiStmt:
\_assignment: , line:186
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (updated_csr), line:186
|vpiName:updated_csr
|vpiFullName:work@csr_regs.updated_csr
|vpiRhs:
\_operation: , line:186
|vpiOpType:28
|vpiOperand:
\_ref_obj: (selected_csr_r), line:186
|vpiName:selected_csr_r
|vpiFullName:work@csr_regs.selected_csr_r
|vpiOperand:
\_operation: , line:186
|vpiOpType:4
|vpiOperand:
\_ref_obj: (csr_inputs.rs1), line:186
|vpiName:csr_inputs.rs1
|vpiFullName:work@csr_regs.csr_inputs.rs1
|vpiCaseItem:
\_case_item: , line:187
|vpiStmt:
\_assignment: , line:187
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (updated_csr), line:187
|vpiName:updated_csr
|vpiFullName:work@csr_regs.updated_csr
|vpiRhs:
\_ref_obj: (csr_inputs.rs1), line:187
|vpiName:csr_inputs.rs1
|vpiFullName:work@csr_regs.csr_inputs.rs1
|vpiProcess:
\_always: , line:454
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:454
|vpiCondition:
\_operation: , line:454
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:454
|vpiName:clk
|vpiFullName:work@csr_regs.clk
|vpiStmt:
\_begin: , line:454
|vpiFullName:work@csr_regs
|vpiStmt:
\_if_else: , line:455
|vpiCondition:
\_ref_obj: (rst), line:455
|vpiName:rst
|vpiFullName:work@csr_regs.rst
|vpiStmt:
\_begin: , line:455
|vpiFullName:work@csr_regs
|vpiStmt:
\_assignment: , line:456
|vpiOpType:82
|vpiLhs:
\_ref_obj: (inst_ret_inc), line:456
|vpiName:inst_ret_inc
|vpiFullName:work@csr_regs.inst_ret_inc
|vpiRhs:
\_constant: , line:456
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiElseStmt:
\_begin: , line:457
|vpiFullName:work@csr_regs
|vpiStmt:
\_if_else: , line:458
|vpiCondition:
\_operation: , line:458
|vpiOpType:28
|vpiOperand:
\_ref_obj: (instruction_complete), line:458
|vpiName:instruction_complete
|vpiFullName:work@csr_regs.instruction_complete
|vpiOperand:
\_ref_obj: (instruction_issued_no_rd), line:458
|vpiName:instruction_issued_no_rd
|vpiFullName:work@csr_regs.instruction_issued_no_rd
|vpiStmt:
\_assignment: , line:459
|vpiOpType:82
|vpiLhs:
\_ref_obj: (inst_ret_inc), line:459
|vpiName:inst_ret_inc
|vpiFullName:work@csr_regs.inst_ret_inc
|vpiRhs:
\_constant: , line:459
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiElseStmt:
\_if_else: , line:460
|vpiCondition:
\_operation: , line:460
|vpiOpType:29
|vpiOperand:
\_ref_obj: (instruction_complete), line:460
|vpiName:instruction_complete
|vpiFullName:work@csr_regs.instruction_complete
|vpiOperand:
\_ref_obj: (instruction_issued_no_rd), line:460
|vpiName:instruction_issued_no_rd
|vpiFullName:work@csr_regs.instruction_issued_no_rd
|vpiStmt:
\_assignment: , line:461
|vpiOpType:82
|vpiLhs:
\_ref_obj: (inst_ret_inc), line:461
|vpiName:inst_ret_inc
|vpiFullName:work@csr_regs.inst_ret_inc
|vpiRhs:
\_constant: , line:461
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiElseStmt:
\_assignment: , line:463
|vpiOpType:82
|vpiLhs:
\_ref_obj: (inst_ret_inc), line:463
|vpiName:inst_ret_inc
|vpiFullName:work@csr_regs.inst_ret_inc
|vpiRhs:
\_constant: , line:463
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiProcess:
\_always: , line:467
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:467
|vpiCondition:
\_operation: , line:467
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:467
|vpiName:clk
|vpiFullName:work@csr_regs.clk
|vpiStmt:
\_begin: , line:467
|vpiFullName:work@csr_regs
|vpiStmt:
\_if_else: , line:468
|vpiCondition:
\_ref_obj: (rst), line:468
|vpiName:rst
|vpiFullName:work@csr_regs.rst
|vpiStmt:
\_begin: , line:468
|vpiFullName:work@csr_regs
|vpiStmt:
\_assignment: , line:469
|vpiOpType:82
|vpiLhs:
\_ref_obj: (mcycle), line:469
|vpiName:mcycle
|vpiFullName:work@csr_regs.mcycle
|vpiRhs:
\_constant: , line:469
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiStmt:
\_assignment: , line:470
|vpiOpType:82
|vpiLhs:
\_ref_obj: (minst_ret), line:470
|vpiName:minst_ret
|vpiFullName:work@csr_regs.minst_ret
|vpiRhs:
\_constant: , line:470
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiElseStmt:
\_begin: , line:471
|vpiFullName:work@csr_regs
|vpiStmt:
\_assignment: , line:472
|vpiOpType:82
|vpiLhs:
\_ref_obj: (mcycle), line:472
|vpiName:mcycle
|vpiFullName:work@csr_regs.mcycle
|vpiRhs:
\_operation: , line:472
|vpiOpType:24
|vpiOperand:
\_ref_obj: (mcycle), line:472
|vpiName:mcycle
|vpiFullName:work@csr_regs.mcycle
|vpiOperand:
\_constant: , line:472
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiStmt:
\_assignment: , line:473
|vpiOpType:82
|vpiLhs:
\_ref_obj: (minst_ret), line:473
|vpiName:minst_ret
|vpiFullName:work@csr_regs.minst_ret
|vpiRhs:
\_operation: , line:473
|vpiOpType:24
|vpiOperand:
\_ref_obj: (minst_ret), line:473
|vpiName:minst_ret
|vpiFullName:work@csr_regs.minst_ret
|vpiOperand:
\_operation: , line:473
|vpiOpType:67
|vpiOperand:
\_ref_obj: (inst_ret_inc), line:473
|vpiName:inst_ret_inc
|vpiFullName:work@csr_regs.inst_ret_inc
|vpiTypespec:
\_void_typespec: (COUNTER_W), line:473
|vpiName:COUNTER_W
|vpiProcess:
\_always: , line:478
|vpiAlwaysType:2
|vpiStmt:
\_begin: , line:478
|vpiFullName:work@csr_regs
|vpiStmt:
\_assignment: , line:479
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (invalid_addr), line:479
|vpiName:invalid_addr
|vpiFullName:work@csr_regs.invalid_addr
|vpiRhs:
\_constant: , line:479
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiStmt:
\_case_stmt: , line:480
|vpiCaseType:1
|vpiCondition:
\_ref_obj: (csr_addr), line:480
|vpiName:csr_addr
|vpiFullName:work@csr_regs.csr_addr
|vpiCaseItem:
\_case_item: , line:482
|vpiExpr:
\_ref_obj: (MISA), line:482
|vpiName:MISA
|vpiFullName:work@csr_regs.MISA
|vpiStmt:
\_assignment: , line:482
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (selected_csr), line:482
|vpiName:selected_csr
|vpiFullName:work@csr_regs.selected_csr
|vpiRhs:
\_ref_obj: (misa), line:482
|vpiName:misa
|vpiFullName:work@csr_regs.misa
|vpiCaseItem:
\_case_item: , line:483
|vpiExpr:
\_ref_obj: (MVENDORID), line:483
|vpiName:MVENDORID
|vpiFullName:work@csr_regs.MVENDORID
|vpiStmt:
\_assignment: , line:483
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (selected_csr), line:483
|vpiName:selected_csr
|vpiFullName:work@csr_regs.selected_csr
|vpiRhs:
\_ref_obj: (mvendorid), line:483
|vpiName:mvendorid
|vpiFullName:work@csr_regs.mvendorid
|vpiCaseItem:
\_case_item: , line:484
|vpiExpr:
\_ref_obj: (MARCHID), line:484
|vpiName:MARCHID
|vpiFullName:work@csr_regs.MARCHID
|vpiStmt:
\_assignment: , line:484
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (selected_csr), line:484
|vpiName:selected_csr
|vpiFullName:work@csr_regs.selected_csr
|vpiRhs:
\_ref_obj: (marchid), line:484
|vpiName:marchid
|vpiFullName:work@csr_regs.marchid
|vpiCaseItem:
\_case_item: , line:485
|vpiExpr:
\_ref_obj: (MIMPID), line:485
|vpiName:MIMPID
|vpiFullName:work@csr_regs.MIMPID
|vpiStmt:
\_assignment: , line:485
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (selected_csr), line:485
|vpiName:selected_csr
|vpiFullName:work@csr_regs.selected_csr
|vpiRhs:
\_ref_obj: (mimpid), line:485
|vpiName:mimpid
|vpiFullName:work@csr_regs.mimpid
|vpiCaseItem:
\_case_item: , line:486
|vpiExpr:
\_ref_obj: (MHARTID), line:486
|vpiName:MHARTID
|vpiFullName:work@csr_regs.MHARTID
|vpiStmt:
\_assignment: , line:486
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (selected_csr), line:486
|vpiName:selected_csr
|vpiFullName:work@csr_regs.selected_csr
|vpiRhs:
\_ref_obj: (mhartid), line:486
|vpiName:mhartid
|vpiFullName:work@csr_regs.mhartid
|vpiCaseItem:
\_case_item: , line:488
|vpiExpr:
\_ref_obj: (MSTATUS), line:488
|vpiName:MSTATUS
|vpiFullName:work@csr_regs.MSTATUS
|vpiStmt:
\_assignment: , line:488
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (selected_csr), line:488
|vpiName:selected_csr
|vpiFullName:work@csr_regs.selected_csr
|vpiRhs:
\_ref_obj: (mstatus), line:488
|vpiName:mstatus
|vpiFullName:work@csr_regs.mstatus
|vpiCaseItem:
\_case_item: , line:489
|vpiExpr:
\_ref_obj: (MEDELEG), line:489
|vpiName:MEDELEG
|vpiFullName:work@csr_regs.MEDELEG
|vpiStmt:
\_assignment: , line:489
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (selected_csr), line:489
|vpiName:selected_csr
|vpiFullName:work@csr_regs.selected_csr
|vpiRhs:
\_ref_obj: (medeleg), line:489
|vpiName:medeleg
|vpiFullName:work@csr_regs.medeleg
|vpiCaseItem:
\_case_item: , line:490
|vpiExpr:
\_ref_obj: (MIDELEG), line:490
|vpiName:MIDELEG
|vpiFullName:work@csr_regs.MIDELEG
|vpiStmt:
\_assignment: , line:490
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (selected_csr), line:490
|vpiName:selected_csr
|vpiFullName:work@csr_regs.selected_csr
|vpiRhs:
\_ref_obj: (mideleg), line:490
|vpiName:mideleg
|vpiFullName:work@csr_regs.mideleg
|vpiCaseItem:
\_case_item: , line:491
|vpiExpr:
\_ref_obj: (MIE), line:491
|vpiName:MIE
|vpiFullName:work@csr_regs.MIE
|vpiStmt:
\_assignment: , line:491
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (selected_csr), line:491
|vpiName:selected_csr
|vpiFullName:work@csr_regs.selected_csr
|vpiRhs:
\_ref_obj: (mie_reg), line:491
|vpiName:mie_reg
|vpiFullName:work@csr_regs.mie_reg
|vpiCaseItem:
\_case_item: , line:492
|vpiExpr:
\_ref_obj: (MTVEC), line:492
|vpiName:MTVEC
|vpiFullName:work@csr_regs.MTVEC
|vpiStmt:
\_assignment: , line:492
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (selected_csr), line:492
|vpiName:selected_csr
|vpiFullName:work@csr_regs.selected_csr
|vpiRhs:
\_ref_obj: (mtvec), line:492
|vpiName:mtvec
|vpiFullName:work@csr_regs.mtvec
|vpiCaseItem:
\_case_item: , line:494
|vpiExpr:
\_ref_obj: (MSCRATCH), line:494
|vpiName:MSCRATCH
|vpiFullName:work@csr_regs.MSCRATCH
|vpiStmt:
\_assignment: , line:494
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (selected_csr), line:494
|vpiName:selected_csr
|vpiFullName:work@csr_regs.selected_csr
|vpiRhs:
\_ref_obj: (scratch_out), line:494
|vpiName:scratch_out
|vpiFullName:work@csr_regs.scratch_out
|vpiCaseItem:
\_case_item: , line:495
|vpiExpr:
\_ref_obj: (MEPC), line:495
|vpiName:MEPC
|vpiFullName:work@csr_regs.MEPC
|vpiStmt:
\_assignment: , line:495
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (selected_csr), line:495
|vpiName:selected_csr
|vpiFullName:work@csr_regs.selected_csr
|vpiRhs:
\_ref_obj: (mepc), line:495
|vpiName:mepc
|vpiFullName:work@csr_regs.mepc
|vpiCaseItem:
\_case_item: , line:496
|vpiExpr:
\_ref_obj: (MCAUSE), line:496
|vpiName:MCAUSE
|vpiFullName:work@csr_regs.MCAUSE
|vpiStmt:
\_assignment: , line:496
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (selected_csr), line:496
|vpiName:selected_csr
|vpiFullName:work@csr_regs.selected_csr
|vpiRhs:
\_ref_obj: (mcause), line:496
|vpiName:mcause
|vpiFullName:work@csr_regs.mcause
|vpiCaseItem:
\_case_item: , line:497
|vpiExpr:
\_ref_obj: (MTVAL), line:497
|vpiName:MTVAL
|vpiFullName:work@csr_regs.MTVAL
|vpiStmt:
\_assignment: , line:497
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (selected_csr), line:497
|vpiName:selected_csr
|vpiFullName:work@csr_regs.selected_csr
|vpiRhs:
\_ref_obj: (mtval), line:497
|vpiName:mtval
|vpiFullName:work@csr_regs.mtval
|vpiCaseItem:
\_case_item: , line:498
|vpiExpr:
\_ref_obj: (MIP), line:498
|vpiName:MIP
|vpiFullName:work@csr_regs.MIP
|vpiStmt:
\_assignment: , line:498
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (selected_csr), line:498
|vpiName:selected_csr
|vpiFullName:work@csr_regs.selected_csr
|vpiRhs:
\_ref_obj: (mip), line:498
|vpiName:mip
|vpiFullName:work@csr_regs.mip
|vpiCaseItem:
\_case_item: , line:500
|vpiExpr:
\_ref_obj: (MCYCLE), line:500
|vpiName:MCYCLE
|vpiFullName:work@csr_regs.MCYCLE
|vpiStmt:
\_assignment: , line:500
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (selected_csr), line:500
|vpiName:selected_csr
|vpiFullName:work@csr_regs.selected_csr
|vpiRhs:
\_part_select: , line:500, parent:mcycle
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (mcycle)
|vpiLeftRange:
\_operation: , line:500
|vpiOpType:11
|vpiOperand:
\_ref_obj: (XLEN), line:500
|vpiName:XLEN
|vpiOperand:
\_constant: , line:500
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:500
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiCaseItem:
\_case_item: , line:501
|vpiExpr:
\_ref_obj: (MINSTRET), line:501
|vpiName:MINSTRET
|vpiFullName:work@csr_regs.MINSTRET
|vpiStmt:
\_assignment: , line:501
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (selected_csr), line:501
|vpiName:selected_csr
|vpiFullName:work@csr_regs.selected_csr
|vpiRhs:
\_part_select: , line:501, parent:minst_ret
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (minst_ret)
|vpiLeftRange:
\_operation: , line:501
|vpiOpType:11
|vpiOperand:
\_ref_obj: (XLEN), line:501
|vpiName:XLEN
|vpiOperand:
\_constant: , line:501
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:501
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiCaseItem:
\_case_item: , line:502
|vpiExpr:
\_ref_obj: (MCYCLEH), line:502
|vpiName:MCYCLEH
|vpiFullName:work@csr_regs.MCYCLEH
|vpiStmt:
\_assignment: , line:502
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (selected_csr), line:502
|vpiName:selected_csr
|vpiFullName:work@csr_regs.selected_csr
|vpiRhs:
\_operation: , line:502
|vpiOpType:67
|vpiOperand:
\_part_select: , line:502, parent:mcycle
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (mcycle)
|vpiLeftRange:
\_operation: , line:502
|vpiOpType:11
|vpiOperand:
\_ref_obj: (COUNTER_W), line:502
|vpiName:COUNTER_W
|vpiFullName:work@csr_regs.COUNTER_W
|vpiOperand:
\_constant: , line:502
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_ref_obj: (XLEN), line:502
|vpiName:XLEN
|vpiFullName:work@csr_regs.XLEN
|vpiTypespec:
\_integer_typespec: , line:502
|INT:32
|vpiCaseItem:
\_case_item: , line:503
|vpiExpr:
\_ref_obj: (MINSTRETH), line:503
|vpiName:MINSTRETH
|vpiFullName:work@csr_regs.MINSTRETH
|vpiStmt:
\_assignment: , line:503
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (selected_csr), line:503
|vpiName:selected_csr
|vpiFullName:work@csr_regs.selected_csr
|vpiRhs:
\_operation: , line:503
|vpiOpType:67
|vpiOperand:
\_part_select: , line:503, parent:minst_ret
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (minst_ret)
|vpiLeftRange:
\_operation: , line:503
|vpiOpType:11
|vpiOperand:
\_ref_obj: (COUNTER_W), line:503
|vpiName:COUNTER_W
|vpiFullName:work@csr_regs.COUNTER_W
|vpiOperand:
\_constant: , line:503
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_ref_obj: (XLEN), line:503
|vpiName:XLEN
|vpiFullName:work@csr_regs.XLEN
|vpiTypespec:
\_integer_typespec: , line:503
|INT:32
|vpiCaseItem:
\_case_item: , line:506
|vpiExpr:
\_ref_obj: (SSTATUS), line:506
|vpiName:SSTATUS
|vpiFullName:work@csr_regs.SSTATUS
|vpiStmt:
\_assignment: , line:506
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (selected_csr), line:506
|vpiName:selected_csr
|vpiFullName:work@csr_regs.selected_csr
|vpiRhs:
\_operation: , line:506
|vpiOpType:28
|vpiOperand:
\_ref_obj: (mstatus), line:506
|vpiName:mstatus
|vpiFullName:work@csr_regs.mstatus
|vpiOperand:
\_ref_obj: (mstatus_smask), line:506
|vpiName:mstatus_smask
|vpiFullName:work@csr_regs.mstatus_smask
|vpiCaseItem:
\_case_item: , line:507
|vpiExpr:
\_ref_obj: (SEDELEG), line:507
|vpiName:SEDELEG
|vpiFullName:work@csr_regs.SEDELEG
|vpiStmt:
\_assignment: , line:507
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (selected_csr), line:507
|vpiName:selected_csr
|vpiFullName:work@csr_regs.selected_csr
|vpiRhs:
\_constant: , line:507
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiCaseItem:
\_case_item: , line:508
|vpiExpr:
\_ref_obj: (SIDELEG), line:508
|vpiName:SIDELEG
|vpiFullName:work@csr_regs.SIDELEG
|vpiStmt:
\_assignment: , line:508
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (selected_csr), line:508
|vpiName:selected_csr
|vpiFullName:work@csr_regs.selected_csr
|vpiRhs:
\_constant: , line:508
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiCaseItem:
\_case_item: , line:509
|vpiExpr:
\_ref_obj: (SIE), line:509
|vpiName:SIE
|vpiFullName:work@csr_regs.SIE
|vpiStmt:
\_assignment: , line:509
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (selected_csr), line:509
|vpiName:selected_csr
|vpiFullName:work@csr_regs.selected_csr
|vpiRhs:
\_operation: , line:509
|vpiOpType:28
|vpiOperand:
\_ref_obj: (mie_reg), line:509
|vpiName:mie_reg
|vpiFullName:work@csr_regs.mie_reg
|vpiOperand:
\_ref_obj: (sie_mask), line:509
|vpiName:sie_mask
|vpiFullName:work@csr_regs.sie_mask
|vpiCaseItem:
\_case_item: , line:510
|vpiExpr:
\_ref_obj: (STVEC), line:510
|vpiName:STVEC
|vpiFullName:work@csr_regs.STVEC
|vpiStmt:
\_assignment: , line:510
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (selected_csr), line:510
|vpiName:selected_csr
|vpiFullName:work@csr_regs.selected_csr
|vpiRhs:
\_ref_obj: (stvec), line:510
|vpiName:stvec
|vpiFullName:work@csr_regs.stvec
|vpiCaseItem:
\_case_item: , line:512
|vpiExpr:
\_ref_obj: (SSCRATCH), line:512
|vpiName:SSCRATCH
|vpiFullName:work@csr_regs.SSCRATCH
|vpiStmt:
\_assignment: , line:512
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (selected_csr), line:512
|vpiName:selected_csr
|vpiFullName:work@csr_regs.selected_csr
|vpiRhs:
\_ref_obj: (scratch_out), line:512
|vpiName:scratch_out
|vpiFullName:work@csr_regs.scratch_out
|vpiCaseItem:
\_case_item: , line:513
|vpiExpr:
\_ref_obj: (SEPC), line:513
|vpiName:SEPC
|vpiFullName:work@csr_regs.SEPC
|vpiStmt:
\_assignment: , line:513
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (selected_csr), line:513
|vpiName:selected_csr
|vpiFullName:work@csr_regs.selected_csr
|vpiRhs:
\_ref_obj: (scratch_out), line:513
|vpiName:scratch_out
|vpiFullName:work@csr_regs.scratch_out
|vpiCaseItem:
\_case_item: , line:514
|vpiExpr:
\_ref_obj: (SCAUSE), line:514
|vpiName:SCAUSE
|vpiFullName:work@csr_regs.SCAUSE
|vpiStmt:
\_assignment: , line:514
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (selected_csr), line:514
|vpiName:selected_csr
|vpiFullName:work@csr_regs.selected_csr
|vpiRhs:
\_ref_obj: (scratch_out), line:514
|vpiName:scratch_out
|vpiFullName:work@csr_regs.scratch_out
|vpiCaseItem:
\_case_item: , line:515
|vpiExpr:
\_ref_obj: (STVAL), line:515
|vpiName:STVAL
|vpiFullName:work@csr_regs.STVAL
|vpiStmt:
\_assignment: , line:515
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (selected_csr), line:515
|vpiName:selected_csr
|vpiFullName:work@csr_regs.selected_csr
|vpiRhs:
\_ref_obj: (scratch_out), line:515
|vpiName:scratch_out
|vpiFullName:work@csr_regs.scratch_out
|vpiCaseItem:
\_case_item: , line:516
|vpiExpr:
\_ref_obj: (SIP), line:516
|vpiName:SIP
|vpiFullName:work@csr_regs.SIP
|vpiStmt:
\_assignment: , line:516
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (selected_csr), line:516
|vpiName:selected_csr
|vpiFullName:work@csr_regs.selected_csr
|vpiRhs:
\_operation: , line:516
|vpiOpType:28
|vpiOperand:
\_ref_obj: (mip), line:516
|vpiName:mip
|vpiFullName:work@csr_regs.mip
|vpiOperand:
\_ref_obj: (sip_mask), line:516
|vpiName:sip_mask
|vpiFullName:work@csr_regs.sip_mask
|vpiCaseItem:
\_case_item: , line:518
|vpiExpr:
\_ref_obj: (SATP), line:518
|vpiName:SATP
|vpiFullName:work@csr_regs.SATP
|vpiStmt:
\_assignment: , line:518
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (selected_csr), line:518
|vpiName:selected_csr
|vpiFullName:work@csr_regs.selected_csr
|vpiRhs:
\_ref_obj: (satp), line:518
|vpiName:satp
|vpiFullName:work@csr_regs.satp
|vpiCaseItem:
\_case_item: , line:522
|vpiExpr:
\_ref_obj: (CYCLE), line:522
|vpiName:CYCLE
|vpiFullName:work@csr_regs.CYCLE
|vpiStmt:
\_assignment: , line:522
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (selected_csr), line:522
|vpiName:selected_csr
|vpiFullName:work@csr_regs.selected_csr
|vpiRhs:
\_part_select: , line:522, parent:mcycle
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (mcycle)
|vpiLeftRange:
\_operation: , line:522
|vpiOpType:11
|vpiOperand:
\_ref_obj: (XLEN), line:522
|vpiName:XLEN
|vpiOperand:
\_constant: , line:522
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:522
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiCaseItem:
\_case_item: , line:523
|vpiExpr:
\_ref_obj: (TIME), line:523
|vpiName:TIME
|vpiFullName:work@csr_regs.TIME
|vpiStmt:
\_assignment: , line:523
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (selected_csr), line:523
|vpiName:selected_csr
|vpiFullName:work@csr_regs.selected_csr
|vpiRhs:
\_part_select: , line:523, parent:mcycle
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (mcycle)
|vpiLeftRange:
\_operation: , line:523
|vpiOpType:11
|vpiOperand:
\_ref_obj: (XLEN), line:523
|vpiName:XLEN
|vpiOperand:
\_constant: , line:523
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:523
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiCaseItem:
\_case_item: , line:524
|vpiExpr:
\_ref_obj: (INSTRET), line:524
|vpiName:INSTRET
|vpiFullName:work@csr_regs.INSTRET
|vpiStmt:
\_assignment: , line:524
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (selected_csr), line:524
|vpiName:selected_csr
|vpiFullName:work@csr_regs.selected_csr
|vpiRhs:
\_part_select: , line:524, parent:minst_ret
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (minst_ret)
|vpiLeftRange:
\_operation: , line:524
|vpiOpType:11
|vpiOperand:
\_ref_obj: (XLEN), line:524
|vpiName:XLEN
|vpiOperand:
\_constant: , line:524
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:524
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiCaseItem:
\_case_item: , line:525
|vpiExpr:
\_ref_obj: (CYCLEH), line:525
|vpiName:CYCLEH
|vpiFullName:work@csr_regs.CYCLEH
|vpiStmt:
\_assignment: , line:525
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (selected_csr), line:525
|vpiName:selected_csr
|vpiFullName:work@csr_regs.selected_csr
|vpiRhs:
\_operation: , line:525
|vpiOpType:67
|vpiOperand:
\_part_select: , line:525, parent:mcycle
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (mcycle)
|vpiLeftRange:
\_operation: , line:525
|vpiOpType:11
|vpiOperand:
\_ref_obj: (COUNTER_W), line:525
|vpiName:COUNTER_W
|vpiFullName:work@csr_regs.COUNTER_W
|vpiOperand:
\_constant: , line:525
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_ref_obj: (XLEN), line:525
|vpiName:XLEN
|vpiFullName:work@csr_regs.XLEN
|vpiTypespec:
\_integer_typespec: , line:525
|INT:32
|vpiCaseItem:
\_case_item: , line:526
|vpiExpr:
\_ref_obj: (TIMEH), line:526
|vpiName:TIMEH
|vpiFullName:work@csr_regs.TIMEH
|vpiStmt:
\_assignment: , line:526
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (selected_csr), line:526
|vpiName:selected_csr
|vpiFullName:work@csr_regs.selected_csr
|vpiRhs:
\_operation: , line:526
|vpiOpType:67
|vpiOperand:
\_part_select: , line:526, parent:mcycle
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (mcycle)
|vpiLeftRange:
\_operation: , line:526
|vpiOpType:11
|vpiOperand:
\_ref_obj: (COUNTER_W), line:526
|vpiName:COUNTER_W
|vpiFullName:work@csr_regs.COUNTER_W
|vpiOperand:
\_constant: , line:526
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_ref_obj: (XLEN), line:526
|vpiName:XLEN
|vpiFullName:work@csr_regs.XLEN
|vpiTypespec:
\_integer_typespec: , line:526
|INT:32
|vpiCaseItem:
\_case_item: , line:527
|vpiExpr:
\_ref_obj: (INSTRETH), line:527
|vpiName:INSTRETH
|vpiFullName:work@csr_regs.INSTRETH
|vpiStmt:
\_assignment: , line:527
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (selected_csr), line:527
|vpiName:selected_csr
|vpiFullName:work@csr_regs.selected_csr
|vpiRhs:
\_operation: , line:527
|vpiOpType:67
|vpiOperand:
\_part_select: , line:527, parent:minst_ret
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (minst_ret)
|vpiLeftRange:
\_operation: , line:527
|vpiOpType:11
|vpiOperand:
\_ref_obj: (COUNTER_W), line:527
|vpiName:COUNTER_W
|vpiFullName:work@csr_regs.COUNTER_W
|vpiOperand:
\_constant: , line:527
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_ref_obj: (XLEN), line:527
|vpiName:XLEN
|vpiFullName:work@csr_regs.XLEN
|vpiTypespec:
\_integer_typespec: , line:527
|INT:32
|vpiCaseItem:
\_case_item: , line:529
|vpiStmt:
\_begin: , line:529
|vpiFullName:work@csr_regs
|vpiStmt:
\_assignment: , line:529
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (selected_csr), line:529
|vpiName:selected_csr
|vpiFullName:work@csr_regs.selected_csr
|vpiRhs:
\_constant: , line:529
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiStmt:
\_assignment: , line:529
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (invalid_addr), line:529
|vpiName:invalid_addr
|vpiFullName:work@csr_regs.invalid_addr
|vpiRhs:
\_constant: , line:529
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiProcess:
\_always: , line:533
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:533
|vpiCondition:
\_operation: , line:533
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:533
|vpiName:clk
|vpiFullName:work@csr_regs.clk
|vpiStmt:
\_begin: , line:533
|vpiFullName:work@csr_regs
|vpiStmt:
\_if_else: , line:534
|vpiCondition:
\_ref_obj: (read_regs), line:534
|vpiName:read_regs
|vpiFullName:work@csr_regs.read_regs
|vpiStmt:
\_assignment: , line:535
|vpiOpType:82
|vpiLhs:
\_ref_obj: (selected_csr_r), line:535
|vpiName:selected_csr_r
|vpiFullName:work@csr_regs.selected_csr_r
|vpiRhs:
\_ref_obj: (selected_csr), line:535
|vpiName:selected_csr
|vpiFullName:work@csr_regs.selected_csr
|vpiElseStmt:
\_assignment: , line:537
|vpiOpType:82
|vpiLhs:
\_ref_obj: (selected_csr_r), line:537
|vpiName:selected_csr_r
|vpiFullName:work@csr_regs.selected_csr_r
|vpiRhs:
\_constant: , line:537
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiPort:
\_port: (clk), line:28
|vpiName:clk
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (clk), line:28
|vpiName:clk
|vpiFullName:work@csr_regs.clk
|vpiNetType:36
|vpiPort:
\_port: (rst), line:29
|vpiName:rst
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (rst), line:29
|vpiName:rst
|vpiFullName:work@csr_regs.rst
|vpiNetType:36
|vpiPort:
\_port: (csr_inputs), line:32
|vpiName:csr_inputs
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (csr_inputs), line:32
|vpiName:csr_inputs
|vpiFullName:work@csr_regs.csr_inputs
|vpiPort:
\_port: (new_request), line:33
|vpiName:new_request
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (new_request), line:33
|vpiName:new_request
|vpiFullName:work@csr_regs.new_request
|vpiPort:
\_port: (read_regs), line:34
|vpiName:read_regs
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (read_regs), line:34
|vpiName:read_regs
|vpiFullName:work@csr_regs.read_regs
|vpiPort:
\_port: (commit), line:35
|vpiName:commit
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (commit), line:35
|vpiName:commit
|vpiFullName:work@csr_regs.commit
|vpiPort:
\_port: (gc_exception), line:36
|vpiName:gc_exception
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (gc_exception), line:36
|vpiName:gc_exception
|vpiFullName:work@csr_regs.gc_exception
|vpiPort:
\_port: (csr_exception), line:37
|vpiName:csr_exception
|vpiDirection:2
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (csr_exception), line:37
|vpiName:csr_exception
|vpiFullName:work@csr_regs.csr_exception
|vpiPort:
\_port: (current_privilege), line:38
|vpiName:current_privilege
|vpiDirection:2
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (current_privilege), line:38
|vpiName:current_privilege
|vpiFullName:work@csr_regs.current_privilege
|vpiNetType:36
|vpiPort:
\_port: (instruction_issued_no_rd), line:41
|vpiName:instruction_issued_no_rd
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (instruction_issued_no_rd), line:41
|vpiName:instruction_issued_no_rd
|vpiFullName:work@csr_regs.instruction_issued_no_rd
|vpiNetType:36
|vpiPort:
\_port: (mret), line:44
|vpiName:mret
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (mret), line:44
|vpiName:mret
|vpiFullName:work@csr_regs.mret
|vpiNetType:36
|vpiPort:
\_port: (sret), line:45
|vpiName:sret
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (sret), line:45
|vpiName:sret
|vpiFullName:work@csr_regs.sret
|vpiNetType:36
|vpiPort:
\_port: (tlb_on), line:48
|vpiName:tlb_on
|vpiDirection:2
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (tlb_on), line:48
|vpiName:tlb_on
|vpiFullName:work@csr_regs.tlb_on
|vpiNetType:36
|vpiPort:
\_port: (asid), line:49
|vpiName:asid
|vpiDirection:2
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (asid), line:49
|vpiName:asid
|vpiFullName:work@csr_regs.asid
|vpiNetType:36
|vpiPort:
\_port: (immu), line:52
|vpiName:immu
|vpiDirection:5
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_modport: (csr)
|vpiPort:
\_port: (dmmu), line:53
|vpiName:dmmu
|vpiDirection:5
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_modport: (csr)
|vpiPort:
\_port: (instruction_complete), line:56
|vpiName:instruction_complete
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (instruction_complete), line:56
|vpiName:instruction_complete
|vpiFullName:work@csr_regs.instruction_complete
|vpiNetType:36
|vpiPort:
\_port: (interrupt), line:60
|vpiName:interrupt
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (interrupt), line:60
|vpiName:interrupt
|vpiFullName:work@csr_regs.interrupt
|vpiNetType:36
|vpiPort:
\_port: (timer_interrupt), line:61
|vpiName:timer_interrupt
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (timer_interrupt), line:61
|vpiName:timer_interrupt
|vpiFullName:work@csr_regs.timer_interrupt
|vpiNetType:36
|vpiPort:
\_port: (wb_csr), line:63
|vpiName:wb_csr
|vpiDirection:2
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (wb_csr), line:63
|vpiName:wb_csr
|vpiFullName:work@csr_regs.wb_csr
|vpiNetType:36
|vpiPort:
\_port: (trap_pc), line:64
|vpiName:trap_pc
|vpiDirection:2
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (trap_pc), line:64
|vpiName:trap_pc
|vpiFullName:work@csr_regs.trap_pc
|vpiNetType:36
|vpiPort:
\_port: (csr_mepc), line:65
|vpiName:csr_mepc
|vpiDirection:2
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (csr_mepc), line:65
|vpiName:csr_mepc
|vpiFullName:work@csr_regs.csr_mepc
|vpiNetType:36
|vpiPort:
\_port: (csr_sepc), line:66
|vpiName:csr_sepc
|vpiDirection:2
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (csr_sepc), line:66
|vpiName:csr_sepc
|vpiFullName:work@csr_regs.csr_sepc
|vpiNetType:36
|vpiContAssign:
\_cont_assign: , line:145
|vpiRhs:
\_ref_obj: (satp.mode), line:145
|vpiName:satp.mode
|vpiFullName:work@csr_regs.satp.mode
|vpiLhs:
\_ref_obj: (tlb_on), line:145
|vpiName:tlb_on
|vpiFullName:work@csr_regs.tlb_on
|vpiContAssign:
\_cont_assign: , line:146
|vpiRhs:
\_ref_obj: (satp.asid), line:146
|vpiName:satp.asid
|vpiFullName:work@csr_regs.satp.asid
|vpiLhs:
\_ref_obj: (asid), line:146
|vpiName:asid
|vpiFullName:work@csr_regs.asid
|vpiContAssign:
\_cont_assign: , line:150
|vpiRhs:
\_ref_obj: (mstatus.mxr), line:150
|vpiName:mstatus.mxr
|vpiFullName:work@csr_regs.mstatus.mxr
|vpiLhs:
\_ref_obj: (immu.mxr), line:150
|vpiName:immu.mxr
|vpiFullName:work@csr_regs.immu.mxr
|vpiContAssign:
\_cont_assign: , line:151
|vpiRhs:
\_ref_obj: (mstatus.mxr), line:151
|vpiName:mstatus.mxr
|vpiFullName:work@csr_regs.mstatus.mxr
|vpiLhs:
\_ref_obj: (dmmu.mxr), line:151
|vpiName:dmmu.mxr
|vpiFullName:work@csr_regs.dmmu.mxr
|vpiContAssign:
\_cont_assign: , line:152
|vpiRhs:
\_ref_obj: (mstatus.sum), line:152
|vpiName:mstatus.sum
|vpiFullName:work@csr_regs.mstatus.sum
|vpiLhs:
\_ref_obj: (immu.pum), line:152
|vpiName:immu.pum
|vpiFullName:work@csr_regs.immu.pum
|vpiContAssign:
\_cont_assign: , line:153
|vpiRhs:
\_ref_obj: (mstatus.sum), line:153
|vpiName:mstatus.sum
|vpiFullName:work@csr_regs.mstatus.sum
|vpiLhs:
\_ref_obj: (dmmu.pum), line:153
|vpiName:dmmu.pum
|vpiFullName:work@csr_regs.dmmu.pum
|vpiContAssign:
\_cont_assign: , line:154
|vpiRhs:
\_ref_obj: (privilege_level), line:154
|vpiName:privilege_level
|vpiFullName:work@csr_regs.privilege_level
|vpiLhs:
\_ref_obj: (immu.privilege), line:154
|vpiName:immu.privilege
|vpiFullName:work@csr_regs.immu.privilege
|vpiContAssign:
\_cont_assign: , line:155
|vpiRhs:
\_operation: , line:155
|vpiOpType:32
|vpiOperand:
\_ref_obj: (mstatus.mprv), line:155
|vpiName:mstatus.mprv
|vpiFullName:work@csr_regs.mstatus.mprv
|vpiOperand:
\_ref_obj: (mstatus.mpp), line:155
|vpiName:mstatus.mpp
|vpiFullName:work@csr_regs.mstatus.mpp
|vpiOperand:
\_ref_obj: (privilege_level), line:155
|vpiName:privilege_level
|vpiFullName:work@csr_regs.privilege_level
|vpiLhs:
\_ref_obj: (dmmu.privilege), line:155
|vpiName:dmmu.privilege
|vpiFullName:work@csr_regs.dmmu.privilege
|vpiContAssign:
\_cont_assign: , line:156
|vpiRhs:
\_ref_obj: (satp.ppn), line:156
|vpiName:satp.ppn
|vpiFullName:work@csr_regs.satp.ppn
|vpiLhs:
\_ref_obj: (immu.ppn), line:156
|vpiName:immu.ppn
|vpiFullName:work@csr_regs.immu.ppn
|vpiContAssign:
\_cont_assign: , line:157
|vpiRhs:
\_ref_obj: (satp.ppn), line:157
|vpiName:satp.ppn
|vpiFullName:work@csr_regs.satp.ppn
|vpiLhs:
\_ref_obj: (dmmu.ppn), line:157
|vpiName:dmmu.ppn
|vpiFullName:work@csr_regs.dmmu.ppn
|vpiContAssign:
\_cont_assign: , line:169
|vpiRhs:
\_ref_obj: (csr_inputs.csr_addr), line:169
|vpiName:csr_inputs.csr_addr
|vpiFullName:work@csr_regs.csr_inputs.csr_addr
|vpiLhs:
\_ref_obj: (csr_addr), line:169
|vpiName:csr_addr
|vpiFullName:work@csr_regs.csr_addr
|vpiContAssign:
\_cont_assign: , line:170
|vpiRhs:
\_operation: , line:170
|vpiOpType:28
|vpiOperand:
\_ref_obj: (new_request), line:170
|vpiName:new_request
|vpiFullName:work@csr_regs.new_request
|vpiOperand:
\_operation: , line:170
|vpiOpType:18
|vpiOperand:
\_ref_obj: (csr_addr.privilege), line:170
|vpiName:csr_addr.privilege
|vpiFullName:work@csr_regs.csr_addr.privilege
|vpiOperand:
\_ref_obj: (privilege_level), line:170
|vpiName:privilege_level
|vpiFullName:work@csr_regs.privilege_level
|vpiLhs:
\_ref_obj: (privilege_exception), line:170
|vpiName:privilege_exception
|vpiFullName:work@csr_regs.privilege_exception
|vpiContAssign:
\_cont_assign: , line:172
|vpiRhs:
\_operation: , line:172
|vpiOpType:26
|vpiOperand:
\_operation: , line:172
|vpiOpType:26
|vpiOperand:
\_ref_obj: (commit), line:172
|vpiName:commit
|vpiFullName:work@csr_regs.commit
|vpiOperand:
\_operation: , line:172
|vpiOpType:3
|vpiOperand:
\_ref_obj: (privilege_exception), line:172
|vpiName:privilege_exception
|vpiFullName:work@csr_regs.privilege_exception
|vpiOperand:
\_operation: , line:172
|vpiOpType:26
|vpiOperand:
\_operation: , line:172
|vpiOpType:15
|vpiOperand:
\_ref_obj: (csr_addr.rw_bits), line:172
|vpiName:csr_addr.rw_bits
|vpiFullName:work@csr_regs.csr_addr.rw_bits
|vpiOperand:
\_ref_obj: (CSR_READ_ONLY), line:172
|vpiName:CSR_READ_ONLY
|vpiFullName:work@csr_regs.CSR_READ_ONLY
|vpiOperand:
\_operation: , line:172
|vpiOpType:14
|vpiOperand:
\_ref_obj: (csr_addr.privilege), line:172
|vpiName:csr_addr.privilege
|vpiFullName:work@csr_regs.csr_addr.privilege
|vpiOperand:
\_ref_obj: (SUPERVISOR_PRIVILEGE), line:172
|vpiName:SUPERVISOR_PRIVILEGE
|vpiFullName:work@csr_regs.SUPERVISOR_PRIVILEGE
|vpiLhs:
\_ref_obj: (supervisor_write), line:172
|vpiName:supervisor_write
|vpiFullName:work@csr_regs.supervisor_write
|vpiContAssign:
\_cont_assign: , line:173
|vpiRhs:
\_operation: , line:173
|vpiOpType:26
|vpiOperand:
\_operation: , line:173
|vpiOpType:26
|vpiOperand:
\_ref_obj: (commit), line:173
|vpiName:commit
|vpiFullName:work@csr_regs.commit
|vpiOperand:
\_operation: , line:173
|vpiOpType:3
|vpiOperand:
\_ref_obj: (privilege_exception), line:173
|vpiName:privilege_exception
|vpiFullName:work@csr_regs.privilege_exception
|vpiOperand:
\_operation: , line:173
|vpiOpType:26
|vpiOperand:
\_operation: , line:173
|vpiOpType:15
|vpiOperand:
\_ref_obj: (csr_addr.rw_bits), line:173
|vpiName:csr_addr.rw_bits
|vpiFullName:work@csr_regs.csr_addr.rw_bits
|vpiOperand:
\_ref_obj: (CSR_READ_ONLY), line:173
|vpiName:CSR_READ_ONLY
|vpiFullName:work@csr_regs.CSR_READ_ONLY
|vpiOperand:
\_operation: , line:173
|vpiOpType:14
|vpiOperand:
\_ref_obj: (csr_addr.privilege), line:173
|vpiName:csr_addr.privilege
|vpiFullName:work@csr_regs.csr_addr.privilege
|vpiOperand:
\_ref_obj: (MACHINE_PRIVILEGE), line:173
|vpiName:MACHINE_PRIVILEGE
|vpiFullName:work@csr_regs.MACHINE_PRIVILEGE
|vpiLhs:
\_ref_obj: (machine_write), line:173
|vpiName:machine_write
|vpiFullName:work@csr_regs.machine_write
|vpiContAssign:
\_cont_assign: , line:176
|vpiRhs:
\_operation: , line:176
|vpiOpType:29
|vpiOperand:
\_ref_obj: (invalid_addr), line:176
|vpiName:invalid_addr
|vpiFullName:work@csr_regs.invalid_addr
|vpiOperand:
\_ref_obj: (privilege_exception), line:176
|vpiName:privilege_exception
|vpiFullName:work@csr_regs.privilege_exception
|vpiLhs:
\_ref_obj: (illegal_instruction), line:176
|vpiName:illegal_instruction
|vpiFullName:work@csr_regs.illegal_instruction
|vpiContAssign:
\_cont_assign: , line:177
|vpiRhs:
\_operation: , line:177
|vpiOpType:28
|vpiOperand:
\_ref_obj: (new_request), line:177
|vpiName:new_request
|vpiFullName:work@csr_regs.new_request
|vpiOperand:
\_ref_obj: (illegal_instruction), line:177
|vpiName:illegal_instruction
|vpiFullName:work@csr_regs.illegal_instruction
|vpiLhs:
\_ref_obj: (csr_exception.valid), line:177
|vpiName:csr_exception.valid
|vpiFullName:work@csr_regs.csr_exception.valid
|vpiContAssign:
\_cont_assign: , line:179
|vpiRhs:
\_operation: , line:179
|vpiOpType:26
|vpiOperand:
\_ref_obj: (gc_exception.valid), line:179
|vpiName:gc_exception.valid
|vpiFullName:work@csr_regs.gc_exception.valid
|vpiOperand:
\_operation: , line:179
|vpiOpType:14
|vpiOperand:
\_ref_obj: (next_privilege_level), line:179
|vpiName:next_privilege_level
|vpiFullName:work@csr_regs.next_privilege_level
|vpiOperand:
\_ref_obj: (MACHINE_PRIVILEGE), line:179
|vpiName:MACHINE_PRIVILEGE
|vpiFullName:work@csr_regs.MACHINE_PRIVILEGE
|vpiLhs:
\_ref_obj: (machine_trap), line:179
|vpiName:machine_trap
|vpiFullName:work@csr_regs.machine_trap
|vpiContAssign:
\_cont_assign: , line:180
|vpiRhs:
\_operation: , line:180
|vpiOpType:26
|vpiOperand:
\_ref_obj: (gc_exception.valid), line:180
|vpiName:gc_exception.valid
|vpiFullName:work@csr_regs.gc_exception.valid
|vpiOperand:
\_operation: , line:180
|vpiOpType:14
|vpiOperand:
\_ref_obj: (next_privilege_level), line:180
|vpiName:next_privilege_level
|vpiFullName:work@csr_regs.next_privilege_level
|vpiOperand:
\_ref_obj: (SUPERVISOR_PRIVILEGE), line:180
|vpiName:SUPERVISOR_PRIVILEGE
|vpiFullName:work@csr_regs.SUPERVISOR_PRIVILEGE
|vpiLhs:
\_ref_obj: (supervisor_trap), line:180
|vpiName:supervisor_trap
|vpiFullName:work@csr_regs.supervisor_trap
|vpiContAssign:
\_cont_assign: , line:540
|vpiRhs:
\_ref_obj: (selected_csr_r), line:540
|vpiName:selected_csr_r
|vpiFullName:work@csr_regs.selected_csr_r
|vpiLhs:
\_ref_obj: (wb_csr), line:540
|vpiName:wb_csr
|vpiFullName:work@csr_regs.wb_csr
|vpiNet:
\_logic_net: (clk), line:28
|vpiNet:
\_logic_net: (rst), line:29
|vpiNet:
\_logic_net: (csr_inputs), line:32
|vpiNet:
\_logic_net: (new_request), line:33
|vpiNet:
\_logic_net: (read_regs), line:34
|vpiNet:
\_logic_net: (commit), line:35
|vpiNet:
\_logic_net: (gc_exception), line:36
|vpiNet:
\_logic_net: (csr_exception), line:37
|vpiNet:
\_logic_net: (current_privilege), line:38
|vpiNet:
\_logic_net: (instruction_issued_no_rd), line:41
|vpiNet:
\_logic_net: (mret), line:44
|vpiNet:
\_logic_net: (sret), line:45
|vpiNet:
\_logic_net: (tlb_on), line:48
|vpiNet:
\_logic_net: (asid), line:49
|vpiNet:
\_logic_net: (instruction_complete), line:56
|vpiNet:
\_logic_net: (interrupt), line:60
|vpiNet:
\_logic_net: (timer_interrupt), line:61
|vpiNet:
\_logic_net: (wb_csr), line:63
|vpiNet:
\_logic_net: (trap_pc), line:64
|vpiNet:
\_logic_net: (csr_mepc), line:65
|vpiNet:
\_logic_net: (csr_sepc), line:66
|vpiNet:
\_logic_net: (misa), line:69
|vpiName:misa
|vpiFullName:work@csr_regs.misa
|vpiNet:
\_logic_net: (mvendorid), line:71
|vpiName:mvendorid
|vpiFullName:work@csr_regs.mvendorid
|vpiNet:
\_logic_net: (marchid), line:72
|vpiName:marchid
|vpiFullName:work@csr_regs.marchid
|vpiNet:
\_logic_net: (mimpid), line:73
|vpiName:mimpid
|vpiFullName:work@csr_regs.mimpid
|vpiNet:
\_logic_net: (mhartid), line:74
|vpiName:mhartid
|vpiFullName:work@csr_regs.mhartid
|vpiNet:
\_logic_net: (mstatus), line:78
|vpiName:mstatus
|vpiFullName:work@csr_regs.mstatus
|vpiNet:
\_logic_net: (mstatus_smask), line:79
|vpiName:mstatus_smask
|vpiFullName:work@csr_regs.mstatus_smask
|vpiNet:
\_logic_net: (privilege_level), line:80
|vpiName:privilege_level
|vpiFullName:work@csr_regs.privilege_level
|vpiNetType:36
|vpiNet:
\_logic_net: (next_privilege_level), line:80
|vpiName:next_privilege_level
|vpiFullName:work@csr_regs.next_privilege_level
|vpiNetType:36
|vpiNet:
\_logic_net: (scratch_regs), line:83
|vpiName:scratch_regs
|vpiFullName:work@csr_regs.scratch_regs
|vpiNetType:36
|vpiNet:
\_logic_net: (scratch_out), line:84
|vpiName:scratch_out
|vpiFullName:work@csr_regs.scratch_out
|vpiNetType:36
|vpiNet:
\_logic_net: (mtvec), line:87
|vpiName:mtvec
|vpiFullName:work@csr_regs.mtvec
|vpiNetType:36
|vpiNet:
\_logic_net: (medeleg), line:88
|vpiName:medeleg
|vpiFullName:work@csr_regs.medeleg
|vpiNetType:36
|vpiNet:
\_logic_net: (mideleg), line:89
|vpiName:mideleg
|vpiFullName:work@csr_regs.mideleg
|vpiNetType:36
|vpiNet:
\_logic_net: (mip), line:90
|vpiName:mip
|vpiFullName:work@csr_regs.mip
|vpiNet:
\_logic_net: (mip_mask), line:90
|vpiName:mip_mask
|vpiFullName:work@csr_regs.mip_mask
|vpiNet:
\_logic_net: (mie_reg), line:91
|vpiName:mie_reg
|vpiFullName:work@csr_regs.mie_reg
|vpiNet:
\_logic_net: (mie_mask), line:91
|vpiName:mie_mask
|vpiFullName:work@csr_regs.mie_mask
|vpiNet:
\_logic_net: (mepc), line:93
|vpiName:mepc
|vpiFullName:work@csr_regs.mepc
|vpiNetType:36
|vpiNet:
\_logic_net: (mtimecmp), line:95
|vpiName:mtimecmp
|vpiFullName:work@csr_regs.mtimecmp
|vpiNetType:36
|vpiNet:
\_logic_net: (mcause), line:97
|vpiName:mcause
|vpiFullName:work@csr_regs.mcause
|vpiNet:
\_logic_net: (mtval), line:98
|vpiName:mtval
|vpiFullName:work@csr_regs.mtval
|vpiNetType:36
|vpiNet:
\_logic_net: (sip_mask), line:100
|vpiName:sip_mask
|vpiFullName:work@csr_regs.sip_mask
|vpiNet:
\_logic_net: (sie_mask), line:101
|vpiName:sie_mask
|vpiFullName:work@csr_regs.sie_mask
|vpiNet:
\_logic_net: (sepc), line:102
|vpiName:sepc
|vpiFullName:work@csr_regs.sepc
|vpiNetType:36
|vpiNet:
\_logic_net: (stime), line:104
|vpiName:stime
|vpiFullName:work@csr_regs.stime
|vpiNetType:36
|vpiNet:
\_logic_net: (stimecmp), line:105
|vpiName:stimecmp
|vpiFullName:work@csr_regs.stimecmp
|vpiNetType:36
|vpiNet:
\_logic_net: (scause), line:107
|vpiName:scause
|vpiFullName:work@csr_regs.scause
|vpiNetType:36
|vpiNet:
\_logic_net: (stval), line:108
|vpiName:stval
|vpiFullName:work@csr_regs.stval
|vpiNetType:36
|vpiNet:
\_logic_net: (sstatus), line:110
|vpiName:sstatus
|vpiFullName:work@csr_regs.sstatus
|vpiNetType:36
|vpiNet:
\_logic_net: (stvec), line:111
|vpiName:stvec
|vpiFullName:work@csr_regs.stvec
|vpiNetType:36
|vpiNet:
\_logic_net: (satp), line:113
|vpiName:satp
|vpiFullName:work@csr_regs.satp
|vpiNet:
\_logic_net: (mcycle), line:115
|vpiName:mcycle
|vpiFullName:work@csr_regs.mcycle
|vpiNetType:36
|vpiNet:
\_logic_net: (mtime), line:116
|vpiName:mtime
|vpiFullName:work@csr_regs.mtime
|vpiNetType:36
|vpiNet:
\_logic_net: (minst_ret), line:117
|vpiName:minst_ret
|vpiFullName:work@csr_regs.minst_ret
|vpiNetType:36
|vpiNet:
\_logic_net: (inst_ret_inc), line:118
|vpiName:inst_ret_inc
|vpiFullName:work@csr_regs.inst_ret_inc
|vpiNetType:36
|vpiNet:
\_logic_net: (supervisor_write), line:121
|vpiName:supervisor_write
|vpiFullName:work@csr_regs.supervisor_write
|vpiNetType:36
|vpiNet:
\_logic_net: (machine_write), line:122
|vpiName:machine_write
|vpiFullName:work@csr_regs.machine_write
|vpiNetType:36
|vpiNet:
\_logic_net: (csr_addr), line:125
|vpiName:csr_addr
|vpiFullName:work@csr_regs.csr_addr
|vpiNet:
\_logic_net: (privilege_exception), line:126
|vpiName:privilege_exception
|vpiFullName:work@csr_regs.privilege_exception
|vpiNetType:36
|vpiNet:
\_logic_net: (selected_csr), line:128
|vpiName:selected_csr
|vpiFullName:work@csr_regs.selected_csr
|vpiNetType:36
|vpiNet:
\_logic_net: (selected_csr_r), line:129
|vpiName:selected_csr_r
|vpiFullName:work@csr_regs.selected_csr_r
|vpiNetType:36
|vpiNet:
\_logic_net: (updated_csr), line:131
|vpiName:updated_csr
|vpiFullName:work@csr_regs.updated_csr
|vpiNetType:36
|vpiNet:
\_logic_net: (invalid_addr), line:133
|vpiName:invalid_addr
|vpiFullName:work@csr_regs.invalid_addr
|vpiNetType:36
|vpiNet:
\_logic_net: (machine_trap), line:135
|vpiName:machine_trap
|vpiFullName:work@csr_regs.machine_trap
|vpiNetType:36
|vpiNet:
\_logic_net: (supervisor_trap), line:136
|vpiName:supervisor_trap
|vpiFullName:work@csr_regs.supervisor_trap
|vpiNetType:36
|vpiNet:
\_logic_net: (done), line:138
|vpiName:done
|vpiFullName:work@csr_regs.done
|vpiNetType:36
|vpiNet:
\_logic_net: (swrite_decoder), line:140
|vpiName:swrite_decoder
|vpiFullName:work@csr_regs.swrite_decoder
|vpiNetType:36
|vpiNet:
\_logic_net: (mwrite_decoder), line:141
|vpiName:mwrite_decoder
|vpiFullName:work@csr_regs.mwrite_decoder
|vpiNetType:36
|vpiNet:
\_logic_net: (illegal_instruction), line:175
|vpiName:illegal_instruction
|vpiFullName:work@csr_regs.illegal_instruction
|vpiNetType:36
|vpiNet:
\_logic_net: (immu), line:52
|vpiName:immu
|vpiFullName:work@csr_regs.immu
|vpiNet:
\_logic_net: (dmmu), line:53
|vpiName:dmmu
|vpiFullName:work@csr_regs.dmmu
|vpiTypedef:
\_struct_typespec: (alu_inputs_t), line:301
|vpiTypedef:
\_enum_typespec: (alu_logic_op_t), line:84
|vpiTypedef:
\_enum_typespec: (alu_op_t), line:91
|vpiTypedef:
\_enum_typespec: (alu_rs1_op_t), line:97
|vpiTypedef:
\_enum_typespec: (alu_rs2_op_t), line:104
|vpiTypedef:
\_struct_typespec: (amo_alu_inputs_t), line:356
|vpiTypedef:
\_struct_typespec: (amo_details_t), line:362
|vpiTypedef:
\_enum_typespec: (amo_t), line:354
|vpiTypedef:
\_struct_typespec: (branch_inputs_t), line:313
|vpiTypedef:
\_logic_typespec: (branch_predictor_metadata_t), line:32
|vpiTypedef:
\_struct_typespec: (branch_results_t), line:330
|vpiTypedef:
\_enum_typespec: (bus_type_t), line:86
|vpiTypedef:
\_struct_typespec: (csr_addr_t), line:37
|vpiTypedef:
\_struct_typespec: (csr_inputs_t), line:396
|vpiTypedef:
\_enum_typespec: (csr_op_t), line:218
|vpiTypedef:
\_enum_typespec: (csr_t), line:201
|vpiTypedef:
\_struct_typespec: (data_access_shared_inputs_t), line:427
|vpiTypedef:
\_struct_typespec: (div_inputs_t), line:389
|vpiTypedef:
\_enum_typespec: (div_type), line:66
|vpiTypedef:
\_enum_typespec: (exception_code_t), line:245
|vpiTypedef:
\_struct_typespec: (exception_packet_t), line:263
|vpiTypedef:
\_struct_typespec: (fetch_buffer_packet_t), line:276
|vpiTypedef:
\_enum_typespec: (fifo_type_t), line:440
|vpiTypedef:
\_enum_typespec: (fn3_arith_t), line:76
|vpiTypedef:
\_enum_typespec: (fn3_branch_t), line:126
|vpiTypedef:
\_enum_typespec: (fn3_csr_t), line:212
|vpiTypedef:
\_enum_typespec: (fn3_ls_t), line:115
|vpiTypedef:
\_enum_typespec: (fn3_mul_div_t), line:138
|vpiTypedef:
\_struct_typespec: (gc_inputs_t), line:404
|vpiTypedef:
\_struct_typespec: (inflight_instruction_packet), line:271
|vpiTypedef:
\_logic_typespec: (instruction_id_t), line:30
|vpiTypedef:
\_enum_typespec: (interrupt_code_t), line:261
|vpiTypedef:
\_struct_typespec: (load_store_inputs_t), line:369
|vpiTypedef:
\_struct_typespec: (mcause_t), line:135
|vpiTypedef:
\_struct_typespec: (mie_t), line:119
|vpiTypedef:
\_struct_typespec: (mip_t), line:103
|vpiTypedef:
\_struct_typespec: (misa_t), line:45
|vpiTypedef:
\_struct_typespec: (mstatus_t), line:78
|vpiTypedef:
\_struct_typespec: (mul_inputs_t), line:383
|vpiTypedef:
\_enum_typespec: (opcodes_t), line:48
|vpiTypedef:
\_enum_typespec: (opcodes_trimmed_t), line:65
|vpiTypedef:
\_enum_typespec: (privilege_t), line:34
|vpiTypedef:
\_struct_typespec: (satp_t), line:142
|vpiTypedef:
\_struct_typespec: (simulation_named_regfile), line:476
|vpiTypedef:
\_struct_typespec: (taiga_trace_events_t), line:442
|vpiTypedef:
\_struct_typespec: (to_l1_arbiter_packet), line:418
|vpiTypedef:
\_struct_typespec: (trace_outputs_t), line:469
|vpiTypedef:
\_logic_typespec: (unit_id_t), line:31
|vpiTypedef:
\_struct_typespec: (unit_writeback_t), line:295
|vpiTypedef:
\_enum_typespec: (vm_t), line:223
|uhdmallModules:
\_module: work@cycler, file:third_party/cores/taiga/core/cycler.sv, line:24, parent:work@div_unit_core_wrapper
|vpiDefName:work@cycler
|vpiFullName:work@cycler
|vpiPort:
\_port: (clk), line:29
|vpiName:clk
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (clk), line:29
|vpiName:clk
|vpiFullName:work@cycler.clk
|vpiNetType:36
|vpiPort:
\_port: (rst), line:30
|vpiName:rst
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (rst), line:30
|vpiName:rst
|vpiFullName:work@cycler.rst
|vpiNetType:36
|vpiPort:
\_port: (en), line:31
|vpiName:en
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (en), line:31
|vpiName:en
|vpiFullName:work@cycler.en
|vpiNetType:36
|vpiPort:
\_port: (one_hot), line:32
|vpiName:one_hot
|vpiDirection:2
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (one_hot), line:32
|vpiName:one_hot
|vpiFullName:work@cycler.one_hot
|vpiNetType:36
|vpiNet:
\_logic_net: (clk), line:29
|vpiNet:
\_logic_net: (rst), line:30
|vpiNet:
\_logic_net: (en), line:31
|vpiNet:
\_logic_net: (one_hot), line:32
|vpiParamAssign:
\_param_assign: , line:26
|vpiRhs:
\_constant: , line:26
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiLhs:
\_parameter: (C_WIDTH), line:26
|vpiName:C_WIDTH
|vpiParameter:
\_parameter: (C_WIDTH), line:26
|uhdmallModules:
\_module: work@dbram, file:third_party/cores/taiga/core/dbram.sv, line:26, parent:work@div_unit_core_wrapper
|vpiDefName:work@dbram
|vpiFullName:work@dbram
|vpiProcess:
\_always: , line:45
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:45
|vpiCondition:
\_operation: , line:45
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:45
|vpiName:clk
|vpiFullName:work@dbram.clk
|vpiStmt:
\_begin: , line:45
|vpiFullName:work@dbram
|vpiStmt:
\_if_else: , line:46
|vpiCondition:
\_ref_obj: (rst), line:46
|vpiName:rst
|vpiFullName:work@dbram.rst
|vpiStmt:
\_assignment: , line:47
|vpiOpType:82
|vpiLhs:
\_ref_obj: (ls.data_valid), line:47
|vpiName:ls.data_valid
|vpiFullName:work@dbram.ls.data_valid
|vpiRhs:
\_constant: , line:47
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiElseStmt:
\_assignment: , line:49
|vpiOpType:82
|vpiLhs:
\_ref_obj: (ls.data_valid), line:49
|vpiName:ls.data_valid
|vpiFullName:work@dbram.ls.data_valid
|vpiRhs:
\_operation: , line:49
|vpiOpType:28
|vpiOperand:
\_ref_obj: (ls.new_request), line:49
|vpiName:ls.new_request
|vpiFullName:work@dbram.ls.new_request
|vpiOperand:
\_ref_obj: (ls_inputs.load), line:49
|vpiName:ls_inputs.load
|vpiFullName:work@dbram.ls_inputs.load
|vpiPort:
\_port: (clk), line:27
|vpiName:clk
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (clk), line:27
|vpiName:clk
|vpiFullName:work@dbram.clk
|vpiNetType:36
|vpiPort:
\_port: (rst), line:28
|vpiName:rst
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (rst), line:28
|vpiName:rst
|vpiFullName:work@dbram.rst
|vpiNetType:36
|vpiPort:
\_port: (ls_inputs), line:30
|vpiName:ls_inputs
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (ls_inputs), line:30
|vpiName:ls_inputs
|vpiFullName:work@dbram.ls_inputs
|vpiPort:
\_port: (ls), line:31
|vpiName:ls
|vpiDirection:5
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_modport: (sub_unit)
|vpiPort:
\_port: (data_out), line:32
|vpiName:data_out
|vpiDirection:2
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (data_out), line:32
|vpiName:data_out
|vpiFullName:work@dbram.data_out
|vpiNetType:36
|vpiPort:
\_port: (data_bram), line:34
|vpiName:data_bram
|vpiDirection:5
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_modport: (master)
|vpiContAssign:
\_cont_assign: , line:37
|vpiRhs:
\_constant: , line:37
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiLhs:
\_ref_obj: (ls.ready), line:37
|vpiName:ls.ready
|vpiFullName:work@dbram.ls.ready
|vpiContAssign:
\_cont_assign: , line:39
|vpiRhs:
\_ref_obj: (ls_inputs.addr), line:39
|vpiName:ls_inputs.addr
|vpiFullName:work@dbram.ls_inputs.addr
|vpiLhs:
\_ref_obj: (data_bram.addr), line:39
|vpiName:data_bram.addr
|vpiFullName:work@dbram.data_bram.addr
|vpiContAssign:
\_cont_assign: , line:40
|vpiRhs:
\_ref_obj: (ls.new_request), line:40
|vpiName:ls.new_request
|vpiFullName:work@dbram.ls.new_request
|vpiLhs:
\_ref_obj: (data_bram.en), line:40
|vpiName:data_bram.en
|vpiFullName:work@dbram.data_bram.en
|vpiContAssign:
\_cont_assign: , line:41
|vpiRhs:
\_ref_obj: (ls_inputs.be), line:41
|vpiName:ls_inputs.be
|vpiFullName:work@dbram.ls_inputs.be
|vpiLhs:
\_ref_obj: (data_bram.be), line:41
|vpiName:data_bram.be
|vpiFullName:work@dbram.data_bram.be
|vpiContAssign:
\_cont_assign: , line:42
|vpiRhs:
\_ref_obj: (ls_inputs.data_in), line:42
|vpiName:ls_inputs.data_in
|vpiFullName:work@dbram.ls_inputs.data_in
|vpiLhs:
\_ref_obj: (data_bram.data_in), line:42
|vpiName:data_bram.data_in
|vpiFullName:work@dbram.data_bram.data_in
|vpiContAssign:
\_cont_assign: , line:43
|vpiRhs:
\_ref_obj: (data_bram.data_out), line:43
|vpiName:data_bram.data_out
|vpiFullName:work@dbram.data_bram.data_out
|vpiLhs:
\_ref_obj: (data_out), line:43
|vpiName:data_out
|vpiFullName:work@dbram.data_out
|vpiNet:
\_logic_net: (clk), line:27
|vpiNet:
\_logic_net: (rst), line:28
|vpiNet:
\_logic_net: (ls_inputs), line:30
|vpiNet:
\_logic_net: (data_out), line:32
|vpiNet:
\_logic_net: (ls), line:31
|vpiName:ls
|vpiFullName:work@dbram.ls
|vpiNet:
\_logic_net: (data_bram), line:34
|vpiName:data_bram
|vpiFullName:work@dbram.data_bram
|vpiTypedef:
\_struct_typespec: (alu_inputs_t), line:301
|vpiTypedef:
\_enum_typespec: (alu_logic_op_t), line:84
|vpiTypedef:
\_enum_typespec: (alu_op_t), line:91
|vpiTypedef:
\_enum_typespec: (alu_rs1_op_t), line:97
|vpiTypedef:
\_enum_typespec: (alu_rs2_op_t), line:104
|vpiTypedef:
\_struct_typespec: (amo_alu_inputs_t), line:356
|vpiTypedef:
\_struct_typespec: (amo_details_t), line:362
|vpiTypedef:
\_enum_typespec: (amo_t), line:354
|vpiTypedef:
\_struct_typespec: (branch_inputs_t), line:313
|vpiTypedef:
\_logic_typespec: (branch_predictor_metadata_t), line:32
|vpiTypedef:
\_struct_typespec: (branch_results_t), line:330
|vpiTypedef:
\_enum_typespec: (bus_type_t), line:86
|vpiTypedef:
\_struct_typespec: (csr_inputs_t), line:396
|vpiTypedef:
\_enum_typespec: (csr_op_t), line:218
|vpiTypedef:
\_enum_typespec: (csr_t), line:201
|vpiTypedef:
\_struct_typespec: (data_access_shared_inputs_t), line:427
|vpiTypedef:
\_struct_typespec: (div_inputs_t), line:389
|vpiTypedef:
\_enum_typespec: (div_type), line:66
|vpiTypedef:
\_enum_typespec: (exception_code_t), line:245
|vpiTypedef:
\_struct_typespec: (exception_packet_t), line:263
|vpiTypedef:
\_struct_typespec: (fetch_buffer_packet_t), line:276
|vpiTypedef:
\_enum_typespec: (fifo_type_t), line:440
|vpiTypedef:
\_enum_typespec: (fn3_arith_t), line:76
|vpiTypedef:
\_enum_typespec: (fn3_branch_t), line:126
|vpiTypedef:
\_enum_typespec: (fn3_csr_t), line:212
|vpiTypedef:
\_enum_typespec: (fn3_ls_t), line:115
|vpiTypedef:
\_enum_typespec: (fn3_mul_div_t), line:138
|vpiTypedef:
\_struct_typespec: (gc_inputs_t), line:404
|vpiTypedef:
\_struct_typespec: (inflight_instruction_packet), line:271
|vpiTypedef:
\_logic_typespec: (instruction_id_t), line:30
|vpiTypedef:
\_enum_typespec: (interrupt_code_t), line:261
|vpiTypedef:
\_struct_typespec: (load_store_inputs_t), line:369
|vpiTypedef:
\_struct_typespec: (mul_inputs_t), line:383
|vpiTypedef:
\_enum_typespec: (opcodes_t), line:48
|vpiTypedef:
\_enum_typespec: (opcodes_trimmed_t), line:65
|vpiTypedef:
\_struct_typespec: (simulation_named_regfile), line:476
|vpiTypedef:
\_struct_typespec: (taiga_trace_events_t), line:442
|vpiTypedef:
\_struct_typespec: (to_l1_arbiter_packet), line:418
|vpiTypedef:
\_struct_typespec: (trace_outputs_t), line:469
|vpiTypedef:
\_logic_typespec: (unit_id_t), line:31
|vpiTypedef:
\_struct_typespec: (unit_writeback_t), line:295
|vpiTypedef:
\_enum_typespec: (vm_t), line:223
|uhdmallModules:
\_module: work@dcache, file:third_party/cores/taiga/core/dcache.sv, line:26, parent:work@div_unit_core_wrapper
|vpiDefName:work@dcache
|vpiFullName:work@dcache
|vpiProcess:
\_always: , line:107
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:107
|vpiCondition:
\_operation: , line:107
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:107
|vpiName:clk
|vpiFullName:work@dcache.clk
|vpiStmt:
\_begin: , line:107
|vpiFullName:work@dcache
|vpiStmt:
\_if_stmt: , line:108
|vpiCondition:
\_ref_obj: (ls.new_request), line:108
|vpiName:ls.new_request
|vpiFullName:work@dcache.ls.new_request
|vpiStmt:
\_begin: , line:108
|vpiFullName:work@dcache
|vpiStmt:
\_assignment: , line:109
|vpiOpType:82
|vpiLhs:
\_ref_obj: (stage2_addr), line:109
|vpiName:stage2_addr
|vpiFullName:work@dcache.stage2_addr
|vpiRhs:
\_ref_obj: (ls_inputs.addr), line:109
|vpiName:ls_inputs.addr
|vpiFullName:work@dcache.ls_inputs.addr
|vpiStmt:
\_assignment: , line:110
|vpiOpType:82
|vpiLhs:
\_ref_obj: (stage2_be), line:110
|vpiName:stage2_be
|vpiFullName:work@dcache.stage2_be
|vpiRhs:
\_ref_obj: (ls_inputs.be), line:110
|vpiName:ls_inputs.be
|vpiFullName:work@dcache.ls_inputs.be
|vpiStmt:
\_assignment: , line:111
|vpiOpType:82
|vpiLhs:
\_ref_obj: (stage2_load), line:111
|vpiName:stage2_load
|vpiFullName:work@dcache.stage2_load
|vpiRhs:
\_ref_obj: (ls_inputs.load), line:111
|vpiName:ls_inputs.load
|vpiFullName:work@dcache.ls_inputs.load
|vpiStmt:
\_assignment: , line:112
|vpiOpType:82
|vpiLhs:
\_ref_obj: (stage2_store), line:112
|vpiName:stage2_store
|vpiFullName:work@dcache.stage2_store
|vpiRhs:
\_ref_obj: (ls_inputs.store), line:112
|vpiName:ls_inputs.store
|vpiFullName:work@dcache.ls_inputs.store
|vpiStmt:
\_assignment: , line:113
|vpiOpType:82
|vpiLhs:
\_ref_obj: (stage2_fn3), line:113
|vpiName:stage2_fn3
|vpiFullName:work@dcache.stage2_fn3
|vpiRhs:
\_ref_obj: (ls_inputs.fn3), line:113
|vpiName:ls_inputs.fn3
|vpiFullName:work@dcache.ls_inputs.fn3
|vpiStmt:
\_assignment: , line:114
|vpiOpType:82
|vpiLhs:
\_ref_obj: (stage2_data), line:114
|vpiName:stage2_data
|vpiFullName:work@dcache.stage2_data
|vpiRhs:
\_ref_obj: (ls_inputs.data_in), line:114
|vpiName:ls_inputs.data_in
|vpiFullName:work@dcache.ls_inputs.data_in
|vpiStmt:
\_assignment: , line:115
|vpiOpType:82
|vpiLhs:
\_ref_obj: (stage2_amo), line:115
|vpiName:stage2_amo
|vpiFullName:work@dcache.stage2_amo
|vpiRhs:
\_ref_obj: (amo), line:115
|vpiName:amo
|vpiFullName:work@dcache.amo
|vpiProcess:
\_always: , line:123
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:123
|vpiCondition:
\_operation: , line:123
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:123
|vpiName:clk
|vpiFullName:work@dcache.clk
|vpiStmt:
\_begin: , line:123
|vpiFullName:work@dcache
|vpiStmt:
\_assignment: , line:124
|vpiOpType:82
|vpiLhs:
\_ref_obj: (read_hit_allowed), line:124
|vpiName:read_hit_allowed
|vpiFullName:work@dcache.read_hit_allowed
|vpiRhs:
\_operation: , line:124
|vpiOpType:28
|vpiOperand:
\_operation: , line:124
|vpiOpType:28
|vpiOperand:
\_operation: , line:124
|vpiOpType:28
|vpiOperand:
\_ref_obj: (ls.new_request), line:124
|vpiName:ls.new_request
|vpiFullName:work@dcache.ls.new_request
|vpiOperand:
\_ref_obj: (ls_inputs.load), line:124
|vpiName:ls_inputs.load
|vpiFullName:work@dcache.ls_inputs.load
|vpiOperand:
\_ref_obj: (dcache_on), line:124
|vpiName:dcache_on
|vpiFullName:work@dcache.dcache_on
|vpiOperand:
\_operation: , line:124
|vpiOpType:4
|vpiOperand:
\_operation: , line:124
|vpiOpType:29
|vpiOperand:
\_ref_obj: (amo.is_lr), line:124
|vpiName:amo.is_lr
|vpiFullName:work@dcache.amo.is_lr
|vpiOperand:
\_ref_obj: (amo.is_amo), line:124
|vpiName:amo.is_amo
|vpiFullName:work@dcache.amo.is_amo
|vpiStmt:
\_assignment: , line:125
|vpiOpType:82
|vpiLhs:
\_ref_obj: (read_hit_data_valid), line:125
|vpiName:read_hit_data_valid
|vpiFullName:work@dcache.read_hit_data_valid
|vpiRhs:
\_ref_obj: (read_hit_allowed), line:125
|vpiName:read_hit_allowed
|vpiFullName:work@dcache.read_hit_allowed
|vpiStmt:
\_assignment: , line:126
|vpiOpType:82
|vpiLhs:
\_ref_obj: (second_cycle), line:126
|vpiName:second_cycle
|vpiFullName:work@dcache.second_cycle
|vpiRhs:
\_ref_obj: (ls.new_request), line:126
|vpiName:ls.new_request
|vpiFullName:work@dcache.ls.new_request
|vpiStmt:
\_assignment: , line:127
|vpiOpType:82
|vpiLhs:
\_ref_obj: (tag_update), line:127
|vpiName:tag_update
|vpiFullName:work@dcache.tag_update
|vpiRhs:
\_operation: , line:127
|vpiOpType:28
|vpiOperand:
\_operation: , line:127
|vpiOpType:28
|vpiOperand:
\_operation: , line:127
|vpiOpType:28
|vpiOperand:
\_ref_obj: (second_cycle), line:127
|vpiName:second_cycle
|vpiFullName:work@dcache.second_cycle
|vpiOperand:
\_ref_obj: (dcache_on), line:127
|vpiName:dcache_on
|vpiFullName:work@dcache.dcache_on
|vpiOperand:
\_ref_obj: (stage2_load), line:127
|vpiName:stage2_load
|vpiFullName:work@dcache.stage2_load
|vpiOperand:
\_operation: , line:127
|vpiOpType:4
|vpiOperand:
\_ref_obj: (tag_hit), line:127
|vpiName:tag_hit
|vpiFullName:work@dcache.tag_hit
|vpiProcess:
\_always: , line:131
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:131
|vpiCondition:
\_operation: , line:131
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:131
|vpiName:clk
|vpiFullName:work@dcache.clk
|vpiStmt:
\_begin: , line:131
|vpiFullName:work@dcache
|vpiStmt:
\_if_else: , line:132
|vpiCondition:
\_ref_obj: (rst), line:132
|vpiName:rst
|vpiFullName:work@dcache.rst
|vpiStmt:
\_assignment: , line:133
|vpiOpType:82
|vpiLhs:
\_ref_obj: (reservation), line:133
|vpiName:reservation
|vpiFullName:work@dcache.reservation
|vpiRhs:
\_constant: , line:133
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiElseStmt:
\_if_else: , line:134
|vpiCondition:
\_ref_obj: (second_cycle), line:134
|vpiName:second_cycle
|vpiFullName:work@dcache.second_cycle
|vpiStmt:
\_assignment: , line:135
|vpiOpType:82
|vpiLhs:
\_ref_obj: (reservation), line:135
|vpiName:reservation
|vpiFullName:work@dcache.reservation
|vpiRhs:
\_ref_obj: (stage2_amo.is_lr), line:135
|vpiName:stage2_amo.is_lr
|vpiFullName:work@dcache.stage2_amo.is_lr
|vpiElseStmt:
\_if_stmt: , line:136
|vpiCondition:
\_operation: , line:136
|vpiOpType:29
|vpiOperand:
\_ref_obj: (sc_complete), line:136
|vpiName:sc_complete
|vpiFullName:work@dcache.sc_complete
|vpiOperand:
\_ref_obj: (clear_reservation), line:136
|vpiName:clear_reservation
|vpiFullName:work@dcache.clear_reservation
|vpiStmt:
\_assignment: , line:137
|vpiOpType:82
|vpiLhs:
\_ref_obj: (reservation), line:137
|vpiName:reservation
|vpiFullName:work@dcache.reservation
|vpiRhs:
\_constant: , line:137
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiProcess:
\_always: , line:150
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:150
|vpiCondition:
\_operation: , line:150
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:150
|vpiName:clk
|vpiFullName:work@dcache.clk
|vpiStmt:
\_begin: , line:150
|vpiFullName:work@dcache
|vpiStmt:
\_if_else: , line:151
|vpiCondition:
\_ref_obj: (rst), line:151
|vpiName:rst
|vpiFullName:work@dcache.rst
|vpiStmt:
\_assignment: , line:152
|vpiOpType:82
|vpiLhs:
\_ref_obj: (word_count), line:152
|vpiName:word_count
|vpiFullName:work@dcache.word_count
|vpiRhs:
\_constant: , line:152
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiElseStmt:
\_if_stmt: , line:153
|vpiCondition:
\_ref_obj: (l1_response.data_valid), line:153
|vpiName:l1_response.data_valid
|vpiFullName:work@dcache.l1_response.data_valid
|vpiStmt:
\_assignment: , line:154
|vpiOpType:82
|vpiLhs:
\_ref_obj: (word_count), line:154
|vpiName:word_count
|vpiFullName:work@dcache.word_count
|vpiRhs:
\_operation: , line:154
|vpiOpType:24
|vpiOperand:
\_ref_obj: (word_count), line:154
|vpiName:word_count
|vpiFullName:work@dcache.word_count
|vpiOperand:
\_constant: , line:154
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiProcess:
\_always: , line:158
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:158
|vpiCondition:
\_operation: , line:158
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:158
|vpiName:clk
|vpiFullName:work@dcache.clk
|vpiStmt:
\_begin: , line:158
|vpiFullName:work@dcache
|vpiStmt:
\_if_else: , line:159
|vpiCondition:
\_ref_obj: (rst), line:159
|vpiName:rst
|vpiFullName:work@dcache.rst
|vpiStmt:
\_assignment: , line:160
|vpiOpType:82
|vpiLhs:
\_ref_obj: (request), line:160
|vpiName:request
|vpiFullName:work@dcache.request
|vpiRhs:
\_constant: , line:160
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiElseStmt:
\_if_else: , line:161
|vpiCondition:
\_operation: , line:161
|vpiOpType:28
|vpiOperand:
\_ref_obj: (second_cycle), line:161
|vpiName:second_cycle
|vpiFullName:work@dcache.second_cycle
|vpiOperand:
\_operation: , line:161
|vpiOpType:4
|vpiOperand:
\_ref_obj: (l1_request.ack), line:161
|vpiName:l1_request.ack
|vpiFullName:work@dcache.l1_request.ack
|vpiStmt:
\_assignment: , line:162
|vpiOpType:82
|vpiLhs:
\_ref_obj: (request), line:162
|vpiName:request
|vpiFullName:work@dcache.request
|vpiRhs:
\_operation: , line:162
|vpiOpType:29
|vpiOperand:
\_operation: , line:162
|vpiOpType:4
|vpiOperand:
\_operation: , line:162
|vpiOpType:28
|vpiOperand:
\_ref_obj: (tag_hit), line:162
|vpiName:tag_hit
|vpiFullName:work@dcache.tag_hit
|vpiOperand:
\_ref_obj: (read_hit_allowed), line:162
|vpiName:read_hit_allowed
|vpiFullName:work@dcache.read_hit_allowed
|vpiOperand:
\_operation: , line:162
|vpiOpType:4
|vpiOperand:
\_ref_obj: (dcache_on), line:162
|vpiName:dcache_on
|vpiFullName:work@dcache.dcache_on
|vpiElseStmt:
\_if_stmt: , line:163
|vpiCondition:
\_ref_obj: (l1_request.ack), line:163
|vpiName:l1_request.ack
|vpiFullName:work@dcache.l1_request.ack
|vpiStmt:
\_assignment: , line:164
|vpiOpType:82
|vpiLhs:
\_ref_obj: (request), line:164
|vpiName:request
|vpiFullName:work@dcache.request
|vpiRhs:
\_constant: , line:164
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiProcess:
\_always: , line:180
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:180
|vpiCondition:
\_operation: , line:180
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:180
|vpiName:clk
|vpiFullName:work@dcache.clk
|vpiStmt:
\_begin: , line:180
|vpiFullName:work@dcache
|vpiStmt:
\_if_stmt: , line:181
|vpiCondition:
\_ref_obj: (second_cycle), line:181
|vpiName:second_cycle
|vpiFullName:work@dcache.second_cycle
|vpiStmt:
\_begin: , line:181
|vpiFullName:work@dcache
|vpiStmt:
\_assignment: , line:182
|vpiOpType:82
|vpiLhs:
\_ref_obj: (tag_update_way), line:182
|vpiName:tag_update_way
|vpiFullName:work@dcache.tag_update_way
|vpiRhs:
\_operation: , line:182
|vpiOpType:32
|vpiOperand:
\_operation: , line:182
|vpiOpType:28
|vpiOperand:
\_ref_obj: (stage2_amo_with_load), line:182
|vpiName:stage2_amo_with_load
|vpiFullName:work@dcache.stage2_amo_with_load
|vpiOperand:
\_ref_obj: (tag_hit), line:182
|vpiName:tag_hit
|vpiFullName:work@dcache.tag_hit
|vpiOperand:
\_ref_obj: (tag_hit_way), line:182
|vpiName:tag_hit_way
|vpiFullName:work@dcache.tag_hit_way
|vpiOperand:
\_ref_obj: (replacement_way), line:182
|vpiName:replacement_way
|vpiFullName:work@dcache.replacement_way
|vpiStmt:
\_assignment: , line:183
|vpiOpType:82
|vpiLhs:
\_ref_obj: (tag_update_way_int), line:183
|vpiName:tag_update_way_int
|vpiFullName:work@dcache.tag_update_way_int
|vpiRhs:
\_operation: , line:183
|vpiOpType:32
|vpiOperand:
\_operation: , line:183
|vpiOpType:28
|vpiOperand:
\_ref_obj: (stage2_amo_with_load), line:183
|vpiName:stage2_amo_with_load
|vpiFullName:work@dcache.stage2_amo_with_load
|vpiOperand:
\_ref_obj: (tag_hit), line:183
|vpiName:tag_hit
|vpiFullName:work@dcache.tag_hit
|vpiOperand:
\_ref_obj: (tag_hit_way_int), line:183
|vpiName:tag_hit_way_int
|vpiFullName:work@dcache.tag_hit_way_int
|vpiOperand:
\_ref_obj: (replacement_way_int), line:183
|vpiName:replacement_way_int
|vpiFullName:work@dcache.replacement_way_int
|vpiProcess:
\_always: , line:203
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:203
|vpiCondition:
\_operation: , line:203
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:203
|vpiName:clk
|vpiFullName:work@dcache.clk
|vpiStmt:
\_begin: , line:203
|vpiFullName:work@dcache
|vpiStmt:
\_assignment: , line:204
|vpiOpType:82
|vpiLhs:
\_ref_obj: (amo_rs2), line:204
|vpiName:amo_rs2
|vpiFullName:work@dcache.amo_rs2
|vpiRhs:
\_ref_obj: (stage2_data), line:204
|vpiName:stage2_data
|vpiFullName:work@dcache.stage2_data
|vpiProcess:
\_always: , line:215
|vpiAlwaysType:2
|vpiStmt:
\_begin: , line:215
|vpiFullName:work@dcache
|vpiStmt:
\_if_else: , line:216
|vpiCondition:
\_operation: , line:216
|vpiOpType:28
|vpiOperand:
\_ref_obj: (stage2_amo.is_amo), line:216
|vpiName:stage2_amo.is_amo
|vpiFullName:work@dcache.stage2_amo.is_amo
|vpiOperand:
\_ref_obj: (is_target_word), line:216
|vpiName:is_target_word
|vpiFullName:work@dcache.is_target_word
|vpiStmt:
\_assignment: , line:217
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (new_line_data), line:217
|vpiName:new_line_data
|vpiFullName:work@dcache.new_line_data
|vpiRhs:
\_ref_obj: (amo_result), line:217
|vpiName:amo_result
|vpiFullName:work@dcache.amo_result
|vpiElseStmt:
\_if_else: , line:218
|vpiCondition:
\_ref_obj: (stage2_amo.is_sc), line:218
|vpiName:stage2_amo.is_sc
|vpiFullName:work@dcache.stage2_amo.is_sc
|vpiStmt:
\_assignment: , line:219
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (new_line_data), line:219
|vpiName:new_line_data
|vpiFullName:work@dcache.new_line_data
|vpiRhs:
\_ref_obj: (stage2_data), line:219
|vpiName:stage2_data
|vpiFullName:work@dcache.stage2_data
|vpiElseStmt:
\_assignment: , line:221
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (new_line_data), line:221
|vpiName:new_line_data
|vpiFullName:work@dcache.new_line_data
|vpiRhs:
\_ref_obj: (l1_response.data), line:221
|vpiName:l1_response.data
|vpiFullName:work@dcache.l1_response.data
|vpiProcess:
\_always: , line:251
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:251
|vpiCondition:
\_operation: , line:251
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:251
|vpiName:clk
|vpiFullName:work@dcache.clk
|vpiStmt:
\_begin: , line:251
|vpiFullName:work@dcache
|vpiStmt:
\_if_else: , line:252
|vpiCondition:
\_operation: , line:252
|vpiOpType:28
|vpiOperand:
\_ref_obj: (l1_response.data_valid), line:252
|vpiName:l1_response.data_valid
|vpiFullName:work@dcache.l1_response.data_valid
|vpiOperand:
\_ref_obj: (is_target_word), line:252
|vpiName:is_target_word
|vpiFullName:work@dcache.is_target_word
|vpiStmt:
\_assignment: , line:253
|vpiOpType:82
|vpiLhs:
\_ref_obj: (miss_data), line:253
|vpiName:miss_data
|vpiFullName:work@dcache.miss_data
|vpiRhs:
\_ref_obj: (l1_response.data), line:253
|vpiName:l1_response.data
|vpiFullName:work@dcache.l1_response.data
|vpiElseStmt:
\_if_stmt: , line:254
|vpiCondition:
\_ref_obj: (sc_complete), line:254
|vpiName:sc_complete
|vpiFullName:work@dcache.sc_complete
|vpiStmt:
\_assignment: , line:255
|vpiOpType:82
|vpiLhs:
\_ref_obj: (miss_data), line:255
|vpiName:miss_data
|vpiFullName:work@dcache.miss_data
|vpiRhs:
\_operation: , line:255
|vpiOpType:33
|vpiOperand:
\_constant: , line:255
|vpiConstType:3
|vpiDecompile:31'b0
|vpiSize:31
|BIN:31'b0
|vpiOperand:
\_ref_obj: (sc_success), line:255
|vpiName:sc_success
|vpiProcess:
\_always: , line:266
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:266
|vpiCondition:
\_operation: , line:266
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:266
|vpiName:clk
|vpiFullName:work@dcache.clk
|vpiStmt:
\_begin: , line:266
|vpiFullName:work@dcache
|vpiStmt:
\_if_else: , line:267
|vpiCondition:
\_ref_obj: (rst), line:267
|vpiName:rst
|vpiFullName:work@dcache.rst
|vpiStmt:
\_assignment: , line:268
|vpiOpType:82
|vpiLhs:
\_ref_obj: (read_miss_complete), line:268
|vpiName:read_miss_complete
|vpiFullName:work@dcache.read_miss_complete
|vpiRhs:
\_constant: , line:268
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiElseStmt:
\_assignment: , line:270
|vpiOpType:82
|vpiLhs:
\_ref_obj: (read_miss_complete), line:270
|vpiName:read_miss_complete
|vpiFullName:work@dcache.read_miss_complete
|vpiRhs:
\_operation: , line:270
|vpiOpType:29
|vpiOperand:
\_ref_obj: (line_complete), line:270
|vpiName:line_complete
|vpiFullName:work@dcache.line_complete
|vpiOperand:
\_ref_obj: (sc_complete), line:270
|vpiName:sc_complete
|vpiFullName:work@dcache.sc_complete
|vpiProcess:
\_always: , line:273
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:273
|vpiCondition:
\_operation: , line:273
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:273
|vpiName:clk
|vpiFullName:work@dcache.clk
|vpiStmt:
\_begin: , line:273
|vpiFullName:work@dcache
|vpiStmt:
\_if_else: , line:274
|vpiCondition:
\_ref_obj: (rst), line:274
|vpiName:rst
|vpiFullName:work@dcache.rst
|vpiStmt:
\_assignment: , line:275
|vpiOpType:82
|vpiLhs:
\_ref_obj: (ls.data_valid), line:275
|vpiName:ls.data_valid
|vpiFullName:work@dcache.ls.data_valid
|vpiRhs:
\_constant: , line:275
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiElseStmt:
\_assignment: , line:277
|vpiOpType:82
|vpiLhs:
\_ref_obj: (ls.data_valid), line:277
|vpiName:ls.data_valid
|vpiFullName:work@dcache.ls.data_valid
|vpiRhs:
\_operation: , line:277
|vpiOpType:29
|vpiOperand:
\_operation: , line:277
|vpiOpType:29
|vpiOperand:
\_operation: , line:277
|vpiOpType:28
|vpiOperand:
\_ref_obj: (l1_response.data_valid), line:277
|vpiName:l1_response.data_valid
|vpiFullName:work@dcache.l1_response.data_valid
|vpiOperand:
\_ref_obj: (is_target_word), line:277
|vpiName:is_target_word
|vpiFullName:work@dcache.is_target_word
|vpiOperand:
\_operation: , line:277
|vpiOpType:28
|vpiOperand:
\_ref_obj: (read_hit_allowed), line:277
|vpiName:read_hit_allowed
|vpiFullName:work@dcache.read_hit_allowed
|vpiOperand:
\_ref_obj: (tag_hit), line:277
|vpiName:tag_hit
|vpiFullName:work@dcache.tag_hit
|vpiOperand:
\_ref_obj: (sc_complete), line:277
|vpiName:sc_complete
|vpiFullName:work@dcache.sc_complete
|vpiProcess:
\_always: , line:282
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:282
|vpiCondition:
\_operation: , line:282
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:282
|vpiName:clk
|vpiFullName:work@dcache.clk
|vpiStmt:
\_begin: , line:282
|vpiFullName:work@dcache
|vpiStmt:
\_if_else: , line:283
|vpiCondition:
\_ref_obj: (rst), line:283
|vpiName:rst
|vpiFullName:work@dcache.rst
|vpiStmt:
\_assignment: , line:284
|vpiOpType:82
|vpiLhs:
\_ref_obj: (idle), line:284
|vpiName:idle
|vpiFullName:work@dcache.idle
|vpiRhs:
\_constant: , line:284
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiElseStmt:
\_if_else: , line:285
|vpiCondition:
\_ref_obj: (ls.new_request), line:285
|vpiName:ls.new_request
|vpiFullName:work@dcache.ls.new_request
|vpiStmt:
\_assignment: , line:286
|vpiOpType:82
|vpiLhs:
\_ref_obj: (idle), line:286
|vpiName:idle
|vpiFullName:work@dcache.idle
|vpiRhs:
\_constant: , line:286
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiElseStmt:
\_if_stmt: , line:287
|vpiCondition:
\_operation: , line:287
|vpiOpType:29
|vpiOperand:
\_operation: , line:287
|vpiOpType:29
|vpiOperand:
\_operation: , line:287
|vpiOpType:28
|vpiOperand:
\_ref_obj: (read_hit_allowed), line:287
|vpiName:read_hit_allowed
|vpiFullName:work@dcache.read_hit_allowed
|vpiOperand:
\_ref_obj: (tag_hit), line:287
|vpiName:tag_hit
|vpiFullName:work@dcache.tag_hit
|vpiOperand:
\_ref_obj: (read_miss_complete), line:287
|vpiName:read_miss_complete
|vpiFullName:work@dcache.read_miss_complete
|vpiOperand:
\_ref_obj: (store_complete), line:287
|vpiName:store_complete
|vpiFullName:work@dcache.store_complete
|vpiStmt:
\_assignment: , line:288
|vpiOpType:82
|vpiLhs:
\_ref_obj: (idle), line:288
|vpiName:idle
|vpiFullName:work@dcache.idle
|vpiRhs:
\_constant: , line:288
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiPort:
\_port: (clk), line:27
|vpiName:clk
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (clk), line:27
|vpiName:clk
|vpiFullName:work@dcache.clk
|vpiNetType:36
|vpiPort:
\_port: (rst), line:28
|vpiName:rst
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (rst), line:28
|vpiName:rst
|vpiFullName:work@dcache.rst
|vpiNetType:36
|vpiPort:
\_port: (dcache_on), line:29
|vpiName:dcache_on
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (dcache_on), line:29
|vpiName:dcache_on
|vpiFullName:work@dcache.dcache_on
|vpiNetType:36
|vpiPort:
\_port: (l1_request), line:30
|vpiName:l1_request
|vpiDirection:5
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_modport: (master)
|vpiPort:
\_port: (l1_response), line:31
|vpiName:l1_response
|vpiDirection:5
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_modport: (master)
|vpiPort:
\_port: (sc_complete), line:32
|vpiName:sc_complete
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (sc_complete), line:32
|vpiName:sc_complete
|vpiFullName:work@dcache.sc_complete
|vpiPort:
\_port: (sc_success), line:33
|vpiName:sc_success
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (sc_success), line:33
|vpiName:sc_success
|vpiFullName:work@dcache.sc_success
|vpiPort:
\_port: (clear_reservation), line:34
|vpiName:clear_reservation
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (clear_reservation), line:34
|vpiName:clear_reservation
|vpiFullName:work@dcache.clear_reservation
|vpiPort:
\_port: (ls_inputs), line:36
|vpiName:ls_inputs
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (ls_inputs), line:36
|vpiName:ls_inputs
|vpiFullName:work@dcache.ls_inputs
|vpiPort:
\_port: (data_out), line:37
|vpiName:data_out
|vpiDirection:2
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (data_out), line:37
|vpiName:data_out
|vpiFullName:work@dcache.data_out
|vpiNetType:36
|vpiPort:
\_port: (amo), line:39
|vpiName:amo
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (amo), line:39
|vpiName:amo
|vpiFullName:work@dcache.amo
|vpiPort:
\_port: (ls), line:40
|vpiName:ls
|vpiDirection:5
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_modport: (sub_unit)
|vpiContAssign:
\_cont_assign: , line:142
|vpiRhs:
\_operation: , line:142
|vpiOpType:33
|vpiOperand:
\_part_select: , line:142, parent:stage2_addr
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (stage2_addr)
|vpiLeftRange:
\_constant: , line:142
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:142
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiOperand:
\_constant: , line:142
|vpiConstType:3
|vpiDecompile:2'b0
|vpiSize:2
|BIN:2'b0
|vpiLhs:
\_ref_obj: (l1_request.addr), line:142
|vpiName:l1_request.addr
|vpiFullName:work@dcache.l1_request.addr
|vpiContAssign:
\_cont_assign: , line:143
|vpiRhs:
\_ref_obj: (stage2_data), line:143
|vpiName:stage2_data
|vpiFullName:work@dcache.stage2_data
|vpiLhs:
\_ref_obj: (l1_request.data), line:143
|vpiName:l1_request.data
|vpiFullName:work@dcache.l1_request.data
|vpiContAssign:
\_cont_assign: , line:144
|vpiRhs:
\_ref_obj: (stage2_load), line:144
|vpiName:stage2_load
|vpiFullName:work@dcache.stage2_load
|vpiLhs:
\_ref_obj: (l1_request.rnw), line:144
|vpiName:l1_request.rnw
|vpiFullName:work@dcache.l1_request.rnw
|vpiContAssign:
\_cont_assign: , line:145
|vpiRhs:
\_ref_obj: (stage2_be), line:145
|vpiName:stage2_be
|vpiFullName:work@dcache.stage2_be
|vpiLhs:
\_ref_obj: (l1_request.be), line:145
|vpiName:l1_request.be
|vpiFullName:work@dcache.l1_request.be
|vpiContAssign:
\_cont_assign: , line:146
|vpiRhs:
\_operation: , line:146
|vpiOpType:32
|vpiOperand:
\_ref_obj: (stage2_load), line:146
|vpiName:stage2_load
|vpiFullName:work@dcache.stage2_load
|vpiOperand:
\_operation: , line:146
|vpiOpType:11
|vpiOperand:
\_ref_obj: (DCACHE_LINE_W), line:146
|vpiName:DCACHE_LINE_W
|vpiFullName:work@dcache.DCACHE_LINE_W
|vpiOperand:
\_constant: , line:146
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiOperand:
\_constant: , line:146
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiLhs:
\_ref_obj: (l1_request.size), line:146
|vpiName:l1_request.size
|vpiFullName:work@dcache.l1_request.size
|vpiContAssign:
\_cont_assign: , line:147
|vpiRhs:
\_operation: , line:147
|vpiOpType:29
|vpiOperand:
\_operation: , line:147
|vpiOpType:29
|vpiOperand:
\_ref_obj: (stage2_amo.is_amo), line:147
|vpiName:stage2_amo.is_amo
|vpiFullName:work@dcache.stage2_amo.is_amo
|vpiOperand:
\_ref_obj: (stage2_amo.is_lr), line:147
|vpiName:stage2_amo.is_lr
|vpiFullName:work@dcache.stage2_amo.is_lr
|vpiOperand:
\_ref_obj: (stage2_amo.is_sc), line:147
|vpiName:stage2_amo.is_sc
|vpiFullName:work@dcache.stage2_amo.is_sc
|vpiLhs:
\_ref_obj: (l1_request.is_amo), line:147
|vpiName:l1_request.is_amo
|vpiFullName:work@dcache.l1_request.is_amo
|vpiContAssign:
\_cont_assign: , line:148
|vpiRhs:
\_ref_obj: (stage2_amo.op), line:148
|vpiName:stage2_amo.op
|vpiFullName:work@dcache.stage2_amo.op
|vpiLhs:
\_ref_obj: (l1_request.amo), line:148
|vpiName:l1_request.amo
|vpiFullName:work@dcache.l1_request.amo
|vpiContAssign:
\_cont_assign: , line:156
|vpiRhs:
\_operation: , line:156
|vpiOpType:14
|vpiOperand:
\_part_select: , line:156, parent:stage2_addr
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (stage2_addr)
|vpiLeftRange:
\_operation: , line:156
|vpiOpType:24
|vpiOperand:
\_ref_obj: (DCACHE_SUB_LINE_ADDR_W), line:156
|vpiName:DCACHE_SUB_LINE_ADDR_W
|vpiOperand:
\_constant: , line:156
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:156
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiOperand:
\_ref_obj: (word_count), line:156
|vpiName:word_count
|vpiFullName:work@dcache.word_count
|vpiLhs:
\_ref_obj: (is_target_word), line:156
|vpiName:is_target_word
|vpiFullName:work@dcache.is_target_word
|vpiContAssign:
\_cont_assign: , line:166
|vpiRhs:
\_operation: , line:166
|vpiOpType:29
|vpiOperand:
\_ref_obj: (request), line:166
|vpiName:request
|vpiFullName:work@dcache.request
|vpiOperand:
\_operation: , line:166
|vpiOpType:28
|vpiOperand:
\_ref_obj: (second_cycle), line:166
|vpiName:second_cycle
|vpiFullName:work@dcache.second_cycle
|vpiOperand:
\_operation: , line:166
|vpiOpType:29
|vpiOperand:
\_operation: , line:166
|vpiOpType:4
|vpiOperand:
\_operation: , line:166
|vpiOpType:28
|vpiOperand:
\_ref_obj: (tag_hit), line:166
|vpiName:tag_hit
|vpiFullName:work@dcache.tag_hit
|vpiOperand:
\_ref_obj: (read_hit_allowed), line:166
|vpiName:read_hit_allowed
|vpiFullName:work@dcache.read_hit_allowed
|vpiOperand:
\_operation: , line:166
|vpiOpType:4
|vpiOperand:
\_ref_obj: (dcache_on), line:166
|vpiName:dcache_on
|vpiFullName:work@dcache.dcache_on
|vpiLhs:
\_ref_obj: (l1_request.request), line:166
|vpiName:l1_request.request
|vpiFullName:work@dcache.l1_request.request
|vpiContAssign:
\_cont_assign: , line:179
|vpiRhs:
\_operation: , line:179
|vpiOpType:29
|vpiOperand:
\_ref_obj: (stage2_amo.is_amo), line:179
|vpiName:stage2_amo.is_amo
|vpiFullName:work@dcache.stage2_amo.is_amo
|vpiOperand:
\_ref_obj: (stage2_amo.is_lr), line:179
|vpiName:stage2_amo.is_lr
|vpiFullName:work@dcache.stage2_amo.is_lr
|vpiLhs:
\_ref_obj: (stage2_amo_with_load), line:179
|vpiName:stage2_amo_with_load
|vpiFullName:work@dcache.stage2_amo_with_load
|vpiContAssign:
\_cont_assign: , line:207
|vpiRhs:
\_ref_obj: (l1_response.data), line:207
|vpiName:l1_response.data
|vpiFullName:work@dcache.l1_response.data
|vpiLhs:
\_ref_obj: (amo_alu_inputs.rs1_load), line:207
|vpiName:amo_alu_inputs.rs1_load
|vpiFullName:work@dcache.amo_alu_inputs.rs1_load
|vpiContAssign:
\_cont_assign: , line:208
|vpiRhs:
\_ref_obj: (amo_rs2), line:208
|vpiName:amo_rs2
|vpiFullName:work@dcache.amo_rs2
|vpiLhs:
\_ref_obj: (amo_alu_inputs.rs2), line:208
|vpiName:amo_alu_inputs.rs2
|vpiFullName:work@dcache.amo_alu_inputs.rs2
|vpiContAssign:
\_cont_assign: , line:209
|vpiRhs:
\_ref_obj: (stage2_amo.op), line:209
|vpiName:stage2_amo.op
|vpiFullName:work@dcache.stage2_amo.op
|vpiLhs:
\_ref_obj: (amo_alu_inputs.op), line:209
|vpiName:amo_alu_inputs.op
|vpiFullName:work@dcache.amo_alu_inputs.op
|vpiContAssign:
\_cont_assign: , line:224
|vpiRhs:
\_part_select: , line:224, parent:stage2_addr
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (stage2_addr)
|vpiLeftRange:
\_operation: , line:224
|vpiOpType:24
|vpiOperand:
\_ref_obj: (DCACHE_SUB_LINE_ADDR_W), line:224
|vpiName:DCACHE_SUB_LINE_ADDR_W
|vpiOperand:
\_constant: , line:224
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:224
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiLhs:
\_ref_obj: (sc_write_index), line:224
|vpiName:sc_write_index
|vpiFullName:work@dcache.sc_write_index
|vpiContAssign:
\_cont_assign: , line:231
|vpiRhs:
\_operation: , line:231
|vpiOpType:28
|vpiOperand:
\_ref_obj: (stage2_be), line:231
|vpiName:stage2_be
|vpiFullName:work@dcache.stage2_be
|vpiOperand:
\_operation: , line:231
|vpiOpType:34
|vpiOperand:
\_constant: , line:231
|vpiConstType:7
|vpiDecompile:4
|vpiSize:32
|INT:4
|vpiOperand:
\_operation:
|vpiOpType:33
|vpiOperand:
\_ref_obj: (tag_hit), line:231
|vpiName:tag_hit
|vpiFullName:work@dcache.tag_hit
|vpiLhs:
\_ref_obj: (write_hit_be), line:231
|vpiName:write_hit_be
|vpiFullName:work@dcache.write_hit_be
|vpiContAssign:
\_cont_assign: , line:232
|vpiRhs:
\_operation: , line:232
|vpiOpType:32
|vpiOperand:
\_ref_obj: (stage2_amo.is_sc), line:232
|vpiName:stage2_amo.is_sc
|vpiFullName:work@dcache.stage2_amo.is_sc
|vpiOperand:
\_ref_obj: (sc_write_index), line:232
|vpiName:sc_write_index
|vpiFullName:work@dcache.sc_write_index
|vpiOperand:
\_ref_obj: (word_count), line:232
|vpiName:word_count
|vpiFullName:work@dcache.word_count
|vpiLhs:
\_ref_obj: (update_word_index), line:232
|vpiName:update_word_index
|vpiFullName:work@dcache.update_word_index
|vpiContAssign:
\_cont_assign: , line:234
|vpiRhs:
\_operation: , line:234
|vpiOpType:33
|vpiOperand:
\_ref_obj: (tag_hit_way_int), line:234
|vpiName:tag_hit_way_int
|vpiOperand:
\_part_select: , line:234, parent:stage2_addr
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (stage2_addr)
|vpiLeftRange:
\_operation: , line:234
|vpiOpType:11
|vpiOperand:
\_operation: , line:234
|vpiOpType:24
|vpiOperand:
\_operation: , line:234
|vpiOpType:24
|vpiOperand:
\_ref_obj: (DCACHE_LINE_ADDR_W), line:234
|vpiName:DCACHE_LINE_ADDR_W
|vpiOperand:
\_ref_obj: (DCACHE_SUB_LINE_ADDR_W), line:234
|vpiName:DCACHE_SUB_LINE_ADDR_W
|vpiOperand:
\_constant: , line:234
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiOperand:
\_constant: , line:234
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:234
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiLhs:
\_ref_obj: (data_bank_addr_a), line:234
|vpiName:data_bank_addr_a
|vpiFullName:work@dcache.data_bank_addr_a
|vpiContAssign:
\_cont_assign: , line:235
|vpiRhs:
\_operation: , line:235
|vpiOpType:33
|vpiOperand:
\_ref_obj: (tag_update_way_int), line:235
|vpiName:tag_update_way_int
|vpiOperand:
\_part_select: , line:235, parent:stage2_addr
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (stage2_addr)
|vpiLeftRange:
\_operation: , line:235
|vpiOpType:11
|vpiOperand:
\_operation: , line:235
|vpiOpType:24
|vpiOperand:
\_operation: , line:235
|vpiOpType:24
|vpiOperand:
\_ref_obj: (DCACHE_LINE_ADDR_W), line:235
|vpiName:DCACHE_LINE_ADDR_W
|vpiOperand:
\_ref_obj: (DCACHE_SUB_LINE_ADDR_W), line:235
|vpiName:DCACHE_SUB_LINE_ADDR_W
|vpiOperand:
\_constant: , line:235
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiOperand:
\_constant: , line:235
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_operation: , line:235
|vpiOpType:24
|vpiOperand:
\_ref_obj: (DCACHE_SUB_LINE_ADDR_W), line:235
|vpiName:DCACHE_SUB_LINE_ADDR_W
|vpiOperand:
\_constant: , line:235
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiOperand:
\_ref_obj: (update_word_index), line:235
|vpiName:update_word_index
|vpiLhs:
\_ref_obj: (data_bank_addr_b), line:235
|vpiName:data_bank_addr_b
|vpiFullName:work@dcache.data_bank_addr_b
|vpiContAssign:
\_cont_assign: , line:258
|vpiRhs:
\_operation: , line:258
|vpiOpType:32
|vpiOperand:
\_ref_obj: (read_hit_data_valid), line:258
|vpiName:read_hit_data_valid
|vpiFullName:work@dcache.read_hit_data_valid
|vpiOperand:
\_ref_obj: (dbank_data_out), line:258
|vpiName:dbank_data_out
|vpiFullName:work@dcache.dbank_data_out
|vpiOperand:
\_ref_obj: (miss_data), line:258
|vpiName:miss_data
|vpiFullName:work@dcache.miss_data
|vpiLhs:
\_ref_obj: (data_out), line:258
|vpiName:data_out
|vpiFullName:work@dcache.data_out
|vpiContAssign:
\_cont_assign: , line:262
|vpiRhs:
\_operation: , line:262
|vpiOpType:26
|vpiOperand:
\_ref_obj: (l1_response.data_valid), line:262
|vpiName:l1_response.data_valid
|vpiFullName:work@dcache.l1_response.data_valid
|vpiOperand:
\_operation: , line:262
|vpiOpType:14
|vpiOperand:
\_ref_obj: (word_count), line:262
|vpiName:word_count
|vpiFullName:work@dcache.word_count
|vpiOperand:
\_operation: , line:262
|vpiOpType:11
|vpiOperand:
\_ref_obj: (DCACHE_LINE_W), line:262
|vpiName:DCACHE_LINE_W
|vpiFullName:work@dcache.DCACHE_LINE_W
|vpiOperand:
\_constant: , line:262
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiLhs:
\_ref_obj: (line_complete), line:262
|vpiName:line_complete
|vpiFullName:work@dcache.line_complete
|vpiContAssign:
\_cont_assign: , line:263
|vpiRhs:
\_operation: , line:263
|vpiOpType:28
|vpiOperand:
\_operation: , line:263
|vpiOpType:28
|vpiOperand:
\_ref_obj: (l1_request.ack), line:263
|vpiName:l1_request.ack
|vpiFullName:work@dcache.l1_request.ack
|vpiOperand:
\_ref_obj: (stage2_store), line:263
|vpiName:stage2_store
|vpiFullName:work@dcache.stage2_store
|vpiOperand:
\_operation: , line:263
|vpiOpType:4
|vpiOperand:
\_ref_obj: (stage2_amo.is_sc), line:263
|vpiName:stage2_amo.is_sc
|vpiFullName:work@dcache.stage2_amo.is_sc
|vpiLhs:
\_ref_obj: (store_complete), line:263
|vpiName:store_complete
|vpiFullName:work@dcache.store_complete
|vpiContAssign:
\_cont_assign: , line:280
|vpiRhs:
\_operation: , line:280
|vpiOpType:29
|vpiOperand:
\_operation: , line:280
|vpiOpType:29
|vpiOperand:
\_operation: , line:280
|vpiOpType:29
|vpiOperand:
\_operation: , line:280
|vpiOpType:28
|vpiOperand:
\_ref_obj: (read_hit_allowed), line:280
|vpiName:read_hit_allowed
|vpiFullName:work@dcache.read_hit_allowed
|vpiOperand:
\_ref_obj: (tag_hit), line:280
|vpiName:tag_hit
|vpiFullName:work@dcache.tag_hit
|vpiOperand:
\_ref_obj: (store_complete), line:280
|vpiName:store_complete
|vpiFullName:work@dcache.store_complete
|vpiOperand:
\_ref_obj: (read_miss_complete), line:280
|vpiName:read_miss_complete
|vpiFullName:work@dcache.read_miss_complete
|vpiOperand:
\_ref_obj: (idle), line:280
|vpiName:idle
|vpiFullName:work@dcache.idle
|vpiLhs:
\_ref_obj: (ls.ready), line:280
|vpiName:ls.ready
|vpiFullName:work@dcache.ls.ready
|vpiNet:
\_logic_net: (clk), line:27
|vpiNet:
\_logic_net: (rst), line:28
|vpiNet:
\_logic_net: (dcache_on), line:29
|vpiNet:
\_logic_net: (sc_complete), line:32
|vpiNet:
\_logic_net: (sc_success), line:33
|vpiNet:
\_logic_net: (clear_reservation), line:34
|vpiNet:
\_logic_net: (ls_inputs), line:36
|vpiNet:
\_logic_net: (data_out), line:37
|vpiNet:
\_logic_net: (amo), line:39
|vpiNet:
\_logic_net: (data_bank_addr_a), line:45
|vpiName:data_bank_addr_a
|vpiFullName:work@dcache.data_bank_addr_a
|vpiNetType:36
|vpiNet:
\_logic_net: (data_bank_addr_b), line:46
|vpiName:data_bank_addr_b
|vpiFullName:work@dcache.data_bank_addr_b
|vpiNetType:36
|vpiNet:
\_logic_net: (tag_hit), line:48
|vpiName:tag_hit
|vpiFullName:work@dcache.tag_hit
|vpiNetType:36
|vpiNet:
\_logic_net: (tag_hit_way), line:49
|vpiName:tag_hit_way
|vpiFullName:work@dcache.tag_hit_way
|vpiNetType:36
|vpiNet:
\_logic_net: (tag_hit_way_int), line:51
|vpiName:tag_hit_way_int
|vpiFullName:work@dcache.tag_hit_way_int
|vpiNetType:36
|vpiNet:
\_logic_net: (tag_update), line:53
|vpiName:tag_update
|vpiFullName:work@dcache.tag_update
|vpiNetType:36
|vpiNet:
\_logic_net: (tag_update_way), line:54
|vpiName:tag_update_way
|vpiFullName:work@dcache.tag_update_way
|vpiNetType:36
|vpiNet:
\_logic_net: (replacement_way), line:55
|vpiName:replacement_way
|vpiFullName:work@dcache.replacement_way
|vpiNetType:36
|vpiNet:
\_logic_net: (replacement_way_int), line:57
|vpiName:replacement_way_int
|vpiFullName:work@dcache.replacement_way_int
|vpiNetType:36
|vpiNet:
\_logic_net: (tag_update_way_int), line:58
|vpiName:tag_update_way_int
|vpiFullName:work@dcache.tag_update_way_int
|vpiNetType:36
|vpiNet:
\_logic_net: (word_count), line:60
|vpiName:word_count
|vpiFullName:work@dcache.word_count
|vpiNetType:36
|vpiNet:
\_logic_net: (sc_write_index), line:61
|vpiName:sc_write_index
|vpiFullName:work@dcache.sc_write_index
|vpiNetType:36
|vpiNet:
\_logic_net: (update_word_index), line:62
|vpiName:update_word_index
|vpiFullName:work@dcache.update_word_index
|vpiNetType:36
|vpiNet:
\_logic_net: (line_complete), line:64
|vpiName:line_complete
|vpiFullName:work@dcache.line_complete
|vpiNetType:36
|vpiNet:
\_logic_net: (reservation), line:65
|vpiName:reservation
|vpiFullName:work@dcache.reservation
|vpiNetType:36
|vpiNet:
\_logic_net: (stage2_addr), line:67
|vpiName:stage2_addr
|vpiFullName:work@dcache.stage2_addr
|vpiNetType:36
|vpiNet:
\_logic_net: (stage2_load), line:68
|vpiName:stage2_load
|vpiFullName:work@dcache.stage2_load
|vpiNetType:36
|vpiNet:
\_logic_net: (stage2_store), line:69
|vpiName:stage2_store
|vpiFullName:work@dcache.stage2_store
|vpiNetType:36
|vpiNet:
\_logic_net: (stage2_be), line:70
|vpiName:stage2_be
|vpiFullName:work@dcache.stage2_be
|vpiNetType:36
|vpiNet:
\_logic_net: (stage2_fn3), line:71
|vpiName:stage2_fn3
|vpiFullName:work@dcache.stage2_fn3
|vpiNetType:36
|vpiNet:
\_logic_net: (stage2_data), line:72
|vpiName:stage2_data
|vpiFullName:work@dcache.stage2_data
|vpiNetType:36
|vpiNet:
\_logic_net: (stage2_amo), line:74
|vpiName:stage2_amo
|vpiFullName:work@dcache.stage2_amo
|vpiNet:
\_logic_net: (dbank_data_out), line:76
|vpiName:dbank_data_out
|vpiFullName:work@dcache.dbank_data_out
|vpiNetType:36
|vpiNet:
\_logic_net: (hit_data), line:77
|vpiName:hit_data
|vpiFullName:work@dcache.hit_data
|vpiNetType:36
|vpiNet:
\_logic_net: (miss_data), line:78
|vpiName:miss_data
|vpiFullName:work@dcache.miss_data
|vpiNetType:36
|vpiNet:
\_logic_net: (new_line_data), line:79
|vpiName:new_line_data
|vpiFullName:work@dcache.new_line_data
|vpiNetType:36
|vpiNet:
\_logic_net: (amo_result), line:80
|vpiName:amo_result
|vpiFullName:work@dcache.amo_result
|vpiNetType:36
|vpiNet:
\_logic_net: (amo_rs2), line:81
|vpiName:amo_rs2
|vpiFullName:work@dcache.amo_rs2
|vpiNetType:36
|vpiNet:
\_logic_net: (write_hit_be), line:83
|vpiName:write_hit_be
|vpiFullName:work@dcache.write_hit_be
|vpiNetType:36
|vpiNet:
\_logic_net: (second_cycle), line:85
|vpiName:second_cycle
|vpiFullName:work@dcache.second_cycle
|vpiNetType:36
|vpiNet:
\_logic_net: (request), line:87
|vpiName:request
|vpiFullName:work@dcache.request
|vpiNetType:36
|vpiNet:
\_logic_net: (is_target_word), line:89
|vpiName:is_target_word
|vpiFullName:work@dcache.is_target_word
|vpiNetType:36
|vpiNet:
\_logic_net: (hit_allowed), line:91
|vpiName:hit_allowed
|vpiFullName:work@dcache.hit_allowed
|vpiNetType:36
|vpiNet:
\_logic_net: (read_hit_allowed), line:92
|vpiName:read_hit_allowed
|vpiFullName:work@dcache.read_hit_allowed
|vpiNetType:36
|vpiNet:
\_logic_net: (read_hit_data_valid), line:93
|vpiName:read_hit_data_valid
|vpiFullName:work@dcache.read_hit_data_valid
|vpiNetType:36
|vpiNet:
\_logic_net: (address_range_valid), line:95
|vpiName:address_range_valid
|vpiFullName:work@dcache.address_range_valid
|vpiNetType:36
|vpiNet:
\_logic_net: (idle), line:97
|vpiName:idle
|vpiFullName:work@dcache.idle
|vpiNetType:36
|vpiNet:
\_logic_net: (read_miss_complete), line:98
|vpiName:read_miss_complete
|vpiFullName:work@dcache.read_miss_complete
|vpiNetType:36
|vpiNet:
\_logic_net: (store_complete), line:100
|vpiName:store_complete
|vpiFullName:work@dcache.store_complete
|vpiNetType:36
|vpiNet:
\_logic_net: (amo_alu_inputs), line:101
|vpiName:amo_alu_inputs
|vpiFullName:work@dcache.amo_alu_inputs
|vpiNet:
\_logic_net: (stage2_amo_with_load), line:178
|vpiName:stage2_amo_with_load
|vpiFullName:work@dcache.stage2_amo_with_load
|vpiNetType:36
|vpiNet:
\_logic_net: (l1_request), line:30
|vpiName:l1_request
|vpiFullName:work@dcache.l1_request
|vpiNet:
\_logic_net: (l1_response), line:31
|vpiName:l1_response
|vpiFullName:work@dcache.l1_response
|vpiNet:
\_logic_net: (ls), line:40
|vpiName:ls
|vpiFullName:work@dcache.ls
|vpiTypedef:
\_struct_typespec: (alu_inputs_t), line:301
|vpiTypedef:
\_enum_typespec: (alu_logic_op_t), line:84
|vpiTypedef:
\_enum_typespec: (alu_op_t), line:91
|vpiTypedef:
\_enum_typespec: (alu_rs1_op_t), line:97
|vpiTypedef:
\_enum_typespec: (alu_rs2_op_t), line:104
|vpiTypedef:
\_struct_typespec: (amo_alu_inputs_t), line:356
|vpiTypedef:
\_struct_typespec: (amo_details_t), line:362
|vpiTypedef:
\_enum_typespec: (amo_t), line:354
|vpiTypedef:
\_struct_typespec: (branch_inputs_t), line:313
|vpiTypedef:
\_logic_typespec: (branch_predictor_metadata_t), line:32
|vpiTypedef:
\_struct_typespec: (branch_results_t), line:330
|vpiTypedef:
\_enum_typespec: (bus_type_t), line:86
|vpiTypedef:
\_struct_typespec: (csr_inputs_t), line:396
|vpiTypedef:
\_enum_typespec: (csr_op_t), line:218
|vpiTypedef:
\_enum_typespec: (csr_t), line:201
|vpiTypedef:
\_struct_typespec: (data_access_shared_inputs_t), line:427
|vpiTypedef:
\_struct_typespec: (div_inputs_t), line:389
|vpiTypedef:
\_enum_typespec: (div_type), line:66
|vpiTypedef:
\_enum_typespec: (exception_code_t), line:245
|vpiTypedef:
\_struct_typespec: (exception_packet_t), line:263
|vpiTypedef:
\_struct_typespec: (fetch_buffer_packet_t), line:276
|vpiTypedef:
\_enum_typespec: (fifo_type_t), line:440
|vpiTypedef:
\_enum_typespec: (fn3_arith_t), line:76
|vpiTypedef:
\_enum_typespec: (fn3_branch_t), line:126
|vpiTypedef:
\_enum_typespec: (fn3_csr_t), line:212
|vpiTypedef:
\_enum_typespec: (fn3_ls_t), line:115
|vpiTypedef:
\_enum_typespec: (fn3_mul_div_t), line:138
|vpiTypedef:
\_struct_typespec: (gc_inputs_t), line:404
|vpiTypedef:
\_struct_typespec: (inflight_instruction_packet), line:271
|vpiTypedef:
\_logic_typespec: (instruction_id_t), line:30
|vpiTypedef:
\_enum_typespec: (interrupt_code_t), line:261
|vpiTypedef:
\_struct_typespec: (load_store_inputs_t), line:369
|vpiTypedef:
\_struct_typespec: (mul_inputs_t), line:383
|vpiTypedef:
\_enum_typespec: (opcodes_t), line:48
|vpiTypedef:
\_enum_typespec: (opcodes_trimmed_t), line:65
|vpiTypedef:
\_struct_typespec: (simulation_named_regfile), line:476
|vpiTypedef:
\_struct_typespec: (taiga_trace_events_t), line:442
|vpiTypedef:
\_struct_typespec: (to_l1_arbiter_packet), line:418
|vpiTypedef:
\_struct_typespec: (trace_outputs_t), line:469
|vpiTypedef:
\_logic_typespec: (unit_id_t), line:31
|vpiTypedef:
\_struct_typespec: (unit_writeback_t), line:295
|vpiTypedef:
\_enum_typespec: (vm_t), line:223
|vpiParamAssign:
\_param_assign: , line:43
|vpiRhs:
\_operation: , line:43
|vpiOpType:25
|vpiOperand:
\_operation: , line:43
|vpiOpType:25
|vpiOperand:
\_ref_obj: (DCACHE_LINES), line:43
|vpiName:DCACHE_LINES
|vpiOperand:
\_ref_obj: (DCACHE_LINE_W), line:43
|vpiName:DCACHE_LINE_W
|vpiOperand:
\_ref_obj: (DCACHE_WAYS), line:43
|vpiName:DCACHE_WAYS
|vpiLhs:
\_parameter: (DCACHE_SIZE_IN_WORDS), line:43
|vpiName:DCACHE_SIZE_IN_WORDS
|vpiLocalParam:1
|vpiParameter:
\_parameter: (DCACHE_SIZE_IN_WORDS), line:43
|uhdmallModules:
\_module: work@ddata_bank, file:third_party/cores/taiga/core/ddata_bank.sv, line:26, parent:work@div_unit_core_wrapper
|vpiDefName:work@ddata_bank
|vpiFullName:work@ddata_bank
|vpiPort:
\_port: (clk), line:30
|vpiName:clk
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (clk), line:30
|vpiName:clk
|vpiFullName:work@ddata_bank.clk
|vpiNetType:36
|vpiPort:
\_port: (addr_a), line:31
|vpiName:addr_a
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (addr_a), line:31
|vpiName:addr_a
|vpiFullName:work@ddata_bank.addr_a
|vpiNetType:36
|vpiPort:
\_port: (en_a), line:32
|vpiName:en_a
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (en_a), line:32
|vpiName:en_a
|vpiFullName:work@ddata_bank.en_a
|vpiNetType:36
|vpiPort:
\_port: (be_a), line:33
|vpiName:be_a
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (be_a), line:33
|vpiName:be_a
|vpiFullName:work@ddata_bank.be_a
|vpiNetType:36
|vpiPort:
\_port: (data_in_a), line:34
|vpiName:data_in_a
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (data_in_a), line:34
|vpiName:data_in_a
|vpiFullName:work@ddata_bank.data_in_a
|vpiNetType:36
|vpiPort:
\_port: (data_out_a), line:35
|vpiName:data_out_a
|vpiDirection:2
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (data_out_a), line:35
|vpiName:data_out_a
|vpiFullName:work@ddata_bank.data_out_a
|vpiNetType:36
|vpiPort:
\_port: (addr_b), line:38
|vpiName:addr_b
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (addr_b), line:38
|vpiName:addr_b
|vpiFullName:work@ddata_bank.addr_b
|vpiNetType:36
|vpiPort:
\_port: (en_b), line:39
|vpiName:en_b
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (en_b), line:39
|vpiName:en_b
|vpiFullName:work@ddata_bank.en_b
|vpiNetType:36
|vpiPort:
\_port: (data_in_b), line:40
|vpiName:data_in_b
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (data_in_b), line:40
|vpiName:data_in_b
|vpiFullName:work@ddata_bank.data_in_b
|vpiNetType:36
|vpiNet:
\_logic_net: (clk), line:30
|vpiNet:
\_logic_net: (addr_a), line:31
|vpiNet:
\_logic_net: (en_a), line:32
|vpiNet:
\_logic_net: (be_a), line:33
|vpiNet:
\_logic_net: (data_in_a), line:34
|vpiNet:
\_logic_net: (data_out_a), line:35
|vpiNet:
\_logic_net: (addr_b), line:38
|vpiNet:
\_logic_net: (en_b), line:39
|vpiNet:
\_logic_net: (data_in_b), line:40
|vpiTypedef:
\_struct_typespec: (alu_inputs_t), line:301
|vpiTypedef:
\_enum_typespec: (alu_logic_op_t), line:84
|vpiTypedef:
\_enum_typespec: (alu_op_t), line:91
|vpiTypedef:
\_enum_typespec: (alu_rs1_op_t), line:97
|vpiTypedef:
\_enum_typespec: (alu_rs2_op_t), line:104
|vpiTypedef:
\_struct_typespec: (amo_alu_inputs_t), line:356
|vpiTypedef:
\_struct_typespec: (amo_details_t), line:362
|vpiTypedef:
\_enum_typespec: (amo_t), line:354
|vpiTypedef:
\_struct_typespec: (branch_inputs_t), line:313
|vpiTypedef:
\_logic_typespec: (branch_predictor_metadata_t), line:32
|vpiTypedef:
\_struct_typespec: (branch_results_t), line:330
|vpiTypedef:
\_enum_typespec: (bus_type_t), line:86
|vpiTypedef:
\_struct_typespec: (csr_inputs_t), line:396
|vpiTypedef:
\_enum_typespec: (csr_op_t), line:218
|vpiTypedef:
\_enum_typespec: (csr_t), line:201
|vpiTypedef:
\_struct_typespec: (data_access_shared_inputs_t), line:427
|vpiTypedef:
\_struct_typespec: (div_inputs_t), line:389
|vpiTypedef:
\_enum_typespec: (div_type), line:66
|vpiTypedef:
\_enum_typespec: (exception_code_t), line:245
|vpiTypedef:
\_struct_typespec: (exception_packet_t), line:263
|vpiTypedef:
\_struct_typespec: (fetch_buffer_packet_t), line:276
|vpiTypedef:
\_enum_typespec: (fifo_type_t), line:440
|vpiTypedef:
\_enum_typespec: (fn3_arith_t), line:76
|vpiTypedef:
\_enum_typespec: (fn3_branch_t), line:126
|vpiTypedef:
\_enum_typespec: (fn3_csr_t), line:212
|vpiTypedef:
\_enum_typespec: (fn3_ls_t), line:115
|vpiTypedef:
\_enum_typespec: (fn3_mul_div_t), line:138
|vpiTypedef:
\_struct_typespec: (gc_inputs_t), line:404
|vpiTypedef:
\_struct_typespec: (inflight_instruction_packet), line:271
|vpiTypedef:
\_logic_typespec: (instruction_id_t), line:30
|vpiTypedef:
\_enum_typespec: (interrupt_code_t), line:261
|vpiTypedef:
\_struct_typespec: (load_store_inputs_t), line:369
|vpiTypedef:
\_struct_typespec: (mul_inputs_t), line:383
|vpiTypedef:
\_enum_typespec: (opcodes_t), line:48
|vpiTypedef:
\_enum_typespec: (opcodes_trimmed_t), line:65
|vpiTypedef:
\_struct_typespec: (simulation_named_regfile), line:476
|vpiTypedef:
\_struct_typespec: (taiga_trace_events_t), line:442
|vpiTypedef:
\_struct_typespec: (to_l1_arbiter_packet), line:418
|vpiTypedef:
\_struct_typespec: (trace_outputs_t), line:469
|vpiTypedef:
\_logic_typespec: (unit_id_t), line:31
|vpiTypedef:
\_struct_typespec: (unit_writeback_t), line:295
|vpiTypedef:
\_enum_typespec: (vm_t), line:223
|vpiParamAssign:
\_param_assign: , line:27
|vpiRhs:
\_constant: , line:27
|vpiConstType:7
|vpiDecompile:2048
|vpiSize:32
|INT:2048
|vpiLhs:
\_parameter: (LINES), line:27
|vpiName:LINES
|vpiParameter:
\_parameter: (LINES), line:27
|uhdmallModules:
\_module: work@decode, file:third_party/cores/taiga/core/decode.sv, line:26, parent:work@div_unit_core_wrapper
|vpiDefName:work@decode
|vpiFullName:work@decode
|vpiProcess:
\_always: , line:155
|vpiAlwaysType:2
|vpiStmt:
\_begin: , line:155
|vpiFullName:work@decode
|vpiStmt:
\_assignment: , line:156
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (unit_requested_for_id_gen), line:156
|vpiName:unit_requested_for_id_gen
|vpiFullName:work@decode.unit_requested_for_id_gen
|vpiRhs:
\_part_select: , line:156, parent:unit_requested
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (unit_requested)
|vpiLeftRange:
\_operation: , line:156
|vpiOpType:11
|vpiOperand:
\_ref_obj: (NUM_WB_UNITS), line:156
|vpiName:NUM_WB_UNITS
|vpiOperand:
\_constant: , line:156
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:156
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiStmt:
\_assignment: , line:157
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_bit_select: (unit_requested_for_id_gen), line:157
|vpiName:unit_requested_for_id_gen
|vpiFullName:work@decode.unit_requested_for_id_gen
|vpiIndex:
\_ref_obj: (LS_UNIT_WB_ID), line:157
|vpiName:LS_UNIT_WB_ID
|vpiRhs:
\_operation: , line:157
|vpiOpType:28
|vpiOperand:
\_bit_select: (unit_requested), line:157
|vpiName:unit_requested
|vpiFullName:work@decode.unit_requested
|vpiIndex:
\_ref_obj: (GC_UNIT_ID), line:157
|vpiName:GC_UNIT_ID
|vpiOperand:
\_ref_obj: (is_csr), line:157
|vpiName:is_csr
|vpiFullName:work@decode.is_csr
|vpiStmt:
\_assignment: , line:158
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (unit_requested_for_id_gen_int), line:158
|vpiName:unit_requested_for_id_gen_int
|vpiFullName:work@decode.unit_requested_for_id_gen_int
|vpiRhs:
\_constant: , line:158
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiStmt:
\_foreach_stmt: , line:159
|vpiFullName:work@decode
|vpiVariables:
\_chandle_var: (unit_requested_for_id_gen), line:159
|vpiName:unit_requested_for_id_gen
|vpiFullName:work@decode.unit_requested_for_id_gen
|vpiLoopVars:
\_chandle_var: (i), line:159
|vpiName:i
|vpiFullName:work@decode.i
|vpiStmt:
\_if_stmt: , line:160
|vpiCondition:
\_bit_select: (unit_requested_for_id_gen), line:160
|vpiName:unit_requested_for_id_gen
|vpiFullName:work@decode.unit_requested_for_id_gen
|vpiIndex:
\_ref_obj: (i), line:160
|vpiName:i
|vpiStmt:
\_assignment: , line:160
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (unit_requested_for_id_gen_int), line:160
|vpiName:unit_requested_for_id_gen_int
|vpiFullName:work@decode.unit_requested_for_id_gen_int
|vpiRhs:
\_part_select: , line:160, parent:i
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (i)
|vpiLeftRange:
\_operation: , line:160
|vpiOpType:11
|vpiOperand:
\_ref_obj: (WB_UNITS_WIDTH), line:160
|vpiName:WB_UNITS_WIDTH
|vpiOperand:
\_constant: , line:160
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:160
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiProcess:
\_always: , line:203
|vpiAlwaysType:2
|vpiStmt:
\_begin: , line:203
|vpiFullName:work@decode
|vpiStmt:
\_assignment: , line:204
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (unit_operands_ready), line:204
|vpiName:unit_operands_ready
|vpiFullName:work@decode.unit_operands_ready
|vpiRhs:
\_operation: , line:204
|vpiOpType:34
|vpiOperand:
\_ref_obj: (NUM_UNITS), line:204
|vpiName:NUM_UNITS
|vpiOperand:
\_operation:
|vpiOpType:33
|vpiOperand:
\_ref_obj: (operands_ready), line:204
|vpiName:operands_ready
|vpiStmt:
\_assignment: , line:205
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_bit_select: (unit_operands_ready), line:205
|vpiName:unit_operands_ready
|vpiFullName:work@decode.unit_operands_ready
|vpiIndex:
\_ref_obj: (LS_UNIT_WB_ID), line:205
|vpiName:LS_UNIT_WB_ID
|vpiRhs:
\_ref_obj: (load_store_operands_ready), line:205
|vpiName:load_store_operands_ready
|vpiFullName:work@decode.load_store_operands_ready
|vpiProcess:
\_always: , line:224
|vpiAlwaysType:2
|vpiStmt:
\_begin: , line:224
|vpiFullName:work@decode
|vpiStmt:
\_case_stmt: , line:225
|vpiCaseType:1
|vpiCondition:
\_ref_obj: (fb.alu_rs1_sel), line:225
|vpiName:fb.alu_rs1_sel
|vpiFullName:work@decode.fb.alu_rs1_sel
|vpiCaseItem:
\_case_item: , line:226
|vpiExpr:
\_ref_obj: (ALU_RS1_ZERO), line:226
|vpiName:ALU_RS1_ZERO
|vpiFullName:work@decode.ALU_RS1_ZERO
|vpiStmt:
\_assignment: , line:226
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (alu_rs1_data), line:226
|vpiName:alu_rs1_data
|vpiFullName:work@decode.alu_rs1_data
|vpiRhs:
\_constant: , line:226
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiCaseItem:
\_case_item: , line:227
|vpiExpr:
\_ref_obj: (ALU_RS1_PC), line:227
|vpiName:ALU_RS1_PC
|vpiFullName:work@decode.ALU_RS1_PC
|vpiStmt:
\_assignment: , line:227
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (alu_rs1_data), line:227
|vpiName:alu_rs1_data
|vpiFullName:work@decode.alu_rs1_data
|vpiRhs:
\_ref_obj: (fb.pc), line:227
|vpiName:fb.pc
|vpiFullName:work@decode.fb.pc
|vpiCaseItem:
\_case_item: , line:228
|vpiStmt:
\_assignment: , line:228
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (alu_rs1_data), line:228
|vpiName:alu_rs1_data
|vpiFullName:work@decode.alu_rs1_data
|vpiRhs:
\_ref_obj: (rf_decode.rs1_data), line:228
|vpiName:rf_decode.rs1_data
|vpiFullName:work@decode.rf_decode.rs1_data
|vpiStmt:
\_case_stmt: , line:231
|vpiCaseType:1
|vpiCondition:
\_ref_obj: (fb.alu_rs2_sel), line:231
|vpiName:fb.alu_rs2_sel
|vpiFullName:work@decode.fb.alu_rs2_sel
|vpiCaseItem:
\_case_item: , line:232
|vpiExpr:
\_ref_obj: (ALU_RS2_LUI_AUIPC), line:232
|vpiName:ALU_RS2_LUI_AUIPC
|vpiFullName:work@decode.ALU_RS2_LUI_AUIPC
|vpiStmt:
\_assignment: , line:232
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (alu_rs2_data), line:232
|vpiName:alu_rs2_data
|vpiFullName:work@decode.alu_rs2_data
|vpiRhs:
\_operation: , line:232
|vpiOpType:33
|vpiOperand:
\_ref_obj: (fb.instruction), line:232
|vpiName:fb.instruction
|vpiOperand:
\_constant: , line:232
|vpiConstType:3
|vpiDecompile:12'b0
|vpiSize:12
|BIN:12'b0
|vpiCaseItem:
\_case_item: , line:233
|vpiExpr:
\_ref_obj: (ALU_RS2_ARITH_IMM), line:233
|vpiName:ALU_RS2_ARITH_IMM
|vpiFullName:work@decode.ALU_RS2_ARITH_IMM
|vpiStmt:
\_assignment: , line:233
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (alu_rs2_data), line:233
|vpiName:alu_rs2_data
|vpiFullName:work@decode.alu_rs2_data
|vpiRhs:
\_operation: , line:233
|vpiOpType:67
|vpiOperand:
\_operation: , line:233
|vpiOpType:67
|vpiOperand:
\_ref_obj: (fb.instruction), line:233
|vpiName:fb.instruction
|vpiTypespec:
\_integer_typespec: , line:233
|INT:32
|vpiCaseItem:
\_case_item: , line:234
|vpiExpr:
\_ref_obj: (ALU_RS2_JAL_JALR), line:234
|vpiName:ALU_RS2_JAL_JALR
|vpiFullName:work@decode.ALU_RS2_JAL_JALR
|vpiStmt:
\_assignment: , line:234
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (alu_rs2_data), line:234
|vpiName:alu_rs2_data
|vpiFullName:work@decode.alu_rs2_data
|vpiRhs:
\_constant: , line:234
|vpiConstType:7
|vpiDecompile:4
|vpiSize:32
|INT:4
|vpiCaseItem:
\_case_item: , line:235
|vpiExpr:
\_ref_obj: (ALU_RS2_RF), line:235
|vpiName:ALU_RS2_RF
|vpiFullName:work@decode.ALU_RS2_RF
|vpiStmt:
\_assignment: , line:235
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (alu_rs2_data), line:235
|vpiName:alu_rs2_data
|vpiFullName:work@decode.alu_rs2_data
|vpiRhs:
\_ref_obj: (rf_decode.rs2_data), line:235
|vpiName:rf_decode.rs2_data
|vpiFullName:work@decode.rf_decode.rs2_data
|vpiProcess:
\_always: , line:312
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:312
|vpiCondition:
\_operation: , line:312
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:312
|vpiName:clk
|vpiFullName:work@decode.clk
|vpiStmt:
\_begin: , line:312
|vpiFullName:work@decode
|vpiStmt:
\_if_stmt: , line:313
|vpiCondition:
\_bit_select: (issue), line:313
|vpiName:issue
|vpiFullName:work@decode.issue
|vpiIndex:
\_ref_obj: (GC_UNIT_ID), line:313
|vpiName:GC_UNIT_ID
|vpiStmt:
\_begin: , line:313
|vpiFullName:work@decode
|vpiStmt:
\_assignment: , line:314
|vpiOpType:82
|vpiLhs:
\_ref_obj: (gc_inputs.pc), line:314
|vpiName:gc_inputs.pc
|vpiFullName:work@decode.gc_inputs.pc
|vpiRhs:
\_ref_obj: (fb.pc), line:314
|vpiName:fb.pc
|vpiFullName:work@decode.fb.pc
|vpiStmt:
\_assignment: , line:315
|vpiOpType:82
|vpiLhs:
\_ref_obj: (gc_inputs.instruction), line:315
|vpiName:gc_inputs.instruction
|vpiFullName:work@decode.gc_inputs.instruction
|vpiRhs:
\_ref_obj: (fb.instruction), line:315
|vpiName:fb.instruction
|vpiFullName:work@decode.fb.instruction
|vpiStmt:
\_assignment: , line:316
|vpiOpType:82
|vpiLhs:
\_ref_obj: (gc_inputs.rs1), line:316
|vpiName:gc_inputs.rs1
|vpiFullName:work@decode.gc_inputs.rs1
|vpiRhs:
\_ref_obj: (rf_decode.rs1_data), line:316
|vpiName:rf_decode.rs1_data
|vpiFullName:work@decode.rf_decode.rs1_data
|vpiStmt:
\_assignment: , line:317
|vpiOpType:82
|vpiLhs:
\_ref_obj: (gc_inputs.rs2), line:317
|vpiName:gc_inputs.rs2
|vpiFullName:work@decode.gc_inputs.rs2
|vpiRhs:
\_ref_obj: (rf_decode.rs2_data), line:317
|vpiName:rf_decode.rs2_data
|vpiFullName:work@decode.rf_decode.rs2_data
|vpiStmt:
\_assignment: , line:318
|vpiOpType:82
|vpiLhs:
\_ref_obj: (gc_inputs.rd_is_zero), line:318
|vpiName:gc_inputs.rd_is_zero
|vpiFullName:work@decode.gc_inputs.rd_is_zero
|vpiRhs:
\_ref_obj: (rd_zero), line:318
|vpiName:rd_zero
|vpiFullName:work@decode.rd_zero
|vpiStmt:
\_assignment: , line:319
|vpiOpType:82
|vpiLhs:
\_ref_obj: (gc_inputs.is_fence), line:319
|vpiName:gc_inputs.is_fence
|vpiFullName:work@decode.gc_inputs.is_fence
|vpiRhs:
\_operation: , line:319
|vpiOpType:26
|vpiOperand:
\_operation: , line:319
|vpiOpType:14
|vpiOperand:
\_ref_obj: (opcode_trim), line:319
|vpiName:opcode_trim
|vpiFullName:work@decode.opcode_trim
|vpiOperand:
\_ref_obj: (FENCE_T), line:319
|vpiName:FENCE_T
|vpiFullName:work@decode.FENCE_T
|vpiOperand:
\_operation: , line:319
|vpiOpType:4
|vpiOperand:
\_bit_select: (fn3), line:319
|vpiName:fn3
|vpiIndex:
\_constant: , line:319
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiStmt:
\_assignment: , line:320
|vpiOpType:82
|vpiLhs:
\_ref_obj: (gc_inputs.is_csr), line:320
|vpiName:gc_inputs.is_csr
|vpiFullName:work@decode.gc_inputs.is_csr
|vpiRhs:
\_ref_obj: (is_csr), line:320
|vpiName:is_csr
|vpiFullName:work@decode.is_csr
|vpiStmt:
\_assignment: , line:322
|vpiOpType:82
|vpiLhs:
\_ref_obj: (gc_inputs.is_ecall), line:322
|vpiName:gc_inputs.is_ecall
|vpiFullName:work@decode.gc_inputs.is_ecall
|vpiRhs:
\_operation: , line:322
|vpiOpType:26
|vpiOperand:
\_operation: , line:322
|vpiOpType:26
|vpiOperand:
\_bit_select: (issue), line:322
|vpiName:issue
|vpiFullName:work@decode.issue
|vpiIndex:
\_ref_obj: (GC_UNIT_ID), line:322
|vpiName:GC_UNIT_ID
|vpiOperand:
\_ref_obj: (environment_op), line:322
|vpiName:environment_op
|vpiFullName:work@decode.environment_op
|vpiOperand:
\_operation: , line:322
|vpiOpType:14
|vpiOperand:
\_ref_obj: (fb.instruction), line:322
|vpiName:fb.instruction
|vpiFullName:work@decode.fb.instruction
|vpiOperand:
\_constant: , line:322
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiStmt:
\_assignment: , line:323
|vpiOpType:82
|vpiLhs:
\_ref_obj: (gc_inputs.is_ebreak), line:323
|vpiName:gc_inputs.is_ebreak
|vpiFullName:work@decode.gc_inputs.is_ebreak
|vpiRhs:
\_operation: , line:323
|vpiOpType:26
|vpiOperand:
\_operation: , line:323
|vpiOpType:26
|vpiOperand:
\_bit_select: (issue), line:323
|vpiName:issue
|vpiFullName:work@decode.issue
|vpiIndex:
\_ref_obj: (GC_UNIT_ID), line:323
|vpiName:GC_UNIT_ID
|vpiOperand:
\_ref_obj: (environment_op), line:323
|vpiName:environment_op
|vpiFullName:work@decode.environment_op
|vpiOperand:
\_operation: , line:323
|vpiOpType:14
|vpiOperand:
\_ref_obj: (fb.instruction), line:323
|vpiName:fb.instruction
|vpiFullName:work@decode.fb.instruction
|vpiOperand:
\_constant: , line:323
|vpiConstType:3
|vpiDecompile:2'b01
|vpiSize:2
|BIN:2'b01
|vpiStmt:
\_assignment: , line:324
|vpiOpType:82
|vpiLhs:
\_ref_obj: (gc_inputs.is_ret), line:324
|vpiName:gc_inputs.is_ret
|vpiFullName:work@decode.gc_inputs.is_ret
|vpiRhs:
\_operation: , line:324
|vpiOpType:26
|vpiOperand:
\_operation: , line:324
|vpiOpType:26
|vpiOperand:
\_bit_select: (issue), line:324
|vpiName:issue
|vpiFullName:work@decode.issue
|vpiIndex:
\_ref_obj: (GC_UNIT_ID), line:324
|vpiName:GC_UNIT_ID
|vpiOperand:
\_ref_obj: (environment_op), line:324
|vpiName:environment_op
|vpiFullName:work@decode.environment_op
|vpiOperand:
\_operation: , line:324
|vpiOpType:14
|vpiOperand:
\_ref_obj: (fb.instruction), line:324
|vpiName:fb.instruction
|vpiFullName:work@decode.fb.instruction
|vpiOperand:
\_constant: , line:324
|vpiConstType:3
|vpiDecompile:2'b10
|vpiSize:2
|BIN:2'b10
|vpiStmt:
\_assignment: , line:325
|vpiOpType:82
|vpiLhs:
\_ref_obj: (gc_inputs.is_i_fence), line:325
|vpiName:gc_inputs.is_i_fence
|vpiFullName:work@decode.gc_inputs.is_i_fence
|vpiRhs:
\_operation: , line:325
|vpiOpType:26
|vpiOperand:
\_bit_select: (issue), line:325
|vpiName:issue
|vpiFullName:work@decode.issue
|vpiIndex:
\_ref_obj: (GC_UNIT_ID), line:325
|vpiName:GC_UNIT_ID
|vpiOperand:
\_ref_obj: (ifence), line:325
|vpiName:ifence
|vpiFullName:work@decode.ifence
|vpiProcess:
\_always: , line:402
|vpiAlwaysType:2
|vpiStmt:
\_begin: , line:402
|vpiFullName:work@decode
|vpiStmt:
\_assignment: , line:403
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (illegal_instruction), line:403
|vpiName:illegal_instruction
|vpiFullName:work@decode.illegal_instruction
|vpiRhs:
\_operation: , line:403
|vpiOpType:3
|vpiOperand:
\_operation: , line:403
|vpiOpType:95
|vpiOperand:
\_ref_obj: (opcode), line:403
|vpiName:opcode
|vpiFullName:work@decode.opcode
|vpiOperand:
\_ref_obj: (LUI), line:403
|vpiName:LUI
|vpiFullName:work@decode.LUI
|vpiOperand:
\_ref_obj: (AUIPC), line:403
|vpiName:AUIPC
|vpiFullName:work@decode.AUIPC
|vpiOperand:
\_ref_obj: (JAL), line:403
|vpiName:JAL
|vpiFullName:work@decode.JAL
|vpiOperand:
\_ref_obj: (JALR), line:403
|vpiName:JALR
|vpiFullName:work@decode.JALR
|vpiOperand:
\_ref_obj: (BRANCH), line:403
|vpiName:BRANCH
|vpiFullName:work@decode.BRANCH
|vpiOperand:
\_ref_obj: (LOAD), line:403
|vpiName:LOAD
|vpiFullName:work@decode.LOAD
|vpiOperand:
\_ref_obj: (STORE), line:403
|vpiName:STORE
|vpiFullName:work@decode.STORE
|vpiOperand:
\_ref_obj: (ARITH), line:403
|vpiName:ARITH
|vpiFullName:work@decode.ARITH
|vpiOperand:
\_ref_obj: (ARITH_IMM), line:403
|vpiName:ARITH_IMM
|vpiFullName:work@decode.ARITH_IMM
|vpiOperand:
\_ref_obj: (FENCE), line:403
|vpiName:FENCE
|vpiFullName:work@decode.FENCE
|vpiOperand:
\_ref_obj: (AMO), line:403
|vpiName:AMO
|vpiFullName:work@decode.AMO
|vpiOperand:
\_ref_obj: (SYSTEM), line:403
|vpiName:SYSTEM
|vpiFullName:work@decode.SYSTEM
|vpiStmt:
\_if_stmt: , line:404
|vpiCondition:
\_operation: , line:404
|vpiOpType:14
|vpiOperand:
\_ref_obj: (opcode), line:404
|vpiName:opcode
|vpiFullName:work@decode.opcode
|vpiOperand:
\_ref_obj: (ARITH), line:404
|vpiName:ARITH
|vpiFullName:work@decode.ARITH
|vpiStmt:
\_begin: , line:404
|vpiFullName:work@decode
|vpiStmt:
\_if_else: , line:405
|vpiCondition:
\_operation: , line:405
|vpiOpType:26
|vpiOperand:
\_operation: , line:405
|vpiOpType:3
|vpiOperand:
\_ref_obj: (USE_MUL), line:405
|vpiName:USE_MUL
|vpiFullName:work@decode.USE_MUL
|vpiOperand:
\_operation: , line:405
|vpiOpType:3
|vpiOperand:
\_ref_obj: (USE_DIV), line:405
|vpiName:USE_DIV
|vpiFullName:work@decode.USE_DIV
|vpiStmt:
\_assignment: , line:406
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (illegal_instruction), line:406
|vpiName:illegal_instruction
|vpiFullName:work@decode.illegal_instruction
|vpiRhs:
\_ref_obj: (fb.instruction), line:406
|vpiName:fb.instruction
|vpiFullName:work@decode.fb.instruction
|vpiElseStmt:
\_if_else: , line:407
|vpiCondition:
\_operation: , line:407
|vpiOpType:26
|vpiOperand:
\_operation: , line:407
|vpiOpType:3
|vpiOperand:
\_ref_obj: (USE_MUL), line:407
|vpiName:USE_MUL
|vpiFullName:work@decode.USE_MUL
|vpiOperand:
\_ref_obj: (USE_DIV), line:407
|vpiName:USE_DIV
|vpiFullName:work@decode.USE_DIV
|vpiStmt:
\_assignment: , line:408
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (illegal_instruction), line:408
|vpiName:illegal_instruction
|vpiFullName:work@decode.illegal_instruction
|vpiRhs:
\_operation: , line:408
|vpiOpType:28
|vpiOperand:
\_ref_obj: (fb.instruction), line:408
|vpiName:fb.instruction
|vpiFullName:work@decode.fb.instruction
|vpiOperand:
\_operation: , line:408
|vpiOpType:4
|vpiOperand:
\_bit_select: (fn3), line:408
|vpiName:fn3
|vpiIndex:
\_constant: , line:408
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiElseStmt:
\_if_else: , line:409
|vpiCondition:
\_operation: , line:409
|vpiOpType:26
|vpiOperand:
\_operation: , line:409
|vpiOpType:3
|vpiOperand:
\_ref_obj: (USE_MUL), line:409
|vpiName:USE_MUL
|vpiFullName:work@decode.USE_MUL
|vpiOperand:
\_operation: , line:409
|vpiOpType:3
|vpiOperand:
\_ref_obj: (USE_DIV), line:409
|vpiName:USE_DIV
|vpiFullName:work@decode.USE_DIV
|vpiStmt:
\_assignment: , line:410
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (illegal_instruction), line:410
|vpiName:illegal_instruction
|vpiFullName:work@decode.illegal_instruction
|vpiRhs:
\_operation: , line:410
|vpiOpType:28
|vpiOperand:
\_ref_obj: (fb.instruction), line:410
|vpiName:fb.instruction
|vpiFullName:work@decode.fb.instruction
|vpiOperand:
\_bit_select: (fn3), line:410
|vpiName:fn3
|vpiFullName:work@decode.fn3
|vpiIndex:
\_constant: , line:410
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiElseStmt:
\_assignment: , line:412
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (illegal_instruction), line:412
|vpiName:illegal_instruction
|vpiFullName:work@decode.illegal_instruction
|vpiRhs:
\_constant: , line:412
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiPort:
\_port: (clk), line:27
|vpiName:clk
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (clk), line:27
|vpiName:clk
|vpiFullName:work@decode.clk
|vpiNetType:36
|vpiPort:
\_port: (rst), line:28
|vpiName:rst
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (rst), line:28
|vpiName:rst
|vpiFullName:work@decode.rst
|vpiNetType:36
|vpiPort:
\_port: (pre_decode_pop), line:30
|vpiName:pre_decode_pop
|vpiDirection:2
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (pre_decode_pop), line:30
|vpiName:pre_decode_pop
|vpiFullName:work@decode.pre_decode_pop
|vpiNetType:36
|vpiPort:
\_port: (fb_valid), line:31
|vpiName:fb_valid
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (fb_valid), line:31
|vpiName:fb_valid
|vpiFullName:work@decode.fb_valid
|vpiNetType:36
|vpiPort:
\_port: (fb), line:32
|vpiName:fb
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (fb), line:32
|vpiName:fb
|vpiFullName:work@decode.fb
|vpiPort:
\_port: (ti), line:34
|vpiName:ti
|vpiDirection:5
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_modport: (decode)
|vpiPort:
\_port: (rf_decode), line:35
|vpiName:rf_decode
|vpiDirection:5
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_modport: (decode)
|vpiPort:
\_port: (alu_inputs), line:37
|vpiName:alu_inputs
|vpiDirection:2
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (alu_inputs), line:37
|vpiName:alu_inputs
|vpiFullName:work@decode.alu_inputs
|vpiPort:
\_port: (ls_inputs), line:38
|vpiName:ls_inputs
|vpiDirection:2
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (ls_inputs), line:38
|vpiName:ls_inputs
|vpiFullName:work@decode.ls_inputs
|vpiPort:
\_port: (branch_inputs), line:39
|vpiName:branch_inputs
|vpiDirection:2
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (branch_inputs), line:39
|vpiName:branch_inputs
|vpiFullName:work@decode.branch_inputs
|vpiPort:
\_port: (gc_inputs), line:40
|vpiName:gc_inputs
|vpiDirection:2
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (gc_inputs), line:40
|vpiName:gc_inputs
|vpiFullName:work@decode.gc_inputs
|vpiPort:
\_port: (mul_inputs), line:41
|vpiName:mul_inputs
|vpiDirection:2
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (mul_inputs), line:41
|vpiName:mul_inputs
|vpiFullName:work@decode.mul_inputs
|vpiPort:
\_port: (div_inputs), line:42
|vpiName:div_inputs
|vpiDirection:2
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (div_inputs), line:42
|vpiName:div_inputs
|vpiFullName:work@decode.div_inputs
|vpiPort:
\_port: (unit_issue), line:44
|vpiName:unit_issue
|vpiDirection:5
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_modport: (decode)
|vpiPort:
\_port: (gc_issue_hold), line:46
|vpiName:gc_issue_hold
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (gc_issue_hold), line:46
|vpiName:gc_issue_hold
|vpiFullName:work@decode.gc_issue_hold
|vpiNetType:36
|vpiPort:
\_port: (gc_fetch_flush), line:47
|vpiName:gc_fetch_flush
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (gc_fetch_flush), line:47
|vpiName:gc_fetch_flush
|vpiFullName:work@decode.gc_fetch_flush
|vpiNetType:36
|vpiPort:
\_port: (gc_issue_flush), line:48
|vpiName:gc_issue_flush
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (gc_issue_flush), line:48
|vpiName:gc_issue_flush
|vpiFullName:work@decode.gc_issue_flush
|vpiNetType:36
|vpiPort:
\_port: (gc_flush_required), line:49
|vpiName:gc_flush_required
|vpiDirection:2
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (gc_flush_required), line:49
|vpiName:gc_flush_required
|vpiFullName:work@decode.gc_flush_required
|vpiNetType:36
|vpiPort:
\_port: (load_store_issue), line:51
|vpiName:load_store_issue
|vpiDirection:2
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (load_store_issue), line:51
|vpiName:load_store_issue
|vpiFullName:work@decode.load_store_issue
|vpiNetType:36
|vpiPort:
\_port: (store_issued_with_data), line:52
|vpiName:store_issued_with_data
|vpiDirection:2
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (store_issued_with_data), line:52
|vpiName:store_issued_with_data
|vpiFullName:work@decode.store_issued_with_data
|vpiNetType:36
|vpiPort:
\_port: (store_data), line:53
|vpiName:store_data
|vpiDirection:2
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (store_data), line:53
|vpiName:store_data
|vpiFullName:work@decode.store_data
|vpiNetType:36
|vpiPort:
\_port: (instruction_issued), line:55
|vpiName:instruction_issued
|vpiDirection:2
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (instruction_issued), line:55
|vpiName:instruction_issued
|vpiFullName:work@decode.instruction_issued
|vpiNetType:36
|vpiPort:
\_port: (instruction_issued_no_rd), line:56
|vpiName:instruction_issued_no_rd
|vpiDirection:2
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (instruction_issued_no_rd), line:56
|vpiName:instruction_issued_no_rd
|vpiFullName:work@decode.instruction_issued_no_rd
|vpiNetType:36
|vpiPort:
\_port: (instruction_issued_with_rd), line:57
|vpiName:instruction_issued_with_rd
|vpiDirection:2
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (instruction_issued_with_rd), line:57
|vpiName:instruction_issued_with_rd
|vpiFullName:work@decode.instruction_issued_with_rd
|vpiNetType:36
|vpiPort:
\_port: (illegal_instruction), line:58
|vpiName:illegal_instruction
|vpiDirection:2
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (illegal_instruction), line:58
|vpiName:illegal_instruction
|vpiFullName:work@decode.illegal_instruction
|vpiNetType:36
|vpiPort:
\_port: (tr_operand_stall), line:61
|vpiName:tr_operand_stall
|vpiDirection:2
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (tr_operand_stall), line:61
|vpiName:tr_operand_stall
|vpiFullName:work@decode.tr_operand_stall
|vpiNetType:36
|vpiPort:
\_port: (tr_unit_stall), line:62
|vpiName:tr_unit_stall
|vpiDirection:2
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (tr_unit_stall), line:62
|vpiName:tr_unit_stall
|vpiFullName:work@decode.tr_unit_stall
|vpiNetType:36
|vpiPort:
\_port: (tr_no_id_stall), line:63
|vpiName:tr_no_id_stall
|vpiDirection:2
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (tr_no_id_stall), line:63
|vpiName:tr_no_id_stall
|vpiFullName:work@decode.tr_no_id_stall
|vpiNetType:36
|vpiPort:
\_port: (tr_no_instruction_stall), line:64
|vpiName:tr_no_instruction_stall
|vpiDirection:2
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (tr_no_instruction_stall), line:64
|vpiName:tr_no_instruction_stall
|vpiFullName:work@decode.tr_no_instruction_stall
|vpiNetType:36
|vpiPort:
\_port: (tr_other_stall), line:65
|vpiName:tr_other_stall
|vpiDirection:2
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (tr_other_stall), line:65
|vpiName:tr_other_stall
|vpiFullName:work@decode.tr_other_stall
|vpiNetType:36
|vpiPort:
\_port: (tr_branch_operand_stall), line:66
|vpiName:tr_branch_operand_stall
|vpiDirection:2
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (tr_branch_operand_stall), line:66
|vpiName:tr_branch_operand_stall
|vpiFullName:work@decode.tr_branch_operand_stall
|vpiNetType:36
|vpiPort:
\_port: (tr_alu_operand_stall), line:67
|vpiName:tr_alu_operand_stall
|vpiDirection:2
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (tr_alu_operand_stall), line:67
|vpiName:tr_alu_operand_stall
|vpiFullName:work@decode.tr_alu_operand_stall
|vpiNetType:36
|vpiPort:
\_port: (tr_ls_operand_stall), line:68
|vpiName:tr_ls_operand_stall
|vpiDirection:2
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (tr_ls_operand_stall), line:68
|vpiName:tr_ls_operand_stall
|vpiFullName:work@decode.tr_ls_operand_stall
|vpiNetType:36
|vpiPort:
\_port: (tr_div_operand_stall), line:69
|vpiName:tr_div_operand_stall
|vpiDirection:2
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (tr_div_operand_stall), line:69
|vpiName:tr_div_operand_stall
|vpiFullName:work@decode.tr_div_operand_stall
|vpiNetType:36
|vpiPort:
\_port: (tr_instruction_issued_dec), line:71
|vpiName:tr_instruction_issued_dec
|vpiDirection:2
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (tr_instruction_issued_dec), line:71
|vpiName:tr_instruction_issued_dec
|vpiFullName:work@decode.tr_instruction_issued_dec
|vpiNetType:36
|vpiPort:
\_port: (tr_instruction_pc_dec), line:72
|vpiName:tr_instruction_pc_dec
|vpiDirection:2
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (tr_instruction_pc_dec), line:72
|vpiName:tr_instruction_pc_dec
|vpiFullName:work@decode.tr_instruction_pc_dec
|vpiNetType:36
|vpiPort:
\_port: (tr_instruction_data_dec), line:73
|vpiName:tr_instruction_data_dec
|vpiDirection:2
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (tr_instruction_data_dec), line:73
|vpiName:tr_instruction_data_dec
|vpiFullName:work@decode.tr_instruction_data_dec
|vpiNetType:36
|vpiContAssign:
\_cont_assign: , line:126
|vpiRhs:
\_ref_obj: (instruction_issued), line:126
|vpiName:instruction_issued
|vpiFullName:work@decode.instruction_issued
|vpiLhs:
\_ref_obj: (pre_decode_pop), line:126
|vpiName:pre_decode_pop
|vpiFullName:work@decode.pre_decode_pop
|vpiContAssign:
\_cont_assign: , line:128
|vpiRhs:
\_ref_obj: (fb.instruction), line:128
|vpiName:fb.instruction
|vpiFullName:work@decode.fb.instruction
|vpiLhs:
\_ref_obj: (opcode), line:128
|vpiName:opcode
|vpiFullName:work@decode.opcode
|vpiContAssign:
\_cont_assign: , line:129
|vpiRhs:
\_part_select: , line:129, parent:opcode
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (opcode)
|vpiLeftRange:
\_constant: , line:129
|vpiConstType:7
|vpiDecompile:6
|vpiSize:32
|INT:6
|vpiRightRange:
\_constant: , line:129
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiLhs:
\_ref_obj: (opcode_trim), line:129
|vpiName:opcode_trim
|vpiFullName:work@decode.opcode_trim
|vpiContAssign:
\_cont_assign: , line:130
|vpiRhs:
\_ref_obj: (fb.instruction), line:130
|vpiName:fb.instruction
|vpiFullName:work@decode.fb.instruction
|vpiLhs:
\_ref_obj: (fn3), line:130
|vpiName:fn3
|vpiFullName:work@decode.fn3
|vpiContAssign:
\_cont_assign: , line:132
|vpiRhs:
\_ref_obj: (fb.uses_rs1), line:132
|vpiName:fb.uses_rs1
|vpiFullName:work@decode.fb.uses_rs1
|vpiLhs:
\_ref_obj: (uses_rs1), line:132
|vpiName:uses_rs1
|vpiFullName:work@decode.uses_rs1
|vpiContAssign:
\_cont_assign: , line:133
|vpiRhs:
\_ref_obj: (fb.uses_rs2), line:133
|vpiName:fb.uses_rs2
|vpiFullName:work@decode.fb.uses_rs2
|vpiLhs:
\_ref_obj: (uses_rs2), line:133
|vpiName:uses_rs2
|vpiFullName:work@decode.uses_rs2
|vpiContAssign:
\_cont_assign: , line:134
|vpiRhs:
\_ref_obj: (fb.uses_rd), line:134
|vpiName:fb.uses_rd
|vpiFullName:work@decode.fb.uses_rd
|vpiLhs:
\_ref_obj: (uses_rd), line:134
|vpiName:uses_rd
|vpiFullName:work@decode.uses_rd
|vpiContAssign:
\_cont_assign: , line:135
|vpiRhs:
\_operation: , line:135
|vpiOpType:8
|vpiOperand:
\_ref_obj: (future_rd_addr), line:135
|vpiName:future_rd_addr
|vpiFullName:work@decode.future_rd_addr
|vpiLhs:
\_ref_obj: (rd_zero), line:135
|vpiName:rd_zero
|vpiFullName:work@decode.rd_zero
|vpiContAssign:
\_cont_assign: , line:137
|vpiRhs:
\_ref_obj: (fb.instruction), line:137
|vpiName:fb.instruction
|vpiFullName:work@decode.fb.instruction
|vpiLhs:
\_ref_obj: (rs1_addr), line:137
|vpiName:rs1_addr
|vpiFullName:work@decode.rs1_addr
|vpiContAssign:
\_cont_assign: , line:138
|vpiRhs:
\_ref_obj: (fb.instruction), line:138
|vpiName:fb.instruction
|vpiFullName:work@decode.fb.instruction
|vpiLhs:
\_ref_obj: (rs2_addr), line:138
|vpiName:rs2_addr
|vpiFullName:work@decode.rs2_addr
|vpiContAssign:
\_cont_assign: , line:139
|vpiRhs:
\_ref_obj: (fb.instruction), line:139
|vpiName:fb.instruction
|vpiFullName:work@decode.fb.instruction
|vpiLhs:
\_ref_obj: (future_rd_addr), line:139
|vpiName:future_rd_addr
|vpiFullName:work@decode.future_rd_addr
|vpiContAssign:
\_cont_assign: , line:140
|vpiRhs:
\_operation: , line:140
|vpiOpType:26
|vpiOperand:
\_operation: , line:140
|vpiOpType:95
|vpiOperand:
\_ref_obj: (opcode_trim), line:140
|vpiName:opcode_trim
|vpiFullName:work@decode.opcode_trim
|vpiOperand:
\_ref_obj: (LUI_T), line:140
|vpiName:LUI_T
|vpiOperand:
\_ref_obj: (AUIPC_T), line:140
|vpiName:AUIPC_T
|vpiOperand:
\_ref_obj: (ARITH_T), line:140
|vpiName:ARITH_T
|vpiOperand:
\_ref_obj: (ARITH_IMM_T), line:140
|vpiName:ARITH_IMM_T
|vpiOperand:
\_ref_obj: (rd_zero), line:140
|vpiName:rd_zero
|vpiFullName:work@decode.rd_zero
|vpiLhs:
\_ref_obj: (nop), line:140
|vpiName:nop
|vpiFullName:work@decode.nop
|vpiContAssign:
\_cont_assign: , line:144
|vpiRhs:
\_ref_obj: (rs1_addr), line:144
|vpiName:rs1_addr
|vpiFullName:work@decode.rs1_addr
|vpiLhs:
\_ref_obj: (rf_decode.rs1_addr), line:144
|vpiName:rf_decode.rs1_addr
|vpiFullName:work@decode.rf_decode.rs1_addr
|vpiContAssign:
\_cont_assign: , line:145
|vpiRhs:
\_ref_obj: (rs2_addr), line:145
|vpiName:rs2_addr
|vpiFullName:work@decode.rs2_addr
|vpiLhs:
\_ref_obj: (rf_decode.rs2_addr), line:145
|vpiName:rf_decode.rs2_addr
|vpiFullName:work@decode.rf_decode.rs2_addr
|vpiContAssign:
\_cont_assign: , line:146
|vpiRhs:
\_ref_obj: (future_rd_addr), line:146
|vpiName:future_rd_addr
|vpiFullName:work@decode.future_rd_addr
|vpiLhs:
\_ref_obj: (rf_decode.future_rd_addr), line:146
|vpiName:rf_decode.future_rd_addr
|vpiFullName:work@decode.rf_decode.future_rd_addr
|vpiContAssign:
\_cont_assign: , line:147
|vpiRhs:
\_operation: , line:147
|vpiOpType:28
|vpiOperand:
\_ref_obj: (instruction_issued_with_rd), line:147
|vpiName:instruction_issued_with_rd
|vpiFullName:work@decode.instruction_issued_with_rd
|vpiOperand:
\_operation: , line:147
|vpiOpType:4
|vpiOperand:
\_ref_obj: (rd_zero), line:147
|vpiName:rd_zero
|vpiFullName:work@decode.rd_zero
|vpiLhs:
\_ref_obj: (rf_decode.instruction_issued), line:147
|vpiName:rf_decode.instruction_issued
|vpiFullName:work@decode.rf_decode.instruction_issued
|vpiContAssign:
\_cont_assign: , line:148
|vpiRhs:
\_ref_obj: (ti.issue_id), line:148
|vpiName:ti.issue_id
|vpiFullName:work@decode.ti.issue_id
|vpiLhs:
\_ref_obj: (rf_decode.id), line:148
|vpiName:rf_decode.id
|vpiFullName:work@decode.rf_decode.id
|vpiContAssign:
\_cont_assign: , line:149
|vpiRhs:
\_ref_obj: (uses_rs1), line:149
|vpiName:uses_rs1
|vpiFullName:work@decode.uses_rs1
|vpiLhs:
\_ref_obj: (rf_decode.uses_rs1), line:149
|vpiName:rf_decode.uses_rs1
|vpiFullName:work@decode.rf_decode.uses_rs1
|vpiContAssign:
\_cont_assign: , line:150
|vpiRhs:
\_ref_obj: (uses_rs2), line:150
|vpiName:uses_rs2
|vpiFullName:work@decode.uses_rs2
|vpiLhs:
\_ref_obj: (rf_decode.uses_rs2), line:150
|vpiName:rf_decode.uses_rs2
|vpiFullName:work@decode.rf_decode.uses_rs2
|vpiContAssign:
\_cont_assign: , line:163
|vpiRhs:
\_ref_obj: (future_rd_addr), line:163
|vpiName:future_rd_addr
|vpiFullName:work@decode.future_rd_addr
|vpiLhs:
\_ref_obj: (ti.inflight_packet), line:163
|vpiName:ti.inflight_packet
|vpiFullName:work@decode.ti.inflight_packet
|vpiContAssign:
\_cont_assign: , line:164
|vpiRhs:
\_ref_obj: (is_store), line:164
|vpiName:is_store
|vpiFullName:work@decode.is_store
|vpiLhs:
\_ref_obj: (ti.inflight_packet), line:164
|vpiName:ti.inflight_packet
|vpiFullName:work@decode.ti.inflight_packet
|vpiContAssign:
\_cont_assign: , line:165
|vpiRhs:
\_operation: , line:165
|vpiOpType:28
|vpiOperand:
\_ref_obj: (instruction_issued), line:165
|vpiName:instruction_issued
|vpiFullName:work@decode.instruction_issued
|vpiOperand:
\_operation: , line:165
|vpiOpType:29
|vpiOperand:
\_ref_obj: (uses_rd), line:165
|vpiName:uses_rd
|vpiFullName:work@decode.uses_rd
|vpiOperand:
\_bit_select: (unit_requested), line:165
|vpiName:unit_requested
|vpiFullName:work@decode.unit_requested
|vpiIndex:
\_ref_obj: (LS_UNIT_WB_ID), line:165
|vpiName:LS_UNIT_WB_ID
|vpiFullName:work@decode.LS_UNIT_WB_ID
|vpiLhs:
\_ref_obj: (ti.issued), line:165
|vpiName:ti.issued
|vpiFullName:work@decode.ti.issued
|vpiContAssign:
\_cont_assign: , line:166
|vpiRhs:
\_ref_obj: (unit_requested_for_id_gen_int), line:166
|vpiName:unit_requested_for_id_gen_int
|vpiFullName:work@decode.unit_requested_for_id_gen_int
|vpiLhs:
\_ref_obj: (ti.issue_unit_id), line:166
|vpiName:ti.issue_unit_id
|vpiFullName:work@decode.ti.issue_unit_id
|vpiContAssign:
\_cont_assign: , line:170
|vpiRhs:
\_ref_obj: (fb.instruction), line:170
|vpiName:fb.instruction
|vpiFullName:work@decode.fb.instruction
|vpiLhs:
\_ref_obj: (mult_div_op), line:170
|vpiName:mult_div_op
|vpiFullName:work@decode.mult_div_op
|vpiContAssign:
\_cont_assign: , line:172
|vpiRhs:
\_operation: , line:172
|vpiOpType:95
|vpiOperand:
\_ref_obj: (opcode_trim), line:172
|vpiName:opcode_trim
|vpiFullName:work@decode.opcode_trim
|vpiOperand:
\_ref_obj: (BRANCH_T), line:172
|vpiName:BRANCH_T
|vpiOperand:
\_ref_obj: (JAL_T), line:172
|vpiName:JAL_T
|vpiOperand:
\_ref_obj: (JALR_T), line:172
|vpiName:JALR_T
|vpiLhs:
\_bit_select: (unit_requested), line:172
|vpiName:unit_requested
|vpiFullName:work@decode.unit_requested
|vpiIndex:
\_ref_obj: (BRANCH_UNIT_ID), line:172
|vpiName:BRANCH_UNIT_ID
|vpiContAssign:
\_cont_assign: , line:173
|vpiRhs:
\_ref_obj: (fb.alu_request), line:173
|vpiName:fb.alu_request
|vpiFullName:work@decode.fb.alu_request
|vpiLhs:
\_bit_select: (unit_requested), line:173
|vpiName:unit_requested
|vpiFullName:work@decode.unit_requested
|vpiIndex:
\_ref_obj: (ALU_UNIT_WB_ID), line:173
|vpiName:ALU_UNIT_WB_ID
|vpiContAssign:
\_cont_assign: , line:174
|vpiRhs:
\_operation: , line:174
|vpiOpType:95
|vpiOperand:
\_ref_obj: (opcode_trim), line:174
|vpiName:opcode_trim
|vpiFullName:work@decode.opcode_trim
|vpiOperand:
\_ref_obj: (LOAD_T), line:174
|vpiName:LOAD_T
|vpiOperand:
\_ref_obj: (STORE_T), line:174
|vpiName:STORE_T
|vpiOperand:
\_ref_obj: (AMO_T), line:174
|vpiName:AMO_T
|vpiLhs:
\_bit_select: (unit_requested), line:174
|vpiName:unit_requested
|vpiFullName:work@decode.unit_requested
|vpiIndex:
\_ref_obj: (LS_UNIT_WB_ID), line:174
|vpiName:LS_UNIT_WB_ID
|vpiContAssign:
\_cont_assign: , line:175
|vpiRhs:
\_operation: , line:175
|vpiOpType:95
|vpiOperand:
\_ref_obj: (opcode_trim), line:175
|vpiName:opcode_trim
|vpiFullName:work@decode.opcode_trim
|vpiOperand:
\_ref_obj: (SYSTEM_T), line:175
|vpiName:SYSTEM_T
|vpiOperand:
\_ref_obj: (FENCE_T), line:175
|vpiName:FENCE_T
|vpiLhs:
\_bit_select: (unit_requested), line:175
|vpiName:unit_requested
|vpiFullName:work@decode.unit_requested
|vpiIndex:
\_ref_obj: (GC_UNIT_ID), line:175
|vpiName:GC_UNIT_ID
|vpiContAssign:
\_cont_assign: , line:185
|vpiRhs:
\_operation: , line:185
|vpiOpType:95
|vpiOperand:
\_ref_obj: (opcode_trim), line:185
|vpiName:opcode_trim
|vpiFullName:work@decode.opcode_trim
|vpiOperand:
\_ref_obj: (BRANCH_T), line:185
|vpiName:BRANCH_T
|vpiOperand:
\_ref_obj: (JAL_T), line:185
|vpiName:JAL_T
|vpiOperand:
\_ref_obj: (JALR_T), line:185
|vpiName:JALR_T
|vpiOperand:
\_ref_obj: (ARITH_T), line:185
|vpiName:ARITH_T
|vpiOperand:
\_ref_obj: (ARITH_IMM_T), line:185
|vpiName:ARITH_IMM_T
|vpiOperand:
\_ref_obj: (AUIPC_T), line:185
|vpiName:AUIPC_T
|vpiOperand:
\_ref_obj: (LUI_T), line:185
|vpiName:LUI_T
|vpiOperand:
\_ref_obj: (LOAD_T), line:185
|vpiName:LOAD_T
|vpiOperand:
\_ref_obj: (STORE_T), line:185
|vpiName:STORE_T
|vpiOperand:
\_ref_obj: (AMO_T), line:185
|vpiName:AMO_T
|vpiOperand:
\_ref_obj: (SYSTEM_T), line:185
|vpiName:SYSTEM_T
|vpiOperand:
\_ref_obj: (FENCE_T), line:185
|vpiName:FENCE_T
|vpiLhs:
\_ref_obj: (valid_opcode), line:185
|vpiName:valid_opcode
|vpiFullName:work@decode.valid_opcode
|vpiContAssign:
\_cont_assign: , line:197
|vpiRhs:
\_operation: , line:197
|vpiOpType:28
|vpiOperand:
\_operation: , line:197
|vpiOpType:28
|vpiOperand:
\_operation: , line:197
|vpiOpType:28
|vpiOperand:
\_ref_obj: (fb_valid), line:197
|vpiName:fb_valid
|vpiFullName:work@decode.fb_valid
|vpiOperand:
\_ref_obj: (ti.id_available), line:197
|vpiName:ti.id_available
|vpiFullName:work@decode.ti.id_available
|vpiOperand:
\_operation: , line:197
|vpiOpType:4
|vpiOperand:
\_ref_obj: (gc_issue_hold), line:197
|vpiName:gc_issue_hold
|vpiFullName:work@decode.gc_issue_hold
|vpiOperand:
\_operation: , line:197
|vpiOpType:4
|vpiOperand:
\_ref_obj: (gc_fetch_flush), line:197
|vpiName:gc_fetch_flush
|vpiFullName:work@decode.gc_fetch_flush
|vpiLhs:
\_ref_obj: (issue_valid), line:197
|vpiName:issue_valid
|vpiFullName:work@decode.issue_valid
|vpiContAssign:
\_cont_assign: , line:199
|vpiRhs:
\_operation: , line:199
|vpiOpType:28
|vpiOperand:
\_operation: , line:199
|vpiOpType:4
|vpiOperand:
\_ref_obj: (rf_decode.rs1_conflict), line:199
|vpiName:rf_decode.rs1_conflict
|vpiFullName:work@decode.rf_decode.rs1_conflict
|vpiOperand:
\_operation: , line:199
|vpiOpType:4
|vpiOperand:
\_ref_obj: (rf_decode.rs2_conflict), line:199
|vpiName:rf_decode.rs2_conflict
|vpiFullName:work@decode.rf_decode.rs2_conflict
|vpiLhs:
\_ref_obj: (operands_ready), line:199
|vpiName:operands_ready
|vpiFullName:work@decode.operands_ready
|vpiContAssign:
\_cont_assign: , line:200
|vpiRhs:
\_operation: , line:200
|vpiOpType:28
|vpiOperand:
\_operation: , line:200
|vpiOpType:4
|vpiOperand:
\_ref_obj: (rf_decode.rs1_conflict), line:200
|vpiName:rf_decode.rs1_conflict
|vpiFullName:work@decode.rf_decode.rs1_conflict
|vpiOperand:
\_operation: , line:200
|vpiOpType:29
|vpiOperand:
\_operation: , line:200
|vpiOpType:4
|vpiOperand:
\_ref_obj: (rf_decode.rs2_conflict), line:200
|vpiName:rf_decode.rs2_conflict
|vpiFullName:work@decode.rf_decode.rs2_conflict
|vpiOperand:
\_operation: , line:200
|vpiOpType:28
|vpiOperand:
\_ref_obj: (rf_decode.rs2_conflict), line:200
|vpiName:rf_decode.rs2_conflict
|vpiFullName:work@decode.rf_decode.rs2_conflict
|vpiOperand:
\_operation: , line:200
|vpiOpType:14
|vpiOperand:
\_ref_obj: (opcode_trim), line:200
|vpiName:opcode_trim
|vpiFullName:work@decode.opcode_trim
|vpiOperand:
\_ref_obj: (STORE_T), line:200
|vpiName:STORE_T
|vpiFullName:work@decode.STORE_T
|vpiLhs:
\_ref_obj: (load_store_operands_ready), line:200
|vpiName:load_store_operands_ready
|vpiFullName:work@decode.load_store_operands_ready
|vpiContAssign:
\_cont_assign: , line:208
|vpiRhs:
\_operation: , line:208
|vpiOpType:28
|vpiOperand:
\_operation: , line:208
|vpiOpType:28
|vpiOperand:
\_operation: , line:208
|vpiOpType:28
|vpiOperand:
\_operation: , line:208
|vpiOpType:34
|vpiOperand:
\_ref_obj: (NUM_UNITS), line:208
|vpiName:NUM_UNITS
|vpiOperand:
\_operation:
|vpiOpType:33
|vpiOperand:
\_ref_obj: (issue_valid), line:208
|vpiName:issue_valid
|vpiOperand:
\_ref_obj: (unit_operands_ready), line:208
|vpiName:unit_operands_ready
|vpiFullName:work@decode.unit_operands_ready
|vpiOperand:
\_ref_obj: (unit_requested), line:208
|vpiName:unit_requested
|vpiFullName:work@decode.unit_requested
|vpiOperand:
\_ref_obj: (unit_ready), line:208
|vpiName:unit_ready
|vpiFullName:work@decode.unit_ready
|vpiLhs:
\_ref_obj: (issue), line:208
|vpiName:issue
|vpiFullName:work@decode.issue
|vpiContAssign:
\_cont_assign: , line:212
|vpiRhs:
\_operation: , line:212
|vpiOpType:28
|vpiOperand:
\_ref_obj: (issue_valid), line:212
|vpiName:issue_valid
|vpiFullName:work@decode.issue_valid
|vpiOperand:
\_ref_obj: (load_store_operands_ready), line:212
|vpiName:load_store_operands_ready
|vpiFullName:work@decode.load_store_operands_ready
|vpiLhs:
\_ref_obj: (instruction_issued), line:212
|vpiName:instruction_issued
|vpiFullName:work@decode.instruction_issued
|vpiContAssign:
\_cont_assign: , line:213
|vpiRhs:
\_operation: , line:213
|vpiOpType:28
|vpiOperand:
\_ref_obj: (instruction_issued), line:213
|vpiName:instruction_issued
|vpiFullName:work@decode.instruction_issued
|vpiOperand:
\_operation: , line:213
|vpiOpType:4
|vpiOperand:
\_ref_obj: (uses_rd), line:213
|vpiName:uses_rd
|vpiFullName:work@decode.uses_rd
|vpiLhs:
\_ref_obj: (instruction_issued_no_rd), line:213
|vpiName:instruction_issued_no_rd
|vpiFullName:work@decode.instruction_issued_no_rd
|vpiContAssign:
\_cont_assign: , line:214
|vpiRhs:
\_operation: , line:214
|vpiOpType:28
|vpiOperand:
\_ref_obj: (instruction_issued), line:214
|vpiName:instruction_issued
|vpiFullName:work@decode.instruction_issued
|vpiOperand:
\_ref_obj: (uses_rd), line:214
|vpiName:uses_rd
|vpiFullName:work@decode.uses_rd
|vpiLhs:
\_ref_obj: (instruction_issued_with_rd), line:214
|vpiName:instruction_issued_with_rd
|vpiFullName:work@decode.instruction_issued_with_rd
|vpiContAssign:
\_cont_assign: , line:217
|vpiRhs:
\_bit_select: (issue), line:217
|vpiName:issue
|vpiFullName:work@decode.issue
|vpiIndex:
\_ref_obj: (LS_UNIT_WB_ID), line:217
|vpiName:LS_UNIT_WB_ID
|vpiLhs:
\_ref_obj: (load_store_issue), line:217
|vpiName:load_store_issue
|vpiFullName:work@decode.load_store_issue
|vpiContAssign:
\_cont_assign: , line:239
|vpiRhs:
\_operation: , line:239
|vpiOpType:33
|vpiOperand:
\_operation: , line:239
|vpiOpType:28
|vpiOperand:
\_bit_select: (alu_rs1_data), line:239
|vpiName:alu_rs1_data
|vpiIndex:
\_operation: , line:239
|vpiOpType:11
|vpiOperand:
\_ref_obj: (XLEN), line:239
|vpiName:XLEN
|vpiOperand:
\_constant: , line:239
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiOperand:
\_operation: , line:239
|vpiOpType:4
|vpiOperand:
\_bit_select: (fn3), line:239
|vpiName:fn3
|vpiIndex:
\_constant: , line:239
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiOperand:
\_ref_obj: (alu_rs1_data), line:239
|vpiName:alu_rs1_data
|vpiLhs:
\_ref_obj: (alu_inputs.in1), line:239
|vpiName:alu_inputs.in1
|vpiFullName:work@decode.alu_inputs.in1
|vpiContAssign:
\_cont_assign: , line:240
|vpiRhs:
\_operation: , line:240
|vpiOpType:33
|vpiOperand:
\_operation: , line:240
|vpiOpType:28
|vpiOperand:
\_bit_select: (alu_rs2_data), line:240
|vpiName:alu_rs2_data
|vpiIndex:
\_operation: , line:240
|vpiOpType:11
|vpiOperand:
\_ref_obj: (XLEN), line:240
|vpiName:XLEN
|vpiOperand:
\_constant: , line:240
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiOperand:
\_operation: , line:240
|vpiOpType:4
|vpiOperand:
\_bit_select: (fn3), line:240
|vpiName:fn3
|vpiIndex:
\_constant: , line:240
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiOperand:
\_ref_obj: (alu_rs2_data), line:240
|vpiName:alu_rs2_data
|vpiLhs:
\_ref_obj: (alu_inputs.in2), line:240
|vpiName:alu_inputs.in2
|vpiFullName:work@decode.alu_inputs.in2
|vpiContAssign:
\_cont_assign: , line:241
|vpiRhs:
\_ref_obj: (rf_decode.rs1_data), line:241
|vpiName:rf_decode.rs1_data
|vpiFullName:work@decode.rf_decode.rs1_data
|vpiLhs:
\_ref_obj: (alu_inputs.shifter_in), line:241
|vpiName:alu_inputs.shifter_in
|vpiFullName:work@decode.alu_inputs.shifter_in
|vpiContAssign:
\_cont_assign: , line:242
|vpiRhs:
\_operation: , line:242
|vpiOpType:32
|vpiOperand:
\_bit_select: (opcode), line:242
|vpiName:opcode
|vpiFullName:work@decode.opcode
|vpiIndex:
\_constant: , line:242
|vpiConstType:7
|vpiDecompile:5
|vpiSize:32
|INT:5
|vpiOperand:
\_ref_obj: (rf_decode.rs2_data), line:242
|vpiName:rf_decode.rs2_data
|vpiFullName:work@decode.rf_decode.rs2_data
|vpiOperand:
\_ref_obj: (rs2_addr), line:242
|vpiName:rs2_addr
|vpiFullName:work@decode.rs2_addr
|vpiLhs:
\_ref_obj: (alu_inputs.shift_amount), line:242
|vpiName:alu_inputs.shift_amount
|vpiFullName:work@decode.alu_inputs.shift_amount
|vpiContAssign:
\_cont_assign: , line:243
|vpiRhs:
\_ref_obj: (fb.alu_sub), line:243
|vpiName:fb.alu_sub
|vpiFullName:work@decode.fb.alu_sub
|vpiLhs:
\_ref_obj: (alu_inputs.subtract), line:243
|vpiName:alu_inputs.subtract
|vpiFullName:work@decode.alu_inputs.subtract
|vpiContAssign:
\_cont_assign: , line:244
|vpiRhs:
\_operation: , line:244
|vpiOpType:28
|vpiOperand:
\_bit_select: (alu_rs1_data), line:244
|vpiName:alu_rs1_data
|vpiFullName:work@decode.alu_rs1_data
|vpiIndex:
\_operation: , line:244
|vpiOpType:11
|vpiOperand:
\_ref_obj: (XLEN), line:244
|vpiName:XLEN
|vpiOperand:
\_constant: , line:244
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiOperand:
\_ref_obj: (fb.instruction), line:244
|vpiName:fb.instruction
|vpiFullName:work@decode.fb.instruction
|vpiLhs:
\_ref_obj: (alu_inputs.arith), line:244
|vpiName:alu_inputs.arith
|vpiFullName:work@decode.alu_inputs.arith
|vpiContAssign:
\_cont_assign: , line:245
|vpiRhs:
\_operation: , line:245
|vpiOpType:4
|vpiOperand:
\_bit_select: (fn3), line:245
|vpiName:fn3
|vpiIndex:
\_constant: , line:245
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiLhs:
\_ref_obj: (alu_inputs.lshift), line:245
|vpiName:alu_inputs.lshift
|vpiFullName:work@decode.alu_inputs.lshift
|vpiContAssign:
\_cont_assign: , line:246
|vpiRhs:
\_ref_obj: (fb.alu_logic_op), line:246
|vpiName:fb.alu_logic_op
|vpiFullName:work@decode.fb.alu_logic_op
|vpiLhs:
\_ref_obj: (alu_inputs.logic_op), line:246
|vpiName:alu_inputs.logic_op
|vpiFullName:work@decode.alu_inputs.logic_op
|vpiContAssign:
\_cont_assign: , line:247
|vpiRhs:
\_ref_obj: (fb.alu_op), line:247
|vpiName:fb.alu_op
|vpiFullName:work@decode.fb.alu_op
|vpiLhs:
\_ref_obj: (alu_inputs.op), line:247
|vpiName:alu_inputs.op
|vpiFullName:work@decode.alu_inputs.op
|vpiContAssign:
\_cont_assign: , line:251
|vpiRhs:
\_operation: , line:251
|vpiOpType:32
|vpiOperand:
\_ref_obj: (USE_AMO), line:251
|vpiName:USE_AMO
|vpiFullName:work@decode.USE_AMO
|vpiOperand:
\_operation: , line:251
|vpiOpType:14
|vpiOperand:
\_ref_obj: (opcode_trim), line:251
|vpiName:opcode_trim
|vpiFullName:work@decode.opcode_trim
|vpiOperand:
\_ref_obj: (AMO_T), line:251
|vpiName:AMO_T
|vpiFullName:work@decode.AMO_T
|vpiOperand:
\_constant: , line:251
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiLhs:
\_ref_obj: (amo_op), line:251
|vpiName:amo_op
|vpiFullName:work@decode.amo_op
|vpiContAssign:
\_cont_assign: , line:252
|vpiRhs:
\_ref_obj: (fb.instruction), line:252
|vpiName:fb.instruction
|vpiFullName:work@decode.fb.instruction
|vpiLhs:
\_ref_obj: (amo_type), line:252
|vpiName:amo_type
|vpiFullName:work@decode.amo_type
|vpiContAssign:
\_cont_assign: , line:253
|vpiRhs:
\_operation: , line:253
|vpiOpType:14
|vpiOperand:
\_ref_obj: (amo_type), line:253
|vpiName:amo_type
|vpiFullName:work@decode.amo_type
|vpiOperand:
\_ref_obj: (AMO_SC), line:253
|vpiName:AMO_SC
|vpiFullName:work@decode.AMO_SC
|vpiLhs:
\_ref_obj: (store_conditional), line:253
|vpiName:store_conditional
|vpiFullName:work@decode.store_conditional
|vpiContAssign:
\_cont_assign: , line:254
|vpiRhs:
\_operation: , line:254
|vpiOpType:14
|vpiOperand:
\_ref_obj: (amo_type), line:254
|vpiName:amo_type
|vpiFullName:work@decode.amo_type
|vpiOperand:
\_ref_obj: (AMO_LR), line:254
|vpiName:AMO_LR
|vpiFullName:work@decode.AMO_LR
|vpiLhs:
\_ref_obj: (load_reserve), line:254
|vpiName:load_reserve
|vpiFullName:work@decode.load_reserve
|vpiContAssign:
\_cont_assign: , line:267
|vpiRhs:
\_operation: , line:267
|vpiOpType:26
|vpiOperand:
\_operation: , line:267
|vpiOpType:95
|vpiOperand:
\_ref_obj: (opcode_trim), line:267
|vpiName:opcode_trim
|vpiFullName:work@decode.opcode_trim
|vpiOperand:
\_ref_obj: (LOAD_T), line:267
|vpiName:LOAD_T
|vpiOperand:
\_ref_obj: (AMO_T), line:267
|vpiName:AMO_T
|vpiOperand:
\_operation: , line:267
|vpiOpType:3
|vpiOperand:
\_operation: , line:267
|vpiOpType:28
|vpiOperand:
\_ref_obj: (amo_op), line:267
|vpiName:amo_op
|vpiFullName:work@decode.amo_op
|vpiOperand:
\_ref_obj: (store_conditional), line:267
|vpiName:store_conditional
|vpiFullName:work@decode.store_conditional
|vpiLhs:
\_ref_obj: (is_load), line:267
|vpiName:is_load
|vpiFullName:work@decode.is_load
|vpiContAssign:
\_cont_assign: , line:268
|vpiRhs:
\_operation: , line:268
|vpiOpType:27
|vpiOperand:
\_operation: , line:268
|vpiOpType:14
|vpiOperand:
\_ref_obj: (opcode_trim), line:268
|vpiName:opcode_trim
|vpiFullName:work@decode.opcode_trim
|vpiOperand:
\_ref_obj: (STORE_T), line:268
|vpiName:STORE_T
|vpiFullName:work@decode.STORE_T
|vpiOperand:
\_operation: , line:268
|vpiOpType:26
|vpiOperand:
\_ref_obj: (amo_op), line:268
|vpiName:amo_op
|vpiFullName:work@decode.amo_op
|vpiOperand:
\_ref_obj: (store_conditional), line:268
|vpiName:store_conditional
|vpiFullName:work@decode.store_conditional
|vpiLhs:
\_ref_obj: (is_store), line:268
|vpiName:is_store
|vpiFullName:work@decode.is_store
|vpiContAssign:
\_cont_assign: , line:269
|vpiRhs:
\_operation: , line:269
|vpiOpType:32
|vpiOperand:
\_bit_select: (opcode), line:269
|vpiName:opcode
|vpiFullName:work@decode.opcode
|vpiIndex:
\_constant: , line:269
|vpiConstType:7
|vpiDecompile:5
|vpiSize:32
|INT:5
|vpiOperand:
\_operation: , line:269
|vpiOpType:33
|vpiOperand:
\_ref_obj: (fb.instruction), line:269
|vpiName:fb.instruction
|vpiFullName:work@decode.fb.instruction
|vpiOperand:
\_ref_obj: (fb.instruction), line:269
|vpiName:fb.instruction
|vpiFullName:work@decode.fb.instruction
|vpiOperand:
\_ref_obj: (fb.instruction), line:269
|vpiName:fb.instruction
|vpiFullName:work@decode.fb.instruction
|vpiLhs:
\_ref_obj: (ls_offset), line:269
|vpiName:ls_offset
|vpiFullName:work@decode.ls_offset
|vpiContAssign:
\_cont_assign: , line:271
|vpiRhs:
\_ref_obj: (rf_decode.rs1_data), line:271
|vpiName:rf_decode.rs1_data
|vpiFullName:work@decode.rf_decode.rs1_data
|vpiLhs:
\_ref_obj: (ls_inputs.rs1), line:271
|vpiName:ls_inputs.rs1
|vpiFullName:work@decode.ls_inputs.rs1
|vpiContAssign:
\_cont_assign: , line:272
|vpiRhs:
\_ref_obj: (ls_offset), line:272
|vpiName:ls_offset
|vpiFullName:work@decode.ls_offset
|vpiLhs:
\_ref_obj: (ls_inputs.offset), line:272
|vpiName:ls_inputs.offset
|vpiFullName:work@decode.ls_inputs.offset
|vpiContAssign:
\_cont_assign: , line:273
|vpiRhs:
\_ref_obj: (fb.pc), line:273
|vpiName:fb.pc
|vpiFullName:work@decode.fb.pc
|vpiLhs:
\_ref_obj: (ls_inputs.pc), line:273
|vpiName:ls_inputs.pc
|vpiFullName:work@decode.ls_inputs.pc
|vpiContAssign:
\_cont_assign: , line:274
|vpiRhs:
\_operation: , line:274
|vpiOpType:32
|vpiOperand:
\_ref_obj: (amo_op), line:274
|vpiName:amo_op
|vpiFullName:work@decode.amo_op
|vpiOperand:
\_ref_obj: (LS_W_fn3), line:274
|vpiName:LS_W_fn3
|vpiFullName:work@decode.LS_W_fn3
|vpiOperand:
\_ref_obj: (fn3), line:274
|vpiName:fn3
|vpiFullName:work@decode.fn3
|vpiLhs:
\_ref_obj: (ls_inputs.fn3), line:274
|vpiName:ls_inputs.fn3
|vpiFullName:work@decode.ls_inputs.fn3
|vpiContAssign:
\_cont_assign: , line:275
|vpiRhs:
\_ref_obj: (is_load), line:275
|vpiName:is_load
|vpiFullName:work@decode.is_load
|vpiLhs:
\_ref_obj: (ls_inputs.load), line:275
|vpiName:ls_inputs.load
|vpiFullName:work@decode.ls_inputs.load
|vpiContAssign:
\_cont_assign: , line:276
|vpiRhs:
\_ref_obj: (is_store), line:276
|vpiName:is_store
|vpiFullName:work@decode.is_store
|vpiLhs:
\_ref_obj: (ls_inputs.store), line:276
|vpiName:ls_inputs.store
|vpiFullName:work@decode.ls_inputs.store
|vpiContAssign:
\_cont_assign: , line:277
|vpiRhs:
\_ref_obj: (rf_decode.rs2_conflict), line:277
|vpiName:rf_decode.rs2_conflict
|vpiFullName:work@decode.rf_decode.rs2_conflict
|vpiLhs:
\_ref_obj: (ls_inputs.load_store_forward), line:277
|vpiName:ls_inputs.load_store_forward
|vpiFullName:work@decode.ls_inputs.load_store_forward
|vpiContAssign:
\_cont_assign: , line:278
|vpiRhs:
\_ref_obj: (rf_decode.rs2_id), line:278
|vpiName:rf_decode.rs2_id
|vpiFullName:work@decode.rf_decode.rs2_id
|vpiLhs:
\_ref_obj: (ls_inputs.store_forward_id), line:278
|vpiName:ls_inputs.store_forward_id
|vpiFullName:work@decode.ls_inputs.store_forward_id
|vpiContAssign:
\_cont_assign: , line:281
|vpiRhs:
\_operation: , line:281
|vpiOpType:28
|vpiOperand:
\_operation: , line:281
|vpiOpType:4
|vpiOperand:
\_ref_obj: (ls_inputs.load_store_forward), line:281
|vpiName:ls_inputs.load_store_forward
|vpiFullName:work@decode.ls_inputs.load_store_forward
|vpiOperand:
\_bit_select: (issue), line:281
|vpiName:issue
|vpiFullName:work@decode.issue
|vpiIndex:
\_ref_obj: (LS_UNIT_WB_ID), line:281
|vpiName:LS_UNIT_WB_ID
|vpiFullName:work@decode.LS_UNIT_WB_ID
|vpiLhs:
\_ref_obj: (store_issued_with_data), line:281
|vpiName:store_issued_with_data
|vpiFullName:work@decode.store_issued_with_data
|vpiContAssign:
\_cont_assign: , line:282
|vpiRhs:
\_ref_obj: (rf_decode.rs2_data), line:282
|vpiName:rf_decode.rs2_data
|vpiFullName:work@decode.rf_decode.rs2_data
|vpiLhs:
\_ref_obj: (store_data), line:282
|vpiName:store_data
|vpiFullName:work@decode.store_data
|vpiContAssign:
\_cont_assign: , line:286
|vpiRhs:
\_ref_obj: (rf_decode.rs1_data), line:286
|vpiName:rf_decode.rs1_data
|vpiFullName:work@decode.rf_decode.rs1_data
|vpiLhs:
\_ref_obj: (branch_inputs.rs1), line:286
|vpiName:branch_inputs.rs1
|vpiFullName:work@decode.branch_inputs.rs1
|vpiContAssign:
\_cont_assign: , line:287
|vpiRhs:
\_ref_obj: (rf_decode.rs2_data), line:287
|vpiName:rf_decode.rs2_data
|vpiFullName:work@decode.rf_decode.rs2_data
|vpiLhs:
\_ref_obj: (branch_inputs.rs2), line:287
|vpiName:branch_inputs.rs2
|vpiFullName:work@decode.branch_inputs.rs2
|vpiContAssign:
\_cont_assign: , line:288
|vpiRhs:
\_ref_obj: (fn3), line:288
|vpiName:fn3
|vpiFullName:work@decode.fn3
|vpiLhs:
\_ref_obj: (branch_inputs.fn3), line:288
|vpiName:branch_inputs.fn3
|vpiFullName:work@decode.branch_inputs.fn3
|vpiContAssign:
\_cont_assign: , line:289
|vpiRhs:
\_ref_obj: (fb.pc), line:289
|vpiName:fb.pc
|vpiFullName:work@decode.fb.pc
|vpiLhs:
\_ref_obj: (branch_inputs.dec_pc), line:289
|vpiName:branch_inputs.dec_pc
|vpiFullName:work@decode.branch_inputs.dec_pc
|vpiContAssign:
\_cont_assign: , line:290
|vpiRhs:
\_ref_obj: (fb_valid), line:290
|vpiName:fb_valid
|vpiFullName:work@decode.fb_valid
|vpiLhs:
\_ref_obj: (branch_inputs.dec_pc_valid), line:290
|vpiName:branch_inputs.dec_pc_valid
|vpiFullName:work@decode.branch_inputs.dec_pc_valid
|vpiContAssign:
\_cont_assign: , line:291
|vpiRhs:
\_operation: , line:291
|vpiOpType:3
|vpiOperand:
\_operation: , line:291
|vpiOpType:95
|vpiOperand:
\_ref_obj: (fn3), line:291
|vpiName:fn3
|vpiFullName:work@decode.fn3
|vpiOperand:
\_ref_obj: (BLTU_fn3), line:291
|vpiName:BLTU_fn3
|vpiFullName:work@decode.BLTU_fn3
|vpiOperand:
\_ref_obj: (BGEU_fn3), line:291
|vpiName:BGEU_fn3
|vpiFullName:work@decode.BGEU_fn3
|vpiLhs:
\_ref_obj: (branch_inputs.use_signed), line:291
|vpiName:branch_inputs.use_signed
|vpiFullName:work@decode.branch_inputs.use_signed
|vpiContAssign:
\_cont_assign: , line:292
|vpiRhs:
\_bit_select: (opcode), line:292
|vpiName:opcode
|vpiFullName:work@decode.opcode
|vpiIndex:
\_constant: , line:292
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiLhs:
\_ref_obj: (branch_inputs.jal), line:292
|vpiName:branch_inputs.jal
|vpiFullName:work@decode.branch_inputs.jal
|vpiContAssign:
\_cont_assign: , line:293
|vpiRhs:
\_operation: , line:293
|vpiOpType:28
|vpiOperand:
\_operation: , line:293
|vpiOpType:4
|vpiOperand:
\_bit_select: (opcode), line:293
|vpiName:opcode
|vpiIndex:
\_constant: , line:293
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiOperand:
\_bit_select: (opcode), line:293
|vpiName:opcode
|vpiFullName:work@decode.opcode
|vpiIndex:
\_constant: , line:293
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiLhs:
\_ref_obj: (branch_inputs.jalr), line:293
|vpiName:branch_inputs.jalr
|vpiFullName:work@decode.branch_inputs.jalr
|vpiContAssign:
\_cont_assign: , line:294
|vpiRhs:
\_ref_obj: (fb.is_call), line:294
|vpiName:fb.is_call
|vpiFullName:work@decode.fb.is_call
|vpiLhs:
\_ref_obj: (branch_inputs.is_call), line:294
|vpiName:branch_inputs.is_call
|vpiFullName:work@decode.branch_inputs.is_call
|vpiContAssign:
\_cont_assign: , line:295
|vpiRhs:
\_ref_obj: (fb.is_return), line:295
|vpiName:fb.is_return
|vpiFullName:work@decode.fb.is_return
|vpiLhs:
\_ref_obj: (branch_inputs.is_return), line:295
|vpiName:branch_inputs.is_return
|vpiFullName:work@decode.branch_inputs.is_return
|vpiContAssign:
\_cont_assign: , line:296
|vpiRhs:
\_ref_obj: (fb.instruction), line:296
|vpiName:fb.instruction
|vpiFullName:work@decode.fb.instruction
|vpiLhs:
\_ref_obj: (branch_inputs.instruction), line:296
|vpiName:branch_inputs.instruction
|vpiFullName:work@decode.branch_inputs.instruction
|vpiContAssign:
\_cont_assign: , line:297
|vpiRhs:
\_ref_obj: (fb.branch_metadata), line:297
|vpiName:fb.branch_metadata
|vpiFullName:work@decode.fb.branch_metadata
|vpiLhs:
\_ref_obj: (branch_inputs.branch_metadata), line:297
|vpiName:branch_inputs.branch_metadata
|vpiFullName:work@decode.branch_inputs.branch_metadata
|vpiContAssign:
\_cont_assign: , line:298
|vpiRhs:
\_ref_obj: (fb.branch_prediction_used), line:298
|vpiName:fb.branch_prediction_used
|vpiFullName:work@decode.fb.branch_prediction_used
|vpiLhs:
\_ref_obj: (branch_inputs.branch_prediction_used), line:298
|vpiName:branch_inputs.branch_prediction_used
|vpiFullName:work@decode.branch_inputs.branch_prediction_used
|vpiContAssign:
\_cont_assign: , line:299
|vpiRhs:
\_ref_obj: (fb.bp_update_way), line:299
|vpiName:fb.bp_update_way
|vpiFullName:work@decode.fb.bp_update_way
|vpiLhs:
\_ref_obj: (branch_inputs.bp_update_way), line:299
|vpiName:branch_inputs.bp_update_way
|vpiFullName:work@decode.branch_inputs.bp_update_way
|vpiContAssign:
\_cont_assign: , line:307
|vpiRhs:
\_ref_obj: (fb.instruction), line:307
|vpiName:fb.instruction
|vpiFullName:work@decode.fb.instruction
|vpiLhs:
\_ref_obj: (sfence), line:307
|vpiName:sfence
|vpiFullName:work@decode.sfence
|vpiContAssign:
\_cont_assign: , line:308
|vpiRhs:
\_operation: , line:308
|vpiOpType:26
|vpiOperand:
\_operation: , line:308
|vpiOpType:14
|vpiOperand:
\_ref_obj: (opcode_trim), line:308
|vpiName:opcode_trim
|vpiFullName:work@decode.opcode_trim
|vpiOperand:
\_ref_obj: (FENCE_T), line:308
|vpiName:FENCE_T
|vpiFullName:work@decode.FENCE_T
|vpiOperand:
\_bit_select: (fn3), line:308
|vpiName:fn3
|vpiFullName:work@decode.fn3
|vpiIndex:
\_constant: , line:308
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiLhs:
\_ref_obj: (ifence), line:308
|vpiName:ifence
|vpiFullName:work@decode.ifence
|vpiContAssign:
\_cont_assign: , line:309
|vpiRhs:
\_operation: , line:309
|vpiOpType:26
|vpiOperand:
\_operation: , line:309
|vpiOpType:14
|vpiOperand:
\_ref_obj: (opcode_trim), line:309
|vpiName:opcode_trim
|vpiFullName:work@decode.opcode_trim
|vpiOperand:
\_ref_obj: (SYSTEM_T), line:309
|vpiName:SYSTEM_T
|vpiFullName:work@decode.SYSTEM_T
|vpiOperand:
\_operation: , line:309
|vpiOpType:14
|vpiOperand:
\_ref_obj: (fn3), line:309
|vpiName:fn3
|vpiFullName:work@decode.fn3
|vpiOperand:
\_constant: , line:309
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiLhs:
\_ref_obj: (environment_op), line:309
|vpiName:environment_op
|vpiFullName:work@decode.environment_op
|vpiContAssign:
\_cont_assign: , line:310
|vpiRhs:
\_operation: , line:310
|vpiOpType:26
|vpiOperand:
\_operation: , line:310
|vpiOpType:14
|vpiOperand:
\_ref_obj: (opcode_trim), line:310
|vpiName:opcode_trim
|vpiFullName:work@decode.opcode_trim
|vpiOperand:
\_ref_obj: (SYSTEM_T), line:310
|vpiName:SYSTEM_T
|vpiFullName:work@decode.SYSTEM_T
|vpiOperand:
\_operation: , line:310
|vpiOpType:15
|vpiOperand:
\_ref_obj: (fn3), line:310
|vpiName:fn3
|vpiFullName:work@decode.fn3
|vpiOperand:
\_constant: , line:310
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiLhs:
\_ref_obj: (is_csr), line:310
|vpiName:is_csr
|vpiFullName:work@decode.is_csr
|vpiContAssign:
\_cont_assign: , line:327
|vpiRhs:
\_operation: , line:327
|vpiOpType:26
|vpiOperand:
\_bit_select: (issue), line:327
|vpiName:issue
|vpiFullName:work@decode.issue
|vpiIndex:
\_ref_obj: (GC_UNIT_ID), line:327
|vpiName:GC_UNIT_ID
|vpiOperand:
\_operation: , line:327
|vpiOpType:29
|vpiOperand:
\_ref_obj: (environment_op), line:327
|vpiName:environment_op
|vpiFullName:work@decode.environment_op
|vpiOperand:
\_ref_obj: (ifence), line:327
|vpiName:ifence
|vpiFullName:work@decode.ifence
|vpiLhs:
\_ref_obj: (gc_flush_required), line:327
|vpiName:gc_flush_required
|vpiFullName:work@decode.gc_flush_required
|vpiNet:
\_logic_net: (clk), line:27
|vpiNet:
\_logic_net: (rst), line:28
|vpiNet:
\_logic_net: (pre_decode_pop), line:30
|vpiNet:
\_logic_net: (fb_valid), line:31
|vpiNet:
\_logic_net: (fb), line:32
|vpiNet:
\_logic_net: (alu_inputs), line:37
|vpiNet:
\_logic_net: (ls_inputs), line:38
|vpiNet:
\_logic_net: (branch_inputs), line:39
|vpiNet:
\_logic_net: (gc_inputs), line:40
|vpiNet:
\_logic_net: (mul_inputs), line:41
|vpiNet:
\_logic_net: (div_inputs), line:42
|vpiNet:
\_logic_net: (gc_issue_hold), line:46
|vpiNet:
\_logic_net: (gc_fetch_flush), line:47
|vpiNet:
\_logic_net: (gc_issue_flush), line:48
|vpiNet:
\_logic_net: (gc_flush_required), line:49
|vpiNet:
\_logic_net: (load_store_issue), line:51
|vpiNet:
\_logic_net: (store_issued_with_data), line:52
|vpiNet:
\_logic_net: (store_data), line:53
|vpiNet:
\_logic_net: (instruction_issued), line:55
|vpiNet:
\_logic_net: (instruction_issued_no_rd), line:56
|vpiNet:
\_logic_net: (instruction_issued_with_rd), line:57
|vpiNet:
\_logic_net: (illegal_instruction), line:58
|vpiNet:
\_logic_net: (tr_operand_stall), line:61
|vpiNet:
\_logic_net: (tr_unit_stall), line:62
|vpiNet:
\_logic_net: (tr_no_id_stall), line:63
|vpiNet:
\_logic_net: (tr_no_instruction_stall), line:64
|vpiNet:
\_logic_net: (tr_other_stall), line:65
|vpiNet:
\_logic_net: (tr_branch_operand_stall), line:66
|vpiNet:
\_logic_net: (tr_alu_operand_stall), line:67
|vpiNet:
\_logic_net: (tr_ls_operand_stall), line:68
|vpiNet:
\_logic_net: (tr_div_operand_stall), line:69
|vpiNet:
\_logic_net: (tr_instruction_issued_dec), line:71
|vpiNet:
\_logic_net: (tr_instruction_pc_dec), line:72
|vpiNet:
\_logic_net: (tr_instruction_data_dec), line:73
|vpiNet:
\_logic_net: (fn3), line:76
|vpiName:fn3
|vpiFullName:work@decode.fn3
|vpiNetType:36
|vpiNet:
\_logic_net: (opcode), line:77
|vpiName:opcode
|vpiFullName:work@decode.opcode
|vpiNetType:36
|vpiNet:
\_logic_net: (opcode_trim), line:78
|vpiName:opcode_trim
|vpiFullName:work@decode.opcode_trim
|vpiNetType:36
|vpiNet:
\_logic_net: (uses_rs1), line:80
|vpiName:uses_rs1
|vpiFullName:work@decode.uses_rs1
|vpiNetType:36
|vpiNet:
\_logic_net: (uses_rs2), line:81
|vpiName:uses_rs2
|vpiFullName:work@decode.uses_rs2
|vpiNetType:36
|vpiNet:
\_logic_net: (uses_rd), line:82
|vpiName:uses_rd
|vpiFullName:work@decode.uses_rd
|vpiNetType:36
|vpiNet:
\_logic_net: (rd_zero), line:83
|vpiName:rd_zero
|vpiFullName:work@decode.rd_zero
|vpiNetType:36
|vpiNet:
\_logic_net: (rs1_addr), line:85
|vpiName:rs1_addr
|vpiFullName:work@decode.rs1_addr
|vpiNetType:36
|vpiNet:
\_logic_net: (rs2_addr), line:86
|vpiName:rs2_addr
|vpiFullName:work@decode.rs2_addr
|vpiNetType:36
|vpiNet:
\_logic_net: (future_rd_addr), line:87
|vpiName:future_rd_addr
|vpiFullName:work@decode.future_rd_addr
|vpiNetType:36
|vpiNet:
\_logic_net: (nop), line:89
|vpiName:nop
|vpiFullName:work@decode.nop
|vpiNetType:36
|vpiNet:
\_logic_net: (register_in_use_by_load_op), line:91
|vpiName:register_in_use_by_load_op
|vpiFullName:work@decode.register_in_use_by_load_op
|vpiNetType:36
|vpiNet:
\_logic_net: (store_data_in_use_by_load_op), line:93
|vpiName:store_data_in_use_by_load_op
|vpiFullName:work@decode.store_data_in_use_by_load_op
|vpiNetType:36
|vpiNet:
\_logic_net: (load_store_forward_possible), line:94
|vpiName:load_store_forward_possible
|vpiFullName:work@decode.load_store_forward_possible
|vpiNetType:36
|vpiNet:
\_logic_net: (issue_valid), line:96
|vpiName:issue_valid
|vpiFullName:work@decode.issue_valid
|vpiNetType:36
|vpiNet:
\_logic_net: (load_store_operands_ready), line:97
|vpiName:load_store_operands_ready
|vpiFullName:work@decode.load_store_operands_ready
|vpiNetType:36
|vpiNet:
\_logic_net: (operands_ready), line:98
|vpiName:operands_ready
|vpiFullName:work@decode.operands_ready
|vpiNetType:36
|vpiNet:
\_logic_net: (unit_operands_ready), line:99
|vpiName:unit_operands_ready
|vpiFullName:work@decode.unit_operands_ready
|vpiNetType:36
|vpiNet:
\_logic_net: (mult_div_op), line:100
|vpiName:mult_div_op
|vpiFullName:work@decode.mult_div_op
|vpiNetType:36
|vpiNet:
\_logic_net: (unit_requested_for_id_gen), line:102
|vpiName:unit_requested_for_id_gen
|vpiFullName:work@decode.unit_requested_for_id_gen
|vpiNetType:36
|vpiNet:
\_logic_net: (unit_requested_for_id_gen_int), line:103
|vpiName:unit_requested_for_id_gen_int
|vpiFullName:work@decode.unit_requested_for_id_gen_int
|vpiNetType:36
|vpiNet:
\_logic_net: (unit_requested), line:104
|vpiName:unit_requested
|vpiFullName:work@decode.unit_requested
|vpiNetType:36
|vpiNet:
\_logic_net: (unit_ready), line:105
|vpiName:unit_ready
|vpiFullName:work@decode.unit_ready
|vpiNetType:36
|vpiNet:
\_logic_net: (issue), line:106
|vpiName:issue
|vpiFullName:work@decode.issue
|vpiNetType:36
|vpiNet:
\_logic_net: (valid_opcode), line:108
|vpiName:valid_opcode
|vpiFullName:work@decode.valid_opcode
|vpiNetType:36
|vpiNet:
\_logic_net: (ls_offset), line:111
|vpiName:ls_offset
|vpiFullName:work@decode.ls_offset
|vpiNetType:36
|vpiNet:
\_logic_net: (is_load), line:112
|vpiName:is_load
|vpiFullName:work@decode.is_load
|vpiNetType:36
|vpiNet:
\_logic_net: (is_store), line:113
|vpiName:is_store
|vpiFullName:work@decode.is_store
|vpiNetType:36
|vpiNet:
\_logic_net: (amo_op), line:114
|vpiName:amo_op
|vpiFullName:work@decode.amo_op
|vpiNetType:36
|vpiNet:
\_logic_net: (store_conditional), line:115
|vpiName:store_conditional
|vpiFullName:work@decode.store_conditional
|vpiNetType:36
|vpiNet:
\_logic_net: (load_reserve), line:116
|vpiName:load_reserve
|vpiFullName:work@decode.load_reserve
|vpiNetType:36
|vpiNet:
\_logic_net: (amo_type), line:117
|vpiName:amo_type
|vpiFullName:work@decode.amo_type
|vpiNetType:36
|vpiNet:
\_logic_net: (alu_rs1_data), line:221
|vpiName:alu_rs1_data
|vpiFullName:work@decode.alu_rs1_data
|vpiNetType:36
|vpiNet:
\_logic_net: (alu_rs2_data), line:222
|vpiName:alu_rs2_data
|vpiFullName:work@decode.alu_rs2_data
|vpiNetType:36
|vpiNet:
\_logic_net: (sfence), line:303
|vpiName:sfence
|vpiFullName:work@decode.sfence
|vpiNetType:36
|vpiNet:
\_logic_net: (ifence), line:304
|vpiName:ifence
|vpiFullName:work@decode.ifence
|vpiNetType:36
|vpiNet:
\_logic_net: (environment_op), line:305
|vpiName:environment_op
|vpiFullName:work@decode.environment_op
|vpiNetType:36
|vpiNet:
\_logic_net: (is_csr), line:306
|vpiName:is_csr
|vpiFullName:work@decode.is_csr
|vpiNetType:36
|vpiNet:
\_logic_net: (ti), line:34
|vpiName:ti
|vpiFullName:work@decode.ti
|vpiNet:
\_logic_net: (rf_decode), line:35
|vpiName:rf_decode
|vpiFullName:work@decode.rf_decode
|vpiNet:
\_logic_net: (unit_issue), line:44
|vpiName:unit_issue
|vpiFullName:work@decode.unit_issue
|vpiTypedef:
\_struct_typespec: (alu_inputs_t), line:301
|vpiTypedef:
\_enum_typespec: (alu_logic_op_t), line:84
|vpiTypedef:
\_enum_typespec: (alu_op_t), line:91
|vpiTypedef:
\_enum_typespec: (alu_rs1_op_t), line:97
|vpiTypedef:
\_enum_typespec: (alu_rs2_op_t), line:104
|vpiTypedef:
\_struct_typespec: (amo_alu_inputs_t), line:356
|vpiTypedef:
\_struct_typespec: (amo_details_t), line:362
|vpiTypedef:
\_enum_typespec: (amo_t), line:354
|vpiTypedef:
\_struct_typespec: (branch_inputs_t), line:313
|vpiTypedef:
\_logic_typespec: (branch_predictor_metadata_t), line:32
|vpiTypedef:
\_struct_typespec: (branch_results_t), line:330
|vpiTypedef:
\_enum_typespec: (bus_type_t), line:86
|vpiTypedef:
\_struct_typespec: (csr_inputs_t), line:396
|vpiTypedef:
\_enum_typespec: (csr_op_t), line:218
|vpiTypedef:
\_enum_typespec: (csr_t), line:201
|vpiTypedef:
\_struct_typespec: (data_access_shared_inputs_t), line:427
|vpiTypedef:
\_struct_typespec: (div_inputs_t), line:389
|vpiTypedef:
\_enum_typespec: (div_type), line:66
|vpiTypedef:
\_enum_typespec: (exception_code_t), line:245
|vpiTypedef:
\_struct_typespec: (exception_packet_t), line:263
|vpiTypedef:
\_struct_typespec: (fetch_buffer_packet_t), line:276
|vpiTypedef:
\_enum_typespec: (fifo_type_t), line:440
|vpiTypedef:
\_enum_typespec: (fn3_arith_t), line:76
|vpiTypedef:
\_enum_typespec: (fn3_branch_t), line:126
|vpiTypedef:
\_enum_typespec: (fn3_csr_t), line:212
|vpiTypedef:
\_enum_typespec: (fn3_ls_t), line:115
|vpiTypedef:
\_enum_typespec: (fn3_mul_div_t), line:138
|vpiTypedef:
\_struct_typespec: (gc_inputs_t), line:404
|vpiTypedef:
\_struct_typespec: (inflight_instruction_packet), line:271
|vpiTypedef:
\_logic_typespec: (instruction_id_t), line:30
|vpiTypedef:
\_enum_typespec: (interrupt_code_t), line:261
|vpiTypedef:
\_struct_typespec: (load_store_inputs_t), line:369
|vpiTypedef:
\_struct_typespec: (mul_inputs_t), line:383
|vpiTypedef:
\_enum_typespec: (opcodes_t), line:48
|vpiTypedef:
\_enum_typespec: (opcodes_trimmed_t), line:65
|vpiTypedef:
\_struct_typespec: (simulation_named_regfile), line:476
|vpiTypedef:
\_struct_typespec: (taiga_trace_events_t), line:442
|vpiTypedef:
\_struct_typespec: (to_l1_arbiter_packet), line:418
|vpiTypedef:
\_struct_typespec: (trace_outputs_t), line:469
|vpiTypedef:
\_logic_typespec: (unit_id_t), line:31
|vpiTypedef:
\_struct_typespec: (unit_writeback_t), line:295
|vpiTypedef:
\_enum_typespec: (vm_t), line:223
|uhdmallModules:
\_module: work@div_algorithm, file:third_party/cores/taiga/core/div_algorithms/div_algorithm.sv, line:27, parent:work@div_unit_core_wrapper
|vpiDefName:work@div_algorithm
|vpiFullName:work@div_algorithm
|vpiPort:
\_port: (clk), line:29
|vpiName:clk
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (clk), line:29
|vpiName:clk
|vpiFullName:work@div_algorithm.clk
|vpiNetType:36
|vpiPort:
\_port: (rst), line:30
|vpiName:rst
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (rst), line:30
|vpiName:rst
|vpiFullName:work@div_algorithm.rst
|vpiNetType:36
|vpiPort:
\_port: (div), line:31
|vpiName:div
|vpiDirection:5
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_modport: (divider)
|vpiNet:
\_logic_net: (clk), line:29
|vpiNet:
\_logic_net: (rst), line:30
|vpiNet:
\_logic_net: (div), line:31
|vpiName:div
|vpiFullName:work@div_algorithm.div
|vpiTypedef:
\_struct_typespec: (alu_inputs_t), line:301
|vpiTypedef:
\_enum_typespec: (alu_logic_op_t), line:84
|vpiTypedef:
\_enum_typespec: (alu_op_t), line:91
|vpiTypedef:
\_enum_typespec: (alu_rs1_op_t), line:97
|vpiTypedef:
\_enum_typespec: (alu_rs2_op_t), line:104
|vpiTypedef:
\_struct_typespec: (amo_alu_inputs_t), line:356
|vpiTypedef:
\_struct_typespec: (amo_details_t), line:362
|vpiTypedef:
\_enum_typespec: (amo_t), line:354
|vpiTypedef:
\_struct_typespec: (branch_inputs_t), line:313
|vpiTypedef:
\_logic_typespec: (branch_predictor_metadata_t), line:32
|vpiTypedef:
\_struct_typespec: (branch_results_t), line:330
|vpiTypedef:
\_enum_typespec: (bus_type_t), line:86
|vpiTypedef:
\_struct_typespec: (csr_inputs_t), line:396
|vpiTypedef:
\_enum_typespec: (csr_op_t), line:218
|vpiTypedef:
\_enum_typespec: (csr_t), line:201
|vpiTypedef:
\_struct_typespec: (data_access_shared_inputs_t), line:427
|vpiTypedef:
\_struct_typespec: (div_inputs_t), line:389
|vpiTypedef:
\_enum_typespec: (div_type), line:66
|vpiTypedef:
\_enum_typespec: (exception_code_t), line:245
|vpiTypedef:
\_struct_typespec: (exception_packet_t), line:263
|vpiTypedef:
\_struct_typespec: (fetch_buffer_packet_t), line:276
|vpiTypedef:
\_enum_typespec: (fifo_type_t), line:440
|vpiTypedef:
\_enum_typespec: (fn3_arith_t), line:76
|vpiTypedef:
\_enum_typespec: (fn3_branch_t), line:126
|vpiTypedef:
\_enum_typespec: (fn3_csr_t), line:212
|vpiTypedef:
\_enum_typespec: (fn3_ls_t), line:115
|vpiTypedef:
\_enum_typespec: (fn3_mul_div_t), line:138
|vpiTypedef:
\_struct_typespec: (gc_inputs_t), line:404
|vpiTypedef:
\_struct_typespec: (inflight_instruction_packet), line:271
|vpiTypedef:
\_logic_typespec: (instruction_id_t), line:30
|vpiTypedef:
\_enum_typespec: (interrupt_code_t), line:261
|vpiTypedef:
\_struct_typespec: (load_store_inputs_t), line:369
|vpiTypedef:
\_struct_typespec: (mul_inputs_t), line:383
|vpiTypedef:
\_enum_typespec: (opcodes_t), line:48
|vpiTypedef:
\_enum_typespec: (opcodes_trimmed_t), line:65
|vpiTypedef:
\_struct_typespec: (simulation_named_regfile), line:476
|vpiTypedef:
\_struct_typespec: (taiga_trace_events_t), line:442
|vpiTypedef:
\_struct_typespec: (to_l1_arbiter_packet), line:418
|vpiTypedef:
\_struct_typespec: (trace_outputs_t), line:469
|vpiTypedef:
\_logic_typespec: (unit_id_t), line:31
|vpiTypedef:
\_struct_typespec: (unit_writeback_t), line:295
|vpiTypedef:
\_enum_typespec: (vm_t), line:223
|uhdmallModules:
\_module: work@div_quick_clz, file:third_party/cores/taiga/core/div_algorithms/div_quick_clz.sv, line:25, parent:work@div_unit_core_wrapper
|vpiDefName:work@div_quick_clz
|vpiFullName:work@div_quick_clz
|vpiProcess:
\_always: , line:64
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:64
|vpiCondition:
\_operation: , line:64
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:64
|vpiName:clk
|vpiFullName:work@div_quick_clz.clk
|vpiStmt:
\_begin: , line:64
|vpiFullName:work@div_quick_clz
|vpiStmt:
\_if_else: , line:65
|vpiCondition:
\_ref_obj: (rst), line:65
|vpiName:rst
|vpiFullName:work@div_quick_clz.rst
|vpiStmt:
\_assignment: , line:66
|vpiOpType:82
|vpiLhs:
\_ref_obj: (running), line:66
|vpiName:running
|vpiFullName:work@div_quick_clz.running
|vpiRhs:
\_constant: , line:66
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiElseStmt:
\_if_else: , line:67
|vpiCondition:
\_operation: , line:67
|vpiOpType:28
|vpiOperand:
\_ref_obj: (div.start), line:67
|vpiName:div.start
|vpiFullName:work@div_quick_clz.div.start
|vpiOperand:
\_operation: , line:67
|vpiOpType:4
|vpiOperand:
\_ref_obj: (div.divisor_is_zero), line:67
|vpiName:div.divisor_is_zero
|vpiFullName:work@div_quick_clz.div.divisor_is_zero
|vpiStmt:
\_assignment: , line:68
|vpiOpType:82
|vpiLhs:
\_ref_obj: (running), line:68
|vpiName:running
|vpiFullName:work@div_quick_clz.running
|vpiRhs:
\_constant: , line:68
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiElseStmt:
\_if_stmt: , line:69
|vpiCondition:
\_ref_obj: (terminate), line:69
|vpiName:terminate
|vpiFullName:work@div_quick_clz.terminate
|vpiStmt:
\_assignment: , line:70
|vpiOpType:82
|vpiLhs:
\_ref_obj: (running), line:70
|vpiName:running
|vpiFullName:work@div_quick_clz.running
|vpiRhs:
\_constant: , line:70
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiProcess:
\_always: , line:73
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:73
|vpiCondition:
\_operation: , line:73
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:73
|vpiName:clk
|vpiFullName:work@div_quick_clz.clk
|vpiStmt:
\_begin: , line:73
|vpiFullName:work@div_quick_clz
|vpiStmt:
\_assignment: , line:74
|vpiOpType:82
|vpiLhs:
\_ref_obj: (div.done), line:74
|vpiName:div.done
|vpiFullName:work@div_quick_clz.div.done
|vpiRhs:
\_operation: , line:74
|vpiOpType:29
|vpiOperand:
\_operation: , line:74
|vpiOpType:28
|vpiOperand:
\_ref_obj: (running), line:74
|vpiName:running
|vpiFullName:work@div_quick_clz.running
|vpiOperand:
\_ref_obj: (terminate), line:74
|vpiName:terminate
|vpiFullName:work@div_quick_clz.terminate
|vpiOperand:
\_operation: , line:74
|vpiOpType:28
|vpiOperand:
\_ref_obj: (div.start), line:74
|vpiName:div.start
|vpiFullName:work@div_quick_clz.div.start
|vpiOperand:
\_ref_obj: (div.divisor_is_zero), line:74
|vpiName:div.divisor_is_zero
|vpiFullName:work@div_quick_clz.div.divisor_is_zero
|vpiProcess:
\_always: , line:81
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:81
|vpiCondition:
\_operation: , line:81
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:81
|vpiName:clk
|vpiFullName:work@div_quick_clz.clk
|vpiStmt:
\_begin: , line:81
|vpiFullName:work@div_quick_clz
|vpiStmt:
\_assignment: , line:82
|vpiOpType:82
|vpiLhs:
\_ref_obj: (divisor_CLZ_r), line:82
|vpiName:divisor_CLZ_r
|vpiFullName:work@div_quick_clz.divisor_CLZ_r
|vpiRhs:
\_ref_obj: (divisor_CLZ), line:82
|vpiName:divisor_CLZ
|vpiFullName:work@div_quick_clz.divisor_CLZ
|vpiStmt:
\_assignment: , line:83
|vpiOpType:82
|vpiLhs:
\_ref_obj: (normalized_divisor), line:83
|vpiName:normalized_divisor
|vpiFullName:work@div_quick_clz.normalized_divisor
|vpiRhs:
\_operation: , line:83
|vpiOpType:22
|vpiOperand:
\_ref_obj: (div.divisor), line:83
|vpiName:div.divisor
|vpiFullName:work@div_quick_clz.div.divisor
|vpiOperand:
\_ref_obj: (divisor_CLZ), line:83
|vpiName:divisor_CLZ
|vpiFullName:work@div_quick_clz.divisor_CLZ
|vpiProcess:
\_initial:
|vpiStmt:
\_begin: , line:96
|vpiFullName:work@div_quick_clz
|vpiStmt:
\_assignment: , line:97
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (div.remainder), line:97
|vpiName:div.remainder
|vpiFullName:work@div_quick_clz.div.remainder
|vpiRhs:
\_constant: , line:97
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiProcess:
\_always: , line:99
|vpiAlwaysType:1
|vpiStmt:
\_event_control: , line:99
|vpiCondition:
\_operation: , line:99
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:99
|vpiName:clk
|vpiFullName:work@div_quick_clz.clk
|vpiStmt:
\_begin: , line:99
|vpiFullName:work@div_quick_clz
|vpiStmt:
\_if_else: , line:100
|vpiCondition:
\_ref_obj: (div.start), line:100
|vpiName:div.start
|vpiFullName:work@div_quick_clz.div.start
|vpiStmt:
\_assignment: , line:101
|vpiOpType:82
|vpiLhs:
\_ref_obj: (div.remainder), line:101
|vpiName:div.remainder
|vpiFullName:work@div_quick_clz.div.remainder
|vpiRhs:
\_ref_obj: (div.dividend), line:101
|vpiName:div.dividend
|vpiFullName:work@div_quick_clz.div.dividend
|vpiElseStmt:
\_if_stmt: , line:102
|vpiCondition:
\_operation: , line:102
|vpiOpType:28
|vpiOperand:
\_operation: , line:102
|vpiOpType:4
|vpiOperand:
\_ref_obj: (terminate), line:102
|vpiName:terminate
|vpiFullName:work@div_quick_clz.terminate
|vpiOperand:
\_ref_obj: (running), line:102
|vpiName:running
|vpiFullName:work@div_quick_clz.running
|vpiStmt:
\_assignment: , line:103
|vpiOpType:82
|vpiLhs:
\_ref_obj: (div.remainder), line:103
|vpiName:div.remainder
|vpiFullName:work@div_quick_clz.div.remainder
|vpiRhs:
\_ref_obj: (new_remainder), line:103
|vpiName:new_remainder
|vpiFullName:work@div_quick_clz.new_remainder
|vpiProcess:
\_always: , line:109
|vpiAlwaysType:2
|vpiStmt:
\_begin: , line:109
|vpiFullName:work@div_quick_clz
|vpiStmt:
\_assignment: , line:110
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (new_Q_bit1), line:110
|vpiName:new_Q_bit1
|vpiFullName:work@div_quick_clz.new_Q_bit1
|vpiRhs:
\_constant: , line:110
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiStmt:
\_assignment: , line:111
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_bit_select: (new_Q_bit1), line:111
|vpiName:new_Q_bit1
|vpiFullName:work@div_quick_clz.new_Q_bit1
|vpiIndex:
\_ref_obj: (CLZ_delta), line:111
|vpiName:CLZ_delta
|vpiRhs:
\_constant: , line:111
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiProcess:
\_always: , line:116
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:116
|vpiCondition:
\_operation: , line:116
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:116
|vpiName:clk
|vpiFullName:work@div_quick_clz.clk
|vpiStmt:
\_begin: , line:116
|vpiFullName:work@div_quick_clz
|vpiStmt:
\_if_else: , line:117
|vpiCondition:
\_ref_obj: (div.start), line:117
|vpiName:div.start
|vpiFullName:work@div_quick_clz.div.start
|vpiStmt:
\_assignment: , line:118
|vpiOpType:82
|vpiLhs:
\_ref_obj: (div.quotient), line:118
|vpiName:div.quotient
|vpiFullName:work@div_quick_clz.div.quotient
|vpiRhs:
\_operation: , line:118
|vpiOpType:32
|vpiOperand:
\_ref_obj: (div.divisor_is_zero), line:118
|vpiName:div.divisor_is_zero
|vpiFullName:work@div_quick_clz.div.divisor_is_zero
|vpiOperand:
\_constant: , line:118
|vpiConstType:3
|vpiDecompile:'b1
|vpiSize:1
|BIN:1
|vpiOperand:
\_constant: , line:118
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiElseStmt:
\_if_stmt: , line:119
|vpiCondition:
\_operation: , line:119
|vpiOpType:28
|vpiOperand:
\_operation: , line:119
|vpiOpType:4
|vpiOperand:
\_ref_obj: (terminate), line:119
|vpiName:terminate
|vpiFullName:work@div_quick_clz.terminate
|vpiOperand:
\_ref_obj: (running), line:119
|vpiName:running
|vpiFullName:work@div_quick_clz.running
|vpiStmt:
\_assignment: , line:120
|vpiOpType:82
|vpiLhs:
\_ref_obj: (div.quotient), line:120
|vpiName:div.quotient
|vpiFullName:work@div_quick_clz.div.quotient
|vpiRhs:
\_ref_obj: (new_quotient), line:120
|vpiName:new_quotient
|vpiFullName:work@div_quick_clz.new_quotient
|vpiPort:
\_port: (clk), line:27
|vpiName:clk
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (clk), line:27
|vpiName:clk
|vpiFullName:work@div_quick_clz.clk
|vpiNetType:36
|vpiPort:
\_port: (rst), line:28
|vpiName:rst
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (rst), line:28
|vpiName:rst
|vpiFullName:work@div_quick_clz.rst
|vpiNetType:36
|vpiPort:
\_port: (div), line:29
|vpiName:div
|vpiDirection:5
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_modport: (divider)
|vpiContAssign:
\_cont_assign: , line:62
|vpiRhs:
\_operation: , line:62
|vpiOpType:28
|vpiOperand:
\_operation: , line:62
|vpiOpType:5
|vpiOperand:
\_ref_obj: (divisor_CLZ), line:62
|vpiName:divisor_CLZ
|vpiFullName:work@div_quick_clz.divisor_CLZ
|vpiOperand:
\_operation: , line:62
|vpiOpType:4
|vpiOperand:
\_ref_obj: (div.divisor), line:62
|vpiName:div.divisor
|vpiFullName:work@div_quick_clz.div.divisor
|vpiLhs:
\_ref_obj: (div.divisor_is_zero), line:62
|vpiName:div.divisor_is_zero
|vpiFullName:work@div_quick_clz.div.divisor_is_zero
|vpiContAssign:
\_cont_assign: , line:77
|vpiRhs:
\_operation: , line:77
|vpiOpType:20
|vpiOperand:
\_ref_obj: (div.remainder), line:77
|vpiName:div.remainder
|vpiFullName:work@div_quick_clz.div.remainder
|vpiOperand:
\_ref_obj: (div.divisor), line:77
|vpiName:div.divisor
|vpiFullName:work@div_quick_clz.div.divisor
|vpiLhs:
\_ref_obj: (terminate), line:77
|vpiName:terminate
|vpiFullName:work@div_quick_clz.terminate
|vpiContAssign:
\_cont_assign: , line:88
|vpiRhs:
\_operation: , line:88
|vpiOpType:23
|vpiOperand:
\_ref_obj: (normalized_divisor), line:88
|vpiName:normalized_divisor
|vpiFullName:work@div_quick_clz.normalized_divisor
|vpiOperand:
\_ref_obj: (remainder_CLZ), line:88
|vpiName:remainder_CLZ
|vpiFullName:work@div_quick_clz.remainder_CLZ
|vpiLhs:
\_ref_obj: (test_multiple1), line:88
|vpiName:test_multiple1
|vpiFullName:work@div_quick_clz.test_multiple1
|vpiContAssign:
\_cont_assign: , line:89
|vpiRhs:
\_operation: , line:89
|vpiOpType:11
|vpiOperand:
\_ref_obj: (div.remainder), line:89
|vpiName:div.remainder
|vpiFullName:work@div_quick_clz.div.remainder
|vpiOperand:
\_ref_obj: (test_multiple1), line:89
|vpiName:test_multiple1
|vpiFullName:work@div_quick_clz.test_multiple1
|vpiLhs:
\_operation: , line:89
|vpiOpType:33
|vpiOperand:
\_ref_obj: (overflow), line:89
|vpiName:overflow
|vpiFullName:work@div_quick_clz.overflow
|vpiOperand:
\_ref_obj: (subtraction1), line:89
|vpiName:subtraction1
|vpiFullName:work@div_quick_clz.subtraction1
|vpiContAssign:
\_cont_assign: , line:91
|vpiRhs:
\_operation: , line:91
|vpiOpType:23
|vpiOperand:
\_ref_obj: (test_multiple1), line:91
|vpiName:test_multiple1
|vpiFullName:work@div_quick_clz.test_multiple1
|vpiOperand:
\_constant: , line:91
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiLhs:
\_ref_obj: (test_multiple2), line:91
|vpiName:test_multiple2
|vpiFullName:work@div_quick_clz.test_multiple2
|vpiContAssign:
\_cont_assign: , line:92
|vpiRhs:
\_operation: , line:92
|vpiOpType:11
|vpiOperand:
\_ref_obj: (div.remainder), line:92
|vpiName:div.remainder
|vpiFullName:work@div_quick_clz.div.remainder
|vpiOperand:
\_ref_obj: (test_multiple2), line:92
|vpiName:test_multiple2
|vpiFullName:work@div_quick_clz.test_multiple2
|vpiLhs:
\_ref_obj: (subtraction2), line:92
|vpiName:subtraction2
|vpiFullName:work@div_quick_clz.subtraction2
|vpiContAssign:
\_cont_assign: , line:94
|vpiRhs:
\_operation: , line:94
|vpiOpType:32
|vpiOperand:
\_ref_obj: (overflow), line:94
|vpiName:overflow
|vpiFullName:work@div_quick_clz.overflow
|vpiOperand:
\_ref_obj: (subtraction2), line:94
|vpiName:subtraction2
|vpiFullName:work@div_quick_clz.subtraction2
|vpiOperand:
\_ref_obj: (subtraction1), line:94
|vpiName:subtraction1
|vpiFullName:work@div_quick_clz.subtraction1
|vpiLhs:
\_ref_obj: (new_remainder), line:94
|vpiName:new_remainder
|vpiFullName:work@div_quick_clz.new_remainder
|vpiContAssign:
\_cont_assign: , line:108
|vpiRhs:
\_operation: , line:108
|vpiOpType:11
|vpiOperand:
\_ref_obj: (divisor_CLZ_r), line:108
|vpiName:divisor_CLZ_r
|vpiFullName:work@div_quick_clz.divisor_CLZ_r
|vpiOperand:
\_ref_obj: (remainder_CLZ), line:108
|vpiName:remainder_CLZ
|vpiFullName:work@div_quick_clz.remainder_CLZ
|vpiLhs:
\_ref_obj: (CLZ_delta), line:108
|vpiName:CLZ_delta
|vpiFullName:work@div_quick_clz.CLZ_delta
|vpiContAssign:
\_cont_assign: , line:113
|vpiRhs:
\_operation: , line:113
|vpiOpType:23
|vpiOperand:
\_ref_obj: (new_Q_bit1), line:113
|vpiName:new_Q_bit1
|vpiFullName:work@div_quick_clz.new_Q_bit1
|vpiOperand:
\_constant: , line:113
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiLhs:
\_ref_obj: (new_Q_bit2), line:113
|vpiName:new_Q_bit2
|vpiFullName:work@div_quick_clz.new_Q_bit2
|vpiContAssign:
\_cont_assign: , line:114
|vpiRhs:
\_operation: , line:114
|vpiOpType:29
|vpiOperand:
\_ref_obj: (div.quotient), line:114
|vpiName:div.quotient
|vpiFullName:work@div_quick_clz.div.quotient
|vpiOperand:
\_operation: , line:114
|vpiOpType:32
|vpiOperand:
\_ref_obj: (overflow), line:114
|vpiName:overflow
|vpiFullName:work@div_quick_clz.overflow
|vpiOperand:
\_ref_obj: (new_Q_bit2), line:114
|vpiName:new_Q_bit2
|vpiFullName:work@div_quick_clz.new_Q_bit2
|vpiOperand:
\_ref_obj: (new_Q_bit1), line:114
|vpiName:new_Q_bit1
|vpiFullName:work@div_quick_clz.new_Q_bit1
|vpiLhs:
\_ref_obj: (new_quotient), line:114
|vpiName:new_quotient
|vpiFullName:work@div_quick_clz.new_quotient
|vpiNet:
\_logic_net: (clk), line:27
|vpiNet:
\_logic_net: (rst), line:28
|vpiNet:
\_logic_net: (running), line:32
|vpiName:running
|vpiFullName:work@div_quick_clz.running
|vpiNetType:36
|vpiNet:
\_logic_net: (terminate), line:33
|vpiName:terminate
|vpiFullName:work@div_quick_clz.terminate
|vpiNetType:36
|vpiNet:
\_logic_net: (normalized_divisor), line:35
|vpiName:normalized_divisor
|vpiFullName:work@div_quick_clz.normalized_divisor
|vpiNetType:36
|vpiNet:
\_logic_net: (overflow), line:37
|vpiName:overflow
|vpiFullName:work@div_quick_clz.overflow
|vpiNetType:36
|vpiNet:
\_logic_net: (subtraction1), line:38
|vpiName:subtraction1
|vpiFullName:work@div_quick_clz.subtraction1
|vpiNetType:36
|vpiNet:
\_logic_net: (subtraction2), line:39
|vpiName:subtraction2
|vpiFullName:work@div_quick_clz.subtraction2
|vpiNetType:36
|vpiNet:
\_logic_net: (new_remainder), line:41
|vpiName:new_remainder
|vpiFullName:work@div_quick_clz.new_remainder
|vpiNetType:36
|vpiNet:
\_logic_net: (new_quotient), line:42
|vpiName:new_quotient
|vpiFullName:work@div_quick_clz.new_quotient
|vpiNetType:36
|vpiNet:
\_logic_net: (new_Q_bit1), line:44
|vpiName:new_Q_bit1
|vpiFullName:work@div_quick_clz.new_Q_bit1
|vpiNetType:36
|vpiNet:
\_logic_net: (new_Q_bit2), line:45
|vpiName:new_Q_bit2
|vpiFullName:work@div_quick_clz.new_Q_bit2
|vpiNetType:36
|vpiNet:
\_logic_net: (test_multiple1), line:47
|vpiName:test_multiple1
|vpiFullName:work@div_quick_clz.test_multiple1
|vpiNetType:36
|vpiNet:
\_logic_net: (test_multiple2), line:48
|vpiName:test_multiple2
|vpiFullName:work@div_quick_clz.test_multiple2
|vpiNetType:36
|vpiNet:
\_logic_net: (remainder_CLZ), line:51
|vpiName:remainder_CLZ
|vpiFullName:work@div_quick_clz.remainder_CLZ
|vpiNetType:36
|vpiNet:
\_logic_net: (divisor_CLZ), line:52
|vpiName:divisor_CLZ
|vpiFullName:work@div_quick_clz.divisor_CLZ
|vpiNetType:36
|vpiNet:
\_logic_net: (divisor_CLZ_r), line:53
|vpiName:divisor_CLZ_r
|vpiFullName:work@div_quick_clz.divisor_CLZ_r
|vpiNetType:36
|vpiNet:
\_logic_net: (CLZ_delta), line:54
|vpiName:CLZ_delta
|vpiFullName:work@div_quick_clz.CLZ_delta
|vpiNetType:36
|vpiNet:
\_logic_net: (div), line:29
|vpiName:div
|vpiFullName:work@div_quick_clz.div
|vpiParamAssign:
\_param_assign: , line:50
|vpiRhs:
\_sys_func_call: ($clog2), line:50
|vpiName:$clog2
|vpiArgument:
\_ref_obj: (div.DATA_WIDTH), line:50
|vpiName:div.DATA_WIDTH
|vpiLhs:
\_parameter: (CLZ_W), line:50
|vpiName:CLZ_W
|vpiLocalParam:1
|vpiParameter:
\_parameter: (CLZ_W), line:50
|uhdmallModules:
\_module: work@div_quick_clz_mk2, file:third_party/cores/taiga/core/div_algorithms/div_quick_clz_mk2.sv, line:25, parent:work@div_unit_core_wrapper
|vpiDefName:work@div_quick_clz_mk2
|vpiFullName:work@div_quick_clz_mk2
|vpiProcess:
\_always: , line:61
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:61
|vpiCondition:
\_operation: , line:61
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:61
|vpiName:clk
|vpiFullName:work@div_quick_clz_mk2.clk
|vpiStmt:
\_begin: , line:61
|vpiFullName:work@div_quick_clz_mk2
|vpiStmt:
\_assignment: , line:62
|vpiOpType:82
|vpiLhs:
\_ref_obj: (B_CLZ_r), line:62
|vpiName:B_CLZ_r
|vpiFullName:work@div_quick_clz_mk2.B_CLZ_r
|vpiRhs:
\_ref_obj: (B_CLZ), line:62
|vpiName:B_CLZ
|vpiFullName:work@div_quick_clz_mk2.B_CLZ
|vpiStmt:
\_assignment: , line:63
|vpiOpType:82
|vpiLhs:
\_ref_obj: (shiftedB), line:63
|vpiName:shiftedB
|vpiFullName:work@div_quick_clz_mk2.shiftedB
|vpiRhs:
\_operation: , line:63
|vpiOpType:22
|vpiOperand:
\_ref_obj: (div.divisor), line:63
|vpiName:div.divisor
|vpiFullName:work@div_quick_clz_mk2.div.divisor
|vpiOperand:
\_ref_obj: (B_CLZ), line:63
|vpiName:B_CLZ
|vpiFullName:work@div_quick_clz_mk2.B_CLZ
|vpiProcess:
\_always: , line:68
|vpiAlwaysType:2
|vpiStmt:
\_begin: , line:68
|vpiFullName:work@div_quick_clz_mk2
|vpiStmt:
\_assignment: , line:69
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (Q_bit1), line:69
|vpiName:Q_bit1
|vpiFullName:work@div_quick_clz_mk2.Q_bit1
|vpiRhs:
\_constant: , line:69
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiStmt:
\_assignment: , line:70
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_bit_select: (Q_bit1), line:70
|vpiName:Q_bit1
|vpiFullName:work@div_quick_clz_mk2.Q_bit1
|vpiIndex:
\_ref_obj: (CLZ_delta), line:70
|vpiName:CLZ_delta
|vpiRhs:
\_constant: , line:70
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiProcess:
\_always: , line:74
|vpiAlwaysType:2
|vpiStmt:
\_begin: , line:74
|vpiFullName:work@div_quick_clz_mk2
|vpiStmt:
\_if_else: , line:75
|vpiCondition:
\_bit_select: (A1), line:75
|vpiName:A1
|vpiFullName:work@div_quick_clz_mk2.A1
|vpiIndex:
\_ref_obj: (div.DATA_WIDTH), line:75
|vpiName:div.DATA_WIDTH
|vpiStmt:
\_assignment: , line:76
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (new_Q_bit), line:76
|vpiName:new_Q_bit
|vpiFullName:work@div_quick_clz_mk2.new_Q_bit
|vpiRhs:
\_ref_obj: (Q_bit2), line:76
|vpiName:Q_bit2
|vpiFullName:work@div_quick_clz_mk2.Q_bit2
|vpiElseStmt:
\_if_else: , line:77
|vpiCondition:
\_operation: , line:77
|vpiOpType:27
|vpiOperand:
\_bit_select: (A0), line:77
|vpiName:A0
|vpiFullName:work@div_quick_clz_mk2.A0
|vpiIndex:
\_ref_obj: (div.DATA_WIDTH), line:77
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_operation: , line:77
|vpiOpType:14
|vpiOperand:
\_ref_obj: (CLZ_delta), line:77
|vpiName:CLZ_delta
|vpiFullName:work@div_quick_clz_mk2.CLZ_delta
|vpiOperand:
\_constant: , line:77
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiStmt:
\_assignment: , line:78
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (new_Q_bit), line:78
|vpiName:new_Q_bit
|vpiFullName:work@div_quick_clz_mk2.new_Q_bit
|vpiRhs:
\_ref_obj: (Q_bit1), line:78
|vpiName:Q_bit1
|vpiFullName:work@div_quick_clz_mk2.Q_bit1
|vpiElseStmt:
\_assignment: , line:80
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (new_Q_bit), line:80
|vpiName:new_Q_bit
|vpiFullName:work@div_quick_clz_mk2.new_Q_bit
|vpiRhs:
\_operation: , line:80
|vpiOpType:29
|vpiOperand:
\_ref_obj: (Q_bit1), line:80
|vpiName:Q_bit1
|vpiFullName:work@div_quick_clz_mk2.Q_bit1
|vpiOperand:
\_ref_obj: (Q_bit2), line:80
|vpiName:Q_bit2
|vpiFullName:work@div_quick_clz_mk2.Q_bit2
|vpiProcess:
\_always: , line:90
|vpiAlwaysType:2
|vpiStmt:
\_begin: , line:90
|vpiFullName:work@div_quick_clz_mk2
|vpiStmt:
\_if_else: , line:91
|vpiCondition:
\_bit_select: (A1), line:91
|vpiName:A1
|vpiFullName:work@div_quick_clz_mk2.A1
|vpiIndex:
\_ref_obj: (div.DATA_WIDTH), line:91
|vpiName:div.DATA_WIDTH
|vpiStmt:
\_assignment: , line:92
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (new_R), line:92
|vpiName:new_R
|vpiFullName:work@div_quick_clz_mk2.new_R
|vpiRhs:
\_part_select: , line:92, parent:A2
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (A2)
|vpiLeftRange:
\_operation: , line:92
|vpiOpType:11
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:92
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:92
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:92
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiElseStmt:
\_if_else: , line:93
|vpiCondition:
\_operation: , line:93
|vpiOpType:27
|vpiOperand:
\_bit_select: (A0), line:93
|vpiName:A0
|vpiFullName:work@div_quick_clz_mk2.A0
|vpiIndex:
\_ref_obj: (div.DATA_WIDTH), line:93
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_operation: , line:93
|vpiOpType:14
|vpiOperand:
\_ref_obj: (CLZ_delta), line:93
|vpiName:CLZ_delta
|vpiFullName:work@div_quick_clz_mk2.CLZ_delta
|vpiOperand:
\_constant: , line:93
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiStmt:
\_assignment: , line:94
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (new_R), line:94
|vpiName:new_R
|vpiFullName:work@div_quick_clz_mk2.new_R
|vpiRhs:
\_part_select: , line:94, parent:A1
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (A1)
|vpiLeftRange:
\_operation: , line:94
|vpiOpType:11
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:94
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:94
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:94
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiElseStmt:
\_assignment: , line:96
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (new_R), line:96
|vpiName:new_R
|vpiFullName:work@div_quick_clz_mk2.new_R
|vpiRhs:
\_part_select: , line:96, parent:A0
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (A0)
|vpiLeftRange:
\_operation: , line:96
|vpiOpType:11
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:96
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:96
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:96
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiProcess:
\_always: , line:101
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:101
|vpiCondition:
\_operation: , line:101
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:101
|vpiName:clk
|vpiFullName:work@div_quick_clz_mk2.clk
|vpiStmt:
\_begin: , line:101
|vpiFullName:work@div_quick_clz_mk2
|vpiStmt:
\_if_else: , line:102
|vpiCondition:
\_ref_obj: (rst), line:102
|vpiName:rst
|vpiFullName:work@div_quick_clz_mk2.rst
|vpiStmt:
\_assignment: , line:103
|vpiOpType:82
|vpiLhs:
\_ref_obj: (running), line:103
|vpiName:running
|vpiFullName:work@div_quick_clz_mk2.running
|vpiRhs:
\_constant: , line:103
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiElseStmt:
\_if_else: , line:104
|vpiCondition:
\_operation: , line:104
|vpiOpType:28
|vpiOperand:
\_ref_obj: (div.start), line:104
|vpiName:div.start
|vpiFullName:work@div_quick_clz_mk2.div.start
|vpiOperand:
\_operation: , line:104
|vpiOpType:4
|vpiOperand:
\_ref_obj: (div.divisor_is_zero), line:104
|vpiName:div.divisor_is_zero
|vpiFullName:work@div_quick_clz_mk2.div.divisor_is_zero
|vpiStmt:
\_assignment: , line:105
|vpiOpType:82
|vpiLhs:
\_ref_obj: (running), line:105
|vpiName:running
|vpiFullName:work@div_quick_clz_mk2.running
|vpiRhs:
\_constant: , line:105
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiElseStmt:
\_if_stmt: , line:106
|vpiCondition:
\_ref_obj: (terminate), line:106
|vpiName:terminate
|vpiFullName:work@div_quick_clz_mk2.terminate
|vpiStmt:
\_assignment: , line:107
|vpiOpType:82
|vpiLhs:
\_ref_obj: (running), line:107
|vpiName:running
|vpiFullName:work@div_quick_clz_mk2.running
|vpiRhs:
\_constant: , line:107
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiProcess:
\_always: , line:110
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:110
|vpiCondition:
\_operation: , line:110
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:110
|vpiName:clk
|vpiFullName:work@div_quick_clz_mk2.clk
|vpiStmt:
\_begin: , line:110
|vpiFullName:work@div_quick_clz_mk2
|vpiStmt:
\_assignment: , line:111
|vpiOpType:82
|vpiLhs:
\_ref_obj: (div.done), line:111
|vpiName:div.done
|vpiFullName:work@div_quick_clz_mk2.div.done
|vpiRhs:
\_operation: , line:111
|vpiOpType:29
|vpiOperand:
\_operation: , line:111
|vpiOpType:28
|vpiOperand:
\_ref_obj: (running), line:111
|vpiName:running
|vpiFullName:work@div_quick_clz_mk2.running
|vpiOperand:
\_ref_obj: (terminate), line:111
|vpiName:terminate
|vpiFullName:work@div_quick_clz_mk2.terminate
|vpiOperand:
\_operation: , line:111
|vpiOpType:28
|vpiOperand:
\_ref_obj: (div.start), line:111
|vpiName:div.start
|vpiFullName:work@div_quick_clz_mk2.div.start
|vpiOperand:
\_ref_obj: (div.divisor_is_zero), line:111
|vpiName:div.divisor_is_zero
|vpiFullName:work@div_quick_clz_mk2.div.divisor_is_zero
|vpiProcess:
\_always: , line:116
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:116
|vpiCondition:
\_operation: , line:116
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:116
|vpiName:clk
|vpiFullName:work@div_quick_clz_mk2.clk
|vpiStmt:
\_begin: , line:116
|vpiFullName:work@div_quick_clz_mk2
|vpiStmt:
\_if_else: , line:117
|vpiCondition:
\_ref_obj: (div.start), line:117
|vpiName:div.start
|vpiFullName:work@div_quick_clz_mk2.div.start
|vpiStmt:
\_assignment: , line:118
|vpiOpType:82
|vpiLhs:
\_ref_obj: (div.quotient), line:118
|vpiName:div.quotient
|vpiFullName:work@div_quick_clz_mk2.div.quotient
|vpiRhs:
\_operation: , line:118
|vpiOpType:32
|vpiOperand:
\_ref_obj: (div.divisor_is_zero), line:118
|vpiName:div.divisor_is_zero
|vpiFullName:work@div_quick_clz_mk2.div.divisor_is_zero
|vpiOperand:
\_constant: , line:118
|vpiConstType:3
|vpiDecompile:'b1
|vpiSize:1
|BIN:1
|vpiOperand:
\_constant: , line:118
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiElseStmt:
\_if_stmt: , line:119
|vpiCondition:
\_operation: , line:119
|vpiOpType:28
|vpiOperand:
\_operation: , line:119
|vpiOpType:4
|vpiOperand:
\_ref_obj: (terminate), line:119
|vpiName:terminate
|vpiFullName:work@div_quick_clz_mk2.terminate
|vpiOperand:
\_ref_obj: (running), line:119
|vpiName:running
|vpiFullName:work@div_quick_clz_mk2.running
|vpiStmt:
\_assignment: , line:120
|vpiOpType:82
|vpiLhs:
\_ref_obj: (div.quotient), line:120
|vpiName:div.quotient
|vpiFullName:work@div_quick_clz_mk2.div.quotient
|vpiRhs:
\_operation: , line:120
|vpiOpType:29
|vpiOperand:
\_ref_obj: (div.quotient), line:120
|vpiName:div.quotient
|vpiFullName:work@div_quick_clz_mk2.div.quotient
|vpiOperand:
\_ref_obj: (new_Q_bit), line:120
|vpiName:new_Q_bit
|vpiFullName:work@div_quick_clz_mk2.new_Q_bit
|vpiProcess:
\_initial:
|vpiStmt:
\_begin: , line:123
|vpiFullName:work@div_quick_clz_mk2
|vpiStmt:
\_assignment: , line:124
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (div.remainder), line:124
|vpiName:div.remainder
|vpiFullName:work@div_quick_clz_mk2.div.remainder
|vpiRhs:
\_constant: , line:124
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiProcess:
\_always: , line:126
|vpiAlwaysType:1
|vpiStmt:
\_event_control: , line:126
|vpiCondition:
\_operation: , line:126
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:126
|vpiName:clk
|vpiFullName:work@div_quick_clz_mk2.clk
|vpiStmt:
\_begin: , line:126
|vpiFullName:work@div_quick_clz_mk2
|vpiStmt:
\_if_else: , line:127
|vpiCondition:
\_ref_obj: (div.start), line:127
|vpiName:div.start
|vpiFullName:work@div_quick_clz_mk2.div.start
|vpiStmt:
\_assignment: , line:128
|vpiOpType:82
|vpiLhs:
\_ref_obj: (div.remainder), line:128
|vpiName:div.remainder
|vpiFullName:work@div_quick_clz_mk2.div.remainder
|vpiRhs:
\_ref_obj: (div.dividend), line:128
|vpiName:div.dividend
|vpiFullName:work@div_quick_clz_mk2.div.dividend
|vpiElseStmt:
\_if_stmt: , line:129
|vpiCondition:
\_operation: , line:129
|vpiOpType:28
|vpiOperand:
\_operation: , line:129
|vpiOpType:4
|vpiOperand:
\_ref_obj: (terminate), line:129
|vpiName:terminate
|vpiFullName:work@div_quick_clz_mk2.terminate
|vpiOperand:
\_ref_obj: (running), line:129
|vpiName:running
|vpiFullName:work@div_quick_clz_mk2.running
|vpiStmt:
\_assignment: , line:130
|vpiOpType:82
|vpiLhs:
\_ref_obj: (div.remainder), line:130
|vpiName:div.remainder
|vpiFullName:work@div_quick_clz_mk2.div.remainder
|vpiRhs:
\_ref_obj: (new_R), line:130
|vpiName:new_R
|vpiFullName:work@div_quick_clz_mk2.new_R
|vpiPort:
\_port: (clk), line:27
|vpiName:clk
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (clk), line:27
|vpiName:clk
|vpiFullName:work@div_quick_clz_mk2.clk
|vpiNetType:36
|vpiPort:
\_port: (rst), line:28
|vpiName:rst
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (rst), line:28
|vpiName:rst
|vpiFullName:work@div_quick_clz_mk2.rst
|vpiNetType:36
|vpiPort:
\_port: (div), line:29
|vpiName:div
|vpiDirection:5
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_modport: (divider)
|vpiContAssign:
\_cont_assign: , line:66
|vpiRhs:
\_operation: , line:66
|vpiOpType:11
|vpiOperand:
\_ref_obj: (B_CLZ_r), line:66
|vpiName:B_CLZ_r
|vpiFullName:work@div_quick_clz_mk2.B_CLZ_r
|vpiOperand:
\_ref_obj: (R_CLZ), line:66
|vpiName:R_CLZ
|vpiFullName:work@div_quick_clz_mk2.R_CLZ
|vpiLhs:
\_ref_obj: (CLZ_delta), line:66
|vpiName:CLZ_delta
|vpiFullName:work@div_quick_clz_mk2.CLZ_delta
|vpiContAssign:
\_cont_assign: , line:72
|vpiRhs:
\_operation: , line:72
|vpiOpType:33
|vpiOperand:
\_constant: , line:72
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiOperand:
\_part_select: , line:72, parent:Q_bit1
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (Q_bit1)
|vpiLeftRange:
\_operation: , line:72
|vpiOpType:11
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:72
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:72
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:72
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiLhs:
\_ref_obj: (Q_bit2), line:72
|vpiName:Q_bit2
|vpiFullName:work@div_quick_clz_mk2.Q_bit2
|vpiContAssign:
\_cont_assign: , line:83
|vpiRhs:
\_operation: , line:83
|vpiOpType:23
|vpiOperand:
\_ref_obj: (shiftedB), line:83
|vpiName:shiftedB
|vpiFullName:work@div_quick_clz_mk2.shiftedB
|vpiOperand:
\_ref_obj: (R_CLZ), line:83
|vpiName:R_CLZ
|vpiFullName:work@div_quick_clz_mk2.R_CLZ
|vpiLhs:
\_ref_obj: (B1), line:83
|vpiName:B1
|vpiFullName:work@div_quick_clz_mk2.B1
|vpiContAssign:
\_cont_assign: , line:84
|vpiRhs:
\_operation: , line:84
|vpiOpType:11
|vpiOperand:
\_ref_obj: (div.remainder), line:84
|vpiName:div.remainder
|vpiFullName:work@div_quick_clz_mk2.div.remainder
|vpiOperand:
\_ref_obj: (B1), line:84
|vpiName:B1
|vpiFullName:work@div_quick_clz_mk2.B1
|vpiLhs:
\_ref_obj: (A1), line:84
|vpiName:A1
|vpiFullName:work@div_quick_clz_mk2.A1
|vpiContAssign:
\_cont_assign: , line:85
|vpiRhs:
\_operation: , line:85
|vpiOpType:33
|vpiOperand:
\_constant: , line:85
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiOperand:
\_part_select: , line:85, parent:B1
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (B1)
|vpiLeftRange:
\_operation: , line:85
|vpiOpType:11
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:85
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:85
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:85
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiLhs:
\_ref_obj: (B2), line:85
|vpiName:B2
|vpiFullName:work@div_quick_clz_mk2.B2
|vpiContAssign:
\_cont_assign: , line:86
|vpiRhs:
\_operation: , line:86
|vpiOpType:11
|vpiOperand:
\_ref_obj: (div.remainder), line:86
|vpiName:div.remainder
|vpiFullName:work@div_quick_clz_mk2.div.remainder
|vpiOperand:
\_ref_obj: (B2), line:86
|vpiName:B2
|vpiFullName:work@div_quick_clz_mk2.B2
|vpiLhs:
\_ref_obj: (A2), line:86
|vpiName:A2
|vpiFullName:work@div_quick_clz_mk2.A2
|vpiContAssign:
\_cont_assign: , line:88
|vpiRhs:
\_operation: , line:88
|vpiOpType:11
|vpiOperand:
\_ref_obj: (div.remainder), line:88
|vpiName:div.remainder
|vpiFullName:work@div_quick_clz_mk2.div.remainder
|vpiOperand:
\_operation: , line:88
|vpiOpType:24
|vpiOperand:
\_ref_obj: (B1), line:88
|vpiName:B1
|vpiFullName:work@div_quick_clz_mk2.B1
|vpiOperand:
\_ref_obj: (B2), line:88
|vpiName:B2
|vpiFullName:work@div_quick_clz_mk2.B2
|vpiLhs:
\_ref_obj: (A0), line:88
|vpiName:A0
|vpiFullName:work@div_quick_clz_mk2.A0
|vpiContAssign:
\_cont_assign: , line:99
|vpiRhs:
\_operation: , line:99
|vpiOpType:26
|vpiOperand:
\_operation: , line:99
|vpiOpType:14
|vpiOperand:
\_ref_obj: (B_CLZ), line:99
|vpiName:B_CLZ
|vpiFullName:work@div_quick_clz_mk2.B_CLZ
|vpiOperand:
\_constant: , line:99
|vpiConstType:3
|vpiDecompile:5'b11111
|vpiSize:5
|BIN:5'b11111
|vpiOperand:
\_operation: , line:99
|vpiOpType:4
|vpiOperand:
\_ref_obj: (div.divisor), line:99
|vpiName:div.divisor
|vpiFullName:work@div_quick_clz_mk2.div.divisor
|vpiLhs:
\_ref_obj: (div.divisor_is_zero), line:99
|vpiName:div.divisor_is_zero
|vpiFullName:work@div_quick_clz_mk2.div.divisor_is_zero
|vpiContAssign:
\_cont_assign: , line:114
|vpiRhs:
\_operation: , line:114
|vpiOpType:20
|vpiOperand:
\_ref_obj: (div.remainder), line:114
|vpiName:div.remainder
|vpiFullName:work@div_quick_clz_mk2.div.remainder
|vpiOperand:
\_ref_obj: (div.divisor), line:114
|vpiName:div.divisor
|vpiFullName:work@div_quick_clz_mk2.div.divisor
|vpiLhs:
\_ref_obj: (terminate), line:114
|vpiName:terminate
|vpiFullName:work@div_quick_clz_mk2.terminate
|vpiNet:
\_logic_net: (clk), line:27
|vpiNet:
\_logic_net: (rst), line:28
|vpiNet:
\_logic_net: (running), line:32
|vpiName:running
|vpiFullName:work@div_quick_clz_mk2.running
|vpiNetType:36
|vpiNet:
\_logic_net: (terminate), line:33
|vpiName:terminate
|vpiFullName:work@div_quick_clz_mk2.terminate
|vpiNetType:36
|vpiNet:
\_logic_net: (A0), line:35
|vpiName:A0
|vpiFullName:work@div_quick_clz_mk2.A0
|vpiNetType:36
|vpiNet:
\_logic_net: (A1), line:36
|vpiName:A1
|vpiFullName:work@div_quick_clz_mk2.A1
|vpiNetType:36
|vpiNet:
\_logic_net: (A2), line:37
|vpiName:A2
|vpiFullName:work@div_quick_clz_mk2.A2
|vpiNetType:36
|vpiNet:
\_logic_net: (new_R), line:39
|vpiName:new_R
|vpiFullName:work@div_quick_clz_mk2.new_R
|vpiNetType:36
|vpiNet:
\_logic_net: (new_Q_bit), line:40
|vpiName:new_Q_bit
|vpiFullName:work@div_quick_clz_mk2.new_Q_bit
|vpiNetType:36
|vpiNet:
\_logic_net: (new_R2), line:41
|vpiName:new_R2
|vpiFullName:work@div_quick_clz_mk2.new_R2
|vpiNetType:36
|vpiNet:
\_logic_net: (Q_bit1), line:43
|vpiName:Q_bit1
|vpiFullName:work@div_quick_clz_mk2.Q_bit1
|vpiNetType:36
|vpiNet:
\_logic_net: (Q_bit2), line:44
|vpiName:Q_bit2
|vpiFullName:work@div_quick_clz_mk2.Q_bit2
|vpiNetType:36
|vpiNet:
\_logic_net: (B1), line:46
|vpiName:B1
|vpiFullName:work@div_quick_clz_mk2.B1
|vpiNetType:36
|vpiNet:
\_logic_net: (B2), line:47
|vpiName:B2
|vpiFullName:work@div_quick_clz_mk2.B2
|vpiNetType:36
|vpiNet:
\_logic_net: (R_CLZ), line:50
|vpiName:R_CLZ
|vpiFullName:work@div_quick_clz_mk2.R_CLZ
|vpiNetType:36
|vpiNet:
\_logic_net: (B_CLZ), line:51
|vpiName:B_CLZ
|vpiFullName:work@div_quick_clz_mk2.B_CLZ
|vpiNetType:36
|vpiNet:
\_logic_net: (B_CLZ_r), line:52
|vpiName:B_CLZ_r
|vpiFullName:work@div_quick_clz_mk2.B_CLZ_r
|vpiNetType:36
|vpiNet:
\_logic_net: (CLZ_delta), line:53
|vpiName:CLZ_delta
|vpiFullName:work@div_quick_clz_mk2.CLZ_delta
|vpiNetType:36
|vpiNet:
\_logic_net: (shiftedB), line:55
|vpiName:shiftedB
|vpiFullName:work@div_quick_clz_mk2.shiftedB
|vpiNetType:36
|vpiNet:
\_logic_net: (div), line:29
|vpiName:div
|vpiFullName:work@div_quick_clz_mk2.div
|vpiParamAssign:
\_param_assign: , line:49
|vpiRhs:
\_sys_func_call: ($clog2), line:49
|vpiName:$clog2
|vpiArgument:
\_ref_obj: (div.DATA_WIDTH), line:49
|vpiName:div.DATA_WIDTH
|vpiLhs:
\_parameter: (CLZ_W), line:49
|vpiName:CLZ_W
|vpiLocalParam:1
|vpiParameter:
\_parameter: (CLZ_W), line:49
|uhdmallModules:
\_module: work@div_quick_naive, file:third_party/cores/taiga/core/div_algorithms/div_quick_naive.sv, line:25, parent:work@div_unit_core_wrapper
|vpiDefName:work@div_quick_naive
|vpiFullName:work@div_quick_naive
|vpiProcess:
\_always: , line:74
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:74
|vpiCondition:
\_operation: , line:74
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:74
|vpiName:clk
|vpiFullName:work@div_quick_naive.clk
|vpiStmt:
\_begin: , line:74
|vpiFullName:work@div_quick_naive
|vpiStmt:
\_if_else: , line:75
|vpiCondition:
\_ref_obj: (rst), line:75
|vpiName:rst
|vpiFullName:work@div_quick_naive.rst
|vpiStmt:
\_assignment: , line:76
|vpiOpType:82
|vpiLhs:
\_ref_obj: (running), line:76
|vpiName:running
|vpiFullName:work@div_quick_naive.running
|vpiRhs:
\_constant: , line:76
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiElseStmt:
\_if_else: , line:77
|vpiCondition:
\_operation: , line:77
|vpiOpType:28
|vpiOperand:
\_ref_obj: (div.start), line:77
|vpiName:div.start
|vpiFullName:work@div_quick_naive.div.start
|vpiOperand:
\_operation: , line:77
|vpiOpType:4
|vpiOperand:
\_ref_obj: (div.divisor_is_zero), line:77
|vpiName:div.divisor_is_zero
|vpiFullName:work@div_quick_naive.div.divisor_is_zero
|vpiStmt:
\_assignment: , line:78
|vpiOpType:82
|vpiLhs:
\_ref_obj: (running), line:78
|vpiName:running
|vpiFullName:work@div_quick_naive.running
|vpiRhs:
\_constant: , line:78
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiElseStmt:
\_if_stmt: , line:79
|vpiCondition:
\_ref_obj: (terminate), line:79
|vpiName:terminate
|vpiFullName:work@div_quick_naive.terminate
|vpiStmt:
\_assignment: , line:80
|vpiOpType:82
|vpiLhs:
\_ref_obj: (running), line:80
|vpiName:running
|vpiFullName:work@div_quick_naive.running
|vpiRhs:
\_constant: , line:80
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiProcess:
\_always: , line:83
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:83
|vpiCondition:
\_operation: , line:83
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:83
|vpiName:clk
|vpiFullName:work@div_quick_naive.clk
|vpiStmt:
\_begin: , line:83
|vpiFullName:work@div_quick_naive
|vpiStmt:
\_if_else: , line:84
|vpiCondition:
\_ref_obj: (rst), line:84
|vpiName:rst
|vpiFullName:work@div_quick_naive.rst
|vpiStmt:
\_assignment: , line:85
|vpiOpType:82
|vpiLhs:
\_ref_obj: (div.done), line:85
|vpiName:div.done
|vpiFullName:work@div_quick_naive.div.done
|vpiRhs:
\_constant: , line:85
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiElseStmt:
\_if_else: , line:86
|vpiCondition:
\_ref_obj: (div.done), line:86
|vpiName:div.done
|vpiFullName:work@div_quick_naive.div.done
|vpiStmt:
\_assignment: , line:87
|vpiOpType:82
|vpiLhs:
\_ref_obj: (div.done), line:87
|vpiName:div.done
|vpiFullName:work@div_quick_naive.div.done
|vpiRhs:
\_constant: , line:87
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiElseStmt:
\_if_stmt: , line:88
|vpiCondition:
\_operation: , line:88
|vpiOpType:29
|vpiOperand:
\_operation: , line:88
|vpiOpType:28
|vpiOperand:
\_ref_obj: (running), line:88
|vpiName:running
|vpiFullName:work@div_quick_naive.running
|vpiOperand:
\_ref_obj: (terminate), line:88
|vpiName:terminate
|vpiFullName:work@div_quick_naive.terminate
|vpiOperand:
\_operation: , line:88
|vpiOpType:28
|vpiOperand:
\_ref_obj: (div.start), line:88
|vpiName:div.start
|vpiFullName:work@div_quick_naive.div.start
|vpiOperand:
\_ref_obj: (div.divisor_is_zero), line:88
|vpiName:div.divisor_is_zero
|vpiFullName:work@div_quick_naive.div.divisor_is_zero
|vpiStmt:
\_assignment: , line:89
|vpiOpType:82
|vpiLhs:
\_ref_obj: (div.done), line:89
|vpiName:div.done
|vpiFullName:work@div_quick_naive.div.done
|vpiRhs:
\_constant: , line:89
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiProcess:
\_always: , line:94
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:94
|vpiCondition:
\_operation: , line:94
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:94
|vpiName:clk
|vpiFullName:work@div_quick_naive.clk
|vpiStmt:
\_begin: , line:94
|vpiFullName:work@div_quick_naive
|vpiStmt:
\_assignment: , line:95
|vpiOpType:82
|vpiLhs:
\_ref_obj: (B_MSB_r), line:95
|vpiName:B_MSB_r
|vpiFullName:work@div_quick_naive.B_MSB_r
|vpiRhs:
\_ref_obj: (B_MSB), line:95
|vpiName:B_MSB
|vpiFullName:work@div_quick_naive.B_MSB
|vpiStmt:
\_if_else: , line:96
|vpiCondition:
\_ref_obj: (div.start), line:96
|vpiName:div.start
|vpiFullName:work@div_quick_naive.div.start
|vpiStmt:
\_begin: , line:96
|vpiFullName:work@div_quick_naive
|vpiStmt:
\_assignment: , line:97
|vpiOpType:82
|vpiLhs:
\_ref_obj: (div.quotient), line:97
|vpiName:div.quotient
|vpiFullName:work@div_quick_naive.div.quotient
|vpiRhs:
\_operation: , line:97
|vpiOpType:32
|vpiOperand:
\_ref_obj: (div.divisor_is_zero), line:97
|vpiName:div.divisor_is_zero
|vpiFullName:work@div_quick_naive.div.divisor_is_zero
|vpiOperand:
\_constant: , line:97
|vpiConstType:3
|vpiDecompile:'b1
|vpiSize:1
|BIN:1
|vpiOperand:
\_constant: , line:97
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiStmt:
\_assignment: , line:98
|vpiOpType:82
|vpiLhs:
\_ref_obj: (div.remainder), line:98
|vpiName:div.remainder
|vpiFullName:work@div_quick_naive.div.remainder
|vpiRhs:
\_ref_obj: (div.dividend), line:98
|vpiName:div.dividend
|vpiFullName:work@div_quick_naive.div.dividend
|vpiElseStmt:
\_if_stmt: , line:100
|vpiCondition:
\_operation: , line:100
|vpiOpType:28
|vpiOperand:
\_operation: , line:100
|vpiOpType:4
|vpiOperand:
\_ref_obj: (terminate), line:100
|vpiName:terminate
|vpiFullName:work@div_quick_naive.terminate
|vpiOperand:
\_ref_obj: (running), line:100
|vpiName:running
|vpiFullName:work@div_quick_naive.running
|vpiStmt:
\_begin: , line:100
|vpiFullName:work@div_quick_naive
|vpiStmt:
\_assignment: , line:101
|vpiOpType:82
|vpiLhs:
\_ref_obj: (div.quotient), line:101
|vpiName:div.quotient
|vpiFullName:work@div_quick_naive.div.quotient
|vpiRhs:
\_ref_obj: (new_Q_bit), line:101
|vpiName:new_Q_bit
|vpiFullName:work@div_quick_naive.new_Q_bit
|vpiStmt:
\_assignment: , line:102
|vpiOpType:82
|vpiLhs:
\_ref_obj: (div.remainder), line:102
|vpiName:div.remainder
|vpiFullName:work@div_quick_naive.div.remainder
|vpiRhs:
\_ref_obj: (new_R), line:102
|vpiName:new_R
|vpiFullName:work@div_quick_naive.new_R
|vpiPort:
\_port: (clk), line:27
|vpiName:clk
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (clk), line:27
|vpiName:clk
|vpiFullName:work@div_quick_naive.clk
|vpiNetType:36
|vpiPort:
\_port: (rst), line:28
|vpiName:rst
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (rst), line:28
|vpiName:rst
|vpiFullName:work@div_quick_naive.rst
|vpiNetType:36
|vpiPort:
\_port: (div), line:29
|vpiName:div
|vpiDirection:5
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_modport: (divider)
|vpiContAssign:
\_cont_assign: , line:58
|vpiRhs:
\_operation: , line:58
|vpiOpType:11
|vpiOperand:
\_ref_obj: (R_MSB), line:58
|vpiName:R_MSB
|vpiFullName:work@div_quick_naive.R_MSB
|vpiOperand:
\_ref_obj: (B_MSB_r), line:58
|vpiName:B_MSB_r
|vpiFullName:work@div_quick_naive.B_MSB_r
|vpiLhs:
\_ref_obj: (MSB_delta), line:58
|vpiName:MSB_delta
|vpiFullName:work@div_quick_naive.MSB_delta
|vpiContAssign:
\_cont_assign: , line:60
|vpiRhs:
\_operation: , line:60
|vpiOpType:43
|vpiOperand:
\_constant: , line:60
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiOperand:
\_ref_obj: (MSB_delta), line:60
|vpiName:MSB_delta
|vpiFullName:work@div_quick_naive.MSB_delta
|vpiLhs:
\_ref_obj: (Q_bit1), line:60
|vpiName:Q_bit1
|vpiFullName:work@div_quick_naive.Q_bit1
|vpiContAssign:
\_cont_assign: , line:61
|vpiRhs:
\_operation: , line:61
|vpiOpType:33
|vpiOperand:
\_constant: , line:61
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiOperand:
\_part_select: , line:61, parent:Q_bit1
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (Q_bit1)
|vpiLeftRange:
\_operation: , line:61
|vpiOpType:11
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:61
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:61
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:61
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiLhs:
\_ref_obj: (Q_bit2), line:61
|vpiName:Q_bit2
|vpiFullName:work@div_quick_naive.Q_bit2
|vpiContAssign:
\_cont_assign: , line:62
|vpiRhs:
\_operation: , line:62
|vpiOpType:29
|vpiOperand:
\_ref_obj: (div.quotient), line:62
|vpiName:div.quotient
|vpiFullName:work@div_quick_naive.div.quotient
|vpiOperand:
\_operation: , line:62
|vpiOpType:32
|vpiOperand:
\_bit_select: (A1), line:62
|vpiName:A1
|vpiFullName:work@div_quick_naive.A1
|vpiIndex:
\_ref_obj: (div.DATA_WIDTH), line:62
|vpiName:div.DATA_WIDTH
|vpiFullName:work@div_quick_naive.div.DATA_WIDTH
|vpiOperand:
\_ref_obj: (Q_bit2), line:62
|vpiName:Q_bit2
|vpiFullName:work@div_quick_naive.Q_bit2
|vpiOperand:
\_ref_obj: (Q_bit1), line:62
|vpiName:Q_bit1
|vpiFullName:work@div_quick_naive.Q_bit1
|vpiLhs:
\_ref_obj: (new_Q_bit), line:62
|vpiName:new_Q_bit
|vpiFullName:work@div_quick_naive.new_Q_bit
|vpiContAssign:
\_cont_assign: , line:64
|vpiRhs:
\_operation: , line:64
|vpiOpType:22
|vpiOperand:
\_ref_obj: (div.divisor), line:64
|vpiName:div.divisor
|vpiFullName:work@div_quick_naive.div.divisor
|vpiOperand:
\_ref_obj: (MSB_delta), line:64
|vpiName:MSB_delta
|vpiFullName:work@div_quick_naive.MSB_delta
|vpiLhs:
\_ref_obj: (B1), line:64
|vpiName:B1
|vpiFullName:work@div_quick_naive.B1
|vpiContAssign:
\_cont_assign: , line:65
|vpiRhs:
\_operation: , line:65
|vpiOpType:11
|vpiOperand:
\_ref_obj: (div.remainder), line:65
|vpiName:div.remainder
|vpiFullName:work@div_quick_naive.div.remainder
|vpiOperand:
\_ref_obj: (B1), line:65
|vpiName:B1
|vpiFullName:work@div_quick_naive.B1
|vpiLhs:
\_ref_obj: (A1), line:65
|vpiName:A1
|vpiFullName:work@div_quick_naive.A1
|vpiContAssign:
\_cont_assign: , line:66
|vpiRhs:
\_operation: , line:66
|vpiOpType:33
|vpiOperand:
\_constant: , line:66
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiOperand:
\_part_select: , line:66, parent:B1
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (B1)
|vpiLeftRange:
\_operation: , line:66
|vpiOpType:11
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:66
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:66
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:66
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiLhs:
\_ref_obj: (B2), line:66
|vpiName:B2
|vpiFullName:work@div_quick_naive.B2
|vpiContAssign:
\_cont_assign: , line:67
|vpiRhs:
\_operation: , line:67
|vpiOpType:11
|vpiOperand:
\_ref_obj: (div.remainder), line:67
|vpiName:div.remainder
|vpiFullName:work@div_quick_naive.div.remainder
|vpiOperand:
\_ref_obj: (B2), line:67
|vpiName:B2
|vpiFullName:work@div_quick_naive.B2
|vpiLhs:
\_ref_obj: (A2), line:67
|vpiName:A2
|vpiFullName:work@div_quick_naive.A2
|vpiContAssign:
\_cont_assign: , line:69
|vpiRhs:
\_operation: , line:69
|vpiOpType:32
|vpiOperand:
\_bit_select: (A1), line:69
|vpiName:A1
|vpiFullName:work@div_quick_naive.A1
|vpiIndex:
\_ref_obj: (div.DATA_WIDTH), line:69
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_ref_obj: (A2), line:69
|vpiName:A2
|vpiFullName:work@div_quick_naive.A2
|vpiOperand:
\_part_select: , line:69, parent:A1
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (A1)
|vpiLeftRange:
\_operation: , line:69
|vpiOpType:11
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:69
|vpiName:div.DATA_WIDTH
|vpiFullName:work@div_quick_naive.div.DATA_WIDTH
|vpiOperand:
\_constant: , line:69
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:69
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiLhs:
\_ref_obj: (new_R), line:69
|vpiName:new_R
|vpiFullName:work@div_quick_naive.new_R
|vpiContAssign:
\_cont_assign: , line:71
|vpiRhs:
\_operation: , line:71
|vpiOpType:26
|vpiOperand:
\_operation: , line:71
|vpiOpType:14
|vpiOperand:
\_ref_obj: (B_MSB), line:71
|vpiName:B_MSB
|vpiFullName:work@div_quick_naive.B_MSB
|vpiOperand:
\_constant: , line:71
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiOperand:
\_operation: , line:71
|vpiOpType:4
|vpiOperand:
\_ref_obj: (div.divisor), line:71
|vpiName:div.divisor
|vpiFullName:work@div_quick_naive.div.divisor
|vpiLhs:
\_ref_obj: (div.divisor_is_zero), line:71
|vpiName:div.divisor_is_zero
|vpiFullName:work@div_quick_naive.div.divisor_is_zero
|vpiContAssign:
\_cont_assign: , line:92
|vpiRhs:
\_operation: , line:92
|vpiOpType:20
|vpiOperand:
\_ref_obj: (div.remainder), line:92
|vpiName:div.remainder
|vpiFullName:work@div_quick_naive.div.remainder
|vpiOperand:
\_ref_obj: (div.divisor), line:92
|vpiName:div.divisor
|vpiFullName:work@div_quick_naive.div.divisor
|vpiLhs:
\_ref_obj: (terminate), line:92
|vpiName:terminate
|vpiFullName:work@div_quick_naive.terminate
|vpiNet:
\_logic_net: (clk), line:27
|vpiNet:
\_logic_net: (rst), line:28
|vpiNet:
\_logic_net: (running), line:32
|vpiName:running
|vpiFullName:work@div_quick_naive.running
|vpiNetType:36
|vpiNet:
\_logic_net: (terminate), line:33
|vpiName:terminate
|vpiFullName:work@div_quick_naive.terminate
|vpiNetType:36
|vpiNet:
\_logic_net: (A1), line:35
|vpiName:A1
|vpiFullName:work@div_quick_naive.A1
|vpiNetType:36
|vpiNet:
\_logic_net: (A2), line:36
|vpiName:A2
|vpiFullName:work@div_quick_naive.A2
|vpiNetType:36
|vpiNet:
\_logic_net: (new_R), line:38
|vpiName:new_R
|vpiFullName:work@div_quick_naive.new_R
|vpiNetType:36
|vpiNet:
\_logic_net: (new_Q_bit), line:39
|vpiName:new_Q_bit
|vpiFullName:work@div_quick_naive.new_Q_bit
|vpiNetType:36
|vpiNet:
\_logic_net: (Q_bit1), line:41
|vpiName:Q_bit1
|vpiFullName:work@div_quick_naive.Q_bit1
|vpiNetType:36
|vpiNet:
\_logic_net: (Q_bit2), line:42
|vpiName:Q_bit2
|vpiFullName:work@div_quick_naive.Q_bit2
|vpiNetType:36
|vpiNet:
\_logic_net: (B1), line:44
|vpiName:B1
|vpiFullName:work@div_quick_naive.B1
|vpiNetType:36
|vpiNet:
\_logic_net: (B2), line:45
|vpiName:B2
|vpiFullName:work@div_quick_naive.B2
|vpiNetType:36
|vpiNet:
\_logic_net: (R_MSB), line:48
|vpiName:R_MSB
|vpiFullName:work@div_quick_naive.R_MSB
|vpiNetType:36
|vpiNet:
\_logic_net: (B_MSB), line:49
|vpiName:B_MSB
|vpiFullName:work@div_quick_naive.B_MSB
|vpiNetType:36
|vpiNet:
\_logic_net: (B_MSB_r), line:50
|vpiName:B_MSB_r
|vpiFullName:work@div_quick_naive.B_MSB_r
|vpiNetType:36
|vpiNet:
\_logic_net: (MSB_delta), line:51
|vpiName:MSB_delta
|vpiFullName:work@div_quick_naive.MSB_delta
|vpiNetType:36
|vpiNet:
\_logic_net: (div), line:29
|vpiName:div
|vpiFullName:work@div_quick_naive.div
|vpiParamAssign:
\_param_assign: , line:47
|vpiRhs:
\_sys_func_call: ($clog2), line:47
|vpiName:$clog2
|vpiArgument:
\_ref_obj: (div.DATA_WIDTH), line:47
|vpiName:div.DATA_WIDTH
|vpiLhs:
\_parameter: (MSB_W), line:47
|vpiName:MSB_W
|vpiLocalParam:1
|vpiParameter:
\_parameter: (MSB_W), line:47
|uhdmallModules:
\_module: work@div_quick_radix_4, file:third_party/cores/taiga/core/div_algorithms/div_quick_radix4.sv, line:25, parent:work@div_unit_core_wrapper
|vpiDefName:work@div_quick_radix_4
|vpiFullName:work@div_quick_radix_4
|vpiProcess:
\_always: , line:72
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:72
|vpiCondition:
\_operation: , line:72
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:72
|vpiName:clk
|vpiFullName:work@div_quick_radix_4.clk
|vpiStmt:
\_begin: , line:72
|vpiFullName:work@div_quick_radix_4
|vpiStmt:
\_if_else: , line:73
|vpiCondition:
\_ref_obj: (rst), line:73
|vpiName:rst
|vpiFullName:work@div_quick_radix_4.rst
|vpiStmt:
\_begin: , line:73
|vpiFullName:work@div_quick_radix_4
|vpiStmt:
\_assignment: , line:74
|vpiOpType:82
|vpiLhs:
\_ref_obj: (firstCycle), line:74
|vpiName:firstCycle
|vpiFullName:work@div_quick_radix_4.firstCycle
|vpiRhs:
\_constant: , line:74
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiStmt:
\_assignment: , line:75
|vpiOpType:82
|vpiLhs:
\_ref_obj: (A_CLZ_r), line:75
|vpiName:A_CLZ_r
|vpiFullName:work@div_quick_radix_4.A_CLZ_r
|vpiRhs:
\_constant: , line:75
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiStmt:
\_assignment: , line:76
|vpiOpType:82
|vpiLhs:
\_ref_obj: (B_CLZ_r), line:76
|vpiName:B_CLZ_r
|vpiFullName:work@div_quick_radix_4.B_CLZ_r
|vpiRhs:
\_constant: , line:76
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiStmt:
\_assignment: , line:77
|vpiOpType:82
|vpiLhs:
\_ref_obj: (A_shifted), line:77
|vpiName:A_shifted
|vpiFullName:work@div_quick_radix_4.A_shifted
|vpiRhs:
\_constant: , line:77
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiStmt:
\_assignment: , line:78
|vpiOpType:82
|vpiLhs:
\_ref_obj: (B_shifted), line:78
|vpiName:B_shifted
|vpiFullName:work@div_quick_radix_4.B_shifted
|vpiRhs:
\_constant: , line:78
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiElseStmt:
\_begin: , line:79
|vpiFullName:work@div_quick_radix_4
|vpiStmt:
\_if_else: , line:80
|vpiCondition:
\_ref_obj: (div.start), line:80
|vpiName:div.start
|vpiFullName:work@div_quick_radix_4.div.start
|vpiStmt:
\_begin: , line:80
|vpiFullName:work@div_quick_radix_4
|vpiStmt:
\_assignment: , line:81
|vpiOpType:82
|vpiLhs:
\_ref_obj: (firstCycle), line:81
|vpiName:firstCycle
|vpiFullName:work@div_quick_radix_4.firstCycle
|vpiRhs:
\_constant: , line:81
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiStmt:
\_assignment: , line:82
|vpiOpType:82
|vpiLhs:
\_ref_obj: (A_CLZ_r), line:82
|vpiName:A_CLZ_r
|vpiFullName:work@div_quick_radix_4.A_CLZ_r
|vpiRhs:
\_ref_obj: (A_CLZ), line:82
|vpiName:A_CLZ
|vpiFullName:work@div_quick_radix_4.A_CLZ
|vpiStmt:
\_assignment: , line:83
|vpiOpType:82
|vpiLhs:
\_ref_obj: (B_CLZ_r), line:83
|vpiName:B_CLZ_r
|vpiFullName:work@div_quick_radix_4.B_CLZ_r
|vpiRhs:
\_ref_obj: (B_CLZ), line:83
|vpiName:B_CLZ
|vpiFullName:work@div_quick_radix_4.B_CLZ
|vpiStmt:
\_assignment: , line:84
|vpiOpType:82
|vpiLhs:
\_ref_obj: (greaterDivisor), line:84
|vpiName:greaterDivisor
|vpiFullName:work@div_quick_radix_4.greaterDivisor
|vpiRhs:
\_operation: , line:84
|vpiOpType:18
|vpiOperand:
\_ref_obj: (div.divisor), line:84
|vpiName:div.divisor
|vpiFullName:work@div_quick_radix_4.div.divisor
|vpiOperand:
\_ref_obj: (div.dividend), line:84
|vpiName:div.dividend
|vpiFullName:work@div_quick_radix_4.div.dividend
|vpiStmt:
\_assignment: , line:85
|vpiOpType:82
|vpiLhs:
\_ref_obj: (A_shifted), line:85
|vpiName:A_shifted
|vpiFullName:work@div_quick_radix_4.A_shifted
|vpiRhs:
\_operation: , line:85
|vpiOpType:22
|vpiOperand:
\_ref_obj: (div.dividend), line:85
|vpiName:div.dividend
|vpiFullName:work@div_quick_radix_4.div.dividend
|vpiOperand:
\_ref_obj: (A_CLZ), line:85
|vpiName:A_CLZ
|vpiFullName:work@div_quick_radix_4.A_CLZ
|vpiStmt:
\_assignment: , line:86
|vpiOpType:82
|vpiLhs:
\_ref_obj: (B_shifted), line:86
|vpiName:B_shifted
|vpiFullName:work@div_quick_radix_4.B_shifted
|vpiRhs:
\_operation: , line:86
|vpiOpType:22
|vpiOperand:
\_ref_obj: (div.divisor), line:86
|vpiName:div.divisor
|vpiFullName:work@div_quick_radix_4.div.divisor
|vpiOperand:
\_ref_obj: (A_CLZ), line:86
|vpiName:A_CLZ
|vpiFullName:work@div_quick_radix_4.A_CLZ
|vpiElseStmt:
\_begin: , line:87
|vpiFullName:work@div_quick_radix_4
|vpiStmt:
\_assignment: , line:88
|vpiOpType:82
|vpiLhs:
\_ref_obj: (firstCycle), line:88
|vpiName:firstCycle
|vpiFullName:work@div_quick_radix_4.firstCycle
|vpiRhs:
\_constant: , line:88
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiProcess:
\_always: , line:99
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:99
|vpiCondition:
\_operation: , line:99
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:99
|vpiName:clk
|vpiFullName:work@div_quick_radix_4.clk
|vpiStmt:
\_begin: , line:99
|vpiFullName:work@div_quick_radix_4
|vpiStmt:
\_if_else: , line:100
|vpiCondition:
\_ref_obj: (rst), line:100
|vpiName:rst
|vpiFullName:work@div_quick_radix_4.rst
|vpiStmt:
\_begin: , line:100
|vpiFullName:work@div_quick_radix_4
|vpiStmt:
\_assignment: , line:101
|vpiOpType:82
|vpiLhs:
\_ref_obj: (shift_count), line:101
|vpiName:shift_count
|vpiFullName:work@div_quick_radix_4.shift_count
|vpiRhs:
\_constant: , line:101
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiElseStmt:
\_if_else: , line:102
|vpiCondition:
\_ref_obj: (firstCycle), line:102
|vpiName:firstCycle
|vpiFullName:work@div_quick_radix_4.firstCycle
|vpiStmt:
\_begin: , line:102
|vpiFullName:work@div_quick_radix_4
|vpiStmt:
\_assignment: , line:103
|vpiOpType:82
|vpiLhs:
\_ref_obj: (shift_count), line:103
|vpiName:shift_count
|vpiFullName:work@div_quick_radix_4.shift_count
|vpiRhs:
\_constant: , line:103
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiElseStmt:
\_if_else: , line:104
|vpiCondition:
\_ref_obj: (terminate), line:104
|vpiName:terminate
|vpiFullName:work@div_quick_radix_4.terminate
|vpiStmt:
\_begin: , line:104
|vpiFullName:work@div_quick_radix_4
|vpiStmt:
\_assignment: , line:105
|vpiOpType:82
|vpiLhs:
\_ref_obj: (shift_count), line:105
|vpiName:shift_count
|vpiFullName:work@div_quick_radix_4.shift_count
|vpiRhs:
\_constant: , line:105
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiElseStmt:
\_begin: , line:106
|vpiFullName:work@div_quick_radix_4
|vpiStmt:
\_assignment: , line:107
|vpiOpType:82
|vpiLhs:
\_ref_obj: (shift_count), line:107
|vpiName:shift_count
|vpiFullName:work@div_quick_radix_4.shift_count
|vpiRhs:
\_operation: , line:107
|vpiOpType:33
|vpiOperand:
\_part_select: , line:107, parent:shift_count
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (shift_count)
|vpiLeftRange:
\_constant: , line:107
|vpiConstType:7
|vpiDecompile:14
|vpiSize:32
|INT:14
|vpiRightRange:
\_constant: , line:107
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiOperand:
\_ref_obj: (firstCycle), line:107
|vpiName:firstCycle
|vpiProcess:
\_always: , line:111
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:111
|vpiCondition:
\_operation: , line:111
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:111
|vpiName:clk
|vpiFullName:work@div_quick_radix_4.clk
|vpiStmt:
\_begin: , line:111
|vpiFullName:work@div_quick_radix_4
|vpiStmt:
\_if_else: , line:112
|vpiCondition:
\_ref_obj: (firstCycle), line:112
|vpiName:firstCycle
|vpiFullName:work@div_quick_radix_4.firstCycle
|vpiStmt:
\_begin: , line:112
|vpiFullName:work@div_quick_radix_4
|vpiStmt:
\_assignment: , line:113
|vpiOpType:82
|vpiLhs:
\_ref_obj: (shift_num_R), line:113
|vpiName:shift_num_R
|vpiFullName:work@div_quick_radix_4.shift_num_R
|vpiRhs:
\_constant: , line:113
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiStmt:
\_assignment: , line:114
|vpiOpType:82
|vpiLhs:
\_ref_obj: (shift_num_R_normalized), line:114
|vpiName:shift_num_R_normalized
|vpiFullName:work@div_quick_radix_4.shift_num_R_normalized
|vpiRhs:
\_operation: , line:114
|vpiOpType:24
|vpiOperand:
\_constant: , line:114
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiOperand:
\_operation: , line:114
|vpiOpType:33
|vpiOperand:
\_constant: , line:114
|vpiConstType:3
|vpiDecompile:2'b0
|vpiSize:2
|BIN:2'b0
|vpiOperand:
\_ref_obj: (A_CLZ_r), line:114
|vpiName:A_CLZ_r
|vpiFullName:work@div_quick_radix_4.A_CLZ_r
|vpiStmt:
\_assignment: , line:115
|vpiOpType:82
|vpiLhs:
\_ref_obj: (shift_num_Q), line:115
|vpiName:shift_num_Q
|vpiFullName:work@div_quick_radix_4.shift_num_Q
|vpiRhs:
\_constant: , line:115
|vpiConstType:7
|vpiDecompile:32
|vpiSize:32
|INT:32
|vpiElseStmt:
\_if_stmt: , line:117
|vpiCondition:
\_operation: , line:117
|vpiOpType:28
|vpiOperand:
\_operation: , line:117
|vpiOpType:4
|vpiOperand:
\_ref_obj: (terminate), line:117
|vpiName:terminate
|vpiFullName:work@div_quick_radix_4.terminate
|vpiOperand:
\_operation: , line:117
|vpiOpType:4
|vpiOperand:
\_ref_obj: (terminate_early), line:117
|vpiName:terminate_early
|vpiFullName:work@div_quick_radix_4.terminate_early
|vpiStmt:
\_begin: , line:117
|vpiFullName:work@div_quick_radix_4
|vpiStmt:
\_assignment: , line:118
|vpiOpType:82
|vpiLhs:
\_ref_obj: (shift_num_R), line:118
|vpiName:shift_num_R
|vpiFullName:work@div_quick_radix_4.shift_num_R
|vpiRhs:
\_operation: , line:118
|vpiOpType:24
|vpiOperand:
\_ref_obj: (shift_num_R), line:118
|vpiName:shift_num_R
|vpiFullName:work@div_quick_radix_4.shift_num_R
|vpiOperand:
\_constant: , line:118
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiStmt:
\_assignment: , line:119
|vpiOpType:82
|vpiLhs:
\_ref_obj: (shift_num_R_normalized), line:119
|vpiName:shift_num_R_normalized
|vpiFullName:work@div_quick_radix_4.shift_num_R_normalized
|vpiRhs:
\_operation: , line:119
|vpiOpType:24
|vpiOperand:
\_ref_obj: (shift_num_R_normalized), line:119
|vpiName:shift_num_R_normalized
|vpiFullName:work@div_quick_radix_4.shift_num_R_normalized
|vpiOperand:
\_constant: , line:119
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiStmt:
\_assignment: , line:120
|vpiOpType:82
|vpiLhs:
\_ref_obj: (shift_num_Q), line:120
|vpiName:shift_num_Q
|vpiFullName:work@div_quick_radix_4.shift_num_Q
|vpiRhs:
\_operation: , line:120
|vpiOpType:11
|vpiOperand:
\_ref_obj: (shift_num_Q), line:120
|vpiName:shift_num_Q
|vpiFullName:work@div_quick_radix_4.shift_num_Q
|vpiOperand:
\_constant: , line:120
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiProcess:
\_always: , line:133
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:133
|vpiCondition:
\_operation: , line:133
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:133
|vpiName:clk
|vpiFullName:work@div_quick_radix_4.clk
|vpiStmt:
\_begin: , line:133
|vpiFullName:work@div_quick_radix_4
|vpiStmt:
\_if_else: , line:134
|vpiCondition:
\_ref_obj: (firstCycle), line:134
|vpiName:firstCycle
|vpiFullName:work@div_quick_radix_4.firstCycle
|vpiStmt:
\_begin: , line:134
|vpiFullName:work@div_quick_radix_4
|vpiStmt:
\_assignment: , line:135
|vpiOpType:82
|vpiLhs:
\_ref_obj: (PR), line:135
|vpiName:PR
|vpiFullName:work@div_quick_radix_4.PR
|vpiRhs:
\_operation: , line:135
|vpiOpType:33
|vpiOperand:
\_operation: , line:135
|vpiOpType:34
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:135
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_operation:
|vpiOpType:33
|vpiOperand:
\_constant: , line:135
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiOperand:
\_part_select: , line:135, parent:A_shifted
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (A_shifted)
|vpiLeftRange:
\_operation: , line:135
|vpiOpType:11
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:135
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:135
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_operation: , line:135
|vpiOpType:11
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:135
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:135
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiStmt:
\_assignment: , line:136
|vpiOpType:82
|vpiLhs:
\_ref_obj: (Q_temp), line:136
|vpiName:Q_temp
|vpiFullName:work@div_quick_radix_4.Q_temp
|vpiRhs:
\_constant: , line:136
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiStmt:
\_assignment: , line:137
|vpiOpType:82
|vpiLhs:
\_ref_obj: (AR_r), line:137
|vpiName:AR_r
|vpiFullName:work@div_quick_radix_4.AR_r
|vpiRhs:
\_operation: , line:137
|vpiOpType:33
|vpiOperand:
\_part_select: , line:137, parent:A_shifted
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (A_shifted)
|vpiLeftRange:
\_operation: , line:137
|vpiOpType:11
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:137
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:137
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiRightRange:
\_constant: , line:137
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiOperand:
\_constant: , line:137
|vpiConstType:3
|vpiDecompile:2'b00
|vpiSize:2
|BIN:2'b00
|vpiStmt:
\_assignment: , line:138
|vpiOpType:82
|vpiLhs:
\_ref_obj: (B_shifted_r), line:138
|vpiName:B_shifted_r
|vpiFullName:work@div_quick_radix_4.B_shifted_r
|vpiRhs:
\_ref_obj: (B_shifted), line:138
|vpiName:B_shifted
|vpiFullName:work@div_quick_radix_4.B_shifted
|vpiStmt:
\_assignment: , line:139
|vpiOpType:82
|vpiLhs:
\_ref_obj: (B_1), line:139
|vpiName:B_1
|vpiFullName:work@div_quick_radix_4.B_1
|vpiRhs:
\_operation: , line:139
|vpiOpType:33
|vpiOperand:
\_constant: , line:139
|vpiConstType:3
|vpiDecompile:2'b0
|vpiSize:2
|BIN:2'b0
|vpiOperand:
\_ref_obj: (B_shifted), line:139
|vpiName:B_shifted
|vpiStmt:
\_assignment: , line:140
|vpiOpType:82
|vpiLhs:
\_ref_obj: (B_2), line:140
|vpiName:B_2
|vpiFullName:work@div_quick_radix_4.B_2
|vpiRhs:
\_operation: , line:140
|vpiOpType:33
|vpiOperand:
\_constant: , line:140
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiOperand:
\_ref_obj: (B_shifted), line:140
|vpiName:B_shifted
|vpiOperand:
\_constant: , line:140
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiStmt:
\_assignment: , line:141
|vpiOpType:82
|vpiLhs:
\_ref_obj: (B_3), line:141
|vpiName:B_3
|vpiFullName:work@div_quick_radix_4.B_3
|vpiRhs:
\_operation: , line:141
|vpiOpType:24
|vpiOperand:
\_operation: , line:141
|vpiOpType:33
|vpiOperand:
\_constant: , line:141
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiOperand:
\_ref_obj: (B_shifted), line:141
|vpiName:B_shifted
|vpiOperand:
\_constant: , line:141
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiOperand:
\_operation: , line:141
|vpiOpType:33
|vpiOperand:
\_constant: , line:141
|vpiConstType:3
|vpiDecompile:2'b0
|vpiSize:2
|BIN:2'b0
|vpiOperand:
\_ref_obj: (B_shifted), line:141
|vpiName:B_shifted
|vpiFullName:work@div_quick_radix_4.B_shifted
|vpiElseStmt:
\_if_stmt: , line:142
|vpiCondition:
\_operation: , line:142
|vpiOpType:28
|vpiOperand:
\_operation: , line:142
|vpiOpType:4
|vpiOperand:
\_ref_obj: (terminate), line:142
|vpiName:terminate
|vpiFullName:work@div_quick_radix_4.terminate
|vpiOperand:
\_operation: , line:142
|vpiOpType:4
|vpiOperand:
\_ref_obj: (terminate_early), line:142
|vpiName:terminate_early
|vpiFullName:work@div_quick_radix_4.terminate_early
|vpiStmt:
\_begin: , line:142
|vpiFullName:work@div_quick_radix_4
|vpiStmt:
\_assignment: , line:143
|vpiOpType:82
|vpiLhs:
\_ref_obj: (AR_r), line:143
|vpiName:AR_r
|vpiFullName:work@div_quick_radix_4.AR_r
|vpiRhs:
\_operation: , line:143
|vpiOpType:33
|vpiOperand:
\_part_select: , line:143, parent:AR_r
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (AR_r)
|vpiLeftRange:
\_operation: , line:143
|vpiOpType:11
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:143
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:143
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiRightRange:
\_constant: , line:143
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiOperand:
\_constant: , line:143
|vpiConstType:3
|vpiDecompile:2'b00
|vpiSize:2
|BIN:2'b00
|vpiStmt:
\_case_stmt: , line:144
|vpiCaseType:1
|vpiCondition:
\_ref_obj: (new_PR_sign), line:144
|vpiName:new_PR_sign
|vpiFullName:work@div_quick_radix_4.new_PR_sign
|vpiCaseItem:
\_case_item: , line:145
|vpiExpr:
\_constant: , line:145
|vpiConstType:3
|vpiDecompile:3'b111
|vpiSize:3
|BIN:3'b111
|vpiStmt:
\_begin: , line:145
|vpiFullName:work@div_quick_radix_4
|vpiStmt:
\_assignment: , line:146
|vpiOpType:82
|vpiLhs:
\_ref_obj: (PR), line:146
|vpiName:PR
|vpiFullName:work@div_quick_radix_4.PR
|vpiRhs:
\_operation: , line:146
|vpiOpType:33
|vpiOperand:
\_part_select: , line:146, parent:PR
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (PR)
|vpiLeftRange:
\_operation: , line:146
|vpiOpType:11
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:146
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:146
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:146
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiOperand:
\_part_select: , line:146, parent:AR_r
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (AR_r)
|vpiLeftRange:
\_operation: , line:146
|vpiOpType:11
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:146
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:146
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_operation: , line:146
|vpiOpType:11
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:146
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:146
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiStmt:
\_assignment: , line:147
|vpiOpType:82
|vpiLhs:
\_ref_obj: (Q_temp), line:147
|vpiName:Q_temp
|vpiFullName:work@div_quick_radix_4.Q_temp
|vpiRhs:
\_operation: , line:147
|vpiOpType:33
|vpiOperand:
\_ref_obj: (div.quotient), line:147
|vpiName:div.quotient
|vpiOperand:
\_constant: , line:147
|vpiConstType:3
|vpiDecompile:2'b00
|vpiSize:2
|BIN:2'b00
|vpiCaseItem:
\_case_item: , line:149
|vpiExpr:
\_constant: , line:149
|vpiConstType:3
|vpiDecompile:3'b110
|vpiSize:3
|BIN:3'b110
|vpiStmt:
\_begin: , line:149
|vpiFullName:work@div_quick_radix_4
|vpiStmt:
\_assignment: , line:150
|vpiOpType:82
|vpiLhs:
\_ref_obj: (PR), line:150
|vpiName:PR
|vpiFullName:work@div_quick_radix_4.PR
|vpiRhs:
\_operation: , line:150
|vpiOpType:33
|vpiOperand:
\_part_select: , line:150, parent:new_PR_1
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (new_PR_1)
|vpiLeftRange:
\_operation: , line:150
|vpiOpType:11
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:150
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:150
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:150
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiOperand:
\_part_select: , line:150, parent:AR_r
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (AR_r)
|vpiLeftRange:
\_operation: , line:150
|vpiOpType:11
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:150
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:150
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_operation: , line:150
|vpiOpType:11
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:150
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:150
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiStmt:
\_assignment: , line:151
|vpiOpType:82
|vpiLhs:
\_ref_obj: (Q_temp), line:151
|vpiName:Q_temp
|vpiFullName:work@div_quick_radix_4.Q_temp
|vpiRhs:
\_operation: , line:151
|vpiOpType:33
|vpiOperand:
\_ref_obj: (div.quotient), line:151
|vpiName:div.quotient
|vpiOperand:
\_constant: , line:151
|vpiConstType:3
|vpiDecompile:2'b01
|vpiSize:2
|BIN:2'b01
|vpiCaseItem:
\_case_item: , line:153
|vpiExpr:
\_constant: , line:153
|vpiConstType:3
|vpiDecompile:3'b100
|vpiSize:3
|BIN:3'b100
|vpiStmt:
\_begin: , line:153
|vpiFullName:work@div_quick_radix_4
|vpiStmt:
\_assignment: , line:154
|vpiOpType:82
|vpiLhs:
\_ref_obj: (PR), line:154
|vpiName:PR
|vpiFullName:work@div_quick_radix_4.PR
|vpiRhs:
\_operation: , line:154
|vpiOpType:33
|vpiOperand:
\_part_select: , line:154, parent:new_PR_2
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (new_PR_2)
|vpiLeftRange:
\_operation: , line:154
|vpiOpType:11
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:154
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:154
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:154
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiOperand:
\_part_select: , line:154, parent:AR_r
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (AR_r)
|vpiLeftRange:
\_operation: , line:154
|vpiOpType:11
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:154
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:154
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_operation: , line:154
|vpiOpType:11
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:154
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:154
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiStmt:
\_assignment: , line:155
|vpiOpType:82
|vpiLhs:
\_ref_obj: (Q_temp), line:155
|vpiName:Q_temp
|vpiFullName:work@div_quick_radix_4.Q_temp
|vpiRhs:
\_operation: , line:155
|vpiOpType:33
|vpiOperand:
\_ref_obj: (div.quotient), line:155
|vpiName:div.quotient
|vpiOperand:
\_constant: , line:155
|vpiConstType:3
|vpiDecompile:2'b10
|vpiSize:2
|BIN:2'b10
|vpiCaseItem:
\_case_item: , line:157
|vpiStmt:
\_begin: , line:157
|vpiFullName:work@div_quick_radix_4
|vpiStmt:
\_assignment: , line:158
|vpiOpType:82
|vpiLhs:
\_ref_obj: (PR), line:158
|vpiName:PR
|vpiFullName:work@div_quick_radix_4.PR
|vpiRhs:
\_operation: , line:158
|vpiOpType:33
|vpiOperand:
\_part_select: , line:158, parent:new_PR_3
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (new_PR_3)
|vpiLeftRange:
\_operation: , line:158
|vpiOpType:11
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:158
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:158
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:158
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiOperand:
\_part_select: , line:158, parent:AR_r
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (AR_r)
|vpiLeftRange:
\_operation: , line:158
|vpiOpType:11
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:158
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:158
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_operation: , line:158
|vpiOpType:11
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:158
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:158
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiStmt:
\_assignment: , line:159
|vpiOpType:82
|vpiLhs:
\_ref_obj: (Q_temp), line:159
|vpiName:Q_temp
|vpiFullName:work@div_quick_radix_4.Q_temp
|vpiRhs:
\_operation: , line:159
|vpiOpType:33
|vpiOperand:
\_ref_obj: (div.quotient), line:159
|vpiName:div.quotient
|vpiOperand:
\_constant: , line:159
|vpiConstType:3
|vpiDecompile:2'b11
|vpiSize:2
|BIN:2'b11
|vpiProcess:
\_always: , line:165
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:165
|vpiCondition:
\_operation: , line:165
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:165
|vpiName:clk
|vpiFullName:work@div_quick_radix_4.clk
|vpiStmt:
\_begin: , line:165
|vpiFullName:work@div_quick_radix_4
|vpiStmt:
\_if_else: , line:166
|vpiCondition:
\_ref_obj: (div.start), line:166
|vpiName:div.start
|vpiFullName:work@div_quick_radix_4.div.start
|vpiStmt:
\_assignment: , line:167
|vpiOpType:82
|vpiLhs:
\_ref_obj: (div.divisor_is_zero), line:167
|vpiName:div.divisor_is_zero
|vpiFullName:work@div_quick_radix_4.div.divisor_is_zero
|vpiRhs:
\_operation: , line:167
|vpiOpType:4
|vpiOperand:
\_operation: , line:167
|vpiOpType:7
|vpiOperand:
\_ref_obj: (div.divisor), line:167
|vpiName:div.divisor
|vpiFullName:work@div_quick_radix_4.div.divisor
|vpiElseStmt:
\_if_stmt: , line:168
|vpiCondition:
\_operation: , line:168
|vpiOpType:28
|vpiOperand:
\_operation: , line:168
|vpiOpType:4
|vpiOperand:
\_ref_obj: (terminate), line:168
|vpiName:terminate
|vpiFullName:work@div_quick_radix_4.terminate
|vpiOperand:
\_operation: , line:168
|vpiOpType:4
|vpiOperand:
\_ref_obj: (terminate_early), line:168
|vpiName:terminate_early
|vpiFullName:work@div_quick_radix_4.terminate_early
|vpiStmt:
\_assignment: , line:169
|vpiOpType:82
|vpiLhs:
\_ref_obj: (div.divisor_is_zero), line:169
|vpiName:div.divisor_is_zero
|vpiFullName:work@div_quick_radix_4.div.divisor_is_zero
|vpiRhs:
\_operation: , line:169
|vpiOpType:28
|vpiOperand:
\_ref_obj: (div.divisor_is_zero), line:169
|vpiName:div.divisor_is_zero
|vpiFullName:work@div_quick_radix_4.div.divisor_is_zero
|vpiOperand:
\_operation: , line:169
|vpiOpType:4
|vpiOperand:
\_operation: , line:169
|vpiOpType:7
|vpiOperand:
\_ref_obj: (new_PR_sign), line:169
|vpiName:new_PR_sign
|vpiFullName:work@div_quick_radix_4.new_PR_sign
|vpiProcess:
\_always: , line:172
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:172
|vpiCondition:
\_operation: , line:172
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:172
|vpiName:clk
|vpiFullName:work@div_quick_radix_4.clk
|vpiStmt:
\_begin: , line:172
|vpiFullName:work@div_quick_radix_4
|vpiStmt:
\_if_else: , line:173
|vpiCondition:
\_ref_obj: (rst), line:173
|vpiName:rst
|vpiFullName:work@div_quick_radix_4.rst
|vpiStmt:
\_assignment: , line:174
|vpiOpType:82
|vpiLhs:
\_ref_obj: (terminate), line:174
|vpiName:terminate
|vpiFullName:work@div_quick_radix_4.terminate
|vpiRhs:
\_constant: , line:174
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiElseStmt:
\_begin: , line:175
|vpiFullName:work@div_quick_radix_4
|vpiStmt:
\_if_else: , line:176
|vpiCondition:
\_ref_obj: (firstCycle), line:176
|vpiName:firstCycle
|vpiFullName:work@div_quick_radix_4.firstCycle
|vpiStmt:
\_assignment: , line:177
|vpiOpType:82
|vpiLhs:
\_ref_obj: (terminate), line:177
|vpiName:terminate
|vpiFullName:work@div_quick_radix_4.terminate
|vpiRhs:
\_constant: , line:177
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiElseStmt:
\_if_stmt: , line:178
|vpiCondition:
\_operation: , line:178
|vpiOpType:29
|vpiOperand:
\_bit_select: (shift_count), line:178
|vpiName:shift_count
|vpiFullName:work@div_quick_radix_4.shift_count
|vpiIndex:
\_constant: , line:178
|vpiConstType:7
|vpiDecompile:15
|vpiSize:32
|INT:15
|vpiOperand:
\_ref_obj: (terminate_early), line:178
|vpiName:terminate_early
|vpiFullName:work@div_quick_radix_4.terminate_early
|vpiStmt:
\_assignment: , line:179
|vpiOpType:82
|vpiLhs:
\_ref_obj: (terminate), line:179
|vpiName:terminate
|vpiFullName:work@div_quick_radix_4.terminate
|vpiRhs:
\_constant: , line:179
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiProcess:
\_always: , line:183
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:183
|vpiCondition:
\_operation: , line:183
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:183
|vpiName:clk
|vpiFullName:work@div_quick_radix_4.clk
|vpiStmt:
\_begin: , line:183
|vpiFullName:work@div_quick_radix_4
|vpiStmt:
\_if_else: , line:184
|vpiCondition:
\_ref_obj: (rst), line:184
|vpiName:rst
|vpiFullName:work@div_quick_radix_4.rst
|vpiStmt:
\_assignment: , line:185
|vpiOpType:82
|vpiLhs:
\_ref_obj: (div.done), line:185
|vpiName:div.done
|vpiFullName:work@div_quick_radix_4.div.done
|vpiRhs:
\_constant: , line:185
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiElseStmt:
\_begin: , line:186
|vpiFullName:work@div_quick_radix_4
|vpiStmt:
\_if_else: , line:187
|vpiCondition:
\_ref_obj: (firstCycle), line:187
|vpiName:firstCycle
|vpiFullName:work@div_quick_radix_4.firstCycle
|vpiStmt:
\_assignment: , line:188
|vpiOpType:82
|vpiLhs:
\_ref_obj: (div.done), line:188
|vpiName:div.done
|vpiFullName:work@div_quick_radix_4.div.done
|vpiRhs:
\_constant: , line:188
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiElseStmt:
\_if_else: , line:189
|vpiCondition:
\_operation: , line:189
|vpiOpType:28
|vpiOperand:
\_operation: , line:189
|vpiOpType:28
|vpiOperand:
\_operation: , line:189
|vpiOpType:29
|vpiOperand:
\_bit_select: (shift_count), line:189
|vpiName:shift_count
|vpiFullName:work@div_quick_radix_4.shift_count
|vpiIndex:
\_constant: , line:189
|vpiConstType:7
|vpiDecompile:15
|vpiSize:32
|INT:15
|vpiOperand:
\_ref_obj: (terminate_early), line:189
|vpiName:terminate_early
|vpiFullName:work@div_quick_radix_4.terminate_early
|vpiOperand:
\_operation: , line:189
|vpiOpType:4
|vpiOperand:
\_ref_obj: (div.done), line:189
|vpiName:div.done
|vpiFullName:work@div_quick_radix_4.div.done
|vpiOperand:
\_operation: , line:189
|vpiOpType:4
|vpiOperand:
\_ref_obj: (terminate), line:189
|vpiName:terminate
|vpiFullName:work@div_quick_radix_4.terminate
|vpiStmt:
\_assignment: , line:190
|vpiOpType:82
|vpiLhs:
\_ref_obj: (div.done), line:190
|vpiName:div.done
|vpiFullName:work@div_quick_radix_4.div.done
|vpiRhs:
\_constant: , line:190
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiElseStmt:
\_if_stmt: , line:191
|vpiCondition:
\_ref_obj: (div.done), line:191
|vpiName:div.done
|vpiFullName:work@div_quick_radix_4.div.done
|vpiStmt:
\_assignment: , line:192
|vpiOpType:82
|vpiLhs:
\_ref_obj: (div.done), line:192
|vpiName:div.done
|vpiFullName:work@div_quick_radix_4.div.done
|vpiRhs:
\_constant: , line:192
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiPort:
\_port: (clk), line:27
|vpiName:clk
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (clk), line:27
|vpiName:clk
|vpiFullName:work@div_quick_radix_4.clk
|vpiNetType:36
|vpiPort:
\_port: (rst), line:28
|vpiName:rst
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (rst), line:28
|vpiName:rst
|vpiFullName:work@div_quick_radix_4.rst
|vpiNetType:36
|vpiPort:
\_port: (div), line:29
|vpiName:div
|vpiDirection:5
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_modport: (divider)
|vpiContAssign:
\_cont_assign: , line:93
|vpiRhs:
\_operation: , line:93
|vpiOpType:11
|vpiOperand:
\_operation: , line:93
|vpiOpType:33
|vpiOperand:
\_constant: , line:93
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiOperand:
\_ref_obj: (PR), line:93
|vpiName:PR
|vpiOperand:
\_operation: , line:93
|vpiOpType:33
|vpiOperand:
\_constant: , line:93
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiOperand:
\_ref_obj: (B_1), line:93
|vpiName:B_1
|vpiFullName:work@div_quick_radix_4.B_1
|vpiLhs:
\_ref_obj: (new_PR_1), line:93
|vpiName:new_PR_1
|vpiFullName:work@div_quick_radix_4.new_PR_1
|vpiContAssign:
\_cont_assign: , line:94
|vpiRhs:
\_operation: , line:94
|vpiOpType:11
|vpiOperand:
\_operation: , line:94
|vpiOpType:33
|vpiOperand:
\_constant: , line:94
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiOperand:
\_ref_obj: (PR), line:94
|vpiName:PR
|vpiOperand:
\_operation: , line:94
|vpiOpType:33
|vpiOperand:
\_constant: , line:94
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiOperand:
\_ref_obj: (B_2), line:94
|vpiName:B_2
|vpiFullName:work@div_quick_radix_4.B_2
|vpiLhs:
\_ref_obj: (new_PR_2), line:94
|vpiName:new_PR_2
|vpiFullName:work@div_quick_radix_4.new_PR_2
|vpiContAssign:
\_cont_assign: , line:95
|vpiRhs:
\_operation: , line:95
|vpiOpType:11
|vpiOperand:
\_operation: , line:95
|vpiOpType:33
|vpiOperand:
\_constant: , line:95
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiOperand:
\_ref_obj: (PR), line:95
|vpiName:PR
|vpiOperand:
\_operation: , line:95
|vpiOpType:33
|vpiOperand:
\_constant: , line:95
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiOperand:
\_ref_obj: (B_3), line:95
|vpiName:B_3
|vpiFullName:work@div_quick_radix_4.B_3
|vpiLhs:
\_ref_obj: (new_PR_3), line:95
|vpiName:new_PR_3
|vpiFullName:work@div_quick_radix_4.new_PR_3
|vpiContAssign:
\_cont_assign: , line:96
|vpiRhs:
\_operation: , line:96
|vpiOpType:33
|vpiOperand:
\_bit_select: (new_PR_3), line:96
|vpiName:new_PR_3
|vpiIndex:
\_operation: , line:96
|vpiOpType:24
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:96
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:96
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiOperand:
\_bit_select: (new_PR_2), line:96
|vpiName:new_PR_2
|vpiIndex:
\_operation: , line:96
|vpiOpType:24
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:96
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:96
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiOperand:
\_bit_select: (new_PR_1), line:96
|vpiName:new_PR_1
|vpiIndex:
\_operation: , line:96
|vpiOpType:24
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:96
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:96
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiLhs:
\_ref_obj: (new_PR_sign), line:96
|vpiName:new_PR_sign
|vpiFullName:work@div_quick_radix_4.new_PR_sign
|vpiContAssign:
\_cont_assign: , line:124
|vpiRhs:
\_operation: , line:124
|vpiOpType:23
|vpiOperand:
\_operation: , line:124
|vpiOpType:33
|vpiOperand:
\_ref_obj: (PR), line:124
|vpiName:PR
|vpiOperand:
\_ref_obj: (AR_r), line:124
|vpiName:AR_r
|vpiOperand:
\_ref_obj: (shift_num_R_normalized), line:124
|vpiName:shift_num_R_normalized
|vpiFullName:work@div_quick_radix_4.shift_num_R_normalized
|vpiLhs:
\_ref_obj: (combined_normalized), line:124
|vpiName:combined_normalized
|vpiFullName:work@div_quick_radix_4.combined_normalized
|vpiContAssign:
\_cont_assign: , line:125
|vpiRhs:
\_part_select: , line:125, parent:combined_normalized
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (combined_normalized)
|vpiLeftRange:
\_operation: , line:125
|vpiOpType:11
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:125
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:125
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:125
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiLhs:
\_ref_obj: (div.remainder), line:125
|vpiName:div.remainder
|vpiFullName:work@div_quick_radix_4.div.remainder
|vpiContAssign:
\_cont_assign: , line:127
|vpiRhs:
\_operation: , line:127
|vpiOpType:23
|vpiOperand:
\_operation: , line:127
|vpiOpType:33
|vpiOperand:
\_ref_obj: (PR), line:127
|vpiName:PR
|vpiOperand:
\_ref_obj: (AR_r), line:127
|vpiName:AR_r
|vpiOperand:
\_ref_obj: (shift_num_R), line:127
|vpiName:shift_num_R
|vpiFullName:work@div_quick_radix_4.shift_num_R
|vpiLhs:
\_ref_obj: (combined), line:127
|vpiName:combined
|vpiFullName:work@div_quick_radix_4.combined
|vpiContAssign:
\_cont_assign: , line:128
|vpiRhs:
\_part_select: , line:128, parent:combined
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (combined)
|vpiLeftRange:
\_operation: , line:128
|vpiOpType:11
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:128
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:128
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:128
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiLhs:
\_ref_obj: (R_shifted), line:128
|vpiName:R_shifted
|vpiFullName:work@div_quick_radix_4.R_shifted
|vpiContAssign:
\_cont_assign: , line:130
|vpiRhs:
\_operation: , line:130
|vpiOpType:28
|vpiOperand:
\_operation: , line:130
|vpiOpType:4
|vpiOperand:
\_ref_obj: (firstCycle), line:130
|vpiName:firstCycle
|vpiFullName:work@div_quick_radix_4.firstCycle
|vpiOperand:
\_operation: , line:130
|vpiOpType:29
|vpiOperand:
\_operation: , line:130
|vpiOpType:18
|vpiOperand:
\_ref_obj: (B_shifted_r), line:130
|vpiName:B_shifted_r
|vpiFullName:work@div_quick_radix_4.B_shifted_r
|vpiOperand:
\_ref_obj: (R_shifted), line:130
|vpiName:R_shifted
|vpiFullName:work@div_quick_radix_4.R_shifted
|vpiOperand:
\_ref_obj: (greaterDivisor), line:130
|vpiName:greaterDivisor
|vpiFullName:work@div_quick_radix_4.greaterDivisor
|vpiLhs:
\_ref_obj: (terminate_early), line:130
|vpiName:terminate_early
|vpiFullName:work@div_quick_radix_4.terminate_early
|vpiContAssign:
\_cont_assign: , line:131
|vpiRhs:
\_operation: , line:131
|vpiOpType:32
|vpiOperand:
\_ref_obj: (terminate_early), line:131
|vpiName:terminate_early
|vpiFullName:work@div_quick_radix_4.terminate_early
|vpiOperand:
\_operation: , line:131
|vpiOpType:22
|vpiOperand:
\_ref_obj: (Q_temp), line:131
|vpiName:Q_temp
|vpiFullName:work@div_quick_radix_4.Q_temp
|vpiOperand:
\_ref_obj: (shift_num_Q), line:131
|vpiName:shift_num_Q
|vpiFullName:work@div_quick_radix_4.shift_num_Q
|vpiOperand:
\_ref_obj: (Q_temp), line:131
|vpiName:Q_temp
|vpiFullName:work@div_quick_radix_4.Q_temp
|vpiLhs:
\_ref_obj: (div.quotient), line:131
|vpiName:div.quotient
|vpiFullName:work@div_quick_radix_4.div.quotient
|vpiNet:
\_logic_net: (clk), line:27
|vpiNet:
\_logic_net: (rst), line:28
|vpiNet:
\_logic_net: (terminate), line:32
|vpiName:terminate
|vpiFullName:work@div_quick_radix_4.terminate
|vpiNetType:36
|vpiNet:
\_logic_net: (shift_count), line:33
|vpiName:shift_count
|vpiFullName:work@div_quick_radix_4.shift_count
|vpiNetType:36
|vpiNet:
\_logic_net: (PR), line:35
|vpiName:PR
|vpiFullName:work@div_quick_radix_4.PR
|vpiNetType:36
|vpiNet:
\_logic_net: (new_PR_sign), line:36
|vpiName:new_PR_sign
|vpiFullName:work@div_quick_radix_4.new_PR_sign
|vpiNetType:36
|vpiNet:
\_logic_net: (new_PR_1), line:37
|vpiName:new_PR_1
|vpiFullName:work@div_quick_radix_4.new_PR_1
|vpiNetType:36
|vpiNet:
\_logic_net: (new_PR_2), line:38
|vpiName:new_PR_2
|vpiFullName:work@div_quick_radix_4.new_PR_2
|vpiNetType:36
|vpiNet:
\_logic_net: (new_PR_3), line:39
|vpiName:new_PR_3
|vpiFullName:work@div_quick_radix_4.new_PR_3
|vpiNetType:36
|vpiNet:
\_logic_net: (B_1), line:40
|vpiName:B_1
|vpiFullName:work@div_quick_radix_4.B_1
|vpiNetType:36
|vpiNet:
\_logic_net: (B_2), line:41
|vpiName:B_2
|vpiFullName:work@div_quick_radix_4.B_2
|vpiNetType:36
|vpiNet:
\_logic_net: (B_3), line:42
|vpiName:B_3
|vpiFullName:work@div_quick_radix_4.B_3
|vpiNetType:36
|vpiNet:
\_logic_net: (AR_r), line:44
|vpiName:AR_r
|vpiFullName:work@div_quick_radix_4.AR_r
|vpiNetType:36
|vpiNet:
\_logic_net: (Q_temp), line:45
|vpiName:Q_temp
|vpiFullName:work@div_quick_radix_4.Q_temp
|vpiNetType:36
|vpiNet:
\_logic_net: (shift_num_R), line:46
|vpiName:shift_num_R
|vpiFullName:work@div_quick_radix_4.shift_num_R
|vpiNetType:36
|vpiNet:
\_logic_net: (shift_num_R_normalized), line:47
|vpiName:shift_num_R_normalized
|vpiFullName:work@div_quick_radix_4.shift_num_R_normalized
|vpiNetType:36
|vpiNet:
\_logic_net: (shift_num_Q), line:48
|vpiName:shift_num_Q
|vpiFullName:work@div_quick_radix_4.shift_num_Q
|vpiNetType:36
|vpiNet:
\_logic_net: (combined), line:49
|vpiName:combined
|vpiFullName:work@div_quick_radix_4.combined
|vpiNetType:36
|vpiNet:
\_logic_net: (combined_normalized), line:50
|vpiName:combined_normalized
|vpiFullName:work@div_quick_radix_4.combined_normalized
|vpiNetType:36
|vpiNet:
\_logic_net: (terminate_early), line:51
|vpiName:terminate_early
|vpiFullName:work@div_quick_radix_4.terminate_early
|vpiNetType:36
|vpiNet:
\_logic_net: (A_CLZ), line:54
|vpiName:A_CLZ
|vpiFullName:work@div_quick_radix_4.A_CLZ
|vpiNetType:36
|vpiNet:
\_logic_net: (B_CLZ), line:55
|vpiName:B_CLZ
|vpiFullName:work@div_quick_radix_4.B_CLZ
|vpiNetType:36
|vpiNet:
\_logic_net: (A_CLZ_r), line:56
|vpiName:A_CLZ_r
|vpiFullName:work@div_quick_radix_4.A_CLZ_r
|vpiNetType:36
|vpiNet:
\_logic_net: (B_CLZ_r), line:57
|vpiName:B_CLZ_r
|vpiFullName:work@div_quick_radix_4.B_CLZ_r
|vpiNetType:36
|vpiNet:
\_logic_net: (CLZ_delta), line:58
|vpiName:CLZ_delta
|vpiFullName:work@div_quick_radix_4.CLZ_delta
|vpiNetType:36
|vpiNet:
\_logic_net: (firstCycle), line:60
|vpiName:firstCycle
|vpiFullName:work@div_quick_radix_4.firstCycle
|vpiNetType:36
|vpiNet:
\_logic_net: (greaterDivisor), line:61
|vpiName:greaterDivisor
|vpiFullName:work@div_quick_radix_4.greaterDivisor
|vpiNetType:36
|vpiNet:
\_logic_net: (A_shifted), line:62
|vpiName:A_shifted
|vpiFullName:work@div_quick_radix_4.A_shifted
|vpiNetType:36
|vpiNet:
\_logic_net: (B_shifted), line:63
|vpiName:B_shifted
|vpiFullName:work@div_quick_radix_4.B_shifted
|vpiNetType:36
|vpiNet:
\_logic_net: (R_shifted), line:64
|vpiName:R_shifted
|vpiFullName:work@div_quick_radix_4.R_shifted
|vpiNetType:36
|vpiNet:
\_logic_net: (B_shifted_r), line:65
|vpiName:B_shifted_r
|vpiFullName:work@div_quick_radix_4.B_shifted_r
|vpiNetType:36
|vpiNet:
\_logic_net: (div), line:29
|vpiName:div
|vpiFullName:work@div_quick_radix_4.div
|vpiParamAssign:
\_param_assign: , line:53
|vpiRhs:
\_sys_func_call: ($clog2), line:53
|vpiName:$clog2
|vpiArgument:
\_ref_obj: (div.DATA_WIDTH), line:53
|vpiName:div.DATA_WIDTH
|vpiLhs:
\_parameter: (CLZ_W), line:53
|vpiName:CLZ_W
|vpiLocalParam:1
|vpiParameter:
\_parameter: (CLZ_W), line:53
|uhdmallModules:
\_module: work@div_radix16, file:third_party/cores/taiga/core/div_algorithms/div_radix16.sv, line:25, parent:work@div_unit_core_wrapper
|vpiDefName:work@div_radix16
|vpiFullName:work@div_radix16
|vpiProcess:
\_always: , line:53
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:53
|vpiCondition:
\_operation: , line:53
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:53
|vpiName:clk
|vpiFullName:work@div_radix16.clk
|vpiStmt:
\_begin: , line:53
|vpiFullName:work@div_radix16
|vpiStmt:
\_assignment: , line:54
|vpiOpType:82
|vpiLhs:
\_bit_select: (shift_count), line:54
|vpiName:shift_count
|vpiFullName:work@div_radix16.shift_count
|vpiIndex:
\_constant: , line:54
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiRhs:
\_ref_obj: (div.start), line:54
|vpiName:div.start
|vpiFullName:work@div_radix16.div.start
|vpiStmt:
\_assignment: , line:55
|vpiOpType:82
|vpiLhs:
\_part_select: , line:55, parent:shift_count
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (shift_count)
|vpiLeftRange:
\_constant: , line:55
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:55
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRhs:
\_part_select: , line:55, parent:shift_count
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (shift_count)
|vpiLeftRange:
\_constant: , line:55
|vpiConstType:7
|vpiDecompile:30
|vpiSize:32
|INT:30
|vpiRightRange:
\_constant: , line:55
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiProcess:
\_always: , line:71
|vpiAlwaysType:2
|vpiStmt:
\_begin: , line:71
|vpiFullName:work@div_radix16
|vpiStmt:
\_assignment: , line:72
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (PR_lower), line:72
|vpiName:PR_lower
|vpiFullName:work@div_radix16.PR_lower
|vpiRhs:
\_operation: , line:72
|vpiOpType:28
|vpiOperand:
\_operation: , line:72
|vpiOpType:33
|vpiOperand:
\_part_select: , line:72, parent:PR
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (PR)
|vpiLeftRange:
\_operation: , line:72
|vpiOpType:11
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:72
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:72
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:72
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiOperand:
\_ref_obj: (div.quotient), line:72
|vpiName:div.quotient
|vpiOperand:
\_operation: , line:72
|vpiOpType:34
|vpiOperand:
\_operation: , line:72
|vpiOpType:24
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:72
|vpiName:div.DATA_WIDTH
|vpiFullName:work@div_radix16.div.DATA_WIDTH
|vpiOperand:
\_constant: , line:72
|vpiConstType:7
|vpiDecompile:4
|vpiSize:32
|INT:4
|vpiOperand:
\_operation:
|vpiOpType:33
|vpiOperand:
\_bit_select: (new_PR_sign), line:72
|vpiName:new_PR_sign
|vpiIndex:
\_constant: , line:72
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiStmt:
\_assignment: , line:73
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (Q_lower), line:73
|vpiName:Q_lower
|vpiFullName:work@div_radix16.Q_lower
|vpiRhs:
\_operation: , line:73
|vpiOpType:28
|vpiOperand:
\_operation: , line:73
|vpiOpType:33
|vpiOperand:
\_ref_obj: (div.quotient), line:73
|vpiName:div.quotient
|vpiOperand:
\_constant: , line:73
|vpiConstType:3
|vpiDecompile:4'b0000
|vpiSize:4
|BIN:4'b0000
|vpiOperand:
\_operation: , line:73
|vpiOpType:34
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:73
|vpiName:div.DATA_WIDTH
|vpiFullName:work@div_radix16.div.DATA_WIDTH
|vpiOperand:
\_operation:
|vpiOpType:33
|vpiOperand:
\_bit_select: (new_PR_sign), line:73
|vpiName:new_PR_sign
|vpiIndex:
\_constant: , line:73
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiStmt:
\_for_stmt: , line:74
|vpiFullName:work@div_radix16
|vpiCondition:
\_operation: , line:74
|vpiOpType:20
|vpiOperand:
\_ref_obj: (i), line:74
|vpiName:i
|vpiFullName:work@div_radix16.i
|vpiOperand:
\_constant: , line:74
|vpiConstType:7
|vpiDecompile:7
|vpiSize:32
|INT:7
|vpiForInitStmt:
\_assign_stmt:
|vpiRhs:
\_constant: , line:74
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiLhs:
\_int_var: (i), line:74
|vpiName:i
|vpiFullName:work@div_radix16.i
|vpiForIncStmt:
\_operation: , line:74
|vpiOpType:82
|vpiOperand:
\_ref_obj: (i), line:74
|vpiName:i
|vpiStmt:
\_begin: , line:74
|vpiFullName:work@div_radix16
|vpiStmt:
\_assignment: , line:75
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (PR_lower), line:75
|vpiName:PR_lower
|vpiFullName:work@div_radix16.PR_lower
|vpiRhs:
\_operation: , line:75
|vpiOpType:29
|vpiOperand:
\_ref_obj: (PR_lower), line:75
|vpiName:PR_lower
|vpiFullName:work@div_radix16.PR_lower
|vpiOperand:
\_operation: , line:75
|vpiOpType:28
|vpiOperand:
\_operation: , line:75
|vpiOpType:33
|vpiOperand:
\_var_select: (new_PR), line:75
|vpiName:new_PR
|vpiIndex:
\_operation: , line:75
|vpiOpType:11
|vpiOperand:
\_ref_obj: (i), line:75
|vpiName:i
|vpiFullName:work@div_radix16.i
|vpiOperand:
\_constant: , line:75
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiIndex:
\_part_select: , parent:new_PR
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (new_PR)
|vpiLeftRange:
\_operation: , line:75
|vpiOpType:11
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:75
|vpiName:div.DATA_WIDTH
|vpiFullName:work@div_radix16.div.DATA_WIDTH
|vpiOperand:
\_constant: , line:75
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:75
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiOperand:
\_ref_obj: (div.quotient), line:75
|vpiName:div.quotient
|vpiFullName:work@div_radix16.div.quotient
|vpiOperand:
\_operation: , line:75
|vpiOpType:34
|vpiOperand:
\_operation: , line:75
|vpiOpType:24
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:75
|vpiName:div.DATA_WIDTH
|vpiFullName:work@div_radix16.div.DATA_WIDTH
|vpiOperand:
\_constant: , line:75
|vpiConstType:7
|vpiDecompile:4
|vpiSize:32
|INT:4
|vpiOperand:
\_operation:
|vpiOpType:33
|vpiOperand:
\_operation: , line:75
|vpiOpType:28
|vpiOperand:
\_operation: , line:75
|vpiOpType:4
|vpiOperand:
\_bit_select: (new_PR_sign), line:75
|vpiName:new_PR_sign
|vpiIndex:
\_operation: , line:75
|vpiOpType:11
|vpiOperand:
\_ref_obj: (i), line:75
|vpiName:i
|vpiFullName:work@div_radix16.i
|vpiOperand:
\_constant: , line:75
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiOperand:
\_bit_select: (new_PR_sign), line:75
|vpiName:new_PR_sign
|vpiFullName:work@div_radix16.new_PR_sign
|vpiIndex:
\_ref_obj: (i), line:75
|vpiName:i
|vpiFullName:work@div_radix16.i
|vpiStmt:
\_assignment: , line:76
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (Q_lower), line:76
|vpiName:Q_lower
|vpiFullName:work@div_radix16.Q_lower
|vpiRhs:
\_operation: , line:76
|vpiOpType:29
|vpiOperand:
\_ref_obj: (Q_lower), line:76
|vpiName:Q_lower
|vpiFullName:work@div_radix16.Q_lower
|vpiOperand:
\_operation: , line:76
|vpiOpType:28
|vpiOperand:
\_operation: , line:76
|vpiOpType:33
|vpiOperand:
\_ref_obj: (div.quotient), line:76
|vpiName:div.quotient
|vpiFullName:work@div_radix16.div.quotient
|vpiOperand:
\_part_select: , line:76, parent:i
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (i)
|vpiLeftRange:
\_constant: , line:76
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiRightRange:
\_constant: , line:76
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiOperand:
\_operation: , line:76
|vpiOpType:34
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:76
|vpiName:div.DATA_WIDTH
|vpiFullName:work@div_radix16.div.DATA_WIDTH
|vpiOperand:
\_operation:
|vpiOpType:33
|vpiOperand:
\_operation: , line:76
|vpiOpType:28
|vpiOperand:
\_operation: , line:76
|vpiOpType:4
|vpiOperand:
\_bit_select: (new_PR_sign), line:76
|vpiName:new_PR_sign
|vpiIndex:
\_operation: , line:76
|vpiOpType:11
|vpiOperand:
\_ref_obj: (i), line:76
|vpiName:i
|vpiFullName:work@div_radix16.i
|vpiOperand:
\_constant: , line:76
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiOperand:
\_bit_select: (new_PR_sign), line:76
|vpiName:new_PR_sign
|vpiFullName:work@div_radix16.new_PR_sign
|vpiIndex:
\_ref_obj: (i), line:76
|vpiName:i
|vpiFullName:work@div_radix16.i
|vpiStmt:
\_assignment: , line:78
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (PR_lower), line:78
|vpiName:PR_lower
|vpiFullName:work@div_radix16.PR_lower
|vpiRhs:
\_operation: , line:78
|vpiOpType:29
|vpiOperand:
\_ref_obj: (PR_lower), line:78
|vpiName:PR_lower
|vpiFullName:work@div_radix16.PR_lower
|vpiOperand:
\_operation: , line:78
|vpiOpType:28
|vpiOperand:
\_operation: , line:78
|vpiOpType:33
|vpiOperand:
\_var_select: (new_PR), line:78
|vpiName:new_PR
|vpiIndex:
\_constant: , line:78
|vpiConstType:7
|vpiDecompile:6
|vpiSize:32
|INT:6
|vpiIndex:
\_part_select: , parent:new_PR
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (new_PR)
|vpiLeftRange:
\_operation: , line:78
|vpiOpType:11
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:78
|vpiName:div.DATA_WIDTH
|vpiFullName:work@div_radix16.div.DATA_WIDTH
|vpiOperand:
\_constant: , line:78
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:78
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiOperand:
\_ref_obj: (div.quotient), line:78
|vpiName:div.quotient
|vpiFullName:work@div_radix16.div.quotient
|vpiOperand:
\_operation: , line:78
|vpiOpType:34
|vpiOperand:
\_operation: , line:78
|vpiOpType:24
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:78
|vpiName:div.DATA_WIDTH
|vpiFullName:work@div_radix16.div.DATA_WIDTH
|vpiOperand:
\_constant: , line:78
|vpiConstType:7
|vpiDecompile:4
|vpiSize:32
|INT:4
|vpiOperand:
\_operation:
|vpiOpType:33
|vpiOperand:
\_operation: , line:78
|vpiOpType:4
|vpiOperand:
\_bit_select: (new_PR_sign), line:78
|vpiName:new_PR_sign
|vpiIndex:
\_constant: , line:78
|vpiConstType:7
|vpiDecompile:6
|vpiSize:32
|INT:6
|vpiStmt:
\_assignment: , line:79
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (Q_lower), line:79
|vpiName:Q_lower
|vpiFullName:work@div_radix16.Q_lower
|vpiRhs:
\_operation: , line:79
|vpiOpType:29
|vpiOperand:
\_ref_obj: (Q_lower), line:79
|vpiName:Q_lower
|vpiFullName:work@div_radix16.Q_lower
|vpiOperand:
\_operation: , line:79
|vpiOpType:28
|vpiOperand:
\_operation: , line:79
|vpiOpType:33
|vpiOperand:
\_ref_obj: (div.quotient), line:79
|vpiName:div.quotient
|vpiFullName:work@div_radix16.div.quotient
|vpiOperand:
\_constant: , line:79
|vpiConstType:3
|vpiDecompile:4'b0111
|vpiSize:4
|BIN:4'b0111
|vpiOperand:
\_operation: , line:79
|vpiOpType:34
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:79
|vpiName:div.DATA_WIDTH
|vpiFullName:work@div_radix16.div.DATA_WIDTH
|vpiOperand:
\_operation:
|vpiOpType:33
|vpiOperand:
\_operation: , line:79
|vpiOpType:4
|vpiOperand:
\_bit_select: (new_PR_sign), line:79
|vpiName:new_PR_sign
|vpiIndex:
\_constant: , line:79
|vpiConstType:7
|vpiDecompile:6
|vpiSize:32
|INT:6
|vpiStmt:
\_assignment: , line:81
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (PR_upper), line:81
|vpiName:PR_upper
|vpiFullName:work@div_radix16.PR_upper
|vpiRhs:
\_operation: , line:81
|vpiOpType:28
|vpiOperand:
\_operation: , line:81
|vpiOpType:33
|vpiOperand:
\_part_select: , line:81, parent:new_PR_8
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (new_PR_8)
|vpiLeftRange:
\_operation: , line:81
|vpiOpType:11
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:81
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:81
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:81
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiOperand:
\_ref_obj: (div.quotient), line:81
|vpiName:div.quotient
|vpiOperand:
\_operation: , line:81
|vpiOpType:34
|vpiOperand:
\_operation: , line:81
|vpiOpType:24
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:81
|vpiName:div.DATA_WIDTH
|vpiFullName:work@div_radix16.div.DATA_WIDTH
|vpiOperand:
\_constant: , line:81
|vpiConstType:7
|vpiDecompile:4
|vpiSize:32
|INT:4
|vpiOperand:
\_operation:
|vpiOpType:33
|vpiOperand:
\_bit_select: (new_PR_sign), line:81
|vpiName:new_PR_sign
|vpiIndex:
\_constant: , line:81
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiStmt:
\_assignment: , line:82
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (Q_upper), line:82
|vpiName:Q_upper
|vpiFullName:work@div_radix16.Q_upper
|vpiRhs:
\_operation: , line:82
|vpiOpType:28
|vpiOperand:
\_operation: , line:82
|vpiOpType:33
|vpiOperand:
\_ref_obj: (div.quotient), line:82
|vpiName:div.quotient
|vpiOperand:
\_constant: , line:82
|vpiConstType:3
|vpiDecompile:4'b1000
|vpiSize:4
|BIN:4'b1000
|vpiOperand:
\_operation: , line:82
|vpiOpType:34
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:82
|vpiName:div.DATA_WIDTH
|vpiFullName:work@div_radix16.div.DATA_WIDTH
|vpiOperand:
\_operation:
|vpiOpType:33
|vpiOperand:
\_bit_select: (new_PR_sign), line:82
|vpiName:new_PR_sign
|vpiIndex:
\_constant: , line:82
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiStmt:
\_for_stmt: , line:83
|vpiFullName:work@div_radix16
|vpiCondition:
\_operation: , line:83
|vpiOpType:20
|vpiOperand:
\_ref_obj: (i), line:83
|vpiName:i
|vpiFullName:work@div_radix16.i
|vpiOperand:
\_constant: , line:83
|vpiConstType:7
|vpiDecompile:7
|vpiSize:32
|INT:7
|vpiForInitStmt:
\_assign_stmt:
|vpiRhs:
\_constant: , line:83
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiLhs:
\_int_var: (i), line:83
|vpiName:i
|vpiFullName:work@div_radix16.i
|vpiForIncStmt:
\_operation: , line:83
|vpiOpType:82
|vpiOperand:
\_ref_obj: (i), line:83
|vpiName:i
|vpiStmt:
\_begin: , line:83
|vpiFullName:work@div_radix16
|vpiStmt:
\_assignment: , line:84
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (PR_upper), line:84
|vpiName:PR_upper
|vpiFullName:work@div_radix16.PR_upper
|vpiRhs:
\_operation: , line:84
|vpiOpType:29
|vpiOperand:
\_ref_obj: (PR_upper), line:84
|vpiName:PR_upper
|vpiFullName:work@div_radix16.PR_upper
|vpiOperand:
\_operation: , line:84
|vpiOpType:28
|vpiOperand:
\_operation: , line:84
|vpiOpType:33
|vpiOperand:
\_var_select: (new_PR), line:84
|vpiName:new_PR
|vpiIndex:
\_operation: , line:84
|vpiOpType:11
|vpiOperand:
\_ref_obj: (i), line:84
|vpiName:i
|vpiFullName:work@div_radix16.i
|vpiOperand:
\_constant: , line:84
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiIndex:
\_part_select: , parent:new_PR
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (new_PR)
|vpiLeftRange:
\_operation: , line:84
|vpiOpType:11
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:84
|vpiName:div.DATA_WIDTH
|vpiFullName:work@div_radix16.div.DATA_WIDTH
|vpiOperand:
\_constant: , line:84
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:84
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiOperand:
\_ref_obj: (div.quotient), line:84
|vpiName:div.quotient
|vpiFullName:work@div_radix16.div.quotient
|vpiOperand:
\_operation: , line:84
|vpiOpType:34
|vpiOperand:
\_operation: , line:84
|vpiOpType:24
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:84
|vpiName:div.DATA_WIDTH
|vpiFullName:work@div_radix16.div.DATA_WIDTH
|vpiOperand:
\_constant: , line:84
|vpiConstType:7
|vpiDecompile:4
|vpiSize:32
|INT:4
|vpiOperand:
\_operation:
|vpiOpType:33
|vpiOperand:
\_operation: , line:84
|vpiOpType:28
|vpiOperand:
\_operation: , line:84
|vpiOpType:4
|vpiOperand:
\_bit_select: (new_PR_sign), line:84
|vpiName:new_PR_sign
|vpiIndex:
\_operation: , line:84
|vpiOpType:11
|vpiOperand:
\_ref_obj: (i), line:84
|vpiName:i
|vpiFullName:work@div_radix16.i
|vpiOperand:
\_constant: , line:84
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiOperand:
\_bit_select: (new_PR_sign), line:84
|vpiName:new_PR_sign
|vpiFullName:work@div_radix16.new_PR_sign
|vpiIndex:
\_ref_obj: (i), line:84
|vpiName:i
|vpiFullName:work@div_radix16.i
|vpiStmt:
\_assignment: , line:85
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (Q_upper), line:85
|vpiName:Q_upper
|vpiFullName:work@div_radix16.Q_upper
|vpiRhs:
\_operation: , line:85
|vpiOpType:29
|vpiOperand:
\_ref_obj: (Q_upper), line:85
|vpiName:Q_upper
|vpiFullName:work@div_radix16.Q_upper
|vpiOperand:
\_operation: , line:85
|vpiOpType:28
|vpiOperand:
\_operation: , line:85
|vpiOpType:33
|vpiOperand:
\_ref_obj: (div.quotient), line:85
|vpiName:div.quotient
|vpiFullName:work@div_radix16.div.quotient
|vpiOperand:
\_operation: , line:85
|vpiOpType:29
|vpiOperand:
\_part_select: , line:85, parent:i
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (i)
|vpiLeftRange:
\_constant: , line:85
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiRightRange:
\_constant: , line:85
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiOperand:
\_constant: , line:85
|vpiConstType:3
|vpiDecompile:4'b1000
|vpiSize:4
|BIN:4'b1000
|vpiOperand:
\_operation: , line:85
|vpiOpType:34
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:85
|vpiName:div.DATA_WIDTH
|vpiFullName:work@div_radix16.div.DATA_WIDTH
|vpiOperand:
\_operation:
|vpiOpType:33
|vpiOperand:
\_operation: , line:85
|vpiOpType:28
|vpiOperand:
\_operation: , line:85
|vpiOpType:4
|vpiOperand:
\_bit_select: (new_PR_sign), line:85
|vpiName:new_PR_sign
|vpiIndex:
\_operation: , line:85
|vpiOpType:11
|vpiOperand:
\_ref_obj: (i), line:85
|vpiName:i
|vpiFullName:work@div_radix16.i
|vpiOperand:
\_constant: , line:85
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiOperand:
\_bit_select: (new_PR_sign), line:85
|vpiName:new_PR_sign
|vpiFullName:work@div_radix16.new_PR_sign
|vpiIndex:
\_ref_obj: (i), line:85
|vpiName:i
|vpiFullName:work@div_radix16.i
|vpiStmt:
\_assignment: , line:87
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (PR_upper), line:87
|vpiName:PR_upper
|vpiFullName:work@div_radix16.PR_upper
|vpiRhs:
\_operation: , line:87
|vpiOpType:29
|vpiOperand:
\_ref_obj: (PR_upper), line:87
|vpiName:PR_upper
|vpiFullName:work@div_radix16.PR_upper
|vpiOperand:
\_operation: , line:87
|vpiOpType:28
|vpiOperand:
\_operation: , line:87
|vpiOpType:33
|vpiOperand:
\_var_select: (new_PR), line:87
|vpiName:new_PR
|vpiIndex:
\_constant: , line:87
|vpiConstType:7
|vpiDecompile:6
|vpiSize:32
|INT:6
|vpiIndex:
\_part_select: , parent:new_PR
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (new_PR)
|vpiLeftRange:
\_operation: , line:87
|vpiOpType:11
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:87
|vpiName:div.DATA_WIDTH
|vpiFullName:work@div_radix16.div.DATA_WIDTH
|vpiOperand:
\_constant: , line:87
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:87
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiOperand:
\_ref_obj: (div.quotient), line:87
|vpiName:div.quotient
|vpiFullName:work@div_radix16.div.quotient
|vpiOperand:
\_operation: , line:87
|vpiOpType:34
|vpiOperand:
\_operation: , line:87
|vpiOpType:24
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:87
|vpiName:div.DATA_WIDTH
|vpiFullName:work@div_radix16.div.DATA_WIDTH
|vpiOperand:
\_constant: , line:87
|vpiConstType:7
|vpiDecompile:4
|vpiSize:32
|INT:4
|vpiOperand:
\_operation:
|vpiOpType:33
|vpiOperand:
\_operation: , line:87
|vpiOpType:4
|vpiOperand:
\_bit_select: (new_PR_sign), line:87
|vpiName:new_PR_sign
|vpiIndex:
\_constant: , line:87
|vpiConstType:7
|vpiDecompile:6
|vpiSize:32
|INT:6
|vpiStmt:
\_assignment: , line:88
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (Q_upper), line:88
|vpiName:Q_upper
|vpiFullName:work@div_radix16.Q_upper
|vpiRhs:
\_operation: , line:88
|vpiOpType:29
|vpiOperand:
\_ref_obj: (Q_upper), line:88
|vpiName:Q_upper
|vpiFullName:work@div_radix16.Q_upper
|vpiOperand:
\_operation: , line:88
|vpiOpType:28
|vpiOperand:
\_operation: , line:88
|vpiOpType:33
|vpiOperand:
\_ref_obj: (div.quotient), line:88
|vpiName:div.quotient
|vpiFullName:work@div_radix16.div.quotient
|vpiOperand:
\_constant: , line:88
|vpiConstType:3
|vpiDecompile:4'b1111
|vpiSize:4
|BIN:4'b1111
|vpiOperand:
\_operation: , line:88
|vpiOpType:34
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:88
|vpiName:div.DATA_WIDTH
|vpiFullName:work@div_radix16.div.DATA_WIDTH
|vpiOperand:
\_operation:
|vpiOpType:33
|vpiOperand:
\_operation: , line:88
|vpiOpType:4
|vpiOperand:
\_bit_select: (new_PR_sign), line:88
|vpiName:new_PR_sign
|vpiIndex:
\_constant: , line:88
|vpiConstType:7
|vpiDecompile:6
|vpiSize:32
|INT:6
|vpiProcess:
\_always: , line:91
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:91
|vpiCondition:
\_operation: , line:91
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:91
|vpiName:clk
|vpiFullName:work@div_radix16.clk
|vpiStmt:
\_begin: , line:91
|vpiFullName:work@div_radix16
|vpiStmt:
\_if_else: , line:92
|vpiCondition:
\_ref_obj: (div.start), line:92
|vpiName:div.start
|vpiFullName:work@div_radix16.div.start
|vpiStmt:
\_begin: , line:92
|vpiFullName:work@div_radix16
|vpiStmt:
\_assignment: , line:93
|vpiOpType:82
|vpiLhs:
\_ref_obj: (B_6), line:93
|vpiName:B_6
|vpiFullName:work@div_radix16.B_6
|vpiRhs:
\_operation: , line:93
|vpiOpType:24
|vpiOperand:
\_operation: , line:93
|vpiOpType:33
|vpiOperand:
\_constant: , line:93
|vpiConstType:3
|vpiDecompile:2'b00
|vpiSize:2
|BIN:2'b00
|vpiOperand:
\_ref_obj: (div.divisor), line:93
|vpiName:div.divisor
|vpiOperand:
\_constant: , line:93
|vpiConstType:3
|vpiDecompile:2'b00
|vpiSize:2
|BIN:2'b00
|vpiOperand:
\_operation: , line:93
|vpiOpType:33
|vpiOperand:
\_constant: , line:93
|vpiConstType:3
|vpiDecompile:3'b000
|vpiSize:3
|BIN:3'b000
|vpiOperand:
\_ref_obj: (div.divisor), line:93
|vpiName:div.divisor
|vpiFullName:work@div_radix16.div.divisor
|vpiOperand:
\_constant: , line:93
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiStmt:
\_assignment: , line:94
|vpiOpType:82
|vpiLhs:
\_ref_obj: (B_10), line:94
|vpiName:B_10
|vpiFullName:work@div_radix16.B_10
|vpiRhs:
\_operation: , line:94
|vpiOpType:24
|vpiOperand:
\_operation: , line:94
|vpiOpType:33
|vpiOperand:
\_constant: , line:94
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiOperand:
\_ref_obj: (div.divisor), line:94
|vpiName:div.divisor
|vpiOperand:
\_constant: , line:94
|vpiConstType:3
|vpiDecompile:3'b000
|vpiSize:3
|BIN:3'b000
|vpiOperand:
\_operation: , line:94
|vpiOpType:33
|vpiOperand:
\_constant: , line:94
|vpiConstType:3
|vpiDecompile:3'b000
|vpiSize:3
|BIN:3'b000
|vpiOperand:
\_ref_obj: (div.divisor), line:94
|vpiName:div.divisor
|vpiFullName:work@div_radix16.div.divisor
|vpiOperand:
\_constant: , line:94
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiStmt:
\_assignment: , line:95
|vpiOpType:82
|vpiLhs:
\_ref_obj: (B_12), line:95
|vpiName:B_12
|vpiFullName:work@div_radix16.B_12
|vpiRhs:
\_operation: , line:95
|vpiOpType:24
|vpiOperand:
\_operation: , line:95
|vpiOpType:33
|vpiOperand:
\_constant: , line:95
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiOperand:
\_ref_obj: (div.divisor), line:95
|vpiName:div.divisor
|vpiOperand:
\_constant: , line:95
|vpiConstType:3
|vpiDecompile:3'b000
|vpiSize:3
|BIN:3'b000
|vpiOperand:
\_operation: , line:95
|vpiOpType:33
|vpiOperand:
\_constant: , line:95
|vpiConstType:3
|vpiDecompile:2'b00
|vpiSize:2
|BIN:2'b00
|vpiOperand:
\_ref_obj: (div.divisor), line:95
|vpiName:div.divisor
|vpiFullName:work@div_radix16.div.divisor
|vpiOperand:
\_constant: , line:95
|vpiConstType:3
|vpiDecompile:2'b00
|vpiSize:2
|BIN:2'b00
|vpiStmt:
\_assignment: , line:96
|vpiOpType:82
|vpiLhs:
\_ref_obj: (B_14), line:96
|vpiName:B_14
|vpiFullName:work@div_radix16.B_14
|vpiRhs:
\_operation: , line:96
|vpiOpType:24
|vpiOperand:
\_operation: , line:96
|vpiOpType:24
|vpiOperand:
\_operation: , line:96
|vpiOpType:33
|vpiOperand:
\_constant: , line:96
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiOperand:
\_ref_obj: (div.divisor), line:96
|vpiName:div.divisor
|vpiOperand:
\_constant: , line:96
|vpiConstType:3
|vpiDecompile:3'b000
|vpiSize:3
|BIN:3'b000
|vpiOperand:
\_operation: , line:96
|vpiOpType:33
|vpiOperand:
\_constant: , line:96
|vpiConstType:3
|vpiDecompile:2'b00
|vpiSize:2
|BIN:2'b00
|vpiOperand:
\_ref_obj: (div.divisor), line:96
|vpiName:div.divisor
|vpiFullName:work@div_radix16.div.divisor
|vpiOperand:
\_constant: , line:96
|vpiConstType:3
|vpiDecompile:2'b00
|vpiSize:2
|BIN:2'b00
|vpiOperand:
\_operation: , line:96
|vpiOpType:33
|vpiOperand:
\_constant: , line:96
|vpiConstType:3
|vpiDecompile:3'b000
|vpiSize:3
|BIN:3'b000
|vpiOperand:
\_ref_obj: (div.divisor), line:96
|vpiName:div.divisor
|vpiFullName:work@div_radix16.div.divisor
|vpiOperand:
\_constant: , line:96
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiStmt:
\_assignment: , line:98
|vpiOpType:82
|vpiLhs:
\_ref_obj: (PR), line:98
|vpiName:PR
|vpiFullName:work@div_radix16.PR
|vpiRhs:
\_operation: , line:98
|vpiOpType:33
|vpiOperand:
\_operation: , line:98
|vpiOpType:34
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:98
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_operation:
|vpiOpType:33
|vpiOperand:
\_constant: , line:98
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiOperand:
\_ref_obj: (div.dividend), line:98
|vpiName:div.dividend
|vpiStmt:
\_assignment: , line:99
|vpiOpType:82
|vpiLhs:
\_ref_obj: (div.quotient), line:99
|vpiName:div.quotient
|vpiFullName:work@div_radix16.div.quotient
|vpiRhs:
\_operation: , line:99
|vpiOpType:33
|vpiOperand:
\_ref_obj: (div.dividend), line:99
|vpiName:div.dividend
|vpiOperand:
\_constant: , line:99
|vpiConstType:3
|vpiDecompile:4'b0000
|vpiSize:4
|BIN:4'b0000
|vpiElseStmt:
\_if_stmt: , line:101
|vpiCondition:
\_operation: , line:101
|vpiOpType:4
|vpiOperand:
\_ref_obj: (terminate), line:101
|vpiName:terminate
|vpiFullName:work@div_radix16.terminate
|vpiStmt:
\_begin: , line:101
|vpiFullName:work@div_radix16
|vpiStmt:
\_case_stmt: , line:102
|vpiCaseType:1
|vpiCondition:
\_bit_select: (new_PR_8), line:102
|vpiName:new_PR_8
|vpiFullName:work@div_radix16.new_PR_8
|vpiIndex:
\_operation: , line:102
|vpiOpType:24
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:102
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:102
|vpiConstType:7
|vpiDecompile:4
|vpiSize:32
|INT:4
|vpiCaseItem:
\_case_item: , line:103
|vpiExpr:
\_constant: , line:103
|vpiConstType:3
|vpiDecompile:'b1
|vpiSize:1
|BIN:1
|vpiStmt:
\_begin: , line:103
|vpiFullName:work@div_radix16
|vpiStmt:
\_assignment: , line:104
|vpiOpType:82
|vpiLhs:
\_ref_obj: (PR), line:104
|vpiName:PR
|vpiFullName:work@div_radix16.PR
|vpiRhs:
\_ref_obj: (PR_lower), line:104
|vpiName:PR_lower
|vpiFullName:work@div_radix16.PR_lower
|vpiStmt:
\_assignment: , line:105
|vpiOpType:82
|vpiLhs:
\_ref_obj: (div.quotient), line:105
|vpiName:div.quotient
|vpiFullName:work@div_radix16.div.quotient
|vpiRhs:
\_ref_obj: (Q_lower), line:105
|vpiName:Q_lower
|vpiFullName:work@div_radix16.Q_lower
|vpiCaseItem:
\_case_item: , line:107
|vpiExpr:
\_constant: , line:107
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiStmt:
\_begin: , line:107
|vpiFullName:work@div_radix16
|vpiStmt:
\_assignment: , line:108
|vpiOpType:82
|vpiLhs:
\_ref_obj: (PR), line:108
|vpiName:PR
|vpiFullName:work@div_radix16.PR
|vpiRhs:
\_ref_obj: (PR_upper), line:108
|vpiName:PR_upper
|vpiFullName:work@div_radix16.PR_upper
|vpiStmt:
\_assignment: , line:109
|vpiOpType:82
|vpiLhs:
\_ref_obj: (div.quotient), line:109
|vpiName:div.quotient
|vpiFullName:work@div_radix16.div.quotient
|vpiRhs:
\_ref_obj: (Q_upper), line:109
|vpiName:Q_upper
|vpiFullName:work@div_radix16.Q_upper
|vpiProcess:
\_always: , line:117
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:117
|vpiCondition:
\_operation: , line:117
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:117
|vpiName:clk
|vpiFullName:work@div_radix16.clk
|vpiStmt:
\_begin: , line:117
|vpiFullName:work@div_radix16
|vpiStmt:
\_if_else: , line:118
|vpiCondition:
\_ref_obj: (div.start), line:118
|vpiName:div.start
|vpiFullName:work@div_radix16.div.start
|vpiStmt:
\_assignment: , line:119
|vpiOpType:82
|vpiLhs:
\_ref_obj: (div.divisor_is_zero), line:119
|vpiName:div.divisor_is_zero
|vpiFullName:work@div_radix16.div.divisor_is_zero
|vpiRhs:
\_operation: , line:119
|vpiOpType:4
|vpiOperand:
\_ref_obj: (div.divisor), line:119
|vpiName:div.divisor
|vpiFullName:work@div_radix16.div.divisor
|vpiElseStmt:
\_if_stmt: , line:120
|vpiCondition:
\_operation: , line:120
|vpiOpType:4
|vpiOperand:
\_ref_obj: (terminate), line:120
|vpiName:terminate
|vpiFullName:work@div_radix16.terminate
|vpiStmt:
\_assignment: , line:121
|vpiOpType:82
|vpiLhs:
\_ref_obj: (div.divisor_is_zero), line:121
|vpiName:div.divisor_is_zero
|vpiFullName:work@div_radix16.div.divisor_is_zero
|vpiRhs:
\_operation: , line:121
|vpiOpType:28
|vpiOperand:
\_ref_obj: (div.divisor_is_zero), line:121
|vpiName:div.divisor_is_zero
|vpiFullName:work@div_radix16.div.divisor_is_zero
|vpiOperand:
\_operation: , line:121
|vpiOpType:4
|vpiOperand:
\_operation: , line:121
|vpiOpType:7
|vpiOperand:
\_ref_obj: (new_PR_sign), line:121
|vpiName:new_PR_sign
|vpiFullName:work@div_radix16.new_PR_sign
|vpiProcess:
\_always: , line:124
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:124
|vpiCondition:
\_operation: , line:124
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:124
|vpiName:clk
|vpiFullName:work@div_radix16.clk
|vpiStmt:
\_begin: , line:124
|vpiFullName:work@div_radix16
|vpiStmt:
\_if_else: , line:125
|vpiCondition:
\_ref_obj: (rst), line:125
|vpiName:rst
|vpiFullName:work@div_radix16.rst
|vpiStmt:
\_assignment: , line:126
|vpiOpType:82
|vpiLhs:
\_ref_obj: (terminate), line:126
|vpiName:terminate
|vpiFullName:work@div_radix16.terminate
|vpiRhs:
\_constant: , line:126
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiElseStmt:
\_begin: , line:127
|vpiFullName:work@div_radix16
|vpiStmt:
\_if_stmt: , line:128
|vpiCondition:
\_ref_obj: (div.start), line:128
|vpiName:div.start
|vpiFullName:work@div_radix16.div.start
|vpiStmt:
\_assignment: , line:129
|vpiOpType:82
|vpiLhs:
\_ref_obj: (terminate), line:129
|vpiName:terminate
|vpiFullName:work@div_radix16.terminate
|vpiRhs:
\_constant: , line:129
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiStmt:
\_if_stmt: , line:130
|vpiCondition:
\_bit_select: (shift_count), line:130
|vpiName:shift_count
|vpiFullName:work@div_radix16.shift_count
|vpiIndex:
\_constant: , line:130
|vpiConstType:7
|vpiDecompile:7
|vpiSize:32
|INT:7
|vpiStmt:
\_assignment: , line:131
|vpiOpType:82
|vpiLhs:
\_ref_obj: (terminate), line:131
|vpiName:terminate
|vpiFullName:work@div_radix16.terminate
|vpiRhs:
\_constant: , line:131
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiProcess:
\_always: , line:135
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:135
|vpiCondition:
\_operation: , line:135
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:135
|vpiName:clk
|vpiFullName:work@div_radix16.clk
|vpiStmt:
\_begin: , line:135
|vpiFullName:work@div_radix16
|vpiStmt:
\_if_else: , line:136
|vpiCondition:
\_ref_obj: (rst), line:136
|vpiName:rst
|vpiFullName:work@div_radix16.rst
|vpiStmt:
\_assignment: , line:137
|vpiOpType:82
|vpiLhs:
\_ref_obj: (div.done), line:137
|vpiName:div.done
|vpiFullName:work@div_radix16.div.done
|vpiRhs:
\_constant: , line:137
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiElseStmt:
\_begin: , line:138
|vpiFullName:work@div_radix16
|vpiStmt:
\_if_else: , line:139
|vpiCondition:
\_bit_select: (shift_count), line:139
|vpiName:shift_count
|vpiFullName:work@div_radix16.shift_count
|vpiIndex:
\_constant: , line:139
|vpiConstType:7
|vpiDecompile:7
|vpiSize:32
|INT:7
|vpiStmt:
\_assignment: , line:140
|vpiOpType:82
|vpiLhs:
\_ref_obj: (div.done), line:140
|vpiName:div.done
|vpiFullName:work@div_radix16.div.done
|vpiRhs:
\_constant: , line:140
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiElseStmt:
\_if_stmt: , line:141
|vpiCondition:
\_ref_obj: (div.done), line:141
|vpiName:div.done
|vpiFullName:work@div_radix16.div.done
|vpiStmt:
\_assignment: , line:142
|vpiOpType:82
|vpiLhs:
\_ref_obj: (div.done), line:142
|vpiName:div.done
|vpiFullName:work@div_radix16.div.done
|vpiRhs:
\_constant: , line:142
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiPort:
\_port: (clk), line:27
|vpiName:clk
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (clk), line:27
|vpiName:clk
|vpiFullName:work@div_radix16.clk
|vpiNetType:36
|vpiPort:
\_port: (rst), line:28
|vpiName:rst
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (rst), line:28
|vpiName:rst
|vpiFullName:work@div_radix16.rst
|vpiNetType:36
|vpiPort:
\_port: (div), line:29
|vpiName:div
|vpiDirection:5
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_modport: (divider)
|vpiContAssign:
\_cont_assign: , line:58
|vpiRhs:
\_operation: , line:58
|vpiOpType:11
|vpiOperand:
\_operation: , line:58
|vpiOpType:33
|vpiOperand:
\_constant: , line:58
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiOperand:
\_ref_obj: (PR), line:58
|vpiName:PR
|vpiOperand:
\_operation: , line:58
|vpiOpType:33
|vpiOperand:
\_constant: , line:58
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiOperand:
\_operation: , line:58
|vpiOpType:33
|vpiOperand:
\_constant: , line:58
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiOperand:
\_ref_obj: (div.divisor), line:58
|vpiName:div.divisor
|vpiFullName:work@div_radix16.div.divisor
|vpiOperand:
\_constant: , line:58
|vpiConstType:3
|vpiDecompile:3'b000
|vpiSize:3
|BIN:3'b000
|vpiLhs:
\_ref_obj: (new_PR_8), line:58
|vpiName:new_PR_8
|vpiFullName:work@div_radix16.new_PR_8
|vpiContAssign:
\_cont_assign: , line:59
|vpiRhs:
\_operation: , line:59
|vpiOpType:32
|vpiOperand:
\_bit_select: (new_PR_8), line:59
|vpiName:new_PR_8
|vpiFullName:work@div_radix16.new_PR_8
|vpiIndex:
\_operation: , line:59
|vpiOpType:24
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:59
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:59
|vpiConstType:7
|vpiDecompile:4
|vpiSize:32
|INT:4
|vpiOperand:
\_operation: , line:59
|vpiOpType:11
|vpiOperand:
\_operation: , line:59
|vpiOpType:33
|vpiOperand:
\_constant: , line:59
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiOperand:
\_ref_obj: (PR), line:59
|vpiName:PR
|vpiFullName:work@div_radix16.PR
|vpiOperand:
\_operation: , line:59
|vpiOpType:33
|vpiOperand:
\_constant: , line:59
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiOperand:
\_operation: , line:59
|vpiOpType:33
|vpiOperand:
\_constant: , line:59
|vpiConstType:3
|vpiDecompile:4'b0000
|vpiSize:4
|BIN:4'b0000
|vpiOperand:
\_ref_obj: (div.divisor), line:59
|vpiName:div.divisor
|vpiFullName:work@div_radix16.div.divisor
|vpiOperand:
\_operation: , line:59
|vpiOpType:11
|vpiOperand:
\_operation: , line:59
|vpiOpType:11
|vpiOperand:
\_operation: , line:59
|vpiOpType:33
|vpiOperand:
\_constant: , line:59
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiOperand:
\_ref_obj: (PR), line:59
|vpiName:PR
|vpiFullName:work@div_radix16.PR
|vpiOperand:
\_operation: , line:59
|vpiOpType:33
|vpiOperand:
\_constant: , line:59
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiOperand:
\_operation: , line:59
|vpiOpType:33
|vpiOperand:
\_constant: , line:59
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiOperand:
\_ref_obj: (div.divisor), line:59
|vpiName:div.divisor
|vpiFullName:work@div_radix16.div.divisor
|vpiOperand:
\_constant: , line:59
|vpiConstType:3
|vpiDecompile:3'b000
|vpiSize:3
|BIN:3'b000
|vpiOperand:
\_operation: , line:59
|vpiOpType:33
|vpiOperand:
\_constant: , line:59
|vpiConstType:3
|vpiDecompile:4'b0000
|vpiSize:4
|BIN:4'b0000
|vpiOperand:
\_ref_obj: (div.divisor), line:59
|vpiName:div.divisor
|vpiFullName:work@div_radix16.div.divisor
|vpiLhs:
\_bit_select: (new_PR), line:59
|vpiName:new_PR
|vpiFullName:work@div_radix16.new_PR
|vpiIndex:
\_constant: , line:59
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiContAssign:
\_cont_assign: , line:60
|vpiRhs:
\_operation: , line:60
|vpiOpType:32
|vpiOperand:
\_bit_select: (new_PR_8), line:60
|vpiName:new_PR_8
|vpiFullName:work@div_radix16.new_PR_8
|vpiIndex:
\_operation: , line:60
|vpiOpType:24
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:60
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:60
|vpiConstType:7
|vpiDecompile:4
|vpiSize:32
|INT:4
|vpiOperand:
\_operation: , line:60
|vpiOpType:11
|vpiOperand:
\_operation: , line:60
|vpiOpType:33
|vpiOperand:
\_constant: , line:60
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiOperand:
\_ref_obj: (PR), line:60
|vpiName:PR
|vpiFullName:work@div_radix16.PR
|vpiOperand:
\_operation: , line:60
|vpiOpType:33
|vpiOperand:
\_constant: , line:60
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiOperand:
\_operation: , line:60
|vpiOpType:33
|vpiOperand:
\_constant: , line:60
|vpiConstType:3
|vpiDecompile:3'b000
|vpiSize:3
|BIN:3'b000
|vpiOperand:
\_ref_obj: (div.divisor), line:60
|vpiName:div.divisor
|vpiFullName:work@div_radix16.div.divisor
|vpiOperand:
\_constant: , line:60
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiOperand:
\_operation: , line:60
|vpiOpType:11
|vpiOperand:
\_operation: , line:60
|vpiOpType:33
|vpiOperand:
\_constant: , line:60
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiOperand:
\_ref_obj: (PR), line:60
|vpiName:PR
|vpiFullName:work@div_radix16.PR
|vpiOperand:
\_operation: , line:60
|vpiOpType:33
|vpiOperand:
\_constant: , line:60
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiOperand:
\_ref_obj: (B_10), line:60
|vpiName:B_10
|vpiFullName:work@div_radix16.B_10
|vpiLhs:
\_bit_select: (new_PR), line:60
|vpiName:new_PR
|vpiFullName:work@div_radix16.new_PR
|vpiIndex:
\_constant: , line:60
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiContAssign:
\_cont_assign: , line:61
|vpiRhs:
\_operation: , line:61
|vpiOpType:32
|vpiOperand:
\_bit_select: (new_PR_8), line:61
|vpiName:new_PR_8
|vpiFullName:work@div_radix16.new_PR_8
|vpiIndex:
\_operation: , line:61
|vpiOpType:24
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:61
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:61
|vpiConstType:7
|vpiDecompile:4
|vpiSize:32
|INT:4
|vpiOperand:
\_operation: , line:61
|vpiOpType:11
|vpiOperand:
\_operation: , line:61
|vpiOpType:11
|vpiOperand:
\_operation: , line:61
|vpiOpType:33
|vpiOperand:
\_constant: , line:61
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiOperand:
\_ref_obj: (PR), line:61
|vpiName:PR
|vpiFullName:work@div_radix16.PR
|vpiOperand:
\_operation: , line:61
|vpiOpType:33
|vpiOperand:
\_constant: , line:61
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiOperand:
\_operation: , line:61
|vpiOpType:33
|vpiOperand:
\_constant: , line:61
|vpiConstType:3
|vpiDecompile:3'b000
|vpiSize:3
|BIN:3'b000
|vpiOperand:
\_ref_obj: (div.divisor), line:61
|vpiName:div.divisor
|vpiFullName:work@div_radix16.div.divisor
|vpiOperand:
\_constant: , line:61
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiOperand:
\_operation: , line:61
|vpiOpType:33
|vpiOperand:
\_constant: , line:61
|vpiConstType:3
|vpiDecompile:4'b0000
|vpiSize:4
|BIN:4'b0000
|vpiOperand:
\_ref_obj: (div.divisor), line:61
|vpiName:div.divisor
|vpiFullName:work@div_radix16.div.divisor
|vpiOperand:
\_operation: , line:61
|vpiOpType:11
|vpiOperand:
\_operation: , line:61
|vpiOpType:11
|vpiOperand:
\_operation: , line:61
|vpiOpType:33
|vpiOperand:
\_constant: , line:61
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiOperand:
\_ref_obj: (PR), line:61
|vpiName:PR
|vpiFullName:work@div_radix16.PR
|vpiOperand:
\_operation: , line:61
|vpiOpType:33
|vpiOperand:
\_constant: , line:61
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiOperand:
\_ref_obj: (B_10), line:61
|vpiName:B_10
|vpiFullName:work@div_radix16.B_10
|vpiOperand:
\_operation: , line:61
|vpiOpType:33
|vpiOperand:
\_constant: , line:61
|vpiConstType:3
|vpiDecompile:4'b0000
|vpiSize:4
|BIN:4'b0000
|vpiOperand:
\_ref_obj: (div.divisor), line:61
|vpiName:div.divisor
|vpiFullName:work@div_radix16.div.divisor
|vpiLhs:
\_bit_select: (new_PR), line:61
|vpiName:new_PR
|vpiFullName:work@div_radix16.new_PR
|vpiIndex:
\_constant: , line:61
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiContAssign:
\_cont_assign: , line:62
|vpiRhs:
\_operation: , line:62
|vpiOpType:32
|vpiOperand:
\_bit_select: (new_PR_8), line:62
|vpiName:new_PR_8
|vpiFullName:work@div_radix16.new_PR_8
|vpiIndex:
\_operation: , line:62
|vpiOpType:24
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:62
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:62
|vpiConstType:7
|vpiDecompile:4
|vpiSize:32
|INT:4
|vpiOperand:
\_operation: , line:62
|vpiOpType:11
|vpiOperand:
\_operation: , line:62
|vpiOpType:33
|vpiOperand:
\_constant: , line:62
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiOperand:
\_ref_obj: (PR), line:62
|vpiName:PR
|vpiFullName:work@div_radix16.PR
|vpiOperand:
\_operation: , line:62
|vpiOpType:33
|vpiOperand:
\_constant: , line:62
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiOperand:
\_operation: , line:62
|vpiOpType:33
|vpiOperand:
\_constant: , line:62
|vpiConstType:3
|vpiDecompile:2'b00
|vpiSize:2
|BIN:2'b00
|vpiOperand:
\_ref_obj: (div.divisor), line:62
|vpiName:div.divisor
|vpiFullName:work@div_radix16.div.divisor
|vpiOperand:
\_constant: , line:62
|vpiConstType:3
|vpiDecompile:2'b00
|vpiSize:2
|BIN:2'b00
|vpiOperand:
\_operation: , line:62
|vpiOpType:11
|vpiOperand:
\_operation: , line:62
|vpiOpType:33
|vpiOperand:
\_constant: , line:62
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiOperand:
\_ref_obj: (PR), line:62
|vpiName:PR
|vpiFullName:work@div_radix16.PR
|vpiOperand:
\_operation: , line:62
|vpiOpType:33
|vpiOperand:
\_constant: , line:62
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiOperand:
\_ref_obj: (B_12), line:62
|vpiName:B_12
|vpiFullName:work@div_radix16.B_12
|vpiLhs:
\_bit_select: (new_PR), line:62
|vpiName:new_PR
|vpiFullName:work@div_radix16.new_PR
|vpiIndex:
\_constant: , line:62
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiContAssign:
\_cont_assign: , line:63
|vpiRhs:
\_operation: , line:63
|vpiOpType:32
|vpiOperand:
\_bit_select: (new_PR_8), line:63
|vpiName:new_PR_8
|vpiFullName:work@div_radix16.new_PR_8
|vpiIndex:
\_operation: , line:63
|vpiOpType:24
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:63
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:63
|vpiConstType:7
|vpiDecompile:4
|vpiSize:32
|INT:4
|vpiOperand:
\_operation: , line:63
|vpiOpType:11
|vpiOperand:
\_operation: , line:63
|vpiOpType:11
|vpiOperand:
\_operation: , line:63
|vpiOpType:33
|vpiOperand:
\_constant: , line:63
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiOperand:
\_ref_obj: (PR), line:63
|vpiName:PR
|vpiFullName:work@div_radix16.PR
|vpiOperand:
\_operation: , line:63
|vpiOpType:33
|vpiOperand:
\_constant: , line:63
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiOperand:
\_operation: , line:63
|vpiOpType:33
|vpiOperand:
\_constant: , line:63
|vpiConstType:3
|vpiDecompile:2'b00
|vpiSize:2
|BIN:2'b00
|vpiOperand:
\_ref_obj: (div.divisor), line:63
|vpiName:div.divisor
|vpiFullName:work@div_radix16.div.divisor
|vpiOperand:
\_constant: , line:63
|vpiConstType:3
|vpiDecompile:2'b00
|vpiSize:2
|BIN:2'b00
|vpiOperand:
\_operation: , line:63
|vpiOpType:33
|vpiOperand:
\_constant: , line:63
|vpiConstType:3
|vpiDecompile:4'b0000
|vpiSize:4
|BIN:4'b0000
|vpiOperand:
\_ref_obj: (div.divisor), line:63
|vpiName:div.divisor
|vpiFullName:work@div_radix16.div.divisor
|vpiOperand:
\_operation: , line:63
|vpiOpType:11
|vpiOperand:
\_operation: , line:63
|vpiOpType:11
|vpiOperand:
\_operation: , line:63
|vpiOpType:33
|vpiOperand:
\_constant: , line:63
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiOperand:
\_ref_obj: (PR), line:63
|vpiName:PR
|vpiFullName:work@div_radix16.PR
|vpiOperand:
\_operation: , line:63
|vpiOpType:33
|vpiOperand:
\_constant: , line:63
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiOperand:
\_ref_obj: (B_12), line:63
|vpiName:B_12
|vpiFullName:work@div_radix16.B_12
|vpiOperand:
\_operation: , line:63
|vpiOpType:33
|vpiOperand:
\_constant: , line:63
|vpiConstType:3
|vpiDecompile:4'b0000
|vpiSize:4
|BIN:4'b0000
|vpiOperand:
\_ref_obj: (div.divisor), line:63
|vpiName:div.divisor
|vpiFullName:work@div_radix16.div.divisor
|vpiLhs:
\_bit_select: (new_PR), line:63
|vpiName:new_PR
|vpiFullName:work@div_radix16.new_PR
|vpiIndex:
\_constant: , line:63
|vpiConstType:7
|vpiDecompile:4
|vpiSize:32
|INT:4
|vpiContAssign:
\_cont_assign: , line:64
|vpiRhs:
\_operation: , line:64
|vpiOpType:32
|vpiOperand:
\_bit_select: (new_PR_8), line:64
|vpiName:new_PR_8
|vpiFullName:work@div_radix16.new_PR_8
|vpiIndex:
\_operation: , line:64
|vpiOpType:24
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:64
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:64
|vpiConstType:7
|vpiDecompile:4
|vpiSize:32
|INT:4
|vpiOperand:
\_operation: , line:64
|vpiOpType:11
|vpiOperand:
\_operation: , line:64
|vpiOpType:33
|vpiOperand:
\_constant: , line:64
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiOperand:
\_ref_obj: (PR), line:64
|vpiName:PR
|vpiFullName:work@div_radix16.PR
|vpiOperand:
\_operation: , line:64
|vpiOpType:33
|vpiOperand:
\_constant: , line:64
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiOperand:
\_ref_obj: (B_6), line:64
|vpiName:B_6
|vpiFullName:work@div_radix16.B_6
|vpiOperand:
\_operation: , line:64
|vpiOpType:11
|vpiOperand:
\_operation: , line:64
|vpiOpType:33
|vpiOperand:
\_constant: , line:64
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiOperand:
\_ref_obj: (PR), line:64
|vpiName:PR
|vpiFullName:work@div_radix16.PR
|vpiOperand:
\_operation: , line:64
|vpiOpType:33
|vpiOperand:
\_constant: , line:64
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiOperand:
\_ref_obj: (B_14), line:64
|vpiName:B_14
|vpiFullName:work@div_radix16.B_14
|vpiLhs:
\_bit_select: (new_PR), line:64
|vpiName:new_PR
|vpiFullName:work@div_radix16.new_PR
|vpiIndex:
\_constant: , line:64
|vpiConstType:7
|vpiDecompile:5
|vpiSize:32
|INT:5
|vpiContAssign:
\_cont_assign: , line:65
|vpiRhs:
\_operation: , line:65
|vpiOpType:32
|vpiOperand:
\_bit_select: (new_PR_8), line:65
|vpiName:new_PR_8
|vpiFullName:work@div_radix16.new_PR_8
|vpiIndex:
\_operation: , line:65
|vpiOpType:24
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:65
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:65
|vpiConstType:7
|vpiDecompile:4
|vpiSize:32
|INT:4
|vpiOperand:
\_operation: , line:65
|vpiOpType:11
|vpiOperand:
\_operation: , line:65
|vpiOpType:11
|vpiOperand:
\_operation: , line:65
|vpiOpType:33
|vpiOperand:
\_constant: , line:65
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiOperand:
\_ref_obj: (PR), line:65
|vpiName:PR
|vpiFullName:work@div_radix16.PR
|vpiOperand:
\_operation: , line:65
|vpiOpType:33
|vpiOperand:
\_constant: , line:65
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiOperand:
\_ref_obj: (B_6), line:65
|vpiName:B_6
|vpiFullName:work@div_radix16.B_6
|vpiOperand:
\_operation: , line:65
|vpiOpType:33
|vpiOperand:
\_constant: , line:65
|vpiConstType:3
|vpiDecompile:4'b0000
|vpiSize:4
|BIN:4'b0000
|vpiOperand:
\_ref_obj: (div.divisor), line:65
|vpiName:div.divisor
|vpiFullName:work@div_radix16.div.divisor
|vpiOperand:
\_operation: , line:65
|vpiOpType:11
|vpiOperand:
\_operation: , line:65
|vpiOpType:11
|vpiOperand:
\_operation: , line:65
|vpiOpType:33
|vpiOperand:
\_constant: , line:65
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiOperand:
\_ref_obj: (PR), line:65
|vpiName:PR
|vpiFullName:work@div_radix16.PR
|vpiOperand:
\_operation: , line:65
|vpiOpType:33
|vpiOperand:
\_constant: , line:65
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiOperand:
\_ref_obj: (B_14), line:65
|vpiName:B_14
|vpiFullName:work@div_radix16.B_14
|vpiOperand:
\_operation: , line:65
|vpiOpType:33
|vpiOperand:
\_constant: , line:65
|vpiConstType:3
|vpiDecompile:4'b0000
|vpiSize:4
|BIN:4'b0000
|vpiOperand:
\_ref_obj: (div.divisor), line:65
|vpiName:div.divisor
|vpiFullName:work@div_radix16.div.divisor
|vpiLhs:
\_bit_select: (new_PR), line:65
|vpiName:new_PR
|vpiFullName:work@div_radix16.new_PR
|vpiIndex:
\_constant: , line:65
|vpiConstType:7
|vpiDecompile:6
|vpiSize:32
|INT:6
|vpiContAssign:
\_cont_assign: , line:67
|vpiRhs:
\_operation: , line:67
|vpiOpType:33
|vpiOperand:
\_bit_select: (new_PR), line:67
|vpiName:new_PR
|vpiIndex:
\_constant: , line:67
|vpiConstType:7
|vpiDecompile:6
|vpiSize:32
|INT:6
|vpiOperand:
\_bit_select: (new_PR), line:67
|vpiName:new_PR
|vpiIndex:
\_constant: , line:67
|vpiConstType:7
|vpiDecompile:5
|vpiSize:32
|INT:5
|vpiOperand:
\_bit_select: (new_PR), line:67
|vpiName:new_PR
|vpiIndex:
\_constant: , line:67
|vpiConstType:7
|vpiDecompile:4
|vpiSize:32
|INT:4
|vpiOperand:
\_bit_select: (new_PR), line:68
|vpiName:new_PR
|vpiIndex:
\_constant: , line:68
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiOperand:
\_bit_select: (new_PR), line:68
|vpiName:new_PR
|vpiIndex:
\_constant: , line:68
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiOperand:
\_bit_select: (new_PR), line:68
|vpiName:new_PR
|vpiIndex:
\_constant: , line:68
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiOperand:
\_bit_select: (new_PR), line:69
|vpiName:new_PR
|vpiIndex:
\_constant: , line:69
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiLhs:
\_ref_obj: (new_PR_sign), line:67
|vpiName:new_PR_sign
|vpiFullName:work@div_radix16.new_PR_sign
|vpiContAssign:
\_cont_assign: , line:115
|vpiRhs:
\_part_select: , line:115, parent:PR
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (PR)
|vpiLeftRange:
\_operation: , line:115
|vpiOpType:24
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:115
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:115
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiRightRange:
\_constant: , line:115
|vpiConstType:7
|vpiDecompile:4
|vpiSize:32
|INT:4
|vpiLhs:
\_ref_obj: (div.remainder), line:115
|vpiName:div.remainder
|vpiFullName:work@div_radix16.div.remainder
|vpiNet:
\_logic_net: (clk), line:27
|vpiNet:
\_logic_net: (rst), line:28
|vpiNet:
\_logic_net: (terminate), line:33
|vpiName:terminate
|vpiFullName:work@div_radix16.terminate
|vpiNetType:36
|vpiNet:
\_logic_net: (shift_count), line:34
|vpiName:shift_count
|vpiFullName:work@div_radix16.shift_count
|vpiNetType:36
|vpiNet:
\_logic_net: (PR), line:36
|vpiName:PR
|vpiFullName:work@div_radix16.PR
|vpiNetType:36
|vpiNet:
\_logic_net: (PR_lower), line:37
|vpiName:PR_lower
|vpiFullName:work@div_radix16.PR_lower
|vpiNetType:36
|vpiNet:
\_logic_net: (PR_upper), line:38
|vpiName:PR_upper
|vpiFullName:work@div_radix16.PR_upper
|vpiNetType:36
|vpiNet:
\_logic_net: (Q_lower), line:39
|vpiName:Q_lower
|vpiFullName:work@div_radix16.Q_lower
|vpiNetType:36
|vpiNet:
\_logic_net: (Q_upper), line:40
|vpiName:Q_upper
|vpiFullName:work@div_radix16.Q_upper
|vpiNetType:36
|vpiNet:
\_logic_net: (new_PR_sign), line:42
|vpiName:new_PR_sign
|vpiFullName:work@div_radix16.new_PR_sign
|vpiNetType:36
|vpiNet:
\_logic_net: (new_PR_8), line:43
|vpiName:new_PR_8
|vpiFullName:work@div_radix16.new_PR_8
|vpiNetType:36
|vpiNet:
\_logic_net: (new_PR), line:44
|vpiName:new_PR
|vpiFullName:work@div_radix16.new_PR
|vpiNetType:36
|vpiNet:
\_logic_net: (B_6), line:46
|vpiName:B_6
|vpiFullName:work@div_radix16.B_6
|vpiNetType:36
|vpiNet:
\_logic_net: (B_10), line:47
|vpiName:B_10
|vpiFullName:work@div_radix16.B_10
|vpiNetType:36
|vpiNet:
\_logic_net: (B_12), line:48
|vpiName:B_12
|vpiFullName:work@div_radix16.B_12
|vpiNetType:36
|vpiNet:
\_logic_net: (B_14), line:49
|vpiName:B_14
|vpiFullName:work@div_radix16.B_14
|vpiNetType:36
|vpiNet:
\_logic_net: (div), line:29
|vpiName:div
|vpiFullName:work@div_radix16.div
|uhdmallModules:
\_module: work@div_radix2, file:third_party/cores/taiga/core/div_algorithms/div_radix2.sv, line:25, parent:work@div_unit_core_wrapper
|vpiDefName:work@div_radix2
|vpiFullName:work@div_radix2
|vpiProcess:
\_always: , line:45
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:45
|vpiCondition:
\_operation: , line:45
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:45
|vpiName:clk
|vpiFullName:work@div_radix2.clk
|vpiStmt:
\_begin: , line:45
|vpiFullName:work@div_radix2
|vpiStmt:
\_assignment: , line:46
|vpiOpType:82
|vpiLhs:
\_ref_obj: (shift_count), line:46
|vpiName:shift_count
|vpiFullName:work@div_radix2.shift_count
|vpiRhs:
\_operation: , line:46
|vpiOpType:33
|vpiOperand:
\_part_select: , line:46, parent:shift_count
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (shift_count)
|vpiLeftRange:
\_constant: , line:46
|vpiConstType:7
|vpiDecompile:30
|vpiSize:32
|INT:30
|vpiRightRange:
\_constant: , line:46
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiOperand:
\_ref_obj: (div.start), line:46
|vpiName:div.start
|vpiProcess:
\_always: , line:49
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:49
|vpiCondition:
\_operation: , line:49
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:49
|vpiName:clk
|vpiFullName:work@div_radix2.clk
|vpiStmt:
\_begin: , line:49
|vpiFullName:work@div_radix2
|vpiStmt:
\_if_else: , line:50
|vpiCondition:
\_ref_obj: (div.start), line:50
|vpiName:div.start
|vpiFullName:work@div_radix2.div.start
|vpiStmt:
\_begin: , line:50
|vpiFullName:work@div_radix2
|vpiStmt:
\_assignment: , line:51
|vpiOpType:82
|vpiLhs:
\_ref_obj: (PR), line:51
|vpiName:PR
|vpiFullName:work@div_radix2.PR
|vpiRhs:
\_operation: , line:51
|vpiOpType:33
|vpiOperand:
\_operation: , line:51
|vpiOpType:67
|vpiOperand:
\_constant: , line:51
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiOperand:
\_ref_obj: (div.dividend), line:51
|vpiName:div.dividend
|vpiStmt:
\_assignment: , line:52
|vpiOpType:82
|vpiLhs:
\_ref_obj: (div.quotient), line:52
|vpiName:div.quotient
|vpiFullName:work@div_radix2.div.quotient
|vpiRhs:
\_operation: , line:52
|vpiOpType:33
|vpiOperand:
\_ref_obj: (div.dividend), line:52
|vpiName:div.dividend
|vpiOperand:
\_constant: , line:52
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiElseStmt:
\_if_stmt: , line:54
|vpiCondition:
\_operation: , line:54
|vpiOpType:4
|vpiOperand:
\_ref_obj: (terminate), line:54
|vpiName:terminate
|vpiFullName:work@div_radix2.terminate
|vpiStmt:
\_begin: , line:54
|vpiFullName:work@div_radix2
|vpiStmt:
\_assignment: , line:55
|vpiOpType:82
|vpiLhs:
\_ref_obj: (PR), line:55
|vpiName:PR
|vpiFullName:work@div_radix2.PR
|vpiRhs:
\_operation: , line:55
|vpiOpType:32
|vpiOperand:
\_ref_obj: (negative_sub_rst), line:55
|vpiName:negative_sub_rst
|vpiFullName:work@div_radix2.negative_sub_rst
|vpiOperand:
\_operation: , line:55
|vpiOpType:33
|vpiOperand:
\_part_select: , line:55, parent:PR
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (PR)
|vpiLeftRange:
\_operation: , line:55
|vpiOpType:11
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:55
|vpiName:div.DATA_WIDTH
|vpiFullName:work@div_radix2.div.DATA_WIDTH
|vpiOperand:
\_constant: , line:55
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:55
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiOperand:
\_ref_obj: (div.quotient), line:55
|vpiName:div.quotient
|vpiFullName:work@div_radix2.div.quotient
|vpiOperand:
\_operation: , line:55
|vpiOpType:33
|vpiOperand:
\_part_select: , line:55, parent:new_PR
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (new_PR)
|vpiLeftRange:
\_operation: , line:55
|vpiOpType:11
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:55
|vpiName:div.DATA_WIDTH
|vpiFullName:work@div_radix2.div.DATA_WIDTH
|vpiOperand:
\_constant: , line:55
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:55
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiOperand:
\_ref_obj: (div.quotient), line:55
|vpiName:div.quotient
|vpiFullName:work@div_radix2.div.quotient
|vpiStmt:
\_assignment: , line:56
|vpiOpType:82
|vpiLhs:
\_ref_obj: (div.quotient), line:56
|vpiName:div.quotient
|vpiFullName:work@div_radix2.div.quotient
|vpiRhs:
\_operation: , line:56
|vpiOpType:33
|vpiOperand:
\_ref_obj: (div.quotient), line:56
|vpiName:div.quotient
|vpiOperand:
\_operation: , line:56
|vpiOpType:4
|vpiOperand:
\_ref_obj: (negative_sub_rst), line:56
|vpiName:negative_sub_rst
|vpiProcess:
\_always: , line:62
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:62
|vpiCondition:
\_operation: , line:62
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:62
|vpiName:clk
|vpiFullName:work@div_radix2.clk
|vpiStmt:
\_begin: , line:62
|vpiFullName:work@div_radix2
|vpiStmt:
\_if_else: , line:63
|vpiCondition:
\_ref_obj: (div.start), line:63
|vpiName:div.start
|vpiFullName:work@div_radix2.div.start
|vpiStmt:
\_assignment: , line:64
|vpiOpType:82
|vpiLhs:
\_ref_obj: (div.divisor_is_zero), line:64
|vpiName:div.divisor_is_zero
|vpiFullName:work@div_radix2.div.divisor_is_zero
|vpiRhs:
\_operation: , line:64
|vpiOpType:4
|vpiOperand:
\_ref_obj: (div.divisor), line:64
|vpiName:div.divisor
|vpiFullName:work@div_radix2.div.divisor
|vpiElseStmt:
\_if_stmt: , line:65
|vpiCondition:
\_operation: , line:65
|vpiOpType:4
|vpiOperand:
\_ref_obj: (terminate), line:65
|vpiName:terminate
|vpiFullName:work@div_radix2.terminate
|vpiStmt:
\_assignment: , line:66
|vpiOpType:82
|vpiLhs:
\_ref_obj: (div.divisor_is_zero), line:66
|vpiName:div.divisor_is_zero
|vpiFullName:work@div_radix2.div.divisor_is_zero
|vpiRhs:
\_operation: , line:66
|vpiOpType:28
|vpiOperand:
\_ref_obj: (div.divisor_is_zero), line:66
|vpiName:div.divisor_is_zero
|vpiFullName:work@div_radix2.div.divisor_is_zero
|vpiOperand:
\_operation: , line:66
|vpiOpType:4
|vpiOperand:
\_ref_obj: (negative_sub_rst), line:66
|vpiName:negative_sub_rst
|vpiFullName:work@div_radix2.negative_sub_rst
|vpiProcess:
\_always: , line:69
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:69
|vpiCondition:
\_operation: , line:69
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:69
|vpiName:clk
|vpiFullName:work@div_radix2.clk
|vpiStmt:
\_begin: , line:69
|vpiFullName:work@div_radix2
|vpiStmt:
\_if_else: , line:70
|vpiCondition:
\_ref_obj: (rst), line:70
|vpiName:rst
|vpiFullName:work@div_radix2.rst
|vpiStmt:
\_assignment: , line:71
|vpiOpType:82
|vpiLhs:
\_ref_obj: (terminate), line:71
|vpiName:terminate
|vpiFullName:work@div_radix2.terminate
|vpiRhs:
\_constant: , line:71
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiElseStmt:
\_begin: , line:72
|vpiFullName:work@div_radix2
|vpiStmt:
\_if_stmt: , line:73
|vpiCondition:
\_ref_obj: (div.start), line:73
|vpiName:div.start
|vpiFullName:work@div_radix2.div.start
|vpiStmt:
\_assignment: , line:74
|vpiOpType:82
|vpiLhs:
\_ref_obj: (terminate), line:74
|vpiName:terminate
|vpiFullName:work@div_radix2.terminate
|vpiRhs:
\_constant: , line:74
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiStmt:
\_if_stmt: , line:75
|vpiCondition:
\_bit_select: (shift_count), line:75
|vpiName:shift_count
|vpiFullName:work@div_radix2.shift_count
|vpiIndex:
\_constant: , line:75
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiStmt:
\_assignment: , line:76
|vpiOpType:82
|vpiLhs:
\_ref_obj: (terminate), line:76
|vpiName:terminate
|vpiFullName:work@div_radix2.terminate
|vpiRhs:
\_constant: , line:76
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiProcess:
\_always: , line:80
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:80
|vpiCondition:
\_operation: , line:80
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:80
|vpiName:clk
|vpiFullName:work@div_radix2.clk
|vpiStmt:
\_begin: , line:80
|vpiFullName:work@div_radix2
|vpiStmt:
\_if_else: , line:81
|vpiCondition:
\_ref_obj: (rst), line:81
|vpiName:rst
|vpiFullName:work@div_radix2.rst
|vpiStmt:
\_assignment: , line:82
|vpiOpType:82
|vpiLhs:
\_ref_obj: (div.done), line:82
|vpiName:div.done
|vpiFullName:work@div_radix2.div.done
|vpiRhs:
\_constant: , line:82
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiElseStmt:
\_begin: , line:83
|vpiFullName:work@div_radix2
|vpiStmt:
\_if_else: , line:84
|vpiCondition:
\_bit_select: (shift_count), line:84
|vpiName:shift_count
|vpiFullName:work@div_radix2.shift_count
|vpiIndex:
\_constant: , line:84
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiStmt:
\_assignment: , line:85
|vpiOpType:82
|vpiLhs:
\_ref_obj: (div.done), line:85
|vpiName:div.done
|vpiFullName:work@div_radix2.div.done
|vpiRhs:
\_constant: , line:85
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiElseStmt:
\_if_stmt: , line:86
|vpiCondition:
\_ref_obj: (div.done), line:86
|vpiName:div.done
|vpiFullName:work@div_radix2.div.done
|vpiStmt:
\_assignment: , line:87
|vpiOpType:82
|vpiLhs:
\_ref_obj: (div.done), line:87
|vpiName:div.done
|vpiFullName:work@div_radix2.div.done
|vpiRhs:
\_constant: , line:87
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiPort:
\_port: (clk), line:27
|vpiName:clk
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (clk), line:27
|vpiName:clk
|vpiFullName:work@div_radix2.clk
|vpiNetType:36
|vpiPort:
\_port: (rst), line:28
|vpiName:rst
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (rst), line:28
|vpiName:rst
|vpiFullName:work@div_radix2.rst
|vpiNetType:36
|vpiPort:
\_port: (div), line:29
|vpiName:div
|vpiDirection:5
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_modport: (divider)
|vpiContAssign:
\_cont_assign: , line:41
|vpiRhs:
\_operation: , line:41
|vpiOpType:11
|vpiOperand:
\_ref_obj: (PR), line:41
|vpiName:PR
|vpiFullName:work@div_radix2.PR
|vpiOperand:
\_operation: , line:41
|vpiOpType:33
|vpiOperand:
\_constant: , line:41
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiOperand:
\_ref_obj: (div.divisor), line:41
|vpiName:div.divisor
|vpiFullName:work@div_radix2.div.divisor
|vpiLhs:
\_ref_obj: (new_PR), line:41
|vpiName:new_PR
|vpiFullName:work@div_radix2.new_PR
|vpiContAssign:
\_cont_assign: , line:42
|vpiRhs:
\_bit_select: (new_PR), line:42
|vpiName:new_PR
|vpiFullName:work@div_radix2.new_PR
|vpiIndex:
\_ref_obj: (div.DATA_WIDTH), line:42
|vpiName:div.DATA_WIDTH
|vpiLhs:
\_ref_obj: (negative_sub_rst), line:42
|vpiName:negative_sub_rst
|vpiFullName:work@div_radix2.negative_sub_rst
|vpiContAssign:
\_cont_assign: , line:60
|vpiRhs:
\_part_select: , line:60, parent:PR
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (PR)
|vpiLeftRange:
\_ref_obj: (div.DATA_WIDTH), line:60
|vpiName:div.DATA_WIDTH
|vpiRightRange:
\_constant: , line:60
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiLhs:
\_ref_obj: (div.remainder), line:60
|vpiName:div.remainder
|vpiFullName:work@div_radix2.div.remainder
|vpiNet:
\_logic_net: (clk), line:27
|vpiNet:
\_logic_net: (rst), line:28
|vpiNet:
\_logic_net: (terminate), line:32
|vpiName:terminate
|vpiFullName:work@div_radix2.terminate
|vpiNetType:36
|vpiNet:
\_logic_net: (new_PR), line:34
|vpiName:new_PR
|vpiFullName:work@div_radix2.new_PR
|vpiNetType:36
|vpiNet:
\_logic_net: (PR), line:35
|vpiName:PR
|vpiFullName:work@div_radix2.PR
|vpiNetType:36
|vpiNet:
\_logic_net: (shift_count), line:36
|vpiName:shift_count
|vpiFullName:work@div_radix2.shift_count
|vpiNetType:36
|vpiNet:
\_logic_net: (negative_sub_rst), line:37
|vpiName:negative_sub_rst
|vpiFullName:work@div_radix2.negative_sub_rst
|vpiNetType:36
|vpiNet:
\_logic_net: (div), line:29
|vpiName:div
|vpiFullName:work@div_radix2.div
|uhdmallModules:
\_module: work@div_radix2_ET, file:third_party/cores/taiga/core/div_algorithms/div_radix2_ET.sv, line:25, parent:work@div_unit_core_wrapper
|vpiDefName:work@div_radix2_ET
|vpiFullName:work@div_radix2_ET
|vpiProcess:
\_always: , line:47
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:47
|vpiCondition:
\_operation: , line:47
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:47
|vpiName:clk
|vpiFullName:work@div_radix2_ET.clk
|vpiStmt:
\_begin: , line:47
|vpiFullName:work@div_radix2_ET
|vpiStmt:
\_assignment: , line:48
|vpiOpType:82
|vpiLhs:
\_ref_obj: (shift_count), line:48
|vpiName:shift_count
|vpiFullName:work@div_radix2_ET.shift_count
|vpiRhs:
\_operation: , line:48
|vpiOpType:33
|vpiOperand:
\_part_select: , line:48, parent:shift_count
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (shift_count)
|vpiLeftRange:
\_constant: , line:48
|vpiConstType:7
|vpiDecompile:30
|vpiSize:32
|INT:30
|vpiRightRange:
\_constant: , line:48
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiOperand:
\_operation: , line:48
|vpiOpType:28
|vpiOperand:
\_ref_obj: (div.start), line:48
|vpiName:div.start
|vpiOperand:
\_operation: , line:48
|vpiOpType:4
|vpiOperand:
\_ref_obj: (terminate_early), line:48
|vpiName:terminate_early
|vpiProcess:
\_always: , line:53
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:53
|vpiCondition:
\_operation: , line:53
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:53
|vpiName:clk
|vpiFullName:work@div_radix2_ET.clk
|vpiStmt:
\_begin: , line:53
|vpiFullName:work@div_radix2_ET
|vpiStmt:
\_if_else: , line:54
|vpiCondition:
\_ref_obj: (div.start), line:54
|vpiName:div.start
|vpiFullName:work@div_radix2_ET.div.start
|vpiStmt:
\_begin: , line:54
|vpiFullName:work@div_radix2_ET
|vpiStmt:
\_if_else: , line:55
|vpiCondition:
\_ref_obj: (terminate_early), line:55
|vpiName:terminate_early
|vpiFullName:work@div_radix2_ET.terminate_early
|vpiStmt:
\_begin: , line:55
|vpiFullName:work@div_radix2_ET
|vpiStmt:
\_assignment: , line:56
|vpiOpType:82
|vpiLhs:
\_ref_obj: (PR), line:56
|vpiName:PR
|vpiFullName:work@div_radix2_ET.PR
|vpiRhs:
\_operation: , line:56
|vpiOpType:33
|vpiOperand:
\_ref_obj: (div.dividend), line:56
|vpiName:div.dividend
|vpiOperand:
\_constant: , line:56
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiStmt:
\_assignment: , line:57
|vpiOpType:82
|vpiLhs:
\_ref_obj: (div.quotient), line:57
|vpiName:div.quotient
|vpiFullName:work@div_radix2_ET.div.quotient
|vpiRhs:
\_constant: , line:57
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiElseStmt:
\_begin: , line:58
|vpiFullName:work@div_radix2_ET
|vpiStmt:
\_assignment: , line:59
|vpiOpType:82
|vpiLhs:
\_ref_obj: (PR), line:59
|vpiName:PR
|vpiFullName:work@div_radix2_ET.PR
|vpiRhs:
\_operation: , line:59
|vpiOpType:33
|vpiOperand:
\_operation: , line:59
|vpiOpType:67
|vpiOperand:
\_constant: , line:59
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiOperand:
\_ref_obj: (div.dividend), line:59
|vpiName:div.dividend
|vpiStmt:
\_assignment: , line:60
|vpiOpType:82
|vpiLhs:
\_ref_obj: (div.quotient), line:60
|vpiName:div.quotient
|vpiFullName:work@div_radix2_ET.div.quotient
|vpiRhs:
\_operation: , line:60
|vpiOpType:33
|vpiOperand:
\_ref_obj: (div.dividend), line:60
|vpiName:div.dividend
|vpiOperand:
\_constant: , line:60
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiElseStmt:
\_if_stmt: , line:62
|vpiCondition:
\_operation: , line:62
|vpiOpType:4
|vpiOperand:
\_ref_obj: (terminate), line:62
|vpiName:terminate
|vpiFullName:work@div_radix2_ET.terminate
|vpiStmt:
\_begin: , line:62
|vpiFullName:work@div_radix2_ET
|vpiStmt:
\_assignment: , line:63
|vpiOpType:82
|vpiLhs:
\_ref_obj: (PR), line:63
|vpiName:PR
|vpiFullName:work@div_radix2_ET.PR
|vpiRhs:
\_operation: , line:63
|vpiOpType:32
|vpiOperand:
\_ref_obj: (negative_sub_rst), line:63
|vpiName:negative_sub_rst
|vpiFullName:work@div_radix2_ET.negative_sub_rst
|vpiOperand:
\_operation: , line:63
|vpiOpType:33
|vpiOperand:
\_part_select: , line:63, parent:PR
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (PR)
|vpiLeftRange:
\_operation: , line:63
|vpiOpType:11
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:63
|vpiName:div.DATA_WIDTH
|vpiFullName:work@div_radix2_ET.div.DATA_WIDTH
|vpiOperand:
\_constant: , line:63
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:63
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiOperand:
\_ref_obj: (div.quotient), line:63
|vpiName:div.quotient
|vpiFullName:work@div_radix2_ET.div.quotient
|vpiOperand:
\_operation: , line:63
|vpiOpType:33
|vpiOperand:
\_part_select: , line:63, parent:new_PR
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (new_PR)
|vpiLeftRange:
\_operation: , line:63
|vpiOpType:11
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:63
|vpiName:div.DATA_WIDTH
|vpiFullName:work@div_radix2_ET.div.DATA_WIDTH
|vpiOperand:
\_constant: , line:63
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:63
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiOperand:
\_ref_obj: (div.quotient), line:63
|vpiName:div.quotient
|vpiFullName:work@div_radix2_ET.div.quotient
|vpiStmt:
\_assignment: , line:64
|vpiOpType:82
|vpiLhs:
\_ref_obj: (div.quotient), line:64
|vpiName:div.quotient
|vpiFullName:work@div_radix2_ET.div.quotient
|vpiRhs:
\_operation: , line:64
|vpiOpType:33
|vpiOperand:
\_ref_obj: (div.quotient), line:64
|vpiName:div.quotient
|vpiOperand:
\_operation: , line:64
|vpiOpType:4
|vpiOperand:
\_ref_obj: (negative_sub_rst), line:64
|vpiName:negative_sub_rst
|vpiProcess:
\_always: , line:70
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:70
|vpiCondition:
\_operation: , line:70
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:70
|vpiName:clk
|vpiFullName:work@div_radix2_ET.clk
|vpiStmt:
\_begin: , line:70
|vpiFullName:work@div_radix2_ET
|vpiStmt:
\_if_else: , line:71
|vpiCondition:
\_ref_obj: (div.start), line:71
|vpiName:div.start
|vpiFullName:work@div_radix2_ET.div.start
|vpiStmt:
\_assignment: , line:72
|vpiOpType:82
|vpiLhs:
\_ref_obj: (div.divisor_is_zero), line:72
|vpiName:div.divisor_is_zero
|vpiFullName:work@div_radix2_ET.div.divisor_is_zero
|vpiRhs:
\_operation: , line:72
|vpiOpType:4
|vpiOperand:
\_ref_obj: (div.divisor), line:72
|vpiName:div.divisor
|vpiFullName:work@div_radix2_ET.div.divisor
|vpiElseStmt:
\_if_stmt: , line:73
|vpiCondition:
\_operation: , line:73
|vpiOpType:4
|vpiOperand:
\_ref_obj: (terminate), line:73
|vpiName:terminate
|vpiFullName:work@div_radix2_ET.terminate
|vpiStmt:
\_assignment: , line:74
|vpiOpType:82
|vpiLhs:
\_ref_obj: (div.divisor_is_zero), line:74
|vpiName:div.divisor_is_zero
|vpiFullName:work@div_radix2_ET.div.divisor_is_zero
|vpiRhs:
\_operation: , line:74
|vpiOpType:28
|vpiOperand:
\_ref_obj: (div.divisor_is_zero), line:74
|vpiName:div.divisor_is_zero
|vpiFullName:work@div_radix2_ET.div.divisor_is_zero
|vpiOperand:
\_operation: , line:74
|vpiOpType:4
|vpiOperand:
\_ref_obj: (negative_sub_rst), line:74
|vpiName:negative_sub_rst
|vpiFullName:work@div_radix2_ET.negative_sub_rst
|vpiProcess:
\_always: , line:77
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:77
|vpiCondition:
\_operation: , line:77
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:77
|vpiName:clk
|vpiFullName:work@div_radix2_ET.clk
|vpiStmt:
\_begin: , line:77
|vpiFullName:work@div_radix2_ET
|vpiStmt:
\_if_else: , line:78
|vpiCondition:
\_ref_obj: (rst), line:78
|vpiName:rst
|vpiFullName:work@div_radix2_ET.rst
|vpiStmt:
\_assignment: , line:79
|vpiOpType:82
|vpiLhs:
\_ref_obj: (terminate), line:79
|vpiName:terminate
|vpiFullName:work@div_radix2_ET.terminate
|vpiRhs:
\_constant: , line:79
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiElseStmt:
\_begin: , line:80
|vpiFullName:work@div_radix2_ET
|vpiStmt:
\_if_stmt: , line:81
|vpiCondition:
\_ref_obj: (div.start), line:81
|vpiName:div.start
|vpiFullName:work@div_radix2_ET.div.start
|vpiStmt:
\_begin: , line:81
|vpiFullName:work@div_radix2_ET
|vpiStmt:
\_if_else: , line:82
|vpiCondition:
\_ref_obj: (terminate_early), line:82
|vpiName:terminate_early
|vpiFullName:work@div_radix2_ET.terminate_early
|vpiStmt:
\_begin: , line:82
|vpiFullName:work@div_radix2_ET
|vpiStmt:
\_assignment: , line:83
|vpiOpType:82
|vpiLhs:
\_ref_obj: (terminate), line:83
|vpiName:terminate
|vpiFullName:work@div_radix2_ET.terminate
|vpiRhs:
\_constant: , line:83
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiElseStmt:
\_begin: , line:84
|vpiFullName:work@div_radix2_ET
|vpiStmt:
\_assignment: , line:85
|vpiOpType:82
|vpiLhs:
\_ref_obj: (terminate), line:85
|vpiName:terminate
|vpiFullName:work@div_radix2_ET.terminate
|vpiRhs:
\_constant: , line:85
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiStmt:
\_if_stmt: , line:88
|vpiCondition:
\_bit_select: (shift_count), line:88
|vpiName:shift_count
|vpiFullName:work@div_radix2_ET.shift_count
|vpiIndex:
\_constant: , line:88
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiStmt:
\_assignment: , line:89
|vpiOpType:82
|vpiLhs:
\_ref_obj: (terminate), line:89
|vpiName:terminate
|vpiFullName:work@div_radix2_ET.terminate
|vpiRhs:
\_constant: , line:89
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiProcess:
\_always: , line:93
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:93
|vpiCondition:
\_operation: , line:93
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:93
|vpiName:clk
|vpiFullName:work@div_radix2_ET.clk
|vpiStmt:
\_begin: , line:93
|vpiFullName:work@div_radix2_ET
|vpiStmt:
\_if_else: , line:94
|vpiCondition:
\_ref_obj: (rst), line:94
|vpiName:rst
|vpiFullName:work@div_radix2_ET.rst
|vpiStmt:
\_assignment: , line:95
|vpiOpType:82
|vpiLhs:
\_ref_obj: (div.done), line:95
|vpiName:div.done
|vpiFullName:work@div_radix2_ET.div.done
|vpiRhs:
\_constant: , line:95
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiElseStmt:
\_begin: , line:96
|vpiFullName:work@div_radix2_ET
|vpiStmt:
\_if_else: , line:97
|vpiCondition:
\_ref_obj: (div.done), line:97
|vpiName:div.done
|vpiFullName:work@div_radix2_ET.div.done
|vpiStmt:
\_assignment: , line:98
|vpiOpType:82
|vpiLhs:
\_ref_obj: (div.done), line:98
|vpiName:div.done
|vpiFullName:work@div_radix2_ET.div.done
|vpiRhs:
\_constant: , line:98
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiElseStmt:
\_if_stmt: , line:99
|vpiCondition:
\_operation: , line:99
|vpiOpType:29
|vpiOperand:
\_operation: , line:99
|vpiOpType:28
|vpiOperand:
\_operation: , line:99
|vpiOpType:4
|vpiOperand:
\_ref_obj: (div.start), line:99
|vpiName:div.start
|vpiFullName:work@div_radix2_ET.div.start
|vpiOperand:
\_bit_select: (shift_count), line:99
|vpiName:shift_count
|vpiFullName:work@div_radix2_ET.shift_count
|vpiIndex:
\_constant: , line:99
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiOperand:
\_operation: , line:99
|vpiOpType:28
|vpiOperand:
\_ref_obj: (div.start), line:99
|vpiName:div.start
|vpiFullName:work@div_radix2_ET.div.start
|vpiOperand:
\_ref_obj: (terminate_early), line:99
|vpiName:terminate_early
|vpiFullName:work@div_radix2_ET.terminate_early
|vpiStmt:
\_assignment: , line:100
|vpiOpType:82
|vpiLhs:
\_ref_obj: (div.done), line:100
|vpiName:div.done
|vpiFullName:work@div_radix2_ET.div.done
|vpiRhs:
\_constant: , line:100
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiPort:
\_port: (clk), line:27
|vpiName:clk
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (clk), line:27
|vpiName:clk
|vpiFullName:work@div_radix2_ET.clk
|vpiNetType:36
|vpiPort:
\_port: (rst), line:28
|vpiName:rst
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (rst), line:28
|vpiName:rst
|vpiFullName:work@div_radix2_ET.rst
|vpiNetType:36
|vpiPort:
\_port: (div), line:29
|vpiName:div
|vpiDirection:5
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_modport: (divider)
|vpiContAssign:
\_cont_assign: , line:44
|vpiRhs:
\_operation: , line:44
|vpiOpType:11
|vpiOperand:
\_ref_obj: (PR), line:44
|vpiName:PR
|vpiFullName:work@div_radix2_ET.PR
|vpiOperand:
\_operation: , line:44
|vpiOpType:33
|vpiOperand:
\_constant: , line:44
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiOperand:
\_ref_obj: (div.divisor), line:44
|vpiName:div.divisor
|vpiFullName:work@div_radix2_ET.div.divisor
|vpiLhs:
\_ref_obj: (new_PR), line:44
|vpiName:new_PR
|vpiFullName:work@div_radix2_ET.new_PR
|vpiContAssign:
\_cont_assign: , line:45
|vpiRhs:
\_bit_select: (new_PR), line:45
|vpiName:new_PR
|vpiFullName:work@div_radix2_ET.new_PR
|vpiIndex:
\_ref_obj: (div.DATA_WIDTH), line:45
|vpiName:div.DATA_WIDTH
|vpiLhs:
\_ref_obj: (negative_sub_rst), line:45
|vpiName:negative_sub_rst
|vpiFullName:work@div_radix2_ET.negative_sub_rst
|vpiContAssign:
\_cont_assign: , line:51
|vpiRhs:
\_operation: , line:51
|vpiOpType:18
|vpiOperand:
\_ref_obj: (div.divisor), line:51
|vpiName:div.divisor
|vpiFullName:work@div_radix2_ET.div.divisor
|vpiOperand:
\_ref_obj: (div.dividend), line:51
|vpiName:div.dividend
|vpiFullName:work@div_radix2_ET.div.dividend
|vpiLhs:
\_ref_obj: (terminate_early), line:51
|vpiName:terminate_early
|vpiFullName:work@div_radix2_ET.terminate_early
|vpiContAssign:
\_cont_assign: , line:68
|vpiRhs:
\_part_select: , line:68, parent:PR
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (PR)
|vpiLeftRange:
\_ref_obj: (div.DATA_WIDTH), line:68
|vpiName:div.DATA_WIDTH
|vpiRightRange:
\_constant: , line:68
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiLhs:
\_ref_obj: (div.remainder), line:68
|vpiName:div.remainder
|vpiFullName:work@div_radix2_ET.div.remainder
|vpiNet:
\_logic_net: (clk), line:27
|vpiNet:
\_logic_net: (rst), line:28
|vpiNet:
\_logic_net: (terminate), line:32
|vpiName:terminate
|vpiFullName:work@div_radix2_ET.terminate
|vpiNetType:36
|vpiNet:
\_logic_net: (terminate_early), line:33
|vpiName:terminate_early
|vpiFullName:work@div_radix2_ET.terminate_early
|vpiNetType:36
|vpiNet:
\_logic_net: (new_PR), line:35
|vpiName:new_PR
|vpiFullName:work@div_radix2_ET.new_PR
|vpiNetType:36
|vpiNet:
\_logic_net: (PR), line:36
|vpiName:PR
|vpiFullName:work@div_radix2_ET.PR
|vpiNetType:36
|vpiNet:
\_logic_net: (shift_count), line:38
|vpiName:shift_count
|vpiFullName:work@div_radix2_ET.shift_count
|vpiNetType:36
|vpiNet:
\_logic_net: (negative_sub_rst), line:40
|vpiName:negative_sub_rst
|vpiFullName:work@div_radix2_ET.negative_sub_rst
|vpiNetType:36
|vpiNet:
\_logic_net: (div), line:29
|vpiName:div
|vpiFullName:work@div_radix2_ET.div
|uhdmallModules:
\_module: work@div_radix2_ET_full, file:third_party/cores/taiga/core/div_algorithms/div_radix2_ET_full.sv, line:25, parent:work@div_unit_core_wrapper
|vpiDefName:work@div_radix2_ET_full
|vpiFullName:work@div_radix2_ET_full
|vpiProcess:
\_always: , line:54
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:54
|vpiCondition:
\_operation: , line:54
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:54
|vpiName:clk
|vpiFullName:work@div_radix2_ET_full.clk
|vpiStmt:
\_begin: , line:54
|vpiFullName:work@div_radix2_ET_full
|vpiStmt:
\_if_else: , line:55
|vpiCondition:
\_ref_obj: (div.start), line:55
|vpiName:div.start
|vpiFullName:work@div_radix2_ET_full.div.start
|vpiStmt:
\_assignment: , line:56
|vpiOpType:82
|vpiLhs:
\_ref_obj: (shift_count), line:56
|vpiName:shift_count
|vpiFullName:work@div_radix2_ET_full.shift_count
|vpiRhs:
\_constant: , line:56
|vpiConstType:3
|vpiDecompile:32'd1
|BIN:32'd1
|vpiElseStmt:
\_assignment: , line:58
|vpiOpType:82
|vpiLhs:
\_ref_obj: (shift_count), line:58
|vpiName:shift_count
|vpiFullName:work@div_radix2_ET_full.shift_count
|vpiRhs:
\_operation: , line:58
|vpiOpType:33
|vpiOperand:
\_part_select: , line:58, parent:shift_count
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (shift_count)
|vpiLeftRange:
\_constant: , line:58
|vpiConstType:7
|vpiDecompile:30
|vpiSize:32
|INT:30
|vpiRightRange:
\_constant: , line:58
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiOperand:
\_ref_obj: (div.start), line:58
|vpiName:div.start
|vpiProcess:
\_always: , line:61
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:61
|vpiCondition:
\_operation: , line:61
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:61
|vpiName:clk
|vpiFullName:work@div_radix2_ET_full.clk
|vpiStmt:
\_begin: , line:61
|vpiFullName:work@div_radix2_ET_full
|vpiStmt:
\_if_else: , line:62
|vpiCondition:
\_ref_obj: (div.start), line:62
|vpiName:div.start
|vpiFullName:work@div_radix2_ET_full.div.start
|vpiStmt:
\_begin: , line:62
|vpiFullName:work@div_radix2_ET_full
|vpiStmt:
\_assignment: , line:63
|vpiOpType:82
|vpiLhs:
\_ref_obj: (shift_num_R), line:63
|vpiName:shift_num_R
|vpiFullName:work@div_radix2_ET_full.shift_num_R
|vpiRhs:
\_constant: , line:63
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiStmt:
\_assignment: , line:64
|vpiOpType:82
|vpiLhs:
\_ref_obj: (shift_num_Q), line:64
|vpiName:shift_num_Q
|vpiFullName:work@div_radix2_ET_full.shift_num_Q
|vpiRhs:
\_constant: , line:64
|vpiConstType:7
|vpiDecompile:32
|vpiSize:32
|INT:32
|vpiElseStmt:
\_if_stmt: , line:66
|vpiCondition:
\_operation: , line:66
|vpiOpType:28
|vpiOperand:
\_operation: , line:66
|vpiOpType:4
|vpiOperand:
\_ref_obj: (terminate), line:66
|vpiName:terminate
|vpiFullName:work@div_radix2_ET_full.terminate
|vpiOperand:
\_operation: , line:66
|vpiOpType:4
|vpiOperand:
\_ref_obj: (terminate_early), line:66
|vpiName:terminate_early
|vpiFullName:work@div_radix2_ET_full.terminate_early
|vpiStmt:
\_begin: , line:66
|vpiFullName:work@div_radix2_ET_full
|vpiStmt:
\_assignment: , line:67
|vpiOpType:82
|vpiLhs:
\_ref_obj: (shift_num_R), line:67
|vpiName:shift_num_R
|vpiFullName:work@div_radix2_ET_full.shift_num_R
|vpiRhs:
\_operation: , line:67
|vpiOpType:24
|vpiOperand:
\_ref_obj: (shift_num_R), line:67
|vpiName:shift_num_R
|vpiFullName:work@div_radix2_ET_full.shift_num_R
|vpiOperand:
\_constant: , line:67
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiStmt:
\_assignment: , line:68
|vpiOpType:82
|vpiLhs:
\_ref_obj: (shift_num_Q), line:68
|vpiName:shift_num_Q
|vpiFullName:work@div_radix2_ET_full.shift_num_Q
|vpiRhs:
\_operation: , line:68
|vpiOpType:11
|vpiOperand:
\_ref_obj: (shift_num_Q), line:68
|vpiName:shift_num_Q
|vpiFullName:work@div_radix2_ET_full.shift_num_Q
|vpiOperand:
\_constant: , line:68
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiProcess:
\_always: , line:78
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:78
|vpiCondition:
\_operation: , line:78
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:78
|vpiName:clk
|vpiFullName:work@div_radix2_ET_full.clk
|vpiStmt:
\_begin: , line:78
|vpiFullName:work@div_radix2_ET_full
|vpiStmt:
\_if_else: , line:79
|vpiCondition:
\_ref_obj: (div.start), line:79
|vpiName:div.start
|vpiFullName:work@div_radix2_ET_full.div.start
|vpiStmt:
\_begin: , line:79
|vpiFullName:work@div_radix2_ET_full
|vpiStmt:
\_assignment: , line:80
|vpiOpType:82
|vpiLhs:
\_ref_obj: (PR), line:80
|vpiName:PR
|vpiFullName:work@div_radix2_ET_full.PR
|vpiRhs:
\_operation: , line:80
|vpiOpType:33
|vpiOperand:
\_operation: , line:80
|vpiOpType:67
|vpiOperand:
\_constant: , line:80
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiOperand:
\_ref_obj: (div.dividend), line:80
|vpiName:div.dividend
|vpiStmt:
\_assignment: , line:81
|vpiOpType:82
|vpiLhs:
\_ref_obj: (Q_temp), line:81
|vpiName:Q_temp
|vpiFullName:work@div_radix2_ET_full.Q_temp
|vpiRhs:
\_constant: , line:81
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiStmt:
\_assignment: , line:82
|vpiOpType:82
|vpiLhs:
\_ref_obj: (AR_r), line:82
|vpiName:AR_r
|vpiFullName:work@div_radix2_ET_full.AR_r
|vpiRhs:
\_operation: , line:82
|vpiOpType:33
|vpiOperand:
\_ref_obj: (div.dividend), line:82
|vpiName:div.dividend
|vpiOperand:
\_constant: , line:82
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiElseStmt:
\_if_stmt: , line:84
|vpiCondition:
\_operation: , line:84
|vpiOpType:28
|vpiOperand:
\_operation: , line:84
|vpiOpType:4
|vpiOperand:
\_ref_obj: (terminate), line:84
|vpiName:terminate
|vpiFullName:work@div_radix2_ET_full.terminate
|vpiOperand:
\_operation: , line:84
|vpiOpType:4
|vpiOperand:
\_ref_obj: (terminate_early), line:84
|vpiName:terminate_early
|vpiFullName:work@div_radix2_ET_full.terminate_early
|vpiStmt:
\_begin: , line:84
|vpiFullName:work@div_radix2_ET_full
|vpiStmt:
\_assignment: , line:85
|vpiOpType:82
|vpiLhs:
\_ref_obj: (PR), line:85
|vpiName:PR
|vpiFullName:work@div_radix2_ET_full.PR
|vpiRhs:
\_operation: , line:85
|vpiOpType:32
|vpiOperand:
\_ref_obj: (negative_sub_rst), line:85
|vpiName:negative_sub_rst
|vpiFullName:work@div_radix2_ET_full.negative_sub_rst
|vpiOperand:
\_operation: , line:85
|vpiOpType:33
|vpiOperand:
\_part_select: , line:85, parent:PR
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (PR)
|vpiLeftRange:
\_operation: , line:85
|vpiOpType:11
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:85
|vpiName:div.DATA_WIDTH
|vpiFullName:work@div_radix2_ET_full.div.DATA_WIDTH
|vpiOperand:
\_constant: , line:85
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:85
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiOperand:
\_bit_select: (AR_r), line:85
|vpiName:AR_r
|vpiIndex:
\_operation: , line:85
|vpiOpType:11
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:85
|vpiName:div.DATA_WIDTH
|vpiFullName:work@div_radix2_ET_full.div.DATA_WIDTH
|vpiOperand:
\_constant: , line:85
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiOperand:
\_operation: , line:86
|vpiOpType:33
|vpiOperand:
\_part_select: , line:86, parent:new_PR
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (new_PR)
|vpiLeftRange:
\_operation: , line:86
|vpiOpType:11
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:86
|vpiName:div.DATA_WIDTH
|vpiFullName:work@div_radix2_ET_full.div.DATA_WIDTH
|vpiOperand:
\_constant: , line:86
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:86
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiOperand:
\_bit_select: (AR_r), line:86
|vpiName:AR_r
|vpiIndex:
\_operation: , line:86
|vpiOpType:11
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:86
|vpiName:div.DATA_WIDTH
|vpiFullName:work@div_radix2_ET_full.div.DATA_WIDTH
|vpiOperand:
\_constant: , line:86
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiStmt:
\_assignment: , line:87
|vpiOpType:82
|vpiLhs:
\_ref_obj: (Q_temp), line:87
|vpiName:Q_temp
|vpiFullName:work@div_radix2_ET_full.Q_temp
|vpiRhs:
\_operation: , line:87
|vpiOpType:33
|vpiOperand:
\_part_select: , line:87, parent:Q_temp
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (Q_temp)
|vpiLeftRange:
\_operation: , line:87
|vpiOpType:11
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:87
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:87
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiRightRange:
\_constant: , line:87
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiOperand:
\_operation: , line:87
|vpiOpType:4
|vpiOperand:
\_ref_obj: (negative_sub_rst), line:87
|vpiName:negative_sub_rst
|vpiStmt:
\_assignment: , line:88
|vpiOpType:82
|vpiLhs:
\_ref_obj: (AR_r), line:88
|vpiName:AR_r
|vpiFullName:work@div_radix2_ET_full.AR_r
|vpiRhs:
\_operation: , line:88
|vpiOpType:33
|vpiOperand:
\_part_select: , line:88, parent:AR_r
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (AR_r)
|vpiLeftRange:
\_operation: , line:88
|vpiOpType:11
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:88
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:88
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiRightRange:
\_constant: , line:88
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiOperand:
\_constant: , line:88
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiProcess:
\_always: , line:92
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:92
|vpiCondition:
\_operation: , line:92
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:92
|vpiName:clk
|vpiFullName:work@div_radix2_ET_full.clk
|vpiStmt:
\_begin: , line:92
|vpiFullName:work@div_radix2_ET_full
|vpiStmt:
\_if_else: , line:93
|vpiCondition:
\_ref_obj: (div.start), line:93
|vpiName:div.start
|vpiFullName:work@div_radix2_ET_full.div.start
|vpiStmt:
\_assignment: , line:94
|vpiOpType:82
|vpiLhs:
\_ref_obj: (div.divisor_is_zero), line:94
|vpiName:div.divisor_is_zero
|vpiFullName:work@div_radix2_ET_full.div.divisor_is_zero
|vpiRhs:
\_operation: , line:94
|vpiOpType:4
|vpiOperand:
\_ref_obj: (div.divisor), line:94
|vpiName:div.divisor
|vpiFullName:work@div_radix2_ET_full.div.divisor
|vpiElseStmt:
\_if_stmt: , line:95
|vpiCondition:
\_operation: , line:95
|vpiOpType:4
|vpiOperand:
\_ref_obj: (terminate), line:95
|vpiName:terminate
|vpiFullName:work@div_radix2_ET_full.terminate
|vpiStmt:
\_assignment: , line:96
|vpiOpType:82
|vpiLhs:
\_ref_obj: (div.divisor_is_zero), line:96
|vpiName:div.divisor_is_zero
|vpiFullName:work@div_radix2_ET_full.div.divisor_is_zero
|vpiRhs:
\_operation: , line:96
|vpiOpType:28
|vpiOperand:
\_ref_obj: (div.divisor_is_zero), line:96
|vpiName:div.divisor_is_zero
|vpiFullName:work@div_radix2_ET_full.div.divisor_is_zero
|vpiOperand:
\_operation: , line:96
|vpiOpType:4
|vpiOperand:
\_ref_obj: (negative_sub_rst), line:96
|vpiName:negative_sub_rst
|vpiFullName:work@div_radix2_ET_full.negative_sub_rst
|vpiProcess:
\_always: , line:99
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:99
|vpiCondition:
\_operation: , line:99
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:99
|vpiName:clk
|vpiFullName:work@div_radix2_ET_full.clk
|vpiStmt:
\_begin: , line:99
|vpiFullName:work@div_radix2_ET_full
|vpiStmt:
\_if_else: , line:100
|vpiCondition:
\_ref_obj: (rst), line:100
|vpiName:rst
|vpiFullName:work@div_radix2_ET_full.rst
|vpiStmt:
\_assignment: , line:101
|vpiOpType:82
|vpiLhs:
\_ref_obj: (terminate), line:101
|vpiName:terminate
|vpiFullName:work@div_radix2_ET_full.terminate
|vpiRhs:
\_constant: , line:101
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiElseStmt:
\_begin: , line:102
|vpiFullName:work@div_radix2_ET_full
|vpiStmt:
\_if_else: , line:103
|vpiCondition:
\_ref_obj: (div.start), line:103
|vpiName:div.start
|vpiFullName:work@div_radix2_ET_full.div.start
|vpiStmt:
\_assignment: , line:104
|vpiOpType:82
|vpiLhs:
\_ref_obj: (terminate), line:104
|vpiName:terminate
|vpiFullName:work@div_radix2_ET_full.terminate
|vpiRhs:
\_constant: , line:104
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiElseStmt:
\_if_stmt: , line:106
|vpiCondition:
\_operation: , line:106
|vpiOpType:29
|vpiOperand:
\_bit_select: (shift_count), line:106
|vpiName:shift_count
|vpiFullName:work@div_radix2_ET_full.shift_count
|vpiIndex:
\_constant: , line:106
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiOperand:
\_ref_obj: (terminate_early), line:106
|vpiName:terminate_early
|vpiFullName:work@div_radix2_ET_full.terminate_early
|vpiStmt:
\_assignment: , line:107
|vpiOpType:82
|vpiLhs:
\_ref_obj: (terminate), line:107
|vpiName:terminate
|vpiFullName:work@div_radix2_ET_full.terminate
|vpiRhs:
\_constant: , line:107
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiProcess:
\_always: , line:111
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:111
|vpiCondition:
\_operation: , line:111
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:111
|vpiName:clk
|vpiFullName:work@div_radix2_ET_full.clk
|vpiStmt:
\_begin: , line:111
|vpiFullName:work@div_radix2_ET_full
|vpiStmt:
\_if_else: , line:112
|vpiCondition:
\_ref_obj: (rst), line:112
|vpiName:rst
|vpiFullName:work@div_radix2_ET_full.rst
|vpiStmt:
\_assignment: , line:113
|vpiOpType:82
|vpiLhs:
\_ref_obj: (div.done), line:113
|vpiName:div.done
|vpiFullName:work@div_radix2_ET_full.div.done
|vpiRhs:
\_constant: , line:113
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiElseStmt:
\_begin: , line:114
|vpiFullName:work@div_radix2_ET_full
|vpiStmt:
\_if_else: , line:116
|vpiCondition:
\_operation: , line:116
|vpiOpType:28
|vpiOperand:
\_operation: , line:116
|vpiOpType:28
|vpiOperand:
\_operation: , line:116
|vpiOpType:28
|vpiOperand:
\_operation: , line:116
|vpiOpType:4
|vpiOperand:
\_ref_obj: (div.start), line:116
|vpiName:div.start
|vpiFullName:work@div_radix2_ET_full.div.start
|vpiOperand:
\_operation: , line:116
|vpiOpType:29
|vpiOperand:
\_bit_select: (shift_count), line:116
|vpiName:shift_count
|vpiFullName:work@div_radix2_ET_full.shift_count
|vpiIndex:
\_constant: , line:116
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiOperand:
\_ref_obj: (terminate_early), line:116
|vpiName:terminate_early
|vpiFullName:work@div_radix2_ET_full.terminate_early
|vpiOperand:
\_operation: , line:116
|vpiOpType:4
|vpiOperand:
\_ref_obj: (div.done), line:116
|vpiName:div.done
|vpiFullName:work@div_radix2_ET_full.div.done
|vpiOperand:
\_operation: , line:116
|vpiOpType:4
|vpiOperand:
\_ref_obj: (terminate), line:116
|vpiName:terminate
|vpiFullName:work@div_radix2_ET_full.terminate
|vpiStmt:
\_assignment: , line:117
|vpiOpType:82
|vpiLhs:
\_ref_obj: (div.done), line:117
|vpiName:div.done
|vpiFullName:work@div_radix2_ET_full.div.done
|vpiRhs:
\_constant: , line:117
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiElseStmt:
\_if_stmt: , line:118
|vpiCondition:
\_ref_obj: (div.done), line:118
|vpiName:div.done
|vpiFullName:work@div_radix2_ET_full.div.done
|vpiStmt:
\_assignment: , line:119
|vpiOpType:82
|vpiLhs:
\_ref_obj: (div.done), line:119
|vpiName:div.done
|vpiFullName:work@div_radix2_ET_full.div.done
|vpiRhs:
\_constant: , line:119
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiPort:
\_port: (clk), line:27
|vpiName:clk
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (clk), line:27
|vpiName:clk
|vpiFullName:work@div_radix2_ET_full.clk
|vpiNetType:36
|vpiPort:
\_port: (rst), line:28
|vpiName:rst
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (rst), line:28
|vpiName:rst
|vpiFullName:work@div_radix2_ET_full.rst
|vpiNetType:36
|vpiPort:
\_port: (div), line:29
|vpiName:div
|vpiDirection:5
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_modport: (divider)
|vpiContAssign:
\_cont_assign: , line:51
|vpiRhs:
\_operation: , line:51
|vpiOpType:11
|vpiOperand:
\_ref_obj: (PR), line:51
|vpiName:PR
|vpiFullName:work@div_radix2_ET_full.PR
|vpiOperand:
\_operation: , line:51
|vpiOpType:33
|vpiOperand:
\_constant: , line:51
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiOperand:
\_ref_obj: (div.divisor), line:51
|vpiName:div.divisor
|vpiFullName:work@div_radix2_ET_full.div.divisor
|vpiLhs:
\_ref_obj: (new_PR), line:51
|vpiName:new_PR
|vpiFullName:work@div_radix2_ET_full.new_PR
|vpiContAssign:
\_cont_assign: , line:52
|vpiRhs:
\_bit_select: (new_PR), line:52
|vpiName:new_PR
|vpiFullName:work@div_radix2_ET_full.new_PR
|vpiIndex:
\_ref_obj: (div.DATA_WIDTH), line:52
|vpiName:div.DATA_WIDTH
|vpiLhs:
\_ref_obj: (negative_sub_rst), line:52
|vpiName:negative_sub_rst
|vpiFullName:work@div_radix2_ET_full.negative_sub_rst
|vpiContAssign:
\_cont_assign: , line:72
|vpiRhs:
\_operation: , line:72
|vpiOpType:23
|vpiOperand:
\_operation: , line:72
|vpiOpType:33
|vpiOperand:
\_ref_obj: (PR), line:72
|vpiName:PR
|vpiOperand:
\_ref_obj: (AR_r), line:72
|vpiName:AR_r
|vpiOperand:
\_ref_obj: (shift_num_R), line:72
|vpiName:shift_num_R
|vpiFullName:work@div_radix2_ET_full.shift_num_R
|vpiLhs:
\_ref_obj: (combined), line:72
|vpiName:combined
|vpiFullName:work@div_radix2_ET_full.combined
|vpiContAssign:
\_cont_assign: , line:74
|vpiRhs:
\_part_select: , line:74, parent:combined
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (combined)
|vpiLeftRange:
\_operation: , line:74
|vpiOpType:11
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:74
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:74
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:74
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiLhs:
\_ref_obj: (div.remainder), line:74
|vpiName:div.remainder
|vpiFullName:work@div_radix2_ET_full.div.remainder
|vpiContAssign:
\_cont_assign: , line:75
|vpiRhs:
\_operation: , line:75
|vpiOpType:18
|vpiOperand:
\_ref_obj: (div.divisor), line:75
|vpiName:div.divisor
|vpiFullName:work@div_radix2_ET_full.div.divisor
|vpiOperand:
\_ref_obj: (div.remainder), line:75
|vpiName:div.remainder
|vpiFullName:work@div_radix2_ET_full.div.remainder
|vpiLhs:
\_ref_obj: (terminate_early), line:75
|vpiName:terminate_early
|vpiFullName:work@div_radix2_ET_full.terminate_early
|vpiContAssign:
\_cont_assign: , line:76
|vpiRhs:
\_operation: , line:76
|vpiOpType:32
|vpiOperand:
\_ref_obj: (terminate_early), line:76
|vpiName:terminate_early
|vpiFullName:work@div_radix2_ET_full.terminate_early
|vpiOperand:
\_operation: , line:76
|vpiOpType:22
|vpiOperand:
\_ref_obj: (Q_temp), line:76
|vpiName:Q_temp
|vpiFullName:work@div_radix2_ET_full.Q_temp
|vpiOperand:
\_ref_obj: (shift_num_Q), line:76
|vpiName:shift_num_Q
|vpiFullName:work@div_radix2_ET_full.shift_num_Q
|vpiOperand:
\_ref_obj: (Q_temp), line:76
|vpiName:Q_temp
|vpiFullName:work@div_radix2_ET_full.Q_temp
|vpiLhs:
\_ref_obj: (div.quotient), line:76
|vpiName:div.quotient
|vpiFullName:work@div_radix2_ET_full.div.quotient
|vpiNet:
\_logic_net: (clk), line:27
|vpiNet:
\_logic_net: (rst), line:28
|vpiNet:
\_logic_net: (terminate), line:32
|vpiName:terminate
|vpiFullName:work@div_radix2_ET_full.terminate
|vpiNetType:36
|vpiNet:
\_logic_net: (new_PR), line:34
|vpiName:new_PR
|vpiFullName:work@div_radix2_ET_full.new_PR
|vpiNetType:36
|vpiNet:
\_logic_net: (PR), line:35
|vpiName:PR
|vpiFullName:work@div_radix2_ET_full.PR
|vpiNetType:36
|vpiNet:
\_logic_net: (shift_count), line:37
|vpiName:shift_count
|vpiFullName:work@div_radix2_ET_full.shift_count
|vpiNetType:36
|vpiNet:
\_logic_net: (negative_sub_rst), line:39
|vpiName:negative_sub_rst
|vpiFullName:work@div_radix2_ET_full.negative_sub_rst
|vpiNetType:36
|vpiNet:
\_logic_net: (AR_r), line:40
|vpiName:AR_r
|vpiFullName:work@div_radix2_ET_full.AR_r
|vpiNetType:36
|vpiNet:
\_logic_net: (Q_temp), line:41
|vpiName:Q_temp
|vpiFullName:work@div_radix2_ET_full.Q_temp
|vpiNetType:36
|vpiNet:
\_logic_net: (shift_num_R), line:42
|vpiName:shift_num_R
|vpiFullName:work@div_radix2_ET_full.shift_num_R
|vpiNetType:36
|vpiNet:
\_logic_net: (shift_num_Q), line:43
|vpiName:shift_num_Q
|vpiFullName:work@div_radix2_ET_full.shift_num_Q
|vpiNetType:36
|vpiNet:
\_logic_net: (combined), line:44
|vpiName:combined
|vpiFullName:work@div_radix2_ET_full.combined
|vpiNetType:36
|vpiNet:
\_logic_net: (combined_r), line:45
|vpiName:combined_r
|vpiFullName:work@div_radix2_ET_full.combined_r
|vpiNetType:36
|vpiNet:
\_logic_net: (terminate_early), line:46
|vpiName:terminate_early
|vpiFullName:work@div_radix2_ET_full.terminate_early
|vpiNetType:36
|vpiNet:
\_logic_net: (terminate_early_r), line:47
|vpiName:terminate_early_r
|vpiFullName:work@div_radix2_ET_full.terminate_early_r
|vpiNetType:36
|vpiNet:
\_logic_net: (div), line:29
|vpiName:div
|vpiFullName:work@div_radix2_ET_full.div
|uhdmallModules:
\_module: work@div_radix4, file:third_party/cores/taiga/core/div_algorithms/div_radix4.sv, line:25, parent:work@div_unit_core_wrapper
|vpiDefName:work@div_radix4
|vpiFullName:work@div_radix4
|vpiProcess:
\_always: , line:52
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:52
|vpiCondition:
\_operation: , line:52
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:52
|vpiName:clk
|vpiFullName:work@div_radix4.clk
|vpiStmt:
\_begin: , line:52
|vpiFullName:work@div_radix4
|vpiStmt:
\_assignment: , line:53
|vpiOpType:82
|vpiLhs:
\_ref_obj: (shift_count), line:53
|vpiName:shift_count
|vpiFullName:work@div_radix4.shift_count
|vpiRhs:
\_operation: , line:53
|vpiOpType:33
|vpiOperand:
\_part_select: , line:53, parent:shift_count
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (shift_count)
|vpiLeftRange:
\_constant: , line:53
|vpiConstType:7
|vpiDecompile:14
|vpiSize:32
|INT:14
|vpiRightRange:
\_constant: , line:53
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiOperand:
\_ref_obj: (div.start), line:53
|vpiName:div.start
|vpiProcess:
\_always: , line:56
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:56
|vpiCondition:
\_operation: , line:56
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:56
|vpiName:clk
|vpiFullName:work@div_radix4.clk
|vpiStmt:
\_begin: , line:56
|vpiFullName:work@div_radix4
|vpiStmt:
\_if_else: , line:57
|vpiCondition:
\_ref_obj: (div.start), line:57
|vpiName:div.start
|vpiFullName:work@div_radix4.div.start
|vpiStmt:
\_begin: , line:57
|vpiFullName:work@div_radix4
|vpiStmt:
\_assignment: , line:58
|vpiOpType:82
|vpiLhs:
\_ref_obj: (PR), line:58
|vpiName:PR
|vpiFullName:work@div_radix4.PR
|vpiRhs:
\_operation: , line:58
|vpiOpType:33
|vpiOperand:
\_operation: , line:58
|vpiOpType:34
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:58
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_operation:
|vpiOpType:33
|vpiOperand:
\_constant: , line:58
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiOperand:
\_ref_obj: (div.dividend), line:58
|vpiName:div.dividend
|vpiStmt:
\_assignment: , line:59
|vpiOpType:82
|vpiLhs:
\_ref_obj: (div.quotient), line:59
|vpiName:div.quotient
|vpiFullName:work@div_radix4.div.quotient
|vpiRhs:
\_operation: , line:59
|vpiOpType:33
|vpiOperand:
\_ref_obj: (div.dividend), line:59
|vpiName:div.dividend
|vpiOperand:
\_constant: , line:59
|vpiConstType:3
|vpiDecompile:2'b00
|vpiSize:2
|BIN:2'b00
|vpiStmt:
\_assignment: , line:61
|vpiOpType:82
|vpiLhs:
\_ref_obj: (B_1), line:61
|vpiName:B_1
|vpiFullName:work@div_radix4.B_1
|vpiRhs:
\_operation: , line:61
|vpiOpType:33
|vpiOperand:
\_constant: , line:61
|vpiConstType:3
|vpiDecompile:2'b0
|vpiSize:2
|BIN:2'b0
|vpiOperand:
\_ref_obj: (div.divisor), line:61
|vpiName:div.divisor
|vpiStmt:
\_assignment: , line:62
|vpiOpType:82
|vpiLhs:
\_ref_obj: (B_2), line:62
|vpiName:B_2
|vpiFullName:work@div_radix4.B_2
|vpiRhs:
\_operation: , line:62
|vpiOpType:33
|vpiOperand:
\_constant: , line:62
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiOperand:
\_ref_obj: (div.divisor), line:62
|vpiName:div.divisor
|vpiOperand:
\_constant: , line:62
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiStmt:
\_assignment: , line:63
|vpiOpType:82
|vpiLhs:
\_ref_obj: (B_3), line:63
|vpiName:B_3
|vpiFullName:work@div_radix4.B_3
|vpiRhs:
\_operation: , line:63
|vpiOpType:24
|vpiOperand:
\_operation: , line:63
|vpiOpType:33
|vpiOperand:
\_constant: , line:63
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiOperand:
\_ref_obj: (div.divisor), line:63
|vpiName:div.divisor
|vpiOperand:
\_constant: , line:63
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiOperand:
\_operation: , line:63
|vpiOpType:33
|vpiOperand:
\_constant: , line:63
|vpiConstType:3
|vpiDecompile:2'b0
|vpiSize:2
|BIN:2'b0
|vpiOperand:
\_ref_obj: (div.divisor), line:63
|vpiName:div.divisor
|vpiFullName:work@div_radix4.div.divisor
|vpiElseStmt:
\_if_stmt: , line:64
|vpiCondition:
\_operation: , line:64
|vpiOpType:4
|vpiOperand:
\_ref_obj: (terminate), line:64
|vpiName:terminate
|vpiFullName:work@div_radix4.terminate
|vpiStmt:
\_begin: , line:64
|vpiFullName:work@div_radix4
|vpiStmt:
\_case_stmt: , line:65
|vpiCaseType:1
|vpiCondition:
\_ref_obj: (new_PR_sign), line:65
|vpiName:new_PR_sign
|vpiFullName:work@div_radix4.new_PR_sign
|vpiCaseItem:
\_case_item: , line:66
|vpiExpr:
\_constant: , line:66
|vpiConstType:3
|vpiDecompile:3'b111
|vpiSize:3
|BIN:3'b111
|vpiStmt:
\_begin: , line:66
|vpiFullName:work@div_radix4
|vpiStmt:
\_assignment: , line:67
|vpiOpType:82
|vpiLhs:
\_ref_obj: (PR), line:67
|vpiName:PR
|vpiFullName:work@div_radix4.PR
|vpiRhs:
\_operation: , line:67
|vpiOpType:33
|vpiOperand:
\_part_select: , line:67, parent:PR
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (PR)
|vpiLeftRange:
\_operation: , line:67
|vpiOpType:11
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:67
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:67
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:67
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiOperand:
\_ref_obj: (div.quotient), line:67
|vpiName:div.quotient
|vpiStmt:
\_assignment: , line:68
|vpiOpType:82
|vpiLhs:
\_ref_obj: (div.quotient), line:68
|vpiName:div.quotient
|vpiFullName:work@div_radix4.div.quotient
|vpiRhs:
\_operation: , line:68
|vpiOpType:33
|vpiOperand:
\_ref_obj: (div.quotient), line:68
|vpiName:div.quotient
|vpiOperand:
\_constant: , line:68
|vpiConstType:3
|vpiDecompile:2'b00
|vpiSize:2
|BIN:2'b00
|vpiCaseItem:
\_case_item: , line:70
|vpiExpr:
\_constant: , line:70
|vpiConstType:3
|vpiDecompile:3'b110
|vpiSize:3
|BIN:3'b110
|vpiStmt:
\_begin: , line:70
|vpiFullName:work@div_radix4
|vpiStmt:
\_assignment: , line:71
|vpiOpType:82
|vpiLhs:
\_ref_obj: (PR), line:71
|vpiName:PR
|vpiFullName:work@div_radix4.PR
|vpiRhs:
\_operation: , line:71
|vpiOpType:33
|vpiOperand:
\_part_select: , line:71, parent:new_PR_1
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (new_PR_1)
|vpiLeftRange:
\_operation: , line:71
|vpiOpType:11
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:71
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:71
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:71
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiOperand:
\_ref_obj: (div.quotient), line:71
|vpiName:div.quotient
|vpiStmt:
\_assignment: , line:72
|vpiOpType:82
|vpiLhs:
\_ref_obj: (div.quotient), line:72
|vpiName:div.quotient
|vpiFullName:work@div_radix4.div.quotient
|vpiRhs:
\_operation: , line:72
|vpiOpType:33
|vpiOperand:
\_ref_obj: (div.quotient), line:72
|vpiName:div.quotient
|vpiOperand:
\_constant: , line:72
|vpiConstType:3
|vpiDecompile:2'b01
|vpiSize:2
|BIN:2'b01
|vpiCaseItem:
\_case_item: , line:74
|vpiExpr:
\_constant: , line:74
|vpiConstType:3
|vpiDecompile:3'b100
|vpiSize:3
|BIN:3'b100
|vpiStmt:
\_begin: , line:74
|vpiFullName:work@div_radix4
|vpiStmt:
\_assignment: , line:75
|vpiOpType:82
|vpiLhs:
\_ref_obj: (PR), line:75
|vpiName:PR
|vpiFullName:work@div_radix4.PR
|vpiRhs:
\_operation: , line:75
|vpiOpType:33
|vpiOperand:
\_part_select: , line:75, parent:new_PR_2
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (new_PR_2)
|vpiLeftRange:
\_operation: , line:75
|vpiOpType:11
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:75
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:75
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:75
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiOperand:
\_ref_obj: (div.quotient), line:75
|vpiName:div.quotient
|vpiStmt:
\_assignment: , line:76
|vpiOpType:82
|vpiLhs:
\_ref_obj: (div.quotient), line:76
|vpiName:div.quotient
|vpiFullName:work@div_radix4.div.quotient
|vpiRhs:
\_operation: , line:76
|vpiOpType:33
|vpiOperand:
\_ref_obj: (div.quotient), line:76
|vpiName:div.quotient
|vpiOperand:
\_constant: , line:76
|vpiConstType:3
|vpiDecompile:2'b10
|vpiSize:2
|BIN:2'b10
|vpiCaseItem:
\_case_item: , line:78
|vpiStmt:
\_begin: , line:78
|vpiFullName:work@div_radix4
|vpiStmt:
\_assignment: , line:79
|vpiOpType:82
|vpiLhs:
\_ref_obj: (PR), line:79
|vpiName:PR
|vpiFullName:work@div_radix4.PR
|vpiRhs:
\_operation: , line:79
|vpiOpType:33
|vpiOperand:
\_part_select: , line:79, parent:new_PR_3
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (new_PR_3)
|vpiLeftRange:
\_operation: , line:79
|vpiOpType:11
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:79
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:79
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:79
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiOperand:
\_ref_obj: (div.quotient), line:79
|vpiName:div.quotient
|vpiStmt:
\_assignment: , line:80
|vpiOpType:82
|vpiLhs:
\_ref_obj: (div.quotient), line:80
|vpiName:div.quotient
|vpiFullName:work@div_radix4.div.quotient
|vpiRhs:
\_operation: , line:80
|vpiOpType:33
|vpiOperand:
\_ref_obj: (div.quotient), line:80
|vpiName:div.quotient
|vpiOperand:
\_constant: , line:80
|vpiConstType:3
|vpiDecompile:2'b11
|vpiSize:2
|BIN:2'b11
|vpiProcess:
\_always: , line:88
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:88
|vpiCondition:
\_operation: , line:88
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:88
|vpiName:clk
|vpiFullName:work@div_radix4.clk
|vpiStmt:
\_begin: , line:88
|vpiFullName:work@div_radix4
|vpiStmt:
\_if_else: , line:89
|vpiCondition:
\_ref_obj: (div.start), line:89
|vpiName:div.start
|vpiFullName:work@div_radix4.div.start
|vpiStmt:
\_assignment: , line:90
|vpiOpType:82
|vpiLhs:
\_ref_obj: (div.divisor_is_zero), line:90
|vpiName:div.divisor_is_zero
|vpiFullName:work@div_radix4.div.divisor_is_zero
|vpiRhs:
\_operation: , line:90
|vpiOpType:4
|vpiOperand:
\_ref_obj: (div.divisor), line:90
|vpiName:div.divisor
|vpiFullName:work@div_radix4.div.divisor
|vpiElseStmt:
\_if_stmt: , line:91
|vpiCondition:
\_operation: , line:91
|vpiOpType:4
|vpiOperand:
\_ref_obj: (terminate), line:91
|vpiName:terminate
|vpiFullName:work@div_radix4.terminate
|vpiStmt:
\_assignment: , line:92
|vpiOpType:82
|vpiLhs:
\_ref_obj: (div.divisor_is_zero), line:92
|vpiName:div.divisor_is_zero
|vpiFullName:work@div_radix4.div.divisor_is_zero
|vpiRhs:
\_operation: , line:92
|vpiOpType:28
|vpiOperand:
\_ref_obj: (div.divisor_is_zero), line:92
|vpiName:div.divisor_is_zero
|vpiFullName:work@div_radix4.div.divisor_is_zero
|vpiOperand:
\_operation: , line:92
|vpiOpType:4
|vpiOperand:
\_operation: , line:92
|vpiOpType:7
|vpiOperand:
\_ref_obj: (new_PR_sign), line:92
|vpiName:new_PR_sign
|vpiFullName:work@div_radix4.new_PR_sign
|vpiProcess:
\_always: , line:95
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:95
|vpiCondition:
\_operation: , line:95
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:95
|vpiName:clk
|vpiFullName:work@div_radix4.clk
|vpiStmt:
\_begin: , line:95
|vpiFullName:work@div_radix4
|vpiStmt:
\_if_else: , line:96
|vpiCondition:
\_ref_obj: (rst), line:96
|vpiName:rst
|vpiFullName:work@div_radix4.rst
|vpiStmt:
\_assignment: , line:97
|vpiOpType:82
|vpiLhs:
\_ref_obj: (terminate), line:97
|vpiName:terminate
|vpiFullName:work@div_radix4.terminate
|vpiRhs:
\_constant: , line:97
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiElseStmt:
\_begin: , line:98
|vpiFullName:work@div_radix4
|vpiStmt:
\_if_stmt: , line:99
|vpiCondition:
\_ref_obj: (div.start), line:99
|vpiName:div.start
|vpiFullName:work@div_radix4.div.start
|vpiStmt:
\_assignment: , line:100
|vpiOpType:82
|vpiLhs:
\_ref_obj: (terminate), line:100
|vpiName:terminate
|vpiFullName:work@div_radix4.terminate
|vpiRhs:
\_constant: , line:100
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiStmt:
\_if_stmt: , line:101
|vpiCondition:
\_bit_select: (shift_count), line:101
|vpiName:shift_count
|vpiFullName:work@div_radix4.shift_count
|vpiIndex:
\_constant: , line:101
|vpiConstType:7
|vpiDecompile:15
|vpiSize:32
|INT:15
|vpiStmt:
\_assignment: , line:102
|vpiOpType:82
|vpiLhs:
\_ref_obj: (terminate), line:102
|vpiName:terminate
|vpiFullName:work@div_radix4.terminate
|vpiRhs:
\_constant: , line:102
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiProcess:
\_always: , line:106
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:106
|vpiCondition:
\_operation: , line:106
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:106
|vpiName:clk
|vpiFullName:work@div_radix4.clk
|vpiStmt:
\_begin: , line:106
|vpiFullName:work@div_radix4
|vpiStmt:
\_if_else: , line:107
|vpiCondition:
\_ref_obj: (rst), line:107
|vpiName:rst
|vpiFullName:work@div_radix4.rst
|vpiStmt:
\_assignment: , line:108
|vpiOpType:82
|vpiLhs:
\_ref_obj: (div.done), line:108
|vpiName:div.done
|vpiFullName:work@div_radix4.div.done
|vpiRhs:
\_constant: , line:108
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiElseStmt:
\_begin: , line:109
|vpiFullName:work@div_radix4
|vpiStmt:
\_if_else: , line:110
|vpiCondition:
\_bit_select: (shift_count), line:110
|vpiName:shift_count
|vpiFullName:work@div_radix4.shift_count
|vpiIndex:
\_constant: , line:110
|vpiConstType:7
|vpiDecompile:15
|vpiSize:32
|INT:15
|vpiStmt:
\_assignment: , line:111
|vpiOpType:82
|vpiLhs:
\_ref_obj: (div.done), line:111
|vpiName:div.done
|vpiFullName:work@div_radix4.div.done
|vpiRhs:
\_constant: , line:111
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiElseStmt:
\_if_stmt: , line:112
|vpiCondition:
\_ref_obj: (div.done), line:112
|vpiName:div.done
|vpiFullName:work@div_radix4.div.done
|vpiStmt:
\_assignment: , line:113
|vpiOpType:82
|vpiLhs:
\_ref_obj: (div.done), line:113
|vpiName:div.done
|vpiFullName:work@div_radix4.div.done
|vpiRhs:
\_constant: , line:113
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiPort:
\_port: (clk), line:27
|vpiName:clk
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (clk), line:27
|vpiName:clk
|vpiFullName:work@div_radix4.clk
|vpiNetType:36
|vpiPort:
\_port: (rst), line:28
|vpiName:rst
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (rst), line:28
|vpiName:rst
|vpiFullName:work@div_radix4.rst
|vpiNetType:36
|vpiPort:
\_port: (div), line:29
|vpiName:div
|vpiDirection:5
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_modport: (divider)
|vpiContAssign:
\_cont_assign: , line:46
|vpiRhs:
\_operation: , line:46
|vpiOpType:11
|vpiOperand:
\_operation: , line:46
|vpiOpType:33
|vpiOperand:
\_constant: , line:46
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiOperand:
\_ref_obj: (PR), line:46
|vpiName:PR
|vpiOperand:
\_operation: , line:46
|vpiOpType:33
|vpiOperand:
\_constant: , line:46
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiOperand:
\_ref_obj: (B_1), line:46
|vpiName:B_1
|vpiFullName:work@div_radix4.B_1
|vpiLhs:
\_ref_obj: (new_PR_1), line:46
|vpiName:new_PR_1
|vpiFullName:work@div_radix4.new_PR_1
|vpiContAssign:
\_cont_assign: , line:47
|vpiRhs:
\_operation: , line:47
|vpiOpType:11
|vpiOperand:
\_operation: , line:47
|vpiOpType:33
|vpiOperand:
\_constant: , line:47
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiOperand:
\_ref_obj: (PR), line:47
|vpiName:PR
|vpiOperand:
\_operation: , line:47
|vpiOpType:33
|vpiOperand:
\_constant: , line:47
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiOperand:
\_ref_obj: (B_2), line:47
|vpiName:B_2
|vpiFullName:work@div_radix4.B_2
|vpiLhs:
\_ref_obj: (new_PR_2), line:47
|vpiName:new_PR_2
|vpiFullName:work@div_radix4.new_PR_2
|vpiContAssign:
\_cont_assign: , line:48
|vpiRhs:
\_operation: , line:48
|vpiOpType:11
|vpiOperand:
\_operation: , line:48
|vpiOpType:33
|vpiOperand:
\_constant: , line:48
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiOperand:
\_ref_obj: (PR), line:48
|vpiName:PR
|vpiOperand:
\_operation: , line:48
|vpiOpType:33
|vpiOperand:
\_constant: , line:48
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiOperand:
\_ref_obj: (B_3), line:48
|vpiName:B_3
|vpiFullName:work@div_radix4.B_3
|vpiLhs:
\_ref_obj: (new_PR_3), line:48
|vpiName:new_PR_3
|vpiFullName:work@div_radix4.new_PR_3
|vpiContAssign:
\_cont_assign: , line:49
|vpiRhs:
\_operation: , line:49
|vpiOpType:33
|vpiOperand:
\_bit_select: (new_PR_3), line:49
|vpiName:new_PR_3
|vpiIndex:
\_operation: , line:49
|vpiOpType:24
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:49
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:49
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiOperand:
\_bit_select: (new_PR_2), line:49
|vpiName:new_PR_2
|vpiIndex:
\_operation: , line:49
|vpiOpType:24
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:49
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:49
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiOperand:
\_bit_select: (new_PR_1), line:49
|vpiName:new_PR_1
|vpiIndex:
\_operation: , line:49
|vpiOpType:24
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:49
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:49
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiLhs:
\_ref_obj: (new_PR_sign), line:49
|vpiName:new_PR_sign
|vpiFullName:work@div_radix4.new_PR_sign
|vpiContAssign:
\_cont_assign: , line:86
|vpiRhs:
\_part_select: , line:86, parent:PR
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (PR)
|vpiLeftRange:
\_operation: , line:86
|vpiOpType:24
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:86
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:86
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:86
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiLhs:
\_ref_obj: (div.remainder), line:86
|vpiName:div.remainder
|vpiFullName:work@div_radix4.div.remainder
|vpiNet:
\_logic_net: (clk), line:27
|vpiNet:
\_logic_net: (rst), line:28
|vpiNet:
\_logic_net: (terminate), line:32
|vpiName:terminate
|vpiFullName:work@div_radix4.terminate
|vpiNetType:36
|vpiNet:
\_logic_net: (shift_count), line:33
|vpiName:shift_count
|vpiFullName:work@div_radix4.shift_count
|vpiNetType:36
|vpiNet:
\_logic_net: (PR), line:35
|vpiName:PR
|vpiFullName:work@div_radix4.PR
|vpiNetType:36
|vpiNet:
\_logic_net: (new_PR_sign), line:36
|vpiName:new_PR_sign
|vpiFullName:work@div_radix4.new_PR_sign
|vpiNetType:36
|vpiNet:
\_logic_net: (new_PR_1), line:37
|vpiName:new_PR_1
|vpiFullName:work@div_radix4.new_PR_1
|vpiNetType:36
|vpiNet:
\_logic_net: (new_PR_2), line:38
|vpiName:new_PR_2
|vpiFullName:work@div_radix4.new_PR_2
|vpiNetType:36
|vpiNet:
\_logic_net: (new_PR_3), line:39
|vpiName:new_PR_3
|vpiFullName:work@div_radix4.new_PR_3
|vpiNetType:36
|vpiNet:
\_logic_net: (B_1), line:40
|vpiName:B_1
|vpiFullName:work@div_radix4.B_1
|vpiNetType:36
|vpiNet:
\_logic_net: (B_2), line:41
|vpiName:B_2
|vpiFullName:work@div_radix4.B_2
|vpiNetType:36
|vpiNet:
\_logic_net: (B_3), line:42
|vpiName:B_3
|vpiFullName:work@div_radix4.B_3
|vpiNetType:36
|vpiNet:
\_logic_net: (div), line:29
|vpiName:div
|vpiFullName:work@div_radix4.div
|uhdmallModules:
\_module: work@div_radix4_ET, file:third_party/cores/taiga/core/div_algorithms/div_radix4_ET.sv, line:25, parent:work@div_unit_core_wrapper
|vpiDefName:work@div_radix4_ET
|vpiFullName:work@div_radix4_ET
|vpiProcess:
\_always: , line:53
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:53
|vpiCondition:
\_operation: , line:53
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:53
|vpiName:clk
|vpiFullName:work@div_radix4_ET.clk
|vpiStmt:
\_begin: , line:53
|vpiFullName:work@div_radix4_ET
|vpiStmt:
\_assignment: , line:54
|vpiOpType:82
|vpiLhs:
\_ref_obj: (shift_count), line:54
|vpiName:shift_count
|vpiFullName:work@div_radix4_ET.shift_count
|vpiRhs:
\_operation: , line:54
|vpiOpType:33
|vpiOperand:
\_part_select: , line:54, parent:shift_count
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (shift_count)
|vpiLeftRange:
\_constant: , line:54
|vpiConstType:7
|vpiDecompile:14
|vpiSize:32
|INT:14
|vpiRightRange:
\_constant: , line:54
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiOperand:
\_operation: , line:54
|vpiOpType:28
|vpiOperand:
\_ref_obj: (div.start), line:54
|vpiName:div.start
|vpiOperand:
\_operation: , line:54
|vpiOpType:4
|vpiOperand:
\_ref_obj: (terminate_early), line:54
|vpiName:terminate_early
|vpiProcess:
\_always: , line:59
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:59
|vpiCondition:
\_operation: , line:59
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:59
|vpiName:clk
|vpiFullName:work@div_radix4_ET.clk
|vpiStmt:
\_begin: , line:59
|vpiFullName:work@div_radix4_ET
|vpiStmt:
\_if_else: , line:60
|vpiCondition:
\_ref_obj: (div.start), line:60
|vpiName:div.start
|vpiFullName:work@div_radix4_ET.div.start
|vpiStmt:
\_begin: , line:60
|vpiFullName:work@div_radix4_ET
|vpiStmt:
\_if_else: , line:61
|vpiCondition:
\_ref_obj: (terminate_early), line:61
|vpiName:terminate_early
|vpiFullName:work@div_radix4_ET.terminate_early
|vpiStmt:
\_begin: , line:61
|vpiFullName:work@div_radix4_ET
|vpiStmt:
\_assignment: , line:62
|vpiOpType:82
|vpiLhs:
\_ref_obj: (PR), line:62
|vpiName:PR
|vpiFullName:work@div_radix4_ET.PR
|vpiRhs:
\_operation: , line:62
|vpiOpType:33
|vpiOperand:
\_ref_obj: (div.dividend), line:62
|vpiName:div.dividend
|vpiOperand:
\_constant: , line:62
|vpiConstType:3
|vpiDecompile:2'b00
|vpiSize:2
|BIN:2'b00
|vpiStmt:
\_assignment: , line:63
|vpiOpType:82
|vpiLhs:
\_ref_obj: (div.quotient), line:63
|vpiName:div.quotient
|vpiFullName:work@div_radix4_ET.div.quotient
|vpiRhs:
\_constant: , line:63
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiElseStmt:
\_begin: , line:65
|vpiFullName:work@div_radix4_ET
|vpiStmt:
\_assignment: , line:66
|vpiOpType:82
|vpiLhs:
\_ref_obj: (PR), line:66
|vpiName:PR
|vpiFullName:work@div_radix4_ET.PR
|vpiRhs:
\_operation: , line:66
|vpiOpType:33
|vpiOperand:
\_operation: , line:66
|vpiOpType:34
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:66
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_operation:
|vpiOpType:33
|vpiOperand:
\_constant: , line:66
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiOperand:
\_ref_obj: (div.dividend), line:66
|vpiName:div.dividend
|vpiStmt:
\_assignment: , line:67
|vpiOpType:82
|vpiLhs:
\_ref_obj: (div.quotient), line:67
|vpiName:div.quotient
|vpiFullName:work@div_radix4_ET.div.quotient
|vpiRhs:
\_operation: , line:67
|vpiOpType:33
|vpiOperand:
\_ref_obj: (div.dividend), line:67
|vpiName:div.dividend
|vpiOperand:
\_constant: , line:67
|vpiConstType:3
|vpiDecompile:2'b00
|vpiSize:2
|BIN:2'b00
|vpiStmt:
\_assignment: , line:69
|vpiOpType:82
|vpiLhs:
\_ref_obj: (B_1), line:69
|vpiName:B_1
|vpiFullName:work@div_radix4_ET.B_1
|vpiRhs:
\_operation: , line:69
|vpiOpType:33
|vpiOperand:
\_constant: , line:69
|vpiConstType:3
|vpiDecompile:2'b0
|vpiSize:2
|BIN:2'b0
|vpiOperand:
\_ref_obj: (div.divisor), line:69
|vpiName:div.divisor
|vpiStmt:
\_assignment: , line:70
|vpiOpType:82
|vpiLhs:
\_ref_obj: (B_2), line:70
|vpiName:B_2
|vpiFullName:work@div_radix4_ET.B_2
|vpiRhs:
\_operation: , line:70
|vpiOpType:33
|vpiOperand:
\_constant: , line:70
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiOperand:
\_ref_obj: (div.divisor), line:70
|vpiName:div.divisor
|vpiOperand:
\_constant: , line:70
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiStmt:
\_assignment: , line:71
|vpiOpType:82
|vpiLhs:
\_ref_obj: (B_3), line:71
|vpiName:B_3
|vpiFullName:work@div_radix4_ET.B_3
|vpiRhs:
\_operation: , line:71
|vpiOpType:24
|vpiOperand:
\_operation: , line:71
|vpiOpType:33
|vpiOperand:
\_constant: , line:71
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiOperand:
\_ref_obj: (div.divisor), line:71
|vpiName:div.divisor
|vpiOperand:
\_constant: , line:71
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiOperand:
\_operation: , line:71
|vpiOpType:33
|vpiOperand:
\_constant: , line:71
|vpiConstType:3
|vpiDecompile:2'b0
|vpiSize:2
|BIN:2'b0
|vpiOperand:
\_ref_obj: (div.divisor), line:71
|vpiName:div.divisor
|vpiFullName:work@div_radix4_ET.div.divisor
|vpiElseStmt:
\_if_stmt: , line:73
|vpiCondition:
\_operation: , line:73
|vpiOpType:4
|vpiOperand:
\_ref_obj: (terminate), line:73
|vpiName:terminate
|vpiFullName:work@div_radix4_ET.terminate
|vpiStmt:
\_begin: , line:73
|vpiFullName:work@div_radix4_ET
|vpiStmt:
\_case_stmt: , line:74
|vpiCaseType:1
|vpiCondition:
\_ref_obj: (new_PR_sign), line:74
|vpiName:new_PR_sign
|vpiFullName:work@div_radix4_ET.new_PR_sign
|vpiCaseItem:
\_case_item: , line:75
|vpiExpr:
\_constant: , line:75
|vpiConstType:3
|vpiDecompile:3'b111
|vpiSize:3
|BIN:3'b111
|vpiStmt:
\_begin: , line:75
|vpiFullName:work@div_radix4_ET
|vpiStmt:
\_assignment: , line:76
|vpiOpType:82
|vpiLhs:
\_ref_obj: (PR), line:76
|vpiName:PR
|vpiFullName:work@div_radix4_ET.PR
|vpiRhs:
\_operation: , line:76
|vpiOpType:33
|vpiOperand:
\_part_select: , line:76, parent:PR
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (PR)
|vpiLeftRange:
\_operation: , line:76
|vpiOpType:11
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:76
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:76
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:76
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiOperand:
\_ref_obj: (div.quotient), line:76
|vpiName:div.quotient
|vpiStmt:
\_assignment: , line:77
|vpiOpType:82
|vpiLhs:
\_ref_obj: (div.quotient), line:77
|vpiName:div.quotient
|vpiFullName:work@div_radix4_ET.div.quotient
|vpiRhs:
\_operation: , line:77
|vpiOpType:33
|vpiOperand:
\_ref_obj: (div.quotient), line:77
|vpiName:div.quotient
|vpiOperand:
\_constant: , line:77
|vpiConstType:3
|vpiDecompile:2'b00
|vpiSize:2
|BIN:2'b00
|vpiCaseItem:
\_case_item: , line:79
|vpiExpr:
\_constant: , line:79
|vpiConstType:3
|vpiDecompile:3'b110
|vpiSize:3
|BIN:3'b110
|vpiStmt:
\_begin: , line:79
|vpiFullName:work@div_radix4_ET
|vpiStmt:
\_assignment: , line:80
|vpiOpType:82
|vpiLhs:
\_ref_obj: (PR), line:80
|vpiName:PR
|vpiFullName:work@div_radix4_ET.PR
|vpiRhs:
\_operation: , line:80
|vpiOpType:33
|vpiOperand:
\_part_select: , line:80, parent:new_PR_1
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (new_PR_1)
|vpiLeftRange:
\_operation: , line:80
|vpiOpType:11
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:80
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:80
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:80
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiOperand:
\_ref_obj: (div.quotient), line:80
|vpiName:div.quotient
|vpiStmt:
\_assignment: , line:81
|vpiOpType:82
|vpiLhs:
\_ref_obj: (div.quotient), line:81
|vpiName:div.quotient
|vpiFullName:work@div_radix4_ET.div.quotient
|vpiRhs:
\_operation: , line:81
|vpiOpType:33
|vpiOperand:
\_ref_obj: (div.quotient), line:81
|vpiName:div.quotient
|vpiOperand:
\_constant: , line:81
|vpiConstType:3
|vpiDecompile:2'b01
|vpiSize:2
|BIN:2'b01
|vpiCaseItem:
\_case_item: , line:83
|vpiExpr:
\_constant: , line:83
|vpiConstType:3
|vpiDecompile:3'b100
|vpiSize:3
|BIN:3'b100
|vpiStmt:
\_begin: , line:83
|vpiFullName:work@div_radix4_ET
|vpiStmt:
\_assignment: , line:84
|vpiOpType:82
|vpiLhs:
\_ref_obj: (PR), line:84
|vpiName:PR
|vpiFullName:work@div_radix4_ET.PR
|vpiRhs:
\_operation: , line:84
|vpiOpType:33
|vpiOperand:
\_part_select: , line:84, parent:new_PR_2
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (new_PR_2)
|vpiLeftRange:
\_operation: , line:84
|vpiOpType:11
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:84
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:84
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:84
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiOperand:
\_ref_obj: (div.quotient), line:84
|vpiName:div.quotient
|vpiStmt:
\_assignment: , line:85
|vpiOpType:82
|vpiLhs:
\_ref_obj: (div.quotient), line:85
|vpiName:div.quotient
|vpiFullName:work@div_radix4_ET.div.quotient
|vpiRhs:
\_operation: , line:85
|vpiOpType:33
|vpiOperand:
\_ref_obj: (div.quotient), line:85
|vpiName:div.quotient
|vpiOperand:
\_constant: , line:85
|vpiConstType:3
|vpiDecompile:2'b10
|vpiSize:2
|BIN:2'b10
|vpiCaseItem:
\_case_item: , line:87
|vpiStmt:
\_begin: , line:87
|vpiFullName:work@div_radix4_ET
|vpiStmt:
\_assignment: , line:88
|vpiOpType:82
|vpiLhs:
\_ref_obj: (PR), line:88
|vpiName:PR
|vpiFullName:work@div_radix4_ET.PR
|vpiRhs:
\_operation: , line:88
|vpiOpType:33
|vpiOperand:
\_part_select: , line:88, parent:new_PR_3
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (new_PR_3)
|vpiLeftRange:
\_operation: , line:88
|vpiOpType:11
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:88
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:88
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:88
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiOperand:
\_ref_obj: (div.quotient), line:88
|vpiName:div.quotient
|vpiStmt:
\_assignment: , line:89
|vpiOpType:82
|vpiLhs:
\_ref_obj: (div.quotient), line:89
|vpiName:div.quotient
|vpiFullName:work@div_radix4_ET.div.quotient
|vpiRhs:
\_operation: , line:89
|vpiOpType:33
|vpiOperand:
\_ref_obj: (div.quotient), line:89
|vpiName:div.quotient
|vpiOperand:
\_constant: , line:89
|vpiConstType:3
|vpiDecompile:2'b11
|vpiSize:2
|BIN:2'b11
|vpiProcess:
\_always: , line:97
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:97
|vpiCondition:
\_operation: , line:97
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:97
|vpiName:clk
|vpiFullName:work@div_radix4_ET.clk
|vpiStmt:
\_begin: , line:97
|vpiFullName:work@div_radix4_ET
|vpiStmt:
\_if_else: , line:98
|vpiCondition:
\_ref_obj: (div.start), line:98
|vpiName:div.start
|vpiFullName:work@div_radix4_ET.div.start
|vpiStmt:
\_assignment: , line:99
|vpiOpType:82
|vpiLhs:
\_ref_obj: (div.divisor_is_zero), line:99
|vpiName:div.divisor_is_zero
|vpiFullName:work@div_radix4_ET.div.divisor_is_zero
|vpiRhs:
\_operation: , line:99
|vpiOpType:4
|vpiOperand:
\_ref_obj: (div.divisor), line:99
|vpiName:div.divisor
|vpiFullName:work@div_radix4_ET.div.divisor
|vpiElseStmt:
\_if_stmt: , line:100
|vpiCondition:
\_operation: , line:100
|vpiOpType:4
|vpiOperand:
\_ref_obj: (terminate), line:100
|vpiName:terminate
|vpiFullName:work@div_radix4_ET.terminate
|vpiStmt:
\_assignment: , line:101
|vpiOpType:82
|vpiLhs:
\_ref_obj: (div.divisor_is_zero), line:101
|vpiName:div.divisor_is_zero
|vpiFullName:work@div_radix4_ET.div.divisor_is_zero
|vpiRhs:
\_operation: , line:101
|vpiOpType:28
|vpiOperand:
\_ref_obj: (div.divisor_is_zero), line:101
|vpiName:div.divisor_is_zero
|vpiFullName:work@div_radix4_ET.div.divisor_is_zero
|vpiOperand:
\_operation: , line:101
|vpiOpType:4
|vpiOperand:
\_operation: , line:101
|vpiOpType:7
|vpiOperand:
\_ref_obj: (new_PR_sign), line:101
|vpiName:new_PR_sign
|vpiFullName:work@div_radix4_ET.new_PR_sign
|vpiProcess:
\_always: , line:104
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:104
|vpiCondition:
\_operation: , line:104
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:104
|vpiName:clk
|vpiFullName:work@div_radix4_ET.clk
|vpiStmt:
\_begin: , line:104
|vpiFullName:work@div_radix4_ET
|vpiStmt:
\_if_else: , line:105
|vpiCondition:
\_ref_obj: (rst), line:105
|vpiName:rst
|vpiFullName:work@div_radix4_ET.rst
|vpiStmt:
\_assignment: , line:106
|vpiOpType:82
|vpiLhs:
\_ref_obj: (terminate), line:106
|vpiName:terminate
|vpiFullName:work@div_radix4_ET.terminate
|vpiRhs:
\_constant: , line:106
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiElseStmt:
\_begin: , line:107
|vpiFullName:work@div_radix4_ET
|vpiStmt:
\_if_stmt: , line:108
|vpiCondition:
\_ref_obj: (div.start), line:108
|vpiName:div.start
|vpiFullName:work@div_radix4_ET.div.start
|vpiStmt:
\_if_else: , line:109
|vpiCondition:
\_ref_obj: (terminate_early), line:109
|vpiName:terminate_early
|vpiFullName:work@div_radix4_ET.terminate_early
|vpiStmt:
\_begin: , line:109
|vpiFullName:work@div_radix4_ET
|vpiStmt:
\_assignment: , line:110
|vpiOpType:82
|vpiLhs:
\_ref_obj: (terminate), line:110
|vpiName:terminate
|vpiFullName:work@div_radix4_ET.terminate
|vpiRhs:
\_constant: , line:110
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiElseStmt:
\_begin: , line:111
|vpiFullName:work@div_radix4_ET
|vpiStmt:
\_assignment: , line:112
|vpiOpType:82
|vpiLhs:
\_ref_obj: (terminate), line:112
|vpiName:terminate
|vpiFullName:work@div_radix4_ET.terminate
|vpiRhs:
\_constant: , line:112
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiStmt:
\_if_stmt: , line:114
|vpiCondition:
\_bit_select: (shift_count), line:114
|vpiName:shift_count
|vpiFullName:work@div_radix4_ET.shift_count
|vpiIndex:
\_constant: , line:114
|vpiConstType:7
|vpiDecompile:15
|vpiSize:32
|INT:15
|vpiStmt:
\_assignment: , line:115
|vpiOpType:82
|vpiLhs:
\_ref_obj: (terminate), line:115
|vpiName:terminate
|vpiFullName:work@div_radix4_ET.terminate
|vpiRhs:
\_constant: , line:115
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiProcess:
\_always: , line:119
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:119
|vpiCondition:
\_operation: , line:119
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:119
|vpiName:clk
|vpiFullName:work@div_radix4_ET.clk
|vpiStmt:
\_begin: , line:119
|vpiFullName:work@div_radix4_ET
|vpiStmt:
\_if_else: , line:120
|vpiCondition:
\_ref_obj: (rst), line:120
|vpiName:rst
|vpiFullName:work@div_radix4_ET.rst
|vpiStmt:
\_assignment: , line:121
|vpiOpType:82
|vpiLhs:
\_ref_obj: (div.done), line:121
|vpiName:div.done
|vpiFullName:work@div_radix4_ET.div.done
|vpiRhs:
\_constant: , line:121
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiElseStmt:
\_begin: , line:122
|vpiFullName:work@div_radix4_ET
|vpiStmt:
\_if_else: , line:123
|vpiCondition:
\_ref_obj: (div.done), line:123
|vpiName:div.done
|vpiFullName:work@div_radix4_ET.div.done
|vpiStmt:
\_assignment: , line:124
|vpiOpType:82
|vpiLhs:
\_ref_obj: (div.done), line:124
|vpiName:div.done
|vpiFullName:work@div_radix4_ET.div.done
|vpiRhs:
\_constant: , line:124
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiElseStmt:
\_if_stmt: , line:125
|vpiCondition:
\_operation: , line:125
|vpiOpType:29
|vpiOperand:
\_operation: , line:125
|vpiOpType:28
|vpiOperand:
\_operation: , line:125
|vpiOpType:4
|vpiOperand:
\_ref_obj: (div.start), line:125
|vpiName:div.start
|vpiFullName:work@div_radix4_ET.div.start
|vpiOperand:
\_bit_select: (shift_count), line:125
|vpiName:shift_count
|vpiFullName:work@div_radix4_ET.shift_count
|vpiIndex:
\_constant: , line:125
|vpiConstType:7
|vpiDecompile:15
|vpiSize:32
|INT:15
|vpiOperand:
\_operation: , line:125
|vpiOpType:28
|vpiOperand:
\_ref_obj: (div.start), line:125
|vpiName:div.start
|vpiFullName:work@div_radix4_ET.div.start
|vpiOperand:
\_ref_obj: (terminate_early), line:125
|vpiName:terminate_early
|vpiFullName:work@div_radix4_ET.terminate_early
|vpiStmt:
\_assignment: , line:126
|vpiOpType:82
|vpiLhs:
\_ref_obj: (div.done), line:126
|vpiName:div.done
|vpiFullName:work@div_radix4_ET.div.done
|vpiRhs:
\_constant: , line:126
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiPort:
\_port: (clk), line:27
|vpiName:clk
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (clk), line:27
|vpiName:clk
|vpiFullName:work@div_radix4_ET.clk
|vpiNetType:36
|vpiPort:
\_port: (rst), line:28
|vpiName:rst
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (rst), line:28
|vpiName:rst
|vpiFullName:work@div_radix4_ET.rst
|vpiNetType:36
|vpiPort:
\_port: (div), line:29
|vpiName:div
|vpiDirection:5
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_modport: (divider)
|vpiContAssign:
\_cont_assign: , line:47
|vpiRhs:
\_operation: , line:47
|vpiOpType:11
|vpiOperand:
\_operation: , line:47
|vpiOpType:33
|vpiOperand:
\_constant: , line:47
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiOperand:
\_ref_obj: (PR), line:47
|vpiName:PR
|vpiOperand:
\_operation: , line:47
|vpiOpType:33
|vpiOperand:
\_constant: , line:47
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiOperand:
\_ref_obj: (B_1), line:47
|vpiName:B_1
|vpiFullName:work@div_radix4_ET.B_1
|vpiLhs:
\_ref_obj: (new_PR_1), line:47
|vpiName:new_PR_1
|vpiFullName:work@div_radix4_ET.new_PR_1
|vpiContAssign:
\_cont_assign: , line:48
|vpiRhs:
\_operation: , line:48
|vpiOpType:11
|vpiOperand:
\_operation: , line:48
|vpiOpType:33
|vpiOperand:
\_constant: , line:48
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiOperand:
\_ref_obj: (PR), line:48
|vpiName:PR
|vpiOperand:
\_operation: , line:48
|vpiOpType:33
|vpiOperand:
\_constant: , line:48
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiOperand:
\_ref_obj: (B_2), line:48
|vpiName:B_2
|vpiFullName:work@div_radix4_ET.B_2
|vpiLhs:
\_ref_obj: (new_PR_2), line:48
|vpiName:new_PR_2
|vpiFullName:work@div_radix4_ET.new_PR_2
|vpiContAssign:
\_cont_assign: , line:49
|vpiRhs:
\_operation: , line:49
|vpiOpType:11
|vpiOperand:
\_operation: , line:49
|vpiOpType:33
|vpiOperand:
\_constant: , line:49
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiOperand:
\_ref_obj: (PR), line:49
|vpiName:PR
|vpiOperand:
\_operation: , line:49
|vpiOpType:33
|vpiOperand:
\_constant: , line:49
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiOperand:
\_ref_obj: (B_3), line:49
|vpiName:B_3
|vpiFullName:work@div_radix4_ET.B_3
|vpiLhs:
\_ref_obj: (new_PR_3), line:49
|vpiName:new_PR_3
|vpiFullName:work@div_radix4_ET.new_PR_3
|vpiContAssign:
\_cont_assign: , line:50
|vpiRhs:
\_operation: , line:50
|vpiOpType:33
|vpiOperand:
\_bit_select: (new_PR_3), line:50
|vpiName:new_PR_3
|vpiIndex:
\_operation: , line:50
|vpiOpType:24
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:50
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:50
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiOperand:
\_bit_select: (new_PR_2), line:50
|vpiName:new_PR_2
|vpiIndex:
\_operation: , line:50
|vpiOpType:24
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:50
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:50
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiOperand:
\_bit_select: (new_PR_1), line:50
|vpiName:new_PR_1
|vpiIndex:
\_operation: , line:50
|vpiOpType:24
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:50
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:50
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiLhs:
\_ref_obj: (new_PR_sign), line:50
|vpiName:new_PR_sign
|vpiFullName:work@div_radix4_ET.new_PR_sign
|vpiContAssign:
\_cont_assign: , line:57
|vpiRhs:
\_operation: , line:57
|vpiOpType:18
|vpiOperand:
\_ref_obj: (div.divisor), line:57
|vpiName:div.divisor
|vpiFullName:work@div_radix4_ET.div.divisor
|vpiOperand:
\_ref_obj: (div.dividend), line:57
|vpiName:div.dividend
|vpiFullName:work@div_radix4_ET.div.dividend
|vpiLhs:
\_ref_obj: (terminate_early), line:57
|vpiName:terminate_early
|vpiFullName:work@div_radix4_ET.terminate_early
|vpiContAssign:
\_cont_assign: , line:95
|vpiRhs:
\_part_select: , line:95, parent:PR
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (PR)
|vpiLeftRange:
\_operation: , line:95
|vpiOpType:24
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:95
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:95
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:95
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiLhs:
\_ref_obj: (div.remainder), line:95
|vpiName:div.remainder
|vpiFullName:work@div_radix4_ET.div.remainder
|vpiNet:
\_logic_net: (clk), line:27
|vpiNet:
\_logic_net: (rst), line:28
|vpiNet:
\_logic_net: (terminate), line:32
|vpiName:terminate
|vpiFullName:work@div_radix4_ET.terminate
|vpiNetType:36
|vpiNet:
\_logic_net: (terminate_early), line:33
|vpiName:terminate_early
|vpiFullName:work@div_radix4_ET.terminate_early
|vpiNetType:36
|vpiNet:
\_logic_net: (shift_count), line:34
|vpiName:shift_count
|vpiFullName:work@div_radix4_ET.shift_count
|vpiNetType:36
|vpiNet:
\_logic_net: (PR), line:36
|vpiName:PR
|vpiFullName:work@div_radix4_ET.PR
|vpiNetType:36
|vpiNet:
\_logic_net: (new_PR_sign), line:37
|vpiName:new_PR_sign
|vpiFullName:work@div_radix4_ET.new_PR_sign
|vpiNetType:36
|vpiNet:
\_logic_net: (new_PR_1), line:38
|vpiName:new_PR_1
|vpiFullName:work@div_radix4_ET.new_PR_1
|vpiNetType:36
|vpiNet:
\_logic_net: (new_PR_2), line:39
|vpiName:new_PR_2
|vpiFullName:work@div_radix4_ET.new_PR_2
|vpiNetType:36
|vpiNet:
\_logic_net: (new_PR_3), line:40
|vpiName:new_PR_3
|vpiFullName:work@div_radix4_ET.new_PR_3
|vpiNetType:36
|vpiNet:
\_logic_net: (B_1), line:41
|vpiName:B_1
|vpiFullName:work@div_radix4_ET.B_1
|vpiNetType:36
|vpiNet:
\_logic_net: (B_2), line:42
|vpiName:B_2
|vpiFullName:work@div_radix4_ET.B_2
|vpiNetType:36
|vpiNet:
\_logic_net: (B_3), line:43
|vpiName:B_3
|vpiFullName:work@div_radix4_ET.B_3
|vpiNetType:36
|vpiNet:
\_logic_net: (div), line:29
|vpiName:div
|vpiFullName:work@div_radix4_ET.div
|uhdmallModules:
\_module: work@div_radix4_ET_full, file:third_party/cores/taiga/core/div_algorithms/div_radix4_ET_full.sv, line:25, parent:work@div_unit_core_wrapper
|vpiDefName:work@div_radix4_ET_full
|vpiFullName:work@div_radix4_ET_full
|vpiProcess:
\_always: , line:60
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:60
|vpiCondition:
\_operation: , line:60
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:60
|vpiName:clk
|vpiFullName:work@div_radix4_ET_full.clk
|vpiStmt:
\_begin: , line:60
|vpiFullName:work@div_radix4_ET_full
|vpiStmt:
\_if_else: , line:61
|vpiCondition:
\_ref_obj: (div.start), line:61
|vpiName:div.start
|vpiFullName:work@div_radix4_ET_full.div.start
|vpiStmt:
\_assignment: , line:62
|vpiOpType:82
|vpiLhs:
\_ref_obj: (shift_count), line:62
|vpiName:shift_count
|vpiFullName:work@div_radix4_ET_full.shift_count
|vpiRhs:
\_constant: , line:62
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiElseStmt:
\_assignment: , line:64
|vpiOpType:82
|vpiLhs:
\_ref_obj: (shift_count), line:64
|vpiName:shift_count
|vpiFullName:work@div_radix4_ET_full.shift_count
|vpiRhs:
\_operation: , line:64
|vpiOpType:33
|vpiOperand:
\_part_select: , line:64, parent:shift_count
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (shift_count)
|vpiLeftRange:
\_constant: , line:64
|vpiConstType:7
|vpiDecompile:14
|vpiSize:32
|INT:14
|vpiRightRange:
\_constant: , line:64
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiOperand:
\_ref_obj: (div.start), line:64
|vpiName:div.start
|vpiProcess:
\_always: , line:67
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:67
|vpiCondition:
\_operation: , line:67
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:67
|vpiName:clk
|vpiFullName:work@div_radix4_ET_full.clk
|vpiStmt:
\_begin: , line:67
|vpiFullName:work@div_radix4_ET_full
|vpiStmt:
\_if_else: , line:68
|vpiCondition:
\_ref_obj: (div.start), line:68
|vpiName:div.start
|vpiFullName:work@div_radix4_ET_full.div.start
|vpiStmt:
\_begin: , line:68
|vpiFullName:work@div_radix4_ET_full
|vpiStmt:
\_assignment: , line:69
|vpiOpType:82
|vpiLhs:
\_ref_obj: (shift_num_R), line:69
|vpiName:shift_num_R
|vpiFullName:work@div_radix4_ET_full.shift_num_R
|vpiRhs:
\_constant: , line:69
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiStmt:
\_assignment: , line:70
|vpiOpType:82
|vpiLhs:
\_ref_obj: (shift_num_Q), line:70
|vpiName:shift_num_Q
|vpiFullName:work@div_radix4_ET_full.shift_num_Q
|vpiRhs:
\_constant: , line:70
|vpiConstType:7
|vpiDecompile:32
|vpiSize:32
|INT:32
|vpiElseStmt:
\_if_stmt: , line:72
|vpiCondition:
\_operation: , line:72
|vpiOpType:28
|vpiOperand:
\_operation: , line:72
|vpiOpType:4
|vpiOperand:
\_ref_obj: (terminate), line:72
|vpiName:terminate
|vpiFullName:work@div_radix4_ET_full.terminate
|vpiOperand:
\_operation: , line:72
|vpiOpType:4
|vpiOperand:
\_ref_obj: (terminate_early), line:72
|vpiName:terminate_early
|vpiFullName:work@div_radix4_ET_full.terminate_early
|vpiStmt:
\_begin: , line:72
|vpiFullName:work@div_radix4_ET_full
|vpiStmt:
\_assignment: , line:73
|vpiOpType:82
|vpiLhs:
\_ref_obj: (shift_num_R), line:73
|vpiName:shift_num_R
|vpiFullName:work@div_radix4_ET_full.shift_num_R
|vpiRhs:
\_operation: , line:73
|vpiOpType:24
|vpiOperand:
\_ref_obj: (shift_num_R), line:73
|vpiName:shift_num_R
|vpiFullName:work@div_radix4_ET_full.shift_num_R
|vpiOperand:
\_constant: , line:73
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiStmt:
\_assignment: , line:74
|vpiOpType:82
|vpiLhs:
\_ref_obj: (shift_num_Q), line:74
|vpiName:shift_num_Q
|vpiFullName:work@div_radix4_ET_full.shift_num_Q
|vpiRhs:
\_operation: , line:74
|vpiOpType:11
|vpiOperand:
\_ref_obj: (shift_num_Q), line:74
|vpiName:shift_num_Q
|vpiFullName:work@div_radix4_ET_full.shift_num_Q
|vpiOperand:
\_constant: , line:74
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiProcess:
\_always: , line:83
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:83
|vpiCondition:
\_operation: , line:83
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:83
|vpiName:clk
|vpiFullName:work@div_radix4_ET_full.clk
|vpiStmt:
\_begin: , line:83
|vpiFullName:work@div_radix4_ET_full
|vpiStmt:
\_if_else: , line:84
|vpiCondition:
\_ref_obj: (div.start), line:84
|vpiName:div.start
|vpiFullName:work@div_radix4_ET_full.div.start
|vpiStmt:
\_begin: , line:84
|vpiFullName:work@div_radix4_ET_full
|vpiStmt:
\_assignment: , line:85
|vpiOpType:82
|vpiLhs:
\_ref_obj: (PR), line:85
|vpiName:PR
|vpiFullName:work@div_radix4_ET_full.PR
|vpiRhs:
\_operation: , line:85
|vpiOpType:33
|vpiOperand:
\_operation: , line:85
|vpiOpType:34
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:85
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_operation:
|vpiOpType:33
|vpiOperand:
\_constant: , line:85
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiOperand:
\_ref_obj: (div.dividend), line:85
|vpiName:div.dividend
|vpiStmt:
\_assignment: , line:86
|vpiOpType:82
|vpiLhs:
\_ref_obj: (Q_temp), line:86
|vpiName:Q_temp
|vpiFullName:work@div_radix4_ET_full.Q_temp
|vpiRhs:
\_constant: , line:86
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiStmt:
\_assignment: , line:87
|vpiOpType:82
|vpiLhs:
\_ref_obj: (AR_r), line:87
|vpiName:AR_r
|vpiFullName:work@div_radix4_ET_full.AR_r
|vpiRhs:
\_operation: , line:87
|vpiOpType:33
|vpiOperand:
\_ref_obj: (div.dividend), line:87
|vpiName:div.dividend
|vpiOperand:
\_constant: , line:87
|vpiConstType:3
|vpiDecompile:2'b00
|vpiSize:2
|BIN:2'b00
|vpiStmt:
\_assignment: , line:88
|vpiOpType:82
|vpiLhs:
\_ref_obj: (B_r), line:88
|vpiName:B_r
|vpiFullName:work@div_radix4_ET_full.B_r
|vpiRhs:
\_ref_obj: (div.divisor), line:88
|vpiName:div.divisor
|vpiFullName:work@div_radix4_ET_full.div.divisor
|vpiStmt:
\_assignment: , line:89
|vpiOpType:82
|vpiLhs:
\_ref_obj: (B_1), line:89
|vpiName:B_1
|vpiFullName:work@div_radix4_ET_full.B_1
|vpiRhs:
\_operation: , line:89
|vpiOpType:33
|vpiOperand:
\_constant: , line:89
|vpiConstType:3
|vpiDecompile:2'b0
|vpiSize:2
|BIN:2'b0
|vpiOperand:
\_ref_obj: (div.divisor), line:89
|vpiName:div.divisor
|vpiStmt:
\_assignment: , line:90
|vpiOpType:82
|vpiLhs:
\_ref_obj: (B_2), line:90
|vpiName:B_2
|vpiFullName:work@div_radix4_ET_full.B_2
|vpiRhs:
\_operation: , line:90
|vpiOpType:33
|vpiOperand:
\_constant: , line:90
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiOperand:
\_ref_obj: (div.divisor), line:90
|vpiName:div.divisor
|vpiOperand:
\_constant: , line:90
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiStmt:
\_assignment: , line:91
|vpiOpType:82
|vpiLhs:
\_ref_obj: (B_3), line:91
|vpiName:B_3
|vpiFullName:work@div_radix4_ET_full.B_3
|vpiRhs:
\_operation: , line:91
|vpiOpType:24
|vpiOperand:
\_operation: , line:91
|vpiOpType:33
|vpiOperand:
\_constant: , line:91
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiOperand:
\_ref_obj: (div.divisor), line:91
|vpiName:div.divisor
|vpiOperand:
\_constant: , line:91
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiOperand:
\_operation: , line:91
|vpiOpType:33
|vpiOperand:
\_constant: , line:91
|vpiConstType:3
|vpiDecompile:2'b0
|vpiSize:2
|BIN:2'b0
|vpiOperand:
\_ref_obj: (div.divisor), line:91
|vpiName:div.divisor
|vpiFullName:work@div_radix4_ET_full.div.divisor
|vpiElseStmt:
\_if_stmt: , line:92
|vpiCondition:
\_operation: , line:92
|vpiOpType:28
|vpiOperand:
\_operation: , line:92
|vpiOpType:4
|vpiOperand:
\_ref_obj: (terminate), line:92
|vpiName:terminate
|vpiFullName:work@div_radix4_ET_full.terminate
|vpiOperand:
\_operation: , line:92
|vpiOpType:4
|vpiOperand:
\_ref_obj: (terminate_early), line:92
|vpiName:terminate_early
|vpiFullName:work@div_radix4_ET_full.terminate_early
|vpiStmt:
\_begin: , line:92
|vpiFullName:work@div_radix4_ET_full
|vpiStmt:
\_assignment: , line:93
|vpiOpType:82
|vpiLhs:
\_ref_obj: (AR_r), line:93
|vpiName:AR_r
|vpiFullName:work@div_radix4_ET_full.AR_r
|vpiRhs:
\_operation: , line:93
|vpiOpType:33
|vpiOperand:
\_part_select: , line:93, parent:AR_r
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (AR_r)
|vpiLeftRange:
\_operation: , line:93
|vpiOpType:11
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:93
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:93
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiRightRange:
\_constant: , line:93
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiOperand:
\_constant: , line:93
|vpiConstType:3
|vpiDecompile:2'b00
|vpiSize:2
|BIN:2'b00
|vpiStmt:
\_case_stmt: , line:94
|vpiCaseType:1
|vpiCondition:
\_ref_obj: (new_PR_sign), line:94
|vpiName:new_PR_sign
|vpiFullName:work@div_radix4_ET_full.new_PR_sign
|vpiCaseItem:
\_case_item: , line:95
|vpiExpr:
\_constant: , line:95
|vpiConstType:3
|vpiDecompile:3'b111
|vpiSize:3
|BIN:3'b111
|vpiStmt:
\_begin: , line:95
|vpiFullName:work@div_radix4_ET_full
|vpiStmt:
\_assignment: , line:96
|vpiOpType:82
|vpiLhs:
\_ref_obj: (PR), line:96
|vpiName:PR
|vpiFullName:work@div_radix4_ET_full.PR
|vpiRhs:
\_operation: , line:96
|vpiOpType:33
|vpiOperand:
\_part_select: , line:96, parent:PR
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (PR)
|vpiLeftRange:
\_operation: , line:96
|vpiOpType:11
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:96
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:96
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:96
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiOperand:
\_part_select: , line:96, parent:AR_r
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (AR_r)
|vpiLeftRange:
\_operation: , line:96
|vpiOpType:11
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:96
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:96
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_operation: , line:96
|vpiOpType:11
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:96
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:96
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiStmt:
\_assignment: , line:97
|vpiOpType:82
|vpiLhs:
\_ref_obj: (Q_temp), line:97
|vpiName:Q_temp
|vpiFullName:work@div_radix4_ET_full.Q_temp
|vpiRhs:
\_operation: , line:97
|vpiOpType:33
|vpiOperand:
\_ref_obj: (div.quotient), line:97
|vpiName:div.quotient
|vpiOperand:
\_constant: , line:97
|vpiConstType:3
|vpiDecompile:2'b00
|vpiSize:2
|BIN:2'b00
|vpiCaseItem:
\_case_item: , line:99
|vpiExpr:
\_constant: , line:99
|vpiConstType:3
|vpiDecompile:3'b110
|vpiSize:3
|BIN:3'b110
|vpiStmt:
\_begin: , line:99
|vpiFullName:work@div_radix4_ET_full
|vpiStmt:
\_assignment: , line:100
|vpiOpType:82
|vpiLhs:
\_ref_obj: (PR), line:100
|vpiName:PR
|vpiFullName:work@div_radix4_ET_full.PR
|vpiRhs:
\_operation: , line:100
|vpiOpType:33
|vpiOperand:
\_part_select: , line:100, parent:new_PR_1
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (new_PR_1)
|vpiLeftRange:
\_operation: , line:100
|vpiOpType:11
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:100
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:100
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:100
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiOperand:
\_part_select: , line:100, parent:AR_r
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (AR_r)
|vpiLeftRange:
\_operation: , line:100
|vpiOpType:11
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:100
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:100
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_operation: , line:100
|vpiOpType:11
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:100
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:100
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiStmt:
\_assignment: , line:101
|vpiOpType:82
|vpiLhs:
\_ref_obj: (Q_temp), line:101
|vpiName:Q_temp
|vpiFullName:work@div_radix4_ET_full.Q_temp
|vpiRhs:
\_operation: , line:101
|vpiOpType:33
|vpiOperand:
\_ref_obj: (div.quotient), line:101
|vpiName:div.quotient
|vpiOperand:
\_constant: , line:101
|vpiConstType:3
|vpiDecompile:2'b01
|vpiSize:2
|BIN:2'b01
|vpiCaseItem:
\_case_item: , line:103
|vpiExpr:
\_constant: , line:103
|vpiConstType:3
|vpiDecompile:3'b100
|vpiSize:3
|BIN:3'b100
|vpiStmt:
\_begin: , line:103
|vpiFullName:work@div_radix4_ET_full
|vpiStmt:
\_assignment: , line:104
|vpiOpType:82
|vpiLhs:
\_ref_obj: (PR), line:104
|vpiName:PR
|vpiFullName:work@div_radix4_ET_full.PR
|vpiRhs:
\_operation: , line:104
|vpiOpType:33
|vpiOperand:
\_part_select: , line:104, parent:new_PR_2
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (new_PR_2)
|vpiLeftRange:
\_operation: , line:104
|vpiOpType:11
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:104
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:104
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:104
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiOperand:
\_part_select: , line:104, parent:AR_r
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (AR_r)
|vpiLeftRange:
\_operation: , line:104
|vpiOpType:11
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:104
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:104
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_operation: , line:104
|vpiOpType:11
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:104
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:104
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiStmt:
\_assignment: , line:105
|vpiOpType:82
|vpiLhs:
\_ref_obj: (Q_temp), line:105
|vpiName:Q_temp
|vpiFullName:work@div_radix4_ET_full.Q_temp
|vpiRhs:
\_operation: , line:105
|vpiOpType:33
|vpiOperand:
\_ref_obj: (div.quotient), line:105
|vpiName:div.quotient
|vpiOperand:
\_constant: , line:105
|vpiConstType:3
|vpiDecompile:2'b10
|vpiSize:2
|BIN:2'b10
|vpiCaseItem:
\_case_item: , line:107
|vpiStmt:
\_begin: , line:107
|vpiFullName:work@div_radix4_ET_full
|vpiStmt:
\_assignment: , line:108
|vpiOpType:82
|vpiLhs:
\_ref_obj: (PR), line:108
|vpiName:PR
|vpiFullName:work@div_radix4_ET_full.PR
|vpiRhs:
\_operation: , line:108
|vpiOpType:33
|vpiOperand:
\_part_select: , line:108, parent:new_PR_3
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (new_PR_3)
|vpiLeftRange:
\_operation: , line:108
|vpiOpType:11
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:108
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:108
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:108
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiOperand:
\_part_select: , line:108, parent:AR_r
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (AR_r)
|vpiLeftRange:
\_operation: , line:108
|vpiOpType:11
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:108
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:108
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_operation: , line:108
|vpiOpType:11
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:108
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:108
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiStmt:
\_assignment: , line:109
|vpiOpType:82
|vpiLhs:
\_ref_obj: (Q_temp), line:109
|vpiName:Q_temp
|vpiFullName:work@div_radix4_ET_full.Q_temp
|vpiRhs:
\_operation: , line:109
|vpiOpType:33
|vpiOperand:
\_ref_obj: (div.quotient), line:109
|vpiName:div.quotient
|vpiOperand:
\_constant: , line:109
|vpiConstType:3
|vpiDecompile:2'b11
|vpiSize:2
|BIN:2'b11
|vpiProcess:
\_always: , line:115
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:115
|vpiCondition:
\_operation: , line:115
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:115
|vpiName:clk
|vpiFullName:work@div_radix4_ET_full.clk
|vpiStmt:
\_begin: , line:115
|vpiFullName:work@div_radix4_ET_full
|vpiStmt:
\_if_else: , line:116
|vpiCondition:
\_ref_obj: (div.start), line:116
|vpiName:div.start
|vpiFullName:work@div_radix4_ET_full.div.start
|vpiStmt:
\_assignment: , line:117
|vpiOpType:82
|vpiLhs:
\_ref_obj: (div.divisor_is_zero), line:117
|vpiName:div.divisor_is_zero
|vpiFullName:work@div_radix4_ET_full.div.divisor_is_zero
|vpiRhs:
\_operation: , line:117
|vpiOpType:4
|vpiOperand:
\_ref_obj: (div.divisor), line:117
|vpiName:div.divisor
|vpiFullName:work@div_radix4_ET_full.div.divisor
|vpiElseStmt:
\_if_stmt: , line:118
|vpiCondition:
\_operation: , line:118
|vpiOpType:4
|vpiOperand:
\_ref_obj: (terminate), line:118
|vpiName:terminate
|vpiFullName:work@div_radix4_ET_full.terminate
|vpiStmt:
\_assignment: , line:119
|vpiOpType:82
|vpiLhs:
\_ref_obj: (div.divisor_is_zero), line:119
|vpiName:div.divisor_is_zero
|vpiFullName:work@div_radix4_ET_full.div.divisor_is_zero
|vpiRhs:
\_operation: , line:119
|vpiOpType:28
|vpiOperand:
\_ref_obj: (div.divisor_is_zero), line:119
|vpiName:div.divisor_is_zero
|vpiFullName:work@div_radix4_ET_full.div.divisor_is_zero
|vpiOperand:
\_operation: , line:119
|vpiOpType:4
|vpiOperand:
\_operation: , line:119
|vpiOpType:7
|vpiOperand:
\_ref_obj: (new_PR_sign), line:119
|vpiName:new_PR_sign
|vpiFullName:work@div_radix4_ET_full.new_PR_sign
|vpiProcess:
\_always: , line:122
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:122
|vpiCondition:
\_operation: , line:122
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:122
|vpiName:clk
|vpiFullName:work@div_radix4_ET_full.clk
|vpiStmt:
\_begin: , line:122
|vpiFullName:work@div_radix4_ET_full
|vpiStmt:
\_if_else: , line:123
|vpiCondition:
\_ref_obj: (rst), line:123
|vpiName:rst
|vpiFullName:work@div_radix4_ET_full.rst
|vpiStmt:
\_assignment: , line:124
|vpiOpType:82
|vpiLhs:
\_ref_obj: (terminate), line:124
|vpiName:terminate
|vpiFullName:work@div_radix4_ET_full.terminate
|vpiRhs:
\_constant: , line:124
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiElseStmt:
\_begin: , line:125
|vpiFullName:work@div_radix4_ET_full
|vpiStmt:
\_if_else: , line:126
|vpiCondition:
\_ref_obj: (div.start), line:126
|vpiName:div.start
|vpiFullName:work@div_radix4_ET_full.div.start
|vpiStmt:
\_assignment: , line:127
|vpiOpType:82
|vpiLhs:
\_ref_obj: (terminate), line:127
|vpiName:terminate
|vpiFullName:work@div_radix4_ET_full.terminate
|vpiRhs:
\_constant: , line:127
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiElseStmt:
\_if_stmt: , line:128
|vpiCondition:
\_operation: , line:128
|vpiOpType:29
|vpiOperand:
\_bit_select: (shift_count), line:128
|vpiName:shift_count
|vpiFullName:work@div_radix4_ET_full.shift_count
|vpiIndex:
\_constant: , line:128
|vpiConstType:7
|vpiDecompile:15
|vpiSize:32
|INT:15
|vpiOperand:
\_ref_obj: (terminate_early), line:128
|vpiName:terminate_early
|vpiFullName:work@div_radix4_ET_full.terminate_early
|vpiStmt:
\_assignment: , line:129
|vpiOpType:82
|vpiLhs:
\_ref_obj: (terminate), line:129
|vpiName:terminate
|vpiFullName:work@div_radix4_ET_full.terminate
|vpiRhs:
\_constant: , line:129
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiProcess:
\_always: , line:133
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:133
|vpiCondition:
\_operation: , line:133
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:133
|vpiName:clk
|vpiFullName:work@div_radix4_ET_full.clk
|vpiStmt:
\_begin: , line:133
|vpiFullName:work@div_radix4_ET_full
|vpiStmt:
\_if_else: , line:134
|vpiCondition:
\_ref_obj: (rst), line:134
|vpiName:rst
|vpiFullName:work@div_radix4_ET_full.rst
|vpiStmt:
\_assignment: , line:135
|vpiOpType:82
|vpiLhs:
\_ref_obj: (div.done), line:135
|vpiName:div.done
|vpiFullName:work@div_radix4_ET_full.div.done
|vpiRhs:
\_constant: , line:135
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiElseStmt:
\_begin: , line:136
|vpiFullName:work@div_radix4_ET_full
|vpiStmt:
\_if_else: , line:137
|vpiCondition:
\_operation: , line:137
|vpiOpType:28
|vpiOperand:
\_operation: , line:137
|vpiOpType:28
|vpiOperand:
\_operation: , line:137
|vpiOpType:28
|vpiOperand:
\_operation: , line:137
|vpiOpType:4
|vpiOperand:
\_ref_obj: (div.start), line:137
|vpiName:div.start
|vpiFullName:work@div_radix4_ET_full.div.start
|vpiOperand:
\_operation: , line:137
|vpiOpType:29
|vpiOperand:
\_bit_select: (shift_count), line:137
|vpiName:shift_count
|vpiFullName:work@div_radix4_ET_full.shift_count
|vpiIndex:
\_constant: , line:137
|vpiConstType:7
|vpiDecompile:15
|vpiSize:32
|INT:15
|vpiOperand:
\_ref_obj: (terminate_early), line:137
|vpiName:terminate_early
|vpiFullName:work@div_radix4_ET_full.terminate_early
|vpiOperand:
\_operation: , line:137
|vpiOpType:4
|vpiOperand:
\_ref_obj: (div.done), line:137
|vpiName:div.done
|vpiFullName:work@div_radix4_ET_full.div.done
|vpiOperand:
\_operation: , line:137
|vpiOpType:4
|vpiOperand:
\_ref_obj: (terminate), line:137
|vpiName:terminate
|vpiFullName:work@div_radix4_ET_full.terminate
|vpiStmt:
\_assignment: , line:138
|vpiOpType:82
|vpiLhs:
\_ref_obj: (div.done), line:138
|vpiName:div.done
|vpiFullName:work@div_radix4_ET_full.div.done
|vpiRhs:
\_constant: , line:138
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiElseStmt:
\_if_stmt: , line:139
|vpiCondition:
\_ref_obj: (div.done), line:139
|vpiName:div.done
|vpiFullName:work@div_radix4_ET_full.div.done
|vpiStmt:
\_assignment: , line:140
|vpiOpType:82
|vpiLhs:
\_ref_obj: (div.done), line:140
|vpiName:div.done
|vpiFullName:work@div_radix4_ET_full.div.done
|vpiRhs:
\_constant: , line:140
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiPort:
\_port: (clk), line:27
|vpiName:clk
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (clk), line:27
|vpiName:clk
|vpiFullName:work@div_radix4_ET_full.clk
|vpiNetType:36
|vpiPort:
\_port: (rst), line:28
|vpiName:rst
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (rst), line:28
|vpiName:rst
|vpiFullName:work@div_radix4_ET_full.rst
|vpiNetType:36
|vpiPort:
\_port: (div), line:29
|vpiName:div
|vpiDirection:5
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_modport: (divider)
|vpiContAssign:
\_cont_assign: , line:54
|vpiRhs:
\_operation: , line:54
|vpiOpType:11
|vpiOperand:
\_operation: , line:54
|vpiOpType:33
|vpiOperand:
\_constant: , line:54
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiOperand:
\_ref_obj: (PR), line:54
|vpiName:PR
|vpiOperand:
\_operation: , line:54
|vpiOpType:33
|vpiOperand:
\_constant: , line:54
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiOperand:
\_ref_obj: (B_1), line:54
|vpiName:B_1
|vpiFullName:work@div_radix4_ET_full.B_1
|vpiLhs:
\_ref_obj: (new_PR_1), line:54
|vpiName:new_PR_1
|vpiFullName:work@div_radix4_ET_full.new_PR_1
|vpiContAssign:
\_cont_assign: , line:55
|vpiRhs:
\_operation: , line:55
|vpiOpType:11
|vpiOperand:
\_operation: , line:55
|vpiOpType:33
|vpiOperand:
\_constant: , line:55
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiOperand:
\_ref_obj: (PR), line:55
|vpiName:PR
|vpiOperand:
\_operation: , line:55
|vpiOpType:33
|vpiOperand:
\_constant: , line:55
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiOperand:
\_ref_obj: (B_2), line:55
|vpiName:B_2
|vpiFullName:work@div_radix4_ET_full.B_2
|vpiLhs:
\_ref_obj: (new_PR_2), line:55
|vpiName:new_PR_2
|vpiFullName:work@div_radix4_ET_full.new_PR_2
|vpiContAssign:
\_cont_assign: , line:56
|vpiRhs:
\_operation: , line:56
|vpiOpType:11
|vpiOperand:
\_operation: , line:56
|vpiOpType:33
|vpiOperand:
\_constant: , line:56
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiOperand:
\_ref_obj: (PR), line:56
|vpiName:PR
|vpiOperand:
\_operation: , line:56
|vpiOpType:33
|vpiOperand:
\_constant: , line:56
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiOperand:
\_ref_obj: (B_3), line:56
|vpiName:B_3
|vpiFullName:work@div_radix4_ET_full.B_3
|vpiLhs:
\_ref_obj: (new_PR_3), line:56
|vpiName:new_PR_3
|vpiFullName:work@div_radix4_ET_full.new_PR_3
|vpiContAssign:
\_cont_assign: , line:57
|vpiRhs:
\_operation: , line:57
|vpiOpType:33
|vpiOperand:
\_bit_select: (new_PR_3), line:57
|vpiName:new_PR_3
|vpiIndex:
\_operation: , line:57
|vpiOpType:24
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:57
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:57
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiOperand:
\_bit_select: (new_PR_2), line:57
|vpiName:new_PR_2
|vpiIndex:
\_operation: , line:57
|vpiOpType:24
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:57
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:57
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiOperand:
\_bit_select: (new_PR_1), line:57
|vpiName:new_PR_1
|vpiIndex:
\_operation: , line:57
|vpiOpType:24
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:57
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:57
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiLhs:
\_ref_obj: (new_PR_sign), line:57
|vpiName:new_PR_sign
|vpiFullName:work@div_radix4_ET_full.new_PR_sign
|vpiContAssign:
\_cont_assign: , line:78
|vpiRhs:
\_operation: , line:78
|vpiOpType:23
|vpiOperand:
\_operation: , line:78
|vpiOpType:33
|vpiOperand:
\_part_select: , line:78, parent:PR
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (PR)
|vpiLeftRange:
\_ref_obj: (div.DATA_WIDTH), line:78
|vpiName:div.DATA_WIDTH
|vpiRightRange:
\_constant: , line:78
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiOperand:
\_ref_obj: (AR_r), line:78
|vpiName:AR_r
|vpiOperand:
\_ref_obj: (shift_num_R), line:78
|vpiName:shift_num_R
|vpiFullName:work@div_radix4_ET_full.shift_num_R
|vpiLhs:
\_ref_obj: (combined), line:78
|vpiName:combined
|vpiFullName:work@div_radix4_ET_full.combined
|vpiContAssign:
\_cont_assign: , line:79
|vpiRhs:
\_part_select: , line:79, parent:combined
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (combined)
|vpiLeftRange:
\_operation: , line:79
|vpiOpType:11
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:79
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:79
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:79
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiLhs:
\_ref_obj: (div.remainder), line:79
|vpiName:div.remainder
|vpiFullName:work@div_radix4_ET_full.div.remainder
|vpiContAssign:
\_cont_assign: , line:80
|vpiRhs:
\_operation: , line:80
|vpiOpType:18
|vpiOperand:
\_ref_obj: (B_r), line:80
|vpiName:B_r
|vpiFullName:work@div_radix4_ET_full.B_r
|vpiOperand:
\_ref_obj: (div.remainder), line:80
|vpiName:div.remainder
|vpiFullName:work@div_radix4_ET_full.div.remainder
|vpiLhs:
\_ref_obj: (terminate_early), line:80
|vpiName:terminate_early
|vpiFullName:work@div_radix4_ET_full.terminate_early
|vpiContAssign:
\_cont_assign: , line:81
|vpiRhs:
\_operation: , line:81
|vpiOpType:32
|vpiOperand:
\_ref_obj: (terminate_early), line:81
|vpiName:terminate_early
|vpiFullName:work@div_radix4_ET_full.terminate_early
|vpiOperand:
\_operation: , line:81
|vpiOpType:22
|vpiOperand:
\_ref_obj: (Q_temp), line:81
|vpiName:Q_temp
|vpiFullName:work@div_radix4_ET_full.Q_temp
|vpiOperand:
\_ref_obj: (shift_num_Q), line:81
|vpiName:shift_num_Q
|vpiFullName:work@div_radix4_ET_full.shift_num_Q
|vpiOperand:
\_ref_obj: (Q_temp), line:81
|vpiName:Q_temp
|vpiFullName:work@div_radix4_ET_full.Q_temp
|vpiLhs:
\_ref_obj: (div.quotient), line:81
|vpiName:div.quotient
|vpiFullName:work@div_radix4_ET_full.div.quotient
|vpiNet:
\_logic_net: (clk), line:27
|vpiNet:
\_logic_net: (rst), line:28
|vpiNet:
\_logic_net: (terminate), line:32
|vpiName:terminate
|vpiFullName:work@div_radix4_ET_full.terminate
|vpiNetType:36
|vpiNet:
\_logic_net: (shift_count), line:33
|vpiName:shift_count
|vpiFullName:work@div_radix4_ET_full.shift_count
|vpiNetType:36
|vpiNet:
\_logic_net: (PR), line:35
|vpiName:PR
|vpiFullName:work@div_radix4_ET_full.PR
|vpiNetType:36
|vpiNet:
\_logic_net: (new_PR_sign), line:36
|vpiName:new_PR_sign
|vpiFullName:work@div_radix4_ET_full.new_PR_sign
|vpiNetType:36
|vpiNet:
\_logic_net: (new_PR_1), line:37
|vpiName:new_PR_1
|vpiFullName:work@div_radix4_ET_full.new_PR_1
|vpiNetType:36
|vpiNet:
\_logic_net: (new_PR_2), line:38
|vpiName:new_PR_2
|vpiFullName:work@div_radix4_ET_full.new_PR_2
|vpiNetType:36
|vpiNet:
\_logic_net: (new_PR_3), line:39
|vpiName:new_PR_3
|vpiFullName:work@div_radix4_ET_full.new_PR_3
|vpiNetType:36
|vpiNet:
\_logic_net: (B_1), line:40
|vpiName:B_1
|vpiFullName:work@div_radix4_ET_full.B_1
|vpiNetType:36
|vpiNet:
\_logic_net: (B_2), line:41
|vpiName:B_2
|vpiFullName:work@div_radix4_ET_full.B_2
|vpiNetType:36
|vpiNet:
\_logic_net: (B_3), line:42
|vpiName:B_3
|vpiFullName:work@div_radix4_ET_full.B_3
|vpiNetType:36
|vpiNet:
\_logic_net: (B_r), line:44
|vpiName:B_r
|vpiFullName:work@div_radix4_ET_full.B_r
|vpiNetType:36
|vpiNet:
\_logic_net: (AR_r), line:45
|vpiName:AR_r
|vpiFullName:work@div_radix4_ET_full.AR_r
|vpiNetType:36
|vpiNet:
\_logic_net: (Q_temp), line:46
|vpiName:Q_temp
|vpiFullName:work@div_radix4_ET_full.Q_temp
|vpiNetType:36
|vpiNet:
\_logic_net: (shift_num_R), line:47
|vpiName:shift_num_R
|vpiFullName:work@div_radix4_ET_full.shift_num_R
|vpiNetType:36
|vpiNet:
\_logic_net: (shift_num_Q), line:48
|vpiName:shift_num_Q
|vpiFullName:work@div_radix4_ET_full.shift_num_Q
|vpiNetType:36
|vpiNet:
\_logic_net: (combined), line:49
|vpiName:combined
|vpiFullName:work@div_radix4_ET_full.combined
|vpiNetType:36
|vpiNet:
\_logic_net: (terminate_early), line:50
|vpiName:terminate_early
|vpiFullName:work@div_radix4_ET_full.terminate_early
|vpiNetType:36
|vpiNet:
\_logic_net: (div), line:29
|vpiName:div
|vpiFullName:work@div_radix4_ET_full.div
|uhdmallModules:
\_module: work@div_radix8, file:third_party/cores/taiga/core/div_algorithms/div_radix8.sv, line:25, parent:work@div_unit_core_wrapper
|vpiDefName:work@div_radix8
|vpiFullName:work@div_radix8
|vpiProcess:
\_always: , line:75
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:75
|vpiCondition:
\_operation: , line:75
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:75
|vpiName:clk
|vpiFullName:work@div_radix8.clk
|vpiStmt:
\_begin: , line:75
|vpiFullName:work@div_radix8
|vpiStmt:
\_assignment: , line:76
|vpiOpType:82
|vpiLhs:
\_ref_obj: (shift_count), line:76
|vpiName:shift_count
|vpiFullName:work@div_radix8.shift_count
|vpiRhs:
\_operation: , line:76
|vpiOpType:33
|vpiOperand:
\_part_select: , line:76, parent:shift_count
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (shift_count)
|vpiLeftRange:
\_constant: , line:76
|vpiConstType:7
|vpiDecompile:9
|vpiSize:32
|INT:9
|vpiRightRange:
\_constant: , line:76
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiOperand:
\_ref_obj: (div.start), line:76
|vpiName:div.start
|vpiProcess:
\_always: , line:79
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:79
|vpiCondition:
\_operation: , line:79
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:79
|vpiName:clk
|vpiFullName:work@div_radix8.clk
|vpiStmt:
\_begin: , line:79
|vpiFullName:work@div_radix8
|vpiStmt:
\_if_else: , line:80
|vpiCondition:
\_ref_obj: (div.start), line:80
|vpiName:div.start
|vpiFullName:work@div_radix8.div.start
|vpiStmt:
\_begin: , line:80
|vpiFullName:work@div_radix8
|vpiStmt:
\_assignment: , line:81
|vpiOpType:82
|vpiLhs:
\_ref_obj: (PR), line:81
|vpiName:PR
|vpiFullName:work@div_radix8.PR
|vpiRhs:
\_operation: , line:81
|vpiOpType:33
|vpiOperand:
\_operation: , line:81
|vpiOpType:34
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:81
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_operation:
|vpiOpType:33
|vpiOperand:
\_constant: , line:81
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiOperand:
\_constant: , line:81
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiOperand:
\_ref_obj: (div.dividend), line:81
|vpiName:div.dividend
|vpiStmt:
\_assignment: , line:82
|vpiOpType:82
|vpiLhs:
\_ref_obj: (Q_33), line:82
|vpiName:Q_33
|vpiFullName:work@div_radix8.Q_33
|vpiRhs:
\_operation: , line:82
|vpiOpType:33
|vpiOperand:
\_ref_obj: (div.dividend), line:82
|vpiName:div.dividend
|vpiOperand:
\_constant: , line:82
|vpiConstType:3
|vpiDecompile:3'b000
|vpiSize:3
|BIN:3'b000
|vpiStmt:
\_assignment: , line:84
|vpiOpType:82
|vpiLhs:
\_ref_obj: (B_1), line:84
|vpiName:B_1
|vpiFullName:work@div_radix8.B_1
|vpiRhs:
\_operation: , line:84
|vpiOpType:33
|vpiOperand:
\_constant: , line:84
|vpiConstType:3
|vpiDecompile:3'b000
|vpiSize:3
|BIN:3'b000
|vpiOperand:
\_ref_obj: (div.divisor), line:84
|vpiName:div.divisor
|vpiStmt:
\_assignment: , line:85
|vpiOpType:82
|vpiLhs:
\_ref_obj: (B_2), line:85
|vpiName:B_2
|vpiFullName:work@div_radix8.B_2
|vpiRhs:
\_operation: , line:85
|vpiOpType:33
|vpiOperand:
\_constant: , line:85
|vpiConstType:3
|vpiDecompile:2'b00
|vpiSize:2
|BIN:2'b00
|vpiOperand:
\_ref_obj: (div.divisor), line:85
|vpiName:div.divisor
|vpiOperand:
\_constant: , line:85
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiStmt:
\_assignment: , line:86
|vpiOpType:82
|vpiLhs:
\_ref_obj: (B_3), line:86
|vpiName:B_3
|vpiFullName:work@div_radix8.B_3
|vpiRhs:
\_operation: , line:86
|vpiOpType:24
|vpiOperand:
\_operation: , line:86
|vpiOpType:33
|vpiOperand:
\_constant: , line:86
|vpiConstType:3
|vpiDecompile:2'b00
|vpiSize:2
|BIN:2'b00
|vpiOperand:
\_ref_obj: (div.divisor), line:86
|vpiName:div.divisor
|vpiOperand:
\_constant: , line:86
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiOperand:
\_operation: , line:86
|vpiOpType:33
|vpiOperand:
\_constant: , line:86
|vpiConstType:3
|vpiDecompile:3'b0
|vpiSize:3
|BIN:3'b0
|vpiOperand:
\_ref_obj: (div.divisor), line:86
|vpiName:div.divisor
|vpiFullName:work@div_radix8.div.divisor
|vpiStmt:
\_assignment: , line:87
|vpiOpType:82
|vpiLhs:
\_ref_obj: (B_4), line:87
|vpiName:B_4
|vpiFullName:work@div_radix8.B_4
|vpiRhs:
\_operation: , line:87
|vpiOpType:33
|vpiOperand:
\_constant: , line:87
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiOperand:
\_ref_obj: (div.divisor), line:87
|vpiName:div.divisor
|vpiOperand:
\_constant: , line:87
|vpiConstType:3
|vpiDecompile:2'b00
|vpiSize:2
|BIN:2'b00
|vpiStmt:
\_assignment: , line:88
|vpiOpType:82
|vpiLhs:
\_ref_obj: (B_5), line:88
|vpiName:B_5
|vpiFullName:work@div_radix8.B_5
|vpiRhs:
\_operation: , line:88
|vpiOpType:24
|vpiOperand:
\_operation: , line:88
|vpiOpType:33
|vpiOperand:
\_constant: , line:88
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiOperand:
\_ref_obj: (div.divisor), line:88
|vpiName:div.divisor
|vpiOperand:
\_constant: , line:88
|vpiConstType:3
|vpiDecompile:2'b00
|vpiSize:2
|BIN:2'b00
|vpiOperand:
\_operation: , line:88
|vpiOpType:33
|vpiOperand:
\_constant: , line:88
|vpiConstType:3
|vpiDecompile:3'b0
|vpiSize:3
|BIN:3'b0
|vpiOperand:
\_ref_obj: (div.divisor), line:88
|vpiName:div.divisor
|vpiFullName:work@div_radix8.div.divisor
|vpiStmt:
\_assignment: , line:89
|vpiOpType:82
|vpiLhs:
\_ref_obj: (B_6), line:89
|vpiName:B_6
|vpiFullName:work@div_radix8.B_6
|vpiRhs:
\_operation: , line:89
|vpiOpType:24
|vpiOperand:
\_operation: , line:89
|vpiOpType:33
|vpiOperand:
\_constant: , line:89
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiOperand:
\_ref_obj: (div.divisor), line:89
|vpiName:div.divisor
|vpiOperand:
\_constant: , line:89
|vpiConstType:3
|vpiDecompile:2'b00
|vpiSize:2
|BIN:2'b00
|vpiOperand:
\_operation: , line:89
|vpiOpType:33
|vpiOperand:
\_constant: , line:89
|vpiConstType:3
|vpiDecompile:2'b00
|vpiSize:2
|BIN:2'b00
|vpiOperand:
\_ref_obj: (div.divisor), line:89
|vpiName:div.divisor
|vpiFullName:work@div_radix8.div.divisor
|vpiOperand:
\_constant: , line:89
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiStmt:
\_assignment: , line:90
|vpiOpType:82
|vpiLhs:
\_ref_obj: (B_7), line:90
|vpiName:B_7
|vpiFullName:work@div_radix8.B_7
|vpiRhs:
\_operation: , line:90
|vpiOpType:24
|vpiOperand:
\_operation: , line:90
|vpiOpType:24
|vpiOperand:
\_operation: , line:90
|vpiOpType:33
|vpiOperand:
\_constant: , line:90
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiOperand:
\_ref_obj: (div.divisor), line:90
|vpiName:div.divisor
|vpiOperand:
\_constant: , line:90
|vpiConstType:3
|vpiDecompile:2'b00
|vpiSize:2
|BIN:2'b00
|vpiOperand:
\_operation: , line:90
|vpiOpType:33
|vpiOperand:
\_constant: , line:90
|vpiConstType:3
|vpiDecompile:2'b00
|vpiSize:2
|BIN:2'b00
|vpiOperand:
\_ref_obj: (div.divisor), line:90
|vpiName:div.divisor
|vpiFullName:work@div_radix8.div.divisor
|vpiOperand:
\_constant: , line:90
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiOperand:
\_operation: , line:90
|vpiOpType:33
|vpiOperand:
\_constant: , line:90
|vpiConstType:3
|vpiDecompile:3'b0
|vpiSize:3
|BIN:3'b0
|vpiOperand:
\_ref_obj: (div.divisor), line:90
|vpiName:div.divisor
|vpiFullName:work@div_radix8.div.divisor
|vpiElseStmt:
\_if_stmt: , line:92
|vpiCondition:
\_operation: , line:92
|vpiOpType:4
|vpiOperand:
\_ref_obj: (terminate), line:92
|vpiName:terminate
|vpiFullName:work@div_radix8.terminate
|vpiStmt:
\_begin: , line:92
|vpiFullName:work@div_radix8
|vpiStmt:
\_case_stmt: , line:93
|vpiCaseType:1
|vpiCondition:
\_ref_obj: (new_PR_sign), line:93
|vpiName:new_PR_sign
|vpiFullName:work@div_radix8.new_PR_sign
|vpiCaseItem:
\_case_item: , line:94
|vpiExpr:
\_constant: , line:94
|vpiConstType:3
|vpiDecompile:7'b1111111
|vpiSize:7
|BIN:7'b1111111
|vpiStmt:
\_begin: , line:94
|vpiFullName:work@div_radix8
|vpiStmt:
\_assignment: , line:95
|vpiOpType:82
|vpiLhs:
\_ref_obj: (PR), line:95
|vpiName:PR
|vpiFullName:work@div_radix8.PR
|vpiRhs:
\_operation: , line:95
|vpiOpType:33
|vpiOperand:
\_part_select: , line:95, parent:PR
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (PR)
|vpiLeftRange:
\_operation: , line:95
|vpiOpType:11
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:95
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:95
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:95
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiOperand:
\_part_select: , line:95, parent:Q_33
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (Q_33)
|vpiLeftRange:
\_ref_obj: (div.DATA_WIDTH), line:95
|vpiName:div.DATA_WIDTH
|vpiRightRange:
\_operation: , line:95
|vpiOpType:11
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:95
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:95
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiStmt:
\_assignment: , line:96
|vpiOpType:82
|vpiLhs:
\_ref_obj: (Q_33), line:96
|vpiName:Q_33
|vpiFullName:work@div_radix8.Q_33
|vpiRhs:
\_operation: , line:96
|vpiOpType:33
|vpiOperand:
\_part_select: , line:96, parent:Q_33
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (Q_33)
|vpiLeftRange:
\_operation: , line:96
|vpiOpType:11
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:96
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:96
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiRightRange:
\_constant: , line:96
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiOperand:
\_constant: , line:96
|vpiConstType:3
|vpiDecompile:3'b000
|vpiSize:3
|BIN:3'b000
|vpiCaseItem:
\_case_item: , line:98
|vpiExpr:
\_constant: , line:98
|vpiConstType:3
|vpiDecompile:7'b1111110
|vpiSize:7
|BIN:7'b1111110
|vpiStmt:
\_begin: , line:98
|vpiFullName:work@div_radix8
|vpiStmt:
\_assignment: , line:99
|vpiOpType:82
|vpiLhs:
\_ref_obj: (PR), line:99
|vpiName:PR
|vpiFullName:work@div_radix8.PR
|vpiRhs:
\_operation: , line:99
|vpiOpType:33
|vpiOperand:
\_part_select: , line:99, parent:new_PR_1
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (new_PR_1)
|vpiLeftRange:
\_operation: , line:99
|vpiOpType:11
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:99
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:99
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:99
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiOperand:
\_part_select: , line:99, parent:Q_33
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (Q_33)
|vpiLeftRange:
\_ref_obj: (div.DATA_WIDTH), line:99
|vpiName:div.DATA_WIDTH
|vpiRightRange:
\_operation: , line:99
|vpiOpType:11
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:99
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:99
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiStmt:
\_assignment: , line:100
|vpiOpType:82
|vpiLhs:
\_ref_obj: (Q_33), line:100
|vpiName:Q_33
|vpiFullName:work@div_radix8.Q_33
|vpiRhs:
\_operation: , line:100
|vpiOpType:33
|vpiOperand:
\_part_select: , line:100, parent:Q_33
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (Q_33)
|vpiLeftRange:
\_operation: , line:100
|vpiOpType:11
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:100
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:100
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiRightRange:
\_constant: , line:100
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiOperand:
\_constant: , line:100
|vpiConstType:3
|vpiDecompile:3'b001
|vpiSize:3
|BIN:3'b001
|vpiCaseItem:
\_case_item: , line:102
|vpiExpr:
\_constant: , line:102
|vpiConstType:3
|vpiDecompile:7'b1111100
|vpiSize:7
|BIN:7'b1111100
|vpiStmt:
\_begin: , line:102
|vpiFullName:work@div_radix8
|vpiStmt:
\_assignment: , line:103
|vpiOpType:82
|vpiLhs:
\_ref_obj: (PR), line:103
|vpiName:PR
|vpiFullName:work@div_radix8.PR
|vpiRhs:
\_operation: , line:103
|vpiOpType:33
|vpiOperand:
\_part_select: , line:103, parent:new_PR_2
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (new_PR_2)
|vpiLeftRange:
\_operation: , line:103
|vpiOpType:11
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:103
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:103
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:103
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiOperand:
\_part_select: , line:103, parent:Q_33
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (Q_33)
|vpiLeftRange:
\_ref_obj: (div.DATA_WIDTH), line:103
|vpiName:div.DATA_WIDTH
|vpiRightRange:
\_operation: , line:103
|vpiOpType:11
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:103
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:103
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiStmt:
\_assignment: , line:104
|vpiOpType:82
|vpiLhs:
\_ref_obj: (Q_33), line:104
|vpiName:Q_33
|vpiFullName:work@div_radix8.Q_33
|vpiRhs:
\_operation: , line:104
|vpiOpType:33
|vpiOperand:
\_part_select: , line:104, parent:Q_33
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (Q_33)
|vpiLeftRange:
\_operation: , line:104
|vpiOpType:11
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:104
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:104
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiRightRange:
\_constant: , line:104
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiOperand:
\_constant: , line:104
|vpiConstType:3
|vpiDecompile:3'b010
|vpiSize:3
|BIN:3'b010
|vpiCaseItem:
\_case_item: , line:106
|vpiExpr:
\_constant: , line:106
|vpiConstType:3
|vpiDecompile:7'b1111000
|vpiSize:7
|BIN:7'b1111000
|vpiStmt:
\_begin: , line:106
|vpiFullName:work@div_radix8
|vpiStmt:
\_assignment: , line:107
|vpiOpType:82
|vpiLhs:
\_ref_obj: (PR), line:107
|vpiName:PR
|vpiFullName:work@div_radix8.PR
|vpiRhs:
\_operation: , line:107
|vpiOpType:33
|vpiOperand:
\_part_select: , line:107, parent:new_PR_3
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (new_PR_3)
|vpiLeftRange:
\_operation: , line:107
|vpiOpType:11
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:107
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:107
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:107
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiOperand:
\_part_select: , line:107, parent:Q_33
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (Q_33)
|vpiLeftRange:
\_ref_obj: (div.DATA_WIDTH), line:107
|vpiName:div.DATA_WIDTH
|vpiRightRange:
\_operation: , line:107
|vpiOpType:11
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:107
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:107
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiStmt:
\_assignment: , line:108
|vpiOpType:82
|vpiLhs:
\_ref_obj: (Q_33), line:108
|vpiName:Q_33
|vpiFullName:work@div_radix8.Q_33
|vpiRhs:
\_operation: , line:108
|vpiOpType:33
|vpiOperand:
\_part_select: , line:108, parent:Q_33
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (Q_33)
|vpiLeftRange:
\_operation: , line:108
|vpiOpType:11
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:108
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:108
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiRightRange:
\_constant: , line:108
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiOperand:
\_constant: , line:108
|vpiConstType:3
|vpiDecompile:3'b011
|vpiSize:3
|BIN:3'b011
|vpiCaseItem:
\_case_item: , line:110
|vpiExpr:
\_constant: , line:110
|vpiConstType:3
|vpiDecompile:7'b1110000
|vpiSize:7
|BIN:7'b1110000
|vpiStmt:
\_begin: , line:110
|vpiFullName:work@div_radix8
|vpiStmt:
\_assignment: , line:111
|vpiOpType:82
|vpiLhs:
\_ref_obj: (PR), line:111
|vpiName:PR
|vpiFullName:work@div_radix8.PR
|vpiRhs:
\_operation: , line:111
|vpiOpType:33
|vpiOperand:
\_part_select: , line:111, parent:new_PR_4
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (new_PR_4)
|vpiLeftRange:
\_operation: , line:111
|vpiOpType:11
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:111
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:111
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:111
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiOperand:
\_part_select: , line:111, parent:Q_33
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (Q_33)
|vpiLeftRange:
\_ref_obj: (div.DATA_WIDTH), line:111
|vpiName:div.DATA_WIDTH
|vpiRightRange:
\_operation: , line:111
|vpiOpType:11
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:111
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:111
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiStmt:
\_assignment: , line:112
|vpiOpType:82
|vpiLhs:
\_ref_obj: (Q_33), line:112
|vpiName:Q_33
|vpiFullName:work@div_radix8.Q_33
|vpiRhs:
\_operation: , line:112
|vpiOpType:33
|vpiOperand:
\_part_select: , line:112, parent:Q_33
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (Q_33)
|vpiLeftRange:
\_operation: , line:112
|vpiOpType:11
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:112
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:112
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiRightRange:
\_constant: , line:112
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiOperand:
\_constant: , line:112
|vpiConstType:3
|vpiDecompile:3'b100
|vpiSize:3
|BIN:3'b100
|vpiCaseItem:
\_case_item: , line:114
|vpiExpr:
\_constant: , line:114
|vpiConstType:3
|vpiDecompile:7'b1100000
|vpiSize:7
|BIN:7'b1100000
|vpiStmt:
\_begin: , line:114
|vpiFullName:work@div_radix8
|vpiStmt:
\_assignment: , line:115
|vpiOpType:82
|vpiLhs:
\_ref_obj: (PR), line:115
|vpiName:PR
|vpiFullName:work@div_radix8.PR
|vpiRhs:
\_operation: , line:115
|vpiOpType:33
|vpiOperand:
\_part_select: , line:115, parent:new_PR_5
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (new_PR_5)
|vpiLeftRange:
\_operation: , line:115
|vpiOpType:11
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:115
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:115
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:115
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiOperand:
\_part_select: , line:115, parent:Q_33
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (Q_33)
|vpiLeftRange:
\_ref_obj: (div.DATA_WIDTH), line:115
|vpiName:div.DATA_WIDTH
|vpiRightRange:
\_operation: , line:115
|vpiOpType:11
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:115
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:115
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiStmt:
\_assignment: , line:116
|vpiOpType:82
|vpiLhs:
\_ref_obj: (Q_33), line:116
|vpiName:Q_33
|vpiFullName:work@div_radix8.Q_33
|vpiRhs:
\_operation: , line:116
|vpiOpType:33
|vpiOperand:
\_part_select: , line:116, parent:Q_33
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (Q_33)
|vpiLeftRange:
\_operation: , line:116
|vpiOpType:11
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:116
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:116
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiRightRange:
\_constant: , line:116
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiOperand:
\_constant: , line:116
|vpiConstType:3
|vpiDecompile:3'b101
|vpiSize:3
|BIN:3'b101
|vpiCaseItem:
\_case_item: , line:118
|vpiExpr:
\_constant: , line:118
|vpiConstType:3
|vpiDecompile:7'b1000000
|vpiSize:7
|BIN:7'b1000000
|vpiStmt:
\_begin: , line:118
|vpiFullName:work@div_radix8
|vpiStmt:
\_assignment: , line:119
|vpiOpType:82
|vpiLhs:
\_ref_obj: (PR), line:119
|vpiName:PR
|vpiFullName:work@div_radix8.PR
|vpiRhs:
\_operation: , line:119
|vpiOpType:33
|vpiOperand:
\_part_select: , line:119, parent:new_PR_6
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (new_PR_6)
|vpiLeftRange:
\_operation: , line:119
|vpiOpType:11
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:119
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:119
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:119
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiOperand:
\_part_select: , line:119, parent:Q_33
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (Q_33)
|vpiLeftRange:
\_ref_obj: (div.DATA_WIDTH), line:119
|vpiName:div.DATA_WIDTH
|vpiRightRange:
\_operation: , line:119
|vpiOpType:11
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:119
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:119
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiStmt:
\_assignment: , line:120
|vpiOpType:82
|vpiLhs:
\_ref_obj: (Q_33), line:120
|vpiName:Q_33
|vpiFullName:work@div_radix8.Q_33
|vpiRhs:
\_operation: , line:120
|vpiOpType:33
|vpiOperand:
\_part_select: , line:120, parent:Q_33
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (Q_33)
|vpiLeftRange:
\_operation: , line:120
|vpiOpType:11
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:120
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:120
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiRightRange:
\_constant: , line:120
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiOperand:
\_constant: , line:120
|vpiConstType:3
|vpiDecompile:3'b110
|vpiSize:3
|BIN:3'b110
|vpiCaseItem:
\_case_item: , line:122
|vpiStmt:
\_begin: , line:122
|vpiFullName:work@div_radix8
|vpiStmt:
\_assignment: , line:123
|vpiOpType:82
|vpiLhs:
\_ref_obj: (PR), line:123
|vpiName:PR
|vpiFullName:work@div_radix8.PR
|vpiRhs:
\_operation: , line:123
|vpiOpType:33
|vpiOperand:
\_part_select: , line:123, parent:new_PR_7
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (new_PR_7)
|vpiLeftRange:
\_operation: , line:123
|vpiOpType:11
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:123
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:123
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:123
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiOperand:
\_part_select: , line:123, parent:Q_33
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (Q_33)
|vpiLeftRange:
\_ref_obj: (div.DATA_WIDTH), line:123
|vpiName:div.DATA_WIDTH
|vpiRightRange:
\_operation: , line:123
|vpiOpType:11
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:123
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:123
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiStmt:
\_assignment: , line:124
|vpiOpType:82
|vpiLhs:
\_ref_obj: (Q_33), line:124
|vpiName:Q_33
|vpiFullName:work@div_radix8.Q_33
|vpiRhs:
\_operation: , line:124
|vpiOpType:33
|vpiOperand:
\_part_select: , line:124, parent:Q_33
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (Q_33)
|vpiLeftRange:
\_operation: , line:124
|vpiOpType:11
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:124
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:124
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiRightRange:
\_constant: , line:124
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiOperand:
\_constant: , line:124
|vpiConstType:3
|vpiDecompile:3'b111
|vpiSize:3
|BIN:3'b111
|vpiProcess:
\_always: , line:133
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:133
|vpiCondition:
\_operation: , line:133
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:133
|vpiName:clk
|vpiFullName:work@div_radix8.clk
|vpiStmt:
\_begin: , line:133
|vpiFullName:work@div_radix8
|vpiStmt:
\_if_else: , line:134
|vpiCondition:
\_ref_obj: (div.start), line:134
|vpiName:div.start
|vpiFullName:work@div_radix8.div.start
|vpiStmt:
\_assignment: , line:135
|vpiOpType:82
|vpiLhs:
\_ref_obj: (div.divisor_is_zero), line:135
|vpiName:div.divisor_is_zero
|vpiFullName:work@div_radix8.div.divisor_is_zero
|vpiRhs:
\_operation: , line:135
|vpiOpType:4
|vpiOperand:
\_ref_obj: (div.divisor), line:135
|vpiName:div.divisor
|vpiFullName:work@div_radix8.div.divisor
|vpiElseStmt:
\_if_stmt: , line:136
|vpiCondition:
\_operation: , line:136
|vpiOpType:4
|vpiOperand:
\_ref_obj: (terminate), line:136
|vpiName:terminate
|vpiFullName:work@div_radix8.terminate
|vpiStmt:
\_assignment: , line:137
|vpiOpType:82
|vpiLhs:
\_ref_obj: (div.divisor_is_zero), line:137
|vpiName:div.divisor_is_zero
|vpiFullName:work@div_radix8.div.divisor_is_zero
|vpiRhs:
\_operation: , line:137
|vpiOpType:28
|vpiOperand:
\_ref_obj: (div.divisor_is_zero), line:137
|vpiName:div.divisor_is_zero
|vpiFullName:work@div_radix8.div.divisor_is_zero
|vpiOperand:
\_operation: , line:137
|vpiOpType:4
|vpiOperand:
\_operation: , line:137
|vpiOpType:7
|vpiOperand:
\_ref_obj: (new_PR_sign), line:137
|vpiName:new_PR_sign
|vpiFullName:work@div_radix8.new_PR_sign
|vpiProcess:
\_always: , line:140
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:140
|vpiCondition:
\_operation: , line:140
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:140
|vpiName:clk
|vpiFullName:work@div_radix8.clk
|vpiStmt:
\_begin: , line:140
|vpiFullName:work@div_radix8
|vpiStmt:
\_if_else: , line:141
|vpiCondition:
\_ref_obj: (rst), line:141
|vpiName:rst
|vpiFullName:work@div_radix8.rst
|vpiStmt:
\_assignment: , line:142
|vpiOpType:82
|vpiLhs:
\_ref_obj: (terminate), line:142
|vpiName:terminate
|vpiFullName:work@div_radix8.terminate
|vpiRhs:
\_constant: , line:142
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiElseStmt:
\_begin: , line:143
|vpiFullName:work@div_radix8
|vpiStmt:
\_if_stmt: , line:144
|vpiCondition:
\_ref_obj: (div.start), line:144
|vpiName:div.start
|vpiFullName:work@div_radix8.div.start
|vpiStmt:
\_assignment: , line:145
|vpiOpType:82
|vpiLhs:
\_ref_obj: (terminate), line:145
|vpiName:terminate
|vpiFullName:work@div_radix8.terminate
|vpiRhs:
\_constant: , line:145
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiStmt:
\_if_stmt: , line:146
|vpiCondition:
\_bit_select: (shift_count), line:146
|vpiName:shift_count
|vpiFullName:work@div_radix8.shift_count
|vpiIndex:
\_constant: , line:146
|vpiConstType:7
|vpiDecompile:10
|vpiSize:32
|INT:10
|vpiStmt:
\_assignment: , line:147
|vpiOpType:82
|vpiLhs:
\_ref_obj: (terminate), line:147
|vpiName:terminate
|vpiFullName:work@div_radix8.terminate
|vpiRhs:
\_constant: , line:147
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiProcess:
\_always: , line:151
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:151
|vpiCondition:
\_operation: , line:151
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:151
|vpiName:clk
|vpiFullName:work@div_radix8.clk
|vpiStmt:
\_begin: , line:151
|vpiFullName:work@div_radix8
|vpiStmt:
\_if_else: , line:152
|vpiCondition:
\_ref_obj: (rst), line:152
|vpiName:rst
|vpiFullName:work@div_radix8.rst
|vpiStmt:
\_assignment: , line:153
|vpiOpType:82
|vpiLhs:
\_ref_obj: (div.done), line:153
|vpiName:div.done
|vpiFullName:work@div_radix8.div.done
|vpiRhs:
\_constant: , line:153
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiElseStmt:
\_begin: , line:154
|vpiFullName:work@div_radix8
|vpiStmt:
\_if_else: , line:155
|vpiCondition:
\_bit_select: (shift_count), line:155
|vpiName:shift_count
|vpiFullName:work@div_radix8.shift_count
|vpiIndex:
\_constant: , line:155
|vpiConstType:7
|vpiDecompile:10
|vpiSize:32
|INT:10
|vpiStmt:
\_assignment: , line:156
|vpiOpType:82
|vpiLhs:
\_ref_obj: (div.done), line:156
|vpiName:div.done
|vpiFullName:work@div_radix8.div.done
|vpiRhs:
\_constant: , line:156
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiElseStmt:
\_if_stmt: , line:157
|vpiCondition:
\_ref_obj: (div.done), line:157
|vpiName:div.done
|vpiFullName:work@div_radix8.div.done
|vpiStmt:
\_assignment: , line:158
|vpiOpType:82
|vpiLhs:
\_ref_obj: (div.done), line:158
|vpiName:div.done
|vpiFullName:work@div_radix8.div.done
|vpiRhs:
\_constant: , line:158
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiPort:
\_port: (clk), line:27
|vpiName:clk
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (clk), line:27
|vpiName:clk
|vpiFullName:work@div_radix8.clk
|vpiNetType:36
|vpiPort:
\_port: (rst), line:28
|vpiName:rst
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (rst), line:28
|vpiName:rst
|vpiFullName:work@div_radix8.rst
|vpiNetType:36
|vpiPort:
\_port: (div), line:29
|vpiName:div
|vpiDirection:5
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_modport: (divider)
|vpiContAssign:
\_cont_assign: , line:63
|vpiRhs:
\_operation: , line:63
|vpiOpType:11
|vpiOperand:
\_operation: , line:63
|vpiOpType:33
|vpiOperand:
\_constant: , line:63
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiOperand:
\_ref_obj: (PR), line:63
|vpiName:PR
|vpiOperand:
\_ref_obj: (B_1), line:63
|vpiName:B_1
|vpiFullName:work@div_radix8.B_1
|vpiLhs:
\_ref_obj: (new_PR_1), line:63
|vpiName:new_PR_1
|vpiFullName:work@div_radix8.new_PR_1
|vpiContAssign:
\_cont_assign: , line:64
|vpiRhs:
\_operation: , line:64
|vpiOpType:11
|vpiOperand:
\_operation: , line:64
|vpiOpType:33
|vpiOperand:
\_constant: , line:64
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiOperand:
\_ref_obj: (PR), line:64
|vpiName:PR
|vpiOperand:
\_ref_obj: (B_2), line:64
|vpiName:B_2
|vpiFullName:work@div_radix8.B_2
|vpiLhs:
\_ref_obj: (new_PR_2), line:64
|vpiName:new_PR_2
|vpiFullName:work@div_radix8.new_PR_2
|vpiContAssign:
\_cont_assign: , line:65
|vpiRhs:
\_operation: , line:65
|vpiOpType:11
|vpiOperand:
\_operation: , line:65
|vpiOpType:33
|vpiOperand:
\_constant: , line:65
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiOperand:
\_ref_obj: (PR), line:65
|vpiName:PR
|vpiOperand:
\_ref_obj: (B_3), line:65
|vpiName:B_3
|vpiFullName:work@div_radix8.B_3
|vpiLhs:
\_ref_obj: (new_PR_3), line:65
|vpiName:new_PR_3
|vpiFullName:work@div_radix8.new_PR_3
|vpiContAssign:
\_cont_assign: , line:66
|vpiRhs:
\_operation: , line:66
|vpiOpType:11
|vpiOperand:
\_operation: , line:66
|vpiOpType:33
|vpiOperand:
\_constant: , line:66
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiOperand:
\_ref_obj: (PR), line:66
|vpiName:PR
|vpiOperand:
\_ref_obj: (B_4), line:66
|vpiName:B_4
|vpiFullName:work@div_radix8.B_4
|vpiLhs:
\_ref_obj: (new_PR_4), line:66
|vpiName:new_PR_4
|vpiFullName:work@div_radix8.new_PR_4
|vpiContAssign:
\_cont_assign: , line:67
|vpiRhs:
\_operation: , line:67
|vpiOpType:11
|vpiOperand:
\_operation: , line:67
|vpiOpType:33
|vpiOperand:
\_constant: , line:67
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiOperand:
\_ref_obj: (PR), line:67
|vpiName:PR
|vpiOperand:
\_ref_obj: (B_5), line:67
|vpiName:B_5
|vpiFullName:work@div_radix8.B_5
|vpiLhs:
\_ref_obj: (new_PR_5), line:67
|vpiName:new_PR_5
|vpiFullName:work@div_radix8.new_PR_5
|vpiContAssign:
\_cont_assign: , line:68
|vpiRhs:
\_operation: , line:68
|vpiOpType:11
|vpiOperand:
\_operation: , line:68
|vpiOpType:33
|vpiOperand:
\_constant: , line:68
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiOperand:
\_ref_obj: (PR), line:68
|vpiName:PR
|vpiOperand:
\_ref_obj: (B_6), line:68
|vpiName:B_6
|vpiFullName:work@div_radix8.B_6
|vpiLhs:
\_ref_obj: (new_PR_6), line:68
|vpiName:new_PR_6
|vpiFullName:work@div_radix8.new_PR_6
|vpiContAssign:
\_cont_assign: , line:69
|vpiRhs:
\_operation: , line:69
|vpiOpType:11
|vpiOperand:
\_operation: , line:69
|vpiOpType:33
|vpiOperand:
\_constant: , line:69
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiOperand:
\_ref_obj: (PR), line:69
|vpiName:PR
|vpiOperand:
\_ref_obj: (B_7), line:69
|vpiName:B_7
|vpiFullName:work@div_radix8.B_7
|vpiLhs:
\_ref_obj: (new_PR_7), line:69
|vpiName:new_PR_7
|vpiFullName:work@div_radix8.new_PR_7
|vpiContAssign:
\_cont_assign: , line:70
|vpiRhs:
\_operation: , line:70
|vpiOpType:33
|vpiOperand:
\_bit_select: (new_PR_7), line:70
|vpiName:new_PR_7
|vpiIndex:
\_operation: , line:70
|vpiOpType:24
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:70
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:70
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiOperand:
\_bit_select: (new_PR_6), line:70
|vpiName:new_PR_6
|vpiIndex:
\_operation: , line:70
|vpiOpType:24
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:70
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:70
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiOperand:
\_bit_select: (new_PR_5), line:70
|vpiName:new_PR_5
|vpiIndex:
\_operation: , line:70
|vpiOpType:24
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:70
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:70
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiOperand:
\_bit_select: (new_PR_4), line:71
|vpiName:new_PR_4
|vpiIndex:
\_operation: , line:71
|vpiOpType:24
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:71
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:71
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiOperand:
\_bit_select: (new_PR_3), line:71
|vpiName:new_PR_3
|vpiIndex:
\_operation: , line:71
|vpiOpType:24
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:71
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:71
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiOperand:
\_bit_select: (new_PR_2), line:71
|vpiName:new_PR_2
|vpiIndex:
\_operation: , line:71
|vpiOpType:24
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:71
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:71
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiOperand:
\_bit_select: (new_PR_1), line:72
|vpiName:new_PR_1
|vpiIndex:
\_operation: , line:72
|vpiOpType:24
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:72
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:72
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiLhs:
\_ref_obj: (new_PR_sign), line:70
|vpiName:new_PR_sign
|vpiFullName:work@div_radix8.new_PR_sign
|vpiContAssign:
\_cont_assign: , line:130
|vpiRhs:
\_part_select: , line:130, parent:PR
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (PR)
|vpiLeftRange:
\_operation: , line:130
|vpiOpType:24
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:130
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:130
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiRightRange:
\_constant: , line:130
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiLhs:
\_ref_obj: (div.remainder), line:130
|vpiName:div.remainder
|vpiFullName:work@div_radix8.div.remainder
|vpiContAssign:
\_cont_assign: , line:131
|vpiRhs:
\_part_select: , line:131, parent:Q_33
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (Q_33)
|vpiLeftRange:
\_operation: , line:131
|vpiOpType:11
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:131
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:131
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:131
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiLhs:
\_ref_obj: (div.quotient), line:131
|vpiName:div.quotient
|vpiFullName:work@div_radix8.div.quotient
|vpiNet:
\_logic_net: (clk), line:27
|vpiNet:
\_logic_net: (rst), line:28
|vpiNet:
\_logic_net: (terminate), line:32
|vpiName:terminate
|vpiFullName:work@div_radix8.terminate
|vpiNetType:36
|vpiNet:
\_logic_net: (shift_count), line:33
|vpiName:shift_count
|vpiFullName:work@div_radix8.shift_count
|vpiNetType:36
|vpiNet:
\_logic_net: (PR), line:35
|vpiName:PR
|vpiFullName:work@div_radix8.PR
|vpiNetType:36
|vpiNet:
\_logic_net: (Q_33), line:36
|vpiName:Q_33
|vpiFullName:work@div_radix8.Q_33
|vpiNetType:36
|vpiNet:
\_logic_net: (new_PR_sign), line:37
|vpiName:new_PR_sign
|vpiFullName:work@div_radix8.new_PR_sign
|vpiNetType:36
|vpiNet:
\_logic_net: (new_PR_1), line:39
|vpiName:new_PR_1
|vpiFullName:work@div_radix8.new_PR_1
|vpiNetType:36
|vpiNet:
\_logic_net: (new_PR_2), line:40
|vpiName:new_PR_2
|vpiFullName:work@div_radix8.new_PR_2
|vpiNetType:36
|vpiNet:
\_logic_net: (new_PR_3), line:41
|vpiName:new_PR_3
|vpiFullName:work@div_radix8.new_PR_3
|vpiNetType:36
|vpiNet:
\_logic_net: (new_PR_4), line:42
|vpiName:new_PR_4
|vpiFullName:work@div_radix8.new_PR_4
|vpiNetType:36
|vpiNet:
\_logic_net: (new_PR_5), line:43
|vpiName:new_PR_5
|vpiFullName:work@div_radix8.new_PR_5
|vpiNetType:36
|vpiNet:
\_logic_net: (new_PR_6), line:44
|vpiName:new_PR_6
|vpiFullName:work@div_radix8.new_PR_6
|vpiNetType:36
|vpiNet:
\_logic_net: (new_PR_7), line:45
|vpiName:new_PR_7
|vpiFullName:work@div_radix8.new_PR_7
|vpiNetType:36
|vpiNet:
\_logic_net: (B_1), line:46
|vpiName:B_1
|vpiFullName:work@div_radix8.B_1
|vpiNetType:36
|vpiNet:
\_logic_net: (B_2), line:47
|vpiName:B_2
|vpiFullName:work@div_radix8.B_2
|vpiNetType:36
|vpiNet:
\_logic_net: (B_3), line:48
|vpiName:B_3
|vpiFullName:work@div_radix8.B_3
|vpiNetType:36
|vpiNet:
\_logic_net: (B_4), line:49
|vpiName:B_4
|vpiFullName:work@div_radix8.B_4
|vpiNetType:36
|vpiNet:
\_logic_net: (B_5), line:50
|vpiName:B_5
|vpiFullName:work@div_radix8.B_5
|vpiNetType:36
|vpiNet:
\_logic_net: (B_6), line:51
|vpiName:B_6
|vpiFullName:work@div_radix8.B_6
|vpiNetType:36
|vpiNet:
\_logic_net: (B_7), line:52
|vpiName:B_7
|vpiFullName:work@div_radix8.B_7
|vpiNetType:36
|vpiNet:
\_logic_net: (div), line:29
|vpiName:div
|vpiFullName:work@div_radix8.div
|uhdmallModules:
\_module: work@div_radix8_ET, file:third_party/cores/taiga/core/div_algorithms/div_radix8_ET.sv, line:25, parent:work@div_unit_core_wrapper
|vpiDefName:work@div_radix8_ET
|vpiFullName:work@div_radix8_ET
|vpiProcess:
\_always: , line:62
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:62
|vpiCondition:
\_operation: , line:62
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:62
|vpiName:clk
|vpiFullName:work@div_radix8_ET.clk
|vpiStmt:
\_begin: , line:62
|vpiFullName:work@div_radix8_ET
|vpiStmt:
\_assignment: , line:63
|vpiOpType:82
|vpiLhs:
\_ref_obj: (shift_count), line:63
|vpiName:shift_count
|vpiFullName:work@div_radix8_ET.shift_count
|vpiRhs:
\_operation: , line:63
|vpiOpType:33
|vpiOperand:
\_part_select: , line:63, parent:shift_count
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (shift_count)
|vpiLeftRange:
\_constant: , line:63
|vpiConstType:7
|vpiDecompile:9
|vpiSize:32
|INT:9
|vpiRightRange:
\_constant: , line:63
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiOperand:
\_operation: , line:63
|vpiOpType:28
|vpiOperand:
\_ref_obj: (div.start), line:63
|vpiName:div.start
|vpiOperand:
\_operation: , line:63
|vpiOpType:4
|vpiOperand:
\_ref_obj: (terminate_early), line:63
|vpiName:terminate_early
|vpiProcess:
\_always: , line:68
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:68
|vpiCondition:
\_operation: , line:68
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:68
|vpiName:clk
|vpiFullName:work@div_radix8_ET.clk
|vpiStmt:
\_begin: , line:68
|vpiFullName:work@div_radix8_ET
|vpiStmt:
\_if_else: , line:69
|vpiCondition:
\_ref_obj: (div.start), line:69
|vpiName:div.start
|vpiFullName:work@div_radix8_ET.div.start
|vpiStmt:
\_begin: , line:69
|vpiFullName:work@div_radix8_ET
|vpiStmt:
\_if_else: , line:70
|vpiCondition:
\_ref_obj: (terminate_early), line:70
|vpiName:terminate_early
|vpiFullName:work@div_radix8_ET.terminate_early
|vpiStmt:
\_begin: , line:70
|vpiFullName:work@div_radix8_ET
|vpiStmt:
\_assignment: , line:71
|vpiOpType:82
|vpiLhs:
\_ref_obj: (PR), line:71
|vpiName:PR
|vpiFullName:work@div_radix8_ET.PR
|vpiRhs:
\_operation: , line:71
|vpiOpType:33
|vpiOperand:
\_ref_obj: (div.dividend), line:71
|vpiName:div.dividend
|vpiOperand:
\_constant: , line:71
|vpiConstType:3
|vpiDecompile:3'b000
|vpiSize:3
|BIN:3'b000
|vpiStmt:
\_assignment: , line:72
|vpiOpType:82
|vpiLhs:
\_ref_obj: (Q_33), line:72
|vpiName:Q_33
|vpiFullName:work@div_radix8_ET.Q_33
|vpiRhs:
\_constant: , line:72
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiElseStmt:
\_begin: , line:73
|vpiFullName:work@div_radix8_ET
|vpiStmt:
\_assignment: , line:74
|vpiOpType:82
|vpiLhs:
\_ref_obj: (PR), line:74
|vpiName:PR
|vpiFullName:work@div_radix8_ET.PR
|vpiRhs:
\_operation: , line:74
|vpiOpType:33
|vpiOperand:
\_operation: , line:74
|vpiOpType:34
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:74
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_operation:
|vpiOpType:33
|vpiOperand:
\_constant: , line:74
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiOperand:
\_constant: , line:74
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiOperand:
\_ref_obj: (div.dividend), line:74
|vpiName:div.dividend
|vpiStmt:
\_assignment: , line:75
|vpiOpType:82
|vpiLhs:
\_ref_obj: (Q_33), line:75
|vpiName:Q_33
|vpiFullName:work@div_radix8_ET.Q_33
|vpiRhs:
\_operation: , line:75
|vpiOpType:33
|vpiOperand:
\_ref_obj: (div.dividend), line:75
|vpiName:div.dividend
|vpiOperand:
\_constant: , line:75
|vpiConstType:3
|vpiDecompile:3'b000
|vpiSize:3
|BIN:3'b000
|vpiElseStmt:
\_if_stmt: , line:78
|vpiCondition:
\_operation: , line:78
|vpiOpType:4
|vpiOperand:
\_ref_obj: (terminate), line:78
|vpiName:terminate
|vpiFullName:work@div_radix8_ET.terminate
|vpiStmt:
\_begin: , line:78
|vpiFullName:work@div_radix8_ET
|vpiStmt:
\_case_stmt: , line:79
|vpiCaseType:1
|vpiCondition:
\_ref_obj: (new_PR_sign), line:79
|vpiName:new_PR_sign
|vpiFullName:work@div_radix8_ET.new_PR_sign
|vpiCaseItem:
\_case_item: , line:80
|vpiExpr:
\_constant: , line:80
|vpiConstType:3
|vpiDecompile:7'b1111111
|vpiSize:7
|BIN:7'b1111111
|vpiStmt:
\_begin: , line:80
|vpiFullName:work@div_radix8_ET
|vpiStmt:
\_assignment: , line:81
|vpiOpType:82
|vpiLhs:
\_ref_obj: (PR), line:81
|vpiName:PR
|vpiFullName:work@div_radix8_ET.PR
|vpiRhs:
\_operation: , line:81
|vpiOpType:33
|vpiOperand:
\_part_select: , line:81, parent:PR
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (PR)
|vpiLeftRange:
\_operation: , line:81
|vpiOpType:11
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:81
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:81
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:81
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiOperand:
\_part_select: , line:81, parent:Q_33
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (Q_33)
|vpiLeftRange:
\_ref_obj: (div.DATA_WIDTH), line:81
|vpiName:div.DATA_WIDTH
|vpiRightRange:
\_operation: , line:81
|vpiOpType:11
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:81
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:81
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiStmt:
\_assignment: , line:82
|vpiOpType:82
|vpiLhs:
\_ref_obj: (Q_33), line:82
|vpiName:Q_33
|vpiFullName:work@div_radix8_ET.Q_33
|vpiRhs:
\_operation: , line:82
|vpiOpType:33
|vpiOperand:
\_part_select: , line:82, parent:Q_33
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (Q_33)
|vpiLeftRange:
\_operation: , line:82
|vpiOpType:11
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:82
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:82
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiRightRange:
\_constant: , line:82
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiOperand:
\_constant: , line:82
|vpiConstType:3
|vpiDecompile:3'b000
|vpiSize:3
|BIN:3'b000
|vpiCaseItem:
\_case_item: , line:84
|vpiExpr:
\_constant: , line:84
|vpiConstType:3
|vpiDecompile:7'b1111110
|vpiSize:7
|BIN:7'b1111110
|vpiStmt:
\_begin: , line:84
|vpiFullName:work@div_radix8_ET
|vpiStmt:
\_assignment: , line:85
|vpiOpType:82
|vpiLhs:
\_ref_obj: (PR), line:85
|vpiName:PR
|vpiFullName:work@div_radix8_ET.PR
|vpiRhs:
\_operation: , line:85
|vpiOpType:33
|vpiOperand:
\_part_select: , line:85, parent:new_PR_1
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (new_PR_1)
|vpiLeftRange:
\_operation: , line:85
|vpiOpType:11
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:85
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:85
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:85
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiOperand:
\_part_select: , line:85, parent:Q_33
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (Q_33)
|vpiLeftRange:
\_ref_obj: (div.DATA_WIDTH), line:85
|vpiName:div.DATA_WIDTH
|vpiRightRange:
\_operation: , line:85
|vpiOpType:11
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:85
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:85
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiStmt:
\_assignment: , line:86
|vpiOpType:82
|vpiLhs:
\_ref_obj: (Q_33), line:86
|vpiName:Q_33
|vpiFullName:work@div_radix8_ET.Q_33
|vpiRhs:
\_operation: , line:86
|vpiOpType:33
|vpiOperand:
\_part_select: , line:86, parent:Q_33
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (Q_33)
|vpiLeftRange:
\_operation: , line:86
|vpiOpType:11
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:86
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:86
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiRightRange:
\_constant: , line:86
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiOperand:
\_constant: , line:86
|vpiConstType:3
|vpiDecompile:3'b001
|vpiSize:3
|BIN:3'b001
|vpiCaseItem:
\_case_item: , line:88
|vpiExpr:
\_constant: , line:88
|vpiConstType:3
|vpiDecompile:7'b1111100
|vpiSize:7
|BIN:7'b1111100
|vpiStmt:
\_begin: , line:88
|vpiFullName:work@div_radix8_ET
|vpiStmt:
\_assignment: , line:89
|vpiOpType:82
|vpiLhs:
\_ref_obj: (PR), line:89
|vpiName:PR
|vpiFullName:work@div_radix8_ET.PR
|vpiRhs:
\_operation: , line:89
|vpiOpType:33
|vpiOperand:
\_part_select: , line:89, parent:new_PR_2
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (new_PR_2)
|vpiLeftRange:
\_operation: , line:89
|vpiOpType:11
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:89
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:89
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:89
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiOperand:
\_part_select: , line:89, parent:Q_33
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (Q_33)
|vpiLeftRange:
\_ref_obj: (div.DATA_WIDTH), line:89
|vpiName:div.DATA_WIDTH
|vpiRightRange:
\_operation: , line:89
|vpiOpType:11
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:89
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:89
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiStmt:
\_assignment: , line:90
|vpiOpType:82
|vpiLhs:
\_ref_obj: (Q_33), line:90
|vpiName:Q_33
|vpiFullName:work@div_radix8_ET.Q_33
|vpiRhs:
\_operation: , line:90
|vpiOpType:33
|vpiOperand:
\_part_select: , line:90, parent:Q_33
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (Q_33)
|vpiLeftRange:
\_operation: , line:90
|vpiOpType:11
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:90
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:90
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiRightRange:
\_constant: , line:90
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiOperand:
\_constant: , line:90
|vpiConstType:3
|vpiDecompile:3'b010
|vpiSize:3
|BIN:3'b010
|vpiCaseItem:
\_case_item: , line:92
|vpiExpr:
\_constant: , line:92
|vpiConstType:3
|vpiDecompile:7'b1111000
|vpiSize:7
|BIN:7'b1111000
|vpiStmt:
\_begin: , line:92
|vpiFullName:work@div_radix8_ET
|vpiStmt:
\_assignment: , line:93
|vpiOpType:82
|vpiLhs:
\_ref_obj: (PR), line:93
|vpiName:PR
|vpiFullName:work@div_radix8_ET.PR
|vpiRhs:
\_operation: , line:93
|vpiOpType:33
|vpiOperand:
\_part_select: , line:93, parent:new_PR_3
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (new_PR_3)
|vpiLeftRange:
\_operation: , line:93
|vpiOpType:11
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:93
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:93
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:93
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiOperand:
\_part_select: , line:93, parent:Q_33
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (Q_33)
|vpiLeftRange:
\_ref_obj: (div.DATA_WIDTH), line:93
|vpiName:div.DATA_WIDTH
|vpiRightRange:
\_operation: , line:93
|vpiOpType:11
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:93
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:93
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiStmt:
\_assignment: , line:94
|vpiOpType:82
|vpiLhs:
\_ref_obj: (Q_33), line:94
|vpiName:Q_33
|vpiFullName:work@div_radix8_ET.Q_33
|vpiRhs:
\_operation: , line:94
|vpiOpType:33
|vpiOperand:
\_part_select: , line:94, parent:Q_33
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (Q_33)
|vpiLeftRange:
\_operation: , line:94
|vpiOpType:11
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:94
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:94
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiRightRange:
\_constant: , line:94
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiOperand:
\_constant: , line:94
|vpiConstType:3
|vpiDecompile:3'b011
|vpiSize:3
|BIN:3'b011
|vpiCaseItem:
\_case_item: , line:96
|vpiExpr:
\_constant: , line:96
|vpiConstType:3
|vpiDecompile:7'b1110000
|vpiSize:7
|BIN:7'b1110000
|vpiStmt:
\_begin: , line:96
|vpiFullName:work@div_radix8_ET
|vpiStmt:
\_assignment: , line:97
|vpiOpType:82
|vpiLhs:
\_ref_obj: (PR), line:97
|vpiName:PR
|vpiFullName:work@div_radix8_ET.PR
|vpiRhs:
\_operation: , line:97
|vpiOpType:33
|vpiOperand:
\_part_select: , line:97, parent:new_PR_4
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (new_PR_4)
|vpiLeftRange:
\_operation: , line:97
|vpiOpType:11
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:97
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:97
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:97
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiOperand:
\_part_select: , line:97, parent:Q_33
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (Q_33)
|vpiLeftRange:
\_ref_obj: (div.DATA_WIDTH), line:97
|vpiName:div.DATA_WIDTH
|vpiRightRange:
\_operation: , line:97
|vpiOpType:11
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:97
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:97
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiStmt:
\_assignment: , line:98
|vpiOpType:82
|vpiLhs:
\_ref_obj: (Q_33), line:98
|vpiName:Q_33
|vpiFullName:work@div_radix8_ET.Q_33
|vpiRhs:
\_operation: , line:98
|vpiOpType:33
|vpiOperand:
\_part_select: , line:98, parent:Q_33
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (Q_33)
|vpiLeftRange:
\_operation: , line:98
|vpiOpType:11
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:98
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:98
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiRightRange:
\_constant: , line:98
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiOperand:
\_constant: , line:98
|vpiConstType:3
|vpiDecompile:3'b100
|vpiSize:3
|BIN:3'b100
|vpiCaseItem:
\_case_item: , line:100
|vpiExpr:
\_constant: , line:100
|vpiConstType:3
|vpiDecompile:7'b1100000
|vpiSize:7
|BIN:7'b1100000
|vpiStmt:
\_begin: , line:100
|vpiFullName:work@div_radix8_ET
|vpiStmt:
\_assignment: , line:101
|vpiOpType:82
|vpiLhs:
\_ref_obj: (PR), line:101
|vpiName:PR
|vpiFullName:work@div_radix8_ET.PR
|vpiRhs:
\_operation: , line:101
|vpiOpType:33
|vpiOperand:
\_part_select: , line:101, parent:new_PR_5
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (new_PR_5)
|vpiLeftRange:
\_operation: , line:101
|vpiOpType:11
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:101
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:101
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:101
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiOperand:
\_part_select: , line:101, parent:Q_33
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (Q_33)
|vpiLeftRange:
\_ref_obj: (div.DATA_WIDTH), line:101
|vpiName:div.DATA_WIDTH
|vpiRightRange:
\_operation: , line:101
|vpiOpType:11
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:101
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:101
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiStmt:
\_assignment: , line:102
|vpiOpType:82
|vpiLhs:
\_ref_obj: (Q_33), line:102
|vpiName:Q_33
|vpiFullName:work@div_radix8_ET.Q_33
|vpiRhs:
\_operation: , line:102
|vpiOpType:33
|vpiOperand:
\_part_select: , line:102, parent:Q_33
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (Q_33)
|vpiLeftRange:
\_operation: , line:102
|vpiOpType:11
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:102
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:102
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiRightRange:
\_constant: , line:102
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiOperand:
\_constant: , line:102
|vpiConstType:3
|vpiDecompile:3'b101
|vpiSize:3
|BIN:3'b101
|vpiCaseItem:
\_case_item: , line:104
|vpiExpr:
\_constant: , line:104
|vpiConstType:3
|vpiDecompile:7'b1000000
|vpiSize:7
|BIN:7'b1000000
|vpiStmt:
\_begin: , line:104
|vpiFullName:work@div_radix8_ET
|vpiStmt:
\_assignment: , line:105
|vpiOpType:82
|vpiLhs:
\_ref_obj: (PR), line:105
|vpiName:PR
|vpiFullName:work@div_radix8_ET.PR
|vpiRhs:
\_operation: , line:105
|vpiOpType:33
|vpiOperand:
\_part_select: , line:105, parent:new_PR_6
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (new_PR_6)
|vpiLeftRange:
\_operation: , line:105
|vpiOpType:11
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:105
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:105
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:105
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiOperand:
\_part_select: , line:105, parent:Q_33
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (Q_33)
|vpiLeftRange:
\_ref_obj: (div.DATA_WIDTH), line:105
|vpiName:div.DATA_WIDTH
|vpiRightRange:
\_operation: , line:105
|vpiOpType:11
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:105
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:105
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiStmt:
\_assignment: , line:106
|vpiOpType:82
|vpiLhs:
\_ref_obj: (Q_33), line:106
|vpiName:Q_33
|vpiFullName:work@div_radix8_ET.Q_33
|vpiRhs:
\_operation: , line:106
|vpiOpType:33
|vpiOperand:
\_part_select: , line:106, parent:Q_33
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (Q_33)
|vpiLeftRange:
\_operation: , line:106
|vpiOpType:11
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:106
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:106
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiRightRange:
\_constant: , line:106
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiOperand:
\_constant: , line:106
|vpiConstType:3
|vpiDecompile:3'b110
|vpiSize:3
|BIN:3'b110
|vpiCaseItem:
\_case_item: , line:108
|vpiStmt:
\_begin: , line:108
|vpiFullName:work@div_radix8_ET
|vpiStmt:
\_assignment: , line:109
|vpiOpType:82
|vpiLhs:
\_ref_obj: (PR), line:109
|vpiName:PR
|vpiFullName:work@div_radix8_ET.PR
|vpiRhs:
\_operation: , line:109
|vpiOpType:33
|vpiOperand:
\_part_select: , line:109, parent:new_PR_7
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (new_PR_7)
|vpiLeftRange:
\_operation: , line:109
|vpiOpType:11
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:109
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:109
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:109
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiOperand:
\_part_select: , line:109, parent:Q_33
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (Q_33)
|vpiLeftRange:
\_ref_obj: (div.DATA_WIDTH), line:109
|vpiName:div.DATA_WIDTH
|vpiRightRange:
\_operation: , line:109
|vpiOpType:11
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:109
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:109
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiStmt:
\_assignment: , line:110
|vpiOpType:82
|vpiLhs:
\_ref_obj: (Q_33), line:110
|vpiName:Q_33
|vpiFullName:work@div_radix8_ET.Q_33
|vpiRhs:
\_operation: , line:110
|vpiOpType:33
|vpiOperand:
\_part_select: , line:110, parent:Q_33
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (Q_33)
|vpiLeftRange:
\_operation: , line:110
|vpiOpType:11
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:110
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:110
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiRightRange:
\_constant: , line:110
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiOperand:
\_constant: , line:110
|vpiConstType:3
|vpiDecompile:3'b111
|vpiSize:3
|BIN:3'b111
|vpiProcess:
\_always: , line:119
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:119
|vpiCondition:
\_operation: , line:119
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:119
|vpiName:clk
|vpiFullName:work@div_radix8_ET.clk
|vpiStmt:
\_begin: , line:119
|vpiFullName:work@div_radix8_ET
|vpiStmt:
\_if_else: , line:120
|vpiCondition:
\_ref_obj: (div.start), line:120
|vpiName:div.start
|vpiFullName:work@div_radix8_ET.div.start
|vpiStmt:
\_assignment: , line:121
|vpiOpType:82
|vpiLhs:
\_ref_obj: (div.divisor_is_zero), line:121
|vpiName:div.divisor_is_zero
|vpiFullName:work@div_radix8_ET.div.divisor_is_zero
|vpiRhs:
\_operation: , line:121
|vpiOpType:4
|vpiOperand:
\_ref_obj: (div.divisor), line:121
|vpiName:div.divisor
|vpiFullName:work@div_radix8_ET.div.divisor
|vpiElseStmt:
\_if_stmt: , line:122
|vpiCondition:
\_operation: , line:122
|vpiOpType:4
|vpiOperand:
\_ref_obj: (terminate), line:122
|vpiName:terminate
|vpiFullName:work@div_radix8_ET.terminate
|vpiStmt:
\_assignment: , line:123
|vpiOpType:82
|vpiLhs:
\_ref_obj: (div.divisor_is_zero), line:123
|vpiName:div.divisor_is_zero
|vpiFullName:work@div_radix8_ET.div.divisor_is_zero
|vpiRhs:
\_operation: , line:123
|vpiOpType:28
|vpiOperand:
\_ref_obj: (div.divisor_is_zero), line:123
|vpiName:div.divisor_is_zero
|vpiFullName:work@div_radix8_ET.div.divisor_is_zero
|vpiOperand:
\_operation: , line:123
|vpiOpType:4
|vpiOperand:
\_operation: , line:123
|vpiOpType:7
|vpiOperand:
\_ref_obj: (new_PR_sign), line:123
|vpiName:new_PR_sign
|vpiFullName:work@div_radix8_ET.new_PR_sign
|vpiProcess:
\_always: , line:126
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:126
|vpiCondition:
\_operation: , line:126
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:126
|vpiName:clk
|vpiFullName:work@div_radix8_ET.clk
|vpiStmt:
\_begin: , line:126
|vpiFullName:work@div_radix8_ET
|vpiStmt:
\_if_else: , line:127
|vpiCondition:
\_ref_obj: (rst), line:127
|vpiName:rst
|vpiFullName:work@div_radix8_ET.rst
|vpiStmt:
\_assignment: , line:128
|vpiOpType:82
|vpiLhs:
\_ref_obj: (terminate), line:128
|vpiName:terminate
|vpiFullName:work@div_radix8_ET.terminate
|vpiRhs:
\_constant: , line:128
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiElseStmt:
\_begin: , line:129
|vpiFullName:work@div_radix8_ET
|vpiStmt:
\_if_stmt: , line:130
|vpiCondition:
\_ref_obj: (div.start), line:130
|vpiName:div.start
|vpiFullName:work@div_radix8_ET.div.start
|vpiStmt:
\_if_else: , line:131
|vpiCondition:
\_ref_obj: (terminate_early), line:131
|vpiName:terminate_early
|vpiFullName:work@div_radix8_ET.terminate_early
|vpiStmt:
\_begin: , line:131
|vpiFullName:work@div_radix8_ET
|vpiStmt:
\_assignment: , line:132
|vpiOpType:82
|vpiLhs:
\_ref_obj: (terminate), line:132
|vpiName:terminate
|vpiFullName:work@div_radix8_ET.terminate
|vpiRhs:
\_constant: , line:132
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiElseStmt:
\_begin: , line:133
|vpiFullName:work@div_radix8_ET
|vpiStmt:
\_assignment: , line:134
|vpiOpType:82
|vpiLhs:
\_ref_obj: (terminate), line:134
|vpiName:terminate
|vpiFullName:work@div_radix8_ET.terminate
|vpiRhs:
\_constant: , line:134
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiStmt:
\_if_stmt: , line:136
|vpiCondition:
\_bit_select: (shift_count), line:136
|vpiName:shift_count
|vpiFullName:work@div_radix8_ET.shift_count
|vpiIndex:
\_constant: , line:136
|vpiConstType:7
|vpiDecompile:10
|vpiSize:32
|INT:10
|vpiStmt:
\_assignment: , line:137
|vpiOpType:82
|vpiLhs:
\_ref_obj: (terminate), line:137
|vpiName:terminate
|vpiFullName:work@div_radix8_ET.terminate
|vpiRhs:
\_constant: , line:137
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiProcess:
\_always: , line:141
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:141
|vpiCondition:
\_operation: , line:141
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:141
|vpiName:clk
|vpiFullName:work@div_radix8_ET.clk
|vpiStmt:
\_begin: , line:141
|vpiFullName:work@div_radix8_ET
|vpiStmt:
\_if_else: , line:142
|vpiCondition:
\_ref_obj: (rst), line:142
|vpiName:rst
|vpiFullName:work@div_radix8_ET.rst
|vpiStmt:
\_assignment: , line:143
|vpiOpType:82
|vpiLhs:
\_ref_obj: (div.done), line:143
|vpiName:div.done
|vpiFullName:work@div_radix8_ET.div.done
|vpiRhs:
\_constant: , line:143
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiElseStmt:
\_begin: , line:144
|vpiFullName:work@div_radix8_ET
|vpiStmt:
\_if_else: , line:145
|vpiCondition:
\_ref_obj: (div.done), line:145
|vpiName:div.done
|vpiFullName:work@div_radix8_ET.div.done
|vpiStmt:
\_assignment: , line:146
|vpiOpType:82
|vpiLhs:
\_ref_obj: (div.done), line:146
|vpiName:div.done
|vpiFullName:work@div_radix8_ET.div.done
|vpiRhs:
\_constant: , line:146
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiElseStmt:
\_if_stmt: , line:147
|vpiCondition:
\_operation: , line:147
|vpiOpType:29
|vpiOperand:
\_operation: , line:147
|vpiOpType:28
|vpiOperand:
\_operation: , line:147
|vpiOpType:4
|vpiOperand:
\_ref_obj: (div.start), line:147
|vpiName:div.start
|vpiFullName:work@div_radix8_ET.div.start
|vpiOperand:
\_bit_select: (shift_count), line:147
|vpiName:shift_count
|vpiFullName:work@div_radix8_ET.shift_count
|vpiIndex:
\_constant: , line:147
|vpiConstType:7
|vpiDecompile:10
|vpiSize:32
|INT:10
|vpiOperand:
\_operation: , line:147
|vpiOpType:28
|vpiOperand:
\_ref_obj: (div.start), line:147
|vpiName:div.start
|vpiFullName:work@div_radix8_ET.div.start
|vpiOperand:
\_ref_obj: (terminate_early), line:147
|vpiName:terminate_early
|vpiFullName:work@div_radix8_ET.terminate_early
|vpiStmt:
\_assignment: , line:148
|vpiOpType:82
|vpiLhs:
\_ref_obj: (div.done), line:148
|vpiName:div.done
|vpiFullName:work@div_radix8_ET.div.done
|vpiRhs:
\_constant: , line:148
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiPort:
\_port: (clk), line:27
|vpiName:clk
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (clk), line:27
|vpiName:clk
|vpiFullName:work@div_radix8_ET.clk
|vpiNetType:36
|vpiPort:
\_port: (rst), line:28
|vpiName:rst
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (rst), line:28
|vpiName:rst
|vpiFullName:work@div_radix8_ET.rst
|vpiNetType:36
|vpiPort:
\_port: (div), line:29
|vpiName:div
|vpiDirection:5
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_modport: (divider)
|vpiContAssign:
\_cont_assign: , line:50
|vpiRhs:
\_operation: , line:50
|vpiOpType:11
|vpiOperand:
\_operation: , line:50
|vpiOpType:33
|vpiOperand:
\_constant: , line:50
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiOperand:
\_ref_obj: (PR), line:50
|vpiName:PR
|vpiOperand:
\_operation: , line:50
|vpiOpType:33
|vpiOperand:
\_constant: , line:50
|vpiConstType:3
|vpiDecompile:4'b0
|vpiSize:4
|BIN:4'b0
|vpiOperand:
\_ref_obj: (div.divisor), line:50
|vpiName:div.divisor
|vpiFullName:work@div_radix8_ET.div.divisor
|vpiLhs:
\_ref_obj: (new_PR_1), line:50
|vpiName:new_PR_1
|vpiFullName:work@div_radix8_ET.new_PR_1
|vpiContAssign:
\_cont_assign: , line:51
|vpiRhs:
\_operation: , line:51
|vpiOpType:11
|vpiOperand:
\_operation: , line:51
|vpiOpType:33
|vpiOperand:
\_constant: , line:51
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiOperand:
\_ref_obj: (PR), line:51
|vpiName:PR
|vpiOperand:
\_operation: , line:51
|vpiOpType:33
|vpiOperand:
\_constant: , line:51
|vpiConstType:3
|vpiDecompile:3'b0
|vpiSize:3
|BIN:3'b0
|vpiOperand:
\_ref_obj: (div.divisor), line:51
|vpiName:div.divisor
|vpiFullName:work@div_radix8_ET.div.divisor
|vpiOperand:
\_constant: , line:51
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiLhs:
\_ref_obj: (new_PR_2), line:51
|vpiName:new_PR_2
|vpiFullName:work@div_radix8_ET.new_PR_2
|vpiContAssign:
\_cont_assign: , line:52
|vpiRhs:
\_operation: , line:52
|vpiOpType:11
|vpiOperand:
\_operation: , line:52
|vpiOpType:11
|vpiOperand:
\_operation: , line:52
|vpiOpType:33
|vpiOperand:
\_constant: , line:52
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiOperand:
\_ref_obj: (PR), line:52
|vpiName:PR
|vpiOperand:
\_operation: , line:52
|vpiOpType:33
|vpiOperand:
\_constant: , line:52
|vpiConstType:3
|vpiDecompile:3'b0
|vpiSize:3
|BIN:3'b0
|vpiOperand:
\_ref_obj: (div.divisor), line:52
|vpiName:div.divisor
|vpiFullName:work@div_radix8_ET.div.divisor
|vpiOperand:
\_constant: , line:52
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiOperand:
\_operation: , line:52
|vpiOpType:33
|vpiOperand:
\_constant: , line:52
|vpiConstType:3
|vpiDecompile:4'b0
|vpiSize:4
|BIN:4'b0
|vpiOperand:
\_ref_obj: (div.divisor), line:52
|vpiName:div.divisor
|vpiFullName:work@div_radix8_ET.div.divisor
|vpiLhs:
\_ref_obj: (new_PR_3), line:52
|vpiName:new_PR_3
|vpiFullName:work@div_radix8_ET.new_PR_3
|vpiContAssign:
\_cont_assign: , line:53
|vpiRhs:
\_operation: , line:53
|vpiOpType:11
|vpiOperand:
\_operation: , line:53
|vpiOpType:33
|vpiOperand:
\_constant: , line:53
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiOperand:
\_ref_obj: (PR), line:53
|vpiName:PR
|vpiOperand:
\_operation: , line:53
|vpiOpType:33
|vpiOperand:
\_constant: , line:53
|vpiConstType:3
|vpiDecompile:2'b0
|vpiSize:2
|BIN:2'b0
|vpiOperand:
\_ref_obj: (div.divisor), line:53
|vpiName:div.divisor
|vpiFullName:work@div_radix8_ET.div.divisor
|vpiOperand:
\_constant: , line:53
|vpiConstType:3
|vpiDecompile:2'b0
|vpiSize:2
|BIN:2'b0
|vpiLhs:
\_ref_obj: (new_PR_4), line:53
|vpiName:new_PR_4
|vpiFullName:work@div_radix8_ET.new_PR_4
|vpiContAssign:
\_cont_assign: , line:54
|vpiRhs:
\_operation: , line:54
|vpiOpType:11
|vpiOperand:
\_operation: , line:54
|vpiOpType:11
|vpiOperand:
\_operation: , line:54
|vpiOpType:33
|vpiOperand:
\_constant: , line:54
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiOperand:
\_ref_obj: (PR), line:54
|vpiName:PR
|vpiOperand:
\_operation: , line:54
|vpiOpType:33
|vpiOperand:
\_constant: , line:54
|vpiConstType:3
|vpiDecompile:2'b0
|vpiSize:2
|BIN:2'b0
|vpiOperand:
\_ref_obj: (div.divisor), line:54
|vpiName:div.divisor
|vpiFullName:work@div_radix8_ET.div.divisor
|vpiOperand:
\_constant: , line:54
|vpiConstType:3
|vpiDecompile:2'b0
|vpiSize:2
|BIN:2'b0
|vpiOperand:
\_operation: , line:54
|vpiOpType:33
|vpiOperand:
\_constant: , line:54
|vpiConstType:3
|vpiDecompile:4'b0
|vpiSize:4
|BIN:4'b0
|vpiOperand:
\_ref_obj: (div.divisor), line:54
|vpiName:div.divisor
|vpiFullName:work@div_radix8_ET.div.divisor
|vpiLhs:
\_ref_obj: (new_PR_5), line:54
|vpiName:new_PR_5
|vpiFullName:work@div_radix8_ET.new_PR_5
|vpiContAssign:
\_cont_assign: , line:55
|vpiRhs:
\_operation: , line:55
|vpiOpType:11
|vpiOperand:
\_operation: , line:55
|vpiOpType:11
|vpiOperand:
\_operation: , line:55
|vpiOpType:33
|vpiOperand:
\_constant: , line:55
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiOperand:
\_ref_obj: (PR), line:55
|vpiName:PR
|vpiOperand:
\_operation: , line:55
|vpiOpType:33
|vpiOperand:
\_constant: , line:55
|vpiConstType:3
|vpiDecompile:2'b0
|vpiSize:2
|BIN:2'b0
|vpiOperand:
\_ref_obj: (div.divisor), line:55
|vpiName:div.divisor
|vpiFullName:work@div_radix8_ET.div.divisor
|vpiOperand:
\_constant: , line:55
|vpiConstType:3
|vpiDecompile:2'b0
|vpiSize:2
|BIN:2'b0
|vpiOperand:
\_operation: , line:55
|vpiOpType:33
|vpiOperand:
\_constant: , line:55
|vpiConstType:3
|vpiDecompile:3'b0
|vpiSize:3
|BIN:3'b0
|vpiOperand:
\_ref_obj: (div.divisor), line:55
|vpiName:div.divisor
|vpiFullName:work@div_radix8_ET.div.divisor
|vpiOperand:
\_constant: , line:55
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiLhs:
\_ref_obj: (new_PR_6), line:55
|vpiName:new_PR_6
|vpiFullName:work@div_radix8_ET.new_PR_6
|vpiContAssign:
\_cont_assign: , line:56
|vpiRhs:
\_operation: , line:56
|vpiOpType:11
|vpiOperand:
\_operation: , line:56
|vpiOpType:11
|vpiOperand:
\_operation: , line:56
|vpiOpType:11
|vpiOperand:
\_operation: , line:56
|vpiOpType:33
|vpiOperand:
\_constant: , line:56
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiOperand:
\_ref_obj: (PR), line:56
|vpiName:PR
|vpiOperand:
\_operation: , line:56
|vpiOpType:33
|vpiOperand:
\_constant: , line:56
|vpiConstType:3
|vpiDecompile:2'b0
|vpiSize:2
|BIN:2'b0
|vpiOperand:
\_ref_obj: (div.divisor), line:56
|vpiName:div.divisor
|vpiFullName:work@div_radix8_ET.div.divisor
|vpiOperand:
\_constant: , line:56
|vpiConstType:3
|vpiDecompile:2'b0
|vpiSize:2
|BIN:2'b0
|vpiOperand:
\_operation: , line:56
|vpiOpType:33
|vpiOperand:
\_constant: , line:56
|vpiConstType:3
|vpiDecompile:3'b0
|vpiSize:3
|BIN:3'b0
|vpiOperand:
\_ref_obj: (div.divisor), line:56
|vpiName:div.divisor
|vpiFullName:work@div_radix8_ET.div.divisor
|vpiOperand:
\_constant: , line:56
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiOperand:
\_operation: , line:56
|vpiOpType:33
|vpiOperand:
\_constant: , line:56
|vpiConstType:3
|vpiDecompile:4'b0
|vpiSize:4
|BIN:4'b0
|vpiOperand:
\_ref_obj: (div.divisor), line:56
|vpiName:div.divisor
|vpiFullName:work@div_radix8_ET.div.divisor
|vpiLhs:
\_ref_obj: (new_PR_7), line:56
|vpiName:new_PR_7
|vpiFullName:work@div_radix8_ET.new_PR_7
|vpiContAssign:
\_cont_assign: , line:57
|vpiRhs:
\_operation: , line:57
|vpiOpType:33
|vpiOperand:
\_bit_select: (new_PR_7), line:57
|vpiName:new_PR_7
|vpiIndex:
\_operation: , line:57
|vpiOpType:24
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:57
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:57
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiOperand:
\_bit_select: (new_PR_6), line:57
|vpiName:new_PR_6
|vpiIndex:
\_operation: , line:57
|vpiOpType:24
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:57
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:57
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiOperand:
\_bit_select: (new_PR_5), line:57
|vpiName:new_PR_5
|vpiIndex:
\_operation: , line:57
|vpiOpType:24
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:57
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:57
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiOperand:
\_bit_select: (new_PR_4), line:58
|vpiName:new_PR_4
|vpiIndex:
\_operation: , line:58
|vpiOpType:24
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:58
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:58
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiOperand:
\_bit_select: (new_PR_3), line:58
|vpiName:new_PR_3
|vpiIndex:
\_operation: , line:58
|vpiOpType:24
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:58
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:58
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiOperand:
\_bit_select: (new_PR_2), line:58
|vpiName:new_PR_2
|vpiIndex:
\_operation: , line:58
|vpiOpType:24
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:58
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:58
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiOperand:
\_bit_select: (new_PR_1), line:59
|vpiName:new_PR_1
|vpiIndex:
\_operation: , line:59
|vpiOpType:24
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:59
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:59
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiLhs:
\_ref_obj: (new_PR_sign), line:57
|vpiName:new_PR_sign
|vpiFullName:work@div_radix8_ET.new_PR_sign
|vpiContAssign:
\_cont_assign: , line:66
|vpiRhs:
\_operation: , line:66
|vpiOpType:18
|vpiOperand:
\_ref_obj: (div.divisor), line:66
|vpiName:div.divisor
|vpiFullName:work@div_radix8_ET.div.divisor
|vpiOperand:
\_ref_obj: (div.dividend), line:66
|vpiName:div.dividend
|vpiFullName:work@div_radix8_ET.div.dividend
|vpiLhs:
\_ref_obj: (terminate_early), line:66
|vpiName:terminate_early
|vpiFullName:work@div_radix8_ET.terminate_early
|vpiContAssign:
\_cont_assign: , line:116
|vpiRhs:
\_part_select: , line:116, parent:PR
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (PR)
|vpiLeftRange:
\_operation: , line:116
|vpiOpType:24
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:116
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:116
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiRightRange:
\_constant: , line:116
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiLhs:
\_ref_obj: (div.remainder), line:116
|vpiName:div.remainder
|vpiFullName:work@div_radix8_ET.div.remainder
|vpiContAssign:
\_cont_assign: , line:117
|vpiRhs:
\_part_select: , line:117, parent:Q_33
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (Q_33)
|vpiLeftRange:
\_operation: , line:117
|vpiOpType:11
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:117
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:117
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:117
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiLhs:
\_ref_obj: (div.quotient), line:117
|vpiName:div.quotient
|vpiFullName:work@div_radix8_ET.div.quotient
|vpiNet:
\_logic_net: (clk), line:27
|vpiNet:
\_logic_net: (rst), line:28
|vpiNet:
\_logic_net: (terminate), line:32
|vpiName:terminate
|vpiFullName:work@div_radix8_ET.terminate
|vpiNetType:36
|vpiNet:
\_logic_net: (terminate_early), line:33
|vpiName:terminate_early
|vpiFullName:work@div_radix8_ET.terminate_early
|vpiNetType:36
|vpiNet:
\_logic_net: (shift_count), line:34
|vpiName:shift_count
|vpiFullName:work@div_radix8_ET.shift_count
|vpiNetType:36
|vpiNet:
\_logic_net: (PR), line:36
|vpiName:PR
|vpiFullName:work@div_radix8_ET.PR
|vpiNetType:36
|vpiNet:
\_logic_net: (Q_33), line:37
|vpiName:Q_33
|vpiFullName:work@div_radix8_ET.Q_33
|vpiNetType:36
|vpiNet:
\_logic_net: (new_PR_sign), line:38
|vpiName:new_PR_sign
|vpiFullName:work@div_radix8_ET.new_PR_sign
|vpiNetType:36
|vpiNet:
\_logic_net: (new_PR_1), line:40
|vpiName:new_PR_1
|vpiFullName:work@div_radix8_ET.new_PR_1
|vpiNetType:36
|vpiNet:
\_logic_net: (new_PR_2), line:41
|vpiName:new_PR_2
|vpiFullName:work@div_radix8_ET.new_PR_2
|vpiNetType:36
|vpiNet:
\_logic_net: (new_PR_3), line:42
|vpiName:new_PR_3
|vpiFullName:work@div_radix8_ET.new_PR_3
|vpiNetType:36
|vpiNet:
\_logic_net: (new_PR_4), line:43
|vpiName:new_PR_4
|vpiFullName:work@div_radix8_ET.new_PR_4
|vpiNetType:36
|vpiNet:
\_logic_net: (new_PR_5), line:44
|vpiName:new_PR_5
|vpiFullName:work@div_radix8_ET.new_PR_5
|vpiNetType:36
|vpiNet:
\_logic_net: (new_PR_6), line:45
|vpiName:new_PR_6
|vpiFullName:work@div_radix8_ET.new_PR_6
|vpiNetType:36
|vpiNet:
\_logic_net: (new_PR_7), line:46
|vpiName:new_PR_7
|vpiFullName:work@div_radix8_ET.new_PR_7
|vpiNetType:36
|vpiNet:
\_logic_net: (div), line:29
|vpiName:div
|vpiFullName:work@div_radix8_ET.div
|uhdmallModules:
\_module: work@div_unit, file:third_party/cores/taiga/core/div_unit.sv, line:26, parent:work@div_unit_core_wrapper
|vpiDefName:work@div_unit
|vpiFullName:work@div_unit
|vpiProcess:
\_always: , line:116
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:116
|vpiCondition:
\_operation: , line:116
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:116
|vpiName:clk
|vpiFullName:work@div_unit.clk
|vpiStmt:
\_begin: , line:116
|vpiFullName:work@div_unit
|vpiStmt:
\_if_else: , line:117
|vpiCondition:
\_ref_obj: (rst), line:117
|vpiName:rst
|vpiFullName:work@div_unit.rst
|vpiStmt:
\_assignment: , line:118
|vpiOpType:82
|vpiLhs:
\_ref_obj: (in_progress), line:118
|vpiName:in_progress
|vpiFullName:work@div_unit.in_progress
|vpiRhs:
\_constant: , line:118
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiElseStmt:
\_if_else: , line:119
|vpiCondition:
\_ref_obj: (div_core.start), line:119
|vpiName:div_core.start
|vpiFullName:work@div_unit.div_core.start
|vpiStmt:
\_assignment: , line:120
|vpiOpType:82
|vpiLhs:
\_ref_obj: (in_progress), line:120
|vpiName:in_progress
|vpiFullName:work@div_unit.in_progress
|vpiRhs:
\_constant: , line:120
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiElseStmt:
\_if_stmt: , line:121
|vpiCondition:
\_ref_obj: (div_core.done), line:121
|vpiName:div_core.done
|vpiFullName:work@div_unit.div_core.done
|vpiStmt:
\_assignment: , line:122
|vpiOpType:82
|vpiLhs:
\_ref_obj: (in_progress), line:122
|vpiName:in_progress
|vpiFullName:work@div_unit.in_progress
|vpiRhs:
\_constant: , line:122
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiPort:
\_port: (clk), line:28
|vpiName:clk
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (clk), line:28
|vpiName:clk
|vpiFullName:work@div_unit.clk
|vpiNetType:36
|vpiPort:
\_port: (rst), line:29
|vpiName:rst
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (rst), line:29
|vpiName:rst
|vpiFullName:work@div_unit.rst
|vpiNetType:36
|vpiPort:
\_port: (gc_fetch_flush), line:31
|vpiName:gc_fetch_flush
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (gc_fetch_flush), line:31
|vpiName:gc_fetch_flush
|vpiFullName:work@div_unit.gc_fetch_flush
|vpiNetType:36
|vpiPort:
\_port: (div_inputs), line:33
|vpiName:div_inputs
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (div_inputs), line:33
|vpiName:div_inputs
|vpiFullName:work@div_unit.div_inputs
|vpiPort:
\_port: (issue), line:34
|vpiName:issue
|vpiDirection:5
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_modport: (unit)
|vpiPort:
\_port: (wb), line:35
|vpiName:wb
|vpiDirection:2
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (wb), line:35
|vpiName:wb
|vpiFullName:work@div_unit.wb
|vpiContAssign:
\_cont_assign: , line:77
|vpiRhs:
\_operation: , line:77
|vpiOpType:4
|vpiOperand:
\_ref_obj: (div_inputs.op), line:77
|vpiName:div_inputs.op
|vpiFullName:work@div_unit.div_inputs.op
|vpiLhs:
\_ref_obj: (signed_divop), line:77
|vpiName:signed_divop
|vpiFullName:work@div_unit.signed_divop
|vpiContAssign:
\_cont_assign: , line:79
|vpiRhs:
\_operation: , line:79
|vpiOpType:28
|vpiOperand:
\_ref_obj: (signed_divop), line:79
|vpiName:signed_divop
|vpiFullName:work@div_unit.signed_divop
|vpiOperand:
\_ref_obj: (div_inputs.rs1), line:79
|vpiName:div_inputs.rs1
|vpiFullName:work@div_unit.div_inputs.rs1
|vpiLhs:
\_ref_obj: (negate_dividend), line:79
|vpiName:negate_dividend
|vpiFullName:work@div_unit.negate_dividend
|vpiContAssign:
\_cont_assign: , line:80
|vpiRhs:
\_operation: , line:80
|vpiOpType:28
|vpiOperand:
\_ref_obj: (signed_divop), line:80
|vpiName:signed_divop
|vpiFullName:work@div_unit.signed_divop
|vpiOperand:
\_ref_obj: (div_inputs.rs2), line:80
|vpiName:div_inputs.rs2
|vpiFullName:work@div_unit.div_inputs.rs2
|vpiLhs:
\_ref_obj: (negate_divisor), line:80
|vpiName:negate_divisor
|vpiFullName:work@div_unit.negate_divisor
|vpiContAssign:
\_cont_assign: , line:82
|vpiRhs:
\_operation: , line:82
|vpiOpType:28
|vpiOperand:
\_ref_obj: (signed_divop), line:82
|vpiName:signed_divop
|vpiFullName:work@div_unit.signed_divop
|vpiOperand:
\_operation: , line:82
|vpiOpType:30
|vpiOperand:
\_ref_obj: (div_inputs.rs1), line:82
|vpiName:div_inputs.rs1
|vpiFullName:work@div_unit.div_inputs.rs1
|vpiOperand:
\_ref_obj: (div_inputs.rs2), line:82
|vpiName:div_inputs.rs2
|vpiFullName:work@div_unit.div_inputs.rs2
|vpiLhs:
\_ref_obj: (negate_quotient), line:82
|vpiName:negate_quotient
|vpiFullName:work@div_unit.negate_quotient
|vpiContAssign:
\_cont_assign: , line:83
|vpiRhs:
\_operation: , line:83
|vpiOpType:28
|vpiOperand:
\_ref_obj: (signed_divop), line:83
|vpiName:signed_divop
|vpiFullName:work@div_unit.signed_divop
|vpiOperand:
\_ref_obj: (div_inputs.rs1), line:83
|vpiName:div_inputs.rs1
|vpiFullName:work@div_unit.div_inputs.rs1
|vpiLhs:
\_ref_obj: (negate_remainder), line:83
|vpiName:negate_remainder
|vpiFullName:work@div_unit.negate_remainder
|vpiContAssign:
\_cont_assign: , line:87
|vpiRhs:
\_func_call: (negate_if), line:87
|vpiName:negate_if
|vpiFunction:
\_function: (negate_if), line:71
|vpiName:negate_if
|vpiFullName:work@div_unit.negate_if
|vpiReturn:
\_logic_var: , line:71
|vpiRange:
\_range: , line:71
|vpiLeftRange:
\_constant: , line:71
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:71
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (a)
|vpiName:a
|vpiDirection:1
|vpiExpr:
\_logic_var: , line:71, parent:a
|vpiFullName:a
|vpiRange:
\_range: , line:71
|vpiLeftRange:
\_constant: , line:71
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:71
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (b)
|vpiName:b
|vpiDirection:5
|vpiExpr:
\_logic_var: , line:71, parent:b
|vpiFullName:b
|vpiStmt:
\_return_stmt: , line:72, parent:negate_if
|vpiCondition:
\_operation: , line:72
|vpiOpType:24
|vpiOperand:
\_operation: , line:72
|vpiOpType:30
|vpiOperand:
\_operation: , line:72
|vpiOpType:34
|vpiOperand:
\_constant: , line:72
|vpiConstType:7
|vpiDecompile:32
|vpiSize:32
|INT:32
|vpiOperand:
\_operation:
|vpiOpType:33
|vpiOperand:
\_ref_obj: (b), line:72
|vpiName:b
|vpiOperand:
\_ref_obj: (a), line:72
|vpiName:a
|vpiFullName:work@div_unit.negate_if.a
|vpiOperand:
\_operation: , line:72
|vpiOpType:67
|vpiOperand:
\_ref_obj: (b), line:72
|vpiName:b
|vpiFullName:work@div_unit.negate_if.b
|vpiTypespec:
\_integer_typespec: , line:72
|INT:32
|vpiArgument:
\_ref_obj: (div_inputs.rs1), line:87
|vpiName:div_inputs.rs1
|vpiArgument:
\_ref_obj: (negate_dividend), line:87
|vpiName:negate_dividend
|vpiLhs:
\_ref_obj: (unsigned_dividend), line:87
|vpiName:unsigned_dividend
|vpiFullName:work@div_unit.unsigned_dividend
|vpiContAssign:
\_cont_assign: , line:88
|vpiRhs:
\_func_call: (negate_if), line:88
|vpiName:negate_if
|vpiFunction:
\_function: (negate_if), line:71
|vpiArgument:
\_ref_obj: (div_inputs.rs2), line:88
|vpiName:div_inputs.rs2
|vpiArgument:
\_ref_obj: (negate_divisor), line:88
|vpiName:negate_divisor
|vpiLhs:
\_ref_obj: (unsigned_divisor), line:88
|vpiName:unsigned_divisor
|vpiFullName:work@div_unit.unsigned_divisor
|vpiContAssign:
\_cont_assign: , line:90
|vpiRhs:
\_ref_obj: (unsigned_dividend), line:90
|vpiName:unsigned_dividend
|vpiFullName:work@div_unit.unsigned_dividend
|vpiLhs:
\_ref_obj: (fifo_inputs.unsigned_dividend), line:90
|vpiName:fifo_inputs.unsigned_dividend
|vpiFullName:work@div_unit.fifo_inputs.unsigned_dividend
|vpiContAssign:
\_cont_assign: , line:91
|vpiRhs:
\_ref_obj: (unsigned_divisor), line:91
|vpiName:unsigned_divisor
|vpiFullName:work@div_unit.unsigned_divisor
|vpiLhs:
\_ref_obj: (fifo_inputs.unsigned_divisor), line:91
|vpiName:fifo_inputs.unsigned_divisor
|vpiFullName:work@div_unit.fifo_inputs.unsigned_divisor
|vpiContAssign:
\_cont_assign: , line:92
|vpiRhs:
\_ref_obj: (div_inputs.op), line:92
|vpiName:div_inputs.op
|vpiFullName:work@div_unit.div_inputs.op
|vpiLhs:
\_ref_obj: (fifo_inputs.remainder_op), line:92
|vpiName:fifo_inputs.remainder_op
|vpiFullName:work@div_unit.fifo_inputs.remainder_op
|vpiContAssign:
\_cont_assign: , line:93
|vpiRhs:
\_ref_obj: (negate_quotient), line:93
|vpiName:negate_quotient
|vpiFullName:work@div_unit.negate_quotient
|vpiLhs:
\_ref_obj: (fifo_inputs.negate_quotient), line:93
|vpiName:fifo_inputs.negate_quotient
|vpiFullName:work@div_unit.fifo_inputs.negate_quotient
|vpiContAssign:
\_cont_assign: , line:94
|vpiRhs:
\_ref_obj: (negate_remainder), line:94
|vpiName:negate_remainder
|vpiFullName:work@div_unit.negate_remainder
|vpiLhs:
\_ref_obj: (fifo_inputs.negate_remainder), line:94
|vpiName:fifo_inputs.negate_remainder
|vpiFullName:work@div_unit.fifo_inputs.negate_remainder
|vpiContAssign:
\_cont_assign: , line:95
|vpiRhs:
\_ref_obj: (div_inputs.reuse_result), line:95
|vpiName:div_inputs.reuse_result
|vpiFullName:work@div_unit.div_inputs.reuse_result
|vpiLhs:
\_ref_obj: (fifo_inputs.reuse_result), line:95
|vpiName:fifo_inputs.reuse_result
|vpiFullName:work@div_unit.fifo_inputs.reuse_result
|vpiContAssign:
\_cont_assign: , line:96
|vpiRhs:
\_ref_obj: (issue.instruction_id), line:96
|vpiName:issue.instruction_id
|vpiFullName:work@div_unit.issue.instruction_id
|vpiLhs:
\_ref_obj: (fifo_inputs.instruction_id), line:96
|vpiName:fifo_inputs.instruction_id
|vpiFullName:work@div_unit.fifo_inputs.instruction_id
|vpiContAssign:
\_cont_assign: , line:103
|vpiRhs:
\_ref_obj: (fifo_inputs), line:103
|vpiName:fifo_inputs
|vpiFullName:work@div_unit.fifo_inputs
|vpiLhs:
\_ref_obj: (input_fifo.data_in), line:103
|vpiName:input_fifo.data_in
|vpiFullName:work@div_unit.input_fifo.data_in
|vpiContAssign:
\_cont_assign: , line:104
|vpiRhs:
\_ref_obj: (issue.new_request), line:104
|vpiName:issue.new_request
|vpiFullName:work@div_unit.issue.new_request
|vpiLhs:
\_ref_obj: (input_fifo.push), line:104
|vpiName:input_fifo.push
|vpiFullName:work@div_unit.input_fifo.push
|vpiContAssign:
\_cont_assign: , line:105
|vpiRhs:
\_ref_obj: (gc_fetch_flush), line:105
|vpiName:gc_fetch_flush
|vpiFullName:work@div_unit.gc_fetch_flush
|vpiLhs:
\_ref_obj: (input_fifo.supress_push), line:105
|vpiName:input_fifo.supress_push
|vpiFullName:work@div_unit.input_fifo.supress_push
|vpiContAssign:
\_cont_assign: , line:106
|vpiRhs:
\_constant: , line:106
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiLhs:
\_ref_obj: (issue.ready), line:106
|vpiName:issue.ready
|vpiFullName:work@div_unit.issue.ready
|vpiContAssign:
\_cont_assign: , line:107
|vpiRhs:
\_ref_obj: (div_done), line:107
|vpiName:div_done
|vpiFullName:work@div_unit.div_done
|vpiLhs:
\_ref_obj: (input_fifo.pop), line:107
|vpiName:input_fifo.pop
|vpiFullName:work@div_unit.input_fifo.pop
|vpiContAssign:
\_cont_assign: , line:108
|vpiRhs:
\_ref_obj: (input_fifo.data_out), line:108
|vpiName:input_fifo.data_out
|vpiFullName:work@div_unit.input_fifo.data_out
|vpiLhs:
\_ref_obj: (div_op), line:108
|vpiName:div_op
|vpiFullName:work@div_unit.div_op
|vpiContAssign:
\_cont_assign: , line:112
|vpiRhs:
\_operation: , line:112
|vpiOpType:28
|vpiOperand:
\_operation: , line:112
|vpiOpType:28
|vpiOperand:
\_ref_obj: (input_fifo.valid), line:112
|vpiName:input_fifo.valid
|vpiFullName:work@div_unit.input_fifo.valid
|vpiOperand:
\_operation: , line:112
|vpiOpType:4
|vpiOperand:
\_ref_obj: (in_progress), line:112
|vpiName:in_progress
|vpiFullName:work@div_unit.in_progress
|vpiOperand:
\_operation: , line:112
|vpiOpType:4
|vpiOperand:
\_ref_obj: (div_op.reuse_result), line:112
|vpiName:div_op.reuse_result
|vpiFullName:work@div_unit.div_op.reuse_result
|vpiLhs:
\_ref_obj: (div_core.start), line:112
|vpiName:div_core.start
|vpiFullName:work@div_unit.div_core.start
|vpiContAssign:
\_cont_assign: , line:113
|vpiRhs:
\_operation: , line:113
|vpiOpType:29
|vpiOperand:
\_ref_obj: (div_core.done), line:113
|vpiName:div_core.done
|vpiFullName:work@div_unit.div_core.done
|vpiOperand:
\_operation: , line:113
|vpiOpType:28
|vpiOperand:
\_ref_obj: (input_fifo.valid), line:113
|vpiName:input_fifo.valid
|vpiFullName:work@div_unit.input_fifo.valid
|vpiOperand:
\_ref_obj: (div_op.reuse_result), line:113
|vpiName:div_op.reuse_result
|vpiFullName:work@div_unit.div_op.reuse_result
|vpiLhs:
\_ref_obj: (div_done), line:113
|vpiName:div_done
|vpiFullName:work@div_unit.div_done
|vpiContAssign:
\_cont_assign: , line:127
|vpiRhs:
\_ref_obj: (div_op.unsigned_dividend), line:127
|vpiName:div_op.unsigned_dividend
|vpiFullName:work@div_unit.div_op.unsigned_dividend
|vpiLhs:
\_ref_obj: (div_core.dividend), line:127
|vpiName:div_core.dividend
|vpiFullName:work@div_unit.div_core.dividend
|vpiContAssign:
\_cont_assign: , line:128
|vpiRhs:
\_ref_obj: (div_op.unsigned_divisor), line:128
|vpiName:div_op.unsigned_divisor
|vpiFullName:work@div_unit.div_op.unsigned_divisor
|vpiLhs:
\_ref_obj: (div_core.divisor), line:128
|vpiName:div_core.divisor
|vpiFullName:work@div_unit.div_core.divisor
|vpiContAssign:
\_cont_assign: , line:133
|vpiRhs:
\_operation: , line:133
|vpiOpType:32
|vpiOperand:
\_ref_obj: (div_op.remainder_op), line:133
|vpiName:div_op.remainder_op
|vpiFullName:work@div_unit.div_op.remainder_op
|vpiOperand:
\_ref_obj: (div_op.negate_remainder), line:133
|vpiName:div_op.negate_remainder
|vpiFullName:work@div_unit.div_op.negate_remainder
|vpiOperand:
\_operation: , line:133
|vpiOpType:28
|vpiOperand:
\_operation: , line:133
|vpiOpType:4
|vpiOperand:
\_ref_obj: (div_core.divisor_is_zero), line:133
|vpiName:div_core.divisor_is_zero
|vpiFullName:work@div_unit.div_core.divisor_is_zero
|vpiOperand:
\_ref_obj: (div_op.negate_quotient), line:133
|vpiName:div_op.negate_quotient
|vpiFullName:work@div_unit.div_op.negate_quotient
|vpiLhs:
\_ref_obj: (negate_result), line:133
|vpiName:negate_result
|vpiFullName:work@div_unit.negate_result
|vpiContAssign:
\_cont_assign: , line:134
|vpiRhs:
\_func_call: (negate_if), line:134
|vpiName:negate_if
|vpiFunction:
\_function: (negate_if), line:71
|vpiArgument:
\_operation: , line:134
|vpiOpType:32
|vpiOperand:
\_ref_obj: (div_op.remainder_op), line:134
|vpiName:div_op.remainder_op
|vpiOperand:
\_ref_obj: (div_core.remainder), line:134
|vpiName:div_core.remainder
|vpiOperand:
\_ref_obj: (div_core.quotient), line:134
|vpiName:div_core.quotient
|vpiArgument:
\_ref_obj: (negate_result), line:134
|vpiName:negate_result
|vpiLhs:
\_ref_obj: (wb.rd), line:134
|vpiName:wb.rd
|vpiFullName:work@div_unit.wb.rd
|vpiContAssign:
\_cont_assign: , line:135
|vpiRhs:
\_ref_obj: (div_done), line:135
|vpiName:div_done
|vpiFullName:work@div_unit.div_done
|vpiLhs:
\_ref_obj: (wb.done), line:135
|vpiName:wb.done
|vpiFullName:work@div_unit.wb.done
|vpiContAssign:
\_cont_assign: , line:136
|vpiRhs:
\_ref_obj: (div_op.instruction_id), line:136
|vpiName:div_op.instruction_id
|vpiFullName:work@div_unit.div_op.instruction_id
|vpiLhs:
\_ref_obj: (wb.id), line:136
|vpiName:wb.id
|vpiFullName:work@div_unit.wb.id
|vpiTaskFunc:
\_function: (negate_if), line:71
|vpiNet:
\_logic_net: (clk), line:28
|vpiNet:
\_logic_net: (rst), line:29
|vpiNet:
\_logic_net: (gc_fetch_flush), line:31
|vpiNet:
\_logic_net: (div_inputs), line:33
|vpiNet:
\_logic_net: (wb), line:35
|vpiNet:
\_logic_net: (signed_divop), line:38
|vpiName:signed_divop
|vpiFullName:work@div_unit.signed_divop
|vpiNetType:36
|vpiNet:
\_logic_net: (negate_quotient), line:39
|vpiName:negate_quotient
|vpiFullName:work@div_unit.negate_quotient
|vpiNetType:36
|vpiNet:
\_logic_net: (negate_remainder), line:40
|vpiName:negate_remainder
|vpiFullName:work@div_unit.negate_remainder
|vpiNetType:36
|vpiNet:
\_logic_net: (negate_dividend), line:41
|vpiName:negate_dividend
|vpiFullName:work@div_unit.negate_dividend
|vpiNetType:36
|vpiNet:
\_logic_net: (negate_divisor), line:42
|vpiName:negate_divisor
|vpiFullName:work@div_unit.negate_divisor
|vpiNetType:36
|vpiNet:
\_logic_net: (unsigned_dividend), line:44
|vpiName:unsigned_dividend
|vpiFullName:work@div_unit.unsigned_dividend
|vpiNetType:36
|vpiNet:
\_logic_net: (unsigned_divisor), line:45
|vpiName:unsigned_divisor
|vpiFullName:work@div_unit.unsigned_divisor
|vpiNetType:36
|vpiNet:
\_logic_net: (remainder_op), line:46
|vpiName:remainder_op
|vpiFullName:work@div_unit.remainder_op
|vpiNetType:36
|vpiNet:
\_logic_net: (fifo_inputs), line:58
|vpiName:fifo_inputs
|vpiFullName:work@div_unit.fifo_inputs
|vpiNet:
\_logic_net: (div_op), line:59
|vpiName:div_op
|vpiFullName:work@div_unit.div_op
|vpiNet:
\_logic_net: (in_progress), line:63
|vpiName:in_progress
|vpiFullName:work@div_unit.in_progress
|vpiNetType:36
|vpiNet:
\_logic_net: (div_done), line:64
|vpiName:div_done
|vpiFullName:work@div_unit.div_done
|vpiNetType:36
|vpiNet:
\_logic_net: (negate_result), line:65
|vpiName:negate_result
|vpiFullName:work@div_unit.negate_result
|vpiNetType:36
|vpiNet:
\_logic_net: (issue), line:34
|vpiName:issue
|vpiFullName:work@div_unit.issue
|vpiTypedef:
\_struct_typespec: (alu_inputs_t), line:301
|vpiTypedef:
\_enum_typespec: (alu_logic_op_t), line:84
|vpiTypedef:
\_enum_typespec: (alu_op_t), line:91
|vpiTypedef:
\_enum_typespec: (alu_rs1_op_t), line:97
|vpiTypedef:
\_enum_typespec: (alu_rs2_op_t), line:104
|vpiTypedef:
\_struct_typespec: (amo_alu_inputs_t), line:356
|vpiTypedef:
\_struct_typespec: (amo_details_t), line:362
|vpiTypedef:
\_enum_typespec: (amo_t), line:354
|vpiTypedef:
\_struct_typespec: (branch_inputs_t), line:313
|vpiTypedef:
\_logic_typespec: (branch_predictor_metadata_t), line:32
|vpiTypedef:
\_struct_typespec: (branch_results_t), line:330
|vpiTypedef:
\_enum_typespec: (bus_type_t), line:86
|vpiTypedef:
\_struct_typespec: (csr_inputs_t), line:396
|vpiTypedef:
\_enum_typespec: (csr_op_t), line:218
|vpiTypedef:
\_enum_typespec: (csr_t), line:201
|vpiTypedef:
\_struct_typespec: (data_access_shared_inputs_t), line:427
|vpiTypedef:
\_struct_typespec: (div_fifo_inputs_t), line:48
|vpiPacked:1
|vpiName:div_fifo_inputs_t
|vpiTypespecMember:
\_typespec_member: (unsigned_dividend), line:49
|vpiName:unsigned_dividend
|vpiTypespec:
\_logic_typespec: , line:49
|vpiRange:
\_range: , line:49, parent:div_fifo_inputs_t
|vpiLeftRange:
\_operation: , line:49
|vpiOpType:11
|vpiOperand:
\_ref_obj: (XLEN), line:49, parent:div_fifo_inputs_t
|vpiName:XLEN
|vpiFullName:div_fifo_inputs_t.XLEN
|vpiOperand:
\_constant: , line:49
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:49
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiTypespecMember:
\_typespec_member: (unsigned_divisor), line:50
|vpiName:unsigned_divisor
|vpiTypespec:
\_logic_typespec: , line:50
|vpiRange:
\_range: , line:50, parent:div_fifo_inputs_t
|vpiLeftRange:
\_operation: , line:50
|vpiOpType:11
|vpiOperand:
\_ref_obj: (XLEN), line:50, parent:div_fifo_inputs_t
|vpiName:XLEN
|vpiFullName:div_fifo_inputs_t.XLEN
|vpiOperand:
\_constant: , line:50
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:50
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiTypespecMember:
\_typespec_member: (remainder_op), line:51
|vpiName:remainder_op
|vpiTypespec:
\_logic_typespec: , line:51
|vpiTypespecMember:
\_typespec_member: (negate_quotient), line:52
|vpiName:negate_quotient
|vpiTypespec:
\_logic_typespec: , line:52
|vpiTypespecMember:
\_typespec_member: (negate_remainder), line:53
|vpiName:negate_remainder
|vpiTypespec:
\_logic_typespec: , line:53
|vpiTypespecMember:
\_typespec_member: (reuse_result), line:54
|vpiName:reuse_result
|vpiTypespec:
\_logic_typespec: , line:54
|vpiTypespecMember:
\_typespec_member: (instruction_id), line:55
|vpiName:instruction_id
|vpiTypespec:
\_logic_typespec: (instruction_id_t), line:30
|vpiTypedef:
\_struct_typespec: (div_inputs_t), line:389
|vpiTypedef:
\_enum_typespec: (div_type), line:66
|vpiTypedef:
\_enum_typespec: (exception_code_t), line:245
|vpiTypedef:
\_struct_typespec: (exception_packet_t), line:263
|vpiTypedef:
\_struct_typespec: (fetch_buffer_packet_t), line:276
|vpiTypedef:
\_enum_typespec: (fifo_type_t), line:440
|vpiTypedef:
\_enum_typespec: (fn3_arith_t), line:76
|vpiTypedef:
\_enum_typespec: (fn3_branch_t), line:126
|vpiTypedef:
\_enum_typespec: (fn3_csr_t), line:212
|vpiTypedef:
\_enum_typespec: (fn3_ls_t), line:115
|vpiTypedef:
\_enum_typespec: (fn3_mul_div_t), line:138
|vpiTypedef:
\_struct_typespec: (gc_inputs_t), line:404
|vpiTypedef:
\_struct_typespec: (inflight_instruction_packet), line:271
|vpiTypedef:
\_logic_typespec: (instruction_id_t), line:30
|vpiTypedef:
\_enum_typespec: (interrupt_code_t), line:261
|vpiTypedef:
\_struct_typespec: (load_store_inputs_t), line:369
|vpiTypedef:
\_struct_typespec: (mul_inputs_t), line:383
|vpiTypedef:
\_enum_typespec: (opcodes_t), line:48
|vpiTypedef:
\_enum_typespec: (opcodes_trimmed_t), line:65
|vpiTypedef:
\_struct_typespec: (simulation_named_regfile), line:476
|vpiTypedef:
\_struct_typespec: (taiga_trace_events_t), line:442
|vpiTypedef:
\_struct_typespec: (to_l1_arbiter_packet), line:418
|vpiTypedef:
\_struct_typespec: (trace_outputs_t), line:469
|vpiTypedef:
\_logic_typespec: (unit_id_t), line:31
|vpiTypedef:
\_struct_typespec: (unit_writeback_t), line:295
|vpiTypedef:
\_enum_typespec: (vm_t), line:223
|uhdmallModules:
\_module: work@div_unit_core_wrapper, file:third_party/cores/taiga/core/div_unit_core_wrapper.sv, line:4, parent:work@div_unit_core_wrapper
|vpiDefName:work@div_unit_core_wrapper
|vpiFullName:work@div_unit_core_wrapper
|vpiProcess:
\_always: , line:35
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:35
|vpiCondition:
\_operation: , line:35
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:35
|vpiName:clk
|vpiFullName:work@div_unit_core_wrapper.clk
|vpiStmt:
\_begin: , line:35
|vpiFullName:work@div_unit_core_wrapper
|vpiStmt:
\_assignment: , line:36
|vpiOpType:82
|vpiLhs:
\_ref_obj: (start_r), line:36
|vpiName:start_r
|vpiFullName:work@div_unit_core_wrapper.start_r
|vpiRhs:
\_ref_obj: (start), line:36
|vpiName:start
|vpiFullName:work@div_unit_core_wrapper.start
|vpiStmt:
\_assignment: , line:37
|vpiOpType:82
|vpiLhs:
\_ref_obj: (ack_r), line:37
|vpiName:ack_r
|vpiFullName:work@div_unit_core_wrapper.ack_r
|vpiRhs:
\_ref_obj: (ack), line:37
|vpiName:ack
|vpiFullName:work@div_unit_core_wrapper.ack
|vpiStmt:
\_assignment: , line:38
|vpiOpType:82
|vpiLhs:
\_ref_obj: (A_r), line:38
|vpiName:A_r
|vpiFullName:work@div_unit_core_wrapper.A_r
|vpiRhs:
\_ref_obj: (A), line:38
|vpiName:A
|vpiFullName:work@div_unit_core_wrapper.A
|vpiStmt:
\_assignment: , line:39
|vpiOpType:82
|vpiLhs:
\_ref_obj: (B_r), line:39
|vpiName:B_r
|vpiFullName:work@div_unit_core_wrapper.B_r
|vpiRhs:
\_ref_obj: (B), line:39
|vpiName:B
|vpiFullName:work@div_unit_core_wrapper.B
|vpiProcess:
\_always: , line:58
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:58
|vpiCondition:
\_operation: , line:58
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:58
|vpiName:clk
|vpiFullName:work@div_unit_core_wrapper.clk
|vpiStmt:
\_begin: , line:58
|vpiFullName:work@div_unit_core_wrapper
|vpiStmt:
\_assignment: , line:59
|vpiOpType:82
|vpiLhs:
\_ref_obj: (Q_r), line:59
|vpiName:Q_r
|vpiFullName:work@div_unit_core_wrapper.Q_r
|vpiRhs:
\_ref_obj: (Q_o), line:59
|vpiName:Q_o
|vpiFullName:work@div_unit_core_wrapper.Q_o
|vpiStmt:
\_assignment: , line:60
|vpiOpType:82
|vpiLhs:
\_ref_obj: (R_r), line:60
|vpiName:R_r
|vpiFullName:work@div_unit_core_wrapper.R_r
|vpiRhs:
\_ref_obj: (R_o), line:60
|vpiName:R_o
|vpiFullName:work@div_unit_core_wrapper.R_o
|vpiStmt:
\_assignment: , line:61
|vpiOpType:82
|vpiLhs:
\_ref_obj: (complete_r), line:61
|vpiName:complete_r
|vpiFullName:work@div_unit_core_wrapper.complete_r
|vpiRhs:
\_ref_obj: (complete_o), line:61
|vpiName:complete_o
|vpiFullName:work@div_unit_core_wrapper.complete_o
|vpiStmt:
\_assignment: , line:62
|vpiOpType:82
|vpiLhs:
\_ref_obj: (B_is_zero_r), line:62
|vpiName:B_is_zero_r
|vpiFullName:work@div_unit_core_wrapper.B_is_zero_r
|vpiRhs:
\_ref_obj: (B_is_zero_o), line:62
|vpiName:B_is_zero_o
|vpiFullName:work@div_unit_core_wrapper.B_is_zero_o
|vpiPort:
\_port: (clk), line:8
|vpiName:clk
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (clk), line:8
|vpiName:clk
|vpiFullName:work@div_unit_core_wrapper.clk
|vpiNetType:36
|vpiPort:
\_port: (rst), line:9
|vpiName:rst
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (rst), line:9
|vpiName:rst
|vpiFullName:work@div_unit_core_wrapper.rst
|vpiNetType:36
|vpiPort:
\_port: (start), line:10
|vpiName:start
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (start), line:10
|vpiName:start
|vpiFullName:work@div_unit_core_wrapper.start
|vpiNetType:36
|vpiPort:
\_port: (ack), line:11
|vpiName:ack
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (ack), line:11
|vpiName:ack
|vpiFullName:work@div_unit_core_wrapper.ack
|vpiNetType:36
|vpiPort:
\_port: (A), line:12
|vpiName:A
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (A), line:12
|vpiName:A
|vpiFullName:work@div_unit_core_wrapper.A
|vpiNetType:36
|vpiPort:
\_port: (B), line:13
|vpiName:B
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (B), line:13
|vpiName:B
|vpiFullName:work@div_unit_core_wrapper.B
|vpiNetType:36
|vpiPort:
\_port: (Q), line:14
|vpiName:Q
|vpiDirection:2
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (Q), line:14
|vpiName:Q
|vpiFullName:work@div_unit_core_wrapper.Q
|vpiNetType:36
|vpiPort:
\_port: (R), line:15
|vpiName:R
|vpiDirection:2
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (R), line:15
|vpiName:R
|vpiFullName:work@div_unit_core_wrapper.R
|vpiNetType:36
|vpiPort:
\_port: (complete), line:16
|vpiName:complete
|vpiDirection:2
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (complete), line:16
|vpiName:complete
|vpiFullName:work@div_unit_core_wrapper.complete
|vpiNetType:36
|vpiPort:
\_port: (B_is_zero), line:17
|vpiName:B_is_zero
|vpiDirection:2
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (B_is_zero), line:17
|vpiName:B_is_zero
|vpiFullName:work@div_unit_core_wrapper.B_is_zero
|vpiNetType:36
|vpiContAssign:
\_cont_assign: , line:65
|vpiRhs:
\_ref_obj: (Q_r), line:65
|vpiName:Q_r
|vpiFullName:work@div_unit_core_wrapper.Q_r
|vpiLhs:
\_ref_obj: (Q), line:65
|vpiName:Q
|vpiFullName:work@div_unit_core_wrapper.Q
|vpiContAssign:
\_cont_assign: , line:66
|vpiRhs:
\_ref_obj: (R_r), line:66
|vpiName:R_r
|vpiFullName:work@div_unit_core_wrapper.R_r
|vpiLhs:
\_ref_obj: (R), line:66
|vpiName:R
|vpiFullName:work@div_unit_core_wrapper.R
|vpiContAssign:
\_cont_assign: , line:67
|vpiRhs:
\_ref_obj: (complete_r), line:67
|vpiName:complete_r
|vpiFullName:work@div_unit_core_wrapper.complete_r
|vpiLhs:
\_ref_obj: (complete), line:67
|vpiName:complete
|vpiFullName:work@div_unit_core_wrapper.complete
|vpiContAssign:
\_cont_assign: , line:68
|vpiRhs:
\_ref_obj: (B_is_zero_r), line:68
|vpiName:B_is_zero_r
|vpiFullName:work@div_unit_core_wrapper.B_is_zero_r
|vpiLhs:
\_ref_obj: (B_is_zero), line:68
|vpiName:B_is_zero
|vpiFullName:work@div_unit_core_wrapper.B_is_zero
|vpiNet:
\_logic_net: (clk), line:8
|vpiNet:
\_logic_net: (rst), line:9
|vpiNet:
\_logic_net: (start), line:10
|vpiNet:
\_logic_net: (ack), line:11
|vpiNet:
\_logic_net: (A), line:12
|vpiNet:
\_logic_net: (B), line:13
|vpiNet:
\_logic_net: (Q), line:14
|vpiNet:
\_logic_net: (R), line:15
|vpiNet:
\_logic_net: (complete), line:16
|vpiNet:
\_logic_net: (B_is_zero), line:17
|vpiNet:
\_logic_net: (start_r), line:21
|vpiName:start_r
|vpiFullName:work@div_unit_core_wrapper.start_r
|vpiNetType:36
|vpiNet:
\_logic_net: (ack_r), line:22
|vpiName:ack_r
|vpiFullName:work@div_unit_core_wrapper.ack_r
|vpiNetType:36
|vpiNet:
\_logic_net: (A_r), line:23
|vpiName:A_r
|vpiFullName:work@div_unit_core_wrapper.A_r
|vpiNetType:36
|vpiNet:
\_logic_net: (B_r), line:24
|vpiName:B_r
|vpiFullName:work@div_unit_core_wrapper.B_r
|vpiNetType:36
|vpiNet:
\_logic_net: (Q_r), line:25
|vpiName:Q_r
|vpiFullName:work@div_unit_core_wrapper.Q_r
|vpiNetType:36
|vpiNet:
\_logic_net: (R_r), line:26
|vpiName:R_r
|vpiFullName:work@div_unit_core_wrapper.R_r
|vpiNetType:36
|vpiNet:
\_logic_net: (complete_r), line:27
|vpiName:complete_r
|vpiFullName:work@div_unit_core_wrapper.complete_r
|vpiNetType:36
|vpiNet:
\_logic_net: (B_is_zero_r), line:28
|vpiName:B_is_zero_r
|vpiFullName:work@div_unit_core_wrapper.B_is_zero_r
|vpiNetType:36
|vpiNet:
\_logic_net: (Q_o), line:29
|vpiName:Q_o
|vpiFullName:work@div_unit_core_wrapper.Q_o
|vpiNetType:36
|vpiNet:
\_logic_net: (R_o), line:30
|vpiName:R_o
|vpiFullName:work@div_unit_core_wrapper.R_o
|vpiNetType:36
|vpiNet:
\_logic_net: (complete_o), line:31
|vpiName:complete_o
|vpiFullName:work@div_unit_core_wrapper.complete_o
|vpiNetType:36
|vpiNet:
\_logic_net: (B_is_zero_o), line:32
|vpiName:B_is_zero_o
|vpiFullName:work@div_unit_core_wrapper.B_is_zero_o
|vpiNetType:36
|vpiTypedef:
\_struct_typespec: (alu_inputs_t), line:301
|vpiTypedef:
\_enum_typespec: (alu_logic_op_t), line:84
|vpiTypedef:
\_enum_typespec: (alu_op_t), line:91
|vpiTypedef:
\_enum_typespec: (alu_rs1_op_t), line:97
|vpiTypedef:
\_enum_typespec: (alu_rs2_op_t), line:104
|vpiTypedef:
\_struct_typespec: (amo_alu_inputs_t), line:356
|vpiTypedef:
\_struct_typespec: (amo_details_t), line:362
|vpiTypedef:
\_enum_typespec: (amo_t), line:354
|vpiTypedef:
\_struct_typespec: (branch_inputs_t), line:313
|vpiTypedef:
\_logic_typespec: (branch_predictor_metadata_t), line:32
|vpiTypedef:
\_struct_typespec: (branch_results_t), line:330
|vpiTypedef:
\_enum_typespec: (bus_type_t), line:86
|vpiTypedef:
\_struct_typespec: (csr_inputs_t), line:396
|vpiTypedef:
\_enum_typespec: (csr_op_t), line:218
|vpiTypedef:
\_enum_typespec: (csr_t), line:201
|vpiTypedef:
\_struct_typespec: (data_access_shared_inputs_t), line:427
|vpiTypedef:
\_struct_typespec: (div_inputs_t), line:389
|vpiTypedef:
\_enum_typespec: (div_type), line:66
|vpiTypedef:
\_enum_typespec: (exception_code_t), line:245
|vpiTypedef:
\_struct_typespec: (exception_packet_t), line:263
|vpiTypedef:
\_struct_typespec: (fetch_buffer_packet_t), line:276
|vpiTypedef:
\_enum_typespec: (fifo_type_t), line:440
|vpiTypedef:
\_enum_typespec: (fn3_arith_t), line:76
|vpiTypedef:
\_enum_typespec: (fn3_branch_t), line:126
|vpiTypedef:
\_enum_typespec: (fn3_csr_t), line:212
|vpiTypedef:
\_enum_typespec: (fn3_ls_t), line:115
|vpiTypedef:
\_enum_typespec: (fn3_mul_div_t), line:138
|vpiTypedef:
\_struct_typespec: (gc_inputs_t), line:404
|vpiTypedef:
\_struct_typespec: (inflight_instruction_packet), line:271
|vpiTypedef:
\_logic_typespec: (instruction_id_t), line:30
|vpiTypedef:
\_enum_typespec: (interrupt_code_t), line:261
|vpiTypedef:
\_struct_typespec: (load_store_inputs_t), line:369
|vpiTypedef:
\_struct_typespec: (mul_inputs_t), line:383
|vpiTypedef:
\_enum_typespec: (opcodes_t), line:48
|vpiTypedef:
\_enum_typespec: (opcodes_trimmed_t), line:65
|vpiTypedef:
\_struct_typespec: (simulation_named_regfile), line:476
|vpiTypedef:
\_struct_typespec: (taiga_trace_events_t), line:442
|vpiTypedef:
\_struct_typespec: (to_l1_arbiter_packet), line:418
|vpiTypedef:
\_struct_typespec: (trace_outputs_t), line:469
|vpiTypedef:
\_logic_typespec: (unit_id_t), line:31
|vpiTypedef:
\_struct_typespec: (unit_writeback_t), line:295
|vpiTypedef:
\_enum_typespec: (vm_t), line:223
|vpiParamAssign:
\_param_assign: , line:6
|vpiRhs:
\_constant: , line:6
|vpiConstType:7
|vpiDecompile:32
|vpiSize:32
|INT:32
|vpiLhs:
\_parameter: (C_WIDTH), line:6
|vpiName:C_WIDTH
|vpiParameter:
\_parameter: (C_WIDTH), line:6
|uhdmallModules:
\_module: work@dtag_banks, file:third_party/cores/taiga/core/dtag_banks.sv, line:26, parent:work@div_unit_core_wrapper
|vpiDefName:work@dtag_banks
|vpiFullName:work@dtag_banks
|vpiProcess:
\_always: , line:86
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:86
|vpiCondition:
\_operation: , line:86
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:86
|vpiName:clk
|vpiFullName:work@dtag_banks.clk
|vpiStmt:
\_begin: , line:86
|vpiFullName:work@dtag_banks
|vpiStmt:
\_if_else: , line:87
|vpiCondition:
\_ref_obj: (rst), line:87
|vpiName:rst
|vpiFullName:work@dtag_banks.rst
|vpiStmt:
\_assignment: , line:88
|vpiOpType:82
|vpiLhs:
\_ref_obj: (inv_tags_accessed), line:88
|vpiName:inv_tags_accessed
|vpiFullName:work@dtag_banks.inv_tags_accessed
|vpiRhs:
\_constant: , line:88
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiElseStmt:
\_assignment: , line:90
|vpiOpType:82
|vpiLhs:
\_ref_obj: (inv_tags_accessed), line:90
|vpiName:inv_tags_accessed
|vpiFullName:work@dtag_banks.inv_tags_accessed
|vpiRhs:
\_operation: , line:90
|vpiOpType:28
|vpiOperand:
\_ref_obj: (extern_inv), line:90
|vpiName:extern_inv
|vpiFullName:work@dtag_banks.extern_inv
|vpiOperand:
\_operation: , line:90
|vpiOpType:4
|vpiOperand:
\_ref_obj: (update), line:90
|vpiName:update
|vpiFullName:work@dtag_banks.update
|vpiPort:
\_port: (clk), line:27
|vpiName:clk
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (clk), line:27
|vpiName:clk
|vpiFullName:work@dtag_banks.clk
|vpiNetType:36
|vpiPort:
\_port: (rst), line:28
|vpiName:rst
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (rst), line:28
|vpiName:rst
|vpiFullName:work@dtag_banks.rst
|vpiNetType:36
|vpiPort:
\_port: (stage1_addr), line:30
|vpiName:stage1_addr
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (stage1_addr), line:30
|vpiName:stage1_addr
|vpiFullName:work@dtag_banks.stage1_addr
|vpiNetType:36
|vpiPort:
\_port: (stage2_addr), line:31
|vpiName:stage2_addr
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (stage2_addr), line:31
|vpiName:stage2_addr
|vpiFullName:work@dtag_banks.stage2_addr
|vpiNetType:36
|vpiPort:
\_port: (inv_addr), line:32
|vpiName:inv_addr
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (inv_addr), line:32
|vpiName:inv_addr
|vpiFullName:work@dtag_banks.inv_addr
|vpiNetType:36
|vpiPort:
\_port: (update_way), line:34
|vpiName:update_way
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (update_way), line:34
|vpiName:update_way
|vpiFullName:work@dtag_banks.update_way
|vpiNetType:36
|vpiPort:
\_port: (update), line:35
|vpiName:update
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (update), line:35
|vpiName:update
|vpiFullName:work@dtag_banks.update
|vpiNetType:36
|vpiPort:
\_port: (stage1_adv), line:37
|vpiName:stage1_adv
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (stage1_adv), line:37
|vpiName:stage1_adv
|vpiFullName:work@dtag_banks.stage1_adv
|vpiNetType:36
|vpiPort:
\_port: (stage1_inv), line:38
|vpiName:stage1_inv
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (stage1_inv), line:38
|vpiName:stage1_inv
|vpiFullName:work@dtag_banks.stage1_inv
|vpiNetType:36
|vpiPort:
\_port: (extern_inv), line:40
|vpiName:extern_inv
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (extern_inv), line:40
|vpiName:extern_inv
|vpiFullName:work@dtag_banks.extern_inv
|vpiNetType:36
|vpiPort:
\_port: (extern_inv_complete), line:41
|vpiName:extern_inv_complete
|vpiDirection:2
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (extern_inv_complete), line:41
|vpiName:extern_inv_complete
|vpiFullName:work@dtag_banks.extern_inv_complete
|vpiNetType:36
|vpiPort:
\_port: (tag_hit), line:43
|vpiName:tag_hit
|vpiDirection:2
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (tag_hit), line:43
|vpiName:tag_hit
|vpiFullName:work@dtag_banks.tag_hit
|vpiPort:
\_port: (tag_hit_way), line:44
|vpiName:tag_hit_way
|vpiDirection:2
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (tag_hit_way), line:44
|vpiName:tag_hit_way
|vpiFullName:work@dtag_banks.tag_hit_way
|vpiNetType:36
|vpiContAssign:
\_cont_assign: , line:80
|vpiRhs:
\_operation: , line:80
|vpiOpType:29
|vpiOperand:
\_ref_obj: (update), line:80
|vpiName:update
|vpiFullName:work@dtag_banks.update
|vpiOperand:
\_ref_obj: (extern_inv), line:80
|vpiName:extern_inv
|vpiFullName:work@dtag_banks.extern_inv
|vpiLhs:
\_ref_obj: (miss_or_extern_invalidate), line:80
|vpiName:miss_or_extern_invalidate
|vpiFullName:work@dtag_banks.miss_or_extern_invalidate
|vpiContAssign:
\_cont_assign: , line:81
|vpiRhs:
\_operation: , line:81
|vpiOpType:32
|vpiOperand:
\_ref_obj: (update), line:81
|vpiName:update
|vpiFullName:work@dtag_banks.update
|vpiOperand:
\_func_call: (getLineAddr), line:81
|vpiName:getLineAddr
|vpiFunction:
\_function: (getLineAddr), line:56
|vpiName:getLineAddr
|vpiFullName:work@dtag_banks.getLineAddr
|vpiReturn:
\_logic_var: , line:56
|vpiRange:
\_range: , line:56
|vpiLeftRange:
\_operation: , line:56
|vpiOpType:11
|vpiOperand:
\_ref_obj: (DCACHE_LINE_ADDR_W), line:56
|vpiName:DCACHE_LINE_ADDR_W
|vpiOperand:
\_constant: , line:56
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:56
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (addr)
|vpiName:addr
|vpiDirection:5
|vpiExpr:
\_logic_var: , line:56, parent:addr
|vpiFullName:addr
|vpiRange:
\_range: , line:56
|vpiLeftRange:
\_constant: , line:56
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:56
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiStmt:
\_return_stmt: , line:57, parent:getLineAddr
|vpiCondition:
\_part_select: , line:57
|vpiConstantSelect:1
|vpiParent:
\_return_stmt: , line:57, parent:getLineAddr
|vpiLeftRange:
\_operation: , line:57
|vpiOpType:24
|vpiOperand:
\_operation: , line:57
|vpiOpType:24
|vpiOperand:
\_ref_obj: (DCACHE_LINE_ADDR_W), line:57
|vpiName:DCACHE_LINE_ADDR_W
|vpiOperand:
\_ref_obj: (DCACHE_SUB_LINE_ADDR_W), line:57
|vpiName:DCACHE_SUB_LINE_ADDR_W
|vpiOperand:
\_constant: , line:57
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_operation: , line:57
|vpiOpType:24
|vpiOperand:
\_ref_obj: (DCACHE_SUB_LINE_ADDR_W), line:57
|vpiName:DCACHE_SUB_LINE_ADDR_W
|vpiOperand:
\_constant: , line:57
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiArgument:
\_ref_obj: (stage2_addr), line:81
|vpiName:stage2_addr
|vpiOperand:
\_func_call: (getLineAddr), line:81
|vpiName:getLineAddr
|vpiFunction:
\_function: (getLineAddr), line:56
|vpiArgument:
\_ref_obj: (inv_addr), line:81
|vpiName:inv_addr
|vpiLhs:
\_ref_obj: (update_port_addr), line:81
|vpiName:update_port_addr
|vpiFullName:work@dtag_banks.update_port_addr
|vpiContAssign:
\_cont_assign: , line:83
|vpiRhs:
\_ref_obj: (update), line:83
|vpiName:update
|vpiFullName:work@dtag_banks.update
|vpiLhs:
\_ref_obj: (new_tagline.valid), line:83
|vpiName:new_tagline.valid
|vpiFullName:work@dtag_banks.new_tagline.valid
|vpiContAssign:
\_cont_assign: , line:84
|vpiRhs:
\_func_call: (getTag), line:84
|vpiName:getTag
|vpiFunction:
\_function: (getTag), line:52
|vpiName:getTag
|vpiFullName:work@dtag_banks.getTag
|vpiReturn:
\_logic_var: , line:52
|vpiRange:
\_range: , line:52
|vpiLeftRange:
\_operation: , line:52
|vpiOpType:11
|vpiOperand:
\_ref_obj: (DCACHE_TAG_W), line:52
|vpiName:DCACHE_TAG_W
|vpiOperand:
\_constant: , line:52
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:52
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (addr)
|vpiName:addr
|vpiDirection:5
|vpiExpr:
\_logic_var: , line:52, parent:addr
|vpiFullName:addr
|vpiRange:
\_range: , line:52
|vpiLeftRange:
\_constant: , line:52
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:52
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiStmt:
\_return_stmt: , line:53, parent:getTag
|vpiCondition:
\_part_select: , line:53
|vpiConstantSelect:1
|vpiParent:
\_return_stmt: , line:53, parent:getTag
|vpiLeftRange:
\_constant: , line:53
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_operation: , line:53
|vpiOpType:11
|vpiOperand:
\_constant: , line:53
|vpiConstType:7
|vpiDecompile:32
|vpiSize:32
|INT:32
|vpiOperand:
\_ref_obj: (DCACHE_TAG_W), line:53
|vpiName:DCACHE_TAG_W
|vpiArgument:
\_ref_obj: (stage2_addr), line:84
|vpiName:stage2_addr
|vpiLhs:
\_ref_obj: (new_tagline.tag), line:84
|vpiName:new_tagline.tag
|vpiFullName:work@dtag_banks.new_tagline.tag
|vpiContAssign:
\_cont_assign: , line:93
|vpiRhs:
\_operation: , line:93
|vpiOpType:28
|vpiOperand:
\_operation: , line:93
|vpiOpType:28
|vpiOperand:
\_ref_obj: (extern_inv), line:93
|vpiName:extern_inv
|vpiFullName:work@dtag_banks.extern_inv
|vpiOperand:
\_operation: , line:93
|vpiOpType:4
|vpiOperand:
\_ref_obj: (update), line:93
|vpiName:update
|vpiFullName:work@dtag_banks.update
|vpiOperand:
\_ref_obj: (inv_tags_accessed), line:93
|vpiName:inv_tags_accessed
|vpiFullName:work@dtag_banks.inv_tags_accessed
|vpiLhs:
\_ref_obj: (extern_inv_complete), line:93
|vpiName:extern_inv_complete
|vpiFullName:work@dtag_banks.extern_inv_complete
|vpiContAssign:
\_cont_assign: , line:102
|vpiRhs:
\_constant: , line:102
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiLhs:
\_ref_obj: (stage2_hit_comparison_tagline.valid), line:102
|vpiName:stage2_hit_comparison_tagline.valid
|vpiFullName:work@dtag_banks.stage2_hit_comparison_tagline.valid
|vpiContAssign:
\_cont_assign: , line:103
|vpiRhs:
\_func_call: (getTag), line:103
|vpiName:getTag
|vpiFunction:
\_function: (getTag), line:52
|vpiArgument:
\_ref_obj: (stage2_addr), line:103
|vpiName:stage2_addr
|vpiLhs:
\_ref_obj: (stage2_hit_comparison_tagline.tag), line:103
|vpiName:stage2_hit_comparison_tagline.tag
|vpiFullName:work@dtag_banks.stage2_hit_comparison_tagline.tag
|vpiContAssign:
\_cont_assign: , line:104
|vpiRhs:
\_constant: , line:104
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiLhs:
\_ref_obj: (inv_hit_comparison_tagline.valid), line:104
|vpiName:inv_hit_comparison_tagline.valid
|vpiFullName:work@dtag_banks.inv_hit_comparison_tagline.valid
|vpiContAssign:
\_cont_assign: , line:105
|vpiRhs:
\_func_call: (getTag), line:105
|vpiName:getTag
|vpiFunction:
\_function: (getTag), line:52
|vpiArgument:
\_ref_obj: (inv_addr), line:105
|vpiName:inv_addr
|vpiLhs:
\_ref_obj: (inv_hit_comparison_tagline.tag), line:105
|vpiName:inv_hit_comparison_tagline.tag
|vpiFullName:work@dtag_banks.inv_hit_comparison_tagline.tag
|vpiContAssign:
\_cont_assign: , line:126
|vpiRhs:
\_operation: , line:126
|vpiOpType:7
|vpiOperand:
\_ref_obj: (tag_hit_way), line:126
|vpiName:tag_hit_way
|vpiFullName:work@dtag_banks.tag_hit_way
|vpiLhs:
\_ref_obj: (tag_hit), line:126
|vpiName:tag_hit
|vpiFullName:work@dtag_banks.tag_hit
|vpiTaskFunc:
\_function: (getTag), line:52
|vpiTaskFunc:
\_function: (getLineAddr), line:56
|vpiNet:
\_logic_net: (clk), line:27
|vpiNet:
\_logic_net: (rst), line:28
|vpiNet:
\_logic_net: (stage1_addr), line:30
|vpiNet:
\_logic_net: (stage2_addr), line:31
|vpiNet:
\_logic_net: (inv_addr), line:32
|vpiNet:
\_logic_net: (update_way), line:34
|vpiNet:
\_logic_net: (update), line:35
|vpiNet:
\_logic_net: (stage1_adv), line:37
|vpiNet:
\_logic_net: (stage1_inv), line:38
|vpiNet:
\_logic_net: (extern_inv), line:40
|vpiNet:
\_logic_net: (extern_inv_complete), line:41
|vpiNet:
\_logic_net: (tag_hit), line:43
|vpiNet:
\_logic_net: (tag_hit_way), line:44
|vpiNet:
\_logic_net: (tag_line), line:60
|vpiName:tag_line
|vpiFullName:work@dtag_banks.tag_line
|vpiNet:
\_logic_net: (inv_tag_line), line:61
|vpiName:inv_tag_line
|vpiFullName:work@dtag_banks.inv_tag_line
|vpiNet:
\_logic_net: (new_tagline), line:63
|vpiName:new_tagline
|vpiFullName:work@dtag_banks.new_tagline
|vpiNet:
\_logic_net: (miss_or_extern_invalidate), line:65
|vpiName:miss_or_extern_invalidate
|vpiFullName:work@dtag_banks.miss_or_extern_invalidate
|vpiNetType:36
|vpiNet:
\_logic_net: (update_tag_way), line:66
|vpiName:update_tag_way
|vpiFullName:work@dtag_banks.update_tag_way
|vpiNetType:36
|vpiNet:
\_logic_net: (inv_tags_accessed), line:68
|vpiName:inv_tags_accessed
|vpiFullName:work@dtag_banks.inv_tags_accessed
|vpiNetType:36
|vpiNet:
\_logic_net: (inv_hit_way), line:70
|vpiName:inv_hit_way
|vpiFullName:work@dtag_banks.inv_hit_way
|vpiNetType:36
|vpiNet:
\_logic_net: (inv_hit_way_r), line:71
|vpiName:inv_hit_way_r
|vpiFullName:work@dtag_banks.inv_hit_way_r
|vpiNetType:36
|vpiNet:
\_logic_net: (update_port_addr), line:73
|vpiName:update_port_addr
|vpiFullName:work@dtag_banks.update_port_addr
|vpiNetType:36
|vpiNet:
\_logic_net: (stage2_hit_comparison_tagline), line:99
|vpiName:stage2_hit_comparison_tagline
|vpiFullName:work@dtag_banks.stage2_hit_comparison_tagline
|vpiNet:
\_logic_net: (inv_hit_comparison_tagline), line:100
|vpiName:inv_hit_comparison_tagline
|vpiFullName:work@dtag_banks.inv_hit_comparison_tagline
|vpiTypedef:
\_struct_typespec: (alu_inputs_t), line:301
|vpiTypedef:
\_enum_typespec: (alu_logic_op_t), line:84
|vpiTypedef:
\_enum_typespec: (alu_op_t), line:91
|vpiTypedef:
\_enum_typespec: (alu_rs1_op_t), line:97
|vpiTypedef:
\_enum_typespec: (alu_rs2_op_t), line:104
|vpiTypedef:
\_struct_typespec: (amo_alu_inputs_t), line:356
|vpiTypedef:
\_struct_typespec: (amo_details_t), line:362
|vpiTypedef:
\_enum_typespec: (amo_t), line:354
|vpiTypedef:
\_struct_typespec: (branch_inputs_t), line:313
|vpiTypedef:
\_logic_typespec: (branch_predictor_metadata_t), line:32
|vpiTypedef:
\_struct_typespec: (branch_results_t), line:330
|vpiTypedef:
\_enum_typespec: (bus_type_t), line:86
|vpiTypedef:
\_struct_typespec: (csr_inputs_t), line:396
|vpiTypedef:
\_enum_typespec: (csr_op_t), line:218
|vpiTypedef:
\_enum_typespec: (csr_t), line:201
|vpiTypedef:
\_struct_typespec: (data_access_shared_inputs_t), line:427
|vpiTypedef:
\_struct_typespec: (div_inputs_t), line:389
|vpiTypedef:
\_enum_typespec: (div_type), line:66
|vpiTypedef:
\_struct_typespec: (dtag_entry_t), line:47
|vpiPacked:1
|vpiName:dtag_entry_t
|vpiTypespecMember:
\_typespec_member: (valid), line:48
|vpiName:valid
|vpiTypespec:
\_logic_typespec: , line:48
|vpiTypespecMember:
\_typespec_member: (tag), line:49
|vpiName:tag
|vpiTypespec:
\_logic_typespec: , line:49
|vpiRange:
\_range: , line:49, parent:dtag_entry_t
|vpiLeftRange:
\_operation: , line:49
|vpiOpType:11
|vpiOperand:
\_ref_obj: (DCACHE_TAG_W), line:49, parent:dtag_entry_t
|vpiName:DCACHE_TAG_W
|vpiFullName:dtag_entry_t.DCACHE_TAG_W
|vpiOperand:
\_constant: , line:49
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:49
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiTypedef:
\_enum_typespec: (exception_code_t), line:245
|vpiTypedef:
\_struct_typespec: (exception_packet_t), line:263
|vpiTypedef:
\_struct_typespec: (fetch_buffer_packet_t), line:276
|vpiTypedef:
\_enum_typespec: (fifo_type_t), line:440
|vpiTypedef:
\_enum_typespec: (fn3_arith_t), line:76
|vpiTypedef:
\_enum_typespec: (fn3_branch_t), line:126
|vpiTypedef:
\_enum_typespec: (fn3_csr_t), line:212
|vpiTypedef:
\_enum_typespec: (fn3_ls_t), line:115
|vpiTypedef:
\_enum_typespec: (fn3_mul_div_t), line:138
|vpiTypedef:
\_struct_typespec: (gc_inputs_t), line:404
|vpiTypedef:
\_struct_typespec: (inflight_instruction_packet), line:271
|vpiTypedef:
\_logic_typespec: (instruction_id_t), line:30
|vpiTypedef:
\_enum_typespec: (interrupt_code_t), line:261
|vpiTypedef:
\_struct_typespec: (load_store_inputs_t), line:369
|vpiTypedef:
\_struct_typespec: (mul_inputs_t), line:383
|vpiTypedef:
\_enum_typespec: (opcodes_t), line:48
|vpiTypedef:
\_enum_typespec: (opcodes_trimmed_t), line:65
|vpiTypedef:
\_struct_typespec: (simulation_named_regfile), line:476
|vpiTypedef:
\_struct_typespec: (taiga_trace_events_t), line:442
|vpiTypedef:
\_struct_typespec: (to_l1_arbiter_packet), line:418
|vpiTypedef:
\_struct_typespec: (trace_outputs_t), line:469
|vpiTypedef:
\_logic_typespec: (unit_id_t), line:31
|vpiTypedef:
\_struct_typespec: (unit_writeback_t), line:295
|vpiTypedef:
\_enum_typespec: (vm_t), line:223
|uhdmallModules:
\_module: work@fetch, file:third_party/cores/taiga/core/fetch.sv, line:26, parent:work@div_unit_core_wrapper
|vpiDefName:work@fetch
|vpiFullName:work@fetch
|vpiProcess:
\_always: , line:95
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:95
|vpiCondition:
\_operation: , line:95
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:95
|vpiName:clk
|vpiFullName:work@fetch.clk
|vpiStmt:
\_begin: , line:95
|vpiFullName:work@fetch
|vpiStmt:
\_if_else: , line:96
|vpiCondition:
\_ref_obj: (rst), line:96
|vpiName:rst
|vpiFullName:work@fetch.rst
|vpiStmt:
\_assignment: , line:97
|vpiOpType:82
|vpiLhs:
\_ref_obj: (pc), line:97
|vpiName:pc
|vpiFullName:work@fetch.pc
|vpiRhs:
\_ref_obj: (RESET_VEC), line:97
|vpiName:RESET_VEC
|vpiFullName:work@fetch.RESET_VEC
|vpiElseStmt:
\_if_stmt: , line:98
|vpiCondition:
\_operation: , line:98
|vpiOpType:29
|vpiOperand:
\_ref_obj: (new_mem_request), line:98
|vpiName:new_mem_request
|vpiFullName:work@fetch.new_mem_request
|vpiOperand:
\_ref_obj: (gc_fetch_flush), line:98
|vpiName:gc_fetch_flush
|vpiFullName:work@fetch.gc_fetch_flush
|vpiStmt:
\_assignment: , line:99
|vpiOpType:82
|vpiLhs:
\_ref_obj: (pc), line:99
|vpiName:pc
|vpiFullName:work@fetch.pc
|vpiRhs:
\_operation: , line:99
|vpiOpType:33
|vpiOperand:
\_part_select: , line:99, parent:next_pc
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (next_pc)
|vpiLeftRange:
\_constant: , line:99
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:99
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiOperand:
\_constant: , line:99
|vpiConstType:3
|vpiDecompile:2'b0
|vpiSize:2
|BIN:2'b0
|vpiProcess:
\_always: , line:102
|vpiAlwaysType:2
|vpiStmt:
\_begin: , line:102
|vpiFullName:work@fetch
|vpiStmt:
\_if_else: , line:103
|vpiCondition:
\_ref_obj: (branch_flush), line:103
|vpiName:branch_flush
|vpiFullName:work@fetch.branch_flush
|vpiStmt:
\_assignment: , line:104
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (next_pc), line:104
|vpiName:next_pc
|vpiFullName:work@fetch.next_pc
|vpiRhs:
\_ref_obj: (bp.branch_flush_pc), line:104
|vpiName:bp.branch_flush_pc
|vpiFullName:work@fetch.bp.branch_flush_pc
|vpiElseStmt:
\_if_else: , line:105
|vpiCondition:
\_ref_obj: (gc_fetch_pc_override), line:105
|vpiName:gc_fetch_pc_override
|vpiFullName:work@fetch.gc_fetch_pc_override
|vpiStmt:
\_assignment: , line:106
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (next_pc), line:106
|vpiName:next_pc
|vpiFullName:work@fetch.next_pc
|vpiRhs:
\_ref_obj: (gc_fetch_pc), line:106
|vpiName:gc_fetch_pc
|vpiFullName:work@fetch.gc_fetch_pc
|vpiElseStmt:
\_if_else: , line:107
|vpiCondition:
\_ref_obj: (bp.use_prediction), line:107
|vpiName:bp.use_prediction
|vpiFullName:work@fetch.bp.use_prediction
|vpiStmt:
\_assignment: , line:108
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (next_pc), line:108
|vpiName:next_pc
|vpiFullName:work@fetch.next_pc
|vpiRhs:
\_operation: , line:108
|vpiOpType:32
|vpiOperand:
\_operation: , line:108
|vpiOpType:28
|vpiOperand:
\_ref_obj: (bp.use_ras), line:108
|vpiName:bp.use_ras
|vpiFullName:work@fetch.bp.use_ras
|vpiOperand:
\_ref_obj: (ras.valid), line:108
|vpiName:ras.valid
|vpiFullName:work@fetch.ras.valid
|vpiOperand:
\_ref_obj: (ras.addr), line:108
|vpiName:ras.addr
|vpiFullName:work@fetch.ras.addr
|vpiOperand:
\_ref_obj: (bp.predicted_pc), line:108
|vpiName:bp.predicted_pc
|vpiFullName:work@fetch.bp.predicted_pc
|vpiElseStmt:
\_assignment: , line:110
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (next_pc), line:110
|vpiName:next_pc
|vpiFullName:work@fetch.next_pc
|vpiRhs:
\_operation: , line:110
|vpiOpType:24
|vpiOperand:
\_ref_obj: (pc), line:110
|vpiName:pc
|vpiFullName:work@fetch.pc
|vpiOperand:
\_constant: , line:110
|vpiConstType:7
|vpiDecompile:4
|vpiSize:32
|INT:4
|vpiProcess:
\_always: , line:124
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:124
|vpiCondition:
\_operation: , line:124
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:124
|vpiName:clk
|vpiFullName:work@fetch.clk
|vpiStmt:
\_begin: , line:124
|vpiFullName:work@fetch
|vpiStmt:
\_if_stmt: , line:125
|vpiCondition:
\_ref_obj: (new_mem_request), line:125
|vpiName:new_mem_request
|vpiFullName:work@fetch.new_mem_request
|vpiStmt:
\_assignment: , line:126
|vpiOpType:82
|vpiLhs:
\_ref_obj: (stage2_phys_address), line:126
|vpiName:stage2_phys_address
|vpiFullName:work@fetch.stage2_phys_address
|vpiRhs:
\_ref_obj: (tlb.physical_address), line:126
|vpiName:tlb.physical_address
|vpiFullName:work@fetch.tlb.physical_address
|vpiProcess:
\_always: , line:133
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:133
|vpiCondition:
\_operation: , line:133
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:133
|vpiName:clk
|vpiFullName:work@fetch.clk
|vpiStmt:
\_begin: , line:133
|vpiFullName:work@fetch
|vpiStmt:
\_if_else: , line:134
|vpiCondition:
\_ref_obj: (flush_or_rst), line:134
|vpiName:flush_or_rst
|vpiFullName:work@fetch.flush_or_rst
|vpiStmt:
\_assignment: , line:135
|vpiOpType:82
|vpiLhs:
\_ref_obj: (inflight_count), line:135
|vpiName:inflight_count
|vpiFullName:work@fetch.inflight_count
|vpiRhs:
\_constant: , line:135
|vpiConstType:3
|vpiDecompile:'b1
|vpiSize:1
|BIN:1
|vpiElseStmt:
\_assignment: , line:137
|vpiOpType:82
|vpiLhs:
\_ref_obj: (inflight_count), line:137
|vpiName:inflight_count
|vpiFullName:work@fetch.inflight_count
|vpiRhs:
\_operation: , line:137
|vpiOpType:24
|vpiOperand:
\_operation: , line:137
|vpiOpType:11
|vpiOperand:
\_ref_obj: (inflight_count), line:137
|vpiName:inflight_count
|vpiFullName:work@fetch.inflight_count
|vpiOperand:
\_operation: , line:137
|vpiOpType:67
|vpiOperand:
\_ref_obj: (new_mem_request), line:137
|vpiName:new_mem_request
|vpiFullName:work@fetch.new_mem_request
|vpiOperand:
\_operation: , line:137
|vpiOpType:67
|vpiOperand:
\_ref_obj: (pre_decode_pop), line:137
|vpiName:pre_decode_pop
|vpiFullName:work@fetch.pre_decode_pop
|vpiProcess:
\_always: , line:210
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:210
|vpiCondition:
\_operation: , line:210
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:210
|vpiName:clk
|vpiFullName:work@fetch.clk
|vpiStmt:
\_begin: , line:210
|vpiFullName:work@fetch
|vpiStmt:
\_if_stmt: , line:211
|vpiCondition:
\_ref_obj: (new_mem_request), line:211
|vpiName:new_mem_request
|vpiFullName:work@fetch.new_mem_request
|vpiStmt:
\_begin: , line:211
|vpiFullName:work@fetch
|vpiStmt:
\_assignment: , line:212
|vpiOpType:82
|vpiLhs:
\_ref_obj: (branch_metadata), line:212
|vpiName:branch_metadata
|vpiFullName:work@fetch.branch_metadata
|vpiRhs:
\_ref_obj: (bp.metadata), line:212
|vpiName:bp.metadata
|vpiFullName:work@fetch.bp.metadata
|vpiStmt:
\_assignment: , line:213
|vpiOpType:82
|vpiLhs:
\_ref_obj: (branch_prediction_used), line:213
|vpiName:branch_prediction_used
|vpiFullName:work@fetch.branch_prediction_used
|vpiRhs:
\_ref_obj: (bp.use_prediction), line:213
|vpiName:bp.use_prediction
|vpiFullName:work@fetch.bp.use_prediction
|vpiStmt:
\_assignment: , line:214
|vpiOpType:82
|vpiLhs:
\_ref_obj: (bp_update_way), line:214
|vpiName:bp_update_way
|vpiFullName:work@fetch.bp_update_way
|vpiRhs:
\_ref_obj: (bp.update_way), line:214
|vpiName:bp.update_way
|vpiFullName:work@fetch.bp.update_way
|vpiPort:
\_port: (clk), line:27
|vpiName:clk
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (clk), line:27
|vpiName:clk
|vpiFullName:work@fetch.clk
|vpiNetType:36
|vpiPort:
\_port: (rst), line:28
|vpiName:rst
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (rst), line:28
|vpiName:rst
|vpiFullName:work@fetch.rst
|vpiNetType:36
|vpiPort:
\_port: (branch_flush), line:30
|vpiName:branch_flush
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (branch_flush), line:30
|vpiName:branch_flush
|vpiFullName:work@fetch.branch_flush
|vpiNetType:36
|vpiPort:
\_port: (gc_fetch_flush), line:31
|vpiName:gc_fetch_flush
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (gc_fetch_flush), line:31
|vpiName:gc_fetch_flush
|vpiFullName:work@fetch.gc_fetch_flush
|vpiNetType:36
|vpiPort:
\_port: (gc_fetch_pc_override), line:32
|vpiName:gc_fetch_pc_override
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (gc_fetch_pc_override), line:32
|vpiName:gc_fetch_pc_override
|vpiFullName:work@fetch.gc_fetch_pc_override
|vpiNetType:36
|vpiPort:
\_port: (exception), line:33
|vpiName:exception
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (exception), line:33
|vpiName:exception
|vpiFullName:work@fetch.exception
|vpiNetType:36
|vpiPort:
\_port: (gc_fetch_pc), line:34
|vpiName:gc_fetch_pc
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (gc_fetch_pc), line:34
|vpiName:gc_fetch_pc
|vpiFullName:work@fetch.gc_fetch_pc
|vpiNetType:36
|vpiPort:
\_port: (bp), line:36
|vpiName:bp
|vpiDirection:5
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_modport: (fetch)
|vpiPort:
\_port: (ras), line:37
|vpiName:ras
|vpiDirection:5
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_modport: (fetch)
|vpiPort:
\_port: (tlb), line:39
|vpiName:tlb
|vpiDirection:5
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_modport: (mem)
|vpiPort:
\_port: (instruction_bram), line:40
|vpiName:instruction_bram
|vpiDirection:5
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_modport: (master)
|vpiPort:
\_port: (icache_on), line:41
|vpiName:icache_on
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (icache_on), line:41
|vpiName:icache_on
|vpiFullName:work@fetch.icache_on
|vpiNetType:36
|vpiPort:
\_port: (l1_request), line:42
|vpiName:l1_request
|vpiDirection:5
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_modport: (master)
|vpiPort:
\_port: (l1_response), line:43
|vpiName:l1_response
|vpiDirection:5
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_modport: (master)
|vpiPort:
\_port: (pre_decode_pop), line:45
|vpiName:pre_decode_pop
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (pre_decode_pop), line:45
|vpiName:pre_decode_pop
|vpiFullName:work@fetch.pre_decode_pop
|vpiNetType:36
|vpiPort:
\_port: (pre_decode_instruction), line:47
|vpiName:pre_decode_instruction
|vpiDirection:2
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (pre_decode_instruction), line:47
|vpiName:pre_decode_instruction
|vpiFullName:work@fetch.pre_decode_instruction
|vpiNetType:36
|vpiPort:
\_port: (pre_decode_pc), line:48
|vpiName:pre_decode_pc
|vpiDirection:2
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (pre_decode_pc), line:48
|vpiName:pre_decode_pc
|vpiFullName:work@fetch.pre_decode_pc
|vpiNetType:36
|vpiPort:
\_port: (branch_metadata), line:49
|vpiName:branch_metadata
|vpiDirection:2
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (branch_metadata), line:49
|vpiName:branch_metadata
|vpiFullName:work@fetch.branch_metadata
|vpiPort:
\_port: (branch_prediction_used), line:50
|vpiName:branch_prediction_used
|vpiDirection:2
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (branch_prediction_used), line:50
|vpiName:branch_prediction_used
|vpiFullName:work@fetch.branch_prediction_used
|vpiNetType:36
|vpiPort:
\_port: (bp_update_way), line:51
|vpiName:bp_update_way
|vpiDirection:2
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (bp_update_way), line:51
|vpiName:bp_update_way
|vpiFullName:work@fetch.bp_update_way
|vpiNetType:36
|vpiPort:
\_port: (pre_decode_push), line:52
|vpiName:pre_decode_push
|vpiDirection:2
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (pre_decode_push), line:52
|vpiName:pre_decode_push
|vpiFullName:work@fetch.pre_decode_push
|vpiNetType:36
|vpiContAssign:
\_cont_assign: , line:113
|vpiRhs:
\_operation: , line:113
|vpiOpType:29
|vpiOperand:
\_ref_obj: (new_mem_request), line:113
|vpiName:new_mem_request
|vpiFullName:work@fetch.new_mem_request
|vpiOperand:
\_ref_obj: (gc_fetch_flush), line:113
|vpiName:gc_fetch_flush
|vpiFullName:work@fetch.gc_fetch_flush
|vpiLhs:
\_ref_obj: (bp.new_mem_request), line:113
|vpiName:bp.new_mem_request
|vpiFullName:work@fetch.bp.new_mem_request
|vpiContAssign:
\_cont_assign: , line:114
|vpiRhs:
\_ref_obj: (next_pc), line:114
|vpiName:next_pc
|vpiFullName:work@fetch.next_pc
|vpiLhs:
\_ref_obj: (bp.next_pc), line:114
|vpiName:bp.next_pc
|vpiFullName:work@fetch.bp.next_pc
|vpiContAssign:
\_cont_assign: , line:116
|vpiRhs:
\_ref_obj: (pc), line:116
|vpiName:pc
|vpiFullName:work@fetch.pc
|vpiLhs:
\_ref_obj: (bp.if_pc), line:116
|vpiName:bp.if_pc
|vpiFullName:work@fetch.bp.if_pc
|vpiContAssign:
\_cont_assign: , line:120
|vpiRhs:
\_ref_obj: (pc), line:120
|vpiName:pc
|vpiFullName:work@fetch.pc
|vpiLhs:
\_ref_obj: (tlb.virtual_address), line:120
|vpiName:tlb.virtual_address
|vpiFullName:work@fetch.tlb.virtual_address
|vpiContAssign:
\_cont_assign: , line:121
|vpiRhs:
\_constant: , line:121
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiLhs:
\_ref_obj: (tlb.execute), line:121
|vpiName:tlb.execute
|vpiFullName:work@fetch.tlb.execute
|vpiContAssign:
\_cont_assign: , line:122
|vpiRhs:
\_constant: , line:122
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiLhs:
\_ref_obj: (tlb.rnw), line:122
|vpiName:tlb.rnw
|vpiFullName:work@fetch.tlb.rnw
|vpiContAssign:
\_cont_assign: , line:131
|vpiRhs:
\_operation: , line:131
|vpiOpType:29
|vpiOperand:
\_ref_obj: (rst), line:131
|vpiName:rst
|vpiFullName:work@fetch.rst
|vpiOperand:
\_ref_obj: (gc_fetch_flush), line:131
|vpiName:gc_fetch_flush
|vpiFullName:work@fetch.gc_fetch_flush
|vpiLhs:
\_ref_obj: (flush_or_rst), line:131
|vpiName:flush_or_rst
|vpiFullName:work@fetch.flush_or_rst
|vpiContAssign:
\_cont_assign: , line:140
|vpiRhs:
\_bit_select: (inflight_count), line:140
|vpiName:inflight_count
|vpiFullName:work@fetch.inflight_count
|vpiIndex:
\_ref_obj: (FETCH_BUFFER_DEPTH_W), line:140
|vpiName:FETCH_BUFFER_DEPTH_W
|vpiLhs:
\_ref_obj: (space_in_inst_buffer), line:140
|vpiName:space_in_inst_buffer
|vpiFullName:work@fetch.space_in_inst_buffer
|vpiContAssign:
\_cont_assign: , line:141
|vpiRhs:
\_operation: , line:141
|vpiOpType:28
|vpiOperand:
\_operation: , line:141
|vpiOpType:28
|vpiOperand:
\_ref_obj: (tlb.complete), line:141
|vpiName:tlb.complete
|vpiFullName:work@fetch.tlb.complete
|vpiOperand:
\_ref_obj: (space_in_inst_buffer), line:141
|vpiName:space_in_inst_buffer
|vpiFullName:work@fetch.space_in_inst_buffer
|vpiOperand:
\_ref_obj: (units_ready), line:141
|vpiName:units_ready
|vpiFullName:work@fetch.units_ready
|vpiLhs:
\_ref_obj: (new_mem_request), line:141
|vpiName:new_mem_request
|vpiFullName:work@fetch.new_mem_request
|vpiContAssign:
\_cont_assign: , line:145
|vpiRhs:
\_ref_obj: (new_mem_request), line:145
|vpiName:new_mem_request
|vpiFullName:work@fetch.new_mem_request
|vpiLhs:
\_ref_obj: (next_unit.push), line:145
|vpiName:next_unit.push
|vpiFullName:work@fetch.next_unit.push
|vpiContAssign:
\_cont_assign: , line:146
|vpiRhs:
\_ref_obj: (units_data_valid), line:146
|vpiName:units_data_valid
|vpiFullName:work@fetch.units_data_valid
|vpiLhs:
\_ref_obj: (next_unit.pop), line:146
|vpiName:next_unit.pop
|vpiFullName:work@fetch.next_unit.pop
|vpiContAssign:
\_cont_assign: , line:164
|vpiRhs:
\_operation: , line:164
|vpiOpType:5
|vpiOperand:
\_ref_obj: (unit_ready), line:164
|vpiName:unit_ready
|vpiFullName:work@fetch.unit_ready
|vpiLhs:
\_ref_obj: (units_ready), line:164
|vpiName:units_ready
|vpiFullName:work@fetch.units_ready
|vpiContAssign:
\_cont_assign: , line:165
|vpiRhs:
\_operation: , line:165
|vpiOpType:7
|vpiOperand:
\_ref_obj: (unit_data_valid), line:165
|vpiName:unit_data_valid
|vpiFullName:work@fetch.unit_data_valid
|vpiLhs:
\_ref_obj: (units_data_valid), line:165
|vpiName:units_data_valid
|vpiFullName:work@fetch.units_data_valid
|vpiContAssign:
\_cont_assign: , line:206
|vpiRhs:
\_bit_select: (unit_data_array), line:206
|vpiName:unit_data_array
|vpiFullName:work@fetch.unit_data_array
|vpiIndex:
\_ref_obj: (next_unit.data_out), line:206
|vpiName:next_unit.data_out
|vpiLhs:
\_ref_obj: (pre_decode_instruction), line:206
|vpiName:pre_decode_instruction
|vpiFullName:work@fetch.pre_decode_instruction
|vpiContAssign:
\_cont_assign: , line:207
|vpiRhs:
\_ref_obj: (stage2_phys_address), line:207
|vpiName:stage2_phys_address
|vpiFullName:work@fetch.stage2_phys_address
|vpiLhs:
\_ref_obj: (pre_decode_pc), line:207
|vpiName:pre_decode_pc
|vpiFullName:work@fetch.pre_decode_pc
|vpiContAssign:
\_cont_assign: , line:208
|vpiRhs:
\_operation: , line:208
|vpiOpType:28
|vpiOperand:
\_operation: , line:208
|vpiOpType:4
|vpiOperand:
\_ref_obj: (delayed_flush), line:208
|vpiName:delayed_flush
|vpiFullName:work@fetch.delayed_flush
|vpiOperand:
\_ref_obj: (units_data_valid), line:208
|vpiName:units_data_valid
|vpiFullName:work@fetch.units_data_valid
|vpiLhs:
\_ref_obj: (pre_decode_push), line:208
|vpiName:pre_decode_push
|vpiFullName:work@fetch.pre_decode_push
|vpiNet:
\_logic_net: (clk), line:27
|vpiNet:
\_logic_net: (rst), line:28
|vpiNet:
\_logic_net: (branch_flush), line:30
|vpiNet:
\_logic_net: (gc_fetch_flush), line:31
|vpiNet:
\_logic_net: (gc_fetch_pc_override), line:32
|vpiNet:
\_logic_net: (exception), line:33
|vpiNet:
\_logic_net: (gc_fetch_pc), line:34
|vpiNet:
\_logic_net: (icache_on), line:41
|vpiNet:
\_logic_net: (pre_decode_pop), line:45
|vpiNet:
\_logic_net: (pre_decode_instruction), line:47
|vpiNet:
\_logic_net: (pre_decode_pc), line:48
|vpiNet:
\_logic_net: (branch_metadata), line:49
|vpiNet:
\_logic_net: (branch_prediction_used), line:50
|vpiNet:
\_logic_net: (bp_update_way), line:51
|vpiNet:
\_logic_net: (pre_decode_push), line:52
|vpiNet:
\_logic_net: (sub_unit_address_match), line:66
|vpiName:sub_unit_address_match
|vpiFullName:work@fetch.sub_unit_address_match
|vpiNetType:36
|vpiNet:
\_logic_net: (last_sub_unit_id), line:67
|vpiName:last_sub_unit_id
|vpiFullName:work@fetch.last_sub_unit_id
|vpiNetType:36
|vpiNet:
\_logic_net: (unit_ready), line:68
|vpiName:unit_ready
|vpiFullName:work@fetch.unit_ready
|vpiNetType:36
|vpiNet:
\_logic_net: (unit_data_valid), line:69
|vpiName:unit_data_valid
|vpiFullName:work@fetch.unit_data_valid
|vpiNetType:36
|vpiNet:
\_logic_net: (unit_data_array), line:70
|vpiName:unit_data_array
|vpiFullName:work@fetch.unit_data_array
|vpiNetType:36
|vpiNet:
\_logic_net: (anded_unit_data_array), line:71
|vpiName:anded_unit_data_array
|vpiFullName:work@fetch.anded_unit_data_array
|vpiNetType:36
|vpiNet:
\_logic_net: (units_ready), line:73
|vpiName:units_ready
|vpiFullName:work@fetch.units_ready
|vpiNetType:36
|vpiNet:
\_logic_net: (units_data_valid), line:74
|vpiName:units_data_valid
|vpiFullName:work@fetch.units_data_valid
|vpiNetType:36
|vpiNet:
\_logic_net: (next_pc), line:76
|vpiName:next_pc
|vpiFullName:work@fetch.next_pc
|vpiNetType:36
|vpiNet:
\_logic_net: (pc), line:77
|vpiName:pc
|vpiFullName:work@fetch.pc
|vpiNetType:36
|vpiNet:
\_logic_net: (flush_or_rst), line:79
|vpiName:flush_or_rst
|vpiFullName:work@fetch.flush_or_rst
|vpiNetType:36
|vpiNet:
\_logic_net: (inflight_count), line:80
|vpiName:inflight_count
|vpiFullName:work@fetch.inflight_count
|vpiNetType:36
|vpiNet:
\_logic_net: (space_in_inst_buffer), line:82
|vpiName:space_in_inst_buffer
|vpiFullName:work@fetch.space_in_inst_buffer
|vpiNetType:36
|vpiNet:
\_logic_net: (new_mem_request), line:83
|vpiName:new_mem_request
|vpiFullName:work@fetch.new_mem_request
|vpiNetType:36
|vpiNet:
\_logic_net: (delayed_flush), line:86
|vpiName:delayed_flush
|vpiFullName:work@fetch.delayed_flush
|vpiNetType:36
|vpiNet:
\_logic_net: (stage2_phys_address), line:87
|vpiName:stage2_phys_address
|vpiFullName:work@fetch.stage2_phys_address
|vpiNetType:36
|vpiNet:
\_logic_net: (stage2_valid), line:88
|vpiName:stage2_valid
|vpiFullName:work@fetch.stage2_valid
|vpiNetType:36
|vpiNet:
\_logic_net: (bp), line:36
|vpiName:bp
|vpiFullName:work@fetch.bp
|vpiNet:
\_logic_net: (ras), line:37
|vpiName:ras
|vpiFullName:work@fetch.ras
|vpiNet:
\_logic_net: (tlb), line:39
|vpiName:tlb
|vpiFullName:work@fetch.tlb
|vpiNet:
\_logic_net: (instruction_bram), line:40
|vpiName:instruction_bram
|vpiFullName:work@fetch.instruction_bram
|vpiNet:
\_logic_net: (l1_request), line:42
|vpiName:l1_request
|vpiFullName:work@fetch.l1_request
|vpiNet:
\_logic_net: (l1_response), line:43
|vpiName:l1_response
|vpiFullName:work@fetch.l1_response
|vpiTypedef:
\_struct_typespec: (alu_inputs_t), line:301
|vpiTypedef:
\_enum_typespec: (alu_logic_op_t), line:84
|vpiTypedef:
\_enum_typespec: (alu_op_t), line:91
|vpiTypedef:
\_enum_typespec: (alu_rs1_op_t), line:97
|vpiTypedef:
\_enum_typespec: (alu_rs2_op_t), line:104
|vpiTypedef:
\_struct_typespec: (amo_alu_inputs_t), line:356
|vpiTypedef:
\_struct_typespec: (amo_details_t), line:362
|vpiTypedef:
\_enum_typespec: (amo_t), line:354
|vpiTypedef:
\_struct_typespec: (branch_inputs_t), line:313
|vpiTypedef:
\_logic_typespec: (branch_predictor_metadata_t), line:32
|vpiTypedef:
\_struct_typespec: (branch_results_t), line:330
|vpiTypedef:
\_enum_typespec: (bus_type_t), line:86
|vpiTypedef:
\_struct_typespec: (csr_inputs_t), line:396
|vpiTypedef:
\_enum_typespec: (csr_op_t), line:218
|vpiTypedef:
\_enum_typespec: (csr_t), line:201
|vpiTypedef:
\_struct_typespec: (data_access_shared_inputs_t), line:427
|vpiTypedef:
\_struct_typespec: (div_inputs_t), line:389
|vpiTypedef:
\_enum_typespec: (div_type), line:66
|vpiTypedef:
\_enum_typespec: (exception_code_t), line:245
|vpiTypedef:
\_struct_typespec: (exception_packet_t), line:263
|vpiTypedef:
\_struct_typespec: (fetch_buffer_packet_t), line:276
|vpiTypedef:
\_enum_typespec: (fifo_type_t), line:440
|vpiTypedef:
\_enum_typespec: (fn3_arith_t), line:76
|vpiTypedef:
\_enum_typespec: (fn3_branch_t), line:126
|vpiTypedef:
\_enum_typespec: (fn3_csr_t), line:212
|vpiTypedef:
\_enum_typespec: (fn3_ls_t), line:115
|vpiTypedef:
\_enum_typespec: (fn3_mul_div_t), line:138
|vpiTypedef:
\_struct_typespec: (gc_inputs_t), line:404
|vpiTypedef:
\_struct_typespec: (inflight_instruction_packet), line:271
|vpiTypedef:
\_logic_typespec: (instruction_id_t), line:30
|vpiTypedef:
\_enum_typespec: (interrupt_code_t), line:261
|vpiTypedef:
\_struct_typespec: (load_store_inputs_t), line:369
|vpiTypedef:
\_struct_typespec: (mul_inputs_t), line:383
|vpiTypedef:
\_enum_typespec: (opcodes_t), line:48
|vpiTypedef:
\_enum_typespec: (opcodes_trimmed_t), line:65
|vpiTypedef:
\_struct_typespec: (simulation_named_regfile), line:476
|vpiTypedef:
\_struct_typespec: (taiga_trace_events_t), line:442
|vpiTypedef:
\_struct_typespec: (to_l1_arbiter_packet), line:418
|vpiTypedef:
\_struct_typespec: (trace_outputs_t), line:469
|vpiTypedef:
\_logic_typespec: (unit_id_t), line:31
|vpiTypedef:
\_struct_typespec: (unit_writeback_t), line:295
|vpiTypedef:
\_enum_typespec: (vm_t), line:223
|vpiParamAssign:
\_param_assign: , line:55
|vpiRhs:
\_operation: , line:55
|vpiOpType:24
|vpiOperand:
\_ref_obj: (USE_I_SCRATCH_MEM), line:55
|vpiName:USE_I_SCRATCH_MEM
|vpiOperand:
\_ref_obj: (USE_ICACHE), line:55
|vpiName:USE_ICACHE
|vpiLhs:
\_parameter: (NUM_SUB_UNITS), line:55
|vpiName:NUM_SUB_UNITS
|vpiLocalParam:1
|vpiParamAssign:
\_param_assign: , line:56
|vpiRhs:
\_operation: , line:56
|vpiOpType:32
|vpiOperand:
\_operation: , line:56
|vpiOpType:14
|vpiOperand:
\_operation: , line:56
|vpiOpType:24
|vpiOperand:
\_ref_obj: (USE_I_SCRATCH_MEM), line:55
|vpiName:USE_I_SCRATCH_MEM
|vpiOperand:
\_ref_obj: (USE_ICACHE), line:55
|vpiName:USE_ICACHE
|vpiOperand:
\_constant: , line:56
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiOperand:
\_constant: , line:56
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiOperand:
\_sys_func_call: ($clog2), line:56
|vpiName:$clog2
|vpiArgument:
\_ref_obj: (NUM_SUB_UNITS), line:56
|vpiName:NUM_SUB_UNITS
|vpiLhs:
\_parameter: (NUM_SUB_UNITS_W), line:56
|vpiName:NUM_SUB_UNITS_W
|vpiLocalParam:1
|vpiParamAssign:
\_param_assign: , line:58
|vpiRhs:
\_constant: , line:58
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiLhs:
\_parameter: (BRAM_ID), line:58
|vpiName:BRAM_ID
|vpiLocalParam:1
|vpiParamAssign:
\_param_assign: , line:59
|vpiRhs:
\_ref_obj: (USE_I_SCRATCH_MEM), line:59
|vpiName:USE_I_SCRATCH_MEM
|vpiLhs:
\_parameter: (ICACHE_ID), line:59
|vpiName:ICACHE_ID
|vpiLocalParam:1
|vpiParamAssign:
\_param_assign: , line:61
|vpiRhs:
\_sys_func_call: ($clog2), line:61
|vpiName:$clog2
|vpiArgument:
\_ref_obj: (FETCH_BUFFER_DEPTH), line:61
|vpiName:FETCH_BUFFER_DEPTH
|vpiLhs:
\_parameter: (FETCH_BUFFER_DEPTH_W), line:61
|vpiName:FETCH_BUFFER_DEPTH_W
|vpiLocalParam:1
|vpiParamAssign:
\_param_assign: , line:62
|vpiRhs:
\_operation: , line:62
|vpiOpType:32
|vpiOperand:
\_ref_obj: (USE_ICACHE), line:62
|vpiName:USE_ICACHE
|vpiOperand:
\_constant: , line:62
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiOperand:
\_constant: , line:62
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiLhs:
\_parameter: (NEXT_ID_DEPTH), line:62
|vpiName:NEXT_ID_DEPTH
|vpiLocalParam:1
|vpiParameter:
\_parameter: (NUM_SUB_UNITS), line:55
|vpiParameter:
\_parameter: (NUM_SUB_UNITS_W), line:56
|vpiParameter:
\_parameter: (BRAM_ID), line:58
|vpiParameter:
\_parameter: (ICACHE_ID), line:59
|vpiParameter:
\_parameter: (FETCH_BUFFER_DEPTH_W), line:61
|vpiParameter:
\_parameter: (NEXT_ID_DEPTH), line:62
|uhdmallModules:
\_module: work@gc_unit, file:third_party/cores/taiga/core/gc_unit.sv, line:27, parent:work@div_unit_core_wrapper
|vpiDefName:work@gc_unit
|vpiFullName:work@gc_unit
|vpiProcess:
\_always: , line:181
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:181
|vpiCondition:
\_operation: , line:181
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:181
|vpiName:clk
|vpiFullName:work@gc_unit.clk
|vpiStmt:
\_begin: , line:181
|vpiFullName:work@gc_unit
|vpiStmt:
\_assignment: , line:182
|vpiOpType:82
|vpiLhs:
\_ref_obj: (gc_issue_hold), line:182
|vpiName:gc_issue_hold
|vpiFullName:work@gc_unit.gc_issue_hold
|vpiRhs:
\_operation: , line:182
|vpiOpType:27
|vpiOperand:
\_operation: , line:182
|vpiOpType:27
|vpiOperand:
\_operation: , line:182
|vpiOpType:27
|vpiOperand:
\_ref_obj: (issue.new_request), line:182
|vpiName:issue.new_request
|vpiFullName:work@gc_unit.issue.new_request
|vpiOperand:
\_ref_obj: (is_csr), line:182
|vpiName:is_csr
|vpiFullName:work@gc_unit.is_csr
|vpiOperand:
\_ref_obj: (processing_csr), line:182
|vpiName:processing_csr
|vpiFullName:work@gc_unit.processing_csr
|vpiOperand:
\_operation: , line:182
|vpiOpType:95
|vpiOperand:
\_ref_obj: (next_state), line:182
|vpiName:next_state
|vpiFullName:work@gc_unit.next_state
|vpiOperand:
\_ref_obj: (TLB_CLEAR_STATE), line:182
|vpiName:TLB_CLEAR_STATE
|vpiFullName:work@gc_unit.TLB_CLEAR_STATE
|vpiOperand:
\_ref_obj: (IQ_DRAIN), line:182
|vpiName:IQ_DRAIN
|vpiFullName:work@gc_unit.IQ_DRAIN
|vpiOperand:
\_ref_obj: (IQ_DISCARD), line:182
|vpiName:IQ_DISCARD
|vpiFullName:work@gc_unit.IQ_DISCARD
|vpiProcess:
\_always: , line:185
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:185
|vpiCondition:
\_operation: , line:185
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:185
|vpiName:clk
|vpiFullName:work@gc_unit.clk
|vpiStmt:
\_begin: , line:185
|vpiFullName:work@gc_unit
|vpiStmt:
\_assignment: , line:186
|vpiOpType:82
|vpiLhs:
\_ref_obj: (gc_issue_flush), line:186
|vpiName:gc_issue_flush
|vpiFullName:work@gc_unit.gc_issue_flush
|vpiRhs:
\_operation: , line:186
|vpiOpType:14
|vpiOperand:
\_ref_obj: (next_state), line:186
|vpiName:next_state
|vpiFullName:work@gc_unit.next_state
|vpiOperand:
\_ref_obj: (IQ_DISCARD), line:186
|vpiName:IQ_DISCARD
|vpiFullName:work@gc_unit.IQ_DISCARD
|vpiProcess:
\_always: , line:189
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:189
|vpiCondition:
\_operation: , line:189
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:189
|vpiName:clk
|vpiFullName:work@gc_unit.clk
|vpiStmt:
\_begin: , line:189
|vpiFullName:work@gc_unit
|vpiStmt:
\_assignment: , line:190
|vpiOpType:82
|vpiLhs:
\_ref_obj: (gc_supress_writeback), line:190
|vpiName:gc_supress_writeback
|vpiFullName:work@gc_unit.gc_supress_writeback
|vpiRhs:
\_operation: , line:190
|vpiOpType:32
|vpiOperand:
\_operation: , line:190
|vpiOpType:95
|vpiOperand:
\_ref_obj: (next_state), line:190
|vpiName:next_state
|vpiFullName:work@gc_unit.next_state
|vpiOperand:
\_ref_obj: (TLB_CLEAR_STATE), line:190
|vpiName:TLB_CLEAR_STATE
|vpiOperand:
\_ref_obj: (IQ_DISCARD), line:190
|vpiName:IQ_DISCARD
|vpiOperand:
\_constant: , line:190
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiOperand:
\_constant: , line:190
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiProcess:
\_always: , line:195
|vpiAlwaysType:1
|vpiStmt:
\_event_control: , line:195
|vpiCondition:
\_operation: , line:195
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:195
|vpiName:clk
|vpiFullName:work@gc_unit.clk
|vpiStmt:
\_begin: , line:195
|vpiFullName:work@gc_unit
|vpiStmt:
\_if_else: , line:196
|vpiCondition:
\_ref_obj: (rst), line:196
|vpiName:rst
|vpiFullName:work@gc_unit.rst
|vpiStmt:
\_assignment: , line:197
|vpiOpType:82
|vpiLhs:
\_ref_obj: (state), line:197
|vpiName:state
|vpiFullName:work@gc_unit.state
|vpiRhs:
\_ref_obj: (RST_STATE), line:197
|vpiName:RST_STATE
|vpiFullName:work@gc_unit.RST_STATE
|vpiElseStmt:
\_assignment: , line:199
|vpiOpType:82
|vpiLhs:
\_ref_obj: (state), line:199
|vpiName:state
|vpiFullName:work@gc_unit.state
|vpiRhs:
\_ref_obj: (next_state), line:199
|vpiName:next_state
|vpiFullName:work@gc_unit.next_state
|vpiProcess:
\_always: , line:202
|vpiAlwaysType:2
|vpiStmt:
\_begin: , line:202
|vpiFullName:work@gc_unit
|vpiStmt:
\_assignment: , line:203
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (next_state), line:203
|vpiName:next_state
|vpiFullName:work@gc_unit.next_state
|vpiRhs:
\_ref_obj: (state), line:203
|vpiName:state
|vpiFullName:work@gc_unit.state
|vpiStmt:
\_case_stmt: , line:204
|vpiCaseType:1
|vpiCondition:
\_ref_obj: (state), line:204
|vpiName:state
|vpiFullName:work@gc_unit.state
|vpiCaseItem:
\_case_item: , line:205
|vpiExpr:
\_ref_obj: (RST_STATE), line:205
|vpiName:RST_STATE
|vpiFullName:work@gc_unit.RST_STATE
|vpiStmt:
\_assignment: , line:205
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (next_state), line:205
|vpiName:next_state
|vpiFullName:work@gc_unit.next_state
|vpiRhs:
\_ref_obj: (IDLE_STATE), line:205
|vpiName:IDLE_STATE
|vpiFullName:work@gc_unit.IDLE_STATE
|vpiCaseItem:
\_case_item: , line:206
|vpiExpr:
\_ref_obj: (IDLE_STATE), line:206
|vpiName:IDLE_STATE
|vpiFullName:work@gc_unit.IDLE_STATE
|vpiStmt:
\_if_stmt: , line:206
|vpiCondition:
\_ref_obj: (ls_exception_valid), line:206
|vpiName:ls_exception_valid
|vpiFullName:work@gc_unit.ls_exception_valid
|vpiStmt:
\_assignment: , line:206
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (next_state), line:206
|vpiName:next_state
|vpiFullName:work@gc_unit.next_state
|vpiRhs:
\_ref_obj: (IQ_DISCARD), line:206
|vpiName:IQ_DISCARD
|vpiFullName:work@gc_unit.IQ_DISCARD
|vpiCaseItem:
\_case_item: , line:207
|vpiExpr:
\_ref_obj: (TLB_CLEAR_STATE), line:207
|vpiName:TLB_CLEAR_STATE
|vpiFullName:work@gc_unit.TLB_CLEAR_STATE
|vpiStmt:
\_if_stmt: , line:207
|vpiCondition:
\_ref_obj: (tlb_clear_done), line:207
|vpiName:tlb_clear_done
|vpiFullName:work@gc_unit.tlb_clear_done
|vpiStmt:
\_assignment: , line:207
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (next_state), line:207
|vpiName:next_state
|vpiFullName:work@gc_unit.next_state
|vpiRhs:
\_ref_obj: (IDLE_STATE), line:207
|vpiName:IDLE_STATE
|vpiFullName:work@gc_unit.IDLE_STATE
|vpiCaseItem:
\_case_item: , line:208
|vpiExpr:
\_ref_obj: (IQ_DRAIN), line:208
|vpiName:IQ_DRAIN
|vpiFullName:work@gc_unit.IQ_DRAIN
|vpiStmt:
\_if_stmt: , line:208
|vpiCondition:
\_operation: , line:208
|vpiOpType:14
|vpiOperand:
\_ref_obj: (ls_exception.id), line:208
|vpiName:ls_exception.id
|vpiFullName:work@gc_unit.ls_exception.id
|vpiOperand:
\_ref_obj: (oldest_id), line:208
|vpiName:oldest_id
|vpiFullName:work@gc_unit.oldest_id
|vpiStmt:
\_assignment: , line:208
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (next_state), line:208
|vpiName:next_state
|vpiFullName:work@gc_unit.next_state
|vpiRhs:
\_ref_obj: (IQ_DISCARD), line:208
|vpiName:IQ_DISCARD
|vpiFullName:work@gc_unit.IQ_DISCARD
|vpiCaseItem:
\_case_item: , line:209
|vpiExpr:
\_ref_obj: (IQ_DISCARD), line:209
|vpiName:IQ_DISCARD
|vpiFullName:work@gc_unit.IQ_DISCARD
|vpiStmt:
\_if_stmt: , line:209
|vpiCondition:
\_ref_obj: (instruction_queue_empty), line:209
|vpiName:instruction_queue_empty
|vpiFullName:work@gc_unit.instruction_queue_empty
|vpiStmt:
\_assignment: , line:209
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (next_state), line:209
|vpiName:next_state
|vpiFullName:work@gc_unit.next_state
|vpiRhs:
\_ref_obj: (IDLE_STATE), line:209
|vpiName:IDLE_STATE
|vpiFullName:work@gc_unit.IDLE_STATE
|vpiCaseItem:
\_case_item: , line:210
|vpiStmt:
\_assignment: , line:210
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (next_state), line:210
|vpiName:next_state
|vpiFullName:work@gc_unit.next_state
|vpiRhs:
\_ref_obj: (RST_STATE), line:210
|vpiName:RST_STATE
|vpiFullName:work@gc_unit.RST_STATE
|vpiProcess:
\_always: , line:223
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:223
|vpiCondition:
\_operation: , line:223
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:223
|vpiName:clk
|vpiFullName:work@gc_unit.clk
|vpiStmt:
\_begin: , line:223
|vpiFullName:work@gc_unit
|vpiStmt:
\_assignment: , line:224
|vpiOpType:82
|vpiLhs:
\_ref_obj: (ls_exception_second_cycle), line:224
|vpiName:ls_exception_second_cycle
|vpiFullName:work@gc_unit.ls_exception_second_cycle
|vpiRhs:
\_ref_obj: (ls_exception_first_cycle), line:224
|vpiName:ls_exception_first_cycle
|vpiFullName:work@gc_unit.ls_exception_first_cycle
|vpiProcess:
\_always: , line:227
|vpiAlwaysType:2
|vpiStmt:
\_begin: , line:227
|vpiFullName:work@gc_unit
|vpiStmt:
\_case_stmt: , line:228
|vpiCaseType:1
|vpiCondition:
\_ref_obj: (current_privilege), line:228
|vpiName:current_privilege
|vpiFullName:work@gc_unit.current_privilege
|vpiCaseItem:
\_case_item: , line:229
|vpiExpr:
\_ref_obj: (USER_PRIVILEGE), line:229
|vpiName:USER_PRIVILEGE
|vpiFullName:work@gc_unit.USER_PRIVILEGE
|vpiStmt:
\_assignment: , line:229
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (ecall_code), line:229
|vpiName:ecall_code
|vpiFullName:work@gc_unit.ecall_code
|vpiRhs:
\_ref_obj: (ECALL_U), line:229
|vpiName:ECALL_U
|vpiFullName:work@gc_unit.ECALL_U
|vpiCaseItem:
\_case_item: , line:230
|vpiExpr:
\_ref_obj: (SUPERVISOR_PRIVILEGE), line:230
|vpiName:SUPERVISOR_PRIVILEGE
|vpiFullName:work@gc_unit.SUPERVISOR_PRIVILEGE
|vpiStmt:
\_assignment: , line:230
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (ecall_code), line:230
|vpiName:ecall_code
|vpiFullName:work@gc_unit.ecall_code
|vpiRhs:
\_ref_obj: (ECALL_S), line:230
|vpiName:ECALL_S
|vpiFullName:work@gc_unit.ECALL_S
|vpiCaseItem:
\_case_item: , line:231
|vpiExpr:
\_ref_obj: (MACHINE_PRIVILEGE), line:231
|vpiName:MACHINE_PRIVILEGE
|vpiFullName:work@gc_unit.MACHINE_PRIVILEGE
|vpiStmt:
\_assignment: , line:231
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (ecall_code), line:231
|vpiName:ecall_code
|vpiFullName:work@gc_unit.ecall_code
|vpiRhs:
\_ref_obj: (ECALL_M), line:231
|vpiName:ECALL_M
|vpiFullName:work@gc_unit.ECALL_M
|vpiCaseItem:
\_case_item: , line:232
|vpiStmt:
\_assignment: , line:232
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (ecall_code), line:232
|vpiName:ecall_code
|vpiFullName:work@gc_unit.ecall_code
|vpiRhs:
\_ref_obj: (ECALL_U), line:232
|vpiName:ECALL_U
|vpiFullName:work@gc_unit.ECALL_U
|vpiProcess:
\_always: , line:243
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:243
|vpiCondition:
\_operation: , line:243
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:243
|vpiName:clk
|vpiFullName:work@gc_unit.clk
|vpiStmt:
\_begin: , line:243
|vpiFullName:work@gc_unit
|vpiStmt:
\_assignment: , line:244
|vpiOpType:82
|vpiLhs:
\_ref_obj: (second_cycle_flush), line:244
|vpiName:second_cycle_flush
|vpiFullName:work@gc_unit.second_cycle_flush
|vpiRhs:
\_ref_obj: (gc_flush_required), line:244
|vpiName:gc_flush_required
|vpiFullName:work@gc_unit.gc_flush_required
|vpiStmt:
\_assignment: , line:245
|vpiOpType:82
|vpiLhs:
\_ref_obj: (gc_fetch_pc_override), line:245
|vpiName:gc_fetch_pc_override
|vpiFullName:work@gc_unit.gc_fetch_pc_override
|vpiRhs:
\_operation: , line:245
|vpiOpType:29
|vpiOperand:
\_operation: , line:245
|vpiOpType:29
|vpiOperand:
\_ref_obj: (gc_flush_required), line:245
|vpiName:gc_flush_required
|vpiFullName:work@gc_unit.gc_flush_required
|vpiOperand:
\_ref_obj: (second_cycle_flush), line:245
|vpiName:second_cycle_flush
|vpiFullName:work@gc_unit.second_cycle_flush
|vpiOperand:
\_ref_obj: (ls_exception_first_cycle), line:245
|vpiName:ls_exception_first_cycle
|vpiFullName:work@gc_unit.ls_exception_first_cycle
|vpiStmt:
\_assignment: , line:246
|vpiOpType:82
|vpiLhs:
\_ref_obj: (gc_fetch_pc), line:246
|vpiName:gc_fetch_pc
|vpiFullName:work@gc_unit.gc_fetch_pc
|vpiRhs:
\_operation: , line:247
|vpiOpType:32
|vpiOperand:
\_operation: , line:247
|vpiOpType:32
|vpiOperand:
\_ref_obj: (gc_inputs.is_i_fence), line:247
|vpiName:gc_inputs.is_i_fence
|vpiFullName:work@gc_unit.gc_inputs.is_i_fence
|vpiOperand:
\_operation: , line:247
|vpiOpType:24
|vpiOperand:
\_ref_obj: (gc_inputs.pc), line:247
|vpiName:gc_inputs.pc
|vpiFullName:work@gc_unit.gc_inputs.pc
|vpiOperand:
\_constant: , line:247
|vpiConstType:7
|vpiDecompile:4
|vpiSize:32
|INT:4
|vpiOperand:
\_ref_obj: (gc_inputs.is_ret), line:248
|vpiName:gc_inputs.is_ret
|vpiFullName:work@gc_unit.gc_inputs.is_ret
|vpiOperand:
\_ref_obj: (csr_mepc), line:248
|vpiName:csr_mepc
|vpiFullName:work@gc_unit.csr_mepc
|vpiOperand:
\_ref_obj: (trap_pc), line:249
|vpiName:trap_pc
|vpiFullName:work@gc_unit.trap_pc
|vpiProcess:
\_always: , line:269
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:269
|vpiCondition:
\_operation: , line:269
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:269
|vpiName:clk
|vpiFullName:work@gc_unit.clk
|vpiStmt:
\_begin: , line:269
|vpiFullName:work@gc_unit
|vpiStmt:
\_if_else: , line:270
|vpiCondition:
\_ref_obj: (rst), line:270
|vpiName:rst
|vpiFullName:work@gc_unit.rst
|vpiStmt:
\_assignment: , line:271
|vpiOpType:82
|vpiLhs:
\_ref_obj: (processing_csr), line:271
|vpiName:processing_csr
|vpiFullName:work@gc_unit.processing_csr
|vpiRhs:
\_constant: , line:271
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiElseStmt:
\_if_else: , line:272
|vpiCondition:
\_ref_obj: (csr_ready_to_complete), line:272
|vpiName:csr_ready_to_complete
|vpiFullName:work@gc_unit.csr_ready_to_complete
|vpiStmt:
\_assignment: , line:273
|vpiOpType:82
|vpiLhs:
\_ref_obj: (processing_csr), line:273
|vpiName:processing_csr
|vpiFullName:work@gc_unit.processing_csr
|vpiRhs:
\_constant: , line:273
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiElseStmt:
\_if_stmt: , line:274
|vpiCondition:
\_ref_obj: (is_csr), line:274
|vpiName:is_csr
|vpiFullName:work@gc_unit.is_csr
|vpiStmt:
\_assignment: , line:275
|vpiOpType:82
|vpiLhs:
\_ref_obj: (processing_csr), line:275
|vpiName:processing_csr
|vpiFullName:work@gc_unit.processing_csr
|vpiRhs:
\_constant: , line:275
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiProcess:
\_always: , line:279
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:279
|vpiCondition:
\_operation: , line:279
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:279
|vpiName:clk
|vpiFullName:work@gc_unit.clk
|vpiStmt:
\_begin: , line:279
|vpiFullName:work@gc_unit
|vpiStmt:
\_assignment: , line:280
|vpiOpType:82
|vpiLhs:
\_ref_obj: (csr_ready_to_complete_r), line:280
|vpiName:csr_ready_to_complete_r
|vpiFullName:work@gc_unit.csr_ready_to_complete_r
|vpiRhs:
\_ref_obj: (csr_ready_to_complete), line:280
|vpiName:csr_ready_to_complete
|vpiFullName:work@gc_unit.csr_ready_to_complete
|vpiStmt:
\_assignment: , line:281
|vpiOpType:82
|vpiLhs:
\_ref_obj: (csr_id), line:281
|vpiName:csr_id
|vpiFullName:work@gc_unit.csr_id
|vpiRhs:
\_ref_obj: (instruction_id), line:281
|vpiName:instruction_id
|vpiFullName:work@gc_unit.instruction_id
|vpiStmt:
\_if_stmt: , line:282
|vpiCondition:
\_ref_obj: (issue.new_request), line:282
|vpiName:issue.new_request
|vpiFullName:work@gc_unit.issue.new_request
|vpiStmt:
\_begin: , line:282
|vpiFullName:work@gc_unit
|vpiStmt:
\_assignment: , line:283
|vpiOpType:82
|vpiLhs:
\_ref_obj: (instruction_id), line:283
|vpiName:instruction_id
|vpiFullName:work@gc_unit.instruction_id
|vpiRhs:
\_ref_obj: (issue.instruction_id), line:283
|vpiName:issue.instruction_id
|vpiFullName:work@gc_unit.issue.instruction_id
|vpiPort:
\_port: (clk), line:28
|vpiName:clk
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (clk), line:28
|vpiName:clk
|vpiFullName:work@gc_unit.clk
|vpiNetType:36
|vpiPort:
\_port: (rst), line:29
|vpiName:rst
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (rst), line:29
|vpiName:rst
|vpiFullName:work@gc_unit.rst
|vpiNetType:36
|vpiPort:
\_port: (issue), line:33
|vpiName:issue
|vpiDirection:5
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_modport: (unit)
|vpiPort:
\_port: (gc_inputs), line:34
|vpiName:gc_inputs
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (gc_inputs), line:34
|vpiName:gc_inputs
|vpiFullName:work@gc_unit.gc_inputs
|vpiPort:
\_port: (instruction_issued_no_rd), line:35
|vpiName:instruction_issued_no_rd
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (instruction_issued_no_rd), line:35
|vpiName:instruction_issued_no_rd
|vpiFullName:work@gc_unit.instruction_issued_no_rd
|vpiNetType:36
|vpiPort:
\_port: (gc_flush_required), line:36
|vpiName:gc_flush_required
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (gc_flush_required), line:36
|vpiName:gc_flush_required
|vpiFullName:work@gc_unit.gc_flush_required
|vpiNetType:36
|vpiPort:
\_port: (branch_flush), line:38
|vpiName:branch_flush
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (branch_flush), line:38
|vpiName:branch_flush
|vpiFullName:work@gc_unit.branch_flush
|vpiNetType:36
|vpiPort:
\_port: (ls_exception), line:41
|vpiName:ls_exception
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (ls_exception), line:41
|vpiName:ls_exception
|vpiFullName:work@gc_unit.ls_exception
|vpiPort:
\_port: (ls_exception_valid), line:42
|vpiName:ls_exception_valid
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (ls_exception_valid), line:42
|vpiName:ls_exception_valid
|vpiFullName:work@gc_unit.ls_exception_valid
|vpiNetType:36
|vpiPort:
\_port: (tlb_on), line:45
|vpiName:tlb_on
|vpiDirection:2
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (tlb_on), line:45
|vpiName:tlb_on
|vpiFullName:work@gc_unit.tlb_on
|vpiNetType:36
|vpiPort:
\_port: (asid), line:46
|vpiName:asid
|vpiDirection:2
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (asid), line:46
|vpiName:asid
|vpiFullName:work@gc_unit.asid
|vpiNetType:36
|vpiPort:
\_port: (immu), line:49
|vpiName:immu
|vpiDirection:5
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_modport: (csr)
|vpiPort:
\_port: (dmmu), line:50
|vpiName:dmmu
|vpiDirection:5
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_modport: (csr)
|vpiPort:
\_port: (instruction_complete), line:53
|vpiName:instruction_complete
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (instruction_complete), line:53
|vpiName:instruction_complete
|vpiFullName:work@gc_unit.instruction_complete
|vpiNetType:36
|vpiPort:
\_port: (instruction_queue_empty), line:54
|vpiName:instruction_queue_empty
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (instruction_queue_empty), line:54
|vpiName:instruction_queue_empty
|vpiFullName:work@gc_unit.instruction_queue_empty
|vpiNetType:36
|vpiPort:
\_port: (oldest_id), line:55
|vpiName:oldest_id
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (oldest_id), line:55
|vpiName:oldest_id
|vpiFullName:work@gc_unit.oldest_id
|vpiPort:
\_port: (interrupt), line:59
|vpiName:interrupt
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (interrupt), line:59
|vpiName:interrupt
|vpiFullName:work@gc_unit.interrupt
|vpiNetType:36
|vpiPort:
\_port: (timer_interrupt), line:60
|vpiName:timer_interrupt
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (timer_interrupt), line:60
|vpiName:timer_interrupt
|vpiFullName:work@gc_unit.timer_interrupt
|vpiNetType:36
|vpiPort:
\_port: (gc_issue_hold), line:63
|vpiName:gc_issue_hold
|vpiDirection:2
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (gc_issue_hold), line:63
|vpiName:gc_issue_hold
|vpiFullName:work@gc_unit.gc_issue_hold
|vpiNetType:36
|vpiPort:
\_port: (gc_issue_flush), line:64
|vpiName:gc_issue_flush
|vpiDirection:2
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (gc_issue_flush), line:64
|vpiName:gc_issue_flush
|vpiFullName:work@gc_unit.gc_issue_flush
|vpiNetType:36
|vpiPort:
\_port: (gc_fetch_flush), line:65
|vpiName:gc_fetch_flush
|vpiDirection:2
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (gc_fetch_flush), line:65
|vpiName:gc_fetch_flush
|vpiFullName:work@gc_unit.gc_fetch_flush
|vpiNetType:36
|vpiPort:
\_port: (gc_fetch_pc_override), line:66
|vpiName:gc_fetch_pc_override
|vpiDirection:2
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (gc_fetch_pc_override), line:66
|vpiName:gc_fetch_pc_override
|vpiFullName:work@gc_unit.gc_fetch_pc_override
|vpiNetType:36
|vpiPort:
\_port: (gc_supress_writeback), line:67
|vpiName:gc_supress_writeback
|vpiDirection:2
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (gc_supress_writeback), line:67
|vpiName:gc_supress_writeback
|vpiFullName:work@gc_unit.gc_supress_writeback
|vpiNetType:36
|vpiPort:
\_port: (gc_fetch_pc), line:69
|vpiName:gc_fetch_pc
|vpiDirection:2
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (gc_fetch_pc), line:69
|vpiName:gc_fetch_pc
|vpiFullName:work@gc_unit.gc_fetch_pc
|vpiNetType:36
|vpiPort:
\_port: (csr_rd), line:72
|vpiName:csr_rd
|vpiDirection:2
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (csr_rd), line:72
|vpiName:csr_rd
|vpiFullName:work@gc_unit.csr_rd
|vpiNetType:36
|vpiPort:
\_port: (csr_id), line:73
|vpiName:csr_id
|vpiDirection:2
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (csr_id), line:73
|vpiName:csr_id
|vpiFullName:work@gc_unit.csr_id
|vpiPort:
\_port: (csr_done), line:74
|vpiName:csr_done
|vpiDirection:2
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (csr_done), line:74
|vpiName:csr_done
|vpiFullName:work@gc_unit.csr_done
|vpiNetType:36
|vpiContAssign:
\_cont_assign: , line:170
|vpiRhs:
\_ref_obj: (gc_inputs.instruction), line:170
|vpiName:gc_inputs.instruction
|vpiFullName:work@gc_unit.gc_inputs.instruction
|vpiLhs:
\_ref_obj: (opcode), line:170
|vpiName:opcode
|vpiFullName:work@gc_unit.opcode
|vpiContAssign:
\_cont_assign: , line:171
|vpiRhs:
\_part_select: , line:171, parent:opcode
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (opcode)
|vpiLeftRange:
\_constant: , line:171
|vpiConstType:7
|vpiDecompile:6
|vpiSize:32
|INT:6
|vpiRightRange:
\_constant: , line:171
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiLhs:
\_ref_obj: (opcode_trim), line:171
|vpiName:opcode_trim
|vpiFullName:work@gc_unit.opcode_trim
|vpiContAssign:
\_cont_assign: , line:172
|vpiRhs:
\_ref_obj: (gc_inputs.instruction), line:172
|vpiName:gc_inputs.instruction
|vpiFullName:work@gc_unit.gc_inputs.instruction
|vpiLhs:
\_ref_obj: (fn3), line:172
|vpiName:fn3
|vpiFullName:work@gc_unit.fn3
|vpiContAssign:
\_cont_assign: , line:173
|vpiRhs:
\_ref_obj: (gc_inputs.instruction), line:173
|vpiName:gc_inputs.instruction
|vpiFullName:work@gc_unit.gc_inputs.instruction
|vpiLhs:
\_ref_obj: (rs1_addr), line:173
|vpiName:rs1_addr
|vpiFullName:work@gc_unit.rs1_addr
|vpiContAssign:
\_cont_assign: , line:177
|vpiRhs:
\_operation: , line:177
|vpiOpType:28
|vpiOperand:
\_ref_obj: (issue.new_request_r), line:177
|vpiName:issue.new_request_r
|vpiFullName:work@gc_unit.issue.new_request_r
|vpiOperand:
\_ref_obj: (gc_inputs.is_csr), line:177
|vpiName:gc_inputs.is_csr
|vpiFullName:work@gc_unit.gc_inputs.is_csr
|vpiLhs:
\_ref_obj: (is_csr), line:177
|vpiName:is_csr
|vpiFullName:work@gc_unit.is_csr
|vpiContAssign:
\_cont_assign: , line:179
|vpiRhs:
\_operation: , line:179
|vpiOpType:29
|vpiOperand:
\_ref_obj: (branch_flush), line:179
|vpiName:branch_flush
|vpiFullName:work@gc_unit.branch_flush
|vpiOperand:
\_ref_obj: (gc_fetch_pc_override), line:179
|vpiName:gc_fetch_pc_override
|vpiFullName:work@gc_unit.gc_fetch_pc_override
|vpiLhs:
\_ref_obj: (gc_fetch_flush), line:179
|vpiName:gc_fetch_flush
|vpiFullName:work@gc_unit.gc_fetch_flush
|vpiContAssign:
\_cont_assign: , line:222
|vpiRhs:
\_ref_obj: (ls_exception_valid), line:222
|vpiName:ls_exception_valid
|vpiFullName:work@gc_unit.ls_exception_valid
|vpiLhs:
\_ref_obj: (ls_exception_first_cycle), line:222
|vpiName:ls_exception_first_cycle
|vpiFullName:work@gc_unit.ls_exception_first_cycle
|vpiContAssign:
\_cont_assign: , line:236
|vpiRhs:
\_operation: , line:237
|vpiOpType:32
|vpiOperand:
\_operation: , line:237
|vpiOpType:32
|vpiOperand:
\_ref_obj: (ls_exception_second_cycle), line:237
|vpiName:ls_exception_second_cycle
|vpiFullName:work@gc_unit.ls_exception_second_cycle
|vpiOperand:
\_ref_obj: (ls_exception.code), line:237
|vpiName:ls_exception.code
|vpiFullName:work@gc_unit.ls_exception.code
|vpiOperand:
\_ref_obj: (gc_inputs.is_ecall), line:238
|vpiName:gc_inputs.is_ecall
|vpiFullName:work@gc_unit.gc_inputs.is_ecall
|vpiOperand:
\_ref_obj: (ecall_code), line:238
|vpiName:ecall_code
|vpiFullName:work@gc_unit.ecall_code
|vpiOperand:
\_ref_obj: (BREAK), line:238
|vpiName:BREAK
|vpiFullName:work@gc_unit.BREAK
|vpiLhs:
\_ref_obj: (gc_exception.code), line:236
|vpiName:gc_exception.code
|vpiFullName:work@gc_unit.gc_exception.code
|vpiContAssign:
\_cont_assign: , line:239
|vpiRhs:
\_operation: , line:239
|vpiOpType:32
|vpiOperand:
\_ref_obj: (ls_exception_second_cycle), line:239
|vpiName:ls_exception_second_cycle
|vpiFullName:work@gc_unit.ls_exception_second_cycle
|vpiOperand:
\_ref_obj: (ls_exception.pc), line:239
|vpiName:ls_exception.pc
|vpiFullName:work@gc_unit.ls_exception.pc
|vpiOperand:
\_ref_obj: (gc_inputs.pc), line:239
|vpiName:gc_inputs.pc
|vpiFullName:work@gc_unit.gc_inputs.pc
|vpiLhs:
\_ref_obj: (gc_exception.pc), line:239
|vpiName:gc_exception.pc
|vpiFullName:work@gc_unit.gc_exception.pc
|vpiContAssign:
\_cont_assign: , line:240
|vpiRhs:
\_operation: , line:240
|vpiOpType:32
|vpiOperand:
\_ref_obj: (ls_exception_second_cycle), line:240
|vpiName:ls_exception_second_cycle
|vpiFullName:work@gc_unit.ls_exception_second_cycle
|vpiOperand:
\_ref_obj: (ls_exception.tval), line:240
|vpiName:ls_exception.tval
|vpiFullName:work@gc_unit.ls_exception.tval
|vpiOperand:
\_constant: , line:240
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiLhs:
\_ref_obj: (gc_exception.tval), line:240
|vpiName:gc_exception.tval
|vpiFullName:work@gc_unit.gc_exception.tval
|vpiContAssign:
\_cont_assign: , line:241
|vpiRhs:
\_operation: , line:241
|vpiOpType:29
|vpiOperand:
\_operation: , line:241
|vpiOpType:29
|vpiOperand:
\_ref_obj: (gc_inputs.is_ecall), line:241
|vpiName:gc_inputs.is_ecall
|vpiFullName:work@gc_unit.gc_inputs.is_ecall
|vpiOperand:
\_ref_obj: (gc_inputs.is_ebreak), line:241
|vpiName:gc_inputs.is_ebreak
|vpiFullName:work@gc_unit.gc_inputs.is_ebreak
|vpiOperand:
\_ref_obj: (ls_exception_second_cycle), line:241
|vpiName:ls_exception_second_cycle
|vpiFullName:work@gc_unit.ls_exception_second_cycle
|vpiLhs:
\_ref_obj: (gc_exception.valid), line:241
|vpiName:gc_exception.valid
|vpiFullName:work@gc_unit.gc_exception.valid
|vpiContAssign:
\_cont_assign: , line:254
|vpiRhs:
\_operation: , line:254
|vpiOpType:32
|vpiOperand:
\_bit_select: (fn3), line:254
|vpiName:fn3
|vpiFullName:work@gc_unit.fn3
|vpiIndex:
\_constant: , line:254
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiOperand:
\_operation: , line:254
|vpiOpType:33
|vpiOperand:
\_constant: , line:254
|vpiConstType:3
|vpiDecompile:27'b0
|vpiSize:27
|BIN:27'b0
|vpiOperand:
\_ref_obj: (rs1_addr), line:254
|vpiName:rs1_addr
|vpiFullName:work@gc_unit.rs1_addr
|vpiOperand:
\_ref_obj: (gc_inputs.rs1), line:254
|vpiName:gc_inputs.rs1
|vpiFullName:work@gc_unit.gc_inputs.rs1
|vpiLhs:
\_ref_obj: (csr_inputs.rs1), line:254
|vpiName:csr_inputs.rs1
|vpiFullName:work@gc_unit.csr_inputs.rs1
|vpiContAssign:
\_cont_assign: , line:255
|vpiRhs:
\_ref_obj: (gc_inputs.instruction), line:255
|vpiName:gc_inputs.instruction
|vpiFullName:work@gc_unit.gc_inputs.instruction
|vpiLhs:
\_ref_obj: (csr_inputs.csr_addr), line:255
|vpiName:csr_inputs.csr_addr
|vpiFullName:work@gc_unit.csr_inputs.csr_addr
|vpiContAssign:
\_cont_assign: , line:256
|vpiRhs:
\_part_select: , line:256, parent:fn3
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (fn3)
|vpiLeftRange:
\_constant: , line:256
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:256
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiLhs:
\_ref_obj: (csr_inputs.csr_op), line:256
|vpiName:csr_inputs.csr_op
|vpiFullName:work@gc_unit.csr_inputs.csr_op
|vpiContAssign:
\_cont_assign: , line:257
|vpiRhs:
\_operation: , line:257
|vpiOpType:14
|vpiOperand:
\_ref_obj: (rs1_addr), line:257
|vpiName:rs1_addr
|vpiFullName:work@gc_unit.rs1_addr
|vpiOperand:
\_constant: , line:257
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiLhs:
\_ref_obj: (csr_inputs.rs1_is_zero), line:257
|vpiName:csr_inputs.rs1_is_zero
|vpiFullName:work@gc_unit.csr_inputs.rs1_is_zero
|vpiContAssign:
\_cont_assign: , line:258
|vpiRhs:
\_ref_obj: (gc_inputs.rd_is_zero), line:258
|vpiName:gc_inputs.rd_is_zero
|vpiFullName:work@gc_unit.gc_inputs.rd_is_zero
|vpiLhs:
\_ref_obj: (csr_inputs.rd_is_zero), line:258
|vpiName:csr_inputs.rd_is_zero
|vpiFullName:work@gc_unit.csr_inputs.rd_is_zero
|vpiContAssign:
\_cont_assign: , line:267
|vpiRhs:
\_constant: , line:267
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiLhs:
\_ref_obj: (issue.ready), line:267
|vpiName:issue.ready
|vpiFullName:work@gc_unit.issue.ready
|vpiContAssign:
\_cont_assign: , line:278
|vpiRhs:
\_operation: , line:278
|vpiOpType:26
|vpiOperand:
\_operation: , line:278
|vpiOpType:29
|vpiOperand:
\_ref_obj: (is_csr), line:278
|vpiName:is_csr
|vpiFullName:work@gc_unit.is_csr
|vpiOperand:
\_ref_obj: (processing_csr), line:278
|vpiName:processing_csr
|vpiFullName:work@gc_unit.processing_csr
|vpiOperand:
\_operation: , line:278
|vpiOpType:14
|vpiOperand:
\_ref_obj: (oldest_id), line:278
|vpiName:oldest_id
|vpiFullName:work@gc_unit.oldest_id
|vpiOperand:
\_ref_obj: (csr_id), line:278
|vpiName:csr_id
|vpiFullName:work@gc_unit.csr_id
|vpiLhs:
\_ref_obj: (csr_ready_to_complete), line:278
|vpiName:csr_ready_to_complete
|vpiFullName:work@gc_unit.csr_ready_to_complete
|vpiContAssign:
\_cont_assign: , line:287
|vpiRhs:
\_ref_obj: (csr_ready_to_complete_r), line:287
|vpiName:csr_ready_to_complete_r
|vpiFullName:work@gc_unit.csr_ready_to_complete_r
|vpiLhs:
\_ref_obj: (csr_done), line:287
|vpiName:csr_done
|vpiFullName:work@gc_unit.csr_done
|vpiContAssign:
\_cont_assign: , line:288
|vpiRhs:
\_ref_obj: (wb_csr), line:288
|vpiName:wb_csr
|vpiFullName:work@gc_unit.wb_csr
|vpiLhs:
\_ref_obj: (csr_rd), line:288
|vpiName:csr_rd
|vpiFullName:work@gc_unit.csr_rd
|vpiNet:
\_logic_net: (clk), line:28
|vpiNet:
\_logic_net: (rst), line:29
|vpiNet:
\_logic_net: (gc_inputs), line:34
|vpiNet:
\_logic_net: (instruction_issued_no_rd), line:35
|vpiNet:
\_logic_net: (gc_flush_required), line:36
|vpiNet:
\_logic_net: (branch_flush), line:38
|vpiNet:
\_logic_net: (ls_exception), line:41
|vpiNet:
\_logic_net: (ls_exception_valid), line:42
|vpiNet:
\_logic_net: (tlb_on), line:45
|vpiNet:
\_logic_net: (asid), line:46
|vpiNet:
\_logic_net: (instruction_complete), line:53
|vpiNet:
\_logic_net: (instruction_queue_empty), line:54
|vpiNet:
\_logic_net: (oldest_id), line:55
|vpiNet:
\_logic_net: (interrupt), line:59
|vpiNet:
\_logic_net: (timer_interrupt), line:60
|vpiNet:
\_logic_net: (gc_issue_hold), line:63
|vpiNet:
\_logic_net: (gc_issue_flush), line:64
|vpiNet:
\_logic_net: (gc_fetch_flush), line:65
|vpiNet:
\_logic_net: (gc_fetch_pc_override), line:66
|vpiNet:
\_logic_net: (gc_supress_writeback), line:67
|vpiNet:
\_logic_net: (gc_fetch_pc), line:69
|vpiNet:
\_logic_net: (csr_rd), line:72
|vpiNet:
\_logic_net: (csr_id), line:73
|vpiNet:
\_logic_net: (csr_done), line:74
|vpiNet:
\_logic_net: (state), line:130
|vpiName:state
|vpiFullName:work@gc_unit.state
|vpiNet:
\_logic_net: (next_state), line:131
|vpiName:next_state
|vpiFullName:work@gc_unit.next_state
|vpiNet:
\_logic_net: (tlb_clear_done), line:133
|vpiName:tlb_clear_done
|vpiFullName:work@gc_unit.tlb_clear_done
|vpiNetType:36
|vpiNet:
\_logic_net: (i_fence_flush), line:135
|vpiName:i_fence_flush
|vpiFullName:work@gc_unit.i_fence_flush
|vpiNetType:36
|vpiNet:
\_logic_net: (ecall_code), line:136
|vpiName:ecall_code
|vpiFullName:work@gc_unit.ecall_code
|vpiNet:
\_logic_net: (second_cycle_flush), line:137
|vpiName:second_cycle_flush
|vpiFullName:work@gc_unit.second_cycle_flush
|vpiNetType:36
|vpiNet:
\_logic_net: (mret), line:140
|vpiName:mret
|vpiFullName:work@gc_unit.mret
|vpiNetType:36
|vpiNet:
\_logic_net: (sret), line:141
|vpiName:sret
|vpiFullName:work@gc_unit.sret
|vpiNetType:36
|vpiNet:
\_logic_net: (wb_csr), line:142
|vpiName:wb_csr
|vpiFullName:work@gc_unit.wb_csr
|vpiNetType:36
|vpiNet:
\_logic_net: (csr_inputs), line:143
|vpiName:csr_inputs
|vpiFullName:work@gc_unit.csr_inputs
|vpiNet:
\_logic_net: (gc_exception), line:144
|vpiName:gc_exception
|vpiFullName:work@gc_unit.gc_exception
|vpiNet:
\_logic_net: (csr_exception), line:145
|vpiName:csr_exception
|vpiFullName:work@gc_unit.csr_exception
|vpiNet:
\_logic_net: (current_privilege), line:146
|vpiName:current_privilege
|vpiFullName:work@gc_unit.current_privilege
|vpiNetType:36
|vpiNet:
\_logic_net: (trap_pc), line:147
|vpiName:trap_pc
|vpiFullName:work@gc_unit.trap_pc
|vpiNetType:36
|vpiNet:
\_logic_net: (csr_mepc), line:148
|vpiName:csr_mepc
|vpiFullName:work@gc_unit.csr_mepc
|vpiNetType:36
|vpiNet:
\_logic_net: (csr_sepc), line:149
|vpiName:csr_sepc
|vpiFullName:work@gc_unit.csr_sepc
|vpiNetType:36
|vpiNet:
\_logic_net: (fn3), line:152
|vpiName:fn3
|vpiFullName:work@gc_unit.fn3
|vpiNetType:36
|vpiNet:
\_logic_net: (opcode), line:153
|vpiName:opcode
|vpiFullName:work@gc_unit.opcode
|vpiNetType:36
|vpiNet:
\_logic_net: (opcode_trim), line:154
|vpiName:opcode_trim
|vpiFullName:work@gc_unit.opcode_trim
|vpiNetType:36
|vpiNet:
\_logic_net: (rs1_addr), line:156
|vpiName:rs1_addr
|vpiFullName:work@gc_unit.rs1_addr
|vpiNetType:36
|vpiNet:
\_logic_net: (rs2_addr), line:157
|vpiName:rs2_addr
|vpiFullName:work@gc_unit.rs2_addr
|vpiNetType:36
|vpiNet:
\_logic_net: (future_rd_addr), line:158
|vpiName:future_rd_addr
|vpiFullName:work@gc_unit.future_rd_addr
|vpiNetType:36
|vpiNet:
\_logic_net: (is_csr), line:160
|vpiName:is_csr
|vpiFullName:work@gc_unit.is_csr
|vpiNetType:36
|vpiNet:
\_logic_net: (processing_csr), line:161
|vpiName:processing_csr
|vpiFullName:work@gc_unit.processing_csr
|vpiNetType:36
|vpiNet:
\_logic_net: (csr_ready_to_complete), line:162
|vpiName:csr_ready_to_complete
|vpiFullName:work@gc_unit.csr_ready_to_complete
|vpiNetType:36
|vpiNet:
\_logic_net: (csr_ready_to_complete_r), line:163
|vpiName:csr_ready_to_complete_r
|vpiFullName:work@gc_unit.csr_ready_to_complete_r
|vpiNetType:36
|vpiNet:
\_logic_net: (instruction_id), line:164
|vpiName:instruction_id
|vpiFullName:work@gc_unit.instruction_id
|vpiNet:
\_logic_net: (ls_exception_first_cycle), line:219
|vpiName:ls_exception_first_cycle
|vpiFullName:work@gc_unit.ls_exception_first_cycle
|vpiNetType:36
|vpiNet:
\_logic_net: (ls_exception_second_cycle), line:220
|vpiName:ls_exception_second_cycle
|vpiFullName:work@gc_unit.ls_exception_second_cycle
|vpiNetType:36
|vpiNet:
\_logic_net: (issue), line:33
|vpiName:issue
|vpiFullName:work@gc_unit.issue
|vpiNet:
\_logic_net: (immu), line:49
|vpiName:immu
|vpiFullName:work@gc_unit.immu
|vpiNet:
\_logic_net: (dmmu), line:50
|vpiName:dmmu
|vpiFullName:work@gc_unit.dmmu
|vpiTypedef:
\_struct_typespec: (alu_inputs_t), line:301
|vpiTypedef:
\_enum_typespec: (alu_logic_op_t), line:84
|vpiTypedef:
\_enum_typespec: (alu_op_t), line:91
|vpiTypedef:
\_enum_typespec: (alu_rs1_op_t), line:97
|vpiTypedef:
\_enum_typespec: (alu_rs2_op_t), line:104
|vpiTypedef:
\_struct_typespec: (amo_alu_inputs_t), line:356
|vpiTypedef:
\_struct_typespec: (amo_details_t), line:362
|vpiTypedef:
\_enum_typespec: (amo_t), line:354
|vpiTypedef:
\_struct_typespec: (branch_inputs_t), line:313
|vpiTypedef:
\_logic_typespec: (branch_predictor_metadata_t), line:32
|vpiTypedef:
\_struct_typespec: (branch_results_t), line:330
|vpiTypedef:
\_enum_typespec: (bus_type_t), line:86
|vpiTypedef:
\_struct_typespec: (csr_addr_t), line:37
|vpiTypedef:
\_struct_typespec: (csr_inputs_t), line:396
|vpiTypedef:
\_enum_typespec: (csr_op_t), line:218
|vpiTypedef:
\_enum_typespec: (csr_t), line:201
|vpiTypedef:
\_struct_typespec: (data_access_shared_inputs_t), line:427
|vpiTypedef:
\_struct_typespec: (div_inputs_t), line:389
|vpiTypedef:
\_enum_typespec: (div_type), line:66
|vpiTypedef:
\_enum_typespec: (exception_code_t), line:245
|vpiTypedef:
\_struct_typespec: (exception_packet_t), line:263
|vpiTypedef:
\_struct_typespec: (fetch_buffer_packet_t), line:276
|vpiTypedef:
\_enum_typespec: (fifo_type_t), line:440
|vpiTypedef:
\_enum_typespec: (fn3_arith_t), line:76
|vpiTypedef:
\_enum_typespec: (fn3_branch_t), line:126
|vpiTypedef:
\_enum_typespec: (fn3_csr_t), line:212
|vpiTypedef:
\_enum_typespec: (fn3_ls_t), line:115
|vpiTypedef:
\_enum_typespec: (fn3_mul_div_t), line:138
|vpiTypedef:
\_struct_typespec: (gc_inputs_t), line:404
|vpiTypedef:
\_enum_typespec: (gc_state), line:129
|vpiName:gc_state
|vpiEnumConst:
\_enum_const: (IDLE_STATE), line:129
|vpiName:IDLE_STATE
|INT:1
|vpiEnumConst:
\_enum_const: (IQ_DISCARD), line:129
|vpiName:IQ_DISCARD
|INT:4
|vpiEnumConst:
\_enum_const: (IQ_DRAIN), line:129
|vpiName:IQ_DRAIN
|INT:3
|vpiEnumConst:
\_enum_const: (RST_STATE), line:129
|vpiName:RST_STATE
|INT:0
|vpiEnumConst:
\_enum_const: (TLB_CLEAR_STATE), line:129
|vpiName:TLB_CLEAR_STATE
|INT:2
|vpiTypedef:
\_struct_typespec: (inflight_instruction_packet), line:271
|vpiTypedef:
\_logic_typespec: (instruction_id_t), line:30
|vpiTypedef:
\_enum_typespec: (interrupt_code_t), line:261
|vpiTypedef:
\_struct_typespec: (load_store_inputs_t), line:369
|vpiTypedef:
\_struct_typespec: (mcause_t), line:135
|vpiTypedef:
\_struct_typespec: (mie_t), line:119
|vpiTypedef:
\_struct_typespec: (mip_t), line:103
|vpiTypedef:
\_struct_typespec: (misa_t), line:45
|vpiTypedef:
\_struct_typespec: (mstatus_t), line:78
|vpiTypedef:
\_struct_typespec: (mul_inputs_t), line:383
|vpiTypedef:
\_enum_typespec: (opcodes_t), line:48
|vpiTypedef:
\_enum_typespec: (opcodes_trimmed_t), line:65
|vpiTypedef:
\_enum_typespec: (privilege_t), line:34
|vpiTypedef:
\_struct_typespec: (satp_t), line:142
|vpiTypedef:
\_struct_typespec: (simulation_named_regfile), line:476
|vpiTypedef:
\_struct_typespec: (taiga_trace_events_t), line:442
|vpiTypedef:
\_struct_typespec: (to_l1_arbiter_packet), line:418
|vpiTypedef:
\_struct_typespec: (trace_outputs_t), line:469
|vpiTypedef:
\_logic_typespec: (unit_id_t), line:31
|vpiTypedef:
\_struct_typespec: (unit_writeback_t), line:295
|vpiTypedef:
\_enum_typespec: (vm_t), line:223
|vpiParamAssign:
\_param_assign: , line:78
|vpiRhs:
\_operation: , line:78
|vpiOpType:32
|vpiOperand:
\_operation: , line:78
|vpiOpType:18
|vpiOperand:
\_ref_obj: (DTLB_DEPTH), line:78
|vpiName:DTLB_DEPTH
|vpiOperand:
\_ref_obj: (ITLB_DEPTH), line:78
|vpiName:ITLB_DEPTH
|vpiOperand:
\_ref_obj: (DTLB_DEPTH), line:78
|vpiName:DTLB_DEPTH
|vpiOperand:
\_ref_obj: (ITLB_DEPTH), line:78
|vpiName:ITLB_DEPTH
|vpiLhs:
\_parameter: (TLB_CLEAR_DEPTH), line:78
|vpiName:TLB_CLEAR_DEPTH
|vpiLocalParam:1
|vpiTypespec:
\_int_typespec: , line:78
|vpiParamAssign:
\_param_assign: , line:80
|vpiRhs:
\_operation: , line:80
|vpiOpType:32
|vpiOperand:
\_ref_obj: (ENABLE_S_MODE), line:80
|vpiName:ENABLE_S_MODE
|vpiOperand:
\_operation: , line:80
|vpiOpType:32
|vpiOperand:
\_operation: , line:78
|vpiOpType:18
|vpiOperand:
\_ref_obj: (DTLB_DEPTH), line:78
|vpiName:DTLB_DEPTH
|vpiOperand:
\_ref_obj: (ITLB_DEPTH), line:78
|vpiName:ITLB_DEPTH
|vpiOperand:
\_ref_obj: (DTLB_DEPTH), line:78
|vpiName:DTLB_DEPTH
|vpiOperand:
\_ref_obj: (ITLB_DEPTH), line:78
|vpiName:ITLB_DEPTH
|vpiOperand:
\_constant: , line:80
|vpiConstType:7
|vpiDecompile:32
|vpiSize:32
|INT:32
|vpiLhs:
\_parameter: (CLEAR_DEPTH), line:80
|vpiName:CLEAR_DEPTH
|vpiLocalParam:1
|vpiTypespec:
\_int_typespec: , line:80
|vpiParameter:
\_parameter: (TLB_CLEAR_DEPTH), line:78
|vpiParameter:
\_parameter: (CLEAR_DEPTH), line:80
|uhdmallModules:
\_module: work@ibram, file:third_party/cores/taiga/core/ibram.sv, line:26, parent:work@div_unit_core_wrapper
|vpiDefName:work@ibram
|vpiFullName:work@ibram
|vpiProcess:
\_always: , line:42
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:42
|vpiCondition:
\_operation: , line:42
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:42
|vpiName:clk
|vpiFullName:work@ibram.clk
|vpiStmt:
\_begin: , line:42
|vpiFullName:work@ibram
|vpiStmt:
\_if_else: , line:43
|vpiCondition:
\_operation: , line:43
|vpiOpType:29
|vpiOperand:
\_ref_obj: (rst), line:43
|vpiName:rst
|vpiFullName:work@ibram.rst
|vpiOperand:
\_ref_obj: (fetch_sub.flush), line:43
|vpiName:fetch_sub.flush
|vpiFullName:work@ibram.fetch_sub.flush
|vpiStmt:
\_assignment: , line:44
|vpiOpType:82
|vpiLhs:
\_ref_obj: (fetch_sub.data_valid), line:44
|vpiName:fetch_sub.data_valid
|vpiFullName:work@ibram.fetch_sub.data_valid
|vpiRhs:
\_constant: , line:44
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiElseStmt:
\_assignment: , line:46
|vpiOpType:82
|vpiLhs:
\_ref_obj: (fetch_sub.data_valid), line:46
|vpiName:fetch_sub.data_valid
|vpiFullName:work@ibram.fetch_sub.data_valid
|vpiRhs:
\_ref_obj: (fetch_sub.new_request), line:46
|vpiName:fetch_sub.new_request
|vpiFullName:work@ibram.fetch_sub.new_request
|vpiPort:
\_port: (clk), line:27
|vpiName:clk
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (clk), line:27
|vpiName:clk
|vpiFullName:work@ibram.clk
|vpiNetType:36
|vpiPort:
\_port: (rst), line:28
|vpiName:rst
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (rst), line:28
|vpiName:rst
|vpiFullName:work@ibram.rst
|vpiNetType:36
|vpiPort:
\_port: (fetch_sub), line:30
|vpiName:fetch_sub
|vpiDirection:5
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_modport: (sub_unit)
|vpiPort:
\_port: (instruction_bram), line:31
|vpiName:instruction_bram
|vpiDirection:5
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_modport: (master)
|vpiContAssign:
\_cont_assign: , line:34
|vpiRhs:
\_constant: , line:34
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiLhs:
\_ref_obj: (fetch_sub.ready), line:34
|vpiName:fetch_sub.ready
|vpiFullName:work@ibram.fetch_sub.ready
|vpiContAssign:
\_cont_assign: , line:36
|vpiRhs:
\_ref_obj: (fetch_sub.stage1_addr), line:36
|vpiName:fetch_sub.stage1_addr
|vpiFullName:work@ibram.fetch_sub.stage1_addr
|vpiLhs:
\_ref_obj: (instruction_bram.addr), line:36
|vpiName:instruction_bram.addr
|vpiFullName:work@ibram.instruction_bram.addr
|vpiContAssign:
\_cont_assign: , line:37
|vpiRhs:
\_ref_obj: (fetch_sub.new_request), line:37
|vpiName:fetch_sub.new_request
|vpiFullName:work@ibram.fetch_sub.new_request
|vpiLhs:
\_ref_obj: (instruction_bram.en), line:37
|vpiName:instruction_bram.en
|vpiFullName:work@ibram.instruction_bram.en
|vpiContAssign:
\_cont_assign: , line:38
|vpiRhs:
\_constant: , line:38
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiLhs:
\_ref_obj: (instruction_bram.be), line:38
|vpiName:instruction_bram.be
|vpiFullName:work@ibram.instruction_bram.be
|vpiContAssign:
\_cont_assign: , line:39
|vpiRhs:
\_constant: , line:39
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiLhs:
\_ref_obj: (instruction_bram.data_in), line:39
|vpiName:instruction_bram.data_in
|vpiFullName:work@ibram.instruction_bram.data_in
|vpiContAssign:
\_cont_assign: , line:40
|vpiRhs:
\_ref_obj: (instruction_bram.data_out), line:40
|vpiName:instruction_bram.data_out
|vpiFullName:work@ibram.instruction_bram.data_out
|vpiLhs:
\_ref_obj: (fetch_sub.data_out), line:40
|vpiName:fetch_sub.data_out
|vpiFullName:work@ibram.fetch_sub.data_out
|vpiNet:
\_logic_net: (clk), line:27
|vpiNet:
\_logic_net: (rst), line:28
|vpiNet:
\_logic_net: (fetch_sub), line:30
|vpiName:fetch_sub
|vpiFullName:work@ibram.fetch_sub
|vpiNet:
\_logic_net: (instruction_bram), line:31
|vpiName:instruction_bram
|vpiFullName:work@ibram.instruction_bram
|vpiTypedef:
\_struct_typespec: (alu_inputs_t), line:301
|vpiTypedef:
\_enum_typespec: (alu_logic_op_t), line:84
|vpiTypedef:
\_enum_typespec: (alu_op_t), line:91
|vpiTypedef:
\_enum_typespec: (alu_rs1_op_t), line:97
|vpiTypedef:
\_enum_typespec: (alu_rs2_op_t), line:104
|vpiTypedef:
\_struct_typespec: (amo_alu_inputs_t), line:356
|vpiTypedef:
\_struct_typespec: (amo_details_t), line:362
|vpiTypedef:
\_enum_typespec: (amo_t), line:354
|vpiTypedef:
\_struct_typespec: (branch_inputs_t), line:313
|vpiTypedef:
\_logic_typespec: (branch_predictor_metadata_t), line:32
|vpiTypedef:
\_struct_typespec: (branch_results_t), line:330
|vpiTypedef:
\_enum_typespec: (bus_type_t), line:86
|vpiTypedef:
\_struct_typespec: (csr_inputs_t), line:396
|vpiTypedef:
\_enum_typespec: (csr_op_t), line:218
|vpiTypedef:
\_enum_typespec: (csr_t), line:201
|vpiTypedef:
\_struct_typespec: (data_access_shared_inputs_t), line:427
|vpiTypedef:
\_struct_typespec: (div_inputs_t), line:389
|vpiTypedef:
\_enum_typespec: (div_type), line:66
|vpiTypedef:
\_enum_typespec: (exception_code_t), line:245
|vpiTypedef:
\_struct_typespec: (exception_packet_t), line:263
|vpiTypedef:
\_struct_typespec: (fetch_buffer_packet_t), line:276
|vpiTypedef:
\_enum_typespec: (fifo_type_t), line:440
|vpiTypedef:
\_enum_typespec: (fn3_arith_t), line:76
|vpiTypedef:
\_enum_typespec: (fn3_branch_t), line:126
|vpiTypedef:
\_enum_typespec: (fn3_csr_t), line:212
|vpiTypedef:
\_enum_typespec: (fn3_ls_t), line:115
|vpiTypedef:
\_enum_typespec: (fn3_mul_div_t), line:138
|vpiTypedef:
\_struct_typespec: (gc_inputs_t), line:404
|vpiTypedef:
\_struct_typespec: (inflight_instruction_packet), line:271
|vpiTypedef:
\_logic_typespec: (instruction_id_t), line:30
|vpiTypedef:
\_enum_typespec: (interrupt_code_t), line:261
|vpiTypedef:
\_struct_typespec: (load_store_inputs_t), line:369
|vpiTypedef:
\_struct_typespec: (mul_inputs_t), line:383
|vpiTypedef:
\_enum_typespec: (opcodes_t), line:48
|vpiTypedef:
\_enum_typespec: (opcodes_trimmed_t), line:65
|vpiTypedef:
\_struct_typespec: (simulation_named_regfile), line:476
|vpiTypedef:
\_struct_typespec: (taiga_trace_events_t), line:442
|vpiTypedef:
\_struct_typespec: (to_l1_arbiter_packet), line:418
|vpiTypedef:
\_struct_typespec: (trace_outputs_t), line:469
|vpiTypedef:
\_logic_typespec: (unit_id_t), line:31
|vpiTypedef:
\_struct_typespec: (unit_writeback_t), line:295
|vpiTypedef:
\_enum_typespec: (vm_t), line:223
|uhdmallModules:
\_module: work@icache, file:third_party/cores/taiga/core/icache.sv, line:26, parent:work@div_unit_core_wrapper
|vpiDefName:work@icache
|vpiFullName:work@icache
|vpiProcess:
\_always: , line:61
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:61
|vpiCondition:
\_operation: , line:61
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:61
|vpiName:clk
|vpiFullName:work@icache.clk
|vpiStmt:
\_begin: , line:61
|vpiFullName:work@icache
|vpiStmt:
\_if_else: , line:62
|vpiCondition:
\_operation: , line:62
|vpiOpType:29
|vpiOperand:
\_ref_obj: (rst), line:62
|vpiName:rst
|vpiFullName:work@icache.rst
|vpiOperand:
\_ref_obj: (fetch_sub.flush), line:62
|vpiName:fetch_sub.flush
|vpiFullName:work@icache.fetch_sub.flush
|vpiStmt:
\_assignment: , line:63
|vpiOpType:82
|vpiLhs:
\_ref_obj: (second_cycle), line:63
|vpiName:second_cycle
|vpiFullName:work@icache.second_cycle
|vpiRhs:
\_constant: , line:63
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiElseStmt:
\_assignment: , line:65
|vpiOpType:82
|vpiLhs:
\_ref_obj: (second_cycle), line:65
|vpiName:second_cycle
|vpiFullName:work@icache.second_cycle
|vpiRhs:
\_ref_obj: (fetch_sub.new_request), line:65
|vpiName:fetch_sub.new_request
|vpiFullName:work@icache.fetch_sub.new_request
|vpiProcess:
\_always: , line:68
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:68
|vpiCondition:
\_operation: , line:68
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:68
|vpiName:clk
|vpiFullName:work@icache.clk
|vpiStmt:
\_begin: , line:68
|vpiFullName:work@icache
|vpiStmt:
\_if_else: , line:69
|vpiCondition:
\_ref_obj: (rst), line:69
|vpiName:rst
|vpiFullName:work@icache.rst
|vpiStmt:
\_assignment: , line:70
|vpiOpType:82
|vpiLhs:
\_ref_obj: (tag_update), line:70
|vpiName:tag_update
|vpiFullName:work@icache.tag_update
|vpiRhs:
\_constant: , line:70
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiElseStmt:
\_if_else: , line:71
|vpiCondition:
\_ref_obj: (second_cycle), line:71
|vpiName:second_cycle
|vpiFullName:work@icache.second_cycle
|vpiStmt:
\_assignment: , line:72
|vpiOpType:82
|vpiLhs:
\_ref_obj: (tag_update), line:72
|vpiName:tag_update
|vpiFullName:work@icache.tag_update
|vpiRhs:
\_operation: , line:72
|vpiOpType:28
|vpiOperand:
\_ref_obj: (icache_on), line:72
|vpiName:icache_on
|vpiFullName:work@icache.icache_on
|vpiOperand:
\_operation: , line:72
|vpiOpType:4
|vpiOperand:
\_ref_obj: (tag_hit), line:72
|vpiName:tag_hit
|vpiFullName:work@icache.tag_hit
|vpiElseStmt:
\_assignment: , line:74
|vpiOpType:82
|vpiLhs:
\_ref_obj: (tag_update), line:74
|vpiName:tag_update
|vpiFullName:work@icache.tag_update
|vpiRhs:
\_constant: , line:74
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiProcess:
\_always: , line:88
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:88
|vpiCondition:
\_operation: , line:88
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:88
|vpiName:clk
|vpiFullName:work@icache.clk
|vpiStmt:
\_begin: , line:88
|vpiFullName:work@icache
|vpiStmt:
\_if_else: , line:89
|vpiCondition:
\_ref_obj: (rst), line:89
|vpiName:rst
|vpiFullName:work@icache.rst
|vpiStmt:
\_assignment: , line:90
|vpiOpType:82
|vpiLhs:
\_ref_obj: (word_count), line:90
|vpiName:word_count
|vpiFullName:work@icache.word_count
|vpiRhs:
\_constant: , line:90
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiElseStmt:
\_if_stmt: , line:91
|vpiCondition:
\_ref_obj: (l1_response.data_valid), line:91
|vpiName:l1_response.data_valid
|vpiFullName:work@icache.l1_response.data_valid
|vpiStmt:
\_assignment: , line:92
|vpiOpType:82
|vpiLhs:
\_ref_obj: (word_count), line:92
|vpiName:word_count
|vpiFullName:work@icache.word_count
|vpiRhs:
\_operation: , line:92
|vpiOpType:24
|vpiOperand:
\_ref_obj: (word_count), line:92
|vpiName:word_count
|vpiFullName:work@icache.word_count
|vpiOperand:
\_constant: , line:92
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiProcess:
\_always: , line:96
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:96
|vpiCondition:
\_operation: , line:96
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:96
|vpiName:clk
|vpiFullName:work@icache.clk
|vpiStmt:
\_begin: , line:96
|vpiFullName:work@icache
|vpiStmt:
\_if_else: , line:97
|vpiCondition:
\_ref_obj: (rst), line:97
|vpiName:rst
|vpiFullName:work@icache.rst
|vpiStmt:
\_assignment: , line:98
|vpiOpType:82
|vpiLhs:
\_ref_obj: (l1_request.request), line:98
|vpiName:l1_request.request
|vpiFullName:work@icache.l1_request.request
|vpiRhs:
\_constant: , line:98
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiElseStmt:
\_if_else: , line:99
|vpiCondition:
\_ref_obj: (second_cycle), line:99
|vpiName:second_cycle
|vpiFullName:work@icache.second_cycle
|vpiStmt:
\_assignment: , line:100
|vpiOpType:82
|vpiLhs:
\_ref_obj: (l1_request.request), line:100
|vpiName:l1_request.request
|vpiFullName:work@icache.l1_request.request
|vpiRhs:
\_operation: , line:100
|vpiOpType:29
|vpiOperand:
\_operation: , line:100
|vpiOpType:4
|vpiOperand:
\_ref_obj: (tag_hit), line:100
|vpiName:tag_hit
|vpiFullName:work@icache.tag_hit
|vpiOperand:
\_operation: , line:100
|vpiOpType:4
|vpiOperand:
\_ref_obj: (icache_on), line:100
|vpiName:icache_on
|vpiFullName:work@icache.icache_on
|vpiElseStmt:
\_if_stmt: , line:101
|vpiCondition:
\_ref_obj: (l1_request.ack), line:101
|vpiName:l1_request.ack
|vpiFullName:work@icache.l1_request.ack
|vpiStmt:
\_assignment: , line:102
|vpiOpType:82
|vpiLhs:
\_ref_obj: (l1_request.request), line:102
|vpiName:l1_request.request
|vpiFullName:work@icache.l1_request.request
|vpiRhs:
\_constant: , line:102
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiProcess:
\_always: , line:112
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:112
|vpiCondition:
\_operation: , line:112
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:112
|vpiName:clk
|vpiFullName:work@icache.clk
|vpiStmt:
\_begin: , line:112
|vpiFullName:work@icache
|vpiStmt:
\_if_stmt: , line:113
|vpiCondition:
\_ref_obj: (second_cycle), line:113
|vpiName:second_cycle
|vpiFullName:work@icache.second_cycle
|vpiStmt:
\_begin: , line:113
|vpiFullName:work@icache
|vpiStmt:
\_assignment: , line:114
|vpiOpType:82
|vpiLhs:
\_ref_obj: (tag_update_way), line:114
|vpiName:tag_update_way
|vpiFullName:work@icache.tag_update_way
|vpiRhs:
\_ref_obj: (replacement_way), line:114
|vpiName:replacement_way
|vpiFullName:work@icache.replacement_way
|vpiProcess:
\_always: , line:152
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:152
|vpiCondition:
\_operation: , line:152
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:152
|vpiName:clk
|vpiFullName:work@icache.clk
|vpiStmt:
\_begin: , line:152
|vpiFullName:work@icache
|vpiStmt:
\_if_else: , line:153
|vpiCondition:
\_operation: , line:153
|vpiOpType:28
|vpiOperand:
\_ref_obj: (l1_response.data_valid), line:153
|vpiName:l1_response.data_valid
|vpiFullName:work@icache.l1_response.data_valid
|vpiOperand:
\_ref_obj: (is_target_word), line:153
|vpiName:is_target_word
|vpiFullName:work@icache.is_target_word
|vpiStmt:
\_assignment: , line:154
|vpiOpType:82
|vpiLhs:
\_ref_obj: (miss_data), line:154
|vpiName:miss_data
|vpiFullName:work@icache.miss_data
|vpiRhs:
\_ref_obj: (l1_response.data), line:154
|vpiName:l1_response.data
|vpiFullName:work@icache.l1_response.data
|vpiElseStmt:
\_assignment: , line:156
|vpiOpType:82
|vpiLhs:
\_ref_obj: (miss_data), line:156
|vpiName:miss_data
|vpiFullName:work@icache.miss_data
|vpiRhs:
\_constant: , line:156
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiProcess:
\_always: , line:159
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:159
|vpiCondition:
\_operation: , line:159
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:159
|vpiName:clk
|vpiFullName:work@icache.clk
|vpiStmt:
\_begin: , line:159
|vpiFullName:work@icache
|vpiStmt:
\_if_else: , line:160
|vpiCondition:
\_ref_obj: (rst), line:160
|vpiName:rst
|vpiFullName:work@icache.rst
|vpiStmt:
\_assignment: , line:161
|vpiOpType:82
|vpiLhs:
\_ref_obj: (miss_data_ready), line:161
|vpiName:miss_data_ready
|vpiFullName:work@icache.miss_data_ready
|vpiRhs:
\_constant: , line:161
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiElseStmt:
\_assignment: , line:163
|vpiOpType:82
|vpiLhs:
\_ref_obj: (miss_data_ready), line:163
|vpiName:miss_data_ready
|vpiFullName:work@icache.miss_data_ready
|vpiRhs:
\_operation: , line:163
|vpiOpType:28
|vpiOperand:
\_ref_obj: (l1_response.data_valid), line:163
|vpiName:l1_response.data_valid
|vpiFullName:work@icache.l1_response.data_valid
|vpiOperand:
\_ref_obj: (is_target_word), line:163
|vpiName:is_target_word
|vpiFullName:work@icache.is_target_word
|vpiProcess:
\_always: , line:167
|vpiAlwaysType:2
|vpiStmt:
\_begin: , line:167
|vpiFullName:work@icache
|vpiStmt:
\_assignment: , line:168
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (fetch_sub.data_out), line:168
|vpiName:fetch_sub.data_out
|vpiFullName:work@icache.fetch_sub.data_out
|vpiRhs:
\_ref_obj: (miss_data), line:168
|vpiName:miss_data
|vpiFullName:work@icache.miss_data
|vpiStmt:
\_for_stmt: , line:169
|vpiFullName:work@icache
|vpiCondition:
\_operation: , line:169
|vpiOpType:20
|vpiOperand:
\_ref_obj: (i), line:169
|vpiName:i
|vpiFullName:work@icache.i
|vpiOperand:
\_ref_obj: (ICACHE_WAYS), line:169
|vpiName:ICACHE_WAYS
|vpiFullName:work@icache.ICACHE_WAYS
|vpiForInitStmt:
\_assign_stmt:
|vpiRhs:
\_constant: , line:169
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiLhs:
\_int_var: (i), line:169
|vpiName:i
|vpiFullName:work@icache.i
|vpiForIncStmt:
\_operation: , line:169
|vpiOpType:62
|vpiOperand:
\_ref_obj: (i), line:169
|vpiName:i
|vpiStmt:
\_begin: , line:169
|vpiFullName:work@icache
|vpiStmt:
\_assignment: , line:170
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (fetch_sub.data_out), line:170
|vpiName:fetch_sub.data_out
|vpiFullName:work@icache.fetch_sub.data_out
|vpiRhs:
\_operation: , line:170
|vpiOpType:29
|vpiOperand:
\_ref_obj: (fetch_sub.data_out), line:170
|vpiName:fetch_sub.data_out
|vpiFullName:work@icache.fetch_sub.data_out
|vpiOperand:
\_operation: , line:170
|vpiOpType:28
|vpiOperand:
\_bit_select: (data_out), line:170
|vpiName:data_out
|vpiFullName:work@icache.data_out
|vpiIndex:
\_ref_obj: (i), line:170
|vpiName:i
|vpiFullName:work@icache.i
|vpiOperand:
\_operation: , line:170
|vpiOpType:34
|vpiOperand:
\_constant: , line:170
|vpiConstType:7
|vpiDecompile:32
|vpiSize:32
|INT:32
|vpiOperand:
\_operation:
|vpiOpType:33
|vpiOperand:
\_bit_select: (tag_hit_way), line:170
|vpiName:tag_hit_way
|vpiIndex:
\_ref_obj: (i), line:170
|vpiName:i
|vpiFullName:work@icache.i
|vpiProcess:
\_always: , line:181
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:181
|vpiCondition:
\_operation: , line:181
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:181
|vpiName:clk
|vpiFullName:work@icache.clk
|vpiStmt:
\_begin: , line:181
|vpiFullName:work@icache
|vpiStmt:
\_if_else: , line:182
|vpiCondition:
\_ref_obj: (rst), line:182
|vpiName:rst
|vpiFullName:work@icache.rst
|vpiStmt:
\_assignment: , line:183
|vpiOpType:82
|vpiLhs:
\_ref_obj: (memory_complete), line:183
|vpiName:memory_complete
|vpiFullName:work@icache.memory_complete
|vpiRhs:
\_constant: , line:183
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiElseStmt:
\_assignment: , line:185
|vpiOpType:82
|vpiLhs:
\_ref_obj: (memory_complete), line:185
|vpiName:memory_complete
|vpiFullName:work@icache.memory_complete
|vpiRhs:
\_ref_obj: (line_complete), line:185
|vpiName:line_complete
|vpiFullName:work@icache.line_complete
|vpiProcess:
\_always: , line:190
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:190
|vpiCondition:
\_operation: , line:190
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:190
|vpiName:clk
|vpiFullName:work@icache.clk
|vpiStmt:
\_begin: , line:190
|vpiFullName:work@icache
|vpiStmt:
\_if_else: , line:191
|vpiCondition:
\_ref_obj: (rst), line:191
|vpiName:rst
|vpiFullName:work@icache.rst
|vpiStmt:
\_assignment: , line:192
|vpiOpType:82
|vpiLhs:
\_ref_obj: (idle), line:192
|vpiName:idle
|vpiFullName:work@icache.idle
|vpiRhs:
\_constant: , line:192
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiElseStmt:
\_if_else: , line:193
|vpiCondition:
\_operation: , line:193
|vpiOpType:28
|vpiOperand:
\_ref_obj: (fetch_sub.new_request), line:193
|vpiName:fetch_sub.new_request
|vpiFullName:work@icache.fetch_sub.new_request
|vpiOperand:
\_operation: , line:193
|vpiOpType:4
|vpiOperand:
\_ref_obj: (fetch_sub.flush), line:193
|vpiName:fetch_sub.flush
|vpiFullName:work@icache.fetch_sub.flush
|vpiStmt:
\_assignment: , line:194
|vpiOpType:82
|vpiLhs:
\_ref_obj: (idle), line:194
|vpiName:idle
|vpiFullName:work@icache.idle
|vpiRhs:
\_constant: , line:194
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiElseStmt:
\_if_stmt: , line:195
|vpiCondition:
\_operation: , line:195
|vpiOpType:29
|vpiOperand:
\_ref_obj: (memory_complete), line:195
|vpiName:memory_complete
|vpiFullName:work@icache.memory_complete
|vpiOperand:
\_ref_obj: (tag_hit), line:195
|vpiName:tag_hit
|vpiFullName:work@icache.tag_hit
|vpiStmt:
\_assignment: , line:196
|vpiOpType:82
|vpiLhs:
\_ref_obj: (idle), line:196
|vpiName:idle
|vpiFullName:work@icache.idle
|vpiRhs:
\_constant: , line:196
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiPort:
\_port: (clk), line:27
|vpiName:clk
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (clk), line:27
|vpiName:clk
|vpiFullName:work@icache.clk
|vpiNetType:36
|vpiPort:
\_port: (rst), line:28
|vpiName:rst
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (rst), line:28
|vpiName:rst
|vpiFullName:work@icache.rst
|vpiNetType:36
|vpiPort:
\_port: (icache_on), line:29
|vpiName:icache_on
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (icache_on), line:29
|vpiName:icache_on
|vpiFullName:work@icache.icache_on
|vpiNetType:36
|vpiPort:
\_port: (l1_request), line:30
|vpiName:l1_request
|vpiDirection:5
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_modport: (master)
|vpiPort:
\_port: (l1_response), line:31
|vpiName:l1_response
|vpiDirection:5
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_modport: (master)
|vpiPort:
\_port: (fetch_sub), line:33
|vpiName:fetch_sub
|vpiDirection:5
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_modport: (sub_unit)
|vpiContAssign:
\_cont_assign: , line:80
|vpiRhs:
\_ref_obj: (fetch_sub.stage2_addr), line:80
|vpiName:fetch_sub.stage2_addr
|vpiFullName:work@icache.fetch_sub.stage2_addr
|vpiLhs:
\_ref_obj: (l1_request.addr), line:80
|vpiName:l1_request.addr
|vpiFullName:work@icache.l1_request.addr
|vpiContAssign:
\_cont_assign: , line:81
|vpiRhs:
\_constant: , line:81
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiLhs:
\_ref_obj: (l1_request.data), line:81
|vpiName:l1_request.data
|vpiFullName:work@icache.l1_request.data
|vpiContAssign:
\_cont_assign: , line:82
|vpiRhs:
\_constant: , line:82
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiLhs:
\_ref_obj: (l1_request.rnw), line:82
|vpiName:l1_request.rnw
|vpiFullName:work@icache.l1_request.rnw
|vpiContAssign:
\_cont_assign: , line:83
|vpiRhs:
\_constant: , line:83
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiLhs:
\_ref_obj: (l1_request.be), line:83
|vpiName:l1_request.be
|vpiFullName:work@icache.l1_request.be
|vpiContAssign:
\_cont_assign: , line:84
|vpiRhs:
\_operation: , line:84
|vpiOpType:11
|vpiOperand:
\_ref_obj: (ICACHE_LINE_W), line:84
|vpiName:ICACHE_LINE_W
|vpiFullName:work@icache.ICACHE_LINE_W
|vpiOperand:
\_constant: , line:84
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiLhs:
\_ref_obj: (l1_request.size), line:84
|vpiName:l1_request.size
|vpiFullName:work@icache.l1_request.size
|vpiContAssign:
\_cont_assign: , line:85
|vpiRhs:
\_constant: , line:85
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiLhs:
\_ref_obj: (l1_request.is_amo), line:85
|vpiName:l1_request.is_amo
|vpiFullName:work@icache.l1_request.is_amo
|vpiContAssign:
\_cont_assign: , line:86
|vpiRhs:
\_constant: , line:86
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiLhs:
\_ref_obj: (l1_request.amo), line:86
|vpiName:l1_request.amo
|vpiFullName:work@icache.l1_request.amo
|vpiContAssign:
\_cont_assign: , line:150
|vpiRhs:
\_operation: , line:150
|vpiOpType:14
|vpiOperand:
\_ref_obj: (fetch_sub.stage2_addr), line:150
|vpiName:fetch_sub.stage2_addr
|vpiFullName:work@icache.fetch_sub.stage2_addr
|vpiOperand:
\_ref_obj: (word_count), line:150
|vpiName:word_count
|vpiFullName:work@icache.word_count
|vpiLhs:
\_ref_obj: (is_target_word), line:150
|vpiName:is_target_word
|vpiFullName:work@icache.is_target_word
|vpiContAssign:
\_cont_assign: , line:174
|vpiRhs:
\_operation: , line:174
|vpiOpType:29
|vpiOperand:
\_ref_obj: (miss_data_ready), line:174
|vpiName:miss_data_ready
|vpiFullName:work@icache.miss_data_ready
|vpiOperand:
\_ref_obj: (tag_hit), line:174
|vpiName:tag_hit
|vpiFullName:work@icache.tag_hit
|vpiLhs:
\_ref_obj: (fetch_sub.data_valid), line:174
|vpiName:fetch_sub.data_valid
|vpiFullName:work@icache.fetch_sub.data_valid
|vpiContAssign:
\_cont_assign: , line:179
|vpiRhs:
\_operation: , line:179
|vpiOpType:26
|vpiOperand:
\_ref_obj: (l1_response.data_valid), line:179
|vpiName:l1_response.data_valid
|vpiFullName:work@icache.l1_response.data_valid
|vpiOperand:
\_operation: , line:179
|vpiOpType:14
|vpiOperand:
\_ref_obj: (word_count), line:179
|vpiName:word_count
|vpiFullName:work@icache.word_count
|vpiOperand:
\_operation: , line:179
|vpiOpType:11
|vpiOperand:
\_ref_obj: (ICACHE_LINE_W), line:179
|vpiName:ICACHE_LINE_W
|vpiFullName:work@icache.ICACHE_LINE_W
|vpiOperand:
\_constant: , line:179
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiLhs:
\_ref_obj: (line_complete), line:179
|vpiName:line_complete
|vpiFullName:work@icache.line_complete
|vpiContAssign:
\_cont_assign: , line:188
|vpiRhs:
\_operation: , line:188
|vpiOpType:29
|vpiOperand:
\_operation: , line:188
|vpiOpType:29
|vpiOperand:
\_ref_obj: (tag_hit), line:188
|vpiName:tag_hit
|vpiFullName:work@icache.tag_hit
|vpiOperand:
\_ref_obj: (memory_complete), line:188
|vpiName:memory_complete
|vpiFullName:work@icache.memory_complete
|vpiOperand:
\_ref_obj: (idle), line:188
|vpiName:idle
|vpiFullName:work@icache.idle
|vpiLhs:
\_ref_obj: (fetch_sub.ready), line:188
|vpiName:fetch_sub.ready
|vpiFullName:work@icache.fetch_sub.ready
|vpiNet:
\_logic_net: (clk), line:27
|vpiNet:
\_logic_net: (rst), line:28
|vpiNet:
\_logic_net: (icache_on), line:29
|vpiNet:
\_logic_net: (tag_hit), line:36
|vpiName:tag_hit
|vpiFullName:work@icache.tag_hit
|vpiNetType:36
|vpiNet:
\_logic_net: (tag_hit_way), line:37
|vpiName:tag_hit_way
|vpiFullName:work@icache.tag_hit_way
|vpiNetType:36
|vpiNet:
\_logic_net: (tag_update), line:39
|vpiName:tag_update
|vpiFullName:work@icache.tag_update
|vpiNetType:36
|vpiNet:
\_logic_net: (replacement_way), line:40
|vpiName:replacement_way
|vpiFullName:work@icache.replacement_way
|vpiNetType:36
|vpiNet:
\_logic_net: (tag_update_way), line:41
|vpiName:tag_update_way
|vpiFullName:work@icache.tag_update_way
|vpiNetType:36
|vpiNet:
\_logic_net: (word_count), line:43
|vpiName:word_count
|vpiFullName:work@icache.word_count
|vpiNetType:36
|vpiNet:
\_logic_net: (is_target_word), line:44
|vpiName:is_target_word
|vpiFullName:work@icache.is_target_word
|vpiNetType:36
|vpiNet:
\_logic_net: (line_complete), line:45
|vpiName:line_complete
|vpiFullName:work@icache.line_complete
|vpiNetType:36
|vpiNet:
\_logic_net: (data_out), line:47
|vpiName:data_out
|vpiFullName:work@icache.data_out
|vpiNetType:36
|vpiNet:
\_logic_net: (miss_data), line:48
|vpiName:miss_data
|vpiFullName:work@icache.miss_data
|vpiNetType:36
|vpiNet:
\_logic_net: (miss_data_ready), line:50
|vpiName:miss_data_ready
|vpiFullName:work@icache.miss_data_ready
|vpiNetType:36
|vpiNet:
\_logic_net: (second_cycle), line:51
|vpiName:second_cycle
|vpiFullName:work@icache.second_cycle
|vpiNetType:36
|vpiNet:
\_logic_net: (idle), line:53
|vpiName:idle
|vpiFullName:work@icache.idle
|vpiNetType:36
|vpiNet:
\_logic_net: (memory_complete), line:54
|vpiName:memory_complete
|vpiFullName:work@icache.memory_complete
|vpiNetType:36
|vpiNet:
\_logic_net: (hit_allowed), line:55
|vpiName:hit_allowed
|vpiFullName:work@icache.hit_allowed
|vpiNetType:36
|vpiNet:
\_logic_net: (l1_request), line:30
|vpiName:l1_request
|vpiFullName:work@icache.l1_request
|vpiNet:
\_logic_net: (l1_response), line:31
|vpiName:l1_response
|vpiFullName:work@icache.l1_response
|vpiNet:
\_logic_net: (fetch_sub), line:33
|vpiName:fetch_sub
|vpiFullName:work@icache.fetch_sub
|vpiTypedef:
\_struct_typespec: (alu_inputs_t), line:301
|vpiTypedef:
\_enum_typespec: (alu_logic_op_t), line:84
|vpiTypedef:
\_enum_typespec: (alu_op_t), line:91
|vpiTypedef:
\_enum_typespec: (alu_rs1_op_t), line:97
|vpiTypedef:
\_enum_typespec: (alu_rs2_op_t), line:104
|vpiTypedef:
\_struct_typespec: (amo_alu_inputs_t), line:356
|vpiTypedef:
\_struct_typespec: (amo_details_t), line:362
|vpiTypedef:
\_enum_typespec: (amo_t), line:354
|vpiTypedef:
\_struct_typespec: (branch_inputs_t), line:313
|vpiTypedef:
\_logic_typespec: (branch_predictor_metadata_t), line:32
|vpiTypedef:
\_struct_typespec: (branch_results_t), line:330
|vpiTypedef:
\_enum_typespec: (bus_type_t), line:86
|vpiTypedef:
\_struct_typespec: (csr_inputs_t), line:396
|vpiTypedef:
\_enum_typespec: (csr_op_t), line:218
|vpiTypedef:
\_enum_typespec: (csr_t), line:201
|vpiTypedef:
\_struct_typespec: (data_access_shared_inputs_t), line:427
|vpiTypedef:
\_struct_typespec: (div_inputs_t), line:389
|vpiTypedef:
\_enum_typespec: (div_type), line:66
|vpiTypedef:
\_enum_typespec: (exception_code_t), line:245
|vpiTypedef:
\_struct_typespec: (exception_packet_t), line:263
|vpiTypedef:
\_struct_typespec: (fetch_buffer_packet_t), line:276
|vpiTypedef:
\_enum_typespec: (fifo_type_t), line:440
|vpiTypedef:
\_enum_typespec: (fn3_arith_t), line:76
|vpiTypedef:
\_enum_typespec: (fn3_branch_t), line:126
|vpiTypedef:
\_enum_typespec: (fn3_csr_t), line:212
|vpiTypedef:
\_enum_typespec: (fn3_ls_t), line:115
|vpiTypedef:
\_enum_typespec: (fn3_mul_div_t), line:138
|vpiTypedef:
\_struct_typespec: (gc_inputs_t), line:404
|vpiTypedef:
\_struct_typespec: (inflight_instruction_packet), line:271
|vpiTypedef:
\_logic_typespec: (instruction_id_t), line:30
|vpiTypedef:
\_enum_typespec: (interrupt_code_t), line:261
|vpiTypedef:
\_struct_typespec: (load_store_inputs_t), line:369
|vpiTypedef:
\_struct_typespec: (mul_inputs_t), line:383
|vpiTypedef:
\_enum_typespec: (opcodes_t), line:48
|vpiTypedef:
\_enum_typespec: (opcodes_trimmed_t), line:65
|vpiTypedef:
\_struct_typespec: (simulation_named_regfile), line:476
|vpiTypedef:
\_struct_typespec: (taiga_trace_events_t), line:442
|vpiTypedef:
\_struct_typespec: (to_l1_arbiter_packet), line:418
|vpiTypedef:
\_struct_typespec: (trace_outputs_t), line:469
|vpiTypedef:
\_logic_typespec: (unit_id_t), line:31
|vpiTypedef:
\_struct_typespec: (unit_writeback_t), line:295
|vpiTypedef:
\_enum_typespec: (vm_t), line:223
|uhdmallModules:
\_module: work@id_inuse, file:third_party/cores/taiga/core/id_inuse.sv, line:26, parent:work@div_unit_core_wrapper
|vpiDefName:work@id_inuse
|vpiFullName:work@id_inuse
|vpiProcess:
\_always: , line:50
|vpiAlwaysType:2
|vpiStmt:
\_begin: , line:50
|vpiFullName:work@id_inuse
|vpiStmt:
\_assignment: , line:51
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (issue_id_one_hot), line:51
|vpiName:issue_id_one_hot
|vpiFullName:work@id_inuse.issue_id_one_hot
|vpiRhs:
\_constant: , line:51
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiStmt:
\_assignment: , line:52
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_bit_select: (issue_id_one_hot), line:52
|vpiName:issue_id_one_hot
|vpiFullName:work@id_inuse.issue_id_one_hot
|vpiIndex:
\_ref_obj: (issue_id), line:52
|vpiName:issue_id
|vpiRhs:
\_ref_obj: (issued), line:52
|vpiName:issued
|vpiFullName:work@id_inuse.issued
|vpiStmt:
\_assignment: , line:54
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (retired_id_one_hot), line:54
|vpiName:retired_id_one_hot
|vpiFullName:work@id_inuse.retired_id_one_hot
|vpiRhs:
\_constant: , line:54
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiStmt:
\_assignment: , line:55
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_bit_select: (retired_id_one_hot), line:55
|vpiName:retired_id_one_hot
|vpiFullName:work@id_inuse.retired_id_one_hot
|vpiIndex:
\_ref_obj: (retired_id), line:55
|vpiName:retired_id
|vpiRhs:
\_ref_obj: (retired), line:55
|vpiName:retired
|vpiFullName:work@id_inuse.retired
|vpiStmt:
\_assignment: , line:57
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (id_inuse_new), line:57
|vpiName:id_inuse_new
|vpiFullName:work@id_inuse.id_inuse_new
|vpiRhs:
\_operation: , line:57
|vpiOpType:29
|vpiOperand:
\_ref_obj: (issue_id_one_hot), line:57
|vpiName:issue_id_one_hot
|vpiFullName:work@id_inuse.issue_id_one_hot
|vpiOperand:
\_operation: , line:57
|vpiOpType:28
|vpiOperand:
\_ref_obj: (id_inuse), line:57
|vpiName:id_inuse
|vpiFullName:work@id_inuse.id_inuse
|vpiOperand:
\_operation: , line:57
|vpiOpType:4
|vpiOperand:
\_ref_obj: (retired_id_one_hot), line:57
|vpiName:retired_id_one_hot
|vpiFullName:work@id_inuse.retired_id_one_hot
|vpiProcess:
\_always: , line:60
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:60
|vpiCondition:
\_operation: , line:60
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:60
|vpiName:clk
|vpiFullName:work@id_inuse.clk
|vpiStmt:
\_begin: , line:60
|vpiFullName:work@id_inuse
|vpiStmt:
\_if_else: , line:61
|vpiCondition:
\_ref_obj: (rst), line:61
|vpiName:rst
|vpiFullName:work@id_inuse.rst
|vpiStmt:
\_assignment: , line:62
|vpiOpType:82
|vpiLhs:
\_ref_obj: (id_inuse), line:62
|vpiName:id_inuse
|vpiFullName:work@id_inuse.id_inuse
|vpiRhs:
\_constant: , line:62
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiElseStmt:
\_assignment: , line:64
|vpiOpType:82
|vpiLhs:
\_ref_obj: (id_inuse), line:64
|vpiName:id_inuse
|vpiFullName:work@id_inuse.id_inuse
|vpiRhs:
\_ref_obj: (id_inuse_new), line:64
|vpiName:id_inuse_new
|vpiFullName:work@id_inuse.id_inuse_new
|vpiProcess:
\_always: , line:67
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:67
|vpiCondition:
\_operation: , line:67
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:67
|vpiName:clk
|vpiFullName:work@id_inuse.clk
|vpiStmt:
\_begin: , line:67
|vpiFullName:work@id_inuse
|vpiStmt:
\_if_stmt: , line:68
|vpiCondition:
\_ref_obj: (issued), line:68
|vpiName:issued
|vpiFullName:work@id_inuse.issued
|vpiStmt:
\_assignment: , line:69
|vpiOpType:82
|vpiLhs:
\_bit_select: (rd_addr_list), line:69
|vpiName:rd_addr_list
|vpiFullName:work@id_inuse.rd_addr_list
|vpiIndex:
\_ref_obj: (issue_id), line:69
|vpiName:issue_id
|vpiRhs:
\_ref_obj: (issued_rd_addr), line:69
|vpiName:issued_rd_addr
|vpiFullName:work@id_inuse.issued_rd_addr
|vpiProcess:
\_always: , line:72
|vpiAlwaysType:2
|vpiStmt:
\_begin: , line:72
|vpiFullName:work@id_inuse
|vpiStmt:
\_assignment: , line:73
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (rs1_inuse), line:73
|vpiName:rs1_inuse
|vpiFullName:work@id_inuse.rs1_inuse
|vpiRhs:
\_constant: , line:73
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiStmt:
\_assignment: , line:74
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (rs2_inuse), line:74
|vpiName:rs2_inuse
|vpiFullName:work@id_inuse.rs2_inuse
|vpiRhs:
\_constant: , line:74
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiStmt:
\_foreach_stmt: , line:76
|vpiFullName:work@id_inuse
|vpiVariables:
\_chandle_var: (rd_addr_list), line:76
|vpiName:rd_addr_list
|vpiFullName:work@id_inuse.rd_addr_list
|vpiLoopVars:
\_chandle_var: (i), line:76
|vpiName:i
|vpiFullName:work@id_inuse.i
|vpiStmt:
\_begin: , line:76
|vpiFullName:work@id_inuse
|vpiStmt:
\_assignment: , line:77
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (rs1_inuse), line:77
|vpiName:rs1_inuse
|vpiFullName:work@id_inuse.rs1_inuse
|vpiRhs:
\_operation: , line:77
|vpiOpType:14
|vpiOperand:
\_operation: , line:77
|vpiOpType:33
|vpiOperand:
\_bit_select: (id_inuse), line:77
|vpiName:id_inuse
|vpiIndex:
\_ref_obj: (i), line:77
|vpiName:i
|vpiOperand:
\_bit_select: (rd_addr_list), line:77
|vpiName:rd_addr_list
|vpiIndex:
\_ref_obj: (i), line:77
|vpiName:i
|vpiOperand:
\_operation: , line:77
|vpiOpType:33
|vpiOperand:
\_constant: , line:77
|vpiConstType:3
|vpiDecompile:'b1
|vpiSize:1
|BIN:1
|vpiOperand:
\_ref_obj: (rs1_addr), line:77
|vpiName:rs1_addr
|vpiFullName:work@id_inuse.rs1_addr
|vpiStmt:
\_assignment: , line:78
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (rs2_inuse), line:78
|vpiName:rs2_inuse
|vpiFullName:work@id_inuse.rs2_inuse
|vpiRhs:
\_operation: , line:78
|vpiOpType:14
|vpiOperand:
\_operation: , line:78
|vpiOpType:33
|vpiOperand:
\_bit_select: (id_inuse), line:78
|vpiName:id_inuse
|vpiIndex:
\_ref_obj: (i), line:78
|vpiName:i
|vpiOperand:
\_bit_select: (rd_addr_list), line:78
|vpiName:rd_addr_list
|vpiIndex:
\_ref_obj: (i), line:78
|vpiName:i
|vpiOperand:
\_operation: , line:78
|vpiOpType:33
|vpiOperand:
\_constant: , line:78
|vpiConstType:3
|vpiDecompile:'b1
|vpiSize:1
|BIN:1
|vpiOperand:
\_ref_obj: (rs2_addr), line:78
|vpiName:rs2_addr
|vpiFullName:work@id_inuse.rs2_addr
|vpiPort:
\_port: (clk), line:27
|vpiName:clk
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (clk), line:27
|vpiName:clk
|vpiFullName:work@id_inuse.clk
|vpiNetType:36
|vpiPort:
\_port: (rst), line:28
|vpiName:rst
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (rst), line:28
|vpiName:rst
|vpiFullName:work@id_inuse.rst
|vpiNetType:36
|vpiPort:
\_port: (rs1_addr), line:29
|vpiName:rs1_addr
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (rs1_addr), line:29
|vpiName:rs1_addr
|vpiFullName:work@id_inuse.rs1_addr
|vpiNetType:36
|vpiPort:
\_port: (rs2_addr), line:30
|vpiName:rs2_addr
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (rs2_addr), line:30
|vpiName:rs2_addr
|vpiFullName:work@id_inuse.rs2_addr
|vpiNetType:36
|vpiPort:
\_port: (issued_rd_addr), line:31
|vpiName:issued_rd_addr
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (issued_rd_addr), line:31
|vpiName:issued_rd_addr
|vpiFullName:work@id_inuse.issued_rd_addr
|vpiNetType:36
|vpiPort:
\_port: (issue_id), line:32
|vpiName:issue_id
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (issue_id), line:32
|vpiName:issue_id
|vpiFullName:work@id_inuse.issue_id
|vpiPort:
\_port: (retired_id), line:33
|vpiName:retired_id
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (retired_id), line:33
|vpiName:retired_id
|vpiFullName:work@id_inuse.retired_id
|vpiPort:
\_port: (issued), line:34
|vpiName:issued
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (issued), line:34
|vpiName:issued
|vpiFullName:work@id_inuse.issued
|vpiNetType:36
|vpiPort:
\_port: (retired), line:35
|vpiName:retired
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (retired), line:35
|vpiName:retired
|vpiFullName:work@id_inuse.retired
|vpiNetType:36
|vpiPort:
\_port: (rs1_inuse), line:36
|vpiName:rs1_inuse
|vpiDirection:2
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (rs1_inuse), line:36
|vpiName:rs1_inuse
|vpiFullName:work@id_inuse.rs1_inuse
|vpiNetType:36
|vpiPort:
\_port: (rs2_inuse), line:37
|vpiName:rs2_inuse
|vpiDirection:2
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (rs2_inuse), line:37
|vpiName:rs2_inuse
|vpiFullName:work@id_inuse.rs2_inuse
|vpiNetType:36
|vpiNet:
\_logic_net: (clk), line:27
|vpiNet:
\_logic_net: (rst), line:28
|vpiNet:
\_logic_net: (rs1_addr), line:29
|vpiNet:
\_logic_net: (rs2_addr), line:30
|vpiNet:
\_logic_net: (issued_rd_addr), line:31
|vpiNet:
\_logic_net: (issue_id), line:32
|vpiNet:
\_logic_net: (retired_id), line:33
|vpiNet:
\_logic_net: (issued), line:34
|vpiNet:
\_logic_net: (retired), line:35
|vpiNet:
\_logic_net: (rs1_inuse), line:36
|vpiNet:
\_logic_net: (rs2_inuse), line:37
|vpiNet:
\_logic_net: (rd_addr_list), line:40
|vpiName:rd_addr_list
|vpiFullName:work@id_inuse.rd_addr_list
|vpiNetType:36
|vpiNet:
\_logic_net: (id_inuse), line:42
|vpiName:id_inuse
|vpiFullName:work@id_inuse.id_inuse
|vpiNetType:36
|vpiNet:
\_logic_net: (id_inuse_new), line:43
|vpiName:id_inuse_new
|vpiFullName:work@id_inuse.id_inuse_new
|vpiNetType:36
|vpiNet:
\_logic_net: (issue_id_one_hot), line:45
|vpiName:issue_id_one_hot
|vpiFullName:work@id_inuse.issue_id_one_hot
|vpiNetType:36
|vpiNet:
\_logic_net: (retired_id_one_hot), line:46
|vpiName:retired_id_one_hot
|vpiFullName:work@id_inuse.retired_id_one_hot
|vpiNetType:36
|vpiTypedef:
\_struct_typespec: (alu_inputs_t), line:301
|vpiTypedef:
\_enum_typespec: (alu_logic_op_t), line:84
|vpiTypedef:
\_enum_typespec: (alu_op_t), line:91
|vpiTypedef:
\_enum_typespec: (alu_rs1_op_t), line:97
|vpiTypedef:
\_enum_typespec: (alu_rs2_op_t), line:104
|vpiTypedef:
\_struct_typespec: (amo_alu_inputs_t), line:356
|vpiTypedef:
\_struct_typespec: (amo_details_t), line:362
|vpiTypedef:
\_enum_typespec: (amo_t), line:354
|vpiTypedef:
\_struct_typespec: (branch_inputs_t), line:313
|vpiTypedef:
\_logic_typespec: (branch_predictor_metadata_t), line:32
|vpiTypedef:
\_struct_typespec: (branch_results_t), line:330
|vpiTypedef:
\_enum_typespec: (bus_type_t), line:86
|vpiTypedef:
\_struct_typespec: (csr_inputs_t), line:396
|vpiTypedef:
\_enum_typespec: (csr_op_t), line:218
|vpiTypedef:
\_enum_typespec: (csr_t), line:201
|vpiTypedef:
\_struct_typespec: (data_access_shared_inputs_t), line:427
|vpiTypedef:
\_struct_typespec: (div_inputs_t), line:389
|vpiTypedef:
\_enum_typespec: (div_type), line:66
|vpiTypedef:
\_enum_typespec: (exception_code_t), line:245
|vpiTypedef:
\_struct_typespec: (exception_packet_t), line:263
|vpiTypedef:
\_struct_typespec: (fetch_buffer_packet_t), line:276
|vpiTypedef:
\_enum_typespec: (fifo_type_t), line:440
|vpiTypedef:
\_enum_typespec: (fn3_arith_t), line:76
|vpiTypedef:
\_enum_typespec: (fn3_branch_t), line:126
|vpiTypedef:
\_enum_typespec: (fn3_csr_t), line:212
|vpiTypedef:
\_enum_typespec: (fn3_ls_t), line:115
|vpiTypedef:
\_enum_typespec: (fn3_mul_div_t), line:138
|vpiTypedef:
\_struct_typespec: (gc_inputs_t), line:404
|vpiTypedef:
\_struct_typespec: (inflight_instruction_packet), line:271
|vpiTypedef:
\_logic_typespec: (instruction_id_t), line:30
|vpiTypedef:
\_enum_typespec: (interrupt_code_t), line:261
|vpiTypedef:
\_struct_typespec: (load_store_inputs_t), line:369
|vpiTypedef:
\_struct_typespec: (mul_inputs_t), line:383
|vpiTypedef:
\_enum_typespec: (opcodes_t), line:48
|vpiTypedef:
\_enum_typespec: (opcodes_trimmed_t), line:65
|vpiTypedef:
\_struct_typespec: (simulation_named_regfile), line:476
|vpiTypedef:
\_struct_typespec: (taiga_trace_events_t), line:442
|vpiTypedef:
\_struct_typespec: (to_l1_arbiter_packet), line:418
|vpiTypedef:
\_struct_typespec: (trace_outputs_t), line:469
|vpiTypedef:
\_logic_typespec: (unit_id_t), line:31
|vpiTypedef:
\_struct_typespec: (unit_writeback_t), line:295
|vpiTypedef:
\_enum_typespec: (vm_t), line:223
|uhdmallModules:
\_module: work@id_tracking, file:third_party/cores/taiga/core/id_tracking.sv, line:26, parent:work@div_unit_core_wrapper
|vpiDefName:work@id_tracking
|vpiFullName:work@id_tracking
|vpiProcess:
\_always: , line:42
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:42
|vpiCondition:
\_operation: , line:42
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:42
|vpiName:clk
|vpiFullName:work@id_tracking.clk
|vpiStmt:
\_begin: , line:42
|vpiFullName:work@id_tracking
|vpiStmt:
\_if_else: , line:43
|vpiCondition:
\_ref_obj: (rst), line:43
|vpiName:rst
|vpiFullName:work@id_tracking.rst
|vpiStmt:
\_assignment: , line:44
|vpiOpType:82
|vpiLhs:
\_ref_obj: (oldest_id), line:44
|vpiName:oldest_id
|vpiFullName:work@id_tracking.oldest_id
|vpiRhs:
\_constant: , line:44
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiElseStmt:
\_assignment: , line:46
|vpiOpType:82
|vpiLhs:
\_ref_obj: (oldest_id), line:46
|vpiName:oldest_id
|vpiFullName:work@id_tracking.oldest_id
|vpiRhs:
\_operation: , line:46
|vpiOpType:24
|vpiOperand:
\_ref_obj: (oldest_id), line:46
|vpiName:oldest_id
|vpiFullName:work@id_tracking.oldest_id
|vpiOperand:
\_operation: , line:46
|vpiOpType:67
|vpiOperand:
\_ref_obj: (retired), line:46
|vpiName:retired
|vpiFullName:work@id_tracking.retired
|vpiTypespec:
\_void_typespec: (LOG2_MAX_INFLIGHT_COUNT), line:46
|vpiName:LOG2_MAX_INFLIGHT_COUNT
|vpiProcess:
\_always: , line:48
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:48
|vpiCondition:
\_operation: , line:48
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:48
|vpiName:clk
|vpiFullName:work@id_tracking.clk
|vpiStmt:
\_begin: , line:48
|vpiFullName:work@id_tracking
|vpiStmt:
\_if_else: , line:49
|vpiCondition:
\_ref_obj: (rst), line:49
|vpiName:rst
|vpiFullName:work@id_tracking.rst
|vpiStmt:
\_assignment: , line:50
|vpiOpType:82
|vpiLhs:
\_ref_obj: (next_id), line:50
|vpiName:next_id
|vpiFullName:work@id_tracking.next_id
|vpiRhs:
\_constant: , line:50
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiElseStmt:
\_assignment: , line:52
|vpiOpType:82
|vpiLhs:
\_ref_obj: (next_id), line:52
|vpiName:next_id
|vpiFullName:work@id_tracking.next_id
|vpiRhs:
\_operation: , line:52
|vpiOpType:24
|vpiOperand:
\_ref_obj: (next_id), line:52
|vpiName:next_id
|vpiFullName:work@id_tracking.next_id
|vpiOperand:
\_operation: , line:52
|vpiOpType:67
|vpiOperand:
\_ref_obj: (issued), line:52
|vpiName:issued
|vpiFullName:work@id_tracking.issued
|vpiTypespec:
\_void_typespec: (LOG2_MAX_INFLIGHT_COUNT), line:52
|vpiName:LOG2_MAX_INFLIGHT_COUNT
|vpiProcess:
\_always: , line:56
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:56
|vpiCondition:
\_operation: , line:56
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:56
|vpiName:clk
|vpiFullName:work@id_tracking.clk
|vpiStmt:
\_begin: , line:56
|vpiFullName:work@id_tracking
|vpiStmt:
\_if_else: , line:57
|vpiCondition:
\_ref_obj: (rst), line:57
|vpiName:rst
|vpiFullName:work@id_tracking.rst
|vpiStmt:
\_assignment: , line:58
|vpiOpType:82
|vpiLhs:
\_ref_obj: (inflight_count), line:58
|vpiName:inflight_count
|vpiFullName:work@id_tracking.inflight_count
|vpiRhs:
\_constant: , line:58
|vpiConstType:3
|vpiDecompile:'b1
|vpiSize:1
|BIN:1
|vpiElseStmt:
\_assignment: , line:60
|vpiOpType:82
|vpiLhs:
\_ref_obj: (inflight_count), line:60
|vpiName:inflight_count
|vpiFullName:work@id_tracking.inflight_count
|vpiRhs:
\_operation: , line:60
|vpiOpType:11
|vpiOperand:
\_operation: , line:60
|vpiOpType:24
|vpiOperand:
\_ref_obj: (inflight_count), line:60
|vpiName:inflight_count
|vpiFullName:work@id_tracking.inflight_count
|vpiOperand:
\_operation: , line:60
|vpiOpType:67
|vpiOperand:
\_ref_obj: (retired), line:60
|vpiName:retired
|vpiFullName:work@id_tracking.retired
|vpiOperand:
\_operation: , line:60
|vpiOpType:67
|vpiOperand:
\_ref_obj: (issued), line:60
|vpiName:issued
|vpiFullName:work@id_tracking.issued
|vpiProcess:
\_always: , line:72
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:72
|vpiCondition:
\_operation: , line:72
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:72
|vpiName:clk
|vpiFullName:work@id_tracking.clk
|vpiStmt:
\_begin: , line:72
|vpiFullName:work@id_tracking
|vpiStmt:
\_immediate_assert: , line:73
|vpiExpr:
\_operation: , line:73
|vpiOpType:29
|vpiOperand:
\_ref_obj: (rst), line:73
|vpiName:rst
|vpiFullName:work@id_tracking.rst
|vpiOperand:
\_operation: , line:73
|vpiOpType:3
|vpiOperand:
\_operation: , line:73
|vpiOpType:28
|vpiOperand:
\_operation: , line:73
|vpiOpType:28
|vpiOperand:
\_operation: , line:73
|vpiOpType:4
|vpiOperand:
\_ref_obj: (rst), line:73
|vpiName:rst
|vpiFullName:work@id_tracking.rst
|vpiOperand:
\_operation: , line:73
|vpiOpType:4
|vpiOperand:
\_ref_obj: (id_available), line:73
|vpiName:id_available
|vpiFullName:work@id_tracking.id_available
|vpiOperand:
\_ref_obj: (issued), line:73
|vpiName:issued
|vpiFullName:work@id_tracking.issued
|vpiElseStmt:
\_sys_func_call: ($error), line:73
|vpiName:$error
|vpiArgument:
\_constant: , line:73
|vpiConstType:6
|vpiDecompile:"Issued without valid ID!"
|vpiSize:26
|STRING:"Issued without valid ID!"
|vpiStmt:
\_immediate_assert: , line:74
|vpiExpr:
\_operation: , line:74
|vpiOpType:29
|vpiOperand:
\_ref_obj: (rst), line:74
|vpiName:rst
|vpiFullName:work@id_tracking.rst
|vpiOperand:
\_operation: , line:74
|vpiOpType:3
|vpiOperand:
\_operation: , line:74
|vpiOpType:28
|vpiOperand:
\_operation: , line:74
|vpiOpType:28
|vpiOperand:
\_operation: , line:74
|vpiOpType:4
|vpiOperand:
\_ref_obj: (rst), line:74
|vpiName:rst
|vpiFullName:work@id_tracking.rst
|vpiOperand:
\_ref_obj: (empty), line:74
|vpiName:empty
|vpiFullName:work@id_tracking.empty
|vpiOperand:
\_operation: , line:74
|vpiOpType:28
|vpiOperand:
\_ref_obj: (retired), line:74
|vpiName:retired
|vpiFullName:work@id_tracking.retired
|vpiOperand:
\_operation: , line:74
|vpiOpType:4
|vpiOperand:
\_ref_obj: (issued), line:74
|vpiName:issued
|vpiFullName:work@id_tracking.issued
|vpiElseStmt:
\_sys_func_call: ($error), line:74
|vpiName:$error
|vpiArgument:
\_constant: , line:74
|vpiConstType:6
|vpiDecompile:"Retired without any instruction inflight!"
|vpiSize:43
|STRING:"Retired without any instruction inflight!"
|vpiPort:
\_port: (clk), line:28
|vpiName:clk
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (clk), line:28
|vpiName:clk
|vpiFullName:work@id_tracking.clk
|vpiNetType:36
|vpiPort:
\_port: (rst), line:29
|vpiName:rst
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (rst), line:29
|vpiName:rst
|vpiFullName:work@id_tracking.rst
|vpiNetType:36
|vpiPort:
\_port: (issued), line:30
|vpiName:issued
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (issued), line:30
|vpiName:issued
|vpiFullName:work@id_tracking.issued
|vpiNetType:36
|vpiPort:
\_port: (retired), line:31
|vpiName:retired
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (retired), line:31
|vpiName:retired
|vpiFullName:work@id_tracking.retired
|vpiNetType:36
|vpiPort:
\_port: (id_available), line:32
|vpiName:id_available
|vpiDirection:2
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (id_available), line:32
|vpiName:id_available
|vpiFullName:work@id_tracking.id_available
|vpiNetType:36
|vpiPort:
\_port: (oldest_id), line:33
|vpiName:oldest_id
|vpiDirection:2
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (oldest_id), line:33
|vpiName:oldest_id
|vpiFullName:work@id_tracking.oldest_id
|vpiPort:
\_port: (next_id), line:34
|vpiName:next_id
|vpiDirection:2
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (next_id), line:34
|vpiName:next_id
|vpiFullName:work@id_tracking.next_id
|vpiPort:
\_port: (empty), line:35
|vpiName:empty
|vpiDirection:2
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (empty), line:35
|vpiName:empty
|vpiFullName:work@id_tracking.empty
|vpiNetType:36
|vpiContAssign:
\_cont_assign: , line:63
|vpiRhs:
\_operation: , line:63
|vpiOpType:5
|vpiOperand:
\_ref_obj: (inflight_count), line:63
|vpiName:inflight_count
|vpiFullName:work@id_tracking.inflight_count
|vpiLhs:
\_ref_obj: (empty), line:63
|vpiName:empty
|vpiFullName:work@id_tracking.empty
|vpiContAssign:
\_cont_assign: , line:64
|vpiRhs:
\_bit_select: (inflight_count), line:64
|vpiName:inflight_count
|vpiFullName:work@id_tracking.inflight_count
|vpiIndex:
\_ref_obj: (LOG2_MAX_INFLIGHT_COUNT), line:64
|vpiName:LOG2_MAX_INFLIGHT_COUNT
|vpiLhs:
\_ref_obj: (id_available), line:64
|vpiName:id_available
|vpiFullName:work@id_tracking.id_available
|vpiNet:
\_logic_net: (clk), line:28
|vpiNet:
\_logic_net: (rst), line:29
|vpiNet:
\_logic_net: (issued), line:30
|vpiNet:
\_logic_net: (retired), line:31
|vpiNet:
\_logic_net: (id_available), line:32
|vpiNet:
\_logic_net: (oldest_id), line:33
|vpiNet:
\_logic_net: (next_id), line:34
|vpiNet:
\_logic_net: (empty), line:35
|vpiNet:
\_logic_net: (inflight_count), line:39
|vpiName:inflight_count
|vpiFullName:work@id_tracking.inflight_count
|vpiNetType:36
|vpiTypedef:
\_struct_typespec: (alu_inputs_t), line:301
|vpiTypedef:
\_enum_typespec: (alu_logic_op_t), line:84
|vpiTypedef:
\_enum_typespec: (alu_op_t), line:91
|vpiTypedef:
\_enum_typespec: (alu_rs1_op_t), line:97
|vpiTypedef:
\_enum_typespec: (alu_rs2_op_t), line:104
|vpiTypedef:
\_struct_typespec: (amo_alu_inputs_t), line:356
|vpiTypedef:
\_struct_typespec: (amo_details_t), line:362
|vpiTypedef:
\_enum_typespec: (amo_t), line:354
|vpiTypedef:
\_struct_typespec: (branch_inputs_t), line:313
|vpiTypedef:
\_logic_typespec: (branch_predictor_metadata_t), line:32
|vpiTypedef:
\_struct_typespec: (branch_results_t), line:330
|vpiTypedef:
\_enum_typespec: (bus_type_t), line:86
|vpiTypedef:
\_struct_typespec: (csr_inputs_t), line:396
|vpiTypedef:
\_enum_typespec: (csr_op_t), line:218
|vpiTypedef:
\_enum_typespec: (csr_t), line:201
|vpiTypedef:
\_struct_typespec: (data_access_shared_inputs_t), line:427
|vpiTypedef:
\_struct_typespec: (div_inputs_t), line:389
|vpiTypedef:
\_enum_typespec: (div_type), line:66
|vpiTypedef:
\_enum_typespec: (exception_code_t), line:245
|vpiTypedef:
\_struct_typespec: (exception_packet_t), line:263
|vpiTypedef:
\_struct_typespec: (fetch_buffer_packet_t), line:276
|vpiTypedef:
\_enum_typespec: (fifo_type_t), line:440
|vpiTypedef:
\_enum_typespec: (fn3_arith_t), line:76
|vpiTypedef:
\_enum_typespec: (fn3_branch_t), line:126
|vpiTypedef:
\_enum_typespec: (fn3_csr_t), line:212
|vpiTypedef:
\_enum_typespec: (fn3_ls_t), line:115
|vpiTypedef:
\_enum_typespec: (fn3_mul_div_t), line:138
|vpiTypedef:
\_struct_typespec: (gc_inputs_t), line:404
|vpiTypedef:
\_struct_typespec: (inflight_instruction_packet), line:271
|vpiTypedef:
\_logic_typespec: (instruction_id_t), line:30
|vpiTypedef:
\_enum_typespec: (interrupt_code_t), line:261
|vpiTypedef:
\_struct_typespec: (load_store_inputs_t), line:369
|vpiTypedef:
\_struct_typespec: (mul_inputs_t), line:383
|vpiTypedef:
\_enum_typespec: (opcodes_t), line:48
|vpiTypedef:
\_enum_typespec: (opcodes_trimmed_t), line:65
|vpiTypedef:
\_struct_typespec: (simulation_named_regfile), line:476
|vpiTypedef:
\_struct_typespec: (taiga_trace_events_t), line:442
|vpiTypedef:
\_struct_typespec: (to_l1_arbiter_packet), line:418
|vpiTypedef:
\_struct_typespec: (trace_outputs_t), line:469
|vpiTypedef:
\_logic_typespec: (unit_id_t), line:31
|vpiTypedef:
\_struct_typespec: (unit_writeback_t), line:295
|vpiTypedef:
\_enum_typespec: (vm_t), line:223
|vpiParamAssign:
\_param_assign: , line:38
|vpiRhs:
\_sys_func_call: ($clog2), line:38
|vpiName:$clog2
|vpiArgument:
\_ref_obj: (MAX_INFLIGHT_COUNT), line:38
|vpiName:MAX_INFLIGHT_COUNT
|vpiLhs:
\_parameter: (LOG2_MAX_INFLIGHT_COUNT), line:38
|vpiName:LOG2_MAX_INFLIGHT_COUNT
|vpiLocalParam:1
|vpiParameter:
\_parameter: (LOG2_MAX_INFLIGHT_COUNT), line:38
|uhdmallModules:
\_module: work@itag_banks, file:third_party/cores/taiga/core/itag_banks.sv, line:26, parent:work@div_unit_core_wrapper
|vpiDefName:work@itag_banks
|vpiFullName:work@itag_banks
|vpiProcess:
\_always: , line:59
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:59
|vpiCondition:
\_operation: , line:59
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:59
|vpiName:clk
|vpiFullName:work@itag_banks.clk
|vpiStmt:
\_begin: , line:59
|vpiFullName:work@itag_banks
|vpiStmt:
\_if_else: , line:60
|vpiCondition:
\_ref_obj: (rst), line:60
|vpiName:rst
|vpiFullName:work@itag_banks.rst
|vpiStmt:
\_assignment: , line:61
|vpiOpType:82
|vpiLhs:
\_ref_obj: (hit_allowed), line:61
|vpiName:hit_allowed
|vpiFullName:work@itag_banks.hit_allowed
|vpiRhs:
\_constant: , line:61
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiElseStmt:
\_assignment: , line:63
|vpiOpType:82
|vpiLhs:
\_ref_obj: (hit_allowed), line:63
|vpiName:hit_allowed
|vpiFullName:work@itag_banks.hit_allowed
|vpiRhs:
\_ref_obj: (stage1_adv), line:63
|vpiName:stage1_adv
|vpiFullName:work@itag_banks.stage1_adv
|vpiPort:
\_port: (clk), line:27
|vpiName:clk
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (clk), line:27
|vpiName:clk
|vpiFullName:work@itag_banks.clk
|vpiNetType:36
|vpiPort:
\_port: (rst), line:28
|vpiName:rst
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (rst), line:28
|vpiName:rst
|vpiFullName:work@itag_banks.rst
|vpiNetType:36
|vpiPort:
\_port: (stage1_addr), line:30
|vpiName:stage1_addr
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (stage1_addr), line:30
|vpiName:stage1_addr
|vpiFullName:work@itag_banks.stage1_addr
|vpiNetType:36
|vpiPort:
\_port: (stage2_addr), line:31
|vpiName:stage2_addr
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (stage2_addr), line:31
|vpiName:stage2_addr
|vpiFullName:work@itag_banks.stage2_addr
|vpiNetType:36
|vpiPort:
\_port: (update_way), line:33
|vpiName:update_way
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (update_way), line:33
|vpiName:update_way
|vpiFullName:work@itag_banks.update_way
|vpiNetType:36
|vpiPort:
\_port: (update), line:34
|vpiName:update
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (update), line:34
|vpiName:update
|vpiFullName:work@itag_banks.update
|vpiNetType:36
|vpiPort:
\_port: (stage1_adv), line:36
|vpiName:stage1_adv
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (stage1_adv), line:36
|vpiName:stage1_adv
|vpiFullName:work@itag_banks.stage1_adv
|vpiNetType:36
|vpiPort:
\_port: (tag_hit), line:38
|vpiName:tag_hit
|vpiDirection:2
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (tag_hit), line:38
|vpiName:tag_hit
|vpiFullName:work@itag_banks.tag_hit
|vpiPort:
\_port: (tag_hit_way), line:39
|vpiName:tag_hit_way
|vpiDirection:2
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (tag_hit_way), line:39
|vpiName:tag_hit_way
|vpiFullName:work@itag_banks.tag_hit_way
|vpiNetType:36
|vpiContAssign:
\_cont_assign: , line:56
|vpiRhs:
\_operation: , line:56
|vpiOpType:33
|vpiOperand:
\_constant: , line:56
|vpiConstType:3
|vpiDecompile:'b1
|vpiSize:1
|BIN:1
|vpiOperand:
\_func_call: (getTag), line:56
|vpiName:getTag
|vpiFunction:
\_function: (getTag), line:44
|vpiName:getTag
|vpiFullName:work@itag_banks.getTag
|vpiReturn:
\_logic_var: , line:44
|vpiRange:
\_range: , line:44
|vpiLeftRange:
\_operation: , line:44
|vpiOpType:11
|vpiOperand:
\_ref_obj: (ICACHE_TAG_W), line:44
|vpiName:ICACHE_TAG_W
|vpiOperand:
\_constant: , line:44
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:44
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (addr)
|vpiName:addr
|vpiDirection:5
|vpiExpr:
\_logic_var: , line:44, parent:addr
|vpiFullName:addr
|vpiRange:
\_range: , line:44
|vpiLeftRange:
\_constant: , line:44
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:44
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiStmt:
\_return_stmt: , line:45, parent:getTag
|vpiCondition:
\_part_select: , line:45
|vpiConstantSelect:1
|vpiParent:
\_return_stmt: , line:45, parent:getTag
|vpiLeftRange:
\_constant: , line:45
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_operation: , line:45
|vpiOpType:11
|vpiOperand:
\_constant: , line:45
|vpiConstType:7
|vpiDecompile:32
|vpiSize:32
|INT:32
|vpiOperand:
\_ref_obj: (ICACHE_TAG_W), line:45
|vpiName:ICACHE_TAG_W
|vpiArgument:
\_ref_obj: (stage2_addr), line:56
|vpiName:stage2_addr
|vpiLhs:
\_ref_obj: (stage2_tag), line:56
|vpiName:stage2_tag
|vpiFullName:work@itag_banks.stage2_tag
|vpiContAssign:
\_cont_assign: , line:85
|vpiRhs:
\_operation: , line:85
|vpiOpType:7
|vpiOperand:
\_ref_obj: (tag_hit_way), line:85
|vpiName:tag_hit_way
|vpiFullName:work@itag_banks.tag_hit_way
|vpiLhs:
\_ref_obj: (tag_hit), line:85
|vpiName:tag_hit
|vpiFullName:work@itag_banks.tag_hit
|vpiTaskFunc:
\_function: (getTag), line:44
|vpiTaskFunc:
\_function: (getLineAddr), line:48
|vpiName:getLineAddr
|vpiFullName:work@itag_banks.getLineAddr
|vpiReturn:
\_logic_var: , line:48
|vpiRange:
\_range: , line:48
|vpiLeftRange:
\_operation: , line:48
|vpiOpType:11
|vpiOperand:
\_ref_obj: (ICACHE_LINE_ADDR_W), line:48
|vpiName:ICACHE_LINE_ADDR_W
|vpiOperand:
\_constant: , line:48
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:48
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (addr)
|vpiName:addr
|vpiDirection:5
|vpiExpr:
\_logic_var: , line:48, parent:addr
|vpiFullName:addr
|vpiRange:
\_range: , line:48
|vpiLeftRange:
\_constant: , line:48
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:48
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiStmt:
\_return_stmt: , line:49, parent:getLineAddr
|vpiCondition:
\_part_select: , line:49
|vpiConstantSelect:1
|vpiParent:
\_return_stmt: , line:49, parent:getLineAddr
|vpiLeftRange:
\_operation: , line:49
|vpiOpType:24
|vpiOperand:
\_operation: , line:49
|vpiOpType:24
|vpiOperand:
\_ref_obj: (ICACHE_LINE_ADDR_W), line:49
|vpiName:ICACHE_LINE_ADDR_W
|vpiOperand:
\_ref_obj: (ICACHE_SUB_LINE_ADDR_W), line:49
|vpiName:ICACHE_SUB_LINE_ADDR_W
|vpiOperand:
\_constant: , line:49
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_operation: , line:49
|vpiOpType:24
|vpiOperand:
\_ref_obj: (ICACHE_SUB_LINE_ADDR_W), line:49
|vpiName:ICACHE_SUB_LINE_ADDR_W
|vpiOperand:
\_constant: , line:49
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiNet:
\_logic_net: (clk), line:27
|vpiNet:
\_logic_net: (rst), line:28
|vpiNet:
\_logic_net: (stage1_addr), line:30
|vpiNet:
\_logic_net: (stage2_addr), line:31
|vpiNet:
\_logic_net: (update_way), line:33
|vpiNet:
\_logic_net: (update), line:34
|vpiNet:
\_logic_net: (stage1_adv), line:36
|vpiNet:
\_logic_net: (tag_hit), line:38
|vpiNet:
\_logic_net: (tag_hit_way), line:39
|vpiNet:
\_logic_net: (hit_allowed), line:52
|vpiName:hit_allowed
|vpiFullName:work@itag_banks.hit_allowed
|vpiNetType:36
|vpiNet:
\_logic_net: (tag_line), line:53
|vpiName:tag_line
|vpiFullName:work@itag_banks.tag_line
|vpiNet:
\_logic_net: (stage2_tag), line:55
|vpiName:stage2_tag
|vpiFullName:work@itag_banks.stage2_tag
|vpiTypedef:
\_struct_typespec: (alu_inputs_t), line:301
|vpiTypedef:
\_enum_typespec: (alu_logic_op_t), line:84
|vpiTypedef:
\_enum_typespec: (alu_op_t), line:91
|vpiTypedef:
\_enum_typespec: (alu_rs1_op_t), line:97
|vpiTypedef:
\_enum_typespec: (alu_rs2_op_t), line:104
|vpiTypedef:
\_struct_typespec: (amo_alu_inputs_t), line:356
|vpiTypedef:
\_struct_typespec: (amo_details_t), line:362
|vpiTypedef:
\_enum_typespec: (amo_t), line:354
|vpiTypedef:
\_struct_typespec: (branch_inputs_t), line:313
|vpiTypedef:
\_logic_typespec: (branch_predictor_metadata_t), line:32
|vpiTypedef:
\_struct_typespec: (branch_results_t), line:330
|vpiTypedef:
\_enum_typespec: (bus_type_t), line:86
|vpiTypedef:
\_struct_typespec: (csr_inputs_t), line:396
|vpiTypedef:
\_enum_typespec: (csr_op_t), line:218
|vpiTypedef:
\_enum_typespec: (csr_t), line:201
|vpiTypedef:
\_struct_typespec: (data_access_shared_inputs_t), line:427
|vpiTypedef:
\_struct_typespec: (div_inputs_t), line:389
|vpiTypedef:
\_enum_typespec: (div_type), line:66
|vpiTypedef:
\_enum_typespec: (exception_code_t), line:245
|vpiTypedef:
\_struct_typespec: (exception_packet_t), line:263
|vpiTypedef:
\_struct_typespec: (fetch_buffer_packet_t), line:276
|vpiTypedef:
\_enum_typespec: (fifo_type_t), line:440
|vpiTypedef:
\_enum_typespec: (fn3_arith_t), line:76
|vpiTypedef:
\_enum_typespec: (fn3_branch_t), line:126
|vpiTypedef:
\_enum_typespec: (fn3_csr_t), line:212
|vpiTypedef:
\_enum_typespec: (fn3_ls_t), line:115
|vpiTypedef:
\_enum_typespec: (fn3_mul_div_t), line:138
|vpiTypedef:
\_struct_typespec: (gc_inputs_t), line:404
|vpiTypedef:
\_struct_typespec: (inflight_instruction_packet), line:271
|vpiTypedef:
\_logic_typespec: (instruction_id_t), line:30
|vpiTypedef:
\_enum_typespec: (interrupt_code_t), line:261
|vpiTypedef:
\_logic_typespec: (itag_entry_t), line:42
|vpiName:itag_entry_t
|vpiRange:
\_range: , line:42
|vpiLeftRange:
\_ref_obj: (ICACHE_TAG_W), line:42
|vpiName:ICACHE_TAG_W
|vpiRightRange:
\_constant: , line:42
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiTypedef:
\_struct_typespec: (load_store_inputs_t), line:369
|vpiTypedef:
\_struct_typespec: (mul_inputs_t), line:383
|vpiTypedef:
\_enum_typespec: (opcodes_t), line:48
|vpiTypedef:
\_enum_typespec: (opcodes_trimmed_t), line:65
|vpiTypedef:
\_struct_typespec: (simulation_named_regfile), line:476
|vpiTypedef:
\_struct_typespec: (taiga_trace_events_t), line:442
|vpiTypedef:
\_struct_typespec: (to_l1_arbiter_packet), line:418
|vpiTypedef:
\_struct_typespec: (trace_outputs_t), line:469
|vpiTypedef:
\_logic_typespec: (unit_id_t), line:31
|vpiTypedef:
\_struct_typespec: (unit_writeback_t), line:295
|vpiTypedef:
\_enum_typespec: (vm_t), line:223
|uhdmallModules:
\_module: work@l1_arbiter, file:third_party/cores/taiga/core/l1_arbiter.sv, line:27, parent:work@div_unit_core_wrapper
|vpiDefName:work@l1_arbiter
|vpiFullName:work@l1_arbiter
|vpiProcess:
\_always: , line:76
|vpiAlwaysType:2
|vpiStmt:
\_begin: , line:76
|vpiFullName:work@l1_arbiter
|vpiStmt:
\_assignment: , line:77
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (request_exists), line:77
|vpiName:request_exists
|vpiFullName:work@l1_arbiter.request_exists
|vpiRhs:
\_bit_select: (l1_request.request), line:77
|vpiName:l1_request.request
|vpiFullName:work@l1_arbiter.l1_request.request
|vpiIndex:
\_constant: , line:77
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiStmt:
\_assignment: , line:78
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_bit_select: (acks), line:78
|vpiName:acks
|vpiFullName:work@l1_arbiter.acks
|vpiIndex:
\_constant: , line:78
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiRhs:
\_operation: , line:78
|vpiOpType:28
|vpiOperand:
\_bit_select: (l1_request.request), line:78
|vpiName:l1_request.request
|vpiFullName:work@l1_arbiter.l1_request.request
|vpiIndex:
\_constant: , line:78
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiOperand:
\_ref_obj: (push_ready), line:78
|vpiName:push_ready
|vpiFullName:work@l1_arbiter.push_ready
|vpiStmt:
\_assignment: , line:79
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (busy), line:79
|vpiName:busy
|vpiFullName:work@l1_arbiter.busy
|vpiRhs:
\_bit_select: (l1_request.request), line:79
|vpiName:l1_request.request
|vpiFullName:work@l1_arbiter.l1_request.request
|vpiIndex:
\_constant: , line:79
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiStmt:
\_for_stmt: , line:80
|vpiFullName:work@l1_arbiter
|vpiCondition:
\_operation: , line:80
|vpiOpType:20
|vpiOperand:
\_ref_obj: (i), line:80
|vpiName:i
|vpiFullName:work@l1_arbiter.i
|vpiOperand:
\_ref_obj: (L1_CONNECTIONS), line:80
|vpiName:L1_CONNECTIONS
|vpiFullName:work@l1_arbiter.L1_CONNECTIONS
|vpiForInitStmt:
\_assign_stmt:
|vpiRhs:
\_constant: , line:80
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiLhs:
\_int_var: (i), line:80
|vpiName:i
|vpiFullName:work@l1_arbiter.i
|vpiForIncStmt:
\_operation: , line:80
|vpiOpType:62
|vpiOperand:
\_ref_obj: (i), line:80
|vpiName:i
|vpiStmt:
\_begin: , line:80
|vpiFullName:work@l1_arbiter
|vpiStmt:
\_assignment: , line:81
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (request_exists), line:81
|vpiName:request_exists
|vpiFullName:work@l1_arbiter.request_exists
|vpiRhs:
\_bit_select: (requests), line:81
|vpiName:requests
|vpiFullName:work@l1_arbiter.requests
|vpiIndex:
\_ref_obj: (i), line:81
|vpiName:i
|vpiStmt:
\_assignment: , line:82
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_bit_select: (acks), line:82
|vpiName:acks
|vpiFullName:work@l1_arbiter.acks
|vpiIndex:
\_ref_obj: (i), line:82
|vpiName:i
|vpiRhs:
\_operation: , line:82
|vpiOpType:28
|vpiOperand:
\_operation: , line:82
|vpiOpType:28
|vpiOperand:
\_bit_select: (requests), line:82
|vpiName:requests
|vpiFullName:work@l1_arbiter.requests
|vpiIndex:
\_ref_obj: (i), line:82
|vpiName:i
|vpiOperand:
\_ref_obj: (push_ready), line:82
|vpiName:push_ready
|vpiFullName:work@l1_arbiter.push_ready
|vpiOperand:
\_operation: , line:82
|vpiOpType:4
|vpiOperand:
\_ref_obj: (busy), line:82
|vpiName:busy
|vpiFullName:work@l1_arbiter.busy
|vpiStmt:
\_assignment: , line:83
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (busy), line:83
|vpiName:busy
|vpiFullName:work@l1_arbiter.busy
|vpiRhs:
\_bit_select: (requests), line:83
|vpiName:requests
|vpiFullName:work@l1_arbiter.requests
|vpiIndex:
\_ref_obj: (i), line:83
|vpiName:i
|vpiProcess:
\_always: , line:158
|vpiAlwaysType:2
|vpiStmt:
\_begin: , line:158
|vpiFullName:work@l1_arbiter
|vpiStmt:
\_assignment: , line:160
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (l2.addr), line:160
|vpiName:l2.addr
|vpiFullName:work@l1_arbiter.l2.addr
|vpiRhs:
\_bit_select: (l2_requests.addr), line:160
|vpiName:l2_requests.addr
|vpiFullName:work@l1_arbiter.l2_requests.addr
|vpiIndex:
\_operation: , line:160
|vpiOpType:11
|vpiOperand:
\_ref_obj: (L1_CONNECTIONS), line:160
|vpiName:L1_CONNECTIONS
|vpiOperand:
\_constant: , line:160
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiStmt:
\_assignment: , line:161
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (l2.rnw), line:161
|vpiName:l2.rnw
|vpiFullName:work@l1_arbiter.l2.rnw
|vpiRhs:
\_bit_select: (l2_requests.rnw), line:161
|vpiName:l2_requests.rnw
|vpiFullName:work@l1_arbiter.l2_requests.rnw
|vpiIndex:
\_operation: , line:161
|vpiOpType:11
|vpiOperand:
\_ref_obj: (L1_CONNECTIONS), line:161
|vpiName:L1_CONNECTIONS
|vpiOperand:
\_constant: , line:161
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiStmt:
\_assignment: , line:162
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (l2.be), line:162
|vpiName:l2.be
|vpiFullName:work@l1_arbiter.l2.be
|vpiRhs:
\_bit_select: (l2_requests.be), line:162
|vpiName:l2_requests.be
|vpiFullName:work@l1_arbiter.l2_requests.be
|vpiIndex:
\_operation: , line:162
|vpiOpType:11
|vpiOperand:
\_ref_obj: (L1_CONNECTIONS), line:162
|vpiName:L1_CONNECTIONS
|vpiOperand:
\_constant: , line:162
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiStmt:
\_assignment: , line:163
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (l2.is_amo), line:163
|vpiName:l2.is_amo
|vpiFullName:work@l1_arbiter.l2.is_amo
|vpiRhs:
\_bit_select: (l2_requests.is_amo), line:163
|vpiName:l2_requests.is_amo
|vpiFullName:work@l1_arbiter.l2_requests.is_amo
|vpiIndex:
\_operation: , line:163
|vpiOpType:11
|vpiOperand:
\_ref_obj: (L1_CONNECTIONS), line:163
|vpiName:L1_CONNECTIONS
|vpiOperand:
\_constant: , line:163
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiStmt:
\_assignment: , line:164
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (l2.amo_type_or_burst_size), line:164
|vpiName:l2.amo_type_or_burst_size
|vpiFullName:work@l1_arbiter.l2.amo_type_or_burst_size
|vpiRhs:
\_bit_select: (l2_requests.amo_type_or_burst_size), line:164
|vpiName:l2_requests.amo_type_or_burst_size
|vpiFullName:work@l1_arbiter.l2_requests.amo_type_or_burst_size
|vpiIndex:
\_operation: , line:164
|vpiOpType:11
|vpiOperand:
\_ref_obj: (L1_CONNECTIONS), line:164
|vpiName:L1_CONNECTIONS
|vpiOperand:
\_constant: , line:164
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiStmt:
\_assignment: , line:165
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (l2.sub_id), line:165
|vpiName:l2.sub_id
|vpiFullName:work@l1_arbiter.l2.sub_id
|vpiRhs:
\_bit_select: (l2_requests.sub_id), line:165
|vpiName:l2_requests.sub_id
|vpiFullName:work@l1_arbiter.l2_requests.sub_id
|vpiIndex:
\_operation: , line:165
|vpiOpType:11
|vpiOperand:
\_ref_obj: (L1_CONNECTIONS), line:165
|vpiName:L1_CONNECTIONS
|vpiOperand:
\_constant: , line:165
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiStmt:
\_for_stmt: , line:166
|vpiFullName:work@l1_arbiter
|vpiCondition:
\_operation: , line:166
|vpiOpType:19
|vpiOperand:
\_ref_obj: (i), line:166
|vpiName:i
|vpiFullName:work@l1_arbiter.i
|vpiOperand:
\_constant: , line:166
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiForInitStmt:
\_assign_stmt:
|vpiRhs:
\_operation: , line:166
|vpiOpType:11
|vpiOperand:
\_ref_obj: (L1_CONNECTIONS), line:166
|vpiName:L1_CONNECTIONS
|vpiFullName:work@l1_arbiter.L1_CONNECTIONS
|vpiOperand:
\_constant: , line:166
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiLhs:
\_int_var: (i), line:166
|vpiName:i
|vpiFullName:work@l1_arbiter.i
|vpiForIncStmt:
\_operation: , line:166
|vpiOpType:64
|vpiOperand:
\_ref_obj: (i), line:166
|vpiName:i
|vpiStmt:
\_begin: , line:166
|vpiFullName:work@l1_arbiter
|vpiStmt:
\_if_stmt: , line:167
|vpiCondition:
\_bit_select: (requests), line:167
|vpiName:requests
|vpiFullName:work@l1_arbiter.requests
|vpiIndex:
\_ref_obj: (i), line:167
|vpiName:i
|vpiStmt:
\_begin: , line:167
|vpiFullName:work@l1_arbiter
|vpiStmt:
\_assignment: , line:169
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (l2.addr), line:169
|vpiName:l2.addr
|vpiFullName:work@l1_arbiter.l2.addr
|vpiRhs:
\_bit_select: (l2_requests.addr), line:169
|vpiName:l2_requests.addr
|vpiFullName:work@l1_arbiter.l2_requests.addr
|vpiIndex:
\_ref_obj: (i), line:169
|vpiName:i
|vpiStmt:
\_assignment: , line:170
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (l2.rnw), line:170
|vpiName:l2.rnw
|vpiFullName:work@l1_arbiter.l2.rnw
|vpiRhs:
\_bit_select: (l2_requests.rnw), line:170
|vpiName:l2_requests.rnw
|vpiFullName:work@l1_arbiter.l2_requests.rnw
|vpiIndex:
\_ref_obj: (i), line:170
|vpiName:i
|vpiStmt:
\_assignment: , line:171
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (l2.be), line:171
|vpiName:l2.be
|vpiFullName:work@l1_arbiter.l2.be
|vpiRhs:
\_bit_select: (l2_requests.be), line:171
|vpiName:l2_requests.be
|vpiFullName:work@l1_arbiter.l2_requests.be
|vpiIndex:
\_ref_obj: (i), line:171
|vpiName:i
|vpiStmt:
\_assignment: , line:172
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (l2.is_amo), line:172
|vpiName:l2.is_amo
|vpiFullName:work@l1_arbiter.l2.is_amo
|vpiRhs:
\_bit_select: (l2_requests.is_amo), line:172
|vpiName:l2_requests.is_amo
|vpiFullName:work@l1_arbiter.l2_requests.is_amo
|vpiIndex:
\_ref_obj: (i), line:172
|vpiName:i
|vpiStmt:
\_assignment: , line:173
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (l2.amo_type_or_burst_size), line:173
|vpiName:l2.amo_type_or_burst_size
|vpiFullName:work@l1_arbiter.l2.amo_type_or_burst_size
|vpiRhs:
\_bit_select: (l2_requests.amo_type_or_burst_size), line:173
|vpiName:l2_requests.amo_type_or_burst_size
|vpiFullName:work@l1_arbiter.l2_requests.amo_type_or_burst_size
|vpiIndex:
\_ref_obj: (i), line:173
|vpiName:i
|vpiStmt:
\_assignment: , line:174
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (l2.sub_id), line:174
|vpiName:l2.sub_id
|vpiFullName:work@l1_arbiter.l2.sub_id
|vpiRhs:
\_bit_select: (l2_requests.sub_id), line:174
|vpiName:l2_requests.sub_id
|vpiFullName:work@l1_arbiter.l2_requests.sub_id
|vpiIndex:
\_ref_obj: (i), line:174
|vpiName:i
|vpiPort:
\_port: (clk), line:29
|vpiName:clk
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (clk), line:29
|vpiName:clk
|vpiFullName:work@l1_arbiter.clk
|vpiNetType:36
|vpiPort:
\_port: (rst), line:30
|vpiName:rst
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (rst), line:30
|vpiName:rst
|vpiFullName:work@l1_arbiter.rst
|vpiNetType:36
|vpiPort:
\_port: (l2), line:32
|vpiName:l2
|vpiDirection:5
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_modport: (master)
|vpiPort:
\_port: (sc_complete), line:34
|vpiName:sc_complete
|vpiDirection:2
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (sc_complete), line:34
|vpiName:sc_complete
|vpiFullName:work@l1_arbiter.sc_complete
|vpiPort:
\_port: (sc_success), line:35
|vpiName:sc_success
|vpiDirection:2
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (sc_success), line:35
|vpiName:sc_success
|vpiFullName:work@l1_arbiter.sc_success
|vpiPort:
\_port: (l1_request), line:37
|vpiName:l1_request
|vpiDirection:5
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_modport: (slave)
|vpiPort:
\_port: (l1_response), line:38
|vpiName:l1_response
|vpiDirection:5
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_modport: (slave)
|vpiContAssign:
\_cont_assign: , line:67
|vpiRhs:
\_ref_obj: (l2.rd_data_valid), line:67
|vpiName:l2.rd_data_valid
|vpiFullName:work@l1_arbiter.l2.rd_data_valid
|vpiLhs:
\_ref_obj: (l2.rd_data_ack), line:67
|vpiName:l2.rd_data_ack
|vpiFullName:work@l1_arbiter.l2.rd_data_ack
|vpiContAssign:
\_cont_assign: , line:68
|vpiRhs:
\_ref_obj: (l2.con_valid), line:68
|vpiName:l2.con_valid
|vpiFullName:work@l1_arbiter.l2.con_valid
|vpiLhs:
\_ref_obj: (sc_complete), line:68
|vpiName:sc_complete
|vpiFullName:work@l1_arbiter.sc_complete
|vpiContAssign:
\_cont_assign: , line:69
|vpiRhs:
\_ref_obj: (l2.con_result), line:69
|vpiName:l2.con_result
|vpiFullName:work@l1_arbiter.l2.con_result
|vpiLhs:
\_ref_obj: (sc_success), line:69
|vpiName:sc_success
|vpiFullName:work@l1_arbiter.sc_success
|vpiContAssign:
\_cont_assign: , line:72
|vpiRhs:
\_operation: , line:72
|vpiOpType:28
|vpiOperand:
\_operation: , line:72
|vpiOpType:4
|vpiOperand:
\_ref_obj: (l2.request_full), line:72
|vpiName:l2.request_full
|vpiFullName:work@l1_arbiter.l2.request_full
|vpiOperand:
\_operation: , line:72
|vpiOpType:4
|vpiOperand:
\_ref_obj: (l2.data_full), line:72
|vpiName:l2.data_full
|vpiFullName:work@l1_arbiter.l2.data_full
|vpiLhs:
\_ref_obj: (push_ready), line:72
|vpiName:push_ready
|vpiFullName:work@l1_arbiter.push_ready
|vpiContAssign:
\_cont_assign: , line:87
|vpiRhs:
\_operation: , line:87
|vpiOpType:28
|vpiOperand:
\_ref_obj: (push_ready), line:87
|vpiName:push_ready
|vpiFullName:work@l1_arbiter.push_ready
|vpiOperand:
\_ref_obj: (request_exists), line:87
|vpiName:request_exists
|vpiFullName:work@l1_arbiter.request_exists
|vpiLhs:
\_ref_obj: (l2.request_push), line:87
|vpiName:l2.request_push
|vpiFullName:work@l1_arbiter.l2.request_push
|vpiNet:
\_logic_net: (clk), line:29
|vpiNet:
\_logic_net: (rst), line:30
|vpiNet:
\_logic_net: (sc_complete), line:34
|vpiNet:
\_logic_net: (sc_success), line:35
|vpiNet:
\_logic_net: (l2_requests), line:41
|vpiName:l2_requests
|vpiFullName:work@l1_arbiter.l2_requests
|vpiNet:
\_logic_net: (requests), line:43
|vpiName:requests
|vpiFullName:work@l1_arbiter.requests
|vpiNetType:36
|vpiNet:
\_logic_net: (acks), line:44
|vpiName:acks
|vpiFullName:work@l1_arbiter.acks
|vpiNetType:36
|vpiNet:
\_logic_net: (push_ready), line:46
|vpiName:push_ready
|vpiFullName:work@l1_arbiter.push_ready
|vpiNetType:36
|vpiNet:
\_logic_net: (request_exists), line:47
|vpiName:request_exists
|vpiFullName:work@l1_arbiter.request_exists
|vpiNetType:36
|vpiNet:
\_logic_net: (busy), line:75
|vpiName:busy
|vpiFullName:work@l1_arbiter.busy
|vpiNetType:36
|vpiNet:
\_logic_net: (l2), line:32
|vpiName:l2
|vpiFullName:work@l1_arbiter.l2
|vpiNet:
\_logic_net: (l1_request), line:37
|vpiName:l1_request
|vpiFullName:work@l1_arbiter.l1_request
|vpiNet:
\_logic_net: (l1_response), line:38
|vpiName:l1_response
|vpiFullName:work@l1_arbiter.l1_response
|vpiTypedef:
\_struct_typespec: (alu_inputs_t), line:301
|vpiTypedef:
\_enum_typespec: (alu_logic_op_t), line:84
|vpiTypedef:
\_enum_typespec: (alu_op_t), line:91
|vpiTypedef:
\_enum_typespec: (alu_rs1_op_t), line:97
|vpiTypedef:
\_enum_typespec: (alu_rs2_op_t), line:104
|vpiTypedef:
\_struct_typespec: (amo_alu_inputs_t), line:356
|vpiTypedef:
\_struct_typespec: (amo_details_t), line:362
|vpiTypedef:
\_enum_typespec: (amo_t), line:354
|vpiTypedef:
\_struct_typespec: (branch_inputs_t), line:313
|vpiTypedef:
\_logic_typespec: (branch_predictor_metadata_t), line:32
|vpiTypedef:
\_struct_typespec: (branch_results_t), line:330
|vpiTypedef:
\_enum_typespec: (bus_type_t), line:86
|vpiTypedef:
\_struct_typespec: (csr_inputs_t), line:396
|vpiTypedef:
\_enum_typespec: (csr_op_t), line:218
|vpiTypedef:
\_enum_typespec: (csr_t), line:201
|vpiTypedef:
\_struct_typespec: (data_access_shared_inputs_t), line:427
|vpiTypedef:
\_struct_typespec: (div_inputs_t), line:389
|vpiTypedef:
\_enum_typespec: (div_type), line:66
|vpiTypedef:
\_enum_typespec: (exception_code_t), line:245
|vpiTypedef:
\_struct_typespec: (exception_packet_t), line:263
|vpiTypedef:
\_struct_typespec: (fetch_buffer_packet_t), line:276
|vpiTypedef:
\_enum_typespec: (fifo_type_t), line:440
|vpiTypedef:
\_enum_typespec: (fn3_arith_t), line:76
|vpiTypedef:
\_enum_typespec: (fn3_branch_t), line:126
|vpiTypedef:
\_enum_typespec: (fn3_csr_t), line:212
|vpiTypedef:
\_enum_typespec: (fn3_ls_t), line:115
|vpiTypedef:
\_enum_typespec: (fn3_mul_div_t), line:138
|vpiTypedef:
\_struct_typespec: (gc_inputs_t), line:404
|vpiTypedef:
\_struct_typespec: (inflight_instruction_packet), line:271
|vpiTypedef:
\_logic_typespec: (instruction_id_t), line:30
|vpiTypedef:
\_enum_typespec: (interrupt_code_t), line:261
|vpiTypedef:
\_struct_typespec: (l2_data_attributes_t), line:68
|vpiTypedef:
\_struct_typespec: (l2_mem_request_t), line:58
|vpiTypedef:
\_struct_typespec: (l2_mem_return_data_t), line:75
|vpiTypedef:
\_struct_typespec: (l2_request_t), line:49
|vpiTypedef:
\_struct_typespec: (l2_return_data_t), line:81
|vpiTypedef:
\_struct_typespec: (load_store_inputs_t), line:369
|vpiTypedef:
\_struct_typespec: (mul_inputs_t), line:383
|vpiTypedef:
\_enum_typespec: (opcodes_t), line:48
|vpiTypedef:
\_enum_typespec: (opcodes_trimmed_t), line:65
|vpiTypedef:
\_struct_typespec: (simulation_named_regfile), line:476
|vpiTypedef:
\_struct_typespec: (taiga_trace_events_t), line:442
|vpiTypedef:
\_struct_typespec: (to_l1_arbiter_packet), line:418
|vpiTypedef:
\_struct_typespec: (trace_outputs_t), line:469
|vpiTypedef:
\_logic_typespec: (unit_id_t), line:31
|vpiTypedef:
\_struct_typespec: (unit_writeback_t), line:295
|vpiTypedef:
\_enum_typespec: (vm_t), line:223
|uhdmallModules:
\_module: work@l2_arbiter, file:third_party/cores/taiga/l2_arbiter/l2_arbiter.sv, line:26, parent:work@div_unit_core_wrapper
|vpiDefName:work@l2_arbiter
|vpiFullName:work@l2_arbiter
|vpiProcess:
\_always: , line:172
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:172
|vpiCondition:
\_operation: , line:172
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:172
|vpiName:clk
|vpiFullName:work@l2_arbiter.clk
|vpiStmt:
\_begin: , line:172
|vpiFullName:work@l2_arbiter
|vpiStmt:
\_if_stmt: , line:173
|vpiCondition:
\_ref_obj: (advance), line:173
|vpiName:advance
|vpiFullName:work@l2_arbiter.advance
|vpiStmt:
\_begin: , line:173
|vpiFullName:work@l2_arbiter
|vpiStmt:
\_assignment: , line:174
|vpiOpType:82
|vpiLhs:
\_ref_obj: (reserv_request), line:174
|vpiName:reserv_request
|vpiFullName:work@l2_arbiter.reserv_request
|vpiRhs:
\_bit_select: (requests), line:174
|vpiName:requests
|vpiFullName:work@l2_arbiter.requests
|vpiIndex:
\_ref_obj: (arb.grantee_i), line:174
|vpiName:arb.grantee_i
|vpiStmt:
\_assignment: , line:175
|vpiOpType:82
|vpiLhs:
\_ref_obj: (reserv_id), line:175
|vpiName:reserv_id
|vpiFullName:work@l2_arbiter.reserv_id
|vpiRhs:
\_ref_obj: (arb.grantee_i), line:175
|vpiName:arb.grantee_i
|vpiFullName:work@l2_arbiter.arb.grantee_i
|vpiStmt:
\_assignment: , line:176
|vpiOpType:82
|vpiLhs:
\_ref_obj: (reserv_id_v), line:176
|vpiName:reserv_id_v
|vpiFullName:work@l2_arbiter.reserv_id_v
|vpiRhs:
\_ref_obj: (arb.grantee_v), line:176
|vpiName:arb.grantee_v
|vpiFullName:work@l2_arbiter.arb.grantee_v
|vpiProcess:
\_always: , line:180
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:180
|vpiCondition:
\_operation: , line:180
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:180
|vpiName:clk
|vpiFullName:work@l2_arbiter.clk
|vpiStmt:
\_begin: , line:180
|vpiFullName:work@l2_arbiter
|vpiStmt:
\_if_else: , line:181
|vpiCondition:
\_ref_obj: (rst), line:181
|vpiName:rst
|vpiFullName:work@l2_arbiter.rst
|vpiStmt:
\_assignment: , line:182
|vpiOpType:82
|vpiLhs:
\_ref_obj: (reserv_valid), line:182
|vpiName:reserv_valid
|vpiFullName:work@l2_arbiter.reserv_valid
|vpiRhs:
\_constant: , line:182
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiElseStmt:
\_assignment: , line:184
|vpiOpType:82
|vpiLhs:
\_ref_obj: (reserv_valid), line:184
|vpiName:reserv_valid
|vpiFullName:work@l2_arbiter.reserv_valid
|vpiRhs:
\_ref_obj: (advance), line:184
|vpiName:advance
|vpiFullName:work@l2_arbiter.advance
|vpiProcess:
\_always: , line:247
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:247
|vpiCondition:
\_operation: , line:247
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:247
|vpiName:clk
|vpiFullName:work@l2_arbiter.clk
|vpiStmt:
\_begin: , line:247
|vpiFullName:work@l2_arbiter
|vpiStmt:
\_if_else: , line:248
|vpiCondition:
\_ref_obj: (rst), line:248
|vpiName:rst
|vpiFullName:work@l2_arbiter.rst
|vpiStmt:
\_assignment: , line:249
|vpiOpType:82
|vpiLhs:
\_ref_obj: (burst_count), line:249
|vpiName:burst_count
|vpiFullName:work@l2_arbiter.burst_count
|vpiRhs:
\_constant: , line:249
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiElseStmt:
\_if_else: , line:250
|vpiCondition:
\_ref_obj: (write_done), line:250
|vpiName:write_done
|vpiFullName:work@l2_arbiter.write_done
|vpiStmt:
\_assignment: , line:251
|vpiOpType:82
|vpiLhs:
\_ref_obj: (burst_count), line:251
|vpiName:burst_count
|vpiFullName:work@l2_arbiter.burst_count
|vpiRhs:
\_constant: , line:251
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiElseStmt:
\_if_stmt: , line:252
|vpiCondition:
\_operation: , line:252
|vpiOpType:28
|vpiOperand:
\_ref_obj: (data_attributes.valid), line:252
|vpiName:data_attributes.valid
|vpiFullName:work@l2_arbiter.data_attributes.valid
|vpiOperand:
\_operation: , line:252
|vpiOpType:4
|vpiOperand:
\_ref_obj: (mem_data_fifo.full), line:252
|vpiName:mem_data_fifo.full
|vpiFullName:work@l2_arbiter.mem_data_fifo.full
|vpiStmt:
\_assignment: , line:253
|vpiOpType:82
|vpiLhs:
\_ref_obj: (burst_count), line:253
|vpiName:burst_count
|vpiFullName:work@l2_arbiter.burst_count
|vpiRhs:
\_operation: , line:253
|vpiOpType:24
|vpiOperand:
\_ref_obj: (burst_count), line:253
|vpiName:burst_count
|vpiFullName:work@l2_arbiter.burst_count
|vpiOperand:
\_constant: , line:253
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiProcess:
\_always: , line:277
|vpiAlwaysType:2
|vpiStmt:
\_begin: , line:277
|vpiFullName:work@l2_arbiter
|vpiStmt:
\_assignment: , line:278
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (return_push), line:278
|vpiName:return_push
|vpiFullName:work@l2_arbiter.return_push
|vpiRhs:
\_constant: , line:278
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiStmt:
\_assignment: , line:279
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_bit_select: (return_push), line:279
|vpiName:return_push
|vpiFullName:work@l2_arbiter.return_push
|vpiIndex:
\_ref_obj: (mem_return_data.id), line:279
|vpiName:mem_return_data.id
|vpiRhs:
\_ref_obj: (mem_returndata_fifo.valid), line:279
|vpiName:mem_returndata_fifo.valid
|vpiFullName:work@l2_arbiter.mem_returndata_fifo.valid
|vpiPort:
\_port: (clk), line:27
|vpiName:clk
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (clk), line:27
|vpiName:clk
|vpiFullName:work@l2_arbiter.clk
|vpiNetType:36
|vpiPort:
\_port: (rst), line:28
|vpiName:rst
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (rst), line:28
|vpiName:rst
|vpiFullName:work@l2_arbiter.rst
|vpiNetType:36
|vpiPort:
\_port: (request), line:30
|vpiName:request
|vpiDirection:5
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_modport: (slave)
|vpiPort:
\_port: (mem), line:31
|vpiName:mem
|vpiDirection:5
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_modport: (master)
|vpiContAssign:
\_cont_assign: , line:78
|vpiRhs:
\_ref_obj: (clk), line:78
|vpiName:clk
|vpiFullName:work@l2_arbiter.clk
|vpiLhs:
\_ref_obj: (wr_clk), line:78
|vpiName:wr_clk
|vpiFullName:work@l2_arbiter.wr_clk
|vpiContAssign:
\_cont_assign: , line:79
|vpiRhs:
\_ref_obj: (clk), line:79
|vpiName:clk
|vpiFullName:work@l2_arbiter.clk
|vpiLhs:
\_ref_obj: (rd_clk), line:79
|vpiName:rd_clk
|vpiFullName:work@l2_arbiter.rd_clk
|vpiContAssign:
\_cont_assign: , line:141
|vpiRhs:
\_operation: , line:141
|vpiOpType:28
|vpiOperand:
\_ref_obj: (arb.grantee_valid), line:141
|vpiName:arb.grantee_valid
|vpiFullName:work@l2_arbiter.arb.grantee_valid
|vpiOperand:
\_operation: , line:141
|vpiOpType:4
|vpiOperand:
\_ref_obj: (mem_addr_fifo.full), line:141
|vpiName:mem_addr_fifo.full
|vpiFullName:work@l2_arbiter.mem_addr_fifo.full
|vpiLhs:
\_ref_obj: (advance), line:141
|vpiName:advance
|vpiFullName:work@l2_arbiter.advance
|vpiContAssign:
\_cont_assign: , line:142
|vpiRhs:
\_ref_obj: (advance), line:142
|vpiName:advance
|vpiFullName:work@l2_arbiter.advance
|vpiLhs:
\_ref_obj: (arb.strobe), line:142
|vpiName:arb.strobe
|vpiFullName:work@l2_arbiter.arb.strobe
|vpiContAssign:
\_cont_assign: , line:143
|vpiRhs:
\_ref_obj: (advance), line:143
|vpiName:advance
|vpiFullName:work@l2_arbiter.advance
|vpiLhs:
\_ref_obj: (mem_addr_fifo.push), line:143
|vpiName:mem_addr_fifo.push
|vpiFullName:work@l2_arbiter.mem_addr_fifo.push
|vpiContAssign:
\_cont_assign: , line:144
|vpiRhs:
\_ref_obj: (mem.request_pop), line:144
|vpiName:mem.request_pop
|vpiFullName:work@l2_arbiter.mem.request_pop
|vpiLhs:
\_ref_obj: (mem_addr_fifo.pop), line:144
|vpiName:mem_addr_fifo.pop
|vpiFullName:work@l2_arbiter.mem_addr_fifo.pop
|vpiContAssign:
\_cont_assign: , line:145
|vpiRhs:
\_ref_obj: (mem_addr_fifo.valid), line:145
|vpiName:mem_addr_fifo.valid
|vpiFullName:work@l2_arbiter.mem_addr_fifo.valid
|vpiLhs:
\_ref_obj: (mem.request_valid), line:145
|vpiName:mem.request_valid
|vpiFullName:work@l2_arbiter.mem.request_valid
|vpiContAssign:
\_cont_assign: , line:147
|vpiRhs:
\_bit_select: (requests), line:147
|vpiName:requests
|vpiFullName:work@l2_arbiter.requests
|vpiIndex:
\_ref_obj: (arb.grantee_i), line:147
|vpiName:arb.grantee_i
|vpiLhs:
\_ref_obj: (arb_request), line:147
|vpiName:arb_request
|vpiFullName:work@l2_arbiter.arb_request
|vpiContAssign:
\_cont_assign: , line:149
|vpiRhs:
\_ref_obj: (arb_request.addr), line:149
|vpiName:arb_request.addr
|vpiFullName:work@l2_arbiter.arb_request.addr
|vpiLhs:
\_ref_obj: (mem_request.addr), line:149
|vpiName:mem_request.addr
|vpiFullName:work@l2_arbiter.mem_request.addr
|vpiContAssign:
\_cont_assign: , line:150
|vpiRhs:
\_ref_obj: (arb_request.be), line:150
|vpiName:arb_request.be
|vpiFullName:work@l2_arbiter.arb_request.be
|vpiLhs:
\_ref_obj: (mem_request.be), line:150
|vpiName:mem_request.be
|vpiFullName:work@l2_arbiter.mem_request.be
|vpiContAssign:
\_cont_assign: , line:151
|vpiRhs:
\_ref_obj: (arb_request.rnw), line:151
|vpiName:arb_request.rnw
|vpiFullName:work@l2_arbiter.arb_request.rnw
|vpiLhs:
\_ref_obj: (mem_request.rnw), line:151
|vpiName:mem_request.rnw
|vpiFullName:work@l2_arbiter.mem_request.rnw
|vpiContAssign:
\_cont_assign: , line:152
|vpiRhs:
\_ref_obj: (arb_request.is_amo), line:152
|vpiName:arb_request.is_amo
|vpiFullName:work@l2_arbiter.arb_request.is_amo
|vpiLhs:
\_ref_obj: (mem_request.is_amo), line:152
|vpiName:mem_request.is_amo
|vpiFullName:work@l2_arbiter.mem_request.is_amo
|vpiContAssign:
\_cont_assign: , line:153
|vpiRhs:
\_ref_obj: (arb_request.amo_type_or_burst_size), line:153
|vpiName:arb_request.amo_type_or_burst_size
|vpiFullName:work@l2_arbiter.arb_request.amo_type_or_burst_size
|vpiLhs:
\_ref_obj: (mem_request.amo_type_or_burst_size), line:153
|vpiName:mem_request.amo_type_or_burst_size
|vpiFullName:work@l2_arbiter.mem_request.amo_type_or_burst_size
|vpiContAssign:
\_cont_assign: , line:154
|vpiRhs:
\_operation: , line:154
|vpiOpType:33
|vpiOperand:
\_ref_obj: (arb.grantee_i), line:154
|vpiName:arb.grantee_i
|vpiOperand:
\_ref_obj: (arb_request.sub_id), line:154
|vpiName:arb_request.sub_id
|vpiLhs:
\_ref_obj: (mem_request.id), line:154
|vpiName:mem_request.id
|vpiFullName:work@l2_arbiter.mem_request.id
|vpiContAssign:
\_cont_assign: , line:156
|vpiRhs:
\_ref_obj: (mem_request), line:156
|vpiName:mem_request
|vpiFullName:work@l2_arbiter.mem_request
|vpiLhs:
\_ref_obj: (mem_addr_fifo.data_in), line:156
|vpiName:mem_addr_fifo.data_in
|vpiFullName:work@l2_arbiter.mem_addr_fifo.data_in
|vpiContAssign:
\_cont_assign: , line:159
|vpiRhs:
\_ref_obj: (mem_addr_fifo.data_out), line:159
|vpiName:mem_addr_fifo.data_out
|vpiFullName:work@l2_arbiter.mem_addr_fifo.data_out
|vpiLhs:
\_ref_obj: (mem_addr_fifo_data_out), line:159
|vpiName:mem_addr_fifo_data_out
|vpiFullName:work@l2_arbiter.mem_addr_fifo_data_out
|vpiContAssign:
\_cont_assign: , line:160
|vpiRhs:
\_ref_obj: (mem_addr_fifo_data_out.addr), line:160
|vpiName:mem_addr_fifo_data_out.addr
|vpiFullName:work@l2_arbiter.mem_addr_fifo_data_out.addr
|vpiLhs:
\_ref_obj: (mem.addr), line:160
|vpiName:mem.addr
|vpiFullName:work@l2_arbiter.mem.addr
|vpiContAssign:
\_cont_assign: , line:161
|vpiRhs:
\_ref_obj: (mem_addr_fifo_data_out.rnw), line:161
|vpiName:mem_addr_fifo_data_out.rnw
|vpiFullName:work@l2_arbiter.mem_addr_fifo_data_out.rnw
|vpiLhs:
\_ref_obj: (mem.rnw), line:161
|vpiName:mem.rnw
|vpiFullName:work@l2_arbiter.mem.rnw
|vpiContAssign:
\_cont_assign: , line:162
|vpiRhs:
\_ref_obj: (mem_addr_fifo_data_out.be), line:162
|vpiName:mem_addr_fifo_data_out.be
|vpiFullName:work@l2_arbiter.mem_addr_fifo_data_out.be
|vpiLhs:
\_ref_obj: (mem.be), line:162
|vpiName:mem.be
|vpiFullName:work@l2_arbiter.mem.be
|vpiContAssign:
\_cont_assign: , line:163
|vpiRhs:
\_ref_obj: (mem_addr_fifo_data_out.is_amo), line:163
|vpiName:mem_addr_fifo_data_out.is_amo
|vpiFullName:work@l2_arbiter.mem_addr_fifo_data_out.is_amo
|vpiLhs:
\_ref_obj: (mem.is_amo), line:163
|vpiName:mem.is_amo
|vpiFullName:work@l2_arbiter.mem.is_amo
|vpiContAssign:
\_cont_assign: , line:164
|vpiRhs:
\_ref_obj: (mem_addr_fifo_data_out.amo_type_or_burst_size), line:164
|vpiName:mem_addr_fifo_data_out.amo_type_or_burst_size
|vpiFullName:work@l2_arbiter.mem_addr_fifo_data_out.amo_type_or_burst_size
|vpiLhs:
\_ref_obj: (mem.amo_type_or_burst_size), line:164
|vpiName:mem.amo_type_or_burst_size
|vpiFullName:work@l2_arbiter.mem.amo_type_or_burst_size
|vpiContAssign:
\_cont_assign: , line:187
|vpiRhs:
\_operation: , line:187
|vpiOpType:26
|vpiOperand:
\_ref_obj: (reserv_request.is_amo), line:187
|vpiName:reserv_request.is_amo
|vpiFullName:work@l2_arbiter.reserv_request.is_amo
|vpiOperand:
\_operation: , line:187
|vpiOpType:14
|vpiOperand:
\_ref_obj: (reserv_request.amo_type_or_burst_size), line:187
|vpiName:reserv_request.amo_type_or_burst_size
|vpiFullName:work@l2_arbiter.reserv_request.amo_type_or_burst_size
|vpiOperand:
\_ref_obj: (AMO_LR), line:187
|vpiName:AMO_LR
|vpiFullName:work@l2_arbiter.AMO_LR
|vpiLhs:
\_ref_obj: (reserv_lr), line:187
|vpiName:reserv_lr
|vpiFullName:work@l2_arbiter.reserv_lr
|vpiContAssign:
\_cont_assign: , line:188
|vpiRhs:
\_operation: , line:188
|vpiOpType:26
|vpiOperand:
\_ref_obj: (reserv_request.is_amo), line:188
|vpiName:reserv_request.is_amo
|vpiFullName:work@l2_arbiter.reserv_request.is_amo
|vpiOperand:
\_operation: , line:188
|vpiOpType:14
|vpiOperand:
\_ref_obj: (reserv_request.amo_type_or_burst_size), line:188
|vpiName:reserv_request.amo_type_or_burst_size
|vpiFullName:work@l2_arbiter.reserv_request.amo_type_or_burst_size
|vpiOperand:
\_ref_obj: (AMO_SC), line:188
|vpiName:AMO_SC
|vpiFullName:work@l2_arbiter.AMO_SC
|vpiLhs:
\_ref_obj: (reserv_sc), line:188
|vpiName:reserv_sc
|vpiFullName:work@l2_arbiter.reserv_sc
|vpiContAssign:
\_cont_assign: , line:189
|vpiRhs:
\_operation: , line:189
|vpiOpType:29
|vpiOperand:
\_operation: , line:189
|vpiOpType:4
|vpiOperand:
\_ref_obj: (reserv_request.rnw), line:189
|vpiName:reserv_request.rnw
|vpiFullName:work@l2_arbiter.reserv_request.rnw
|vpiOperand:
\_operation: , line:189
|vpiOpType:26
|vpiOperand:
\_ref_obj: (reserv_request.is_amo), line:189
|vpiName:reserv_request.is_amo
|vpiFullName:work@l2_arbiter.reserv_request.is_amo
|vpiOperand:
\_operation: , line:189
|vpiOpType:15
|vpiOperand:
\_ref_obj: (reserv_request.amo_type_or_burst_size), line:189
|vpiName:reserv_request.amo_type_or_burst_size
|vpiFullName:work@l2_arbiter.reserv_request.amo_type_or_burst_size
|vpiOperand:
\_ref_obj: (AMO_LR), line:189
|vpiName:AMO_LR
|vpiFullName:work@l2_arbiter.AMO_LR
|vpiLhs:
\_ref_obj: (reserv_store), line:189
|vpiName:reserv_store
|vpiFullName:work@l2_arbiter.reserv_store
|vpiContAssign:
\_cont_assign: , line:235
|vpiRhs:
\_ref_obj: (reserv_id), line:235
|vpiName:reserv_id
|vpiFullName:work@l2_arbiter.reserv_id
|vpiLhs:
\_ref_obj: (new_attr.id), line:235
|vpiName:new_attr.id
|vpiFullName:work@l2_arbiter.new_attr.id
|vpiContAssign:
\_cont_assign: , line:236
|vpiRhs:
\_ref_obj: (reserv_request.amo_type_or_burst_size), line:236
|vpiName:reserv_request.amo_type_or_burst_size
|vpiFullName:work@l2_arbiter.reserv_request.amo_type_or_burst_size
|vpiLhs:
\_ref_obj: (new_attr.burst_size), line:236
|vpiName:new_attr.burst_size
|vpiFullName:work@l2_arbiter.new_attr.burst_size
|vpiContAssign:
\_cont_assign: , line:237
|vpiRhs:
\_ref_obj: (mem.abort), line:237
|vpiName:mem.abort
|vpiFullName:work@l2_arbiter.mem.abort
|vpiLhs:
\_ref_obj: (new_attr.abort), line:237
|vpiName:new_attr.abort
|vpiFullName:work@l2_arbiter.new_attr.abort
|vpiContAssign:
\_cont_assign: , line:239
|vpiRhs:
\_ref_obj: (new_attr), line:239
|vpiName:new_attr
|vpiFullName:work@l2_arbiter.new_attr
|vpiLhs:
\_ref_obj: (data_attributes.data_in), line:239
|vpiName:data_attributes.data_in
|vpiFullName:work@l2_arbiter.data_attributes.data_in
|vpiContAssign:
\_cont_assign: , line:240
|vpiRhs:
\_operation: , line:240
|vpiOpType:28
|vpiOperand:
\_operation: , line:240
|vpiOpType:28
|vpiOperand:
\_ref_obj: (reserv_valid), line:240
|vpiName:reserv_valid
|vpiFullName:work@l2_arbiter.reserv_valid
|vpiOperand:
\_operation: , line:240
|vpiOpType:4
|vpiOperand:
\_ref_obj: (reserv_request.rnw), line:240
|vpiName:reserv_request.rnw
|vpiFullName:work@l2_arbiter.reserv_request.rnw
|vpiOperand:
\_operation: , line:240
|vpiOpType:4
|vpiOperand:
\_ref_obj: (mem.abort), line:240
|vpiName:mem.abort
|vpiFullName:work@l2_arbiter.mem.abort
|vpiLhs:
\_ref_obj: (data_attributes.push), line:240
|vpiName:data_attributes.push
|vpiFullName:work@l2_arbiter.data_attributes.push
|vpiContAssign:
\_cont_assign: , line:244
|vpiRhs:
\_ref_obj: (write_done), line:244
|vpiName:write_done
|vpiFullName:work@l2_arbiter.write_done
|vpiLhs:
\_ref_obj: (data_attributes.pop), line:244
|vpiName:data_attributes.pop
|vpiFullName:work@l2_arbiter.data_attributes.pop
|vpiContAssign:
\_cont_assign: , line:245
|vpiRhs:
\_ref_obj: (data_attributes.data_out), line:245
|vpiName:data_attributes.data_out
|vpiFullName:work@l2_arbiter.data_attributes.data_out
|vpiLhs:
\_ref_obj: (current_attr), line:245
|vpiName:current_attr
|vpiFullName:work@l2_arbiter.current_attr
|vpiContAssign:
\_cont_assign: , line:256
|vpiRhs:
\_operation: , line:256
|vpiOpType:28
|vpiOperand:
\_operation: , line:256
|vpiOpType:28
|vpiOperand:
\_ref_obj: (data_attributes.valid), line:256
|vpiName:data_attributes.valid
|vpiFullName:work@l2_arbiter.data_attributes.valid
|vpiOperand:
\_operation: , line:256
|vpiOpType:4
|vpiOperand:
\_ref_obj: (mem_data_fifo.full), line:256
|vpiName:mem_data_fifo.full
|vpiFullName:work@l2_arbiter.mem_data_fifo.full
|vpiOperand:
\_operation: , line:256
|vpiOpType:14
|vpiOperand:
\_ref_obj: (burst_count), line:256
|vpiName:burst_count
|vpiFullName:work@l2_arbiter.burst_count
|vpiOperand:
\_ref_obj: (current_attr.burst_size), line:256
|vpiName:current_attr.burst_size
|vpiFullName:work@l2_arbiter.current_attr.burst_size
|vpiLhs:
\_ref_obj: (write_done), line:256
|vpiName:write_done
|vpiFullName:work@l2_arbiter.write_done
|vpiContAssign:
\_cont_assign: , line:260
|vpiRhs:
\_operation: , line:260
|vpiOpType:28
|vpiOperand:
\_operation: , line:260
|vpiOpType:28
|vpiOperand:
\_ref_obj: (data_attributes.valid), line:260
|vpiName:data_attributes.valid
|vpiFullName:work@l2_arbiter.data_attributes.valid
|vpiOperand:
\_operation: , line:260
|vpiOpType:4
|vpiOperand:
\_ref_obj: (mem_data_fifo.full), line:260
|vpiName:mem_data_fifo.full
|vpiFullName:work@l2_arbiter.mem_data_fifo.full
|vpiOperand:
\_operation: , line:260
|vpiOpType:4
|vpiOperand:
\_ref_obj: (current_attr.abort), line:260
|vpiName:current_attr.abort
|vpiFullName:work@l2_arbiter.current_attr.abort
|vpiLhs:
\_ref_obj: (mem_data_fifo.push), line:260
|vpiName:mem_data_fifo.push
|vpiFullName:work@l2_arbiter.mem_data_fifo.push
|vpiContAssign:
\_cont_assign: , line:261
|vpiRhs:
\_bit_select: (input_data), line:261
|vpiName:input_data
|vpiFullName:work@l2_arbiter.input_data
|vpiIndex:
\_ref_obj: (current_attr.id), line:261
|vpiName:current_attr.id
|vpiLhs:
\_ref_obj: (mem_data_fifo.data_in), line:261
|vpiName:mem_data_fifo.data_in
|vpiFullName:work@l2_arbiter.mem_data_fifo.data_in
|vpiContAssign:
\_cont_assign: , line:263
|vpiRhs:
\_ref_obj: (mem_data_fifo.data_out), line:263
|vpiName:mem_data_fifo.data_out
|vpiFullName:work@l2_arbiter.mem_data_fifo.data_out
|vpiLhs:
\_ref_obj: (mem.wr_data), line:263
|vpiName:mem.wr_data
|vpiFullName:work@l2_arbiter.mem.wr_data
|vpiContAssign:
\_cont_assign: , line:264
|vpiRhs:
\_ref_obj: (mem_data_fifo.valid), line:264
|vpiName:mem_data_fifo.valid
|vpiFullName:work@l2_arbiter.mem_data_fifo.valid
|vpiLhs:
\_ref_obj: (mem.wr_data_valid), line:264
|vpiName:mem.wr_data_valid
|vpiFullName:work@l2_arbiter.mem.wr_data_valid
|vpiContAssign:
\_cont_assign: , line:265
|vpiRhs:
\_ref_obj: (mem.wr_data_read), line:265
|vpiName:mem.wr_data_read
|vpiFullName:work@l2_arbiter.mem.wr_data_read
|vpiLhs:
\_ref_obj: (mem_data_fifo.pop), line:265
|vpiName:mem_data_fifo.pop
|vpiFullName:work@l2_arbiter.mem_data_fifo.pop
|vpiContAssign:
\_cont_assign: , line:272
|vpiRhs:
\_ref_obj: (mem.rd_data_valid), line:272
|vpiName:mem.rd_data_valid
|vpiFullName:work@l2_arbiter.mem.rd_data_valid
|vpiLhs:
\_ref_obj: (mem_returndata_fifo.push), line:272
|vpiName:mem_returndata_fifo.push
|vpiFullName:work@l2_arbiter.mem_returndata_fifo.push
|vpiContAssign:
\_cont_assign: , line:273
|vpiRhs:
\_operation: , line:273
|vpiOpType:33
|vpiOperand:
\_ref_obj: (mem.rd_id), line:273
|vpiName:mem.rd_id
|vpiOperand:
\_ref_obj: (mem.rd_data), line:273
|vpiName:mem.rd_data
|vpiLhs:
\_ref_obj: (mem_returndata_fifo.data_in), line:273
|vpiName:mem_returndata_fifo.data_in
|vpiFullName:work@l2_arbiter.mem_returndata_fifo.data_in
|vpiContAssign:
\_cont_assign: , line:274
|vpiRhs:
\_ref_obj: (mem_returndata_fifo.data_out), line:274
|vpiName:mem_returndata_fifo.data_out
|vpiFullName:work@l2_arbiter.mem_returndata_fifo.data_out
|vpiLhs:
\_ref_obj: (mem_return_data), line:274
|vpiName:mem_return_data
|vpiFullName:work@l2_arbiter.mem_return_data
|vpiContAssign:
\_cont_assign: , line:275
|vpiRhs:
\_ref_obj: (mem_returndata_fifo.valid), line:275
|vpiName:mem_returndata_fifo.valid
|vpiFullName:work@l2_arbiter.mem_returndata_fifo.valid
|vpiLhs:
\_ref_obj: (mem_returndata_fifo.pop), line:275
|vpiName:mem_returndata_fifo.pop
|vpiFullName:work@l2_arbiter.mem_returndata_fifo.pop
|vpiNet:
\_logic_net: (clk), line:27
|vpiNet:
\_logic_net: (rst), line:28
|vpiNet:
\_logic_net: (mem_addr_fifo_data_out), line:50
|vpiName:mem_addr_fifo_data_out
|vpiFullName:work@l2_arbiter.mem_addr_fifo_data_out
|vpiNet:
\_logic_net: (requests_in), line:51
|vpiName:requests_in
|vpiFullName:work@l2_arbiter.requests_in
|vpiNet:
\_logic_net: (advance), line:53
|vpiName:advance
|vpiFullName:work@l2_arbiter.advance
|vpiNetType:36
|vpiNet:
\_logic_net: (arb_request), line:54
|vpiName:arb_request
|vpiFullName:work@l2_arbiter.arb_request
|vpiNet:
\_logic_net: (mem_request), line:55
|vpiName:mem_request
|vpiFullName:work@l2_arbiter.mem_request
|vpiNet:
\_logic_net: (reserv_valid), line:57
|vpiName:reserv_valid
|vpiFullName:work@l2_arbiter.reserv_valid
|vpiNetType:36
|vpiNet:
\_logic_net: (reserv_lr), line:58
|vpiName:reserv_lr
|vpiFullName:work@l2_arbiter.reserv_lr
|vpiNetType:36
|vpiNet:
\_logic_net: (reserv_sc), line:59
|vpiName:reserv_sc
|vpiFullName:work@l2_arbiter.reserv_sc
|vpiNetType:36
|vpiNet:
\_logic_net: (reserv_store), line:60
|vpiName:reserv_store
|vpiFullName:work@l2_arbiter.reserv_store
|vpiNetType:36
|vpiNet:
\_logic_net: (requests), line:61
|vpiName:requests
|vpiFullName:work@l2_arbiter.requests
|vpiNet:
\_logic_net: (reserv_request), line:62
|vpiName:reserv_request
|vpiFullName:work@l2_arbiter.reserv_request
|vpiNet:
\_logic_net: (reserv_id), line:63
|vpiName:reserv_id
|vpiFullName:work@l2_arbiter.reserv_id
|vpiNetType:36
|vpiNet:
\_logic_net: (reserv_id_v), line:64
|vpiName:reserv_id_v
|vpiFullName:work@l2_arbiter.reserv_id_v
|vpiNetType:36
|vpiNet:
\_logic_net: (write_done), line:66
|vpiName:write_done
|vpiFullName:work@l2_arbiter.write_done
|vpiNetType:36
|vpiNet:
\_logic_net: (burst_count), line:67
|vpiName:burst_count
|vpiFullName:work@l2_arbiter.burst_count
|vpiNetType:36
|vpiNet:
\_logic_net: (new_attr), line:68
|vpiName:new_attr
|vpiFullName:work@l2_arbiter.new_attr
|vpiNet:
\_logic_net: (current_attr), line:69
|vpiName:current_attr
|vpiFullName:work@l2_arbiter.current_attr
|vpiNet:
\_logic_net: (input_data), line:71
|vpiName:input_data
|vpiFullName:work@l2_arbiter.input_data
|vpiNetType:36
|vpiNet:
\_logic_net: (mem_return_data), line:73
|vpiName:mem_return_data
|vpiFullName:work@l2_arbiter.mem_return_data
|vpiNet:
\_logic_net: (return_data), line:74
|vpiName:return_data
|vpiFullName:work@l2_arbiter.return_data
|vpiNet:
\_logic_net: (return_push), line:75
|vpiName:return_push
|vpiFullName:work@l2_arbiter.return_push
|vpiNetType:36
|vpiNet:
\_logic_net: (wr_clk), line:77
|vpiName:wr_clk
|vpiFullName:work@l2_arbiter.wr_clk
|vpiNetType:36
|vpiNet:
\_logic_net: (rd_clk), line:77
|vpiName:rd_clk
|vpiFullName:work@l2_arbiter.rd_clk
|vpiNetType:36
|vpiNet:
\_logic_net: (request), line:30
|vpiName:request
|vpiFullName:work@l2_arbiter.request
|vpiNet:
\_logic_net: (mem), line:31
|vpiName:mem
|vpiFullName:work@l2_arbiter.mem
|vpiTypedef:
\_struct_typespec: (alu_inputs_t), line:301
|vpiTypedef:
\_enum_typespec: (alu_logic_op_t), line:84
|vpiTypedef:
\_enum_typespec: (alu_op_t), line:91
|vpiTypedef:
\_enum_typespec: (alu_rs1_op_t), line:97
|vpiTypedef:
\_enum_typespec: (alu_rs2_op_t), line:104
|vpiTypedef:
\_struct_typespec: (amo_alu_inputs_t), line:356
|vpiTypedef:
\_struct_typespec: (amo_details_t), line:362
|vpiTypedef:
\_enum_typespec: (amo_t), line:354
|vpiTypedef:
\_struct_typespec: (branch_inputs_t), line:313
|vpiTypedef:
\_logic_typespec: (branch_predictor_metadata_t), line:32
|vpiTypedef:
\_struct_typespec: (branch_results_t), line:330
|vpiTypedef:
\_enum_typespec: (bus_type_t), line:86
|vpiTypedef:
\_struct_typespec: (csr_inputs_t), line:396
|vpiTypedef:
\_enum_typespec: (csr_op_t), line:218
|vpiTypedef:
\_enum_typespec: (csr_t), line:201
|vpiTypedef:
\_struct_typespec: (data_access_shared_inputs_t), line:427
|vpiTypedef:
\_struct_typespec: (div_inputs_t), line:389
|vpiTypedef:
\_enum_typespec: (div_type), line:66
|vpiTypedef:
\_enum_typespec: (exception_code_t), line:245
|vpiTypedef:
\_struct_typespec: (exception_packet_t), line:263
|vpiTypedef:
\_struct_typespec: (fetch_buffer_packet_t), line:276
|vpiTypedef:
\_enum_typespec: (fifo_type_t), line:440
|vpiTypedef:
\_enum_typespec: (fn3_arith_t), line:76
|vpiTypedef:
\_enum_typespec: (fn3_branch_t), line:126
|vpiTypedef:
\_enum_typespec: (fn3_csr_t), line:212
|vpiTypedef:
\_enum_typespec: (fn3_ls_t), line:115
|vpiTypedef:
\_enum_typespec: (fn3_mul_div_t), line:138
|vpiTypedef:
\_struct_typespec: (gc_inputs_t), line:404
|vpiTypedef:
\_struct_typespec: (inflight_instruction_packet), line:271
|vpiTypedef:
\_logic_typespec: (instruction_id_t), line:30
|vpiTypedef:
\_enum_typespec: (interrupt_code_t), line:261
|vpiTypedef:
\_struct_typespec: (l2_data_attributes_t), line:68
|vpiTypedef:
\_struct_typespec: (l2_mem_request_t), line:58
|vpiTypedef:
\_struct_typespec: (l2_mem_return_data_t), line:75
|vpiTypedef:
\_struct_typespec: (l2_request_t), line:49
|vpiTypedef:
\_struct_typespec: (l2_return_data_t), line:81
|vpiTypedef:
\_struct_typespec: (load_store_inputs_t), line:369
|vpiTypedef:
\_struct_typespec: (mul_inputs_t), line:383
|vpiTypedef:
\_enum_typespec: (opcodes_t), line:48
|vpiTypedef:
\_enum_typespec: (opcodes_trimmed_t), line:65
|vpiTypedef:
\_struct_typespec: (simulation_named_regfile), line:476
|vpiTypedef:
\_struct_typespec: (taiga_trace_events_t), line:442
|vpiTypedef:
\_struct_typespec: (to_l1_arbiter_packet), line:418
|vpiTypedef:
\_struct_typespec: (trace_outputs_t), line:469
|vpiTypedef:
\_logic_typespec: (unit_id_t), line:31
|vpiTypedef:
\_struct_typespec: (unit_writeback_t), line:295
|vpiTypedef:
\_enum_typespec: (vm_t), line:223
|uhdmallModules:
\_module: work@l2_fifo, file:third_party/cores/taiga/l2_arbiter/l2_fifo.sv, line:23, parent:work@div_unit_core_wrapper
|vpiDefName:work@l2_fifo
|vpiFullName:work@l2_fifo
|vpiPort:
\_port: (clk), line:25
|vpiName:clk
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (clk), line:25
|vpiName:clk
|vpiFullName:work@l2_fifo.clk
|vpiNetType:36
|vpiPort:
\_port: (wr_clk), line:26
|vpiName:wr_clk
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (wr_clk), line:26
|vpiName:wr_clk
|vpiFullName:work@l2_fifo.wr_clk
|vpiNetType:36
|vpiPort:
\_port: (rd_clk), line:27
|vpiName:rd_clk
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (rd_clk), line:27
|vpiName:rd_clk
|vpiFullName:work@l2_fifo.rd_clk
|vpiNetType:36
|vpiPort:
\_port: (rst), line:29
|vpiName:rst
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (rst), line:29
|vpiName:rst
|vpiFullName:work@l2_fifo.rst
|vpiNetType:36
|vpiPort:
\_port: (fifo), line:30
|vpiName:fifo
|vpiDirection:5
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_modport: (structure)
|vpiNet:
\_logic_net: (clk), line:25
|vpiNet:
\_logic_net: (wr_clk), line:26
|vpiNet:
\_logic_net: (rd_clk), line:27
|vpiNet:
\_logic_net: (rst), line:29
|vpiNet:
\_logic_net: (fifo), line:30
|vpiName:fifo
|vpiFullName:work@l2_fifo.fifo
|vpiParamAssign:
\_param_assign: , line:23
|vpiRhs:
\_constant: , line:23
|vpiConstType:7
|vpiDecompile:32
|vpiSize:32
|INT:32
|vpiLhs:
\_parameter: (DATA_WIDTH), line:23
|vpiName:DATA_WIDTH
|vpiParamAssign:
\_param_assign: , line:23
|vpiRhs:
\_constant: , line:23
|vpiConstType:7
|vpiDecompile:4
|vpiSize:32
|INT:4
|vpiLhs:
\_parameter: (FIFO_DEPTH), line:23
|vpiName:FIFO_DEPTH
|vpiParamAssign:
\_param_assign: , line:23
|vpiRhs:
\_constant: , line:23
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiLhs:
\_parameter: (ASYNC), line:23
|vpiName:ASYNC
|vpiParameter:
\_parameter: (DATA_WIDTH), line:23
|vpiParameter:
\_parameter: (FIFO_DEPTH), line:23
|vpiParameter:
\_parameter: (ASYNC), line:23
|uhdmallModules:
\_module: work@l2_reservation_logic, file:third_party/cores/taiga/l2_arbiter/l2_reservation_logic.sv, line:25, parent:work@div_unit_core_wrapper
|vpiDefName:work@l2_reservation_logic
|vpiFullName:work@l2_reservation_logic
|vpiProcess:
\_always: , line:48
|vpiAlwaysType:2
|vpiStmt:
\_begin: , line:48
|vpiFullName:work@l2_reservation_logic
|vpiStmt:
\_for_stmt: , line:49
|vpiFullName:work@l2_reservation_logic
|vpiCondition:
\_operation: , line:49
|vpiOpType:20
|vpiOperand:
\_ref_obj: (i), line:49
|vpiName:i
|vpiFullName:work@l2_reservation_logic.i
|vpiOperand:
\_ref_obj: (L2_NUM_PORTS), line:49
|vpiName:L2_NUM_PORTS
|vpiFullName:work@l2_reservation_logic.L2_NUM_PORTS
|vpiForInitStmt:
\_assign_stmt:
|vpiRhs:
\_constant: , line:49
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiLhs:
\_int_var: (i), line:49
|vpiName:i
|vpiFullName:work@l2_reservation_logic.i
|vpiForIncStmt:
\_operation: , line:49
|vpiOpType:62
|vpiOperand:
\_ref_obj: (i), line:49
|vpiName:i
|vpiStmt:
\_begin: , line:49
|vpiFullName:work@l2_reservation_logic
|vpiStmt:
\_assignment: , line:50
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_bit_select: (address_match), line:50
|vpiName:address_match
|vpiFullName:work@l2_reservation_logic.address_match
|vpiIndex:
\_ref_obj: (i), line:50
|vpiName:i
|vpiRhs:
\_operation: , line:50
|vpiOpType:14
|vpiOperand:
\_bit_select: (reservation_address), line:50
|vpiName:reservation_address
|vpiFullName:work@l2_reservation_logic.reservation_address
|vpiIndex:
\_ref_obj: (i), line:50
|vpiName:i
|vpiOperand:
\_ref_obj: (addr), line:50
|vpiName:addr
|vpiFullName:work@l2_reservation_logic.addr
|vpiStmt:
\_assignment: , line:51
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_bit_select: (revoke_reservation), line:51
|vpiName:revoke_reservation
|vpiFullName:work@l2_reservation_logic.revoke_reservation
|vpiIndex:
\_ref_obj: (i), line:51
|vpiName:i
|vpiRhs:
\_operation: , line:51
|vpiOpType:29
|vpiOperand:
\_ref_obj: (sc), line:51
|vpiName:sc
|vpiFullName:work@l2_reservation_logic.sc
|vpiOperand:
\_operation: , line:51
|vpiOpType:28
|vpiOperand:
\_ref_obj: (store), line:51
|vpiName:store
|vpiFullName:work@l2_reservation_logic.store
|vpiOperand:
\_bit_select: (address_match), line:51
|vpiName:address_match
|vpiFullName:work@l2_reservation_logic.address_match
|vpiIndex:
\_ref_obj: (i), line:51
|vpiName:i
|vpiFullName:work@l2_reservation_logic.i
|vpiProcess:
\_always: , line:55
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:55
|vpiCondition:
\_operation: , line:55
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:55
|vpiName:clk
|vpiFullName:work@l2_reservation_logic.clk
|vpiStmt:
\_begin: , line:55
|vpiFullName:work@l2_reservation_logic
|vpiStmt:
\_for_stmt: , line:56
|vpiFullName:work@l2_reservation_logic
|vpiCondition:
\_operation: , line:56
|vpiOpType:20
|vpiOperand:
\_ref_obj: (i), line:56
|vpiName:i
|vpiFullName:work@l2_reservation_logic.i
|vpiOperand:
\_ref_obj: (L2_NUM_PORTS), line:56
|vpiName:L2_NUM_PORTS
|vpiFullName:work@l2_reservation_logic.L2_NUM_PORTS
|vpiForInitStmt:
\_assign_stmt:
|vpiRhs:
\_constant: , line:56
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiLhs:
\_int_var: (i), line:56
|vpiName:i
|vpiFullName:work@l2_reservation_logic.i
|vpiForIncStmt:
\_operation: , line:56
|vpiOpType:62
|vpiOperand:
\_ref_obj: (i), line:56
|vpiName:i
|vpiStmt:
\_begin: , line:56
|vpiFullName:work@l2_reservation_logic
|vpiStmt:
\_if_else: , line:57
|vpiCondition:
\_ref_obj: (rst), line:57
|vpiName:rst
|vpiFullName:work@l2_reservation_logic.rst
|vpiStmt:
\_assignment: , line:58
|vpiOpType:82
|vpiLhs:
\_bit_select: (reservation), line:58
|vpiName:reservation
|vpiFullName:work@l2_reservation_logic.reservation
|vpiIndex:
\_ref_obj: (i), line:58
|vpiName:i
|vpiRhs:
\_constant: , line:58
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiElseStmt:
\_if_stmt: , line:59
|vpiCondition:
\_ref_obj: (strobe), line:59
|vpiName:strobe
|vpiFullName:work@l2_reservation_logic.strobe
|vpiStmt:
\_begin: , line:59
|vpiFullName:work@l2_reservation_logic
|vpiStmt:
\_if_else: , line:60
|vpiCondition:
\_bit_select: (revoke_reservation), line:60
|vpiName:revoke_reservation
|vpiFullName:work@l2_reservation_logic.revoke_reservation
|vpiIndex:
\_ref_obj: (i), line:60
|vpiName:i
|vpiStmt:
\_assignment: , line:61
|vpiOpType:82
|vpiLhs:
\_bit_select: (reservation), line:61
|vpiName:reservation
|vpiFullName:work@l2_reservation_logic.reservation
|vpiIndex:
\_ref_obj: (i), line:61
|vpiName:i
|vpiRhs:
\_constant: , line:61
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiElseStmt:
\_if_stmt: , line:62
|vpiCondition:
\_ref_obj: (lr), line:62
|vpiName:lr
|vpiFullName:work@l2_reservation_logic.lr
|vpiStmt:
\_assignment: , line:63
|vpiOpType:82
|vpiLhs:
\_bit_select: (reservation), line:63
|vpiName:reservation
|vpiFullName:work@l2_reservation_logic.reservation
|vpiIndex:
\_ref_obj: (i), line:63
|vpiName:i
|vpiRhs:
\_constant: , line:63
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiProcess:
\_always: , line:68
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:68
|vpiCondition:
\_operation: , line:68
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:68
|vpiName:clk
|vpiFullName:work@l2_reservation_logic.clk
|vpiStmt:
\_begin: , line:68
|vpiFullName:work@l2_reservation_logic
|vpiStmt:
\_if_stmt: , line:69
|vpiCondition:
\_operation: , line:69
|vpiOpType:28
|vpiOperand:
\_ref_obj: (strobe), line:69
|vpiName:strobe
|vpiFullName:work@l2_reservation_logic.strobe
|vpiOperand:
\_ref_obj: (lr), line:69
|vpiName:lr
|vpiFullName:work@l2_reservation_logic.lr
|vpiStmt:
\_assignment: , line:70
|vpiOpType:82
|vpiLhs:
\_bit_select: (reservation_address), line:70
|vpiName:reservation_address
|vpiFullName:work@l2_reservation_logic.reservation_address
|vpiIndex:
\_ref_obj: (id), line:70
|vpiName:id
|vpiRhs:
\_ref_obj: (addr), line:70
|vpiName:addr
|vpiFullName:work@l2_reservation_logic.addr
|vpiPort:
\_port: (clk), line:27
|vpiName:clk
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (clk), line:27
|vpiName:clk
|vpiFullName:work@l2_reservation_logic.clk
|vpiNetType:36
|vpiPort:
\_port: (rst), line:28
|vpiName:rst
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (rst), line:28
|vpiName:rst
|vpiFullName:work@l2_reservation_logic.rst
|vpiNetType:36
|vpiPort:
\_port: (addr), line:30
|vpiName:addr
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (addr), line:30
|vpiName:addr
|vpiFullName:work@l2_reservation_logic.addr
|vpiNetType:36
|vpiPort:
\_port: (id), line:31
|vpiName:id
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (id), line:31
|vpiName:id
|vpiFullName:work@l2_reservation_logic.id
|vpiNetType:36
|vpiPort:
\_port: (strobe), line:32
|vpiName:strobe
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (strobe), line:32
|vpiName:strobe
|vpiFullName:work@l2_reservation_logic.strobe
|vpiNetType:36
|vpiPort:
\_port: (lr), line:34
|vpiName:lr
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (lr), line:34
|vpiName:lr
|vpiFullName:work@l2_reservation_logic.lr
|vpiNetType:36
|vpiPort:
\_port: (sc), line:35
|vpiName:sc
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (sc), line:35
|vpiName:sc
|vpiFullName:work@l2_reservation_logic.sc
|vpiNetType:36
|vpiPort:
\_port: (store), line:36
|vpiName:store
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (store), line:36
|vpiName:store
|vpiFullName:work@l2_reservation_logic.store
|vpiNetType:36
|vpiPort:
\_port: (abort), line:38
|vpiName:abort
|vpiDirection:2
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (abort), line:38
|vpiName:abort
|vpiFullName:work@l2_reservation_logic.abort
|vpiNetType:36
|vpiContAssign:
\_cont_assign: , line:73
|vpiRhs:
\_operation: , line:73
|vpiOpType:26
|vpiOperand:
\_ref_obj: (sc), line:73
|vpiName:sc
|vpiFullName:work@l2_reservation_logic.sc
|vpiOperand:
\_operation: , line:73
|vpiOpType:27
|vpiOperand:
\_operation: , line:73
|vpiOpType:4
|vpiOperand:
\_bit_select: (reservation), line:73
|vpiName:reservation
|vpiIndex:
\_ref_obj: (id), line:73
|vpiName:id
|vpiFullName:work@l2_reservation_logic.id
|vpiOperand:
\_operation: , line:73
|vpiOpType:26
|vpiOperand:
\_bit_select: (reservation), line:73
|vpiName:reservation
|vpiFullName:work@l2_reservation_logic.reservation
|vpiIndex:
\_ref_obj: (id), line:73
|vpiName:id
|vpiFullName:work@l2_reservation_logic.id
|vpiOperand:
\_operation: , line:73
|vpiOpType:4
|vpiOperand:
\_bit_select: (address_match), line:73
|vpiName:address_match
|vpiIndex:
\_ref_obj: (id), line:73
|vpiName:id
|vpiFullName:work@l2_reservation_logic.id
|vpiLhs:
\_ref_obj: (abort), line:73
|vpiName:abort
|vpiFullName:work@l2_reservation_logic.abort
|vpiNet:
\_logic_net: (clk), line:27
|vpiNet:
\_logic_net: (rst), line:28
|vpiNet:
\_logic_net: (addr), line:30
|vpiNet:
\_logic_net: (id), line:31
|vpiNet:
\_logic_net: (strobe), line:32
|vpiNet:
\_logic_net: (lr), line:34
|vpiNet:
\_logic_net: (sc), line:35
|vpiNet:
\_logic_net: (store), line:36
|vpiNet:
\_logic_net: (abort), line:38
|vpiNet:
\_logic_net: (reservation_address), line:42
|vpiName:reservation_address
|vpiFullName:work@l2_reservation_logic.reservation_address
|vpiNetType:36
|vpiNet:
\_logic_net: (reservation), line:43
|vpiName:reservation
|vpiFullName:work@l2_reservation_logic.reservation
|vpiNetType:36
|vpiNet:
\_logic_net: (address_match), line:45
|vpiName:address_match
|vpiFullName:work@l2_reservation_logic.address_match
|vpiNetType:36
|vpiNet:
\_logic_net: (revoke_reservation), line:46
|vpiName:revoke_reservation
|vpiFullName:work@l2_reservation_logic.revoke_reservation
|vpiNetType:36
|vpiTypedef:
\_struct_typespec: (l2_data_attributes_t), line:68
|vpiTypedef:
\_struct_typespec: (l2_mem_request_t), line:58
|vpiTypedef:
\_struct_typespec: (l2_mem_return_data_t), line:75
|vpiTypedef:
\_struct_typespec: (l2_request_t), line:49
|vpiTypedef:
\_struct_typespec: (l2_return_data_t), line:81
|uhdmallModules:
\_module: work@l2_round_robin, file:third_party/cores/taiga/l2_arbiter/l2_round_robin.sv, line:25, parent:work@div_unit_core_wrapper
|vpiDefName:work@l2_round_robin
|vpiFullName:work@l2_round_robin
|vpiPort:
\_port: (clk), line:27
|vpiName:clk
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (clk), line:27
|vpiName:clk
|vpiFullName:work@l2_round_robin.clk
|vpiNetType:36
|vpiPort:
\_port: (rst), line:28
|vpiName:rst
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (rst), line:28
|vpiName:rst
|vpiFullName:work@l2_round_robin.rst
|vpiNetType:36
|vpiPort:
\_port: (arb), line:29
|vpiName:arb
|vpiDirection:5
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_modport: (slave)
|vpiNet:
\_logic_net: (clk), line:27
|vpiNet:
\_logic_net: (rst), line:28
|vpiNet:
\_logic_net: (state), line:32
|vpiName:state
|vpiFullName:work@l2_round_robin.state
|vpiNetType:36
|vpiNet:
\_logic_net: (muxes), line:33
|vpiName:muxes
|vpiFullName:work@l2_round_robin.muxes
|vpiNetType:36
|vpiNet:
\_logic_net: (arb), line:29
|vpiName:arb
|vpiFullName:work@l2_round_robin.arb
|vpiTypedef:
\_struct_typespec: (l2_data_attributes_t), line:68
|vpiTypedef:
\_struct_typespec: (l2_mem_request_t), line:58
|vpiTypedef:
\_struct_typespec: (l2_mem_return_data_t), line:75
|vpiTypedef:
\_struct_typespec: (l2_request_t), line:49
|vpiTypedef:
\_struct_typespec: (l2_return_data_t), line:81
|uhdmallModules:
\_module: work@load_store_unit, file:third_party/cores/taiga/core/load_store_unit.sv, line:26, parent:work@div_unit_core_wrapper
|vpiDefName:work@load_store_unit
|vpiFullName:work@load_store_unit
|vpiProcess:
\_always: , line:161
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:161
|vpiCondition:
\_operation: , line:161
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:161
|vpiName:clk
|vpiFullName:work@load_store_unit.clk
|vpiStmt:
\_begin: , line:161
|vpiFullName:work@load_store_unit
|vpiStmt:
\_if_stmt: , line:162
|vpiCondition:
\_ref_obj: (load_attributes.push), line:162
|vpiName:load_attributes.push
|vpiFullName:work@load_store_unit.load_attributes.push
|vpiStmt:
\_assignment: , line:163
|vpiOpType:82
|vpiLhs:
\_ref_obj: (last_unit), line:163
|vpiName:last_unit
|vpiFullName:work@load_store_unit.last_unit
|vpiRhs:
\_ref_obj: (sub_unit_address_match), line:163
|vpiName:sub_unit_address_match
|vpiFullName:work@load_store_unit.sub_unit_address_match
|vpiProcess:
\_always: , line:171
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:171
|vpiCondition:
\_operation: , line:171
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:171
|vpiName:clk
|vpiFullName:work@load_store_unit.clk
|vpiStmt:
\_begin: , line:171
|vpiFullName:work@load_store_unit
|vpiStmt:
\_assignment: , line:172
|vpiOpType:82
|vpiLhs:
\_ref_obj: (store_done_id), line:172
|vpiName:store_done_id
|vpiFullName:work@load_store_unit.store_done_id
|vpiRhs:
\_ref_obj: (stage1.instruction_id), line:172
|vpiName:stage1.instruction_id
|vpiFullName:work@load_store_unit.stage1.instruction_id
|vpiStmt:
\_assignment: , line:173
|vpiOpType:82
|vpiLhs:
\_ref_obj: (store_complete), line:173
|vpiName:store_complete
|vpiFullName:work@load_store_unit.store_complete
|vpiRhs:
\_operation: , line:173
|vpiOpType:28
|vpiOperand:
\_ref_obj: (stage1.store), line:173
|vpiName:stage1.store
|vpiFullName:work@load_store_unit.stage1.store
|vpiOperand:
\_ref_obj: (issue_request), line:173
|vpiName:issue_request
|vpiFullName:work@load_store_unit.issue_request
|vpiProcess:
\_always: , line:192
|vpiAlwaysType:2
|vpiStmt:
\_begin: , line:192
|vpiFullName:work@load_store_unit
|vpiStmt:
\_case_stmt: , line:193
|vpiCaseType:1
|vpiCondition:
\_ref_obj: (stage1.fn3), line:193
|vpiName:stage1.fn3
|vpiFullName:work@load_store_unit.stage1.fn3
|vpiCaseItem:
\_case_item: , line:194
|vpiExpr:
\_ref_obj: (LS_H_fn3), line:194
|vpiName:LS_H_fn3
|vpiFullName:work@load_store_unit.LS_H_fn3
|vpiStmt:
\_assignment: , line:194
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (unaligned_addr), line:194
|vpiName:unaligned_addr
|vpiFullName:work@load_store_unit.unaligned_addr
|vpiRhs:
\_bit_select: (virtual_address), line:194
|vpiName:virtual_address
|vpiFullName:work@load_store_unit.virtual_address
|vpiIndex:
\_constant: , line:194
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiCaseItem:
\_case_item: , line:195
|vpiExpr:
\_ref_obj: (LS_W_fn3), line:195
|vpiName:LS_W_fn3
|vpiFullName:work@load_store_unit.LS_W_fn3
|vpiStmt:
\_assignment: , line:195
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (unaligned_addr), line:195
|vpiName:unaligned_addr
|vpiFullName:work@load_store_unit.unaligned_addr
|vpiRhs:
\_operation: , line:195
|vpiOpType:7
|vpiOperand:
\_part_select: , line:195, parent:virtual_address
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (virtual_address)
|vpiLeftRange:
\_constant: , line:195
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:195
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiCaseItem:
\_case_item: , line:196
|vpiStmt:
\_assignment: , line:196
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (unaligned_addr), line:196
|vpiName:unaligned_addr
|vpiFullName:work@load_store_unit.unaligned_addr
|vpiRhs:
\_constant: , line:196
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiProcess:
\_always: , line:221
|vpiAlwaysType:2
|vpiStmt:
\_begin: , line:221
|vpiFullName:work@load_store_unit
|vpiStmt:
\_foreach_stmt: , line:222
|vpiFullName:work@load_store_unit
|vpiVariables:
\_chandle_var: (be), line:222
|vpiName:be
|vpiFullName:work@load_store_unit.be
|vpiLoopVars:
\_chandle_var: (i), line:222
|vpiName:i
|vpiFullName:work@load_store_unit.i
|vpiStmt:
\_begin: , line:222
|vpiFullName:work@load_store_unit
|vpiStmt:
\_case_stmt: , line:223
|vpiCaseType:1
|vpiCondition:
\_ref_obj: (stage1.fn3), line:223
|vpiName:stage1.fn3
|vpiFullName:work@load_store_unit.stage1.fn3
|vpiCaseItem:
\_case_item: , line:224
|vpiStmt:
\_assignment: , line:224
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_bit_select: (be), line:224
|vpiName:be
|vpiFullName:work@load_store_unit.be
|vpiIndex:
\_ref_obj: (i), line:224
|vpiName:i
|vpiRhs:
\_operation: , line:224
|vpiOpType:14
|vpiOperand:
\_part_select: , line:224, parent:virtual_address
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (virtual_address)
|vpiLeftRange:
\_constant: , line:224
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:224
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiOperand:
\_part_select: , line:224, parent:i
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (i)
|vpiLeftRange:
\_constant: , line:224
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:224
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiCaseItem:
\_case_item: , line:225
|vpiStmt:
\_assignment: , line:225
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_bit_select: (be), line:225
|vpiName:be
|vpiFullName:work@load_store_unit.be
|vpiIndex:
\_ref_obj: (i), line:225
|vpiName:i
|vpiRhs:
\_operation: , line:225
|vpiOpType:14
|vpiOperand:
\_bit_select: (virtual_address), line:225
|vpiName:virtual_address
|vpiFullName:work@load_store_unit.virtual_address
|vpiIndex:
\_constant: , line:225
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiOperand:
\_bit_select: (i), line:225
|vpiName:i
|vpiFullName:work@load_store_unit.i
|vpiIndex:
\_constant: , line:225
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiCaseItem:
\_case_item: , line:226
|vpiStmt:
\_assignment: , line:226
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_bit_select: (be), line:226
|vpiName:be
|vpiFullName:work@load_store_unit.be
|vpiIndex:
\_ref_obj: (i), line:226
|vpiName:i
|vpiRhs:
\_constant: , line:226
|vpiConstType:3
|vpiDecompile:'b1
|vpiSize:1
|BIN:1
|vpiStmt:
\_assignment: , line:228
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_bit_select: (be), line:228
|vpiName:be
|vpiFullName:work@load_store_unit.be
|vpiIndex:
\_ref_obj: (i), line:228
|vpiName:i
|vpiRhs:
\_ref_obj: (stage1.store), line:228
|vpiName:stage1.store
|vpiFullName:work@load_store_unit.stage1.store
|vpiProcess:
\_always: , line:247
|vpiAlwaysType:2
|vpiStmt:
\_begin: , line:247
|vpiFullName:work@load_store_unit
|vpiStmt:
\_assignment: , line:248
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_part_select: , line:248, parent:shared_inputs.data_in
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (shared_inputs.data_in)
|vpiLeftRange:
\_constant: , line:248
|vpiConstType:7
|vpiDecompile:7
|vpiSize:32
|INT:7
|vpiRightRange:
\_constant: , line:248
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiRhs:
\_part_select: , line:248, parent:stage1_raw_data
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (stage1_raw_data)
|vpiLeftRange:
\_constant: , line:248
|vpiConstType:7
|vpiDecompile:7
|vpiSize:32
|INT:7
|vpiRightRange:
\_constant: , line:248
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiStmt:
\_assignment: , line:249
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_part_select: , line:249, parent:shared_inputs.data_in
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (shared_inputs.data_in)
|vpiLeftRange:
\_constant: , line:249
|vpiConstType:7
|vpiDecompile:15
|vpiSize:32
|INT:15
|vpiRightRange:
\_constant: , line:249
|vpiConstType:7
|vpiDecompile:8
|vpiSize:32
|INT:8
|vpiRhs:
\_operation: , line:249
|vpiOpType:32
|vpiOperand:
\_operation: , line:249
|vpiOpType:14
|vpiOperand:
\_part_select: , line:249, parent:virtual_address
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (virtual_address)
|vpiLeftRange:
\_constant: , line:249
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:249
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiOperand:
\_constant: , line:249
|vpiConstType:3
|vpiDecompile:2'b01
|vpiSize:2
|BIN:2'b01
|vpiOperand:
\_part_select: , line:249, parent:stage1_raw_data
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (stage1_raw_data)
|vpiLeftRange:
\_constant: , line:249
|vpiConstType:7
|vpiDecompile:7
|vpiSize:32
|INT:7
|vpiRightRange:
\_constant: , line:249
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiOperand:
\_part_select: , line:249, parent:stage1_raw_data
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (stage1_raw_data)
|vpiLeftRange:
\_constant: , line:249
|vpiConstType:7
|vpiDecompile:15
|vpiSize:32
|INT:15
|vpiRightRange:
\_constant: , line:249
|vpiConstType:7
|vpiDecompile:8
|vpiSize:32
|INT:8
|vpiStmt:
\_assignment: , line:250
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_part_select: , line:250, parent:shared_inputs.data_in
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (shared_inputs.data_in)
|vpiLeftRange:
\_constant: , line:250
|vpiConstType:7
|vpiDecompile:23
|vpiSize:32
|INT:23
|vpiRightRange:
\_constant: , line:250
|vpiConstType:7
|vpiDecompile:16
|vpiSize:32
|INT:16
|vpiRhs:
\_operation: , line:250
|vpiOpType:32
|vpiOperand:
\_operation: , line:250
|vpiOpType:14
|vpiOperand:
\_part_select: , line:250, parent:virtual_address
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (virtual_address)
|vpiLeftRange:
\_constant: , line:250
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:250
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiOperand:
\_constant: , line:250
|vpiConstType:3
|vpiDecompile:2'b10
|vpiSize:2
|BIN:2'b10
|vpiOperand:
\_part_select: , line:250, parent:stage1_raw_data
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (stage1_raw_data)
|vpiLeftRange:
\_constant: , line:250
|vpiConstType:7
|vpiDecompile:7
|vpiSize:32
|INT:7
|vpiRightRange:
\_constant: , line:250
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiOperand:
\_part_select: , line:250, parent:stage1_raw_data
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (stage1_raw_data)
|vpiLeftRange:
\_constant: , line:250
|vpiConstType:7
|vpiDecompile:23
|vpiSize:32
|INT:23
|vpiRightRange:
\_constant: , line:250
|vpiConstType:7
|vpiDecompile:16
|vpiSize:32
|INT:16
|vpiStmt:
\_case_stmt: , line:251
|vpiCaseType:1
|vpiCondition:
\_part_select: , line:251, parent:virtual_address
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (virtual_address)
|vpiLeftRange:
\_constant: , line:251
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:251
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiCaseItem:
\_case_item: , line:252
|vpiExpr:
\_constant: , line:252
|vpiConstType:3
|vpiDecompile:2'b10
|vpiSize:2
|BIN:2'b10
|vpiStmt:
\_assignment: , line:252
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_part_select: , line:252, parent:shared_inputs.data_in
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (shared_inputs.data_in)
|vpiLeftRange:
\_constant: , line:252
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:252
|vpiConstType:7
|vpiDecompile:24
|vpiSize:32
|INT:24
|vpiRhs:
\_part_select: , line:252, parent:stage1_raw_data
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (stage1_raw_data)
|vpiLeftRange:
\_constant: , line:252
|vpiConstType:7
|vpiDecompile:15
|vpiSize:32
|INT:15
|vpiRightRange:
\_constant: , line:252
|vpiConstType:7
|vpiDecompile:8
|vpiSize:32
|INT:8
|vpiCaseItem:
\_case_item: , line:253
|vpiExpr:
\_constant: , line:253
|vpiConstType:3
|vpiDecompile:2'b11
|vpiSize:2
|BIN:2'b11
|vpiStmt:
\_assignment: , line:253
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_part_select: , line:253, parent:shared_inputs.data_in
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (shared_inputs.data_in)
|vpiLeftRange:
\_constant: , line:253
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:253
|vpiConstType:7
|vpiDecompile:24
|vpiSize:32
|INT:24
|vpiRhs:
\_part_select: , line:253, parent:stage1_raw_data
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (stage1_raw_data)
|vpiLeftRange:
\_constant: , line:253
|vpiConstType:7
|vpiDecompile:7
|vpiSize:32
|INT:7
|vpiRightRange:
\_constant: , line:253
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiCaseItem:
\_case_item: , line:254
|vpiStmt:
\_assignment: , line:254
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_part_select: , line:254, parent:shared_inputs.data_in
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (shared_inputs.data_in)
|vpiLeftRange:
\_constant: , line:254
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:254
|vpiConstType:7
|vpiDecompile:24
|vpiSize:32
|INT:24
|vpiRhs:
\_part_select: , line:254, parent:stage1_raw_data
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (stage1_raw_data)
|vpiLeftRange:
\_constant: , line:254
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:254
|vpiConstType:7
|vpiDecompile:24
|vpiSize:32
|INT:24
|vpiProcess:
\_always: , line:321
|vpiAlwaysType:2
|vpiStmt:
\_begin: , line:321
|vpiFullName:work@load_store_unit
|vpiStmt:
\_assignment: , line:322
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_part_select: , line:322, parent:aligned_load_data
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (aligned_load_data)
|vpiLeftRange:
\_constant: , line:322
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:322
|vpiConstType:7
|vpiDecompile:16
|vpiSize:32
|INT:16
|vpiRhs:
\_part_select: , line:322, parent:unit_muxed_load_data
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (unit_muxed_load_data)
|vpiLeftRange:
\_constant: , line:322
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:322
|vpiConstType:7
|vpiDecompile:16
|vpiSize:32
|INT:16
|vpiStmt:
\_assignment: , line:323
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_part_select: , line:323, parent:aligned_load_data
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (aligned_load_data)
|vpiLeftRange:
\_constant: , line:323
|vpiConstType:7
|vpiDecompile:15
|vpiSize:32
|INT:15
|vpiRightRange:
\_constant: , line:323
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiRhs:
\_operation: , line:323
|vpiOpType:32
|vpiOperand:
\_ref_obj: (stage2_attr.byte_addr), line:323
|vpiName:stage2_attr.byte_addr
|vpiFullName:work@load_store_unit.stage2_attr.byte_addr
|vpiOperand:
\_part_select: , line:323, parent:unit_muxed_load_data
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (unit_muxed_load_data)
|vpiLeftRange:
\_constant: , line:323
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:323
|vpiConstType:7
|vpiDecompile:16
|vpiSize:32
|INT:16
|vpiOperand:
\_part_select: , line:323, parent:unit_muxed_load_data
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (unit_muxed_load_data)
|vpiLeftRange:
\_constant: , line:323
|vpiConstType:7
|vpiDecompile:15
|vpiSize:32
|INT:15
|vpiRightRange:
\_constant: , line:323
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiStmt:
\_assignment: , line:325
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_part_select: , line:325, parent:aligned_load_data
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (aligned_load_data)
|vpiLeftRange:
\_constant: , line:325
|vpiConstType:7
|vpiDecompile:7
|vpiSize:32
|INT:7
|vpiRightRange:
\_constant: , line:325
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiRhs:
\_operation: , line:325
|vpiOpType:32
|vpiOperand:
\_ref_obj: (stage2_attr.byte_addr), line:325
|vpiName:stage2_attr.byte_addr
|vpiFullName:work@load_store_unit.stage2_attr.byte_addr
|vpiOperand:
\_part_select: , line:325, parent:aligned_load_data
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (aligned_load_data)
|vpiLeftRange:
\_constant: , line:325
|vpiConstType:7
|vpiDecompile:15
|vpiSize:32
|INT:15
|vpiRightRange:
\_constant: , line:325
|vpiConstType:7
|vpiDecompile:8
|vpiSize:32
|INT:8
|vpiOperand:
\_part_select: , line:325, parent:aligned_load_data
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (aligned_load_data)
|vpiLeftRange:
\_constant: , line:325
|vpiConstType:7
|vpiDecompile:7
|vpiSize:32
|INT:7
|vpiRightRange:
\_constant: , line:325
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiProcess:
\_always: , line:329
|vpiAlwaysType:2
|vpiStmt:
\_begin: , line:329
|vpiFullName:work@load_store_unit
|vpiStmt:
\_case_stmt: , line:330
|vpiCaseType:1
|vpiCondition:
\_ref_obj: (stage2_attr.fn3), line:330
|vpiName:stage2_attr.fn3
|vpiFullName:work@load_store_unit.stage2_attr.fn3
|vpiCaseItem:
\_case_item: , line:331
|vpiExpr:
\_ref_obj: (LS_B_fn3), line:331
|vpiName:LS_B_fn3
|vpiFullName:work@load_store_unit.LS_B_fn3
|vpiStmt:
\_assignment: , line:331
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (final_load_data), line:331
|vpiName:final_load_data
|vpiFullName:work@load_store_unit.final_load_data
|vpiRhs:
\_operation: , line:331
|vpiOpType:67
|vpiOperand:
\_operation: , line:331
|vpiOpType:67
|vpiOperand:
\_part_select: , line:331, parent:aligned_load_data
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (aligned_load_data)
|vpiLeftRange:
\_constant: , line:331
|vpiConstType:7
|vpiDecompile:7
|vpiSize:32
|INT:7
|vpiRightRange:
\_constant: , line:331
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiTypespec:
\_integer_typespec: , line:331
|INT:32
|vpiCaseItem:
\_case_item: , line:332
|vpiExpr:
\_ref_obj: (LS_H_fn3), line:332
|vpiName:LS_H_fn3
|vpiFullName:work@load_store_unit.LS_H_fn3
|vpiStmt:
\_assignment: , line:332
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (final_load_data), line:332
|vpiName:final_load_data
|vpiFullName:work@load_store_unit.final_load_data
|vpiRhs:
\_operation: , line:332
|vpiOpType:67
|vpiOperand:
\_operation: , line:332
|vpiOpType:67
|vpiOperand:
\_part_select: , line:332, parent:aligned_load_data
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (aligned_load_data)
|vpiLeftRange:
\_constant: , line:332
|vpiConstType:7
|vpiDecompile:15
|vpiSize:32
|INT:15
|vpiRightRange:
\_constant: , line:332
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiTypespec:
\_integer_typespec: , line:332
|INT:32
|vpiCaseItem:
\_case_item: , line:333
|vpiExpr:
\_ref_obj: (LS_W_fn3), line:333
|vpiName:LS_W_fn3
|vpiFullName:work@load_store_unit.LS_W_fn3
|vpiStmt:
\_assignment: , line:333
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (final_load_data), line:333
|vpiName:final_load_data
|vpiFullName:work@load_store_unit.final_load_data
|vpiRhs:
\_ref_obj: (aligned_load_data), line:333
|vpiName:aligned_load_data
|vpiFullName:work@load_store_unit.aligned_load_data
|vpiCaseItem:
\_case_item: , line:335
|vpiExpr:
\_ref_obj: (L_BU_fn3), line:335
|vpiName:L_BU_fn3
|vpiFullName:work@load_store_unit.L_BU_fn3
|vpiStmt:
\_assignment: , line:335
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (final_load_data), line:335
|vpiName:final_load_data
|vpiFullName:work@load_store_unit.final_load_data
|vpiRhs:
\_operation: , line:335
|vpiOpType:67
|vpiOperand:
\_operation: , line:335
|vpiOpType:67
|vpiOperand:
\_part_select: , line:335, parent:aligned_load_data
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (aligned_load_data)
|vpiLeftRange:
\_constant: , line:335
|vpiConstType:7
|vpiDecompile:7
|vpiSize:32
|INT:7
|vpiRightRange:
\_constant: , line:335
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiTypespec:
\_integer_typespec: , line:335
|INT:32
|vpiCaseItem:
\_case_item: , line:336
|vpiExpr:
\_ref_obj: (L_HU_fn3), line:336
|vpiName:L_HU_fn3
|vpiFullName:work@load_store_unit.L_HU_fn3
|vpiStmt:
\_assignment: , line:336
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (final_load_data), line:336
|vpiName:final_load_data
|vpiFullName:work@load_store_unit.final_load_data
|vpiRhs:
\_operation: , line:336
|vpiOpType:67
|vpiOperand:
\_operation: , line:336
|vpiOpType:67
|vpiOperand:
\_part_select: , line:336, parent:aligned_load_data
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (aligned_load_data)
|vpiLeftRange:
\_constant: , line:336
|vpiConstType:7
|vpiDecompile:15
|vpiSize:32
|INT:15
|vpiRightRange:
\_constant: , line:336
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiTypespec:
\_integer_typespec: , line:336
|INT:32
|vpiCaseItem:
\_case_item: , line:339
|vpiStmt:
\_assignment: , line:339
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (final_load_data), line:339
|vpiName:final_load_data
|vpiFullName:work@load_store_unit.final_load_data
|vpiRhs:
\_ref_obj: (aligned_load_data), line:339
|vpiName:aligned_load_data
|vpiFullName:work@load_store_unit.aligned_load_data
|vpiProcess:
\_always: , line:349
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:349
|vpiCondition:
\_operation: , line:349
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:349
|vpiName:clk
|vpiFullName:work@load_store_unit.clk
|vpiStmt:
\_begin: , line:349
|vpiFullName:work@load_store_unit
|vpiStmt:
\_assignment: , line:350
|vpiOpType:82
|vpiLhs:
\_ref_obj: (exception_complete), line:350
|vpiName:exception_complete
|vpiFullName:work@load_store_unit.exception_complete
|vpiRhs:
\_operation: , line:350
|vpiOpType:28
|vpiOperand:
\_operation: , line:350
|vpiOpType:28
|vpiOperand:
\_ref_obj: (input_fifo.valid), line:350
|vpiName:input_fifo.valid
|vpiFullName:work@load_store_unit.input_fifo.valid
|vpiOperand:
\_ref_obj: (ls_exception_valid), line:350
|vpiName:ls_exception_valid
|vpiFullName:work@load_store_unit.ls_exception_valid
|vpiOperand:
\_ref_obj: (stage1.load), line:350
|vpiName:stage1.load
|vpiFullName:work@load_store_unit.stage1.load
|vpiProcess:
\_always: , line:362
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:362
|vpiCondition:
\_operation: , line:362
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:362
|vpiName:clk
|vpiFullName:work@load_store_unit.clk
|vpiStmt:
\_begin: , line:362
|vpiFullName:work@load_store_unit
|vpiStmt:
\_immediate_assert: , line:363
|vpiExpr:
\_operation: , line:363
|vpiOpType:27
|vpiOperand:
\_operation: , line:363
|vpiOpType:28
|vpiOperand:
\_ref_obj: (issue_request), line:363
|vpiName:issue_request
|vpiFullName:work@load_store_unit.issue_request
|vpiOperand:
\_operation: , line:363
|vpiOpType:7
|vpiOperand:
\_ref_obj: (sub_unit_address_match), line:363
|vpiName:sub_unit_address_match
|vpiFullName:work@load_store_unit.sub_unit_address_match
|vpiOperand:
\_operation: , line:363
|vpiOpType:3
|vpiOperand:
\_ref_obj: (issue_request), line:363
|vpiName:issue_request
|vpiFullName:work@load_store_unit.issue_request
|vpiElseStmt:
\_sys_func_call: ($error), line:363
|vpiName:$error
|vpiArgument:
\_constant: , line:363
|vpiConstType:6
|vpiDecompile:"invalid L/S address"
|vpiSize:21
|STRING:"invalid L/S address"
|vpiPort:
\_port: (clk), line:27
|vpiName:clk
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (clk), line:27
|vpiName:clk
|vpiFullName:work@load_store_unit.clk
|vpiNetType:36
|vpiPort:
\_port: (rst), line:28
|vpiName:rst
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (rst), line:28
|vpiName:rst
|vpiFullName:work@load_store_unit.rst
|vpiNetType:36
|vpiPort:
\_port: (ls_inputs), line:29
|vpiName:ls_inputs
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (ls_inputs), line:29
|vpiName:ls_inputs
|vpiFullName:work@load_store_unit.ls_inputs
|vpiPort:
\_port: (issue), line:30
|vpiName:issue
|vpiDirection:5
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_modport: (unit)
|vpiPort:
\_port: (dcache_on), line:32
|vpiName:dcache_on
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (dcache_on), line:32
|vpiName:dcache_on
|vpiFullName:work@load_store_unit.dcache_on
|vpiNetType:36
|vpiPort:
\_port: (clear_reservation), line:33
|vpiName:clear_reservation
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (clear_reservation), line:33
|vpiName:clear_reservation
|vpiFullName:work@load_store_unit.clear_reservation
|vpiNetType:36
|vpiPort:
\_port: (tlb), line:34
|vpiName:tlb
|vpiDirection:5
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_modport: (mem)
|vpiPort:
\_port: (gc_fetch_flush), line:36
|vpiName:gc_fetch_flush
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (gc_fetch_flush), line:36
|vpiName:gc_fetch_flush
|vpiFullName:work@load_store_unit.gc_fetch_flush
|vpiNetType:36
|vpiPort:
\_port: (gc_issue_flush), line:37
|vpiName:gc_issue_flush
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (gc_issue_flush), line:37
|vpiName:gc_issue_flush
|vpiFullName:work@load_store_unit.gc_issue_flush
|vpiNetType:36
|vpiPort:
\_port: (l1_request), line:39
|vpiName:l1_request
|vpiDirection:5
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_modport: (master)
|vpiPort:
\_port: (l1_response), line:40
|vpiName:l1_response
|vpiDirection:5
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_modport: (master)
|vpiPort:
\_port: (sc_complete), line:41
|vpiName:sc_complete
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (sc_complete), line:41
|vpiName:sc_complete
|vpiFullName:work@load_store_unit.sc_complete
|vpiPort:
\_port: (sc_success), line:42
|vpiName:sc_success
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (sc_success), line:42
|vpiName:sc_success
|vpiFullName:work@load_store_unit.sc_success
|vpiPort:
\_port: (m_axi), line:44
|vpiName:m_axi
|vpiDirection:5
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_modport: (master)
|vpiPort:
\_port: (m_avalon), line:45
|vpiName:m_avalon
|vpiDirection:5
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_modport: (master)
|vpiPort:
\_port: (m_wishbone), line:46
|vpiName:m_wishbone
|vpiDirection:5
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_modport: (master)
|vpiPort:
\_port: (data_bram), line:48
|vpiName:data_bram
|vpiDirection:5
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_modport: (master)
|vpiPort:
\_port: (store_done_id), line:51
|vpiName:store_done_id
|vpiDirection:2
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (store_done_id), line:51
|vpiName:store_done_id
|vpiFullName:work@load_store_unit.store_done_id
|vpiPort:
\_port: (store_complete), line:52
|vpiName:store_complete
|vpiDirection:2
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (store_complete), line:52
|vpiName:store_complete
|vpiFullName:work@load_store_unit.store_complete
|vpiNetType:36
|vpiPort:
\_port: (store_forwarding), line:54
|vpiName:store_forwarding
|vpiDirection:5
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_modport: (unit)
|vpiPort:
\_port: (csr_rd), line:56
|vpiName:csr_rd
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (csr_rd), line:56
|vpiName:csr_rd
|vpiFullName:work@load_store_unit.csr_rd
|vpiNetType:36
|vpiPort:
\_port: (csr_id), line:57
|vpiName:csr_id
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (csr_id), line:57
|vpiName:csr_id
|vpiFullName:work@load_store_unit.csr_id
|vpiPort:
\_port: (csr_done), line:58
|vpiName:csr_done
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (csr_done), line:58
|vpiName:csr_done
|vpiFullName:work@load_store_unit.csr_done
|vpiNetType:36
|vpiPort:
\_port: (ls_exception), line:60
|vpiName:ls_exception
|vpiDirection:2
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (ls_exception), line:60
|vpiName:ls_exception
|vpiFullName:work@load_store_unit.ls_exception
|vpiPort:
\_port: (ls_exception_valid), line:61
|vpiName:ls_exception_valid
|vpiDirection:2
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (ls_exception_valid), line:61
|vpiName:ls_exception_valid
|vpiFullName:work@load_store_unit.ls_exception_valid
|vpiNetType:36
|vpiPort:
\_port: (wb), line:63
|vpiName:wb
|vpiDirection:2
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (wb), line:63
|vpiName:wb
|vpiFullName:work@load_store_unit.wb
|vpiContAssign:
\_cont_assign: , line:141
|vpiRhs:
\_operation: , line:141
|vpiOpType:24
|vpiOperand:
\_ref_obj: (ls_inputs.rs1), line:141
|vpiName:ls_inputs.rs1
|vpiFullName:work@load_store_unit.ls_inputs.rs1
|vpiOperand:
\_operation: , line:141
|vpiOpType:67
|vpiOperand:
\_operation: , line:141
|vpiOpType:67
|vpiOperand:
\_ref_obj: (ls_inputs.offset), line:141
|vpiName:ls_inputs.offset
|vpiTypespec:
\_integer_typespec: , line:141
|INT:32
|vpiLhs:
\_ref_obj: (fifo_inputs.virtual_address), line:141
|vpiName:fifo_inputs.virtual_address
|vpiFullName:work@load_store_unit.fifo_inputs.virtual_address
|vpiContAssign:
\_cont_assign: , line:142
|vpiRhs:
\_ref_obj: (ls_inputs.fn3), line:142
|vpiName:ls_inputs.fn3
|vpiFullName:work@load_store_unit.ls_inputs.fn3
|vpiLhs:
\_ref_obj: (fifo_inputs.fn3), line:142
|vpiName:fifo_inputs.fn3
|vpiFullName:work@load_store_unit.fifo_inputs.fn3
|vpiContAssign:
\_cont_assign: , line:143
|vpiRhs:
\_ref_obj: (ls_inputs.load), line:143
|vpiName:ls_inputs.load
|vpiFullName:work@load_store_unit.ls_inputs.load
|vpiLhs:
\_ref_obj: (fifo_inputs.load), line:143
|vpiName:fifo_inputs.load
|vpiFullName:work@load_store_unit.fifo_inputs.load
|vpiContAssign:
\_cont_assign: , line:144
|vpiRhs:
\_ref_obj: (ls_inputs.store), line:144
|vpiName:ls_inputs.store
|vpiFullName:work@load_store_unit.ls_inputs.store
|vpiLhs:
\_ref_obj: (fifo_inputs.store), line:144
|vpiName:fifo_inputs.store
|vpiFullName:work@load_store_unit.fifo_inputs.store
|vpiContAssign:
\_cont_assign: , line:145
|vpiRhs:
\_ref_obj: (ls_inputs.load_store_forward), line:145
|vpiName:ls_inputs.load_store_forward
|vpiFullName:work@load_store_unit.ls_inputs.load_store_forward
|vpiLhs:
\_ref_obj: (fifo_inputs.load_store_forward), line:145
|vpiName:fifo_inputs.load_store_forward
|vpiFullName:work@load_store_unit.fifo_inputs.load_store_forward
|vpiContAssign:
\_cont_assign: , line:146
|vpiRhs:
\_ref_obj: (issue.instruction_id), line:146
|vpiName:issue.instruction_id
|vpiFullName:work@load_store_unit.issue.instruction_id
|vpiLhs:
\_ref_obj: (fifo_inputs.instruction_id), line:146
|vpiName:fifo_inputs.instruction_id
|vpiFullName:work@load_store_unit.fifo_inputs.instruction_id
|vpiContAssign:
\_cont_assign: , line:147
|vpiRhs:
\_ref_obj: (ls_inputs.store_forward_id), line:147
|vpiName:ls_inputs.store_forward_id
|vpiFullName:work@load_store_unit.ls_inputs.store_forward_id
|vpiLhs:
\_ref_obj: (fifo_inputs.store_forward_id), line:147
|vpiName:fifo_inputs.store_forward_id
|vpiFullName:work@load_store_unit.fifo_inputs.store_forward_id
|vpiContAssign:
\_cont_assign: , line:148
|vpiRhs:
\_ref_obj: (ls_inputs.pc), line:148
|vpiName:ls_inputs.pc
|vpiFullName:work@load_store_unit.ls_inputs.pc
|vpiLhs:
\_ref_obj: (fifo_inputs.pc), line:148
|vpiName:fifo_inputs.pc
|vpiFullName:work@load_store_unit.fifo_inputs.pc
|vpiContAssign:
\_cont_assign: , line:149
|vpiRhs:
\_ref_obj: (ls_inputs.amo), line:149
|vpiName:ls_inputs.amo
|vpiFullName:work@load_store_unit.ls_inputs.amo
|vpiLhs:
\_ref_obj: (fifo_inputs.amo), line:149
|vpiName:fifo_inputs.amo
|vpiFullName:work@load_store_unit.fifo_inputs.amo
|vpiContAssign:
\_cont_assign: , line:151
|vpiRhs:
\_ref_obj: (fifo_inputs), line:151
|vpiName:fifo_inputs
|vpiFullName:work@load_store_unit.fifo_inputs
|vpiLhs:
\_ref_obj: (input_fifo.data_in), line:151
|vpiName:input_fifo.data_in
|vpiFullName:work@load_store_unit.input_fifo.data_in
|vpiContAssign:
\_cont_assign: , line:152
|vpiRhs:
\_ref_obj: (issue.new_request), line:152
|vpiName:issue.new_request
|vpiFullName:work@load_store_unit.issue.new_request
|vpiLhs:
\_ref_obj: (input_fifo.push), line:152
|vpiName:input_fifo.push
|vpiFullName:work@load_store_unit.input_fifo.push
|vpiContAssign:
\_cont_assign: , line:153
|vpiRhs:
\_ref_obj: (gc_fetch_flush), line:153
|vpiName:gc_fetch_flush
|vpiFullName:work@load_store_unit.gc_fetch_flush
|vpiLhs:
\_ref_obj: (input_fifo.supress_push), line:153
|vpiName:input_fifo.supress_push
|vpiFullName:work@load_store_unit.input_fifo.supress_push
|vpiContAssign:
\_cont_assign: , line:154
|vpiRhs:
\_constant: , line:154
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiLhs:
\_ref_obj: (issue.ready), line:154
|vpiName:issue.ready
|vpiFullName:work@load_store_unit.issue.ready
|vpiContAssign:
\_cont_assign: , line:155
|vpiRhs:
\_ref_obj: (issue_request), line:155
|vpiName:issue_request
|vpiFullName:work@load_store_unit.issue_request
|vpiLhs:
\_ref_obj: (input_fifo.pop), line:155
|vpiName:input_fifo.pop
|vpiFullName:work@load_store_unit.input_fifo.pop
|vpiContAssign:
\_cont_assign: , line:156
|vpiRhs:
\_ref_obj: (input_fifo.data_out), line:156
|vpiName:input_fifo.data_out
|vpiFullName:work@load_store_unit.input_fifo.data_out
|vpiLhs:
\_ref_obj: (stage1), line:156
|vpiName:stage1
|vpiFullName:work@load_store_unit.stage1
|vpiContAssign:
\_cont_assign: , line:160
|vpiRhs:
\_ref_obj: (sub_unit_address_match), line:160
|vpiName:sub_unit_address_match
|vpiFullName:work@load_store_unit.sub_unit_address_match
|vpiLhs:
\_ref_obj: (current_unit), line:160
|vpiName:current_unit
|vpiFullName:work@load_store_unit.current_unit
|vpiContAssign:
\_cont_assign: , line:168
|vpiRhs:
\_operation: , line:168
|vpiOpType:5
|vpiOperand:
\_ref_obj: (unit_ready), line:168
|vpiName:unit_ready
|vpiFullName:work@load_store_unit.unit_ready
|vpiLhs:
\_ref_obj: (units_ready), line:168
|vpiName:units_ready
|vpiFullName:work@load_store_unit.units_ready
|vpiContAssign:
\_cont_assign: , line:169
|vpiRhs:
\_operation: , line:169
|vpiOpType:7
|vpiOperand:
\_ref_obj: (unit_data_valid), line:169
|vpiName:unit_data_valid
|vpiFullName:work@load_store_unit.unit_data_valid
|vpiLhs:
\_ref_obj: (load_complete), line:169
|vpiName:load_complete
|vpiFullName:work@load_store_unit.load_complete
|vpiContAssign:
\_cont_assign: , line:177
|vpiRhs:
\_operation: , line:177
|vpiOpType:26
|vpiOperand:
\_operation: , line:177
|vpiOpType:15
|vpiOperand:
\_ref_obj: (current_unit), line:177
|vpiName:current_unit
|vpiFullName:work@load_store_unit.current_unit
|vpiOperand:
\_ref_obj: (last_unit), line:177
|vpiName:last_unit
|vpiFullName:work@load_store_unit.last_unit
|vpiOperand:
\_ref_obj: (load_attributes.valid), line:177
|vpiName:load_attributes.valid
|vpiFullName:work@load_store_unit.load_attributes.valid
|vpiLhs:
\_ref_obj: (unit_stall), line:177
|vpiName:unit_stall
|vpiFullName:work@load_store_unit.unit_stall
|vpiContAssign:
\_cont_assign: , line:178
|vpiRhs:
\_operation: , line:178
|vpiOpType:28
|vpiOperand:
\_ref_obj: (stage1.store), line:178
|vpiName:stage1.store
|vpiFullName:work@load_store_unit.stage1.store
|vpiOperand:
\_ref_obj: (store_forwarding.data_valid), line:178
|vpiName:store_forwarding.data_valid
|vpiFullName:work@load_store_unit.store_forwarding.data_valid
|vpiLhs:
\_ref_obj: (store_ready), line:178
|vpiName:store_ready
|vpiFullName:work@load_store_unit.store_ready
|vpiContAssign:
\_cont_assign: , line:179
|vpiRhs:
\_operation: , line:179
|vpiOpType:28
|vpiOperand:
\_operation: , line:179
|vpiOpType:28
|vpiOperand:
\_operation: , line:179
|vpiOpType:28
|vpiOperand:
\_operation: , line:179
|vpiOpType:28
|vpiOperand:
\_ref_obj: (input_fifo.valid), line:179
|vpiName:input_fifo.valid
|vpiFullName:work@load_store_unit.input_fifo.valid
|vpiOperand:
\_ref_obj: (units_ready), line:179
|vpiName:units_ready
|vpiFullName:work@load_store_unit.units_ready
|vpiOperand:
\_operation: , line:179
|vpiOpType:4
|vpiOperand:
\_ref_obj: (unit_stall), line:179
|vpiName:unit_stall
|vpiFullName:work@load_store_unit.unit_stall
|vpiOperand:
\_operation: , line:179
|vpiOpType:4
|vpiOperand:
\_ref_obj: (unaligned_addr), line:179
|vpiName:unaligned_addr
|vpiFullName:work@load_store_unit.unaligned_addr
|vpiOperand:
\_operation: , line:179
|vpiOpType:29
|vpiOperand:
\_operation: , line:179
|vpiOpType:4
|vpiOperand:
\_ref_obj: (stage1.store), line:179
|vpiName:stage1.store
|vpiFullName:work@load_store_unit.stage1.store
|vpiOperand:
\_ref_obj: (store_ready), line:179
|vpiName:store_ready
|vpiFullName:work@load_store_unit.store_ready
|vpiLhs:
\_ref_obj: (issue_request), line:179
|vpiName:issue_request
|vpiFullName:work@load_store_unit.issue_request
|vpiContAssign:
\_cont_assign: , line:183
|vpiRhs:
\_ref_obj: (stage1.virtual_address), line:183
|vpiName:stage1.virtual_address
|vpiFullName:work@load_store_unit.stage1.virtual_address
|vpiLhs:
\_ref_obj: (virtual_address), line:183
|vpiName:virtual_address
|vpiFullName:work@load_store_unit.virtual_address
|vpiContAssign:
\_cont_assign: , line:185
|vpiRhs:
\_ref_obj: (virtual_address), line:185
|vpiName:virtual_address
|vpiFullName:work@load_store_unit.virtual_address
|vpiLhs:
\_ref_obj: (tlb.virtual_address), line:185
|vpiName:tlb.virtual_address
|vpiFullName:work@load_store_unit.tlb.virtual_address
|vpiContAssign:
\_cont_assign: , line:186
|vpiRhs:
\_ref_obj: (input_fifo.valid), line:186
|vpiName:input_fifo.valid
|vpiFullName:work@load_store_unit.input_fifo.valid
|vpiLhs:
\_ref_obj: (tlb.new_request), line:186
|vpiName:tlb.new_request
|vpiFullName:work@load_store_unit.tlb.new_request
|vpiContAssign:
\_cont_assign: , line:187
|vpiRhs:
\_constant: , line:187
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiLhs:
\_ref_obj: (tlb.execute), line:187
|vpiName:tlb.execute
|vpiFullName:work@load_store_unit.tlb.execute
|vpiContAssign:
\_cont_assign: , line:188
|vpiRhs:
\_operation: , line:188
|vpiOpType:28
|vpiOperand:
\_ref_obj: (stage1.load), line:188
|vpiName:stage1.load
|vpiFullName:work@load_store_unit.stage1.load
|vpiOperand:
\_operation: , line:188
|vpiOpType:4
|vpiOperand:
\_ref_obj: (stage1.store), line:188
|vpiName:stage1.store
|vpiFullName:work@load_store_unit.stage1.store
|vpiLhs:
\_ref_obj: (tlb.rnw), line:188
|vpiName:tlb.rnw
|vpiFullName:work@load_store_unit.tlb.rnw
|vpiContAssign:
\_cont_assign: , line:200
|vpiRhs:
\_constant: , line:200
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiLhs:
\_ref_obj: (ls_exception_valid), line:200
|vpiName:ls_exception_valid
|vpiFullName:work@load_store_unit.ls_exception_valid
|vpiContAssign:
\_cont_assign: , line:234
|vpiRhs:
\_ref_obj: (tlb.physical_address), line:234
|vpiName:tlb.physical_address
|vpiFullName:work@load_store_unit.tlb.physical_address
|vpiLhs:
\_ref_obj: (shared_inputs.addr), line:234
|vpiName:shared_inputs.addr
|vpiFullName:work@load_store_unit.shared_inputs.addr
|vpiContAssign:
\_cont_assign: , line:235
|vpiRhs:
\_ref_obj: (stage1.load), line:235
|vpiName:stage1.load
|vpiFullName:work@load_store_unit.stage1.load
|vpiLhs:
\_ref_obj: (shared_inputs.load), line:235
|vpiName:shared_inputs.load
|vpiFullName:work@load_store_unit.shared_inputs.load
|vpiContAssign:
\_cont_assign: , line:236
|vpiRhs:
\_ref_obj: (stage1.store), line:236
|vpiName:stage1.store
|vpiFullName:work@load_store_unit.stage1.store
|vpiLhs:
\_ref_obj: (shared_inputs.store), line:236
|vpiName:shared_inputs.store
|vpiFullName:work@load_store_unit.shared_inputs.store
|vpiContAssign:
\_cont_assign: , line:237
|vpiRhs:
\_ref_obj: (be), line:237
|vpiName:be
|vpiFullName:work@load_store_unit.be
|vpiLhs:
\_ref_obj: (shared_inputs.be), line:237
|vpiName:shared_inputs.be
|vpiFullName:work@load_store_unit.shared_inputs.be
|vpiContAssign:
\_cont_assign: , line:238
|vpiRhs:
\_ref_obj: (stage1.fn3), line:238
|vpiName:stage1.fn3
|vpiFullName:work@load_store_unit.stage1.fn3
|vpiLhs:
\_ref_obj: (shared_inputs.fn3), line:238
|vpiName:shared_inputs.fn3
|vpiFullName:work@load_store_unit.shared_inputs.fn3
|vpiContAssign:
\_cont_assign: , line:241
|vpiRhs:
\_operation: , line:241
|vpiOpType:32
|vpiOperand:
\_ref_obj: (stage1.load_store_forward), line:241
|vpiName:stage1.load_store_forward
|vpiFullName:work@load_store_unit.stage1.load_store_forward
|vpiOperand:
\_ref_obj: (stage1.store_forward_id), line:241
|vpiName:stage1.store_forward_id
|vpiFullName:work@load_store_unit.stage1.store_forward_id
|vpiOperand:
\_ref_obj: (stage1.instruction_id), line:241
|vpiName:stage1.instruction_id
|vpiFullName:work@load_store_unit.stage1.instruction_id
|vpiLhs:
\_ref_obj: (store_forwarding.id), line:241
|vpiName:store_forwarding.id
|vpiFullName:work@load_store_unit.store_forwarding.id
|vpiContAssign:
\_cont_assign: , line:242
|vpiRhs:
\_ref_obj: (store_forwarding.data), line:242
|vpiName:store_forwarding.data
|vpiFullName:work@load_store_unit.store_forwarding.data
|vpiLhs:
\_ref_obj: (stage1_raw_data), line:242
|vpiName:stage1_raw_data
|vpiFullName:work@load_store_unit.stage1_raw_data
|vpiContAssign:
\_cont_assign: , line:263
|vpiRhs:
\_ref_obj: (stage1.fn3), line:263
|vpiName:stage1.fn3
|vpiFullName:work@load_store_unit.stage1.fn3
|vpiLhs:
\_ref_obj: (load_attributes_in.fn3), line:263
|vpiName:load_attributes_in.fn3
|vpiFullName:work@load_store_unit.load_attributes_in.fn3
|vpiContAssign:
\_cont_assign: , line:264
|vpiRhs:
\_part_select: , line:264, parent:virtual_address
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (virtual_address)
|vpiLeftRange:
\_constant: , line:264
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:264
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiLhs:
\_ref_obj: (load_attributes_in.byte_addr), line:264
|vpiName:load_attributes_in.byte_addr
|vpiFullName:work@load_store_unit.load_attributes_in.byte_addr
|vpiContAssign:
\_cont_assign: , line:265
|vpiRhs:
\_ref_obj: (stage1.instruction_id), line:265
|vpiName:stage1.instruction_id
|vpiFullName:work@load_store_unit.stage1.instruction_id
|vpiLhs:
\_ref_obj: (load_attributes_in.instruction_id), line:265
|vpiName:load_attributes_in.instruction_id
|vpiFullName:work@load_store_unit.load_attributes_in.instruction_id
|vpiContAssign:
\_cont_assign: , line:267
|vpiRhs:
\_ref_obj: (load_attributes_in), line:267
|vpiName:load_attributes_in
|vpiFullName:work@load_store_unit.load_attributes_in
|vpiLhs:
\_ref_obj: (load_attributes.data_in), line:267
|vpiName:load_attributes.data_in
|vpiFullName:work@load_store_unit.load_attributes.data_in
|vpiContAssign:
\_cont_assign: , line:269
|vpiRhs:
\_operation: , line:269
|vpiOpType:28
|vpiOperand:
\_ref_obj: (issue_request), line:269
|vpiName:issue_request
|vpiFullName:work@load_store_unit.issue_request
|vpiOperand:
\_ref_obj: (stage1.load), line:269
|vpiName:stage1.load
|vpiFullName:work@load_store_unit.stage1.load
|vpiLhs:
\_ref_obj: (load_attributes.push), line:269
|vpiName:load_attributes.push
|vpiFullName:work@load_store_unit.load_attributes.push
|vpiContAssign:
\_cont_assign: , line:270
|vpiRhs:
\_ref_obj: (load_complete), line:270
|vpiName:load_complete
|vpiFullName:work@load_store_unit.load_complete
|vpiLhs:
\_ref_obj: (load_attributes.pop), line:270
|vpiName:load_attributes.pop
|vpiFullName:work@load_store_unit.load_attributes.pop
|vpiContAssign:
\_cont_assign: , line:271
|vpiRhs:
\_constant: , line:271
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiLhs:
\_ref_obj: (load_attributes.supress_push), line:271
|vpiName:load_attributes.supress_push
|vpiFullName:work@load_store_unit.load_attributes.supress_push
|vpiContAssign:
\_cont_assign: , line:273
|vpiRhs:
\_ref_obj: (load_attributes.data_out), line:273
|vpiName:load_attributes.data_out
|vpiFullName:work@load_store_unit.load_attributes.data_out
|vpiLhs:
\_ref_obj: (stage2_attr), line:273
|vpiName:stage2_attr
|vpiFullName:work@load_store_unit.stage2_attr
|vpiContAssign:
\_cont_assign: , line:318
|vpiRhs:
\_bit_select: (unit_data_array), line:318
|vpiName:unit_data_array
|vpiFullName:work@load_store_unit.unit_data_array
|vpiIndex:
\_ref_obj: (stage2_attr.subunit_id), line:318
|vpiName:stage2_attr.subunit_id
|vpiLhs:
\_ref_obj: (unit_muxed_load_data), line:318
|vpiName:unit_muxed_load_data
|vpiFullName:work@load_store_unit.unit_muxed_load_data
|vpiContAssign:
\_cont_assign: , line:345
|vpiRhs:
\_operation: , line:345
|vpiOpType:32
|vpiOperand:
\_ref_obj: (ls_done), line:345
|vpiName:ls_done
|vpiFullName:work@load_store_unit.ls_done
|vpiOperand:
\_ref_obj: (final_load_data), line:345
|vpiName:final_load_data
|vpiFullName:work@load_store_unit.final_load_data
|vpiOperand:
\_ref_obj: (csr_rd), line:345
|vpiName:csr_rd
|vpiFullName:work@load_store_unit.csr_rd
|vpiLhs:
\_ref_obj: (wb.rd), line:345
|vpiName:wb.rd
|vpiFullName:work@load_store_unit.wb.rd
|vpiContAssign:
\_cont_assign: , line:352
|vpiRhs:
\_operation: , line:352
|vpiOpType:29
|vpiOperand:
\_ref_obj: (load_complete), line:352
|vpiName:load_complete
|vpiFullName:work@load_store_unit.load_complete
|vpiOperand:
\_ref_obj: (exception_complete), line:352
|vpiName:exception_complete
|vpiFullName:work@load_store_unit.exception_complete
|vpiLhs:
\_ref_obj: (ls_done), line:352
|vpiName:ls_done
|vpiFullName:work@load_store_unit.ls_done
|vpiContAssign:
\_cont_assign: , line:354
|vpiRhs:
\_operation: , line:354
|vpiOpType:29
|vpiOperand:
\_ref_obj: (csr_done), line:354
|vpiName:csr_done
|vpiFullName:work@load_store_unit.csr_done
|vpiOperand:
\_ref_obj: (ls_done), line:354
|vpiName:ls_done
|vpiFullName:work@load_store_unit.ls_done
|vpiLhs:
\_ref_obj: (wb.done), line:354
|vpiName:wb.done
|vpiFullName:work@load_store_unit.wb.done
|vpiContAssign:
\_cont_assign: , line:355
|vpiRhs:
\_operation: , line:355
|vpiOpType:32
|vpiOperand:
\_ref_obj: (csr_done), line:355
|vpiName:csr_done
|vpiFullName:work@load_store_unit.csr_done
|vpiOperand:
\_ref_obj: (csr_id), line:355
|vpiName:csr_id
|vpiFullName:work@load_store_unit.csr_id
|vpiOperand:
\_ref_obj: (stage2_attr.instruction_id), line:355
|vpiName:stage2_attr.instruction_id
|vpiFullName:work@load_store_unit.stage2_attr.instruction_id
|vpiLhs:
\_ref_obj: (wb.id), line:355
|vpiName:wb.id
|vpiFullName:work@load_store_unit.wb.id
|vpiNet:
\_logic_net: (clk), line:27
|vpiNet:
\_logic_net: (rst), line:28
|vpiNet:
\_logic_net: (ls_inputs), line:29
|vpiNet:
\_logic_net: (dcache_on), line:32
|vpiNet:
\_logic_net: (clear_reservation), line:33
|vpiNet:
\_logic_net: (gc_fetch_flush), line:36
|vpiNet:
\_logic_net: (gc_issue_flush), line:37
|vpiNet:
\_logic_net: (sc_complete), line:41
|vpiNet:
\_logic_net: (sc_success), line:42
|vpiNet:
\_logic_net: (store_done_id), line:51
|vpiNet:
\_logic_net: (store_complete), line:52
|vpiNet:
\_logic_net: (csr_rd), line:56
|vpiNet:
\_logic_net: (csr_id), line:57
|vpiNet:
\_logic_net: (csr_done), line:58
|vpiNet:
\_logic_net: (ls_exception), line:60
|vpiNet:
\_logic_net: (ls_exception_valid), line:61
|vpiNet:
\_logic_net: (wb), line:63
|vpiNet:
\_logic_net: (shared_inputs), line:76
|vpiName:shared_inputs
|vpiFullName:work@load_store_unit.shared_inputs
|vpiNet:
\_logic_net: (units_ready), line:81
|vpiName:units_ready
|vpiFullName:work@load_store_unit.units_ready
|vpiNetType:36
|vpiNet:
\_logic_net: (store_ready), line:82
|vpiName:store_ready
|vpiFullName:work@load_store_unit.store_ready
|vpiNetType:36
|vpiNet:
\_logic_net: (issue_request), line:83
|vpiName:issue_request
|vpiFullName:work@load_store_unit.issue_request
|vpiNetType:36
|vpiNet:
\_logic_net: (load_complete), line:84
|vpiName:load_complete
|vpiFullName:work@load_store_unit.load_complete
|vpiNetType:36
|vpiNet:
\_logic_net: (virtual_address), line:86
|vpiName:virtual_address
|vpiFullName:work@load_store_unit.virtual_address
|vpiNetType:36
|vpiNet:
\_logic_net: (be), line:87
|vpiName:be
|vpiFullName:work@load_store_unit.be
|vpiNetType:36
|vpiNet:
\_logic_net: (unit_muxed_load_data), line:89
|vpiName:unit_muxed_load_data
|vpiFullName:work@load_store_unit.unit_muxed_load_data
|vpiNetType:36
|vpiNet:
\_logic_net: (aligned_load_data), line:90
|vpiName:aligned_load_data
|vpiFullName:work@load_store_unit.aligned_load_data
|vpiNetType:36
|vpiNet:
\_logic_net: (final_load_data), line:91
|vpiName:final_load_data
|vpiFullName:work@load_store_unit.final_load_data
|vpiNetType:36
|vpiNet:
\_logic_net: (stage1_raw_data), line:93
|vpiName:stage1_raw_data
|vpiFullName:work@load_store_unit.stage1_raw_data
|vpiNetType:36
|vpiNet:
\_logic_net: (unit_data_array), line:95
|vpiName:unit_data_array
|vpiFullName:work@load_store_unit.unit_data_array
|vpiNetType:36
|vpiNet:
\_logic_net: (unit_ready), line:96
|vpiName:unit_ready
|vpiFullName:work@load_store_unit.unit_ready
|vpiNetType:36
|vpiNet:
\_logic_net: (unit_data_valid), line:97
|vpiName:unit_data_valid
|vpiFullName:work@load_store_unit.unit_data_valid
|vpiNetType:36
|vpiNet:
\_logic_net: (last_unit), line:98
|vpiName:last_unit
|vpiFullName:work@load_store_unit.last_unit
|vpiNetType:36
|vpiNet:
\_logic_net: (current_unit), line:99
|vpiName:current_unit
|vpiFullName:work@load_store_unit.current_unit
|vpiNetType:36
|vpiNet:
\_logic_net: (unaligned_addr), line:101
|vpiName:unaligned_addr
|vpiFullName:work@load_store_unit.unaligned_addr
|vpiNetType:36
|vpiNet:
\_logic_net: (sub_unit_address_match), line:102
|vpiName:sub_unit_address_match
|vpiFullName:work@load_store_unit.sub_unit_address_match
|vpiNetType:36
|vpiNet:
\_logic_net: (unit_stall), line:104
|vpiName:unit_stall
|vpiFullName:work@load_store_unit.unit_stall
|vpiNetType:36
|vpiNet:
\_logic_net: (fifo_inputs), line:119
|vpiName:fifo_inputs
|vpiFullName:work@load_store_unit.fifo_inputs
|vpiNet:
\_logic_net: (load_attributes_in), line:127
|vpiName:load_attributes_in
|vpiFullName:work@load_store_unit.load_attributes_in
|vpiNet:
\_logic_net: (stage2_attr), line:127
|vpiName:stage2_attr
|vpiFullName:work@load_store_unit.stage2_attr
|vpiNet:
\_logic_net: (stage1), line:128
|vpiName:stage1
|vpiFullName:work@load_store_unit.stage1
|vpiNet:
\_logic_net: (exception_complete), line:347
|vpiName:exception_complete
|vpiFullName:work@load_store_unit.exception_complete
|vpiNetType:36
|vpiNet:
\_logic_net: (ls_done), line:348
|vpiName:ls_done
|vpiFullName:work@load_store_unit.ls_done
|vpiNetType:36
|vpiNet:
\_logic_net: (issue), line:30
|vpiName:issue
|vpiFullName:work@load_store_unit.issue
|vpiNet:
\_logic_net: (tlb), line:34
|vpiName:tlb
|vpiFullName:work@load_store_unit.tlb
|vpiNet:
\_logic_net: (l1_request), line:39
|vpiName:l1_request
|vpiFullName:work@load_store_unit.l1_request
|vpiNet:
\_logic_net: (l1_response), line:40
|vpiName:l1_response
|vpiFullName:work@load_store_unit.l1_response
|vpiNet:
\_logic_net: (m_axi), line:44
|vpiName:m_axi
|vpiFullName:work@load_store_unit.m_axi
|vpiNet:
\_logic_net: (m_avalon), line:45
|vpiName:m_avalon
|vpiFullName:work@load_store_unit.m_avalon
|vpiNet:
\_logic_net: (m_wishbone), line:46
|vpiName:m_wishbone
|vpiFullName:work@load_store_unit.m_wishbone
|vpiNet:
\_logic_net: (data_bram), line:48
|vpiName:data_bram
|vpiFullName:work@load_store_unit.data_bram
|vpiNet:
\_logic_net: (store_forwarding), line:54
|vpiName:store_forwarding
|vpiFullName:work@load_store_unit.store_forwarding
|vpiTypedef:
\_struct_typespec: (alu_inputs_t), line:301
|vpiTypedef:
\_enum_typespec: (alu_logic_op_t), line:84
|vpiTypedef:
\_enum_typespec: (alu_op_t), line:91
|vpiTypedef:
\_enum_typespec: (alu_rs1_op_t), line:97
|vpiTypedef:
\_enum_typespec: (alu_rs2_op_t), line:104
|vpiTypedef:
\_struct_typespec: (amo_alu_inputs_t), line:356
|vpiTypedef:
\_struct_typespec: (amo_details_t), line:362
|vpiTypedef:
\_enum_typespec: (amo_t), line:354
|vpiTypedef:
\_struct_typespec: (branch_inputs_t), line:313
|vpiTypedef:
\_logic_typespec: (branch_predictor_metadata_t), line:32
|vpiTypedef:
\_struct_typespec: (branch_results_t), line:330
|vpiTypedef:
\_enum_typespec: (bus_type_t), line:86
|vpiTypedef:
\_struct_typespec: (csr_inputs_t), line:396
|vpiTypedef:
\_enum_typespec: (csr_op_t), line:218
|vpiTypedef:
\_enum_typespec: (csr_t), line:201
|vpiTypedef:
\_struct_typespec: (data_access_shared_inputs_t), line:427
|vpiTypedef:
\_struct_typespec: (div_inputs_t), line:389
|vpiTypedef:
\_enum_typespec: (div_type), line:66
|vpiTypedef:
\_enum_typespec: (exception_code_t), line:245
|vpiTypedef:
\_struct_typespec: (exception_packet_t), line:263
|vpiTypedef:
\_struct_typespec: (fetch_buffer_packet_t), line:276
|vpiTypedef:
\_enum_typespec: (fifo_type_t), line:440
|vpiTypedef:
\_enum_typespec: (fn3_arith_t), line:76
|vpiTypedef:
\_enum_typespec: (fn3_branch_t), line:126
|vpiTypedef:
\_enum_typespec: (fn3_csr_t), line:212
|vpiTypedef:
\_enum_typespec: (fn3_ls_t), line:115
|vpiTypedef:
\_enum_typespec: (fn3_mul_div_t), line:138
|vpiTypedef:
\_struct_typespec: (gc_inputs_t), line:404
|vpiTypedef:
\_struct_typespec: (inflight_instruction_packet), line:271
|vpiTypedef:
\_logic_typespec: (instruction_id_t), line:30
|vpiTypedef:
\_enum_typespec: (interrupt_code_t), line:261
|vpiTypedef:
\_struct_typespec: (load_attributes_t), line:121
|vpiPacked:1
|vpiName:load_attributes_t
|vpiTypespecMember:
\_typespec_member: (fn3), line:122
|vpiName:fn3
|vpiTypespec:
\_logic_typespec: , line:122
|vpiRange:
\_range: , line:122, parent:load_attributes_t
|vpiLeftRange:
\_constant: , line:122
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiRightRange:
\_constant: , line:122
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiTypespecMember:
\_typespec_member: (byte_addr), line:123
|vpiName:byte_addr
|vpiTypespec:
\_logic_typespec: , line:123
|vpiRange:
\_range: , line:123, parent:load_attributes_t
|vpiLeftRange:
\_constant: , line:123
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:123
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiTypespecMember:
\_typespec_member: (instruction_id), line:124
|vpiName:instruction_id
|vpiTypespec:
\_logic_typespec: (instruction_id_t), line:30
|vpiTypespecMember:
\_typespec_member: (subunit_id), line:125
|vpiName:subunit_id
|vpiTypespec:
\_logic_typespec: , line:125
|vpiRange:
\_range: , line:125, parent:load_attributes_t
|vpiLeftRange:
\_constant: , line:125
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiRightRange:
\_constant: , line:125
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiTypedef:
\_struct_typespec: (load_store_input_fifo_t), line:106
|vpiPacked:1
|vpiName:load_store_input_fifo_t
|vpiTypespecMember:
\_typespec_member: (virtual_address), line:107
|vpiName:virtual_address
|vpiTypespec:
\_logic_typespec: , line:107
|vpiRange:
\_range: , line:107, parent:load_store_input_fifo_t
|vpiLeftRange:
\_constant: , line:107
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:107
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiTypespecMember:
\_typespec_member: (fn3), line:108
|vpiName:fn3
|vpiTypespec:
\_logic_typespec: , line:108
|vpiRange:
\_range: , line:108, parent:load_store_input_fifo_t
|vpiLeftRange:
\_constant: , line:108
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiRightRange:
\_constant: , line:108
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiTypespecMember:
\_typespec_member: (load), line:109
|vpiName:load
|vpiTypespec:
\_logic_typespec: , line:109
|vpiTypespecMember:
\_typespec_member: (store), line:110
|vpiName:store
|vpiTypespec:
\_logic_typespec: , line:110
|vpiTypespecMember:
\_typespec_member: (load_store_forward), line:111
|vpiName:load_store_forward
|vpiTypespec:
\_logic_typespec: , line:111
|vpiTypespecMember:
\_typespec_member: (instruction_id), line:112
|vpiName:instruction_id
|vpiTypespec:
\_logic_typespec: (instruction_id_t), line:30
|vpiTypespecMember:
\_typespec_member: (store_forward_id), line:113
|vpiName:store_forward_id
|vpiTypespec:
\_logic_typespec: (instruction_id_t), line:30
|vpiTypespecMember:
\_typespec_member: (pc), line:115
|vpiName:pc
|vpiTypespec:
\_logic_typespec: , line:115
|vpiRange:
\_range: , line:115, parent:load_store_input_fifo_t
|vpiLeftRange:
\_constant: , line:115
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:115
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiTypespecMember:
\_typespec_member: (amo), line:117
|vpiName:amo
|vpiTypespec:
\_struct_typespec: (amo_details_t), line:362
|vpiTypedef:
\_struct_typespec: (load_store_inputs_t), line:369
|vpiTypedef:
\_struct_typespec: (mul_inputs_t), line:383
|vpiTypedef:
\_enum_typespec: (opcodes_t), line:48
|vpiTypedef:
\_enum_typespec: (opcodes_trimmed_t), line:65
|vpiTypedef:
\_struct_typespec: (simulation_named_regfile), line:476
|vpiTypedef:
\_struct_typespec: (taiga_trace_events_t), line:442
|vpiTypedef:
\_struct_typespec: (to_l1_arbiter_packet), line:418
|vpiTypedef:
\_struct_typespec: (trace_outputs_t), line:469
|vpiTypedef:
\_logic_typespec: (unit_id_t), line:31
|vpiTypedef:
\_struct_typespec: (unit_writeback_t), line:295
|vpiTypedef:
\_enum_typespec: (vm_t), line:223
|vpiParamAssign:
\_param_assign: , line:66
|vpiRhs:
\_operation: , line:66
|vpiOpType:24
|vpiOperand:
\_operation: , line:66
|vpiOpType:24
|vpiOperand:
\_ref_obj: (USE_D_SCRATCH_MEM), line:66
|vpiName:USE_D_SCRATCH_MEM
|vpiOperand:
\_ref_obj: (USE_BUS), line:66
|vpiName:USE_BUS
|vpiOperand:
\_ref_obj: (USE_DCACHE), line:66
|vpiName:USE_DCACHE
|vpiLhs:
\_parameter: (NUM_SUB_UNITS), line:66
|vpiName:NUM_SUB_UNITS
|vpiLocalParam:1
|vpiParamAssign:
\_param_assign: , line:67
|vpiRhs:
\_operation: , line:67
|vpiOpType:32
|vpiOperand:
\_operation: , line:67
|vpiOpType:14
|vpiOperand:
\_operation: , line:67
|vpiOpType:24
|vpiOperand:
\_operation: , line:66
|vpiOpType:24
|vpiOperand:
\_ref_obj: (USE_D_SCRATCH_MEM), line:66
|vpiName:USE_D_SCRATCH_MEM
|vpiOperand:
\_ref_obj: (USE_BUS), line:66
|vpiName:USE_BUS
|vpiOperand:
\_ref_obj: (USE_DCACHE), line:66
|vpiName:USE_DCACHE
|vpiOperand:
\_constant: , line:67
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiOperand:
\_constant: , line:67
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiOperand:
\_sys_func_call: ($clog2), line:67
|vpiName:$clog2
|vpiArgument:
\_ref_obj: (NUM_SUB_UNITS), line:67
|vpiName:NUM_SUB_UNITS
|vpiLhs:
\_parameter: (NUM_SUB_UNITS_W), line:67
|vpiName:NUM_SUB_UNITS_W
|vpiLocalParam:1
|vpiParamAssign:
\_param_assign: , line:69
|vpiRhs:
\_constant: , line:69
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiLhs:
\_parameter: (BRAM_ID), line:69
|vpiName:BRAM_ID
|vpiLocalParam:1
|vpiParamAssign:
\_param_assign: , line:70
|vpiRhs:
\_ref_obj: (USE_D_SCRATCH_MEM), line:70
|vpiName:USE_D_SCRATCH_MEM
|vpiLhs:
\_parameter: (BUS_ID), line:70
|vpiName:BUS_ID
|vpiLocalParam:1
|vpiParamAssign:
\_param_assign: , line:71
|vpiRhs:
\_operation: , line:71
|vpiOpType:24
|vpiOperand:
\_ref_obj: (USE_D_SCRATCH_MEM), line:71
|vpiName:USE_D_SCRATCH_MEM
|vpiOperand:
\_ref_obj: (USE_BUS), line:71
|vpiName:USE_BUS
|vpiLhs:
\_parameter: (DCACHE_ID), line:71
|vpiName:DCACHE_ID
|vpiLocalParam:1
|vpiParamAssign:
\_param_assign: , line:74
|vpiRhs:
\_operation: , line:74
|vpiOpType:32
|vpiOperand:
\_ref_obj: (USE_DCACHE), line:74
|vpiName:USE_DCACHE
|vpiOperand:
\_constant: , line:74
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiOperand:
\_constant: , line:74
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiLhs:
\_parameter: (ATTRIBUTES_DEPTH), line:74
|vpiName:ATTRIBUTES_DEPTH
|vpiLocalParam:1
|vpiParameter:
\_parameter: (NUM_SUB_UNITS), line:66
|vpiParameter:
\_parameter: (NUM_SUB_UNITS_W), line:67
|vpiParameter:
\_parameter: (BRAM_ID), line:69
|vpiParameter:
\_parameter: (BUS_ID), line:70
|vpiParameter:
\_parameter: (DCACHE_ID), line:71
|vpiParameter:
\_parameter: (ATTRIBUTES_DEPTH), line:74
|uhdmallModules:
\_module: work@local_mem, file:third_party/cores/taiga/local_memory/local_mem.sv, line:24, parent:work@div_unit_core_wrapper
|vpiDefName:work@local_mem
|vpiFullName:work@local_mem
|vpiPort:
\_port: (clk), line:31
|vpiName:clk
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (clk), line:31
|vpiName:clk
|vpiFullName:work@local_mem.clk
|vpiNetType:36
|vpiPort:
\_port: (rst), line:32
|vpiName:rst
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (rst), line:32
|vpiName:rst
|vpiFullName:work@local_mem.rst
|vpiNetType:36
|vpiPort:
\_port: (portA), line:33
|vpiName:portA
|vpiDirection:5
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_modport: (slave)
|vpiPort:
\_port: (portB), line:34
|vpiName:portB
|vpiDirection:5
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_modport: (slave)
|vpiNet:
\_logic_net: (clk), line:31
|vpiNet:
\_logic_net: (rst), line:32
|vpiNet:
\_logic_net: (portA), line:33
|vpiName:portA
|vpiFullName:work@local_mem.portA
|vpiNet:
\_logic_net: (portB), line:34
|vpiName:portB
|vpiFullName:work@local_mem.portB
|vpiParamAssign:
\_param_assign: , line:26
|vpiRhs:
\_constant: , line:26
|vpiConstType:7
|vpiDecompile:64
|vpiSize:32
|INT:64
|vpiLhs:
\_parameter: (RAM_SIZE), line:26
|vpiName:RAM_SIZE
|vpiParamAssign:
\_param_assign: , line:27
|vpiRhs:
\_constant: , line:27
|vpiConstType:6
|vpiDecompile:""
|vpiSize:2
|STRING:""
|vpiLhs:
\_parameter: (preload_file), line:27
|vpiName:preload_file
|vpiParamAssign:
\_param_assign: , line:28
|vpiRhs:
\_constant: , line:28
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiLhs:
\_parameter: (USE_PRELOAD_FILE), line:28
|vpiName:USE_PRELOAD_FILE
|vpiParamAssign:
\_param_assign: , line:37
|vpiRhs:
\_constant: , line:37
|vpiDecompile:16384
|INT:16384
|vpiLhs:
\_parameter: (LINES), line:37
|vpiName:LINES
|vpiLocalParam:1
|vpiParameter:
\_parameter: (RAM_SIZE), line:26
|vpiParameter:
\_parameter: (preload_file), line:27
|vpiParameter:
\_parameter: (USE_PRELOAD_FILE), line:28
|vpiParameter:
\_parameter: (LINES), line:37
|uhdmallModules:
\_module: work@lut_ram, file:third_party/cores/taiga/core/lut_ram.sv, line:23, parent:work@div_unit_core_wrapper
|vpiDefName:work@lut_ram
|vpiFullName:work@lut_ram
|vpiProcess:
\_initial:
|vpiStmt:
\_begin: , line:41
|vpiFullName:work@lut_ram
|vpiStmt:
\_for_stmt: , line:42
|vpiFullName:work@lut_ram
|vpiCondition:
\_operation: , line:42
|vpiOpType:20
|vpiOperand:
\_ref_obj: (i), line:42
|vpiName:i
|vpiFullName:work@lut_ram.i
|vpiOperand:
\_ref_obj: (DEPTH), line:42
|vpiName:DEPTH
|vpiFullName:work@lut_ram.DEPTH
|vpiForInitStmt:
\_assign_stmt:
|vpiRhs:
\_constant: , line:42
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiLhs:
\_int_var: (i), line:42
|vpiName:i
|vpiFullName:work@lut_ram.i
|vpiForIncStmt:
\_operation: , line:42
|vpiOpType:82
|vpiOperand:
\_ref_obj: (i), line:42
|vpiName:i
|vpiStmt:
\_begin: , line:42
|vpiFullName:work@lut_ram
|vpiStmt:
\_assignment: , line:43
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_bit_select: (ram), line:43
|vpiName:ram
|vpiFullName:work@lut_ram.ram
|vpiIndex:
\_ref_obj: (i), line:43
|vpiName:i
|vpiRhs:
\_constant: , line:43
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiProcess:
\_always: , line:47
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:47
|vpiCondition:
\_operation: , line:47
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:47
|vpiName:clk
|vpiFullName:work@lut_ram.clk
|vpiStmt:
\_begin: , line:47
|vpiFullName:work@lut_ram
|vpiStmt:
\_if_stmt: , line:48
|vpiCondition:
\_ref_obj: (ram_write), line:48
|vpiName:ram_write
|vpiFullName:work@lut_ram.ram_write
|vpiStmt:
\_assignment: , line:49
|vpiOpType:82
|vpiLhs:
\_bit_select: (ram), line:49
|vpiName:ram
|vpiFullName:work@lut_ram.ram
|vpiIndex:
\_ref_obj: (waddr), line:49
|vpiName:waddr
|vpiRhs:
\_ref_obj: (new_ram_data), line:49
|vpiName:new_ram_data
|vpiFullName:work@lut_ram.new_ram_data
|vpiPort:
\_port: (clk), line:28
|vpiName:clk
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (clk), line:28
|vpiName:clk
|vpiFullName:work@lut_ram.clk
|vpiNetType:36
|vpiPort:
\_port: (waddr), line:30
|vpiName:waddr
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (waddr), line:30
|vpiName:waddr
|vpiFullName:work@lut_ram.waddr
|vpiNetType:36
|vpiPort:
\_port: (raddr), line:31
|vpiName:raddr
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (raddr), line:31
|vpiName:raddr
|vpiFullName:work@lut_ram.raddr
|vpiNetType:36
|vpiPort:
\_port: (ram_write), line:33
|vpiName:ram_write
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (ram_write), line:33
|vpiName:ram_write
|vpiFullName:work@lut_ram.ram_write
|vpiNetType:36
|vpiPort:
\_port: (new_ram_data), line:34
|vpiName:new_ram_data
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (new_ram_data), line:34
|vpiName:new_ram_data
|vpiFullName:work@lut_ram.new_ram_data
|vpiNetType:36
|vpiPort:
\_port: (ram_data_out), line:35
|vpiName:ram_data_out
|vpiDirection:2
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (ram_data_out), line:35
|vpiName:ram_data_out
|vpiFullName:work@lut_ram.ram_data_out
|vpiNetType:36
|vpiContAssign:
\_cont_assign: , line:52
|vpiRhs:
\_bit_select: (ram), line:52
|vpiName:ram
|vpiFullName:work@lut_ram.ram
|vpiIndex:
\_ref_obj: (raddr), line:52
|vpiName:raddr
|vpiLhs:
\_ref_obj: (ram_data_out), line:52
|vpiName:ram_data_out
|vpiFullName:work@lut_ram.ram_data_out
|vpiNet:
\_logic_net: (clk), line:28
|vpiNet:
\_logic_net: (waddr), line:30
|vpiNet:
\_logic_net: (raddr), line:31
|vpiNet:
\_logic_net: (ram_write), line:33
|vpiNet:
\_logic_net: (new_ram_data), line:34
|vpiNet:
\_logic_net: (ram_data_out), line:35
|vpiNet:
\_logic_net: (ram), line:39
|vpiName:ram
|vpiFullName:work@lut_ram.ram
|vpiNetType:36
|vpiParamAssign:
\_param_assign: , line:24
|vpiRhs:
\_constant: , line:24
|vpiConstType:7
|vpiDecompile:32
|vpiSize:32
|INT:32
|vpiLhs:
\_parameter: (WIDTH), line:24
|vpiName:WIDTH
|vpiParamAssign:
\_param_assign: , line:25
|vpiRhs:
\_constant: , line:25
|vpiConstType:7
|vpiDecompile:32
|vpiSize:32
|INT:32
|vpiLhs:
\_parameter: (DEPTH), line:25
|vpiName:DEPTH
|vpiParameter:
\_parameter: (WIDTH), line:24
|vpiParameter:
\_parameter: (DEPTH), line:25
|uhdmallModules:
\_module: work@mmu, file:third_party/cores/taiga/core/mmu.sv, line:27, parent:work@div_unit_core_wrapper
|vpiDefName:work@mmu
|vpiFullName:work@mmu
|vpiProcess:
\_always: , line:79
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:79
|vpiCondition:
\_operation: , line:79
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:79
|vpiName:clk
|vpiFullName:work@mmu.clk
|vpiStmt:
\_begin: , line:79
|vpiFullName:work@mmu
|vpiStmt:
\_assignment: , line:80
|vpiOpType:82
|vpiLhs:
\_part_select: , line:80, parent:mmu.new_phys_addr
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (mmu.new_phys_addr)
|vpiLeftRange:
\_constant: , line:80
|vpiConstType:7
|vpiDecompile:19
|vpiSize:32
|INT:19
|vpiRightRange:
\_constant: , line:80
|vpiConstType:7
|vpiDecompile:10
|vpiSize:32
|INT:10
|vpiRhs:
\_ref_obj: (pte.ppn1), line:80
|vpiName:pte.ppn1
|vpiFullName:work@mmu.pte.ppn1
|vpiStmt:
\_if_stmt: , line:82
|vpiCondition:
\_operation: , line:82
|vpiOpType:4
|vpiOperand:
\_ref_obj: (l1_request.request), line:82
|vpiName:l1_request.request
|vpiFullName:work@mmu.l1_request.request
|vpiStmt:
\_assignment: , line:83
|vpiOpType:82
|vpiLhs:
\_ref_obj: (l1_request.addr), line:83
|vpiName:l1_request.addr
|vpiFullName:work@mmu.l1_request.addr
|vpiRhs:
\_ref_obj: (request_addr), line:83
|vpiName:request_addr
|vpiFullName:work@mmu.request_addr
|vpiStmt:
\_if_else: , line:85
|vpiCondition:
\_ref_obj: (second_request), line:85
|vpiName:second_request
|vpiFullName:work@mmu.second_request
|vpiStmt:
\_assignment: , line:86
|vpiOpType:82
|vpiLhs:
\_part_select: , line:86, parent:mmu.new_phys_addr
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (mmu.new_phys_addr)
|vpiLeftRange:
\_constant: , line:86
|vpiConstType:7
|vpiDecompile:9
|vpiSize:32
|INT:9
|vpiRightRange:
\_constant: , line:86
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiRhs:
\_ref_obj: (pte.ppn0), line:86
|vpiName:pte.ppn0
|vpiFullName:work@mmu.pte.ppn0
|vpiElseStmt:
\_assignment: , line:88
|vpiOpType:82
|vpiLhs:
\_part_select: , line:88, parent:mmu.new_phys_addr
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (mmu.new_phys_addr)
|vpiLeftRange:
\_constant: , line:88
|vpiConstType:7
|vpiDecompile:9
|vpiSize:32
|INT:9
|vpiRightRange:
\_constant: , line:88
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiRhs:
\_ref_obj: (mmu.virtual_address), line:88
|vpiName:mmu.virtual_address
|vpiFullName:work@mmu.mmu.virtual_address
|vpiProcess:
\_always: , line:102
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:102
|vpiCondition:
\_operation: , line:102
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:102
|vpiName:clk
|vpiFullName:work@mmu.clk
|vpiStmt:
\_begin: , line:102
|vpiFullName:work@mmu
|vpiStmt:
\_if_else: , line:103
|vpiCondition:
\_ref_obj: (rst), line:103
|vpiName:rst
|vpiFullName:work@mmu.rst
|vpiStmt:
\_begin: , line:103
|vpiFullName:work@mmu
|vpiStmt:
\_assignment: , line:104
|vpiOpType:82
|vpiLhs:
\_ref_obj: (mmu_state), line:104
|vpiName:mmu_state
|vpiFullName:work@mmu.mmu_state
|vpiRhs:
\_ref_obj: (IDLE), line:104
|vpiName:IDLE
|vpiFullName:work@mmu.IDLE
|vpiStmt:
\_assignment: , line:105
|vpiOpType:82
|vpiLhs:
\_ref_obj: (l1_request.request), line:105
|vpiName:l1_request.request
|vpiFullName:work@mmu.l1_request.request
|vpiRhs:
\_constant: , line:105
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiStmt:
\_assignment: , line:106
|vpiOpType:82
|vpiLhs:
\_ref_obj: (mmu.write_entry), line:106
|vpiName:mmu.write_entry
|vpiFullName:work@mmu.mmu.write_entry
|vpiRhs:
\_constant: , line:106
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiStmt:
\_assignment: , line:107
|vpiOpType:82
|vpiLhs:
\_ref_obj: (second_request), line:107
|vpiName:second_request
|vpiFullName:work@mmu.second_request
|vpiRhs:
\_constant: , line:107
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiStmt:
\_assignment: , line:108
|vpiOpType:82
|vpiLhs:
\_ref_obj: (access_exception), line:108
|vpiName:access_exception
|vpiFullName:work@mmu.access_exception
|vpiRhs:
\_constant: , line:108
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiElseStmt:
\_begin: , line:110
|vpiFullName:work@mmu
|vpiStmt:
\_case_stmt: , line:111
|vpiCaseType:1
|vpiQualifier:1
|vpiCondition:
\_ref_obj: (mmu_state), line:111
|vpiName:mmu_state
|vpiFullName:work@mmu.mmu_state
|vpiCaseItem:
\_case_item: , line:112
|vpiExpr:
\_ref_obj: (IDLE), line:112
|vpiName:IDLE
|vpiFullName:work@mmu.IDLE
|vpiStmt:
\_begin: , line:112
|vpiFullName:work@mmu
|vpiStmt:
\_assignment: , line:113
|vpiOpType:82
|vpiLhs:
\_ref_obj: (mmu.write_entry), line:113
|vpiName:mmu.write_entry
|vpiFullName:work@mmu.mmu.write_entry
|vpiRhs:
\_constant: , line:113
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiStmt:
\_assignment: , line:114
|vpiOpType:82
|vpiLhs:
\_ref_obj: (second_request), line:114
|vpiName:second_request
|vpiFullName:work@mmu.second_request
|vpiRhs:
\_constant: , line:114
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiStmt:
\_assignment: , line:115
|vpiOpType:82
|vpiLhs:
\_ref_obj: (access_exception), line:115
|vpiName:access_exception
|vpiFullName:work@mmu.access_exception
|vpiRhs:
\_constant: , line:115
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiStmt:
\_if_stmt: , line:116
|vpiCondition:
\_operation: , line:116
|vpiOpType:28
|vpiOperand:
\_ref_obj: (mmu.new_request), line:116
|vpiName:mmu.new_request
|vpiFullName:work@mmu.mmu.new_request
|vpiOperand:
\_operation: , line:116
|vpiOpType:4
|vpiOperand:
\_ref_obj: (mmu.write_entry), line:116
|vpiName:mmu.write_entry
|vpiFullName:work@mmu.mmu.write_entry
|vpiStmt:
\_begin: , line:116
|vpiFullName:work@mmu
|vpiStmt:
\_assignment: , line:117
|vpiOpType:82
|vpiLhs:
\_ref_obj: (mmu_state), line:117
|vpiName:mmu_state
|vpiFullName:work@mmu.mmu_state
|vpiRhs:
\_ref_obj: (REQUEST), line:117
|vpiName:REQUEST
|vpiFullName:work@mmu.REQUEST
|vpiStmt:
\_assignment: , line:118
|vpiOpType:82
|vpiLhs:
\_ref_obj: (l1_request.request), line:118
|vpiName:l1_request.request
|vpiFullName:work@mmu.l1_request.request
|vpiRhs:
\_constant: , line:118
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiCaseItem:
\_case_item: , line:121
|vpiExpr:
\_ref_obj: (REQUEST), line:121
|vpiName:REQUEST
|vpiFullName:work@mmu.REQUEST
|vpiStmt:
\_begin: , line:121
|vpiFullName:work@mmu
|vpiStmt:
\_if_stmt: , line:122
|vpiCondition:
\_ref_obj: (l1_request.ack), line:122
|vpiName:l1_request.ack
|vpiFullName:work@mmu.l1_request.ack
|vpiStmt:
\_begin: , line:122
|vpiFullName:work@mmu
|vpiStmt:
\_assignment: , line:123
|vpiOpType:82
|vpiLhs:
\_ref_obj: (mmu_state), line:123
|vpiName:mmu_state
|vpiFullName:work@mmu.mmu_state
|vpiRhs:
\_ref_obj: (WAIT), line:123
|vpiName:WAIT
|vpiFullName:work@mmu.WAIT
|vpiStmt:
\_assignment: , line:124
|vpiOpType:82
|vpiLhs:
\_ref_obj: (l1_request.request), line:124
|vpiName:l1_request.request
|vpiFullName:work@mmu.l1_request.request
|vpiRhs:
\_constant: , line:124
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiCaseItem:
\_case_item: , line:127
|vpiExpr:
\_ref_obj: (WAIT), line:127
|vpiName:WAIT
|vpiFullName:work@mmu.WAIT
|vpiStmt:
\_begin: , line:127
|vpiFullName:work@mmu
|vpiStmt:
\_if_stmt: , line:128
|vpiCondition:
\_ref_obj: (l1_response.data_valid), line:128
|vpiName:l1_response.data_valid
|vpiFullName:work@mmu.l1_response.data_valid
|vpiStmt:
\_begin: , line:128
|vpiFullName:work@mmu
|vpiStmt:
\_if_else: , line:129
|vpiCondition:
\_operation: , line:129
|vpiOpType:29
|vpiOperand:
\_operation: , line:129
|vpiOpType:29
|vpiOperand:
\_operation: , line:129
|vpiOpType:4
|vpiOperand:
\_ref_obj: (pte.v), line:129
|vpiName:pte.v
|vpiFullName:work@mmu.pte.v
|vpiOperand:
\_operation: , line:129
|vpiOpType:28
|vpiOperand:
\_operation: , line:129
|vpiOpType:4
|vpiOperand:
\_ref_obj: (pte.r), line:129
|vpiName:pte.r
|vpiFullName:work@mmu.pte.r
|vpiOperand:
\_ref_obj: (pte.w), line:129
|vpiName:pte.w
|vpiFullName:work@mmu.pte.w
|vpiOperand:
\_operation: , line:129
|vpiOpType:28
|vpiOperand:
\_operation: , line:129
|vpiOpType:28
|vpiOperand:
\_operation: , line:129
|vpiOpType:4
|vpiOperand:
\_ref_obj: (pte.r), line:129
|vpiName:pte.r
|vpiFullName:work@mmu.pte.r
|vpiOperand:
\_operation: , line:129
|vpiOpType:4
|vpiOperand:
\_ref_obj: (pte.x), line:129
|vpiName:pte.x
|vpiFullName:work@mmu.pte.x
|vpiOperand:
\_ref_obj: (second_request), line:129
|vpiName:second_request
|vpiFullName:work@mmu.second_request
|vpiStmt:
\_begin: , line:129
|vpiFullName:work@mmu
|vpiStmt:
\_assignment: , line:130
|vpiOpType:82
|vpiLhs:
\_ref_obj: (mmu_state), line:130
|vpiName:mmu_state
|vpiFullName:work@mmu.mmu_state
|vpiRhs:
\_ref_obj: (IDLE), line:130
|vpiName:IDLE
|vpiFullName:work@mmu.IDLE
|vpiStmt:
\_assignment: , line:131
|vpiOpType:82
|vpiLhs:
\_ref_obj: (access_exception), line:131
|vpiName:access_exception
|vpiFullName:work@mmu.access_exception
|vpiRhs:
\_constant: , line:131
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiElseStmt:
\_if_else: , line:133
|vpiCondition:
\_operation: , line:133
|vpiOpType:29
|vpiOperand:
\_ref_obj: (pte.r), line:133
|vpiName:pte.r
|vpiFullName:work@mmu.pte.r
|vpiOperand:
\_ref_obj: (pte.x), line:133
|vpiName:pte.x
|vpiFullName:work@mmu.pte.x
|vpiStmt:
\_begin: , line:133
|vpiFullName:work@mmu
|vpiStmt:
\_assignment: , line:134
|vpiOpType:82
|vpiLhs:
\_ref_obj: (mmu_state), line:134
|vpiName:mmu_state
|vpiFullName:work@mmu.mmu_state
|vpiRhs:
\_ref_obj: (IDLE), line:134
|vpiName:IDLE
|vpiFullName:work@mmu.IDLE
|vpiStmt:
\_if_else: , line:135
|vpiCondition:
\_ref_obj: (permissions_check), line:135
|vpiName:permissions_check
|vpiFullName:work@mmu.permissions_check
|vpiStmt:
\_assignment: , line:136
|vpiOpType:82
|vpiLhs:
\_ref_obj: (mmu.write_entry), line:136
|vpiName:mmu.write_entry
|vpiFullName:work@mmu.mmu.write_entry
|vpiRhs:
\_constant: , line:136
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiElseStmt:
\_assignment: , line:138
|vpiOpType:82
|vpiLhs:
\_ref_obj: (access_exception), line:138
|vpiName:access_exception
|vpiFullName:work@mmu.access_exception
|vpiRhs:
\_constant: , line:138
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiElseStmt:
\_begin: , line:140
|vpiFullName:work@mmu
|vpiStmt:
\_assignment: , line:141
|vpiOpType:82
|vpiLhs:
\_ref_obj: (mmu_state), line:141
|vpiName:mmu_state
|vpiFullName:work@mmu.mmu_state
|vpiRhs:
\_ref_obj: (REQUEST), line:141
|vpiName:REQUEST
|vpiFullName:work@mmu.REQUEST
|vpiStmt:
\_assignment: , line:142
|vpiOpType:82
|vpiLhs:
\_ref_obj: (l1_request.request), line:142
|vpiName:l1_request.request
|vpiFullName:work@mmu.l1_request.request
|vpiRhs:
\_constant: , line:142
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiStmt:
\_assignment: , line:143
|vpiOpType:82
|vpiLhs:
\_ref_obj: (second_request), line:143
|vpiName:second_request
|vpiFullName:work@mmu.second_request
|vpiRhs:
\_constant: , line:143
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiPort:
\_port: (clk), line:29
|vpiName:clk
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (clk), line:29
|vpiName:clk
|vpiFullName:work@mmu.clk
|vpiNetType:36
|vpiPort:
\_port: (rst), line:30
|vpiName:rst
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (rst), line:30
|vpiName:rst
|vpiFullName:work@mmu.rst
|vpiNetType:36
|vpiPort:
\_port: (mmu), line:31
|vpiName:mmu
|vpiDirection:5
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_modport: (mmu)
|vpiPort:
\_port: (l1_request), line:32
|vpiName:l1_request
|vpiDirection:5
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_modport: (master)
|vpiPort:
\_port: (l1_response), line:33
|vpiName:l1_response
|vpiDirection:5
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_modport: (master)
|vpiPort:
\_port: (mmu_exception), line:34
|vpiName:mmu_exception
|vpiDirection:2
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (mmu_exception), line:34
|vpiName:mmu_exception
|vpiFullName:work@mmu.mmu_exception
|vpiContAssign:
\_cont_assign: , line:63
|vpiRhs:
\_constant: , line:63
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiLhs:
\_ref_obj: (l1_request.rnw), line:63
|vpiName:l1_request.rnw
|vpiFullName:work@mmu.l1_request.rnw
|vpiContAssign:
\_cont_assign: , line:64
|vpiRhs:
\_constant: , line:64
|vpiConstType:3
|vpiDecompile:'b1
|vpiSize:1
|BIN:1
|vpiLhs:
\_ref_obj: (l1_request.be), line:64
|vpiName:l1_request.be
|vpiFullName:work@mmu.l1_request.be
|vpiContAssign:
\_cont_assign: , line:65
|vpiRhs:
\_constant: , line:65
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiLhs:
\_ref_obj: (l1_request.size), line:65
|vpiName:l1_request.size
|vpiFullName:work@mmu.l1_request.size
|vpiContAssign:
\_cont_assign: , line:66
|vpiRhs:
\_constant: , line:66
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiLhs:
\_ref_obj: (l1_request.is_amo), line:66
|vpiName:l1_request.is_amo
|vpiFullName:work@mmu.l1_request.is_amo
|vpiContAssign:
\_cont_assign: , line:67
|vpiRhs:
\_constant: , line:67
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiLhs:
\_ref_obj: (l1_request.amo), line:67
|vpiName:l1_request.amo
|vpiFullName:work@mmu.l1_request.amo
|vpiContAssign:
\_cont_assign: , line:70
|vpiRhs:
\_ref_obj: (l1_response.data), line:70
|vpiName:l1_response.data
|vpiFullName:work@mmu.l1_response.data
|vpiLhs:
\_ref_obj: (pte), line:70
|vpiName:pte
|vpiFullName:work@mmu.pte
|vpiContAssign:
\_cont_assign: , line:72
|vpiRhs:
\_ref_obj: (access_exception), line:72
|vpiName:access_exception
|vpiFullName:work@mmu.access_exception
|vpiLhs:
\_ref_obj: (mmu_exception), line:72
|vpiName:mmu_exception
|vpiFullName:work@mmu.mmu_exception
|vpiContAssign:
\_cont_assign: , line:75
|vpiRhs:
\_operation: , line:75
|vpiOpType:32
|vpiOperand:
\_operation: , line:75
|vpiOpType:14
|vpiOperand:
\_ref_obj: (mmu_state), line:75
|vpiName:mmu_state
|vpiFullName:work@mmu.mmu_state
|vpiOperand:
\_ref_obj: (IDLE), line:75
|vpiName:IDLE
|vpiFullName:work@mmu.IDLE
|vpiOperand:
\_ref_obj: (mmu.ppn), line:75
|vpiName:mmu.ppn
|vpiFullName:work@mmu.mmu.ppn
|vpiOperand:
\_operation: , line:75
|vpiOpType:33
|vpiOperand:
\_ref_obj: (pte.ppn1), line:75
|vpiName:pte.ppn1
|vpiFullName:work@mmu.pte.ppn1
|vpiOperand:
\_ref_obj: (pte.ppn0), line:75
|vpiName:pte.ppn0
|vpiFullName:work@mmu.pte.ppn0
|vpiLhs:
\_ref_obj: (request_addr_input_a), line:75
|vpiName:request_addr_input_a
|vpiFullName:work@mmu.request_addr_input_a
|vpiContAssign:
\_cont_assign: , line:76
|vpiRhs:
\_operation: , line:76
|vpiOpType:32
|vpiOperand:
\_operation: , line:76
|vpiOpType:14
|vpiOperand:
\_ref_obj: (mmu_state), line:76
|vpiName:mmu_state
|vpiFullName:work@mmu.mmu_state
|vpiOperand:
\_ref_obj: (IDLE), line:76
|vpiName:IDLE
|vpiFullName:work@mmu.IDLE
|vpiOperand:
\_ref_obj: (mmu.virtual_address), line:76
|vpiName:mmu.virtual_address
|vpiFullName:work@mmu.mmu.virtual_address
|vpiOperand:
\_ref_obj: (mmu.virtual_address), line:76
|vpiName:mmu.virtual_address
|vpiFullName:work@mmu.mmu.virtual_address
|vpiLhs:
\_ref_obj: (request_addr_input_b), line:76
|vpiName:request_addr_input_b
|vpiFullName:work@mmu.request_addr_input_b
|vpiContAssign:
\_cont_assign: , line:77
|vpiRhs:
\_operation: , line:77
|vpiOpType:24
|vpiOperand:
\_operation: , line:77
|vpiOpType:33
|vpiOperand:
\_ref_obj: (request_addr_input_a), line:77
|vpiName:request_addr_input_a
|vpiOperand:
\_constant: , line:77
|vpiConstType:3
|vpiDecompile:12'd0
|BIN:12'd0
|vpiOperand:
\_operation: , line:77
|vpiOpType:33
|vpiOperand:
\_ref_obj: (request_addr_input_b), line:77
|vpiName:request_addr_input_b
|vpiFullName:work@mmu.request_addr_input_b
|vpiOperand:
\_constant: , line:77
|vpiConstType:3
|vpiDecompile:2'b00
|vpiSize:2
|BIN:2'b00
|vpiLhs:
\_ref_obj: (request_addr), line:77
|vpiName:request_addr
|vpiFullName:work@mmu.request_addr
|vpiContAssign:
\_cont_assign: , line:92
|vpiRhs:
\_operation: , line:92
|vpiOpType:3
|vpiOperand:
\_operation: , line:93
|vpiOpType:29
|vpiOperand:
\_operation: , line:93
|vpiOpType:26
|vpiOperand:
\_operation: , line:93
|vpiOpType:14
|vpiOperand:
\_ref_obj: (mmu.privilege), line:93
|vpiName:mmu.privilege
|vpiFullName:work@mmu.mmu.privilege
|vpiOperand:
\_ref_obj: (USER_PRIVILEGE), line:93
|vpiName:USER_PRIVILEGE
|vpiFullName:work@mmu.USER_PRIVILEGE
|vpiOperand:
\_operation: , line:93
|vpiOpType:4
|vpiOperand:
\_ref_obj: (pte.u), line:93
|vpiName:pte.u
|vpiFullName:work@mmu.pte.u
|vpiOperand:
\_operation: , line:94
|vpiOpType:26
|vpiOperand:
\_operation: , line:94
|vpiOpType:26
|vpiOperand:
\_operation: , line:94
|vpiOpType:14
|vpiOperand:
\_ref_obj: (mmu.privilege), line:94
|vpiName:mmu.privilege
|vpiFullName:work@mmu.mmu.privilege
|vpiOperand:
\_ref_obj: (SUPERVISOR_PRIVILEGE), line:94
|vpiName:SUPERVISOR_PRIVILEGE
|vpiFullName:work@mmu.SUPERVISOR_PRIVILEGE
|vpiOperand:
\_ref_obj: (pte.u), line:94
|vpiName:pte.u
|vpiFullName:work@mmu.pte.u
|vpiOperand:
\_ref_obj: (mmu.pum), line:94
|vpiName:mmu.pum
|vpiFullName:work@mmu.mmu.pum
|vpiLhs:
\_ref_obj: (privilege_check), line:92
|vpiName:privilege_check
|vpiFullName:work@mmu.privilege_check
|vpiContAssign:
\_cont_assign: , line:97
|vpiRhs:
\_operation: , line:97
|vpiOpType:28
|vpiOperand:
\_ref_obj: (privilege_check), line:97
|vpiName:privilege_check
|vpiFullName:work@mmu.privilege_check
|vpiOperand:
\_operation: , line:97
|vpiOpType:29
|vpiOperand:
\_operation: , line:97
|vpiOpType:28
|vpiOperand:
\_ref_obj: (mmu.execute), line:97
|vpiName:mmu.execute
|vpiFullName:work@mmu.mmu.execute
|vpiOperand:
\_ref_obj: (pte.x), line:97
|vpiName:pte.x
|vpiFullName:work@mmu.pte.x
|vpiOperand:
\_operation: , line:98
|vpiOpType:28
|vpiOperand:
\_operation: , line:98
|vpiOpType:4
|vpiOperand:
\_ref_obj: (mmu.execute), line:98
|vpiName:mmu.execute
|vpiFullName:work@mmu.mmu.execute
|vpiOperand:
\_operation: , line:99
|vpiOpType:29
|vpiOperand:
\_operation: , line:99
|vpiOpType:28
|vpiOperand:
\_ref_obj: (mmu.rnw), line:99
|vpiName:mmu.rnw
|vpiFullName:work@mmu.mmu.rnw
|vpiOperand:
\_operation: , line:99
|vpiOpType:29
|vpiOperand:
\_ref_obj: (pte.r), line:99
|vpiName:pte.r
|vpiFullName:work@mmu.pte.r
|vpiOperand:
\_operation: , line:99
|vpiOpType:28
|vpiOperand:
\_ref_obj: (pte.x), line:99
|vpiName:pte.x
|vpiFullName:work@mmu.pte.x
|vpiOperand:
\_ref_obj: (mmu.mxr), line:99
|vpiName:mmu.mxr
|vpiFullName:work@mmu.mmu.mxr
|vpiOperand:
\_operation: , line:100
|vpiOpType:28
|vpiOperand:
\_operation: , line:100
|vpiOpType:4
|vpiOperand:
\_ref_obj: (mmu.rnw), line:100
|vpiName:mmu.rnw
|vpiFullName:work@mmu.mmu.rnw
|vpiOperand:
\_ref_obj: (pte.w), line:100
|vpiName:pte.w
|vpiFullName:work@mmu.pte.w
|vpiLhs:
\_ref_obj: (permissions_check), line:97
|vpiName:permissions_check
|vpiFullName:work@mmu.permissions_check
|vpiNet:
\_logic_net: (clk), line:29
|vpiNet:
\_logic_net: (rst), line:30
|vpiNet:
\_logic_net: (mmu_exception), line:34
|vpiNet:
\_logic_net: (request_addr), line:51
|vpiName:request_addr
|vpiFullName:work@mmu.request_addr
|vpiNetType:36
|vpiNet:
\_logic_net: (request_addr_input_a), line:52
|vpiName:request_addr_input_a
|vpiFullName:work@mmu.request_addr_input_a
|vpiNetType:36
|vpiNet:
\_logic_net: (request_addr_input_b), line:53
|vpiName:request_addr_input_b
|vpiFullName:work@mmu.request_addr_input_b
|vpiNetType:36
|vpiNet:
\_logic_net: (privilege_check), line:55
|vpiName:privilege_check
|vpiFullName:work@mmu.privilege_check
|vpiNetType:36
|vpiNet:
\_logic_net: (permissions_check), line:56
|vpiName:permissions_check
|vpiFullName:work@mmu.permissions_check
|vpiNetType:36
|vpiNet:
\_logic_net: (second_request), line:58
|vpiName:second_request
|vpiFullName:work@mmu.second_request
|vpiNetType:36
|vpiNet:
\_logic_net: (access_exception), line:59
|vpiName:access_exception
|vpiFullName:work@mmu.access_exception
|vpiNetType:36
|vpiNet:
\_logic_net: (mmu_state), line:61
|vpiName:mmu_state
|vpiFullName:work@mmu.mmu_state
|vpiNet:
\_logic_net: (pte), line:69
|vpiName:pte
|vpiFullName:work@mmu.pte
|vpiNet:
\_logic_net: (mmu), line:31
|vpiName:mmu
|vpiFullName:work@mmu.mmu
|vpiNet:
\_logic_net: (l1_request), line:32
|vpiName:l1_request
|vpiFullName:work@mmu.l1_request
|vpiNet:
\_logic_net: (l1_response), line:33
|vpiName:l1_response
|vpiFullName:work@mmu.l1_response
|vpiTypedef:
\_struct_typespec: (alu_inputs_t), line:301
|vpiTypedef:
\_enum_typespec: (alu_logic_op_t), line:84
|vpiTypedef:
\_enum_typespec: (alu_op_t), line:91
|vpiTypedef:
\_enum_typespec: (alu_rs1_op_t), line:97
|vpiTypedef:
\_enum_typespec: (alu_rs2_op_t), line:104
|vpiTypedef:
\_struct_typespec: (amo_alu_inputs_t), line:356
|vpiTypedef:
\_struct_typespec: (amo_details_t), line:362
|vpiTypedef:
\_enum_typespec: (amo_t), line:354
|vpiTypedef:
\_struct_typespec: (branch_inputs_t), line:313
|vpiTypedef:
\_logic_typespec: (branch_predictor_metadata_t), line:32
|vpiTypedef:
\_struct_typespec: (branch_results_t), line:330
|vpiTypedef:
\_enum_typespec: (bus_type_t), line:86
|vpiTypedef:
\_struct_typespec: (csr_addr_t), line:37
|vpiTypedef:
\_struct_typespec: (csr_inputs_t), line:396
|vpiTypedef:
\_enum_typespec: (csr_op_t), line:218
|vpiTypedef:
\_enum_typespec: (csr_t), line:201
|vpiTypedef:
\_struct_typespec: (data_access_shared_inputs_t), line:427
|vpiTypedef:
\_struct_typespec: (div_inputs_t), line:389
|vpiTypedef:
\_enum_typespec: (div_type), line:66
|vpiTypedef:
\_enum_typespec: (exception_code_t), line:245
|vpiTypedef:
\_struct_typespec: (exception_packet_t), line:263
|vpiTypedef:
\_struct_typespec: (fetch_buffer_packet_t), line:276
|vpiTypedef:
\_enum_typespec: (fifo_type_t), line:440
|vpiTypedef:
\_enum_typespec: (fn3_arith_t), line:76
|vpiTypedef:
\_enum_typespec: (fn3_branch_t), line:126
|vpiTypedef:
\_enum_typespec: (fn3_csr_t), line:212
|vpiTypedef:
\_enum_typespec: (fn3_ls_t), line:115
|vpiTypedef:
\_enum_typespec: (fn3_mul_div_t), line:138
|vpiTypedef:
\_struct_typespec: (gc_inputs_t), line:404
|vpiTypedef:
\_struct_typespec: (inflight_instruction_packet), line:271
|vpiTypedef:
\_logic_typespec: (instruction_id_t), line:30
|vpiTypedef:
\_enum_typespec: (interrupt_code_t), line:261
|vpiTypedef:
\_struct_typespec: (load_store_inputs_t), line:369
|vpiTypedef:
\_struct_typespec: (mcause_t), line:135
|vpiTypedef:
\_struct_typespec: (mie_t), line:119
|vpiTypedef:
\_struct_typespec: (mip_t), line:103
|vpiTypedef:
\_struct_typespec: (misa_t), line:45
|vpiTypedef:
\_enum_typespec: (mmu_state_t), line:60
|vpiName:mmu_state_t
|vpiBaseTypespec:
\_logic_typespec: , line:60
|vpiRange:
\_range: , line:60
|vpiLeftRange:
\_constant: , line:60
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:60
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiEnumConst:
\_enum_const: (IDLE), line:60
|vpiName:IDLE
|INT:0
|vpiEnumConst:
\_enum_const: (REQUEST), line:60
|vpiName:REQUEST
|INT:1
|vpiEnumConst:
\_enum_const: (WAIT), line:60
|vpiName:WAIT
|INT:2
|vpiTypedef:
\_struct_typespec: (mstatus_t), line:78
|vpiTypedef:
\_struct_typespec: (mul_inputs_t), line:383
|vpiTypedef:
\_enum_typespec: (opcodes_t), line:48
|vpiTypedef:
\_enum_typespec: (opcodes_trimmed_t), line:65
|vpiTypedef:
\_enum_typespec: (privilege_t), line:34
|vpiTypedef:
\_struct_typespec: (pte_t), line:37
|vpiPacked:1
|vpiName:pte_t
|vpiTypespecMember:
\_typespec_member: (ppn1), line:38
|vpiName:ppn1
|vpiTypespec:
\_logic_typespec: , line:38
|vpiRange:
\_range: , line:38, parent:pte_t
|vpiLeftRange:
\_constant: , line:38
|vpiConstType:7
|vpiDecompile:11
|vpiSize:32
|INT:11
|vpiRightRange:
\_constant: , line:38
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiTypespecMember:
\_typespec_member: (ppn0), line:39
|vpiName:ppn0
|vpiTypespec:
\_logic_typespec: , line:39
|vpiRange:
\_range: , line:39, parent:pte_t
|vpiLeftRange:
\_constant: , line:39
|vpiConstType:7
|vpiDecompile:9
|vpiSize:32
|INT:9
|vpiRightRange:
\_constant: , line:39
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiTypespecMember:
\_typespec_member: (reserved), line:40
|vpiName:reserved
|vpiTypespec:
\_logic_typespec: , line:40
|vpiRange:
\_range: , line:40, parent:pte_t
|vpiLeftRange:
\_constant: , line:40
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:40
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiTypespecMember:
\_typespec_member: (d), line:41
|vpiName:d
|vpiTypespec:
\_logic_typespec: , line:41
|vpiTypespecMember:
\_typespec_member: (a), line:42
|vpiName:a
|vpiTypespec:
\_logic_typespec: , line:42
|vpiTypespecMember:
\_typespec_member: (g), line:43
|vpiName:g
|vpiTypespec:
\_logic_typespec: , line:43
|vpiTypespecMember:
\_typespec_member: (u), line:44
|vpiName:u
|vpiTypespec:
\_logic_typespec: , line:44
|vpiTypespecMember:
\_typespec_member: (x), line:45
|vpiName:x
|vpiTypespec:
\_logic_typespec: , line:45
|vpiTypespecMember:
\_typespec_member: (w), line:46
|vpiName:w
|vpiTypespec:
\_logic_typespec: , line:46
|vpiTypespecMember:
\_typespec_member: (r), line:47
|vpiName:r
|vpiTypespec:
\_logic_typespec: , line:47
|vpiTypespecMember:
\_typespec_member: (v), line:48
|vpiName:v
|vpiTypespec:
\_logic_typespec: , line:48
|vpiTypedef:
\_struct_typespec: (satp_t), line:142
|vpiTypedef:
\_struct_typespec: (simulation_named_regfile), line:476
|vpiTypedef:
\_struct_typespec: (taiga_trace_events_t), line:442
|vpiTypedef:
\_struct_typespec: (to_l1_arbiter_packet), line:418
|vpiTypedef:
\_struct_typespec: (trace_outputs_t), line:469
|vpiTypedef:
\_logic_typespec: (unit_id_t), line:31
|vpiTypedef:
\_struct_typespec: (unit_writeback_t), line:295
|vpiTypedef:
\_enum_typespec: (vm_t), line:223
|uhdmallModules:
\_module: work@msb, file:third_party/cores/taiga/core/msb.sv, line:23, parent:work@div_unit_core_wrapper
|vpiDefName:work@msb
|vpiFullName:work@msb
|vpiProcess:
\_always: , line:33
|vpiAlwaysType:2
|vpiStmt:
\_begin: , line:33
|vpiFullName:work@msb
|vpiStmt:
\_for_stmt: , line:34
|vpiFullName:work@msb
|vpiCondition:
\_operation: , line:34
|vpiOpType:20
|vpiOperand:
\_ref_obj: (i), line:34
|vpiName:i
|vpiFullName:work@msb.i
|vpiOperand:
\_constant: , line:34
|vpiConstType:7
|vpiDecompile:4
|vpiSize:32
|INT:4
|vpiForInitStmt:
\_assign_stmt:
|vpiRhs:
\_constant: , line:34
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiLhs:
\_int_var: (i), line:34
|vpiName:i
|vpiFullName:work@msb.i
|vpiForIncStmt:
\_operation: , line:34
|vpiOpType:62
|vpiOperand:
\_ref_obj: (i), line:34
|vpiName:i
|vpiStmt:
\_begin: , line:34
|vpiFullName:work@msb
|vpiStmt:
\_assignment: , line:35
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_bit_select: (quadrant), line:35
|vpiName:quadrant
|vpiFullName:work@msb.quadrant
|vpiIndex:
\_ref_obj: (i), line:35
|vpiName:i
|vpiRhs:
\_operation: , line:35
|vpiOpType:7
|vpiOperand:
\_indexed_part_select: , line:35, parent:msb_input
|vpiConstantSelect:1
|vpiIndexedPartSelectType:1
|vpiBaseExpr:
\_operation: , line:35
|vpiOpType:25
|vpiOperand:
\_ref_obj: (i), line:35
|vpiName:i
|vpiFullName:work@msb.i
|vpiOperand:
\_constant: , line:35
|vpiConstType:7
|vpiDecompile:8
|vpiSize:32
|INT:8
|vpiWidthExpr:
\_constant: , line:35
|vpiConstType:7
|vpiDecompile:8
|vpiSize:32
|INT:8
|vpiStmt:
\_assignment: , line:38
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_bit_select: (msb), line:38
|vpiName:msb
|vpiFullName:work@msb.msb
|vpiIndex:
\_constant: , line:38
|vpiConstType:7
|vpiDecompile:4
|vpiSize:32
|INT:4
|vpiRhs:
\_operation: , line:38
|vpiOpType:29
|vpiOperand:
\_bit_select: (quadrant), line:38
|vpiName:quadrant
|vpiFullName:work@msb.quadrant
|vpiIndex:
\_constant: , line:38
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiOperand:
\_bit_select: (quadrant), line:38
|vpiName:quadrant
|vpiFullName:work@msb.quadrant
|vpiIndex:
\_constant: , line:38
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiStmt:
\_assignment: , line:39
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_bit_select: (msb), line:39
|vpiName:msb
|vpiFullName:work@msb.msb
|vpiIndex:
\_constant: , line:39
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiRhs:
\_operation: , line:39
|vpiOpType:29
|vpiOperand:
\_bit_select: (quadrant), line:39
|vpiName:quadrant
|vpiFullName:work@msb.quadrant
|vpiIndex:
\_constant: , line:39
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiOperand:
\_operation: , line:39
|vpiOpType:28
|vpiOperand:
\_operation: , line:39
|vpiOpType:4
|vpiOperand:
\_bit_select: (quadrant), line:39
|vpiName:quadrant
|vpiIndex:
\_constant: , line:39
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiOperand:
\_bit_select: (quadrant), line:39
|vpiName:quadrant
|vpiFullName:work@msb.quadrant
|vpiIndex:
\_constant: , line:39
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiStmt:
\_for_stmt: , line:41
|vpiFullName:work@msb
|vpiCondition:
\_operation: , line:41
|vpiOpType:20
|vpiOperand:
\_ref_obj: (i), line:41
|vpiName:i
|vpiFullName:work@msb.i
|vpiOperand:
\_constant: , line:41
|vpiConstType:7
|vpiDecompile:8
|vpiSize:32
|INT:8
|vpiForInitStmt:
\_assign_stmt:
|vpiRhs:
\_constant: , line:41
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiLhs:
\_int_var: (i), line:41
|vpiName:i
|vpiFullName:work@msb.i
|vpiForIncStmt:
\_operation: , line:41
|vpiOpType:62
|vpiOperand:
\_ref_obj: (i), line:41
|vpiName:i
|vpiStmt:
\_begin: , line:41
|vpiFullName:work@msb
|vpiStmt:
\_case_stmt: , line:42
|vpiCaseType:3
|vpiCondition:
\_indexed_part_select: , line:42, parent:msb_input
|vpiConstantSelect:1
|vpiIndexedPartSelectType:1
|vpiBaseExpr:
\_operation: , line:42
|vpiOpType:24
|vpiOperand:
\_constant: , line:42
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiOperand:
\_operation: , line:42
|vpiOpType:25
|vpiOperand:
\_ref_obj: (i), line:42
|vpiName:i
|vpiOperand:
\_constant: , line:42
|vpiConstType:7
|vpiDecompile:4
|vpiSize:32
|INT:4
|vpiWidthExpr:
\_constant: , line:42
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiCaseItem:
\_case_item: , line:43
|vpiExpr:
\_constant: , line:43
|vpiConstType:3
|vpiDecompile:3'b1??
|vpiSize:3
|BIN:3'b1??
|vpiStmt:
\_assignment: , line:43
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_bit_select: (sub_sub_msb), line:43
|vpiName:sub_sub_msb
|vpiFullName:work@msb.sub_sub_msb
|vpiIndex:
\_ref_obj: (i), line:43
|vpiName:i
|vpiRhs:
\_constant: , line:43
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiCaseItem:
\_case_item: , line:44
|vpiExpr:
\_constant: , line:44
|vpiConstType:3
|vpiDecompile:3'b01?
|vpiSize:3
|BIN:3'b01?
|vpiStmt:
\_assignment: , line:44
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_bit_select: (sub_sub_msb), line:44
|vpiName:sub_sub_msb
|vpiFullName:work@msb.sub_sub_msb
|vpiIndex:
\_ref_obj: (i), line:44
|vpiName:i
|vpiRhs:
\_constant: , line:44
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiCaseItem:
\_case_item: , line:45
|vpiExpr:
\_constant: , line:45
|vpiConstType:3
|vpiDecompile:3'b001
|vpiSize:3
|BIN:3'b001
|vpiStmt:
\_assignment: , line:45
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_bit_select: (sub_sub_msb), line:45
|vpiName:sub_sub_msb
|vpiFullName:work@msb.sub_sub_msb
|vpiIndex:
\_ref_obj: (i), line:45
|vpiName:i
|vpiRhs:
\_constant: , line:45
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiCaseItem:
\_case_item: , line:46
|vpiStmt:
\_assignment: , line:46
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_bit_select: (sub_sub_msb), line:46
|vpiName:sub_sub_msb
|vpiFullName:work@msb.sub_sub_msb
|vpiIndex:
\_ref_obj: (i), line:46
|vpiName:i
|vpiRhs:
\_constant: , line:46
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiStmt:
\_for_stmt: , line:50
|vpiFullName:work@msb
|vpiCondition:
\_operation: , line:50
|vpiOpType:20
|vpiOperand:
\_ref_obj: (i), line:50
|vpiName:i
|vpiFullName:work@msb.i
|vpiOperand:
\_constant: , line:50
|vpiConstType:7
|vpiDecompile:4
|vpiSize:32
|INT:4
|vpiForInitStmt:
\_assign_stmt:
|vpiRhs:
\_constant: , line:50
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiLhs:
\_int_var: (i), line:50
|vpiName:i
|vpiFullName:work@msb.i
|vpiForIncStmt:
\_operation: , line:50
|vpiOpType:62
|vpiOperand:
\_ref_obj: (i), line:50
|vpiName:i
|vpiStmt:
\_begin: , line:50
|vpiFullName:work@msb
|vpiStmt:
\_assignment: , line:51
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_bit_select: (sub_msb), line:51
|vpiName:sub_msb
|vpiFullName:work@msb.sub_msb
|vpiIndex:
\_ref_obj: (i), line:51
|vpiName:i
|vpiRhs:
\_operation: , line:51
|vpiOpType:7
|vpiOperand:
\_indexed_part_select: , line:51, parent:msb_input
|vpiConstantSelect:1
|vpiIndexedPartSelectType:1
|vpiBaseExpr:
\_operation: , line:51
|vpiOpType:24
|vpiOperand:
\_constant: , line:51
|vpiConstType:7
|vpiDecompile:4
|vpiSize:32
|INT:4
|vpiOperand:
\_operation: , line:51
|vpiOpType:25
|vpiOperand:
\_ref_obj: (i), line:51
|vpiName:i
|vpiFullName:work@msb.i
|vpiOperand:
\_constant: , line:51
|vpiConstType:7
|vpiDecompile:8
|vpiSize:32
|INT:8
|vpiWidthExpr:
\_constant: , line:51
|vpiConstType:7
|vpiDecompile:4
|vpiSize:32
|INT:4
|vpiStmt:
\_assignment: , line:52
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_bit_select: (sub_msb), line:52
|vpiName:sub_msb
|vpiFullName:work@msb.sub_msb
|vpiIndex:
\_ref_obj: (i), line:52
|vpiName:i
|vpiRhs:
\_operation: , line:52
|vpiOpType:29
|vpiOperand:
\_operation: , line:52
|vpiOpType:7
|vpiOperand:
\_indexed_part_select: , line:52, parent:msb_input
|vpiConstantSelect:1
|vpiIndexedPartSelectType:1
|vpiBaseExpr:
\_operation: , line:52
|vpiOpType:24
|vpiOperand:
\_constant: , line:52
|vpiConstType:7
|vpiDecompile:6
|vpiSize:32
|INT:6
|vpiOperand:
\_operation: , line:52
|vpiOpType:25
|vpiOperand:
\_ref_obj: (i), line:52
|vpiName:i
|vpiFullName:work@msb.i
|vpiOperand:
\_constant: , line:52
|vpiConstType:7
|vpiDecompile:8
|vpiSize:32
|INT:8
|vpiWidthExpr:
\_constant: , line:52
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiOperand:
\_operation: , line:52
|vpiOpType:28
|vpiOperand:
\_operation: , line:52
|vpiOpType:8
|vpiOperand:
\_indexed_part_select: , line:52, parent:msb_input
|vpiConstantSelect:1
|vpiIndexedPartSelectType:1
|vpiBaseExpr:
\_operation: , line:52
|vpiOpType:24
|vpiOperand:
\_constant: , line:52
|vpiConstType:7
|vpiDecompile:4
|vpiSize:32
|INT:4
|vpiOperand:
\_operation: , line:52
|vpiOpType:25
|vpiOperand:
\_ref_obj: (i), line:52
|vpiName:i
|vpiFullName:work@msb.i
|vpiOperand:
\_constant: , line:52
|vpiConstType:7
|vpiDecompile:8
|vpiSize:32
|INT:8
|vpiWidthExpr:
\_constant: , line:52
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiOperand:
\_operation: , line:52
|vpiOpType:7
|vpiOperand:
\_indexed_part_select: , line:52, parent:msb_input
|vpiConstantSelect:1
|vpiIndexedPartSelectType:1
|vpiBaseExpr:
\_operation: , line:52
|vpiOpType:24
|vpiOperand:
\_constant: , line:52
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiOperand:
\_operation: , line:52
|vpiOpType:25
|vpiOperand:
\_ref_obj: (i), line:52
|vpiName:i
|vpiFullName:work@msb.i
|vpiOperand:
\_constant: , line:52
|vpiConstType:7
|vpiDecompile:8
|vpiSize:32
|INT:8
|vpiWidthExpr:
\_constant: , line:52
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiStmt:
\_assignment: , line:53
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_bit_select: (sub_msb), line:53
|vpiName:sub_msb
|vpiFullName:work@msb.sub_msb
|vpiIndex:
\_ref_obj: (i), line:53
|vpiName:i
|vpiRhs:
\_operation: , line:53
|vpiOpType:32
|vpiOperand:
\_bit_select: (sub_msb), line:53
|vpiName:sub_msb
|vpiFullName:work@msb.sub_msb
|vpiIndex:
\_ref_obj: (i), line:53
|vpiName:i
|vpiOperand:
\_bit_select: (sub_sub_msb), line:53
|vpiName:sub_sub_msb
|vpiFullName:work@msb.sub_sub_msb
|vpiIndex:
\_operation: , line:53
|vpiOpType:24
|vpiOperand:
\_operation: , line:53
|vpiOpType:25
|vpiOperand:
\_ref_obj: (i), line:53
|vpiName:i
|vpiFullName:work@msb.i
|vpiOperand:
\_constant: , line:53
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiOperand:
\_constant: , line:53
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiOperand:
\_bit_select: (sub_sub_msb), line:53
|vpiName:sub_sub_msb
|vpiFullName:work@msb.sub_sub_msb
|vpiIndex:
\_operation: , line:53
|vpiOpType:25
|vpiOperand:
\_ref_obj: (i), line:53
|vpiName:i
|vpiFullName:work@msb.i
|vpiOperand:
\_constant: , line:53
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiStmt:
\_assignment: , line:56
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_part_select: , line:56, parent:msb
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (msb)
|vpiLeftRange:
\_constant: , line:56
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiRightRange:
\_constant: , line:56
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiRhs:
\_bit_select: (sub_msb), line:56
|vpiName:sub_msb
|vpiFullName:work@msb.sub_msb
|vpiIndex:
\_part_select: , line:56, parent:msb
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (msb)
|vpiLeftRange:
\_constant: , line:56
|vpiConstType:7
|vpiDecompile:4
|vpiSize:32
|INT:4
|vpiRightRange:
\_constant: , line:56
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiPort:
\_port: (msb_input), line:25
|vpiName:msb_input
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (msb_input), line:25
|vpiName:msb_input
|vpiFullName:work@msb.msb_input
|vpiNetType:36
|vpiPort:
\_port: (msb), line:26
|vpiName:msb
|vpiDirection:2
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (msb), line:26
|vpiName:msb
|vpiFullName:work@msb.msb
|vpiNetType:36
|vpiNet:
\_logic_net: (msb_input), line:25
|vpiNet:
\_logic_net: (msb), line:26
|vpiNet:
\_logic_net: (sub_msb), line:29
|vpiName:sub_msb
|vpiFullName:work@msb.sub_msb
|vpiNetType:36
|vpiNet:
\_logic_net: (sub_sub_msb), line:30
|vpiName:sub_sub_msb
|vpiFullName:work@msb.sub_sub_msb
|vpiNetType:36
|vpiNet:
\_logic_net: (quadrant), line:31
|vpiName:quadrant
|vpiFullName:work@msb.quadrant
|vpiNetType:36
|uhdmallModules:
\_module: work@msb_naive, file:third_party/cores/taiga/core/msb_naive.sv, line:25, parent:work@div_unit_core_wrapper
|vpiDefName:work@msb_naive
|vpiFullName:work@msb_naive
|vpiProcess:
\_always: , line:31
|vpiAlwaysType:2
|vpiStmt:
\_begin: , line:31
|vpiFullName:work@msb_naive
|vpiStmt:
\_assignment: , line:32
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (msb), line:32
|vpiName:msb
|vpiFullName:work@msb_naive.msb
|vpiRhs:
\_constant: , line:32
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiStmt:
\_for_stmt: , line:33
|vpiFullName:work@msb_naive
|vpiCondition:
\_operation: , line:33
|vpiOpType:20
|vpiOperand:
\_ref_obj: (i), line:33
|vpiName:i
|vpiFullName:work@msb_naive.i
|vpiOperand:
\_constant: , line:33
|vpiConstType:7
|vpiDecompile:32
|vpiSize:32
|INT:32
|vpiForInitStmt:
\_assign_stmt:
|vpiRhs:
\_constant: , line:33
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiLhs:
\_int_var: (i), line:33
|vpiName:i
|vpiFullName:work@msb_naive.i
|vpiForIncStmt:
\_operation: , line:33
|vpiOpType:62
|vpiOperand:
\_ref_obj: (i), line:33
|vpiName:i
|vpiStmt:
\_begin: , line:33
|vpiFullName:work@msb_naive
|vpiStmt:
\_assignment: , line:34
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (msb), line:34
|vpiName:msb
|vpiFullName:work@msb_naive.msb
|vpiRhs:
\_operation: , line:34
|vpiOpType:32
|vpiOperand:
\_bit_select: (msb_input), line:34
|vpiName:msb_input
|vpiFullName:work@msb_naive.msb_input
|vpiIndex:
\_ref_obj: (i), line:34
|vpiName:i
|vpiOperand:
\_part_select: , line:34, parent:i
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (i)
|vpiLeftRange:
\_constant: , line:34
|vpiConstType:7
|vpiDecompile:4
|vpiSize:32
|INT:4
|vpiRightRange:
\_constant: , line:34
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiOperand:
\_ref_obj: (msb), line:34
|vpiName:msb
|vpiFullName:work@msb_naive.msb
|vpiPort:
\_port: (msb_input), line:27
|vpiName:msb_input
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (msb_input), line:27
|vpiName:msb_input
|vpiFullName:work@msb_naive.msb_input
|vpiNetType:36
|vpiPort:
\_port: (msb), line:28
|vpiName:msb
|vpiDirection:2
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (msb), line:28
|vpiName:msb
|vpiFullName:work@msb_naive.msb
|vpiNetType:36
|vpiNet:
\_logic_net: (msb_input), line:27
|vpiNet:
\_logic_net: (msb), line:28
|uhdmallModules:
\_module: work@mstatus_priv_reg, file:third_party/cores/taiga/core/mstatus_priv_reg.sv, line:27, parent:work@div_unit_core_wrapper
|vpiDefName:work@mstatus_priv_reg
|vpiFullName:work@mstatus_priv_reg
|vpiProcess:
\_always: , line:56
|vpiAlwaysType:2
|vpiStmt:
\_begin: , line:56
|vpiFullName:work@mstatus_priv_reg
|vpiStmt:
\_if_else: , line:57
|vpiCondition:
\_unsupported_expr: , line:57
|STRING: unique if(mret | sret)
|vpiStmt:
\_if_else: , line:57
|vpiCondition:
\_operation: , line:57
|vpiOpType:29
|vpiOperand:
\_ref_obj: (mret), line:57
|vpiName:mret
|vpiFullName:work@mstatus_priv_reg.mret
|vpiOperand:
\_ref_obj: (sret), line:57
|vpiName:sret
|vpiFullName:work@mstatus_priv_reg.sret
|vpiStmt:
\_assignment: , line:58
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (next_privilege_level), line:58
|vpiName:next_privilege_level
|vpiFullName:work@mstatus_priv_reg.next_privilege_level
|vpiRhs:
\_ref_obj: (trap_return_privilege_level), line:58
|vpiName:trap_return_privilege_level
|vpiFullName:work@mstatus_priv_reg.trap_return_privilege_level
|vpiElseStmt:
\_if_else: , line:59
|vpiCondition:
\_ref_obj: (interrupt), line:59
|vpiName:interrupt
|vpiFullName:work@mstatus_priv_reg.interrupt
|vpiStmt:
\_assignment: , line:60
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (next_privilege_level), line:60
|vpiName:next_privilege_level
|vpiFullName:work@mstatus_priv_reg.next_privilege_level
|vpiRhs:
\_ref_obj: (interrupt_privilege_level), line:60
|vpiName:interrupt_privilege_level
|vpiFullName:work@mstatus_priv_reg.interrupt_privilege_level
|vpiElseStmt:
\_if_else: , line:61
|vpiCondition:
\_ref_obj: (exception), line:61
|vpiName:exception
|vpiFullName:work@mstatus_priv_reg.exception
|vpiStmt:
\_assignment: , line:62
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (next_privilege_level), line:62
|vpiName:next_privilege_level
|vpiFullName:work@mstatus_priv_reg.next_privilege_level
|vpiRhs:
\_ref_obj: (exception_privilege_level), line:62
|vpiName:exception_privilege_level
|vpiFullName:work@mstatus_priv_reg.exception_privilege_level
|vpiElseStmt:
\_assignment: , line:64
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (next_privilege_level), line:64
|vpiName:next_privilege_level
|vpiFullName:work@mstatus_priv_reg.next_privilege_level
|vpiRhs:
\_ref_obj: (privilege_level), line:64
|vpiName:privilege_level
|vpiFullName:work@mstatus_priv_reg.privilege_level
|vpiElseStmt:
\_assignment: , line:58
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (next_privilege_level), line:58
|vpiName:next_privilege_level
|vpiFullName:work@mstatus_priv_reg.next_privilege_level
|vpiRhs:
\_ref_obj: (trap_return_privilege_level), line:58
|vpiName:trap_return_privilege_level
|vpiFullName:work@mstatus_priv_reg.trap_return_privilege_level
|vpiProcess:
\_always: , line:68
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:68
|vpiCondition:
\_operation: , line:68
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:68
|vpiName:clk
|vpiFullName:work@mstatus_priv_reg.clk
|vpiStmt:
\_begin: , line:68
|vpiFullName:work@mstatus_priv_reg
|vpiStmt:
\_if_else: , line:69
|vpiCondition:
\_ref_obj: (rst), line:69
|vpiName:rst
|vpiFullName:work@mstatus_priv_reg.rst
|vpiStmt:
\_assignment: , line:70
|vpiOpType:82
|vpiLhs:
\_ref_obj: (privilege_level), line:70
|vpiName:privilege_level
|vpiFullName:work@mstatus_priv_reg.privilege_level
|vpiRhs:
\_ref_obj: (MACHINE_PRIV), line:70
|vpiName:MACHINE_PRIV
|vpiFullName:work@mstatus_priv_reg.MACHINE_PRIV
|vpiElseStmt:
\_assignment: , line:72
|vpiOpType:82
|vpiLhs:
\_ref_obj: (privilege_level), line:72
|vpiName:privilege_level
|vpiFullName:work@mstatus_priv_reg.privilege_level
|vpiRhs:
\_ref_obj: (next_privilege_level), line:72
|vpiName:next_privilege_level
|vpiFullName:work@mstatus_priv_reg.next_privilege_level
|vpiProcess:
\_always: , line:75
|vpiAlwaysType:2
|vpiStmt:
\_begin: , line:75
|vpiFullName:work@mstatus_priv_reg
|vpiStmt:
\_assignment: , line:76
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (mstatus_exception), line:76
|vpiName:mstatus_exception
|vpiFullName:work@mstatus_priv_reg.mstatus_exception
|vpiRhs:
\_ref_obj: (mstatus), line:76
|vpiName:mstatus
|vpiFullName:work@mstatus_priv_reg.mstatus
|vpiStmt:
\_case_stmt: , line:77
|vpiCaseType:1
|vpiQualifier:1
|vpiCondition:
\_ref_obj: (next_privilege_level), line:77
|vpiName:next_privilege_level
|vpiFullName:work@mstatus_priv_reg.next_privilege_level
|vpiCaseItem:
\_case_item: , line:78
|vpiExpr:
\_ref_obj: (SUPERVISOR_PRIV), line:78
|vpiName:SUPERVISOR_PRIV
|vpiFullName:work@mstatus_priv_reg.SUPERVISOR_PRIV
|vpiStmt:
\_begin: , line:78
|vpiFullName:work@mstatus_priv_reg
|vpiStmt:
\_assignment: , line:79
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (mstatus_exception.spie), line:79
|vpiName:mstatus_exception.spie
|vpiFullName:work@mstatus_priv_reg.mstatus_exception.spie
|vpiRhs:
\_operation: , line:79
|vpiOpType:32
|vpiOperand:
\_operation: , line:79
|vpiOpType:14
|vpiOperand:
\_ref_obj: (privilege_level), line:79
|vpiName:privilege_level
|vpiFullName:work@mstatus_priv_reg.privilege_level
|vpiOperand:
\_ref_obj: (SUPERVISOR_PRIV), line:79
|vpiName:SUPERVISOR_PRIV
|vpiFullName:work@mstatus_priv_reg.SUPERVISOR_PRIV
|vpiOperand:
\_ref_obj: (mstatus.sie), line:79
|vpiName:mstatus.sie
|vpiFullName:work@mstatus_priv_reg.mstatus.sie
|vpiOperand:
\_ref_obj: (mstatus.uie), line:79
|vpiName:mstatus.uie
|vpiFullName:work@mstatus_priv_reg.mstatus.uie
|vpiStmt:
\_assignment: , line:80
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (mstatus_exception.sie), line:80
|vpiName:mstatus_exception.sie
|vpiFullName:work@mstatus_priv_reg.mstatus_exception.sie
|vpiRhs:
\_constant: , line:80
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiStmt:
\_assignment: , line:81
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (mstatus_exception.spp), line:81
|vpiName:mstatus_exception.spp
|vpiFullName:work@mstatus_priv_reg.mstatus_exception.spp
|vpiRhs:
\_bit_select: (privilege_level), line:81
|vpiName:privilege_level
|vpiFullName:work@mstatus_priv_reg.privilege_level
|vpiIndex:
\_constant: , line:81
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiCaseItem:
\_case_item: , line:83
|vpiStmt:
\_begin: , line:83
|vpiFullName:work@mstatus_priv_reg
|vpiStmt:
\_assignment: , line:84
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (mstatus_exception.mpie), line:84
|vpiName:mstatus_exception.mpie
|vpiFullName:work@mstatus_priv_reg.mstatus_exception.mpie
|vpiRhs:
\_operation: , line:84
|vpiOpType:32
|vpiOperand:
\_operation: , line:84
|vpiOpType:14
|vpiOperand:
\_ref_obj: (privilege_level), line:84
|vpiName:privilege_level
|vpiFullName:work@mstatus_priv_reg.privilege_level
|vpiOperand:
\_ref_obj: (MACHINE_PRIV), line:84
|vpiName:MACHINE_PRIV
|vpiFullName:work@mstatus_priv_reg.MACHINE_PRIV
|vpiOperand:
\_ref_obj: (mstatus.mie), line:84
|vpiName:mstatus.mie
|vpiFullName:work@mstatus_priv_reg.mstatus.mie
|vpiOperand:
\_operation: , line:84
|vpiOpType:32
|vpiOperand:
\_operation: , line:84
|vpiOpType:14
|vpiOperand:
\_ref_obj: (privilege_level), line:84
|vpiName:privilege_level
|vpiFullName:work@mstatus_priv_reg.privilege_level
|vpiOperand:
\_ref_obj: (SUPERVISOR_PRIV), line:84
|vpiName:SUPERVISOR_PRIV
|vpiFullName:work@mstatus_priv_reg.SUPERVISOR_PRIV
|vpiOperand:
\_ref_obj: (mstatus.sie), line:84
|vpiName:mstatus.sie
|vpiFullName:work@mstatus_priv_reg.mstatus.sie
|vpiOperand:
\_ref_obj: (mstatus.uie), line:84
|vpiName:mstatus.uie
|vpiFullName:work@mstatus_priv_reg.mstatus.uie
|vpiStmt:
\_assignment: , line:85
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (mstatus_exception.mie), line:85
|vpiName:mstatus_exception.mie
|vpiFullName:work@mstatus_priv_reg.mstatus_exception.mie
|vpiRhs:
\_constant: , line:85
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiStmt:
\_assignment: , line:86
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (mstatus_exception.mpp), line:86
|vpiName:mstatus_exception.mpp
|vpiFullName:work@mstatus_priv_reg.mstatus_exception.mpp
|vpiRhs:
\_ref_obj: (privilege_level), line:86
|vpiName:privilege_level
|vpiFullName:work@mstatus_priv_reg.privilege_level
|vpiProcess:
\_always: , line:92
|vpiAlwaysType:2
|vpiStmt:
\_begin: , line:92
|vpiFullName:work@mstatus_priv_reg
|vpiStmt:
\_assignment: , line:93
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (mstatus_return), line:93
|vpiName:mstatus_return
|vpiFullName:work@mstatus_priv_reg.mstatus_return
|vpiRhs:
\_ref_obj: (mstatus), line:93
|vpiName:mstatus
|vpiFullName:work@mstatus_priv_reg.mstatus
|vpiStmt:
\_if_else: , line:94
|vpiCondition:
\_unsupported_expr: , line:94
|STRING: unique if (sret) begin
|vpiStmt:
\_if_else: , line:94
|vpiCondition:
\_ref_obj: (sret), line:94
|vpiName:sret
|vpiFullName:work@mstatus_priv_reg.sret
|vpiStmt:
\_begin: , line:94
|vpiFullName:work@mstatus_priv_reg
|vpiStmt:
\_assignment: , line:95
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (mstatus_return.sie), line:95
|vpiName:mstatus_return.sie
|vpiFullName:work@mstatus_priv_reg.mstatus_return.sie
|vpiRhs:
\_ref_obj: (mstatus_return.spie), line:95
|vpiName:mstatus_return.spie
|vpiFullName:work@mstatus_priv_reg.mstatus_return.spie
|vpiStmt:
\_assignment: , line:96
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (mstatus_return.spie), line:96
|vpiName:mstatus_return.spie
|vpiFullName:work@mstatus_priv_reg.mstatus_return.spie
|vpiRhs:
\_constant: , line:96
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiStmt:
\_assignment: , line:97
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (mstatus_return.spp), line:97
|vpiName:mstatus_return.spp
|vpiFullName:work@mstatus_priv_reg.mstatus_return.spp
|vpiRhs:
\_constant: , line:97
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiElseStmt:
\_if_stmt: , line:98
|vpiCondition:
\_ref_obj: (mret), line:98
|vpiName:mret
|vpiFullName:work@mstatus_priv_reg.mret
|vpiStmt:
\_begin: , line:98
|vpiFullName:work@mstatus_priv_reg
|vpiStmt:
\_assignment: , line:99
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (mstatus_return.mie), line:99
|vpiName:mstatus_return.mie
|vpiFullName:work@mstatus_priv_reg.mstatus_return.mie
|vpiRhs:
\_ref_obj: (mstatus.mpie), line:99
|vpiName:mstatus.mpie
|vpiFullName:work@mstatus_priv_reg.mstatus.mpie
|vpiStmt:
\_assignment: , line:100
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (mstatus_return.mpie), line:100
|vpiName:mstatus_return.mpie
|vpiFullName:work@mstatus_priv_reg.mstatus_return.mpie
|vpiRhs:
\_constant: , line:100
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiStmt:
\_assignment: , line:101
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (mstatus_return.mpp), line:101
|vpiName:mstatus_return.mpp
|vpiFullName:work@mstatus_priv_reg.mstatus_return.mpp
|vpiRhs:
\_ref_obj: (USER_PRIV), line:101
|vpiName:USER_PRIV
|vpiFullName:work@mstatus_priv_reg.USER_PRIV
|vpiElseStmt:
\_begin: , line:94
|vpiFullName:work@mstatus_priv_reg
|vpiStmt:
\_assignment: , line:95
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (mstatus_return.sie), line:95
|vpiName:mstatus_return.sie
|vpiFullName:work@mstatus_priv_reg.mstatus_return.sie
|vpiRhs:
\_ref_obj: (mstatus_return.spie), line:95
|vpiName:mstatus_return.spie
|vpiFullName:work@mstatus_priv_reg.mstatus_return.spie
|vpiStmt:
\_assignment: , line:96
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (mstatus_return.spie), line:96
|vpiName:mstatus_return.spie
|vpiFullName:work@mstatus_priv_reg.mstatus_return.spie
|vpiRhs:
\_constant: , line:96
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiStmt:
\_assignment: , line:97
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (mstatus_return.spp), line:97
|vpiName:mstatus_return.spp
|vpiFullName:work@mstatus_priv_reg.mstatus_return.spp
|vpiRhs:
\_constant: , line:97
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiProcess:
\_always: , line:111
|vpiAlwaysType:2
|vpiStmt:
\_begin: , line:111
|vpiFullName:work@mstatus_priv_reg
|vpiStmt:
\_if_else: , line:112
|vpiCondition:
\_unsupported_expr: , line:112
|STRING: unique if (write_msr_m | write_msr_s)
|vpiStmt:
\_if_else: , line:112
|vpiCondition:
\_operation: , line:112
|vpiOpType:29
|vpiOperand:
\_ref_obj: (write_msr_m), line:112
|vpiName:write_msr_m
|vpiFullName:work@mstatus_priv_reg.write_msr_m
|vpiOperand:
\_ref_obj: (write_msr_s), line:112
|vpiName:write_msr_s
|vpiFullName:work@mstatus_priv_reg.write_msr_s
|vpiStmt:
\_assignment: , line:113
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (mstatus_new), line:113
|vpiName:mstatus_new
|vpiFullName:work@mstatus_priv_reg.mstatus_new
|vpiRhs:
\_operation: , line:113
|vpiOpType:28
|vpiOperand:
\_ref_obj: (updated_csr), line:113
|vpiName:updated_csr
|vpiFullName:work@mstatus_priv_reg.updated_csr
|vpiOperand:
\_ref_obj: (mstatus_mask), line:113
|vpiName:mstatus_mask
|vpiFullName:work@mstatus_priv_reg.mstatus_mask
|vpiElseStmt:
\_if_else: , line:114
|vpiCondition:
\_operation: , line:114
|vpiOpType:29
|vpiOperand:
\_ref_obj: (interrupt), line:114
|vpiName:interrupt
|vpiFullName:work@mstatus_priv_reg.interrupt
|vpiOperand:
\_ref_obj: (exception), line:114
|vpiName:exception
|vpiFullName:work@mstatus_priv_reg.exception
|vpiStmt:
\_assignment: , line:115
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (mstatus_new), line:115
|vpiName:mstatus_new
|vpiFullName:work@mstatus_priv_reg.mstatus_new
|vpiRhs:
\_ref_obj: (mstatus_exception), line:115
|vpiName:mstatus_exception
|vpiFullName:work@mstatus_priv_reg.mstatus_exception
|vpiElseStmt:
\_if_else: , line:116
|vpiCondition:
\_operation: , line:116
|vpiOpType:29
|vpiOperand:
\_ref_obj: (mret), line:116
|vpiName:mret
|vpiFullName:work@mstatus_priv_reg.mret
|vpiOperand:
\_ref_obj: (sret), line:116
|vpiName:sret
|vpiFullName:work@mstatus_priv_reg.sret
|vpiStmt:
\_assignment: , line:117
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (mstatus_new), line:117
|vpiName:mstatus_new
|vpiFullName:work@mstatus_priv_reg.mstatus_new
|vpiRhs:
\_ref_obj: (mstatus_return), line:117
|vpiName:mstatus_return
|vpiFullName:work@mstatus_priv_reg.mstatus_return
|vpiElseStmt:
\_assignment: , line:119
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (mstatus_new), line:119
|vpiName:mstatus_new
|vpiFullName:work@mstatus_priv_reg.mstatus_new
|vpiRhs:
\_ref_obj: (mstatus), line:119
|vpiName:mstatus
|vpiFullName:work@mstatus_priv_reg.mstatus
|vpiElseStmt:
\_assignment: , line:113
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (mstatus_new), line:113
|vpiName:mstatus_new
|vpiFullName:work@mstatus_priv_reg.mstatus_new
|vpiRhs:
\_operation: , line:113
|vpiOpType:28
|vpiOperand:
\_ref_obj: (updated_csr), line:113
|vpiName:updated_csr
|vpiFullName:work@mstatus_priv_reg.updated_csr
|vpiOperand:
\_ref_obj: (mstatus_mask), line:113
|vpiName:mstatus_mask
|vpiFullName:work@mstatus_priv_reg.mstatus_mask
|vpiProcess:
\_always: , line:123
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:123
|vpiCondition:
\_operation: , line:123
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:123
|vpiName:clk
|vpiFullName:work@mstatus_priv_reg.clk
|vpiStmt:
\_begin: , line:123
|vpiFullName:work@mstatus_priv_reg
|vpiStmt:
\_if_else: , line:124
|vpiCondition:
\_ref_obj: (rst), line:124
|vpiName:rst
|vpiFullName:work@mstatus_priv_reg.rst
|vpiStmt:
\_assignment: , line:125
|vpiOpType:82
|vpiLhs:
\_ref_obj: (mstatus), line:125
|vpiName:mstatus
|vpiFullName:work@mstatus_priv_reg.mstatus
|vpiRhs:
\_ref_obj: (mstatus_rst), line:125
|vpiName:mstatus_rst
|vpiFullName:work@mstatus_priv_reg.mstatus_rst
|vpiElseStmt:
\_assignment: , line:127
|vpiOpType:82
|vpiLhs:
\_ref_obj: (mstatus), line:127
|vpiName:mstatus
|vpiFullName:work@mstatus_priv_reg.mstatus
|vpiRhs:
\_ref_obj: (mstatus_new), line:127
|vpiName:mstatus_new
|vpiFullName:work@mstatus_priv_reg.mstatus_new
|vpiPort:
\_port: (clk), line:28
|vpiName:clk
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (clk), line:28
|vpiName:clk
|vpiFullName:work@mstatus_priv_reg.clk
|vpiNetType:36
|vpiPort:
\_port: (rst), line:29
|vpiName:rst
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (rst), line:29
|vpiName:rst
|vpiFullName:work@mstatus_priv_reg.rst
|vpiNetType:36
|vpiPort:
\_port: (exception), line:31
|vpiName:exception
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (exception), line:31
|vpiName:exception
|vpiFullName:work@mstatus_priv_reg.exception
|vpiNetType:36
|vpiPort:
\_port: (interrupt), line:32
|vpiName:interrupt
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (interrupt), line:32
|vpiName:interrupt
|vpiFullName:work@mstatus_priv_reg.interrupt
|vpiNetType:36
|vpiPort:
\_port: (mret), line:33
|vpiName:mret
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (mret), line:33
|vpiName:mret
|vpiFullName:work@mstatus_priv_reg.mret
|vpiNetType:36
|vpiPort:
\_port: (sret), line:34
|vpiName:sret
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (sret), line:34
|vpiName:sret
|vpiFullName:work@mstatus_priv_reg.sret
|vpiNetType:36
|vpiPort:
\_port: (write_msr_m), line:35
|vpiName:write_msr_m
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (write_msr_m), line:35
|vpiName:write_msr_m
|vpiFullName:work@mstatus_priv_reg.write_msr_m
|vpiNetType:36
|vpiPort:
\_port: (write_msr_s), line:36
|vpiName:write_msr_s
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (write_msr_s), line:36
|vpiName:write_msr_s
|vpiFullName:work@mstatus_priv_reg.write_msr_s
|vpiNetType:36
|vpiPort:
\_port: (updated_csr), line:37
|vpiName:updated_csr
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (updated_csr), line:37
|vpiName:updated_csr
|vpiFullName:work@mstatus_priv_reg.updated_csr
|vpiNetType:36
|vpiPort:
\_port: (interrupt_delegated), line:38
|vpiName:interrupt_delegated
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (interrupt_delegated), line:38
|vpiName:interrupt_delegated
|vpiFullName:work@mstatus_priv_reg.interrupt_delegated
|vpiNetType:36
|vpiPort:
\_port: (exception_delegated), line:39
|vpiName:exception_delegated
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (exception_delegated), line:39
|vpiName:exception_delegated
|vpiFullName:work@mstatus_priv_reg.exception_delegated
|vpiNetType:36
|vpiPort:
\_port: (privilege_level), line:40
|vpiName:privilege_level
|vpiDirection:2
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (privilege_level), line:40
|vpiName:privilege_level
|vpiFullName:work@mstatus_priv_reg.privilege_level
|vpiNetType:36
|vpiPort:
\_port: (next_privilege_level), line:41
|vpiName:next_privilege_level
|vpiDirection:2
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (next_privilege_level), line:41
|vpiName:next_privilege_level
|vpiFullName:work@mstatus_priv_reg.next_privilege_level
|vpiNetType:36
|vpiPort:
\_port: (mstatus), line:43
|vpiName:mstatus
|vpiDirection:2
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (mstatus), line:43
|vpiName:mstatus
|vpiFullName:work@mstatus_priv_reg.mstatus
|vpiPort:
\_port: (mstatus_smask), line:44
|vpiName:mstatus_smask
|vpiDirection:2
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (mstatus_smask), line:44
|vpiName:mstatus_smask
|vpiFullName:work@mstatus_priv_reg.mstatus_smask
|vpiContAssign:
\_cont_assign: , line:52
|vpiRhs:
\_operation: , line:52
|vpiOpType:32
|vpiOperand:
\_ref_obj: (mret), line:52
|vpiName:mret
|vpiFullName:work@mstatus_priv_reg.mret
|vpiOperand:
\_ref_obj: (mstatus.mpp), line:52
|vpiName:mstatus.mpp
|vpiFullName:work@mstatus_priv_reg.mstatus.mpp
|vpiOperand:
\_operation: , line:52
|vpiOpType:33
|vpiOperand:
\_constant: , line:52
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiOperand:
\_ref_obj: (mstatus.spp), line:52
|vpiName:mstatus.spp
|vpiFullName:work@mstatus_priv_reg.mstatus.spp
|vpiLhs:
\_ref_obj: (trap_return_privilege_level), line:52
|vpiName:trap_return_privilege_level
|vpiFullName:work@mstatus_priv_reg.trap_return_privilege_level
|vpiContAssign:
\_cont_assign: , line:53
|vpiRhs:
\_operation: , line:53
|vpiOpType:32
|vpiOperand:
\_ref_obj: (exception_delegated), line:53
|vpiName:exception_delegated
|vpiFullName:work@mstatus_priv_reg.exception_delegated
|vpiOperand:
\_ref_obj: (SUPERVISOR_PRIV), line:53
|vpiName:SUPERVISOR_PRIV
|vpiFullName:work@mstatus_priv_reg.SUPERVISOR_PRIV
|vpiOperand:
\_ref_obj: (MACHINE_PRIV), line:53
|vpiName:MACHINE_PRIV
|vpiFullName:work@mstatus_priv_reg.MACHINE_PRIV
|vpiLhs:
\_ref_obj: (exception_privilege_level), line:53
|vpiName:exception_privilege_level
|vpiFullName:work@mstatus_priv_reg.exception_privilege_level
|vpiContAssign:
\_cont_assign: , line:54
|vpiRhs:
\_operation: , line:54
|vpiOpType:32
|vpiOperand:
\_ref_obj: (interrupt_delegated), line:54
|vpiName:interrupt_delegated
|vpiFullName:work@mstatus_priv_reg.interrupt_delegated
|vpiOperand:
\_ref_obj: (SUPERVISOR_PRIV), line:54
|vpiName:SUPERVISOR_PRIV
|vpiFullName:work@mstatus_priv_reg.SUPERVISOR_PRIV
|vpiOperand:
\_ref_obj: (MACHINE_PRIV), line:54
|vpiName:MACHINE_PRIV
|vpiFullName:work@mstatus_priv_reg.MACHINE_PRIV
|vpiLhs:
\_ref_obj: (interrupt_privilege_level), line:54
|vpiName:interrupt_privilege_level
|vpiFullName:work@mstatus_priv_reg.interrupt_privilege_level
|vpiContAssign:
\_cont_assign: , line:106
|vpiRhs:
\_operation: , line:106
|vpiOpType:75
|vpiOperand:
\_constant: , line:106
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiOperand:
\_constant: , line:106
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiOperand:
\_constant: , line:106
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiOperand:
\_constant: , line:106
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiOperand:
\_constant: , line:106
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiOperand:
\_constant: , line:106
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiOperand:
\_constant: , line:106
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiOperand:
\_constant: , line:106
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiOperand:
\_constant: , line:106
|vpiConstType:3
|vpiDecompile:'b1
|vpiSize:1
|BIN:1
|vpiOperand:
\_constant: , line:106
|vpiConstType:3
|vpiDecompile:'b1
|vpiSize:1
|BIN:1
|vpiOperand:
\_constant: , line:106
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiOperand:
\_constant: , line:106
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiOperand:
\_constant: , line:106
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiOperand:
\_constant: , line:106
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiOperand:
\_constant: , line:106
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiOperand:
\_constant: , line:106
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiOperand:
\_constant: , line:106
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiOperand:
\_constant: , line:106
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiOperand:
\_constant: , line:106
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiOperand:
\_constant: , line:106
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiLhs:
\_ref_obj: (mstatus_mmask), line:106
|vpiName:mstatus_mmask
|vpiFullName:work@mstatus_priv_reg.mstatus_mmask
|vpiContAssign:
\_cont_assign: , line:107
|vpiRhs:
\_operation: , line:107
|vpiOpType:75
|vpiOperand:
\_constant: , line:107
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiOperand:
\_constant: , line:107
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiOperand:
\_constant: , line:107
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiOperand:
\_constant: , line:107
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiOperand:
\_constant: , line:107
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiOperand:
\_constant: , line:107
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiOperand:
\_constant: , line:107
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiOperand:
\_constant: , line:107
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiOperand:
\_constant: , line:107
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiOperand:
\_constant: , line:107
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiOperand:
\_constant: , line:107
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiOperand:
\_constant: , line:107
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiLhs:
\_ref_obj: (mstatus_smask), line:107
|vpiName:mstatus_smask
|vpiFullName:work@mstatus_priv_reg.mstatus_smask
|vpiContAssign:
\_cont_assign: , line:108
|vpiRhs:
\_operation: , line:108
|vpiOpType:32
|vpiOperand:
\_ref_obj: (write_msr_m), line:108
|vpiName:write_msr_m
|vpiFullName:work@mstatus_priv_reg.write_msr_m
|vpiOperand:
\_ref_obj: (mstatus_mmask), line:108
|vpiName:mstatus_mmask
|vpiFullName:work@mstatus_priv_reg.mstatus_mmask
|vpiOperand:
\_ref_obj: (mstatus_smask), line:108
|vpiName:mstatus_smask
|vpiFullName:work@mstatus_priv_reg.mstatus_smask
|vpiLhs:
\_ref_obj: (mstatus_mask), line:108
|vpiName:mstatus_mask
|vpiFullName:work@mstatus_priv_reg.mstatus_mask
|vpiContAssign:
\_cont_assign: , line:122
|vpiRhs:
\_operation: , line:122
|vpiOpType:75
|vpiOperand:
\_constant: , line:122
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiOperand:
\_constant: , line:122
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiOperand:
\_ref_obj: (MACHINE_PRIV), line:122
|vpiName:MACHINE_PRIV
|vpiFullName:work@mstatus_priv_reg.MACHINE_PRIV
|vpiOperand:
\_ref_obj: (MACHINE_PRIV), line:122
|vpiName:MACHINE_PRIV
|vpiFullName:work@mstatus_priv_reg.MACHINE_PRIV
|vpiLhs:
\_ref_obj: (mstatus_rst), line:122
|vpiName:mstatus_rst
|vpiFullName:work@mstatus_priv_reg.mstatus_rst
|vpiNet:
\_logic_net: (clk), line:28
|vpiNet:
\_logic_net: (rst), line:29
|vpiNet:
\_logic_net: (exception), line:31
|vpiNet:
\_logic_net: (interrupt), line:32
|vpiNet:
\_logic_net: (mret), line:33
|vpiNet:
\_logic_net: (sret), line:34
|vpiNet:
\_logic_net: (write_msr_m), line:35
|vpiNet:
\_logic_net: (write_msr_s), line:36
|vpiNet:
\_logic_net: (updated_csr), line:37
|vpiNet:
\_logic_net: (interrupt_delegated), line:38
|vpiNet:
\_logic_net: (exception_delegated), line:39
|vpiNet:
\_logic_net: (privilege_level), line:40
|vpiNet:
\_logic_net: (next_privilege_level), line:41
|vpiNet:
\_logic_net: (mstatus), line:43
|vpiNet:
\_logic_net: (mstatus_smask), line:44
|vpiNet:
\_logic_net: (trap_return_privilege_level), line:47
|vpiName:trap_return_privilege_level
|vpiFullName:work@mstatus_priv_reg.trap_return_privilege_level
|vpiNetType:36
|vpiNet:
\_logic_net: (exception_privilege_level), line:47
|vpiName:exception_privilege_level
|vpiFullName:work@mstatus_priv_reg.exception_privilege_level
|vpiNetType:36
|vpiNet:
\_logic_net: (interrupt_privilege_level), line:47
|vpiName:interrupt_privilege_level
|vpiFullName:work@mstatus_priv_reg.interrupt_privilege_level
|vpiNetType:36
|vpiNet:
\_logic_net: (mstatus_exception), line:48
|vpiName:mstatus_exception
|vpiFullName:work@mstatus_priv_reg.mstatus_exception
|vpiNet:
\_logic_net: (mstatus_return), line:48
|vpiName:mstatus_return
|vpiFullName:work@mstatus_priv_reg.mstatus_return
|vpiNet:
\_logic_net: (mstatus_rst), line:48
|vpiName:mstatus_rst
|vpiFullName:work@mstatus_priv_reg.mstatus_rst
|vpiNet:
\_logic_net: (mstatus_new), line:48
|vpiName:mstatus_new
|vpiFullName:work@mstatus_priv_reg.mstatus_new
|vpiNet:
\_logic_net: (mstatus_mmask), line:49
|vpiName:mstatus_mmask
|vpiFullName:work@mstatus_priv_reg.mstatus_mmask
|vpiNet:
\_logic_net: (mstatus_mask), line:49
|vpiName:mstatus_mask
|vpiFullName:work@mstatus_priv_reg.mstatus_mask
|vpiTypedef:
\_struct_typespec: (alu_inputs_t), line:301
|vpiTypedef:
\_enum_typespec: (alu_logic_op_t), line:84
|vpiTypedef:
\_enum_typespec: (alu_op_t), line:91
|vpiTypedef:
\_enum_typespec: (alu_rs1_op_t), line:97
|vpiTypedef:
\_enum_typespec: (alu_rs2_op_t), line:104
|vpiTypedef:
\_struct_typespec: (amo_alu_inputs_t), line:356
|vpiTypedef:
\_struct_typespec: (amo_details_t), line:362
|vpiTypedef:
\_enum_typespec: (amo_t), line:354
|vpiTypedef:
\_struct_typespec: (branch_inputs_t), line:313
|vpiTypedef:
\_logic_typespec: (branch_predictor_metadata_t), line:32
|vpiTypedef:
\_struct_typespec: (branch_results_t), line:330
|vpiTypedef:
\_enum_typespec: (bus_type_t), line:86
|vpiTypedef:
\_struct_typespec: (csr_addr_t), line:37
|vpiTypedef:
\_struct_typespec: (csr_inputs_t), line:396
|vpiTypedef:
\_enum_typespec: (csr_op_t), line:218
|vpiTypedef:
\_enum_typespec: (csr_t), line:201
|vpiTypedef:
\_struct_typespec: (data_access_shared_inputs_t), line:427
|vpiTypedef:
\_struct_typespec: (div_inputs_t), line:389
|vpiTypedef:
\_enum_typespec: (div_type), line:66
|vpiTypedef:
\_enum_typespec: (exception_code_t), line:245
|vpiTypedef:
\_struct_typespec: (exception_packet_t), line:263
|vpiTypedef:
\_struct_typespec: (fetch_buffer_packet_t), line:276
|vpiTypedef:
\_enum_typespec: (fifo_type_t), line:440
|vpiTypedef:
\_enum_typespec: (fn3_arith_t), line:76
|vpiTypedef:
\_enum_typespec: (fn3_branch_t), line:126
|vpiTypedef:
\_enum_typespec: (fn3_csr_t), line:212
|vpiTypedef:
\_enum_typespec: (fn3_ls_t), line:115
|vpiTypedef:
\_enum_typespec: (fn3_mul_div_t), line:138
|vpiTypedef:
\_struct_typespec: (gc_inputs_t), line:404
|vpiTypedef:
\_struct_typespec: (inflight_instruction_packet), line:271
|vpiTypedef:
\_logic_typespec: (instruction_id_t), line:30
|vpiTypedef:
\_enum_typespec: (interrupt_code_t), line:261
|vpiTypedef:
\_struct_typespec: (load_store_inputs_t), line:369
|vpiTypedef:
\_struct_typespec: (mcause_t), line:135
|vpiTypedef:
\_struct_typespec: (mie_t), line:119
|vpiTypedef:
\_struct_typespec: (mip_t), line:103
|vpiTypedef:
\_struct_typespec: (misa_t), line:45
|vpiTypedef:
\_struct_typespec: (mstatus_t), line:78
|vpiTypedef:
\_struct_typespec: (mul_inputs_t), line:383
|vpiTypedef:
\_enum_typespec: (opcodes_t), line:48
|vpiTypedef:
\_enum_typespec: (opcodes_trimmed_t), line:65
|vpiTypedef:
\_enum_typespec: (privilege_t), line:34
|vpiTypedef:
\_struct_typespec: (satp_t), line:142
|vpiTypedef:
\_struct_typespec: (simulation_named_regfile), line:476
|vpiTypedef:
\_struct_typespec: (taiga_trace_events_t), line:442
|vpiTypedef:
\_struct_typespec: (to_l1_arbiter_packet), line:418
|vpiTypedef:
\_struct_typespec: (trace_outputs_t), line:469
|vpiTypedef:
\_logic_typespec: (unit_id_t), line:31
|vpiTypedef:
\_struct_typespec: (unit_writeback_t), line:295
|vpiTypedef:
\_enum_typespec: (vm_t), line:223
|uhdmallModules:
\_module: work@mul_unit, file:third_party/cores/taiga/core/mul_unit.sv, line:26, parent:work@div_unit_core_wrapper
|vpiDefName:work@mul_unit
|vpiFullName:work@mul_unit
|vpiProcess:
\_always: , line:53
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:53
|vpiCondition:
\_operation: , line:53
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:53
|vpiName:clk
|vpiFullName:work@mul_unit.clk
|vpiStmt:
\_begin: , line:53
|vpiFullName:work@mul_unit
|vpiStmt:
\_assignment: , line:54
|vpiOpType:82
|vpiLhs:
\_ref_obj: (rs1_r), line:54
|vpiName:rs1_r
|vpiFullName:work@mul_unit.rs1_r
|vpiRhs:
\_ref_obj: (rs1_ext), line:54
|vpiName:rs1_ext
|vpiFullName:work@mul_unit.rs1_ext
|vpiStmt:
\_assignment: , line:55
|vpiOpType:82
|vpiLhs:
\_ref_obj: (rs2_r), line:55
|vpiName:rs2_r
|vpiFullName:work@mul_unit.rs2_r
|vpiRhs:
\_ref_obj: (rs2_ext), line:55
|vpiName:rs2_ext
|vpiFullName:work@mul_unit.rs2_ext
|vpiStmt:
\_assignment: , line:56
|vpiOpType:82
|vpiLhs:
\_ref_obj: (result), line:56
|vpiName:result
|vpiFullName:work@mul_unit.result
|vpiRhs:
\_operation: , line:56
|vpiOpType:25
|vpiOperand:
\_ref_obj: (rs1_r), line:56
|vpiName:rs1_r
|vpiFullName:work@mul_unit.rs1_r
|vpiOperand:
\_ref_obj: (rs2_r), line:56
|vpiName:rs2_r
|vpiFullName:work@mul_unit.rs2_r
|vpiProcess:
\_always: , line:59
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:59
|vpiCondition:
\_operation: , line:59
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:59
|vpiName:clk
|vpiFullName:work@mul_unit.clk
|vpiStmt:
\_begin: , line:59
|vpiFullName:work@mul_unit
|vpiStmt:
\_assignment: , line:60
|vpiOpType:82
|vpiLhs:
\_bit_select: (mulh), line:60
|vpiName:mulh
|vpiFullName:work@mul_unit.mulh
|vpiIndex:
\_constant: , line:60
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiRhs:
\_operation: , line:60
|vpiOpType:15
|vpiOperand:
\_ref_obj: (mul_inputs.op), line:60
|vpiName:mul_inputs.op
|vpiFullName:work@mul_unit.mul_inputs.op
|vpiOperand:
\_part_select: , line:60, parent:MUL_fn3
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (MUL_fn3)
|vpiLeftRange:
\_constant: , line:60
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:60
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiStmt:
\_assignment: , line:61
|vpiOpType:82
|vpiLhs:
\_bit_select: (mulh), line:61
|vpiName:mulh
|vpiFullName:work@mul_unit.mulh
|vpiIndex:
\_constant: , line:61
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRhs:
\_bit_select: (mulh), line:61
|vpiName:mulh
|vpiFullName:work@mul_unit.mulh
|vpiIndex:
\_constant: , line:61
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiStmt:
\_assignment: , line:63
|vpiOpType:82
|vpiLhs:
\_bit_select: (id), line:63
|vpiName:id
|vpiFullName:work@mul_unit.id
|vpiIndex:
\_constant: , line:63
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiRhs:
\_ref_obj: (issue.instruction_id), line:63
|vpiName:issue.instruction_id
|vpiFullName:work@mul_unit.issue.instruction_id
|vpiStmt:
\_assignment: , line:64
|vpiOpType:82
|vpiLhs:
\_bit_select: (id), line:64
|vpiName:id
|vpiFullName:work@mul_unit.id
|vpiIndex:
\_constant: , line:64
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRhs:
\_bit_select: (id), line:64
|vpiName:id
|vpiFullName:work@mul_unit.id
|vpiIndex:
\_constant: , line:64
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiStmt:
\_assignment: , line:66
|vpiOpType:82
|vpiLhs:
\_bit_select: (done), line:66
|vpiName:done
|vpiFullName:work@mul_unit.done
|vpiIndex:
\_constant: , line:66
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiRhs:
\_ref_obj: (issue.new_request), line:66
|vpiName:issue.new_request
|vpiFullName:work@mul_unit.issue.new_request
|vpiStmt:
\_assignment: , line:67
|vpiOpType:82
|vpiLhs:
\_bit_select: (done), line:67
|vpiName:done
|vpiFullName:work@mul_unit.done
|vpiIndex:
\_constant: , line:67
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRhs:
\_bit_select: (done), line:67
|vpiName:done
|vpiFullName:work@mul_unit.done
|vpiIndex:
\_constant: , line:67
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiPort:
\_port: (clk), line:27
|vpiName:clk
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (clk), line:27
|vpiName:clk
|vpiFullName:work@mul_unit.clk
|vpiNetType:36
|vpiPort:
\_port: (rst), line:28
|vpiName:rst
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (rst), line:28
|vpiName:rst
|vpiFullName:work@mul_unit.rst
|vpiNetType:36
|vpiPort:
\_port: (mul_inputs), line:30
|vpiName:mul_inputs
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (mul_inputs), line:30
|vpiName:mul_inputs
|vpiFullName:work@mul_unit.mul_inputs
|vpiPort:
\_port: (issue), line:31
|vpiName:issue
|vpiDirection:5
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_modport: (unit)
|vpiPort:
\_port: (wb), line:32
|vpiName:wb
|vpiDirection:2
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (wb), line:32
|vpiName:wb
|vpiFullName:work@mul_unit.wb
|vpiContAssign:
\_cont_assign: , line:46
|vpiRhs:
\_operation: , line:46
|vpiOpType:95
|vpiOperand:
\_ref_obj: (mul_inputs.op), line:46
|vpiName:mul_inputs.op
|vpiFullName:work@mul_unit.mul_inputs.op
|vpiOperand:
\_part_select: , line:46, parent:MULH_fn3
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (MULH_fn3)
|vpiLeftRange:
\_constant: , line:46
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:46
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiOperand:
\_part_select: , line:46, parent:MULHSU_fn3
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (MULHSU_fn3)
|vpiLeftRange:
\_constant: , line:46
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:46
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiLhs:
\_ref_obj: (rs1_signed), line:46
|vpiName:rs1_signed
|vpiFullName:work@mul_unit.rs1_signed
|vpiContAssign:
\_cont_assign: , line:47
|vpiRhs:
\_operation: , line:47
|vpiOpType:95
|vpiOperand:
\_ref_obj: (mul_inputs.op), line:47
|vpiName:mul_inputs.op
|vpiFullName:work@mul_unit.mul_inputs.op
|vpiOperand:
\_part_select: , line:47, parent:MUL_fn3
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (MUL_fn3)
|vpiLeftRange:
\_constant: , line:47
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:47
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiOperand:
\_part_select: , line:47, parent:MULH_fn3
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (MULH_fn3)
|vpiLeftRange:
\_constant: , line:47
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:47
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiLhs:
\_ref_obj: (rs2_signed), line:47
|vpiName:rs2_signed
|vpiFullName:work@mul_unit.rs2_signed
|vpiContAssign:
\_cont_assign: , line:49
|vpiRhs:
\_operation: , line:49
|vpiOpType:67
|vpiOperand:
\_operation: , line:49
|vpiOpType:33
|vpiOperand:
\_operation: , line:49
|vpiOpType:28
|vpiOperand:
\_ref_obj: (mul_inputs.rs1), line:49
|vpiName:mul_inputs.rs1
|vpiFullName:work@mul_unit.mul_inputs.rs1
|vpiOperand:
\_ref_obj: (rs1_signed), line:49
|vpiName:rs1_signed
|vpiFullName:work@mul_unit.rs1_signed
|vpiOperand:
\_ref_obj: (mul_inputs.rs1), line:49
|vpiName:mul_inputs.rs1
|vpiFullName:work@mul_unit.mul_inputs.rs1
|vpiLhs:
\_ref_obj: (rs1_ext), line:49
|vpiName:rs1_ext
|vpiFullName:work@mul_unit.rs1_ext
|vpiContAssign:
\_cont_assign: , line:50
|vpiRhs:
\_operation: , line:50
|vpiOpType:67
|vpiOperand:
\_operation: , line:50
|vpiOpType:33
|vpiOperand:
\_operation: , line:50
|vpiOpType:28
|vpiOperand:
\_ref_obj: (mul_inputs.rs2), line:50
|vpiName:mul_inputs.rs2
|vpiFullName:work@mul_unit.mul_inputs.rs2
|vpiOperand:
\_ref_obj: (rs2_signed), line:50
|vpiName:rs2_signed
|vpiFullName:work@mul_unit.rs2_signed
|vpiOperand:
\_ref_obj: (mul_inputs.rs2), line:50
|vpiName:mul_inputs.rs2
|vpiFullName:work@mul_unit.mul_inputs.rs2
|vpiLhs:
\_ref_obj: (rs2_ext), line:50
|vpiName:rs2_ext
|vpiFullName:work@mul_unit.rs2_ext
|vpiContAssign:
\_cont_assign: , line:72
|vpiRhs:
\_constant: , line:72
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiLhs:
\_ref_obj: (issue.ready), line:72
|vpiName:issue.ready
|vpiFullName:work@mul_unit.issue.ready
|vpiContAssign:
\_cont_assign: , line:73
|vpiRhs:
\_operation: , line:73
|vpiOpType:32
|vpiOperand:
\_bit_select: (mulh), line:73
|vpiName:mulh
|vpiFullName:work@mul_unit.mulh
|vpiIndex:
\_constant: , line:73
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiOperand:
\_part_select: , line:73, parent:result
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (result)
|vpiLeftRange:
\_constant: , line:73
|vpiConstType:7
|vpiDecompile:63
|vpiSize:32
|INT:63
|vpiRightRange:
\_constant: , line:73
|vpiConstType:7
|vpiDecompile:32
|vpiSize:32
|INT:32
|vpiOperand:
\_part_select: , line:73, parent:result
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (result)
|vpiLeftRange:
\_constant: , line:73
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:73
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiLhs:
\_ref_obj: (wb.rd), line:73
|vpiName:wb.rd
|vpiFullName:work@mul_unit.wb.rd
|vpiContAssign:
\_cont_assign: , line:74
|vpiRhs:
\_bit_select: (done), line:74
|vpiName:done
|vpiFullName:work@mul_unit.done
|vpiIndex:
\_constant: , line:74
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiLhs:
\_ref_obj: (wb.done), line:74
|vpiName:wb.done
|vpiFullName:work@mul_unit.wb.done
|vpiContAssign:
\_cont_assign: , line:75
|vpiRhs:
\_bit_select: (id), line:75
|vpiName:id
|vpiFullName:work@mul_unit.id
|vpiIndex:
\_constant: , line:75
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiLhs:
\_ref_obj: (wb.id), line:75
|vpiName:wb.id
|vpiFullName:work@mul_unit.wb.id
|vpiNet:
\_logic_net: (clk), line:27
|vpiNet:
\_logic_net: (rst), line:28
|vpiNet:
\_logic_net: (mul_inputs), line:30
|vpiNet:
\_logic_net: (wb), line:32
|vpiNet:
\_logic_net: (result), line:35
|vpiName:result
|vpiFullName:work@mul_unit.result
|vpiNetType:36
|vpiNet:
\_logic_net: (mulh), line:36
|vpiName:mulh
|vpiFullName:work@mul_unit.mulh
|vpiNetType:36
|vpiNet:
\_logic_net: (done), line:37
|vpiName:done
|vpiFullName:work@mul_unit.done
|vpiNetType:36
|vpiNet:
\_logic_net: (id), line:38
|vpiName:id
|vpiFullName:work@mul_unit.id
|vpiNet:
\_logic_net: (rs1_signed), line:40
|vpiName:rs1_signed
|vpiFullName:work@mul_unit.rs1_signed
|vpiNetType:36
|vpiNet:
\_logic_net: (rs2_signed), line:40
|vpiName:rs2_signed
|vpiFullName:work@mul_unit.rs2_signed
|vpiNetType:36
|vpiNet:
\_logic_net: (rs1_ext), line:41
|vpiName:rs1_ext
|vpiFullName:work@mul_unit.rs1_ext
|vpiNetType:36
|vpiNet:
\_logic_net: (rs2_ext), line:41
|vpiName:rs2_ext
|vpiFullName:work@mul_unit.rs2_ext
|vpiNetType:36
|vpiNet:
\_logic_net: (rs1_r), line:42
|vpiName:rs1_r
|vpiFullName:work@mul_unit.rs1_r
|vpiNetType:36
|vpiNet:
\_logic_net: (rs2_r), line:42
|vpiName:rs2_r
|vpiFullName:work@mul_unit.rs2_r
|vpiNetType:36
|vpiNet:
\_logic_net: (issue), line:31
|vpiName:issue
|vpiFullName:work@mul_unit.issue
|vpiTypedef:
\_struct_typespec: (alu_inputs_t), line:301
|vpiTypedef:
\_enum_typespec: (alu_logic_op_t), line:84
|vpiTypedef:
\_enum_typespec: (alu_op_t), line:91
|vpiTypedef:
\_enum_typespec: (alu_rs1_op_t), line:97
|vpiTypedef:
\_enum_typespec: (alu_rs2_op_t), line:104
|vpiTypedef:
\_struct_typespec: (amo_alu_inputs_t), line:356
|vpiTypedef:
\_struct_typespec: (amo_details_t), line:362
|vpiTypedef:
\_enum_typespec: (amo_t), line:354
|vpiTypedef:
\_struct_typespec: (branch_inputs_t), line:313
|vpiTypedef:
\_logic_typespec: (branch_predictor_metadata_t), line:32
|vpiTypedef:
\_struct_typespec: (branch_results_t), line:330
|vpiTypedef:
\_enum_typespec: (bus_type_t), line:86
|vpiTypedef:
\_struct_typespec: (csr_inputs_t), line:396
|vpiTypedef:
\_enum_typespec: (csr_op_t), line:218
|vpiTypedef:
\_enum_typespec: (csr_t), line:201
|vpiTypedef:
\_struct_typespec: (data_access_shared_inputs_t), line:427
|vpiTypedef:
\_struct_typespec: (div_inputs_t), line:389
|vpiTypedef:
\_enum_typespec: (div_type), line:66
|vpiTypedef:
\_enum_typespec: (exception_code_t), line:245
|vpiTypedef:
\_struct_typespec: (exception_packet_t), line:263
|vpiTypedef:
\_struct_typespec: (fetch_buffer_packet_t), line:276
|vpiTypedef:
\_enum_typespec: (fifo_type_t), line:440
|vpiTypedef:
\_enum_typespec: (fn3_arith_t), line:76
|vpiTypedef:
\_enum_typespec: (fn3_branch_t), line:126
|vpiTypedef:
\_enum_typespec: (fn3_csr_t), line:212
|vpiTypedef:
\_enum_typespec: (fn3_ls_t), line:115
|vpiTypedef:
\_enum_typespec: (fn3_mul_div_t), line:138
|vpiTypedef:
\_struct_typespec: (gc_inputs_t), line:404
|vpiTypedef:
\_struct_typespec: (inflight_instruction_packet), line:271
|vpiTypedef:
\_logic_typespec: (instruction_id_t), line:30
|vpiTypedef:
\_enum_typespec: (interrupt_code_t), line:261
|vpiTypedef:
\_struct_typespec: (load_store_inputs_t), line:369
|vpiTypedef:
\_struct_typespec: (mul_inputs_t), line:383
|vpiTypedef:
\_enum_typespec: (opcodes_t), line:48
|vpiTypedef:
\_enum_typespec: (opcodes_trimmed_t), line:65
|vpiTypedef:
\_struct_typespec: (simulation_named_regfile), line:476
|vpiTypedef:
\_struct_typespec: (taiga_trace_events_t), line:442
|vpiTypedef:
\_struct_typespec: (to_l1_arbiter_packet), line:418
|vpiTypedef:
\_struct_typespec: (trace_outputs_t), line:469
|vpiTypedef:
\_logic_typespec: (unit_id_t), line:31
|vpiTypedef:
\_struct_typespec: (unit_writeback_t), line:295
|vpiTypedef:
\_enum_typespec: (vm_t), line:223
|uhdmallModules:
\_module: work@one_hot_occupancy, file:third_party/cores/taiga/core/one_hot_occupancy.sv, line:26, parent:work@div_unit_core_wrapper
|vpiDefName:work@one_hot_occupancy
|vpiFullName:work@one_hot_occupancy
|vpiProcess:
\_always: , line:42
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:42
|vpiCondition:
\_operation: , line:42
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:42
|vpiName:clk
|vpiFullName:work@one_hot_occupancy.clk
|vpiStmt:
\_begin: , line:42
|vpiFullName:work@one_hot_occupancy
|vpiStmt:
\_if_else: , line:43
|vpiCondition:
\_ref_obj: (rst), line:43
|vpiName:rst
|vpiFullName:work@one_hot_occupancy.rst
|vpiStmt:
\_begin: , line:43
|vpiFullName:work@one_hot_occupancy
|vpiStmt:
\_assignment: , line:44
|vpiOpType:82
|vpiLhs:
\_bit_select: (valid_chain), line:44
|vpiName:valid_chain
|vpiFullName:work@one_hot_occupancy.valid_chain
|vpiIndex:
\_constant: , line:44
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiRhs:
\_constant: , line:44
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiStmt:
\_assignment: , line:45
|vpiOpType:82
|vpiLhs:
\_part_select: , line:45, parent:valid_chain
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (valid_chain)
|vpiLeftRange:
\_ref_obj: (DEPTH), line:45
|vpiName:DEPTH
|vpiRightRange:
\_constant: , line:45
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRhs:
\_constant: , line:45
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiElseStmt:
\_begin: , line:47
|vpiFullName:work@one_hot_occupancy
|vpiStmt:
\_case_stmt: , line:48
|vpiCaseType:1
|vpiCondition:
\_operation: , line:48
|vpiOpType:33
|vpiOperand:
\_ref_obj: (push), line:48
|vpiName:push
|vpiOperand:
\_ref_obj: (pop), line:48
|vpiName:pop
|vpiCaseItem:
\_case_item: , line:49
|vpiExpr:
\_constant: , line:49
|vpiConstType:3
|vpiDecompile:2'b10
|vpiSize:2
|BIN:2'b10
|vpiStmt:
\_assignment: , line:49
|vpiOpType:82
|vpiLhs:
\_ref_obj: (valid_chain), line:49
|vpiName:valid_chain
|vpiFullName:work@one_hot_occupancy.valid_chain
|vpiRhs:
\_operation: , line:49
|vpiOpType:33
|vpiOperand:
\_part_select: , line:49, parent:valid_chain
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (valid_chain)
|vpiLeftRange:
\_operation: , line:49
|vpiOpType:11
|vpiOperand:
\_ref_obj: (DEPTH), line:49
|vpiName:DEPTH
|vpiOperand:
\_constant: , line:49
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:49
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiOperand:
\_constant: , line:49
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiCaseItem:
\_case_item: , line:50
|vpiExpr:
\_constant: , line:50
|vpiConstType:3
|vpiDecompile:2'b01
|vpiSize:2
|BIN:2'b01
|vpiStmt:
\_assignment: , line:50
|vpiOpType:82
|vpiLhs:
\_ref_obj: (valid_chain), line:50
|vpiName:valid_chain
|vpiFullName:work@one_hot_occupancy.valid_chain
|vpiRhs:
\_operation: , line:50
|vpiOpType:33
|vpiOperand:
\_constant: , line:50
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiOperand:
\_part_select: , line:50, parent:valid_chain
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (valid_chain)
|vpiLeftRange:
\_ref_obj: (DEPTH), line:50
|vpiName:DEPTH
|vpiRightRange:
\_constant: , line:50
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiCaseItem:
\_case_item: , line:51
|vpiStmt:
\_assignment: , line:51
|vpiOpType:82
|vpiLhs:
\_ref_obj: (valid_chain), line:51
|vpiName:valid_chain
|vpiFullName:work@one_hot_occupancy.valid_chain
|vpiRhs:
\_ref_obj: (valid_chain), line:51
|vpiName:valid_chain
|vpiFullName:work@one_hot_occupancy.valid_chain
|vpiProcess:
\_always: , line:66
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:66
|vpiCondition:
\_operation: , line:66
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:66
|vpiName:clk
|vpiFullName:work@one_hot_occupancy.clk
|vpiStmt:
\_begin: , line:66
|vpiFullName:work@one_hot_occupancy
|vpiStmt:
\_immediate_assert: , line:67
|vpiExpr:
\_operation: , line:67
|vpiOpType:3
|vpiOperand:
\_operation: , line:67
|vpiOpType:28
|vpiOperand:
\_operation: , line:67
|vpiOpType:28
|vpiOperand:
\_operation: , line:67
|vpiOpType:4
|vpiOperand:
\_ref_obj: (rst), line:67
|vpiName:rst
|vpiFullName:work@one_hot_occupancy.rst
|vpiOperand:
\_bit_select: (valid_chain), line:67
|vpiName:valid_chain
|vpiFullName:work@one_hot_occupancy.valid_chain
|vpiIndex:
\_ref_obj: (DEPTH), line:67
|vpiName:DEPTH
|vpiFullName:work@one_hot_occupancy.DEPTH
|vpiOperand:
\_ref_obj: (push), line:67
|vpiName:push
|vpiFullName:work@one_hot_occupancy.push
|vpiElseStmt:
\_sys_func_call: ($error), line:67
|vpiName:$error
|vpiArgument:
\_constant: , line:67
|vpiConstType:6
|vpiDecompile:"overflow"
|vpiSize:10
|STRING:"overflow"
|vpiStmt:
\_immediate_assert: , line:68
|vpiExpr:
\_operation: , line:68
|vpiOpType:3
|vpiOperand:
\_operation: , line:68
|vpiOpType:28
|vpiOperand:
\_operation: , line:68
|vpiOpType:28
|vpiOperand:
\_operation: , line:68
|vpiOpType:4
|vpiOperand:
\_ref_obj: (rst), line:68
|vpiName:rst
|vpiFullName:work@one_hot_occupancy.rst
|vpiOperand:
\_bit_select: (valid_chain), line:68
|vpiName:valid_chain
|vpiFullName:work@one_hot_occupancy.valid_chain
|vpiIndex:
\_constant: , line:68
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiOperand:
\_ref_obj: (pop), line:68
|vpiName:pop
|vpiFullName:work@one_hot_occupancy.pop
|vpiElseStmt:
\_sys_func_call: ($error), line:68
|vpiName:$error
|vpiArgument:
\_constant: , line:68
|vpiConstType:6
|vpiDecompile:"underflow"
|vpiSize:11
|STRING:"underflow"
|vpiPort:
\_port: (clk), line:28
|vpiName:clk
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (clk), line:28
|vpiName:clk
|vpiFullName:work@one_hot_occupancy.clk
|vpiNetType:36
|vpiPort:
\_port: (rst), line:29
|vpiName:rst
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (rst), line:29
|vpiName:rst
|vpiFullName:work@one_hot_occupancy.rst
|vpiNetType:36
|vpiPort:
\_port: (push), line:30
|vpiName:push
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (push), line:30
|vpiName:push
|vpiFullName:work@one_hot_occupancy.push
|vpiNetType:36
|vpiPort:
\_port: (pop), line:31
|vpiName:pop
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (pop), line:31
|vpiName:pop
|vpiFullName:work@one_hot_occupancy.pop
|vpiNetType:36
|vpiPort:
\_port: (almost_full), line:32
|vpiName:almost_full
|vpiDirection:2
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (almost_full), line:32
|vpiName:almost_full
|vpiFullName:work@one_hot_occupancy.almost_full
|vpiNetType:36
|vpiPort:
\_port: (full), line:33
|vpiName:full
|vpiDirection:2
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (full), line:33
|vpiName:full
|vpiFullName:work@one_hot_occupancy.full
|vpiNetType:36
|vpiPort:
\_port: (empty), line:34
|vpiName:empty
|vpiDirection:2
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (empty), line:34
|vpiName:empty
|vpiFullName:work@one_hot_occupancy.empty
|vpiNetType:36
|vpiPort:
\_port: (almost_empty), line:35
|vpiName:almost_empty
|vpiDirection:2
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (almost_empty), line:35
|vpiName:almost_empty
|vpiFullName:work@one_hot_occupancy.almost_empty
|vpiNetType:36
|vpiPort:
\_port: (valid), line:36
|vpiName:valid
|vpiDirection:2
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (valid), line:36
|vpiName:valid
|vpiFullName:work@one_hot_occupancy.valid
|vpiNetType:36
|vpiContAssign:
\_cont_assign: , line:56
|vpiRhs:
\_bit_select: (valid_chain), line:56
|vpiName:valid_chain
|vpiFullName:work@one_hot_occupancy.valid_chain
|vpiIndex:
\_constant: , line:56
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiLhs:
\_ref_obj: (empty), line:56
|vpiName:empty
|vpiFullName:work@one_hot_occupancy.empty
|vpiContAssign:
\_cont_assign: , line:57
|vpiRhs:
\_bit_select: (valid_chain), line:57
|vpiName:valid_chain
|vpiFullName:work@one_hot_occupancy.valid_chain
|vpiIndex:
\_constant: , line:57
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiLhs:
\_ref_obj: (almost_empty), line:57
|vpiName:almost_empty
|vpiFullName:work@one_hot_occupancy.almost_empty
|vpiContAssign:
\_cont_assign: , line:59
|vpiRhs:
\_operation: , line:59
|vpiOpType:4
|vpiOperand:
\_bit_select: (valid_chain), line:59
|vpiName:valid_chain
|vpiIndex:
\_constant: , line:59
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiLhs:
\_ref_obj: (valid), line:59
|vpiName:valid
|vpiFullName:work@one_hot_occupancy.valid
|vpiContAssign:
\_cont_assign: , line:60
|vpiRhs:
\_bit_select: (valid_chain), line:60
|vpiName:valid_chain
|vpiFullName:work@one_hot_occupancy.valid_chain
|vpiIndex:
\_ref_obj: (DEPTH), line:60
|vpiName:DEPTH
|vpiLhs:
\_ref_obj: (full), line:60
|vpiName:full
|vpiFullName:work@one_hot_occupancy.full
|vpiContAssign:
\_cont_assign: , line:62
|vpiRhs:
\_bit_select: (valid_chain), line:62
|vpiName:valid_chain
|vpiFullName:work@one_hot_occupancy.valid_chain
|vpiIndex:
\_operation: , line:62
|vpiOpType:11
|vpiOperand:
\_ref_obj: (DEPTH), line:62
|vpiName:DEPTH
|vpiOperand:
\_constant: , line:62
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiLhs:
\_ref_obj: (almost_full), line:62
|vpiName:almost_full
|vpiFullName:work@one_hot_occupancy.almost_full
|vpiNet:
\_logic_net: (clk), line:28
|vpiNet:
\_logic_net: (rst), line:29
|vpiNet:
\_logic_net: (push), line:30
|vpiNet:
\_logic_net: (pop), line:31
|vpiNet:
\_logic_net: (almost_full), line:32
|vpiNet:
\_logic_net: (full), line:33
|vpiNet:
\_logic_net: (empty), line:34
|vpiNet:
\_logic_net: (almost_empty), line:35
|vpiNet:
\_logic_net: (valid), line:36
|vpiNet:
\_logic_net: (valid_chain), line:39
|vpiName:valid_chain
|vpiFullName:work@one_hot_occupancy.valid_chain
|vpiNetType:36
|vpiTypedef:
\_struct_typespec: (alu_inputs_t), line:301
|vpiTypedef:
\_enum_typespec: (alu_logic_op_t), line:84
|vpiTypedef:
\_enum_typespec: (alu_op_t), line:91
|vpiTypedef:
\_enum_typespec: (alu_rs1_op_t), line:97
|vpiTypedef:
\_enum_typespec: (alu_rs2_op_t), line:104
|vpiTypedef:
\_struct_typespec: (amo_alu_inputs_t), line:356
|vpiTypedef:
\_struct_typespec: (amo_details_t), line:362
|vpiTypedef:
\_enum_typespec: (amo_t), line:354
|vpiTypedef:
\_struct_typespec: (branch_inputs_t), line:313
|vpiTypedef:
\_logic_typespec: (branch_predictor_metadata_t), line:32
|vpiTypedef:
\_struct_typespec: (branch_results_t), line:330
|vpiTypedef:
\_enum_typespec: (bus_type_t), line:86
|vpiTypedef:
\_struct_typespec: (csr_inputs_t), line:396
|vpiTypedef:
\_enum_typespec: (csr_op_t), line:218
|vpiTypedef:
\_enum_typespec: (csr_t), line:201
|vpiTypedef:
\_struct_typespec: (data_access_shared_inputs_t), line:427
|vpiTypedef:
\_struct_typespec: (div_inputs_t), line:389
|vpiTypedef:
\_enum_typespec: (div_type), line:66
|vpiTypedef:
\_enum_typespec: (exception_code_t), line:245
|vpiTypedef:
\_struct_typespec: (exception_packet_t), line:263
|vpiTypedef:
\_struct_typespec: (fetch_buffer_packet_t), line:276
|vpiTypedef:
\_enum_typespec: (fifo_type_t), line:440
|vpiTypedef:
\_enum_typespec: (fn3_arith_t), line:76
|vpiTypedef:
\_enum_typespec: (fn3_branch_t), line:126
|vpiTypedef:
\_enum_typespec: (fn3_csr_t), line:212
|vpiTypedef:
\_enum_typespec: (fn3_ls_t), line:115
|vpiTypedef:
\_enum_typespec: (fn3_mul_div_t), line:138
|vpiTypedef:
\_struct_typespec: (gc_inputs_t), line:404
|vpiTypedef:
\_struct_typespec: (inflight_instruction_packet), line:271
|vpiTypedef:
\_logic_typespec: (instruction_id_t), line:30
|vpiTypedef:
\_enum_typespec: (interrupt_code_t), line:261
|vpiTypedef:
\_struct_typespec: (load_store_inputs_t), line:369
|vpiTypedef:
\_struct_typespec: (mul_inputs_t), line:383
|vpiTypedef:
\_enum_typespec: (opcodes_t), line:48
|vpiTypedef:
\_enum_typespec: (opcodes_trimmed_t), line:65
|vpiTypedef:
\_struct_typespec: (simulation_named_regfile), line:476
|vpiTypedef:
\_struct_typespec: (taiga_trace_events_t), line:442
|vpiTypedef:
\_struct_typespec: (to_l1_arbiter_packet), line:418
|vpiTypedef:
\_struct_typespec: (trace_outputs_t), line:469
|vpiTypedef:
\_logic_typespec: (unit_id_t), line:31
|vpiTypedef:
\_struct_typespec: (unit_writeback_t), line:295
|vpiTypedef:
\_enum_typespec: (vm_t), line:223
|vpiParamAssign:
\_param_assign: , line:26
|vpiRhs:
\_constant: , line:26
|vpiConstType:7
|vpiDecompile:4
|vpiSize:32
|INT:4
|vpiLhs:
\_parameter: (DEPTH), line:26
|vpiName:DEPTH
|vpiParameter:
\_parameter: (DEPTH), line:26
|uhdmallModules:
\_module: work@one_hot_to_integer, file:third_party/cores/taiga/core/one_hot_to_integer.sv, line:25, parent:work@div_unit_core_wrapper
|vpiDefName:work@one_hot_to_integer
|vpiFullName:work@one_hot_to_integer
|vpiProcess:
\_always: , line:51
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:51
|vpiCondition:
\_operation: , line:51
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:51
|vpiName:clk
|vpiFullName:work@one_hot_to_integer.clk
|vpiStmt:
\_begin: , line:51
|vpiFullName:work@one_hot_to_integer
|vpiStmt:
\_immediate_assert: , line:52
|vpiExpr:
\_operation: , line:52
|vpiOpType:27
|vpiOperand:
\_ref_obj: (rst), line:52
|vpiName:rst
|vpiFullName:work@one_hot_to_integer.rst
|vpiOperand:
\_operation: , line:52
|vpiOpType:26
|vpiOperand:
\_operation: , line:52
|vpiOpType:4
|vpiOperand:
\_ref_obj: (rst), line:52
|vpiName:rst
|vpiFullName:work@one_hot_to_integer.rst
|vpiOperand:
\_sys_func_call: ($onehot0), line:52
|vpiName:$onehot0
|vpiArgument:
\_ref_obj: (one_hot), line:52
|vpiName:one_hot
|vpiElseStmt:
\_sys_func_call: ($error), line:52
|vpiName:$error
|vpiArgument:
\_constant: , line:52
|vpiConstType:6
|vpiDecompile:"One-hot signal has multiple bits set!"
|vpiSize:39
|STRING:"One-hot signal has multiple bits set!"
|vpiPort:
\_port: (clk), line:31
|vpiName:clk
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (clk), line:31
|vpiName:clk
|vpiFullName:work@one_hot_to_integer.clk
|vpiNetType:36
|vpiPort:
\_port: (rst), line:32
|vpiName:rst
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (rst), line:32
|vpiName:rst
|vpiFullName:work@one_hot_to_integer.rst
|vpiNetType:36
|vpiPort:
\_port: (one_hot), line:33
|vpiName:one_hot
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (one_hot), line:33
|vpiName:one_hot
|vpiFullName:work@one_hot_to_integer.one_hot
|vpiNetType:36
|vpiPort:
\_port: (int_out), line:34
|vpiName:int_out
|vpiDirection:2
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (int_out), line:34
|vpiName:int_out
|vpiFullName:work@one_hot_to_integer.int_out
|vpiNetType:36
|vpiNet:
\_logic_net: (clk), line:31
|vpiNet:
\_logic_net: (rst), line:32
|vpiNet:
\_logic_net: (one_hot), line:33
|vpiNet:
\_logic_net: (int_out), line:34
|vpiParamAssign:
\_param_assign: , line:27
|vpiRhs:
\_constant: , line:27
|vpiConstType:7
|vpiDecompile:6
|vpiSize:32
|INT:6
|vpiLhs:
\_parameter: (C_WIDTH), line:27
|vpiName:C_WIDTH
|vpiParameter:
\_parameter: (C_WIDTH), line:27
|uhdmallModules:
\_module: work@placer_randomizer, file:third_party/cores/taiga/core/placer_randomizer.sv, line:1, parent:work@div_unit_core_wrapper
|vpiDefName:work@placer_randomizer
|vpiFullName:work@placer_randomizer
|vpiProcess:
\_always: , line:10
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:10
|vpiCondition:
\_operation: , line:10
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:10
|vpiName:clk
|vpiFullName:work@placer_randomizer.clk
|vpiStmt:
\_begin: , line:10
|vpiFullName:work@placer_randomizer
|vpiStmt:
\_assignment: , line:11
|vpiOpType:82
|vpiLhs:
\_ref_obj: (result), line:11
|vpiName:result
|vpiFullName:work@placer_randomizer.result
|vpiRhs:
\_operation: , line:11
|vpiOpType:7
|vpiOperand:
\_operation: , line:11
|vpiOpType:28
|vpiOperand:
\_ref_obj: (samples), line:11
|vpiName:samples
|vpiFullName:work@placer_randomizer.samples
|vpiOperand:
\_ref_obj: (PLACER_SEED), line:11
|vpiName:PLACER_SEED
|vpiFullName:work@placer_randomizer.PLACER_SEED
|vpiPort:
\_port: (clk), line:5
|vpiName:clk
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (clk), line:5
|vpiName:clk
|vpiFullName:work@placer_randomizer.clk
|vpiNetType:36
|vpiPort:
\_port: (samples), line:6
|vpiName:samples
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (samples), line:6
|vpiName:samples
|vpiFullName:work@placer_randomizer.samples
|vpiNetType:36
|vpiPort:
\_port: (result), line:7
|vpiName:result
|vpiDirection:2
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (result), line:7
|vpiName:result
|vpiFullName:work@placer_randomizer.result
|vpiNetType:36
|vpiNet:
\_logic_net: (clk), line:5
|vpiNet:
\_logic_net: (samples), line:6
|vpiNet:
\_logic_net: (result), line:7
|vpiParamAssign:
\_param_assign: , line:2
|vpiRhs:
\_constant: , line:2
|vpiConstType:5
|vpiDecompile:8'h2B
|vpiSize:8
|HEX:8'h2B
|vpiLhs:
\_parameter: (PLACER_SEED), line:2
|vpiName:PLACER_SEED
|vpiTypespec:
\_logic_typespec: , line:2
|vpiRange:
\_range: , line:2
|vpiLeftRange:
\_constant: , line:2
|vpiConstType:7
|vpiDecompile:7
|vpiSize:32
|INT:7
|vpiRightRange:
\_constant: , line:2
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiParameter:
\_parameter: (PLACER_SEED), line:2
|uhdmallModules:
\_module: work@pre_decode, file:third_party/cores/taiga/core/pre_decode.sv, line:26, parent:work@div_unit_core_wrapper
|vpiDefName:work@pre_decode
|vpiFullName:work@pre_decode
|vpiProcess:
\_always: , line:84
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:84
|vpiCondition:
\_operation: , line:84
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:84
|vpiName:clk
|vpiFullName:work@pre_decode.clk
|vpiStmt:
\_begin: , line:84
|vpiFullName:work@pre_decode
|vpiStmt:
\_if_else: , line:85
|vpiCondition:
\_ref_obj: (push_to_reg), line:85
|vpiName:push_to_reg
|vpiFullName:work@pre_decode.push_to_reg
|vpiStmt:
\_assignment: , line:86
|vpiOpType:82
|vpiLhs:
\_ref_obj: (fb), line:86
|vpiName:fb
|vpiFullName:work@pre_decode.fb
|vpiRhs:
\_ref_obj: (data_in), line:86
|vpiName:data_in
|vpiFullName:work@pre_decode.data_in
|vpiElseStmt:
\_if_stmt: , line:87
|vpiCondition:
\_ref_obj: (pre_decode_pop), line:87
|vpiName:pre_decode_pop
|vpiFullName:work@pre_decode.pre_decode_pop
|vpiStmt:
\_assignment: , line:88
|vpiOpType:82
|vpiLhs:
\_ref_obj: (fb), line:88
|vpiName:fb
|vpiFullName:work@pre_decode.fb
|vpiRhs:
\_ref_obj: (data_out), line:88
|vpiName:data_out
|vpiFullName:work@pre_decode.data_out
|vpiProcess:
\_always: , line:91
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:91
|vpiCondition:
\_operation: , line:91
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:91
|vpiName:clk
|vpiFullName:work@pre_decode.clk
|vpiStmt:
\_begin: , line:91
|vpiFullName:work@pre_decode
|vpiStmt:
\_if_else: , line:92
|vpiCondition:
\_ref_obj: (buffer_reset), line:92
|vpiName:buffer_reset
|vpiFullName:work@pre_decode.buffer_reset
|vpiStmt:
\_assignment: , line:93
|vpiOpType:82
|vpiLhs:
\_ref_obj: (fb_valid), line:93
|vpiName:fb_valid
|vpiFullName:work@pre_decode.fb_valid
|vpiRhs:
\_constant: , line:93
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiElseStmt:
\_if_else: , line:94
|vpiCondition:
\_ref_obj: (pre_decode_push), line:94
|vpiName:pre_decode_push
|vpiFullName:work@pre_decode.pre_decode_push
|vpiStmt:
\_assignment: , line:95
|vpiOpType:82
|vpiLhs:
\_ref_obj: (fb_valid), line:95
|vpiName:fb_valid
|vpiFullName:work@pre_decode.fb_valid
|vpiRhs:
\_constant: , line:95
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiElseStmt:
\_if_stmt: , line:96
|vpiCondition:
\_operation: , line:96
|vpiOpType:28
|vpiOperand:
\_ref_obj: (pre_decode_pop), line:96
|vpiName:pre_decode_pop
|vpiFullName:work@pre_decode.pre_decode_pop
|vpiOperand:
\_operation: , line:96
|vpiOpType:4
|vpiOperand:
\_ref_obj: (fb_fifo.valid), line:96
|vpiName:fb_fifo.valid
|vpiFullName:work@pre_decode.fb_fifo.valid
|vpiStmt:
\_assignment: , line:97
|vpiOpType:82
|vpiLhs:
\_ref_obj: (fb_valid), line:97
|vpiName:fb_valid
|vpiFullName:work@pre_decode.fb_valid
|vpiRhs:
\_constant: , line:97
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiProcess:
\_always: , line:152
|vpiAlwaysType:2
|vpiStmt:
\_begin: , line:152
|vpiFullName:work@pre_decode
|vpiStmt:
\_case_stmt: , line:153
|vpiCaseType:1
|vpiCondition:
\_ref_obj: (fn3), line:153
|vpiName:fn3
|vpiFullName:work@pre_decode.fn3
|vpiCaseItem:
\_case_item: , line:154
|vpiExpr:
\_ref_obj: (SLT_fn3), line:154
|vpiName:SLT_fn3
|vpiFullName:work@pre_decode.SLT_fn3
|vpiStmt:
\_assignment: , line:154
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (data_in.alu_logic_op), line:154
|vpiName:data_in.alu_logic_op
|vpiFullName:work@pre_decode.data_in.alu_logic_op
|vpiRhs:
\_ref_obj: (ALU_LOGIC_ADD), line:154
|vpiName:ALU_LOGIC_ADD
|vpiFullName:work@pre_decode.ALU_LOGIC_ADD
|vpiCaseItem:
\_case_item: , line:155
|vpiExpr:
\_ref_obj: (SLTU_fn3), line:155
|vpiName:SLTU_fn3
|vpiFullName:work@pre_decode.SLTU_fn3
|vpiStmt:
\_assignment: , line:155
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (data_in.alu_logic_op), line:155
|vpiName:data_in.alu_logic_op
|vpiFullName:work@pre_decode.data_in.alu_logic_op
|vpiRhs:
\_ref_obj: (ALU_LOGIC_ADD), line:155
|vpiName:ALU_LOGIC_ADD
|vpiFullName:work@pre_decode.ALU_LOGIC_ADD
|vpiCaseItem:
\_case_item: , line:156
|vpiExpr:
\_ref_obj: (SLL_fn3), line:156
|vpiName:SLL_fn3
|vpiFullName:work@pre_decode.SLL_fn3
|vpiStmt:
\_assignment: , line:156
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (data_in.alu_logic_op), line:156
|vpiName:data_in.alu_logic_op
|vpiFullName:work@pre_decode.data_in.alu_logic_op
|vpiRhs:
\_ref_obj: (ALU_LOGIC_ADD), line:156
|vpiName:ALU_LOGIC_ADD
|vpiFullName:work@pre_decode.ALU_LOGIC_ADD
|vpiCaseItem:
\_case_item: , line:157
|vpiExpr:
\_ref_obj: (XOR_fn3), line:157
|vpiName:XOR_fn3
|vpiFullName:work@pre_decode.XOR_fn3
|vpiStmt:
\_assignment: , line:157
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (data_in.alu_logic_op), line:157
|vpiName:data_in.alu_logic_op
|vpiFullName:work@pre_decode.data_in.alu_logic_op
|vpiRhs:
\_ref_obj: (ALU_LOGIC_XOR), line:157
|vpiName:ALU_LOGIC_XOR
|vpiFullName:work@pre_decode.ALU_LOGIC_XOR
|vpiCaseItem:
\_case_item: , line:158
|vpiExpr:
\_ref_obj: (OR_fn3), line:158
|vpiName:OR_fn3
|vpiFullName:work@pre_decode.OR_fn3
|vpiStmt:
\_assignment: , line:158
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (data_in.alu_logic_op), line:158
|vpiName:data_in.alu_logic_op
|vpiFullName:work@pre_decode.data_in.alu_logic_op
|vpiRhs:
\_ref_obj: (ALU_LOGIC_OR), line:158
|vpiName:ALU_LOGIC_OR
|vpiFullName:work@pre_decode.ALU_LOGIC_OR
|vpiCaseItem:
\_case_item: , line:159
|vpiExpr:
\_ref_obj: (AND_fn3), line:159
|vpiName:AND_fn3
|vpiFullName:work@pre_decode.AND_fn3
|vpiStmt:
\_assignment: , line:159
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (data_in.alu_logic_op), line:159
|vpiName:data_in.alu_logic_op
|vpiFullName:work@pre_decode.data_in.alu_logic_op
|vpiRhs:
\_ref_obj: (ALU_LOGIC_AND), line:159
|vpiName:ALU_LOGIC_AND
|vpiFullName:work@pre_decode.ALU_LOGIC_AND
|vpiCaseItem:
\_case_item: , line:160
|vpiExpr:
\_ref_obj: (SRA_fn3), line:160
|vpiName:SRA_fn3
|vpiFullName:work@pre_decode.SRA_fn3
|vpiStmt:
\_assignment: , line:160
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (data_in.alu_logic_op), line:160
|vpiName:data_in.alu_logic_op
|vpiFullName:work@pre_decode.data_in.alu_logic_op
|vpiRhs:
\_ref_obj: (ALU_LOGIC_ADD), line:160
|vpiName:ALU_LOGIC_ADD
|vpiFullName:work@pre_decode.ALU_LOGIC_ADD
|vpiCaseItem:
\_case_item: , line:161
|vpiExpr:
\_ref_obj: (ADD_SUB_fn3), line:161
|vpiName:ADD_SUB_fn3
|vpiFullName:work@pre_decode.ADD_SUB_fn3
|vpiStmt:
\_assignment: , line:161
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (data_in.alu_logic_op), line:161
|vpiName:data_in.alu_logic_op
|vpiFullName:work@pre_decode.data_in.alu_logic_op
|vpiRhs:
\_ref_obj: (ALU_LOGIC_ADD), line:161
|vpiName:ALU_LOGIC_ADD
|vpiFullName:work@pre_decode.ALU_LOGIC_ADD
|vpiStmt:
\_assignment: , line:164
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (data_in.alu_logic_op), line:164
|vpiName:data_in.alu_logic_op
|vpiFullName:work@pre_decode.data_in.alu_logic_op
|vpiRhs:
\_operation: , line:164
|vpiOpType:32
|vpiOperand:
\_bit_select: (opcode), line:164
|vpiName:opcode
|vpiFullName:work@pre_decode.opcode
|vpiIndex:
\_constant: , line:164
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiOperand:
\_ref_obj: (ALU_LOGIC_ADD), line:164
|vpiName:ALU_LOGIC_ADD
|vpiFullName:work@pre_decode.ALU_LOGIC_ADD
|vpiOperand:
\_ref_obj: (data_in.alu_logic_op), line:164
|vpiName:data_in.alu_logic_op
|vpiFullName:work@pre_decode.data_in.alu_logic_op
|vpiProcess:
\_always: , line:167
|vpiAlwaysType:2
|vpiStmt:
\_begin: , line:167
|vpiFullName:work@pre_decode
|vpiStmt:
\_case_stmt: , line:168
|vpiCaseType:1
|vpiCondition:
\_ref_obj: (fn3), line:168
|vpiName:fn3
|vpiFullName:work@pre_decode.fn3
|vpiCaseItem:
\_case_item: , line:169
|vpiExpr:
\_ref_obj: (SLT_fn3), line:169
|vpiName:SLT_fn3
|vpiFullName:work@pre_decode.SLT_fn3
|vpiStmt:
\_assignment: , line:169
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (data_in.alu_op), line:169
|vpiName:data_in.alu_op
|vpiFullName:work@pre_decode.data_in.alu_op
|vpiRhs:
\_ref_obj: (ALU_SLT), line:169
|vpiName:ALU_SLT
|vpiFullName:work@pre_decode.ALU_SLT
|vpiCaseItem:
\_case_item: , line:170
|vpiExpr:
\_ref_obj: (SLTU_fn3), line:170
|vpiName:SLTU_fn3
|vpiFullName:work@pre_decode.SLTU_fn3
|vpiStmt:
\_assignment: , line:170
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (data_in.alu_op), line:170
|vpiName:data_in.alu_op
|vpiFullName:work@pre_decode.data_in.alu_op
|vpiRhs:
\_ref_obj: (ALU_SLT), line:170
|vpiName:ALU_SLT
|vpiFullName:work@pre_decode.ALU_SLT
|vpiCaseItem:
\_case_item: , line:171
|vpiExpr:
\_ref_obj: (SLL_fn3), line:171
|vpiName:SLL_fn3
|vpiFullName:work@pre_decode.SLL_fn3
|vpiStmt:
\_assignment: , line:171
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (data_in.alu_op), line:171
|vpiName:data_in.alu_op
|vpiFullName:work@pre_decode.data_in.alu_op
|vpiRhs:
\_ref_obj: (ALU_LSHIFT), line:171
|vpiName:ALU_LSHIFT
|vpiFullName:work@pre_decode.ALU_LSHIFT
|vpiCaseItem:
\_case_item: , line:172
|vpiExpr:
\_ref_obj: (XOR_fn3), line:172
|vpiName:XOR_fn3
|vpiFullName:work@pre_decode.XOR_fn3
|vpiStmt:
\_assignment: , line:172
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (data_in.alu_op), line:172
|vpiName:data_in.alu_op
|vpiFullName:work@pre_decode.data_in.alu_op
|vpiRhs:
\_ref_obj: (ALU_ADD_SUB), line:172
|vpiName:ALU_ADD_SUB
|vpiFullName:work@pre_decode.ALU_ADD_SUB
|vpiCaseItem:
\_case_item: , line:173
|vpiExpr:
\_ref_obj: (OR_fn3), line:173
|vpiName:OR_fn3
|vpiFullName:work@pre_decode.OR_fn3
|vpiStmt:
\_assignment: , line:173
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (data_in.alu_op), line:173
|vpiName:data_in.alu_op
|vpiFullName:work@pre_decode.data_in.alu_op
|vpiRhs:
\_ref_obj: (ALU_ADD_SUB), line:173
|vpiName:ALU_ADD_SUB
|vpiFullName:work@pre_decode.ALU_ADD_SUB
|vpiCaseItem:
\_case_item: , line:174
|vpiExpr:
\_ref_obj: (AND_fn3), line:174
|vpiName:AND_fn3
|vpiFullName:work@pre_decode.AND_fn3
|vpiStmt:
\_assignment: , line:174
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (data_in.alu_op), line:174
|vpiName:data_in.alu_op
|vpiFullName:work@pre_decode.data_in.alu_op
|vpiRhs:
\_ref_obj: (ALU_ADD_SUB), line:174
|vpiName:ALU_ADD_SUB
|vpiFullName:work@pre_decode.ALU_ADD_SUB
|vpiCaseItem:
\_case_item: , line:175
|vpiExpr:
\_ref_obj: (SRA_fn3), line:175
|vpiName:SRA_fn3
|vpiFullName:work@pre_decode.SRA_fn3
|vpiStmt:
\_assignment: , line:175
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (data_in.alu_op), line:175
|vpiName:data_in.alu_op
|vpiFullName:work@pre_decode.data_in.alu_op
|vpiRhs:
\_ref_obj: (ALU_RSHIFT), line:175
|vpiName:ALU_RSHIFT
|vpiFullName:work@pre_decode.ALU_RSHIFT
|vpiCaseItem:
\_case_item: , line:176
|vpiExpr:
\_ref_obj: (ADD_SUB_fn3), line:176
|vpiName:ADD_SUB_fn3
|vpiFullName:work@pre_decode.ADD_SUB_fn3
|vpiStmt:
\_assignment: , line:176
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (data_in.alu_op), line:176
|vpiName:data_in.alu_op
|vpiFullName:work@pre_decode.data_in.alu_op
|vpiRhs:
\_ref_obj: (ALU_ADD_SUB), line:176
|vpiName:ALU_ADD_SUB
|vpiFullName:work@pre_decode.ALU_ADD_SUB
|vpiStmt:
\_assignment: , line:179
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (data_in.alu_op), line:179
|vpiName:data_in.alu_op
|vpiFullName:work@pre_decode.data_in.alu_op
|vpiRhs:
\_operation: , line:179
|vpiOpType:32
|vpiOperand:
\_bit_select: (opcode), line:179
|vpiName:opcode
|vpiFullName:work@pre_decode.opcode
|vpiIndex:
\_constant: , line:179
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiOperand:
\_ref_obj: (ALU_ADD_SUB), line:179
|vpiName:ALU_ADD_SUB
|vpiFullName:work@pre_decode.ALU_ADD_SUB
|vpiOperand:
\_ref_obj: (data_in.alu_op), line:179
|vpiName:data_in.alu_op
|vpiFullName:work@pre_decode.data_in.alu_op
|vpiProcess:
\_always: , line:185
|vpiAlwaysType:2
|vpiStmt:
\_begin: , line:185
|vpiFullName:work@pre_decode
|vpiStmt:
\_if_else: , line:186
|vpiCondition:
\_operation: , line:186
|vpiOpType:95
|vpiOperand:
\_ref_obj: (opcode_trimmed), line:186
|vpiName:opcode_trimmed
|vpiFullName:work@pre_decode.opcode_trimmed
|vpiOperand:
\_ref_obj: (ARITH_T), line:186
|vpiName:ARITH_T
|vpiOperand:
\_ref_obj: (ARITH_IMM_T), line:186
|vpiName:ARITH_IMM_T
|vpiStmt:
\_assignment: , line:187
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (data_in.alu_rs1_sel), line:187
|vpiName:data_in.alu_rs1_sel
|vpiFullName:work@pre_decode.data_in.alu_rs1_sel
|vpiRhs:
\_ref_obj: (ALU_RS1_RF), line:187
|vpiName:ALU_RS1_RF
|vpiFullName:work@pre_decode.ALU_RS1_RF
|vpiElseStmt:
\_if_else: , line:188
|vpiCondition:
\_operation: , line:188
|vpiOpType:95
|vpiOperand:
\_ref_obj: (opcode_trimmed), line:188
|vpiName:opcode_trimmed
|vpiFullName:work@pre_decode.opcode_trimmed
|vpiOperand:
\_ref_obj: (JAL_T), line:188
|vpiName:JAL_T
|vpiOperand:
\_ref_obj: (JALR_T), line:188
|vpiName:JALR_T
|vpiOperand:
\_ref_obj: (AUIPC_T), line:188
|vpiName:AUIPC_T
|vpiStmt:
\_assignment: , line:189
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (data_in.alu_rs1_sel), line:189
|vpiName:data_in.alu_rs1_sel
|vpiFullName:work@pre_decode.data_in.alu_rs1_sel
|vpiRhs:
\_ref_obj: (ALU_RS1_PC), line:189
|vpiName:ALU_RS1_PC
|vpiFullName:work@pre_decode.ALU_RS1_PC
|vpiElseStmt:
\_assignment: , line:191
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (data_in.alu_rs1_sel), line:191
|vpiName:data_in.alu_rs1_sel
|vpiFullName:work@pre_decode.data_in.alu_rs1_sel
|vpiRhs:
\_ref_obj: (ALU_RS1_ZERO), line:191
|vpiName:ALU_RS1_ZERO
|vpiFullName:work@pre_decode.ALU_RS1_ZERO
|vpiProcess:
\_always: , line:194
|vpiAlwaysType:2
|vpiStmt:
\_begin: , line:194
|vpiFullName:work@pre_decode
|vpiStmt:
\_if_else: , line:195
|vpiCondition:
\_operation: , line:195
|vpiOpType:95
|vpiOperand:
\_ref_obj: (opcode_trimmed), line:195
|vpiName:opcode_trimmed
|vpiFullName:work@pre_decode.opcode_trimmed
|vpiOperand:
\_ref_obj: (LUI_T), line:195
|vpiName:LUI_T
|vpiOperand:
\_ref_obj: (AUIPC_T), line:195
|vpiName:AUIPC_T
|vpiStmt:
\_assignment: , line:196
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (data_in.alu_rs2_sel), line:196
|vpiName:data_in.alu_rs2_sel
|vpiFullName:work@pre_decode.data_in.alu_rs2_sel
|vpiRhs:
\_ref_obj: (ALU_RS2_LUI_AUIPC), line:196
|vpiName:ALU_RS2_LUI_AUIPC
|vpiFullName:work@pre_decode.ALU_RS2_LUI_AUIPC
|vpiElseStmt:
\_if_else: , line:197
|vpiCondition:
\_operation: , line:197
|vpiOpType:14
|vpiOperand:
\_ref_obj: (opcode_trimmed), line:197
|vpiName:opcode_trimmed
|vpiFullName:work@pre_decode.opcode_trimmed
|vpiOperand:
\_ref_obj: (ARITH_IMM_T), line:197
|vpiName:ARITH_IMM_T
|vpiFullName:work@pre_decode.ARITH_IMM_T
|vpiStmt:
\_assignment: , line:198
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (data_in.alu_rs2_sel), line:198
|vpiName:data_in.alu_rs2_sel
|vpiFullName:work@pre_decode.data_in.alu_rs2_sel
|vpiRhs:
\_ref_obj: (ALU_RS2_ARITH_IMM), line:198
|vpiName:ALU_RS2_ARITH_IMM
|vpiFullName:work@pre_decode.ALU_RS2_ARITH_IMM
|vpiElseStmt:
\_if_else: , line:199
|vpiCondition:
\_operation: , line:199
|vpiOpType:95
|vpiOperand:
\_ref_obj: (opcode_trimmed), line:199
|vpiName:opcode_trimmed
|vpiFullName:work@pre_decode.opcode_trimmed
|vpiOperand:
\_ref_obj: (JAL_T), line:199
|vpiName:JAL_T
|vpiOperand:
\_ref_obj: (JALR_T), line:199
|vpiName:JALR_T
|vpiStmt:
\_assignment: , line:200
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (data_in.alu_rs2_sel), line:200
|vpiName:data_in.alu_rs2_sel
|vpiFullName:work@pre_decode.data_in.alu_rs2_sel
|vpiRhs:
\_ref_obj: (ALU_RS2_JAL_JALR), line:200
|vpiName:ALU_RS2_JAL_JALR
|vpiFullName:work@pre_decode.ALU_RS2_JAL_JALR
|vpiElseStmt:
\_assignment: , line:202
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (data_in.alu_rs2_sel), line:202
|vpiName:data_in.alu_rs2_sel
|vpiFullName:work@pre_decode.data_in.alu_rs2_sel
|vpiRhs:
\_ref_obj: (ALU_RS2_RF), line:202
|vpiName:ALU_RS2_RF
|vpiFullName:work@pre_decode.ALU_RS2_RF
|vpiPort:
\_port: (clk), line:28
|vpiName:clk
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (clk), line:28
|vpiName:clk
|vpiFullName:work@pre_decode.clk
|vpiNetType:36
|vpiPort:
\_port: (rst), line:29
|vpiName:rst
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (rst), line:29
|vpiName:rst
|vpiFullName:work@pre_decode.rst
|vpiNetType:36
|vpiPort:
\_port: (pre_decode_instruction), line:32
|vpiName:pre_decode_instruction
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (pre_decode_instruction), line:32
|vpiName:pre_decode_instruction
|vpiFullName:work@pre_decode.pre_decode_instruction
|vpiNetType:36
|vpiPort:
\_port: (pre_decode_pc), line:33
|vpiName:pre_decode_pc
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (pre_decode_pc), line:33
|vpiName:pre_decode_pc
|vpiFullName:work@pre_decode.pre_decode_pc
|vpiNetType:36
|vpiPort:
\_port: (branch_metadata), line:34
|vpiName:branch_metadata
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (branch_metadata), line:34
|vpiName:branch_metadata
|vpiFullName:work@pre_decode.branch_metadata
|vpiPort:
\_port: (branch_prediction_used), line:35
|vpiName:branch_prediction_used
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (branch_prediction_used), line:35
|vpiName:branch_prediction_used
|vpiFullName:work@pre_decode.branch_prediction_used
|vpiNetType:36
|vpiPort:
\_port: (bp_update_way), line:36
|vpiName:bp_update_way
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (bp_update_way), line:36
|vpiName:bp_update_way
|vpiFullName:work@pre_decode.bp_update_way
|vpiNetType:36
|vpiPort:
\_port: (pre_decode_push), line:37
|vpiName:pre_decode_push
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (pre_decode_push), line:37
|vpiName:pre_decode_push
|vpiFullName:work@pre_decode.pre_decode_push
|vpiNetType:36
|vpiPort:
\_port: (gc_fetch_flush), line:40
|vpiName:gc_fetch_flush
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (gc_fetch_flush), line:40
|vpiName:gc_fetch_flush
|vpiFullName:work@pre_decode.gc_fetch_flush
|vpiNetType:36
|vpiPort:
\_port: (pre_decode_pop), line:43
|vpiName:pre_decode_pop
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (pre_decode_pop), line:43
|vpiName:pre_decode_pop
|vpiFullName:work@pre_decode.pre_decode_pop
|vpiNetType:36
|vpiPort:
\_port: (fb_valid), line:44
|vpiName:fb_valid
|vpiDirection:2
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (fb_valid), line:44
|vpiName:fb_valid
|vpiFullName:work@pre_decode.fb_valid
|vpiNetType:36
|vpiPort:
\_port: (fb), line:45
|vpiName:fb
|vpiDirection:2
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (fb), line:45
|vpiName:fb
|vpiFullName:work@pre_decode.fb
|vpiContAssign:
\_cont_assign: , line:71
|vpiRhs:
\_operation: , line:71
|vpiOpType:29
|vpiOperand:
\_ref_obj: (rst), line:71
|vpiName:rst
|vpiFullName:work@pre_decode.rst
|vpiOperand:
\_ref_obj: (gc_fetch_flush), line:71
|vpiName:gc_fetch_flush
|vpiFullName:work@pre_decode.gc_fetch_flush
|vpiLhs:
\_ref_obj: (buffer_reset), line:71
|vpiName:buffer_reset
|vpiFullName:work@pre_decode.buffer_reset
|vpiContAssign:
\_cont_assign: , line:72
|vpiRhs:
\_constant: , line:72
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiLhs:
\_ref_obj: (fb_fifo.supress_push), line:72
|vpiName:fb_fifo.supress_push
|vpiFullName:work@pre_decode.fb_fifo.supress_push
|vpiContAssign:
\_cont_assign: , line:74
|vpiRhs:
\_operation: , line:74
|vpiOpType:28
|vpiOperand:
\_ref_obj: (pre_decode_push), line:74
|vpiName:pre_decode_push
|vpiFullName:work@pre_decode.pre_decode_push
|vpiOperand:
\_operation: , line:74
|vpiOpType:29
|vpiOperand:
\_operation: , line:74
|vpiOpType:28
|vpiOperand:
\_ref_obj: (fb_valid), line:74
|vpiName:fb_valid
|vpiFullName:work@pre_decode.fb_valid
|vpiOperand:
\_operation: , line:74
|vpiOpType:4
|vpiOperand:
\_ref_obj: (pre_decode_pop), line:74
|vpiName:pre_decode_pop
|vpiFullName:work@pre_decode.pre_decode_pop
|vpiOperand:
\_ref_obj: (fb_fifo.valid), line:74
|vpiName:fb_fifo.valid
|vpiFullName:work@pre_decode.fb_fifo.valid
|vpiLhs:
\_ref_obj: (fb_fifo.push), line:74
|vpiName:fb_fifo.push
|vpiFullName:work@pre_decode.fb_fifo.push
|vpiContAssign:
\_cont_assign: , line:75
|vpiRhs:
\_operation: , line:75
|vpiOpType:28
|vpiOperand:
\_ref_obj: (pre_decode_pop), line:75
|vpiName:pre_decode_pop
|vpiFullName:work@pre_decode.pre_decode_pop
|vpiOperand:
\_ref_obj: (fb_fifo.valid), line:75
|vpiName:fb_fifo.valid
|vpiFullName:work@pre_decode.fb_fifo.valid
|vpiLhs:
\_ref_obj: (fb_fifo.pop), line:75
|vpiName:fb_fifo.pop
|vpiFullName:work@pre_decode.fb_fifo.pop
|vpiContAssign:
\_cont_assign: , line:76
|vpiRhs:
\_ref_obj: (data_in), line:76
|vpiName:data_in
|vpiFullName:work@pre_decode.data_in
|vpiLhs:
\_ref_obj: (fb_fifo.data_in), line:76
|vpiName:fb_fifo.data_in
|vpiFullName:work@pre_decode.fb_fifo.data_in
|vpiContAssign:
\_cont_assign: , line:77
|vpiRhs:
\_ref_obj: (fb_fifo.data_out), line:77
|vpiName:fb_fifo.data_out
|vpiFullName:work@pre_decode.fb_fifo.data_out
|vpiLhs:
\_ref_obj: (data_out), line:77
|vpiName:data_out
|vpiFullName:work@pre_decode.data_out
|vpiContAssign:
\_cont_assign: , line:79
|vpiRhs:
\_operation: , line:79
|vpiOpType:28
|vpiOperand:
\_ref_obj: (pre_decode_push), line:79
|vpiName:pre_decode_push
|vpiFullName:work@pre_decode.pre_decode_push
|vpiOperand:
\_operation: , line:80
|vpiOpType:29
|vpiOperand:
\_operation: , line:80
|vpiOpType:28
|vpiOperand:
\_operation: , line:80
|vpiOpType:28
|vpiOperand:
\_operation: , line:80
|vpiOpType:4
|vpiOperand:
\_ref_obj: (fb_fifo.valid), line:80
|vpiName:fb_fifo.valid
|vpiFullName:work@pre_decode.fb_fifo.valid
|vpiOperand:
\_ref_obj: (fb_valid), line:80
|vpiName:fb_valid
|vpiFullName:work@pre_decode.fb_valid
|vpiOperand:
\_ref_obj: (pre_decode_pop), line:80
|vpiName:pre_decode_pop
|vpiFullName:work@pre_decode.pre_decode_pop
|vpiOperand:
\_operation: , line:80
|vpiOpType:28
|vpiOperand:
\_operation: , line:80
|vpiOpType:4
|vpiOperand:
\_ref_obj: (fb_fifo.valid), line:80
|vpiName:fb_fifo.valid
|vpiFullName:work@pre_decode.fb_fifo.valid
|vpiOperand:
\_operation: , line:80
|vpiOpType:4
|vpiOperand:
\_ref_obj: (fb_valid), line:80
|vpiName:fb_valid
|vpiFullName:work@pre_decode.fb_valid
|vpiLhs:
\_ref_obj: (push_to_reg), line:79
|vpiName:push_to_reg
|vpiFullName:work@pre_decode.push_to_reg
|vpiContAssign:
\_cont_assign: , line:107
|vpiRhs:
\_ref_obj: (pre_decode_instruction), line:107
|vpiName:pre_decode_instruction
|vpiFullName:work@pre_decode.pre_decode_instruction
|vpiLhs:
\_ref_obj: (data_in.instruction), line:107
|vpiName:data_in.instruction
|vpiFullName:work@pre_decode.data_in.instruction
|vpiContAssign:
\_cont_assign: , line:108
|vpiRhs:
\_ref_obj: (pre_decode_pc), line:108
|vpiName:pre_decode_pc
|vpiFullName:work@pre_decode.pre_decode_pc
|vpiLhs:
\_ref_obj: (data_in.pc), line:108
|vpiName:data_in.pc
|vpiFullName:work@pre_decode.data_in.pc
|vpiContAssign:
\_cont_assign: , line:111
|vpiRhs:
\_part_select: , line:111, parent:pre_decode_instruction
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (pre_decode_instruction)
|vpiLeftRange:
\_constant: , line:111
|vpiConstType:7
|vpiDecompile:14
|vpiSize:32
|INT:14
|vpiRightRange:
\_constant: , line:111
|vpiConstType:7
|vpiDecompile:12
|vpiSize:32
|INT:12
|vpiLhs:
\_ref_obj: (fn3), line:111
|vpiName:fn3
|vpiFullName:work@pre_decode.fn3
|vpiContAssign:
\_cont_assign: , line:112
|vpiRhs:
\_part_select: , line:112, parent:pre_decode_instruction
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (pre_decode_instruction)
|vpiLeftRange:
\_constant: , line:112
|vpiConstType:7
|vpiDecompile:6
|vpiSize:32
|INT:6
|vpiRightRange:
\_constant: , line:112
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiLhs:
\_ref_obj: (opcode), line:112
|vpiName:opcode
|vpiFullName:work@pre_decode.opcode
|vpiContAssign:
\_cont_assign: , line:113
|vpiRhs:
\_part_select: , line:113, parent:opcode
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (opcode)
|vpiLeftRange:
\_constant: , line:113
|vpiConstType:7
|vpiDecompile:6
|vpiSize:32
|INT:6
|vpiRightRange:
\_constant: , line:113
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiLhs:
\_ref_obj: (opcode_trimmed), line:113
|vpiName:opcode_trimmed
|vpiFullName:work@pre_decode.opcode_trimmed
|vpiContAssign:
\_cont_assign: , line:115
|vpiRhs:
\_part_select: , line:115, parent:pre_decode_instruction
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (pre_decode_instruction)
|vpiLeftRange:
\_constant: , line:115
|vpiConstType:7
|vpiDecompile:19
|vpiSize:32
|INT:19
|vpiRightRange:
\_constant: , line:115
|vpiConstType:7
|vpiDecompile:15
|vpiSize:32
|INT:15
|vpiLhs:
\_ref_obj: (rs1_addr), line:115
|vpiName:rs1_addr
|vpiFullName:work@pre_decode.rs1_addr
|vpiContAssign:
\_cont_assign: , line:116
|vpiRhs:
\_part_select: , line:116, parent:pre_decode_instruction
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (pre_decode_instruction)
|vpiLeftRange:
\_constant: , line:116
|vpiConstType:7
|vpiDecompile:24
|vpiSize:32
|INT:24
|vpiRightRange:
\_constant: , line:116
|vpiConstType:7
|vpiDecompile:20
|vpiSize:32
|INT:20
|vpiLhs:
\_ref_obj: (rs2_addr), line:116
|vpiName:rs2_addr
|vpiFullName:work@pre_decode.rs2_addr
|vpiContAssign:
\_cont_assign: , line:117
|vpiRhs:
\_part_select: , line:117, parent:pre_decode_instruction
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (pre_decode_instruction)
|vpiLeftRange:
\_constant: , line:117
|vpiConstType:7
|vpiDecompile:11
|vpiSize:32
|INT:11
|vpiRightRange:
\_constant: , line:117
|vpiConstType:7
|vpiDecompile:7
|vpiSize:32
|INT:7
|vpiLhs:
\_ref_obj: (rd_addr), line:117
|vpiName:rd_addr
|vpiFullName:work@pre_decode.rd_addr
|vpiContAssign:
\_cont_assign: , line:119
|vpiRhs:
\_operation: , line:119
|vpiOpType:26
|vpiOperand:
\_operation: , line:119
|vpiOpType:14
|vpiOperand:
\_ref_obj: (opcode_trimmed), line:119
|vpiName:opcode_trimmed
|vpiFullName:work@pre_decode.opcode_trimmed
|vpiOperand:
\_ref_obj: (SYSTEM_T), line:119
|vpiName:SYSTEM_T
|vpiFullName:work@pre_decode.SYSTEM_T
|vpiOperand:
\_bit_select: (fn3), line:119
|vpiName:fn3
|vpiFullName:work@pre_decode.fn3
|vpiIndex:
\_constant: , line:119
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiLhs:
\_ref_obj: (csr_imm_op), line:119
|vpiName:csr_imm_op
|vpiFullName:work@pre_decode.csr_imm_op
|vpiContAssign:
\_cont_assign: , line:120
|vpiRhs:
\_operation: , line:120
|vpiOpType:26
|vpiOperand:
\_operation: , line:120
|vpiOpType:14
|vpiOperand:
\_ref_obj: (opcode_trimmed), line:120
|vpiName:opcode_trimmed
|vpiFullName:work@pre_decode.opcode_trimmed
|vpiOperand:
\_ref_obj: (SYSTEM_T), line:120
|vpiName:SYSTEM_T
|vpiFullName:work@pre_decode.SYSTEM_T
|vpiOperand:
\_operation: , line:120
|vpiOpType:14
|vpiOperand:
\_ref_obj: (fn3), line:120
|vpiName:fn3
|vpiFullName:work@pre_decode.fn3
|vpiOperand:
\_constant: , line:120
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiLhs:
\_ref_obj: (sys_op), line:120
|vpiName:sys_op
|vpiFullName:work@pre_decode.sys_op
|vpiContAssign:
\_cont_assign: , line:125
|vpiRhs:
\_operation: , line:125
|vpiOpType:95
|vpiOperand:
\_ref_obj: (rs1_addr), line:125
|vpiName:rs1_addr
|vpiFullName:work@pre_decode.rs1_addr
|vpiOperand:
\_constant: , line:125
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiOperand:
\_constant: , line:125
|vpiConstType:7
|vpiDecompile:5
|vpiSize:32
|INT:5
|vpiLhs:
\_ref_obj: (rs1_link), line:125
|vpiName:rs1_link
|vpiFullName:work@pre_decode.rs1_link
|vpiContAssign:
\_cont_assign: , line:126
|vpiRhs:
\_operation: , line:126
|vpiOpType:95
|vpiOperand:
\_ref_obj: (rd_addr), line:126
|vpiName:rd_addr
|vpiFullName:work@pre_decode.rd_addr
|vpiOperand:
\_constant: , line:126
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiOperand:
\_constant: , line:126
|vpiConstType:7
|vpiDecompile:5
|vpiSize:32
|INT:5
|vpiLhs:
\_ref_obj: (rd_link), line:126
|vpiName:rd_link
|vpiFullName:work@pre_decode.rd_link
|vpiContAssign:
\_cont_assign: , line:127
|vpiRhs:
\_operation: , line:127
|vpiOpType:14
|vpiOperand:
\_ref_obj: (rs1_addr), line:127
|vpiName:rs1_addr
|vpiFullName:work@pre_decode.rs1_addr
|vpiOperand:
\_ref_obj: (rd_addr), line:127
|vpiName:rd_addr
|vpiFullName:work@pre_decode.rd_addr
|vpiLhs:
\_ref_obj: (rs1_eq_rd), line:127
|vpiName:rs1_eq_rd
|vpiFullName:work@pre_decode.rs1_eq_rd
|vpiContAssign:
\_cont_assign: , line:128
|vpiRhs:
\_operation: , line:128
|vpiOpType:26
|vpiOperand:
\_operation: , line:128
|vpiOpType:14
|vpiOperand:
\_ref_obj: (opcode_trimmed), line:128
|vpiName:opcode_trimmed
|vpiFullName:work@pre_decode.opcode_trimmed
|vpiOperand:
\_ref_obj: (JALR_T), line:128
|vpiName:JALR_T
|vpiFullName:work@pre_decode.JALR_T
|vpiOperand:
\_operation: , line:128
|vpiOpType:29
|vpiOperand:
\_operation: , line:128
|vpiOpType:28
|vpiOperand:
\_ref_obj: (rs1_link), line:128
|vpiName:rs1_link
|vpiFullName:work@pre_decode.rs1_link
|vpiOperand:
\_operation: , line:128
|vpiOpType:4
|vpiOperand:
\_ref_obj: (rd_link), line:128
|vpiName:rd_link
|vpiFullName:work@pre_decode.rd_link
|vpiOperand:
\_operation: , line:128
|vpiOpType:28
|vpiOperand:
\_operation: , line:128
|vpiOpType:28
|vpiOperand:
\_ref_obj: (rs1_link), line:128
|vpiName:rs1_link
|vpiFullName:work@pre_decode.rs1_link
|vpiOperand:
\_ref_obj: (rd_link), line:128
|vpiName:rd_link
|vpiFullName:work@pre_decode.rd_link
|vpiOperand:
\_operation: , line:128
|vpiOpType:4
|vpiOperand:
\_ref_obj: (rs1_eq_rd), line:128
|vpiName:rs1_eq_rd
|vpiFullName:work@pre_decode.rs1_eq_rd
|vpiLhs:
\_ref_obj: (use_ras), line:128
|vpiName:use_ras
|vpiFullName:work@pre_decode.use_ras
|vpiContAssign:
\_cont_assign: , line:129
|vpiRhs:
\_ref_obj: (use_ras), line:129
|vpiName:use_ras
|vpiFullName:work@pre_decode.use_ras
|vpiLhs:
\_ref_obj: (data_in.is_return), line:129
|vpiName:data_in.is_return
|vpiFullName:work@pre_decode.data_in.is_return
|vpiContAssign:
\_cont_assign: , line:130
|vpiRhs:
\_operation: , line:130
|vpiOpType:26
|vpiOperand:
\_operation: , line:130
|vpiOpType:95
|vpiOperand:
\_ref_obj: (opcode_trimmed), line:130
|vpiName:opcode_trimmed
|vpiFullName:work@pre_decode.opcode_trimmed
|vpiOperand:
\_ref_obj: (JAL_T), line:130
|vpiName:JAL_T
|vpiOperand:
\_ref_obj: (JALR_T), line:130
|vpiName:JALR_T
|vpiOperand:
\_ref_obj: (rd_link), line:130
|vpiName:rd_link
|vpiFullName:work@pre_decode.rd_link
|vpiLhs:
\_ref_obj: (data_in.is_call), line:130
|vpiName:data_in.is_call
|vpiFullName:work@pre_decode.data_in.is_call
|vpiContAssign:
\_cont_assign: , line:134
|vpiRhs:
\_operation: , line:134
|vpiOpType:3
|vpiOperand:
\_operation: , line:134
|vpiOpType:27
|vpiOperand:
\_operation: , line:134
|vpiOpType:27
|vpiOperand:
\_operation: , line:134
|vpiOpType:95
|vpiOperand:
\_ref_obj: (opcode_trimmed), line:134
|vpiName:opcode_trimmed
|vpiFullName:work@pre_decode.opcode_trimmed
|vpiOperand:
\_ref_obj: (LUI_T), line:134
|vpiName:LUI_T
|vpiFullName:work@pre_decode.LUI_T
|vpiOperand:
\_ref_obj: (AUIPC_T), line:134
|vpiName:AUIPC_T
|vpiFullName:work@pre_decode.AUIPC_T
|vpiOperand:
\_ref_obj: (JAL_T), line:134
|vpiName:JAL_T
|vpiFullName:work@pre_decode.JAL_T
|vpiOperand:
\_ref_obj: (FENCE_T), line:134
|vpiName:FENCE_T
|vpiFullName:work@pre_decode.FENCE_T
|vpiOperand:
\_ref_obj: (csr_imm_op), line:134
|vpiName:csr_imm_op
|vpiFullName:work@pre_decode.csr_imm_op
|vpiOperand:
\_ref_obj: (sys_op), line:134
|vpiName:sys_op
|vpiFullName:work@pre_decode.sys_op
|vpiLhs:
\_ref_obj: (data_in.uses_rs1), line:134
|vpiName:data_in.uses_rs1
|vpiFullName:work@pre_decode.data_in.uses_rs1
|vpiContAssign:
\_cont_assign: , line:135
|vpiRhs:
\_operation: , line:135
|vpiOpType:95
|vpiOperand:
\_ref_obj: (opcode_trimmed), line:135
|vpiName:opcode_trimmed
|vpiFullName:work@pre_decode.opcode_trimmed
|vpiOperand:
\_ref_obj: (BRANCH_T), line:135
|vpiName:BRANCH_T
|vpiOperand:
\_ref_obj: (STORE_T), line:135
|vpiName:STORE_T
|vpiOperand:
\_ref_obj: (ARITH_T), line:135
|vpiName:ARITH_T
|vpiOperand:
\_ref_obj: (AMO_T), line:135
|vpiName:AMO_T
|vpiLhs:
\_ref_obj: (data_in.uses_rs2), line:135
|vpiName:data_in.uses_rs2
|vpiFullName:work@pre_decode.data_in.uses_rs2
|vpiContAssign:
\_cont_assign: , line:136
|vpiRhs:
\_operation: , line:136
|vpiOpType:3
|vpiOperand:
\_operation: , line:136
|vpiOpType:27
|vpiOperand:
\_operation: , line:136
|vpiOpType:95
|vpiOperand:
\_ref_obj: (opcode_trimmed), line:136
|vpiName:opcode_trimmed
|vpiFullName:work@pre_decode.opcode_trimmed
|vpiOperand:
\_ref_obj: (BRANCH_T), line:136
|vpiName:BRANCH_T
|vpiFullName:work@pre_decode.BRANCH_T
|vpiOperand:
\_ref_obj: (STORE_T), line:136
|vpiName:STORE_T
|vpiFullName:work@pre_decode.STORE_T
|vpiOperand:
\_ref_obj: (FENCE_T), line:136
|vpiName:FENCE_T
|vpiFullName:work@pre_decode.FENCE_T
|vpiOperand:
\_ref_obj: (sys_op), line:136
|vpiName:sys_op
|vpiFullName:work@pre_decode.sys_op
|vpiLhs:
\_ref_obj: (data_in.uses_rd), line:136
|vpiName:data_in.uses_rd
|vpiFullName:work@pre_decode.data_in.uses_rd
|vpiContAssign:
\_cont_assign: , line:140
|vpiRhs:
\_ref_obj: (branch_metadata), line:140
|vpiName:branch_metadata
|vpiFullName:work@pre_decode.branch_metadata
|vpiLhs:
\_ref_obj: (data_in.branch_metadata), line:140
|vpiName:data_in.branch_metadata
|vpiFullName:work@pre_decode.data_in.branch_metadata
|vpiContAssign:
\_cont_assign: , line:141
|vpiRhs:
\_ref_obj: (branch_prediction_used), line:141
|vpiName:branch_prediction_used
|vpiFullName:work@pre_decode.branch_prediction_used
|vpiLhs:
\_ref_obj: (data_in.branch_prediction_used), line:141
|vpiName:data_in.branch_prediction_used
|vpiFullName:work@pre_decode.data_in.branch_prediction_used
|vpiContAssign:
\_cont_assign: , line:142
|vpiRhs:
\_ref_obj: (bp_update_way), line:142
|vpiName:bp_update_way
|vpiFullName:work@pre_decode.bp_update_way
|vpiLhs:
\_ref_obj: (data_in.bp_update_way), line:142
|vpiName:data_in.bp_update_way
|vpiFullName:work@pre_decode.data_in.bp_update_way
|vpiContAssign:
\_cont_assign: , line:149
|vpiRhs:
\_operation: , line:149
|vpiOpType:26
|vpiOperand:
\_operation: , line:149
|vpiOpType:26
|vpiOperand:
\_operation: , line:149
|vpiOpType:14
|vpiOperand:
\_ref_obj: (fn3), line:149
|vpiName:fn3
|vpiFullName:work@pre_decode.fn3
|vpiOperand:
\_ref_obj: (ADD_SUB_fn3), line:149
|vpiName:ADD_SUB_fn3
|vpiFullName:work@pre_decode.ADD_SUB_fn3
|vpiOperand:
\_bit_select: (pre_decode_instruction), line:149
|vpiName:pre_decode_instruction
|vpiFullName:work@pre_decode.pre_decode_instruction
|vpiIndex:
\_constant: , line:149
|vpiConstType:7
|vpiDecompile:30
|vpiSize:32
|INT:30
|vpiOperand:
\_bit_select: (opcode), line:149
|vpiName:opcode
|vpiFullName:work@pre_decode.opcode
|vpiIndex:
\_constant: , line:149
|vpiConstType:7
|vpiDecompile:5
|vpiSize:32
|INT:5
|vpiLhs:
\_ref_obj: (sub_instruction), line:149
|vpiName:sub_instruction
|vpiFullName:work@pre_decode.sub_instruction
|vpiContAssign:
\_cont_assign: , line:150
|vpiRhs:
\_operation: , line:150
|vpiOpType:28
|vpiOperand:
\_operation: , line:150
|vpiOpType:4
|vpiOperand:
\_bit_select: (opcode), line:150
|vpiName:opcode
|vpiIndex:
\_constant: , line:150
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiOperand:
\_operation: , line:150
|vpiOpType:27
|vpiOperand:
\_operation: , line:150
|vpiOpType:95
|vpiOperand:
\_ref_obj: (fn3), line:150
|vpiName:fn3
|vpiFullName:work@pre_decode.fn3
|vpiOperand:
\_ref_obj: (SLTU_fn3), line:150
|vpiName:SLTU_fn3
|vpiFullName:work@pre_decode.SLTU_fn3
|vpiOperand:
\_ref_obj: (SLT_fn3), line:150
|vpiName:SLT_fn3
|vpiFullName:work@pre_decode.SLT_fn3
|vpiOperand:
\_ref_obj: (sub_instruction), line:150
|vpiName:sub_instruction
|vpiFullName:work@pre_decode.sub_instruction
|vpiLhs:
\_ref_obj: (data_in.alu_sub), line:150
|vpiName:data_in.alu_sub
|vpiFullName:work@pre_decode.data_in.alu_sub
|vpiContAssign:
\_cont_assign: , line:183
|vpiRhs:
\_operation: , line:183
|vpiOpType:26
|vpiOperand:
\_operation: , line:183
|vpiOpType:14
|vpiOperand:
\_ref_obj: (opcode_trimmed), line:183
|vpiName:opcode_trimmed
|vpiFullName:work@pre_decode.opcode_trimmed
|vpiOperand:
\_ref_obj: (ARITH_T), line:183
|vpiName:ARITH_T
|vpiFullName:work@pre_decode.ARITH_T
|vpiOperand:
\_operation: , line:183
|vpiOpType:4
|vpiOperand:
\_bit_select: (pre_decode_instruction), line:183
|vpiName:pre_decode_instruction
|vpiIndex:
\_constant: , line:183
|vpiConstType:7
|vpiDecompile:25
|vpiSize:32
|INT:25
|vpiLhs:
\_ref_obj: (non_mul_div_arith_op), line:183
|vpiName:non_mul_div_arith_op
|vpiFullName:work@pre_decode.non_mul_div_arith_op
|vpiContAssign:
\_cont_assign: , line:184
|vpiRhs:
\_operation: , line:184
|vpiOpType:27
|vpiOperand:
\_ref_obj: (non_mul_div_arith_op), line:184
|vpiName:non_mul_div_arith_op
|vpiFullName:work@pre_decode.non_mul_div_arith_op
|vpiOperand:
\_operation: , line:184
|vpiOpType:95
|vpiOperand:
\_ref_obj: (opcode_trimmed), line:184
|vpiName:opcode_trimmed
|vpiFullName:work@pre_decode.opcode_trimmed
|vpiOperand:
\_ref_obj: (ARITH_IMM_T), line:184
|vpiName:ARITH_IMM_T
|vpiFullName:work@pre_decode.ARITH_IMM_T
|vpiOperand:
\_ref_obj: (AUIPC_T), line:184
|vpiName:AUIPC_T
|vpiFullName:work@pre_decode.AUIPC_T
|vpiOperand:
\_ref_obj: (LUI_T), line:184
|vpiName:LUI_T
|vpiFullName:work@pre_decode.LUI_T
|vpiOperand:
\_ref_obj: (JAL_T), line:184
|vpiName:JAL_T
|vpiFullName:work@pre_decode.JAL_T
|vpiOperand:
\_ref_obj: (JALR_T), line:184
|vpiName:JALR_T
|vpiFullName:work@pre_decode.JALR_T
|vpiLhs:
\_ref_obj: (data_in.alu_request), line:184
|vpiName:data_in.alu_request
|vpiFullName:work@pre_decode.data_in.alu_request
|vpiNet:
\_logic_net: (clk), line:28
|vpiNet:
\_logic_net: (rst), line:29
|vpiNet:
\_logic_net: (pre_decode_instruction), line:32
|vpiNet:
\_logic_net: (pre_decode_pc), line:33
|vpiNet:
\_logic_net: (branch_metadata), line:34
|vpiNet:
\_logic_net: (branch_prediction_used), line:35
|vpiNet:
\_logic_net: (bp_update_way), line:36
|vpiNet:
\_logic_net: (pre_decode_push), line:37
|vpiNet:
\_logic_net: (gc_fetch_flush), line:40
|vpiNet:
\_logic_net: (pre_decode_pop), line:43
|vpiNet:
\_logic_net: (fb_valid), line:44
|vpiNet:
\_logic_net: (fb), line:45
|vpiNet:
\_logic_net: (buffer_reset), line:48
|vpiName:buffer_reset
|vpiFullName:work@pre_decode.buffer_reset
|vpiNetType:36
|vpiNet:
\_logic_net: (opcode), line:50
|vpiName:opcode
|vpiFullName:work@pre_decode.opcode
|vpiNetType:36
|vpiNet:
\_logic_net: (opcode_trimmed), line:51
|vpiName:opcode_trimmed
|vpiFullName:work@pre_decode.opcode_trimmed
|vpiNetType:36
|vpiNet:
\_logic_net: (rs1_addr), line:52
|vpiName:rs1_addr
|vpiFullName:work@pre_decode.rs1_addr
|vpiNetType:36
|vpiNet:
\_logic_net: (rs2_addr), line:53
|vpiName:rs2_addr
|vpiFullName:work@pre_decode.rs2_addr
|vpiNetType:36
|vpiNet:
\_logic_net: (rd_addr), line:54
|vpiName:rd_addr
|vpiFullName:work@pre_decode.rd_addr
|vpiNetType:36
|vpiNet:
\_logic_net: (fn3), line:55
|vpiName:fn3
|vpiFullName:work@pre_decode.fn3
|vpiNetType:36
|vpiNet:
\_logic_net: (csr_imm_op), line:57
|vpiName:csr_imm_op
|vpiFullName:work@pre_decode.csr_imm_op
|vpiNetType:36
|vpiNet:
\_logic_net: (sys_op), line:58
|vpiName:sys_op
|vpiFullName:work@pre_decode.sys_op
|vpiNetType:36
|vpiNet:
\_logic_net: (rs1_link), line:60
|vpiName:rs1_link
|vpiFullName:work@pre_decode.rs1_link
|vpiNetType:36
|vpiNet:
\_logic_net: (rd_link), line:60
|vpiName:rd_link
|vpiFullName:work@pre_decode.rd_link
|vpiNetType:36
|vpiNet:
\_logic_net: (rs1_eq_rd), line:60
|vpiName:rs1_eq_rd
|vpiFullName:work@pre_decode.rs1_eq_rd
|vpiNetType:36
|vpiNet:
\_logic_net: (use_ras), line:60
|vpiName:use_ras
|vpiFullName:work@pre_decode.use_ras
|vpiNetType:36
|vpiNet:
\_logic_net: (push_to_reg), line:62
|vpiName:push_to_reg
|vpiFullName:work@pre_decode.push_to_reg
|vpiNetType:36
|vpiNet:
\_logic_net: (data_in), line:64
|vpiName:data_in
|vpiFullName:work@pre_decode.data_in
|vpiNet:
\_logic_net: (data_out), line:65
|vpiName:data_out
|vpiFullName:work@pre_decode.data_out
|vpiNet:
\_logic_net: (sub_instruction), line:148
|vpiName:sub_instruction
|vpiFullName:work@pre_decode.sub_instruction
|vpiNetType:36
|vpiNet:
\_logic_net: (non_mul_div_arith_op), line:182
|vpiName:non_mul_div_arith_op
|vpiFullName:work@pre_decode.non_mul_div_arith_op
|vpiNetType:36
|vpiTypedef:
\_struct_typespec: (alu_inputs_t), line:301
|vpiTypedef:
\_enum_typespec: (alu_logic_op_t), line:84
|vpiTypedef:
\_enum_typespec: (alu_op_t), line:91
|vpiTypedef:
\_enum_typespec: (alu_rs1_op_t), line:97
|vpiTypedef:
\_enum_typespec: (alu_rs2_op_t), line:104
|vpiTypedef:
\_struct_typespec: (amo_alu_inputs_t), line:356
|vpiTypedef:
\_struct_typespec: (amo_details_t), line:362
|vpiTypedef:
\_enum_typespec: (amo_t), line:354
|vpiTypedef:
\_struct_typespec: (branch_inputs_t), line:313
|vpiTypedef:
\_logic_typespec: (branch_predictor_metadata_t), line:32
|vpiTypedef:
\_struct_typespec: (branch_results_t), line:330
|vpiTypedef:
\_enum_typespec: (bus_type_t), line:86
|vpiTypedef:
\_struct_typespec: (csr_inputs_t), line:396
|vpiTypedef:
\_enum_typespec: (csr_op_t), line:218
|vpiTypedef:
\_enum_typespec: (csr_t), line:201
|vpiTypedef:
\_struct_typespec: (data_access_shared_inputs_t), line:427
|vpiTypedef:
\_struct_typespec: (div_inputs_t), line:389
|vpiTypedef:
\_enum_typespec: (div_type), line:66
|vpiTypedef:
\_enum_typespec: (exception_code_t), line:245
|vpiTypedef:
\_struct_typespec: (exception_packet_t), line:263
|vpiTypedef:
\_struct_typespec: (fetch_buffer_packet_t), line:276
|vpiTypedef:
\_enum_typespec: (fifo_type_t), line:440
|vpiTypedef:
\_enum_typespec: (fn3_arith_t), line:76
|vpiTypedef:
\_enum_typespec: (fn3_branch_t), line:126
|vpiTypedef:
\_enum_typespec: (fn3_csr_t), line:212
|vpiTypedef:
\_enum_typespec: (fn3_ls_t), line:115
|vpiTypedef:
\_enum_typespec: (fn3_mul_div_t), line:138
|vpiTypedef:
\_struct_typespec: (gc_inputs_t), line:404
|vpiTypedef:
\_struct_typespec: (inflight_instruction_packet), line:271
|vpiTypedef:
\_logic_typespec: (instruction_id_t), line:30
|vpiTypedef:
\_enum_typespec: (interrupt_code_t), line:261
|vpiTypedef:
\_struct_typespec: (load_store_inputs_t), line:369
|vpiTypedef:
\_struct_typespec: (mul_inputs_t), line:383
|vpiTypedef:
\_enum_typespec: (opcodes_t), line:48
|vpiTypedef:
\_enum_typespec: (opcodes_trimmed_t), line:65
|vpiTypedef:
\_struct_typespec: (simulation_named_regfile), line:476
|vpiTypedef:
\_struct_typespec: (taiga_trace_events_t), line:442
|vpiTypedef:
\_struct_typespec: (to_l1_arbiter_packet), line:418
|vpiTypedef:
\_struct_typespec: (trace_outputs_t), line:469
|vpiTypedef:
\_logic_typespec: (unit_id_t), line:31
|vpiTypedef:
\_struct_typespec: (unit_writeback_t), line:295
|vpiTypedef:
\_enum_typespec: (vm_t), line:223
|uhdmallModules:
\_module: work@ras, file:third_party/cores/taiga/core/ras.sv, line:26, parent:work@div_unit_core_wrapper
|vpiDefName:work@ras
|vpiFullName:work@ras
|vpiProcess:
\_initial:
|vpiStmt:
\_for_stmt: , line:42
|vpiFullName:work@ras
|vpiCondition:
\_operation: , line:42
|vpiOpType:20
|vpiOperand:
\_ref_obj: (i), line:42
|vpiName:i
|vpiFullName:work@ras.i
|vpiOperand:
\_ref_obj: (RAS_DEPTH), line:42
|vpiName:RAS_DEPTH
|vpiFullName:work@ras.RAS_DEPTH
|vpiForInitStmt:
\_assign_stmt:
|vpiRhs:
\_constant: , line:42
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiLhs:
\_int_var: (i), line:42
|vpiName:i
|vpiFullName:work@ras.i
|vpiForIncStmt:
\_operation: , line:42
|vpiOpType:62
|vpiOperand:
\_ref_obj: (i), line:42
|vpiName:i
|vpiStmt:
\_begin: , line:42
|vpiFullName:work@ras
|vpiStmt:
\_assignment: , line:43
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_bit_select: (lut_ram), line:43
|vpiName:lut_ram
|vpiFullName:work@ras.lut_ram
|vpiIndex:
\_ref_obj: (i), line:43
|vpiName:i
|vpiRhs:
\_constant: , line:43
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiStmt:
\_assignment: , line:44
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_bit_select: (valid_chain), line:44
|vpiName:valid_chain
|vpiFullName:work@ras.valid_chain
|vpiIndex:
\_ref_obj: (i), line:44
|vpiName:i
|vpiRhs:
\_constant: , line:44
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiProcess:
\_always: , line:50
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:50
|vpiCondition:
\_operation: , line:50
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:50
|vpiName:clk
|vpiFullName:work@ras.clk
|vpiStmt:
\_begin: , line:50
|vpiFullName:work@ras
|vpiStmt:
\_if_stmt: , line:51
|vpiCondition:
\_ref_obj: (ras.push), line:51
|vpiName:ras.push
|vpiFullName:work@ras.ras.push
|vpiStmt:
\_assignment: , line:52
|vpiOpType:82
|vpiLhs:
\_bit_select: (lut_ram), line:52
|vpiName:lut_ram
|vpiFullName:work@ras.lut_ram
|vpiIndex:
\_ref_obj: (write_index), line:52
|vpiName:write_index
|vpiRhs:
\_ref_obj: (ras.new_addr), line:52
|vpiName:ras.new_addr
|vpiFullName:work@ras.ras.new_addr
|vpiProcess:
\_always: , line:57
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:57
|vpiCondition:
\_operation: , line:57
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:57
|vpiName:clk
|vpiFullName:work@ras.clk
|vpiStmt:
\_begin: , line:57
|vpiFullName:work@ras
|vpiStmt:
\_if_else: , line:58
|vpiCondition:
\_ref_obj: (rst), line:58
|vpiName:rst
|vpiFullName:work@ras.rst
|vpiStmt:
\_assignment: , line:59
|vpiOpType:82
|vpiLhs:
\_ref_obj: (read_index), line:59
|vpiName:read_index
|vpiFullName:work@ras.read_index
|vpiRhs:
\_constant: , line:59
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiElseStmt:
\_if_else: , line:60
|vpiCondition:
\_operation: , line:60
|vpiOpType:28
|vpiOperand:
\_ref_obj: (ras.push), line:60
|vpiName:ras.push
|vpiFullName:work@ras.ras.push
|vpiOperand:
\_operation: , line:60
|vpiOpType:4
|vpiOperand:
\_ref_obj: (ras.pop), line:60
|vpiName:ras.pop
|vpiFullName:work@ras.ras.pop
|vpiStmt:
\_assignment: , line:61
|vpiOpType:82
|vpiLhs:
\_ref_obj: (read_index), line:61
|vpiName:read_index
|vpiFullName:work@ras.read_index
|vpiRhs:
\_ref_obj: (write_index), line:61
|vpiName:write_index
|vpiFullName:work@ras.write_index
|vpiElseStmt:
\_if_stmt: , line:62
|vpiCondition:
\_operation: , line:62
|vpiOpType:28
|vpiOperand:
\_ref_obj: (ras.pop), line:62
|vpiName:ras.pop
|vpiFullName:work@ras.ras.pop
|vpiOperand:
\_operation: , line:62
|vpiOpType:4
|vpiOperand:
\_ref_obj: (ras.push), line:62
|vpiName:ras.push
|vpiFullName:work@ras.ras.push
|vpiStmt:
\_assignment: , line:63
|vpiOpType:82
|vpiLhs:
\_ref_obj: (read_index), line:63
|vpiName:read_index
|vpiFullName:work@ras.read_index
|vpiRhs:
\_operation: , line:63
|vpiOpType:11
|vpiOperand:
\_ref_obj: (read_index), line:63
|vpiName:read_index
|vpiFullName:work@ras.read_index
|vpiOperand:
\_constant: , line:63
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiProcess:
\_always: , line:68
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:68
|vpiCondition:
\_operation: , line:68
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:68
|vpiName:clk
|vpiFullName:work@ras.clk
|vpiStmt:
\_begin: , line:68
|vpiFullName:work@ras
|vpiStmt:
\_if_stmt: , line:69
|vpiCondition:
\_ref_obj: (valid_chain_update), line:69
|vpiName:valid_chain_update
|vpiFullName:work@ras.valid_chain_update
|vpiStmt:
\_assignment: , line:70
|vpiOpType:82
|vpiLhs:
\_bit_select: (valid_chain), line:70
|vpiName:valid_chain
|vpiFullName:work@ras.valid_chain
|vpiIndex:
\_ref_obj: (write_index), line:70
|vpiName:write_index
|vpiRhs:
\_ref_obj: (ras.push), line:70
|vpiName:ras.push
|vpiFullName:work@ras.ras.push
|vpiPort:
\_port: (clk), line:27
|vpiName:clk
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (clk), line:27
|vpiName:clk
|vpiFullName:work@ras.clk
|vpiNetType:36
|vpiPort:
\_port: (rst), line:28
|vpiName:rst
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (rst), line:28
|vpiName:rst
|vpiFullName:work@ras.rst
|vpiNetType:36
|vpiPort:
\_port: (ras), line:29
|vpiName:ras
|vpiDirection:5
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_modport: (self)
|vpiContAssign:
\_cont_assign: , line:47
|vpiRhs:
\_bit_select: (lut_ram), line:47
|vpiName:lut_ram
|vpiFullName:work@ras.lut_ram
|vpiIndex:
\_ref_obj: (read_index), line:47
|vpiName:read_index
|vpiLhs:
\_ref_obj: (ras.addr), line:47
|vpiName:ras.addr
|vpiFullName:work@ras.ras.addr
|vpiContAssign:
\_cont_assign: , line:48
|vpiRhs:
\_bit_select: (valid_chain), line:48
|vpiName:valid_chain
|vpiFullName:work@ras.valid_chain
|vpiIndex:
\_ref_obj: (read_index), line:48
|vpiName:read_index
|vpiLhs:
\_ref_obj: (ras.valid), line:48
|vpiName:ras.valid
|vpiFullName:work@ras.ras.valid
|vpiContAssign:
\_cont_assign: , line:65
|vpiRhs:
\_operation: , line:65
|vpiOpType:32
|vpiOperand:
\_operation: , line:65
|vpiOpType:28
|vpiOperand:
\_ref_obj: (ras.push), line:65
|vpiName:ras.push
|vpiFullName:work@ras.ras.push
|vpiOperand:
\_operation: , line:65
|vpiOpType:4
|vpiOperand:
\_ref_obj: (ras.pop), line:65
|vpiName:ras.pop
|vpiFullName:work@ras.ras.pop
|vpiOperand:
\_operation: , line:65
|vpiOpType:24
|vpiOperand:
\_ref_obj: (read_index), line:65
|vpiName:read_index
|vpiFullName:work@ras.read_index
|vpiOperand:
\_operation: , line:65
|vpiOpType:67
|vpiOperand:
\_bit_select: (valid_chain), line:65
|vpiName:valid_chain
|vpiIndex:
\_ref_obj: (read_index), line:65
|vpiName:read_index
|vpiFullName:work@ras.read_index
|vpiTypespec:
\_void_typespec: (RAS_DEPTH_W), line:65
|vpiName:RAS_DEPTH_W
|vpiOperand:
\_ref_obj: (read_index), line:65
|vpiName:read_index
|vpiFullName:work@ras.read_index
|vpiLhs:
\_ref_obj: (write_index), line:65
|vpiName:write_index
|vpiFullName:work@ras.write_index
|vpiContAssign:
\_cont_assign: , line:67
|vpiRhs:
\_operation: , line:67
|vpiOpType:29
|vpiOperand:
\_ref_obj: (ras.push), line:67
|vpiName:ras.push
|vpiFullName:work@ras.ras.push
|vpiOperand:
\_ref_obj: (ras.pop), line:67
|vpiName:ras.pop
|vpiFullName:work@ras.ras.pop
|vpiLhs:
\_ref_obj: (valid_chain_update), line:67
|vpiName:valid_chain_update
|vpiFullName:work@ras.valid_chain_update
|vpiNet:
\_logic_net: (clk), line:27
|vpiNet:
\_logic_net: (rst), line:28
|vpiNet:
\_logic_net: (lut_ram), line:32
|vpiName:lut_ram
|vpiFullName:work@ras.lut_ram
|vpiNetType:36
|vpiNet:
\_logic_net: (read_index), line:35
|vpiName:read_index
|vpiFullName:work@ras.read_index
|vpiNetType:36
|vpiNet:
\_logic_net: (write_index), line:36
|vpiName:write_index
|vpiFullName:work@ras.write_index
|vpiNetType:36
|vpiNet:
\_logic_net: (valid_chain), line:37
|vpiName:valid_chain
|vpiFullName:work@ras.valid_chain
|vpiNetType:36
|vpiNet:
\_logic_net: (valid_chain_update), line:38
|vpiName:valid_chain_update
|vpiFullName:work@ras.valid_chain_update
|vpiNetType:36
|vpiNet:
\_logic_net: (ras), line:29
|vpiName:ras
|vpiFullName:work@ras.ras
|vpiTypedef:
\_struct_typespec: (alu_inputs_t), line:301
|vpiTypedef:
\_enum_typespec: (alu_logic_op_t), line:84
|vpiTypedef:
\_enum_typespec: (alu_op_t), line:91
|vpiTypedef:
\_enum_typespec: (alu_rs1_op_t), line:97
|vpiTypedef:
\_enum_typespec: (alu_rs2_op_t), line:104
|vpiTypedef:
\_struct_typespec: (amo_alu_inputs_t), line:356
|vpiTypedef:
\_struct_typespec: (amo_details_t), line:362
|vpiTypedef:
\_enum_typespec: (amo_t), line:354
|vpiTypedef:
\_struct_typespec: (branch_inputs_t), line:313
|vpiTypedef:
\_logic_typespec: (branch_predictor_metadata_t), line:32
|vpiTypedef:
\_struct_typespec: (branch_results_t), line:330
|vpiTypedef:
\_enum_typespec: (bus_type_t), line:86
|vpiTypedef:
\_struct_typespec: (csr_inputs_t), line:396
|vpiTypedef:
\_enum_typespec: (csr_op_t), line:218
|vpiTypedef:
\_enum_typespec: (csr_t), line:201
|vpiTypedef:
\_struct_typespec: (data_access_shared_inputs_t), line:427
|vpiTypedef:
\_struct_typespec: (div_inputs_t), line:389
|vpiTypedef:
\_enum_typespec: (div_type), line:66
|vpiTypedef:
\_enum_typespec: (exception_code_t), line:245
|vpiTypedef:
\_struct_typespec: (exception_packet_t), line:263
|vpiTypedef:
\_struct_typespec: (fetch_buffer_packet_t), line:276
|vpiTypedef:
\_enum_typespec: (fifo_type_t), line:440
|vpiTypedef:
\_enum_typespec: (fn3_arith_t), line:76
|vpiTypedef:
\_enum_typespec: (fn3_branch_t), line:126
|vpiTypedef:
\_enum_typespec: (fn3_csr_t), line:212
|vpiTypedef:
\_enum_typespec: (fn3_ls_t), line:115
|vpiTypedef:
\_enum_typespec: (fn3_mul_div_t), line:138
|vpiTypedef:
\_struct_typespec: (gc_inputs_t), line:404
|vpiTypedef:
\_struct_typespec: (inflight_instruction_packet), line:271
|vpiTypedef:
\_logic_typespec: (instruction_id_t), line:30
|vpiTypedef:
\_enum_typespec: (interrupt_code_t), line:261
|vpiTypedef:
\_struct_typespec: (load_store_inputs_t), line:369
|vpiTypedef:
\_struct_typespec: (mul_inputs_t), line:383
|vpiTypedef:
\_enum_typespec: (opcodes_t), line:48
|vpiTypedef:
\_enum_typespec: (opcodes_trimmed_t), line:65
|vpiTypedef:
\_struct_typespec: (simulation_named_regfile), line:476
|vpiTypedef:
\_struct_typespec: (taiga_trace_events_t), line:442
|vpiTypedef:
\_struct_typespec: (to_l1_arbiter_packet), line:418
|vpiTypedef:
\_struct_typespec: (trace_outputs_t), line:469
|vpiTypedef:
\_logic_typespec: (unit_id_t), line:31
|vpiTypedef:
\_struct_typespec: (unit_writeback_t), line:295
|vpiTypedef:
\_enum_typespec: (vm_t), line:223
|vpiParamAssign:
\_param_assign: , line:34
|vpiRhs:
\_sys_func_call: ($clog2), line:34
|vpiName:$clog2
|vpiArgument:
\_ref_obj: (RAS_DEPTH), line:34
|vpiName:RAS_DEPTH
|vpiLhs:
\_parameter: (RAS_DEPTH_W), line:34
|vpiName:RAS_DEPTH_W
|vpiLocalParam:1
|vpiParameter:
\_parameter: (RAS_DEPTH_W), line:34
|uhdmallModules:
\_module: work@register_file, file:third_party/cores/taiga/core/register_file.sv, line:26, parent:work@div_unit_core_wrapper
|vpiDefName:work@register_file
|vpiFullName:work@register_file
|vpiProcess:
\_initial:
|vpiStmt:
\_begin: , line:54
|vpiFullName:work@register_file
|vpiStmt:
\_for_stmt: , line:55
|vpiFullName:work@register_file
|vpiCondition:
\_operation: , line:55
|vpiOpType:20
|vpiOperand:
\_ref_obj: (i), line:55
|vpiName:i
|vpiFullName:work@register_file.i
|vpiOperand:
\_constant: , line:55
|vpiConstType:7
|vpiDecompile:32
|vpiSize:32
|INT:32
|vpiForInitStmt:
\_assign_stmt:
|vpiRhs:
\_constant: , line:55
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiLhs:
\_int_var: (i), line:55
|vpiName:i
|vpiFullName:work@register_file.i
|vpiForIncStmt:
\_operation: , line:55
|vpiOpType:62
|vpiOperand:
\_ref_obj: (i), line:55
|vpiName:i
|vpiStmt:
\_begin: , line:55
|vpiFullName:work@register_file
|vpiStmt:
\_assignment: , line:56
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_bit_select: (register), line:56
|vpiName:register
|vpiFullName:work@register_file.register
|vpiIndex:
\_ref_obj: (i), line:56
|vpiName:i
|vpiRhs:
\_constant: , line:56
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiStmt:
\_assignment: , line:57
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_bit_select: (in_use_by), line:57
|vpiName:in_use_by
|vpiFullName:work@register_file.in_use_by
|vpiIndex:
\_ref_obj: (i), line:57
|vpiName:i
|vpiRhs:
\_constant: , line:57
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiProcess:
\_always: , line:62
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:62
|vpiCondition:
\_operation: , line:62
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:62
|vpiName:clk
|vpiFullName:work@register_file.clk
|vpiStmt:
\_begin: , line:62
|vpiFullName:work@register_file
|vpiStmt:
\_if_stmt: , line:63
|vpiCondition:
\_operation: , line:63
|vpiOpType:28
|vpiOperand:
\_operation: , line:63
|vpiOpType:4
|vpiOperand:
\_ref_obj: (gc_supress_writeback), line:63
|vpiName:gc_supress_writeback
|vpiFullName:work@register_file.gc_supress_writeback
|vpiOperand:
\_ref_obj: (valid_write), line:63
|vpiName:valid_write
|vpiFullName:work@register_file.valid_write
|vpiStmt:
\_assignment: , line:64
|vpiOpType:82
|vpiLhs:
\_bit_select: (register), line:64
|vpiName:register
|vpiFullName:work@register_file.register
|vpiIndex:
\_ref_obj: (rf_wb.rd_addr), line:64
|vpiName:rf_wb.rd_addr
|vpiRhs:
\_ref_obj: (rf_wb.rd_data), line:64
|vpiName:rf_wb.rd_data
|vpiFullName:work@register_file.rf_wb.rd_data
|vpiProcess:
\_always: , line:77
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:77
|vpiCondition:
\_operation: , line:77
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:77
|vpiName:clk
|vpiFullName:work@register_file.clk
|vpiStmt:
\_begin: , line:77
|vpiFullName:work@register_file
|vpiStmt:
\_if_stmt: , line:78
|vpiCondition:
\_ref_obj: (rf_decode.instruction_issued), line:78
|vpiName:rf_decode.instruction_issued
|vpiFullName:work@register_file.rf_decode.instruction_issued
|vpiStmt:
\_assignment: , line:79
|vpiOpType:82
|vpiLhs:
\_bit_select: (in_use_by), line:79
|vpiName:in_use_by
|vpiFullName:work@register_file.in_use_by
|vpiIndex:
\_ref_obj: (rf_decode.future_rd_addr), line:79
|vpiName:rf_decode.future_rd_addr
|vpiRhs:
\_ref_obj: (rf_decode.id), line:79
|vpiName:rf_decode.id
|vpiFullName:work@register_file.rf_decode.id
|vpiProcess:
\_always: , line:103
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:103
|vpiCondition:
\_operation: , line:103
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:103
|vpiName:clk
|vpiFullName:work@register_file.clk
|vpiStmt:
\_begin: , line:103
|vpiFullName:work@register_file
|vpiStmt:
\_immediate_assert: , line:104
|vpiExpr:
\_operation: , line:104
|vpiOpType:3
|vpiOperand:
\_operation: , line:104
|vpiOpType:26
|vpiOperand:
\_ref_obj: (rf_decode.instruction_issued), line:104
|vpiName:rf_decode.instruction_issued
|vpiFullName:work@register_file.rf_decode.instruction_issued
|vpiOperand:
\_operation: , line:104
|vpiOpType:14
|vpiOperand:
\_ref_obj: (rf_decode.future_rd_addr), line:104
|vpiName:rf_decode.future_rd_addr
|vpiFullName:work@register_file.rf_decode.future_rd_addr
|vpiOperand:
\_constant: , line:104
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiElseStmt:
\_sys_func_call: ($error), line:104
|vpiName:$error
|vpiArgument:
\_constant: , line:104
|vpiConstType:6
|vpiDecompile:"Write to inuse for register x0 occured!"
|vpiSize:41
|STRING:"Write to inuse for register x0 occured!"
|vpiProcess:
\_always: , line:112
|vpiAlwaysType:2
|vpiStmt:
\_begin: , line:112
|vpiFullName:work@register_file
|vpiStmt:
\_foreach_stmt: , line:113
|vpiFullName:work@register_file
|vpiVariables:
\_chandle_var: (register), line:113
|vpiName:register
|vpiFullName:work@register_file.register
|vpiLoopVars:
\_chandle_var: (i), line:113
|vpiName:i
|vpiFullName:work@register_file.i
|vpiStmt:
\_assignment: , line:114
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_bit_select: (sim_registers_unamed), line:114
|vpiName:sim_registers_unamed
|vpiFullName:work@register_file.sim_registers_unamed
|vpiIndex:
\_ref_obj: (i), line:114
|vpiName:i
|vpiRhs:
\_bit_select: (register), line:114
|vpiName:register
|vpiFullName:work@register_file.register
|vpiIndex:
\_ref_obj: (i), line:114
|vpiName:i
|vpiStmt:
\_assignment: , line:115
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (sim_register), line:115
|vpiName:sim_register
|vpiFullName:work@register_file.sim_register
|vpiRhs:
\_ref_obj: (sim_registers_unamed), line:115
|vpiName:sim_registers_unamed
|vpiFullName:work@register_file.sim_registers_unamed
|vpiPort:
\_port: (clk), line:27
|vpiName:clk
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (clk), line:27
|vpiName:clk
|vpiFullName:work@register_file.clk
|vpiNetType:36
|vpiPort:
\_port: (rst), line:28
|vpiName:rst
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (rst), line:28
|vpiName:rst
|vpiFullName:work@register_file.rst
|vpiNetType:36
|vpiPort:
\_port: (gc_supress_writeback), line:29
|vpiName:gc_supress_writeback
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (gc_supress_writeback), line:29
|vpiName:gc_supress_writeback
|vpiFullName:work@register_file.gc_supress_writeback
|vpiNetType:36
|vpiPort:
\_port: (instruction_issued), line:31
|vpiName:instruction_issued
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (instruction_issued), line:31
|vpiName:instruction_issued
|vpiFullName:work@register_file.instruction_issued
|vpiNetType:36
|vpiPort:
\_port: (rf_wb), line:32
|vpiName:rf_wb
|vpiDirection:5
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_modport: (unit)
|vpiPort:
\_port: (rf_decode), line:33
|vpiName:rf_decode
|vpiDirection:5
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_modport: (unit)
|vpiPort:
\_port: (tr_rs1_forwarding_needed), line:36
|vpiName:tr_rs1_forwarding_needed
|vpiDirection:2
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (tr_rs1_forwarding_needed), line:36
|vpiName:tr_rs1_forwarding_needed
|vpiFullName:work@register_file.tr_rs1_forwarding_needed
|vpiNetType:36
|vpiPort:
\_port: (tr_rs2_forwarding_needed), line:37
|vpiName:tr_rs2_forwarding_needed
|vpiDirection:2
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (tr_rs2_forwarding_needed), line:37
|vpiName:tr_rs2_forwarding_needed
|vpiFullName:work@register_file.tr_rs2_forwarding_needed
|vpiNetType:36
|vpiPort:
\_port: (tr_rs1_and_rs2_forwarding_needed), line:38
|vpiName:tr_rs1_and_rs2_forwarding_needed
|vpiDirection:2
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (tr_rs1_and_rs2_forwarding_needed), line:38
|vpiName:tr_rs1_and_rs2_forwarding_needed
|vpiFullName:work@register_file.tr_rs1_and_rs2_forwarding_needed
|vpiNetType:36
|vpiContAssign:
\_cont_assign: , line:82
|vpiRhs:
\_bit_select: (in_use_by), line:82
|vpiName:in_use_by
|vpiFullName:work@register_file.in_use_by
|vpiIndex:
\_ref_obj: (rf_decode.rs1_addr), line:82
|vpiName:rf_decode.rs1_addr
|vpiLhs:
\_ref_obj: (rf_wb.rs1_id), line:82
|vpiName:rf_wb.rs1_id
|vpiFullName:work@register_file.rf_wb.rs1_id
|vpiContAssign:
\_cont_assign: , line:83
|vpiRhs:
\_bit_select: (in_use_by), line:83
|vpiName:in_use_by
|vpiFullName:work@register_file.in_use_by
|vpiIndex:
\_ref_obj: (rf_decode.rs2_addr), line:83
|vpiName:rf_decode.rs2_addr
|vpiLhs:
\_ref_obj: (rf_wb.rs2_id), line:83
|vpiName:rf_wb.rs2_id
|vpiFullName:work@register_file.rf_wb.rs2_id
|vpiContAssign:
\_cont_assign: , line:84
|vpiRhs:
\_ref_obj: (rf_wb.rs2_id), line:84
|vpiName:rf_wb.rs2_id
|vpiFullName:work@register_file.rf_wb.rs2_id
|vpiLhs:
\_ref_obj: (rf_decode.rs2_id), line:84
|vpiName:rf_decode.rs2_id
|vpiFullName:work@register_file.rf_decode.rs2_id
|vpiContAssign:
\_cont_assign: , line:86
|vpiRhs:
\_operation: , line:86
|vpiOpType:28
|vpiOperand:
\_ref_obj: (rf_wb.rd_nzero), line:86
|vpiName:rf_wb.rd_nzero
|vpiFullName:work@register_file.rf_wb.rd_nzero
|vpiOperand:
\_ref_obj: (rf_wb.retiring), line:86
|vpiName:rf_wb.retiring
|vpiFullName:work@register_file.rf_wb.retiring
|vpiLhs:
\_ref_obj: (valid_write), line:86
|vpiName:valid_write
|vpiFullName:work@register_file.valid_write
|vpiContAssign:
\_cont_assign: , line:88
|vpiRhs:
\_ref_obj: (rs1_inuse), line:88
|vpiName:rs1_inuse
|vpiFullName:work@register_file.rs1_inuse
|vpiLhs:
\_ref_obj: (rs1_feedforward), line:88
|vpiName:rs1_feedforward
|vpiFullName:work@register_file.rs1_feedforward
|vpiContAssign:
\_cont_assign: , line:89
|vpiRhs:
\_ref_obj: (rs2_inuse), line:89
|vpiName:rs2_inuse
|vpiFullName:work@register_file.rs2_inuse
|vpiLhs:
\_ref_obj: (rs2_feedforward), line:89
|vpiName:rs2_feedforward
|vpiFullName:work@register_file.rs2_feedforward
|vpiContAssign:
\_cont_assign: , line:91
|vpiRhs:
\_operation: , line:91
|vpiOpType:32
|vpiOperand:
\_ref_obj: (rs1_feedforward), line:91
|vpiName:rs1_feedforward
|vpiFullName:work@register_file.rs1_feedforward
|vpiOperand:
\_ref_obj: (rf_wb.rs1_data), line:91
|vpiName:rf_wb.rs1_data
|vpiFullName:work@register_file.rf_wb.rs1_data
|vpiOperand:
\_bit_select: (register), line:91
|vpiName:register
|vpiFullName:work@register_file.register
|vpiIndex:
\_ref_obj: (rf_decode.rs1_addr), line:91
|vpiName:rf_decode.rs1_addr
|vpiFullName:work@register_file.rf_decode.rs1_addr
|vpiLhs:
\_ref_obj: (rf_decode.rs1_data), line:91
|vpiName:rf_decode.rs1_data
|vpiFullName:work@register_file.rf_decode.rs1_data
|vpiContAssign:
\_cont_assign: , line:92
|vpiRhs:
\_operation: , line:92
|vpiOpType:32
|vpiOperand:
\_ref_obj: (rs2_feedforward), line:92
|vpiName:rs2_feedforward
|vpiFullName:work@register_file.rs2_feedforward
|vpiOperand:
\_ref_obj: (rf_wb.rs2_data), line:92
|vpiName:rf_wb.rs2_data
|vpiFullName:work@register_file.rf_wb.rs2_data
|vpiOperand:
\_bit_select: (register), line:92
|vpiName:register
|vpiFullName:work@register_file.register
|vpiIndex:
\_ref_obj: (rf_decode.rs2_addr), line:92
|vpiName:rf_decode.rs2_addr
|vpiFullName:work@register_file.rf_decode.rs2_addr
|vpiLhs:
\_ref_obj: (rf_decode.rs2_data), line:92
|vpiName:rf_decode.rs2_data
|vpiFullName:work@register_file.rf_decode.rs2_data
|vpiContAssign:
\_cont_assign: , line:94
|vpiRhs:
\_operation: , line:94
|vpiOpType:28
|vpiOperand:
\_operation: , line:94
|vpiOpType:28
|vpiOperand:
\_ref_obj: (rf_decode.uses_rs1), line:94
|vpiName:rf_decode.uses_rs1
|vpiFullName:work@register_file.rf_decode.uses_rs1
|vpiOperand:
\_ref_obj: (rs1_inuse), line:94
|vpiName:rs1_inuse
|vpiFullName:work@register_file.rs1_inuse
|vpiOperand:
\_operation: , line:94
|vpiOpType:4
|vpiOperand:
\_ref_obj: (rf_wb.rs1_valid), line:94
|vpiName:rf_wb.rs1_valid
|vpiFullName:work@register_file.rf_wb.rs1_valid
|vpiLhs:
\_ref_obj: (rf_decode.rs1_conflict), line:94
|vpiName:rf_decode.rs1_conflict
|vpiFullName:work@register_file.rf_decode.rs1_conflict
|vpiContAssign:
\_cont_assign: , line:95
|vpiRhs:
\_operation: , line:95
|vpiOpType:28
|vpiOperand:
\_operation: , line:95
|vpiOpType:28
|vpiOperand:
\_ref_obj: (rf_decode.uses_rs2), line:95
|vpiName:rf_decode.uses_rs2
|vpiFullName:work@register_file.rf_decode.uses_rs2
|vpiOperand:
\_ref_obj: (rs2_inuse), line:95
|vpiName:rs2_inuse
|vpiFullName:work@register_file.rs2_inuse
|vpiOperand:
\_operation: , line:95
|vpiOpType:4
|vpiOperand:
\_ref_obj: (rf_wb.rs2_valid), line:95
|vpiName:rf_wb.rs2_valid
|vpiFullName:work@register_file.rf_wb.rs2_valid
|vpiLhs:
\_ref_obj: (rf_decode.rs2_conflict), line:95
|vpiName:rf_decode.rs2_conflict
|vpiFullName:work@register_file.rf_decode.rs2_conflict
|vpiNet:
\_logic_net: (clk), line:27
|vpiNet:
\_logic_net: (rst), line:28
|vpiNet:
\_logic_net: (gc_supress_writeback), line:29
|vpiNet:
\_logic_net: (instruction_issued), line:31
|vpiNet:
\_logic_net: (tr_rs1_forwarding_needed), line:36
|vpiNet:
\_logic_net: (tr_rs2_forwarding_needed), line:37
|vpiNet:
\_logic_net: (tr_rs1_and_rs2_forwarding_needed), line:38
|vpiNet:
\_logic_net: (register), line:41
|vpiName:register
|vpiFullName:work@register_file.register
|vpiNetType:36
|vpiNet:
\_logic_net: (in_use_by), line:42
|vpiName:in_use_by
|vpiFullName:work@register_file.in_use_by
|vpiNet:
\_logic_net: (rs1_inuse), line:44
|vpiName:rs1_inuse
|vpiFullName:work@register_file.rs1_inuse
|vpiNetType:36
|vpiNet:
\_logic_net: (rs2_inuse), line:45
|vpiName:rs2_inuse
|vpiFullName:work@register_file.rs2_inuse
|vpiNetType:36
|vpiNet:
\_logic_net: (rs1_feedforward), line:47
|vpiName:rs1_feedforward
|vpiFullName:work@register_file.rs1_feedforward
|vpiNetType:36
|vpiNet:
\_logic_net: (rs2_feedforward), line:48
|vpiName:rs2_feedforward
|vpiFullName:work@register_file.rs2_feedforward
|vpiNetType:36
|vpiNet:
\_logic_net: (valid_write), line:50
|vpiName:valid_write
|vpiFullName:work@register_file.valid_write
|vpiNetType:36
|vpiNet:
\_logic_net: (in_use_match), line:51
|vpiName:in_use_match
|vpiFullName:work@register_file.in_use_match
|vpiNetType:36
|vpiNet:
\_logic_net: (sim_registers_unamed), line:110
|vpiName:sim_registers_unamed
|vpiFullName:work@register_file.sim_registers_unamed
|vpiNetType:36
|vpiNet:
\_logic_net: (sim_register), line:111
|vpiName:sim_register
|vpiFullName:work@register_file.sim_register
|vpiNet:
\_logic_net: (rf_wb), line:32
|vpiName:rf_wb
|vpiFullName:work@register_file.rf_wb
|vpiNet:
\_logic_net: (rf_decode), line:33
|vpiName:rf_decode
|vpiFullName:work@register_file.rf_decode
|vpiTypedef:
\_struct_typespec: (alu_inputs_t), line:301
|vpiTypedef:
\_enum_typespec: (alu_logic_op_t), line:84
|vpiTypedef:
\_enum_typespec: (alu_op_t), line:91
|vpiTypedef:
\_enum_typespec: (alu_rs1_op_t), line:97
|vpiTypedef:
\_enum_typespec: (alu_rs2_op_t), line:104
|vpiTypedef:
\_struct_typespec: (amo_alu_inputs_t), line:356
|vpiTypedef:
\_struct_typespec: (amo_details_t), line:362
|vpiTypedef:
\_enum_typespec: (amo_t), line:354
|vpiTypedef:
\_struct_typespec: (branch_inputs_t), line:313
|vpiTypedef:
\_logic_typespec: (branch_predictor_metadata_t), line:32
|vpiTypedef:
\_struct_typespec: (branch_results_t), line:330
|vpiTypedef:
\_enum_typespec: (bus_type_t), line:86
|vpiTypedef:
\_struct_typespec: (csr_inputs_t), line:396
|vpiTypedef:
\_enum_typespec: (csr_op_t), line:218
|vpiTypedef:
\_enum_typespec: (csr_t), line:201
|vpiTypedef:
\_struct_typespec: (data_access_shared_inputs_t), line:427
|vpiTypedef:
\_struct_typespec: (div_inputs_t), line:389
|vpiTypedef:
\_enum_typespec: (div_type), line:66
|vpiTypedef:
\_enum_typespec: (exception_code_t), line:245
|vpiTypedef:
\_struct_typespec: (exception_packet_t), line:263
|vpiTypedef:
\_struct_typespec: (fetch_buffer_packet_t), line:276
|vpiTypedef:
\_enum_typespec: (fifo_type_t), line:440
|vpiTypedef:
\_enum_typespec: (fn3_arith_t), line:76
|vpiTypedef:
\_enum_typespec: (fn3_branch_t), line:126
|vpiTypedef:
\_enum_typespec: (fn3_csr_t), line:212
|vpiTypedef:
\_enum_typespec: (fn3_ls_t), line:115
|vpiTypedef:
\_enum_typespec: (fn3_mul_div_t), line:138
|vpiTypedef:
\_struct_typespec: (gc_inputs_t), line:404
|vpiTypedef:
\_struct_typespec: (inflight_instruction_packet), line:271
|vpiTypedef:
\_logic_typespec: (instruction_id_t), line:30
|vpiTypedef:
\_enum_typespec: (interrupt_code_t), line:261
|vpiTypedef:
\_struct_typespec: (load_store_inputs_t), line:369
|vpiTypedef:
\_struct_typespec: (mul_inputs_t), line:383
|vpiTypedef:
\_enum_typespec: (opcodes_t), line:48
|vpiTypedef:
\_enum_typespec: (opcodes_trimmed_t), line:65
|vpiTypedef:
\_struct_typespec: (simulation_named_regfile), line:476
|vpiTypedef:
\_struct_typespec: (taiga_trace_events_t), line:442
|vpiTypedef:
\_struct_typespec: (to_l1_arbiter_packet), line:418
|vpiTypedef:
\_struct_typespec: (trace_outputs_t), line:469
|vpiTypedef:
\_logic_typespec: (unit_id_t), line:31
|vpiTypedef:
\_struct_typespec: (unit_writeback_t), line:295
|vpiTypedef:
\_enum_typespec: (vm_t), line:223
|uhdmallModules:
\_module: work@shift_counter, file:third_party/cores/taiga/core/shift_counter.sv, line:26, parent:work@div_unit_core_wrapper
|vpiDefName:work@shift_counter
|vpiFullName:work@shift_counter
|vpiProcess:
\_always: , line:38
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:38
|vpiCondition:
\_operation: , line:38
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:38
|vpiName:clk
|vpiFullName:work@shift_counter.clk
|vpiStmt:
\_begin: , line:38
|vpiFullName:work@shift_counter
|vpiStmt:
\_assignment: , line:39
|vpiOpType:82
|vpiLhs:
\_bit_select: (counter), line:39
|vpiName:counter
|vpiFullName:work@shift_counter.counter
|vpiIndex:
\_constant: , line:39
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiRhs:
\_ref_obj: (start), line:39
|vpiName:start
|vpiFullName:work@shift_counter.start
|vpiStmt:
\_assignment: , line:40
|vpiOpType:82
|vpiLhs:
\_part_select: , line:40, parent:counter
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (counter)
|vpiLeftRange:
\_operation: , line:40
|vpiOpType:11
|vpiOperand:
\_ref_obj: (DEPTH), line:40
|vpiName:DEPTH
|vpiOperand:
\_constant: , line:40
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:40
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRhs:
\_part_select: , line:40, parent:counter
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (counter)
|vpiLeftRange:
\_operation: , line:40
|vpiOpType:11
|vpiOperand:
\_ref_obj: (DEPTH), line:40
|vpiName:DEPTH
|vpiOperand:
\_constant: , line:40
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiRightRange:
\_constant: , line:40
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiPort:
\_port: (clk), line:27
|vpiName:clk
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (clk), line:27
|vpiName:clk
|vpiFullName:work@shift_counter.clk
|vpiNetType:36
|vpiPort:
\_port: (start), line:29
|vpiName:start
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (start), line:29
|vpiName:start
|vpiFullName:work@shift_counter.start
|vpiNetType:36
|vpiPort:
\_port: (done), line:30
|vpiName:done
|vpiDirection:2
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (done), line:30
|vpiName:done
|vpiFullName:work@shift_counter.done
|vpiNetType:36
|vpiContAssign:
\_cont_assign: , line:42
|vpiRhs:
\_bit_select: (counter), line:42
|vpiName:counter
|vpiFullName:work@shift_counter.counter
|vpiIndex:
\_operation: , line:42
|vpiOpType:11
|vpiOperand:
\_ref_obj: (DEPTH), line:42
|vpiName:DEPTH
|vpiOperand:
\_constant: , line:42
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiLhs:
\_ref_obj: (done), line:42
|vpiName:done
|vpiFullName:work@shift_counter.done
|vpiNet:
\_logic_net: (clk), line:27
|vpiNet:
\_logic_net: (start), line:29
|vpiNet:
\_logic_net: (done), line:30
|vpiNet:
\_logic_net: (counter), line:33
|vpiName:counter
|vpiFullName:work@shift_counter.counter
|vpiNetType:36
|vpiTypedef:
\_struct_typespec: (alu_inputs_t), line:301
|vpiTypedef:
\_enum_typespec: (alu_logic_op_t), line:84
|vpiTypedef:
\_enum_typespec: (alu_op_t), line:91
|vpiTypedef:
\_enum_typespec: (alu_rs1_op_t), line:97
|vpiTypedef:
\_enum_typespec: (alu_rs2_op_t), line:104
|vpiTypedef:
\_struct_typespec: (amo_alu_inputs_t), line:356
|vpiTypedef:
\_struct_typespec: (amo_details_t), line:362
|vpiTypedef:
\_enum_typespec: (amo_t), line:354
|vpiTypedef:
\_struct_typespec: (branch_inputs_t), line:313
|vpiTypedef:
\_logic_typespec: (branch_predictor_metadata_t), line:32
|vpiTypedef:
\_struct_typespec: (branch_results_t), line:330
|vpiTypedef:
\_enum_typespec: (bus_type_t), line:86
|vpiTypedef:
\_struct_typespec: (csr_inputs_t), line:396
|vpiTypedef:
\_enum_typespec: (csr_op_t), line:218
|vpiTypedef:
\_enum_typespec: (csr_t), line:201
|vpiTypedef:
\_struct_typespec: (data_access_shared_inputs_t), line:427
|vpiTypedef:
\_struct_typespec: (div_inputs_t), line:389
|vpiTypedef:
\_enum_typespec: (div_type), line:66
|vpiTypedef:
\_enum_typespec: (exception_code_t), line:245
|vpiTypedef:
\_struct_typespec: (exception_packet_t), line:263
|vpiTypedef:
\_struct_typespec: (fetch_buffer_packet_t), line:276
|vpiTypedef:
\_enum_typespec: (fifo_type_t), line:440
|vpiTypedef:
\_enum_typespec: (fn3_arith_t), line:76
|vpiTypedef:
\_enum_typespec: (fn3_branch_t), line:126
|vpiTypedef:
\_enum_typespec: (fn3_csr_t), line:212
|vpiTypedef:
\_enum_typespec: (fn3_ls_t), line:115
|vpiTypedef:
\_enum_typespec: (fn3_mul_div_t), line:138
|vpiTypedef:
\_struct_typespec: (gc_inputs_t), line:404
|vpiTypedef:
\_struct_typespec: (inflight_instruction_packet), line:271
|vpiTypedef:
\_logic_typespec: (instruction_id_t), line:30
|vpiTypedef:
\_enum_typespec: (interrupt_code_t), line:261
|vpiTypedef:
\_struct_typespec: (load_store_inputs_t), line:369
|vpiTypedef:
\_struct_typespec: (mul_inputs_t), line:383
|vpiTypedef:
\_enum_typespec: (opcodes_t), line:48
|vpiTypedef:
\_enum_typespec: (opcodes_trimmed_t), line:65
|vpiTypedef:
\_struct_typespec: (simulation_named_regfile), line:476
|vpiTypedef:
\_struct_typespec: (taiga_trace_events_t), line:442
|vpiTypedef:
\_struct_typespec: (to_l1_arbiter_packet), line:418
|vpiTypedef:
\_struct_typespec: (trace_outputs_t), line:469
|vpiTypedef:
\_logic_typespec: (unit_id_t), line:31
|vpiTypedef:
\_struct_typespec: (unit_writeback_t), line:295
|vpiTypedef:
\_enum_typespec: (vm_t), line:223
|vpiParamAssign:
\_param_assign: , line:26
|vpiRhs:
\_constant: , line:26
|vpiConstType:7
|vpiDecompile:16
|vpiSize:32
|INT:16
|vpiLhs:
\_parameter: (DEPTH), line:26
|vpiName:DEPTH
|vpiParameter:
\_parameter: (DEPTH), line:26
|uhdmallModules:
\_module: work@tag_bank, file:third_party/cores/taiga/core/tag_bank.sv, line:26, parent:work@div_unit_core_wrapper
|vpiDefName:work@tag_bank
|vpiFullName:work@tag_bank
|vpiProcess:
\_initial:
|vpiStmt:
\_for_stmt: , line:50
|vpiFullName:work@tag_bank
|vpiCondition:
\_operation: , line:50
|vpiOpType:20
|vpiOperand:
\_ref_obj: (i), line:50
|vpiName:i
|vpiFullName:work@tag_bank.i
|vpiOperand:
\_ref_obj: (LINES), line:50
|vpiName:LINES
|vpiFullName:work@tag_bank.LINES
|vpiForInitStmt:
\_assign_stmt:
|vpiRhs:
\_constant: , line:50
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiLhs:
\_logic_var: , line:50
|vpiFullName:work@tag_bank
|vpiForIncStmt:
\_operation: , line:50
|vpiOpType:82
|vpiOperand:
\_ref_obj: (i), line:50
|vpiName:i
|vpiStmt:
\_assignment: , line:50
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_bit_select: (tag_entry), line:50
|vpiName:tag_entry
|vpiFullName:work@tag_bank.tag_entry
|vpiIndex:
\_ref_obj: (i), line:50
|vpiName:i
|vpiRhs:
\_constant: , line:50
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiProcess:
\_always: , line:52
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:52
|vpiCondition:
\_operation: , line:52
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:52
|vpiName:clk
|vpiFullName:work@tag_bank.clk
|vpiStmt:
\_begin: , line:52
|vpiFullName:work@tag_bank
|vpiStmt:
\_if_stmt: , line:53
|vpiCondition:
\_ref_obj: (en_a), line:53
|vpiName:en_a
|vpiFullName:work@tag_bank.en_a
|vpiStmt:
\_begin: , line:53
|vpiFullName:work@tag_bank
|vpiStmt:
\_if_else: , line:54
|vpiCondition:
\_ref_obj: (wen_a), line:54
|vpiName:wen_a
|vpiFullName:work@tag_bank.wen_a
|vpiStmt:
\_assignment: , line:55
|vpiOpType:82
|vpiLhs:
\_bit_select: (tag_entry), line:55
|vpiName:tag_entry
|vpiFullName:work@tag_bank.tag_entry
|vpiIndex:
\_ref_obj: (addr_a), line:55
|vpiName:addr_a
|vpiRhs:
\_ref_obj: (data_in_a), line:55
|vpiName:data_in_a
|vpiFullName:work@tag_bank.data_in_a
|vpiElseStmt:
\_assignment: , line:57
|vpiOpType:82
|vpiLhs:
\_ref_obj: (data_out_a), line:57
|vpiName:data_out_a
|vpiFullName:work@tag_bank.data_out_a
|vpiRhs:
\_bit_select: (tag_entry), line:57
|vpiName:tag_entry
|vpiFullName:work@tag_bank.tag_entry
|vpiIndex:
\_ref_obj: (addr_a), line:57
|vpiName:addr_a
|vpiProcess:
\_always: , line:61
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:61
|vpiCondition:
\_operation: , line:61
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:61
|vpiName:clk
|vpiFullName:work@tag_bank.clk
|vpiStmt:
\_begin: , line:61
|vpiFullName:work@tag_bank
|vpiStmt:
\_if_stmt: , line:62
|vpiCondition:
\_ref_obj: (en_b), line:62
|vpiName:en_b
|vpiFullName:work@tag_bank.en_b
|vpiStmt:
\_begin: , line:62
|vpiFullName:work@tag_bank
|vpiStmt:
\_if_else: , line:63
|vpiCondition:
\_ref_obj: (wen_b), line:63
|vpiName:wen_b
|vpiFullName:work@tag_bank.wen_b
|vpiStmt:
\_begin: , line:63
|vpiFullName:work@tag_bank
|vpiStmt:
\_assignment: , line:64
|vpiOpType:82
|vpiLhs:
\_bit_select: (tag_entry), line:64
|vpiName:tag_entry
|vpiFullName:work@tag_bank.tag_entry
|vpiIndex:
\_ref_obj: (addr_b), line:64
|vpiName:addr_b
|vpiRhs:
\_ref_obj: (data_in_b), line:64
|vpiName:data_in_b
|vpiFullName:work@tag_bank.data_in_b
|vpiElseStmt:
\_begin: , line:66
|vpiFullName:work@tag_bank
|vpiStmt:
\_assignment: , line:67
|vpiOpType:82
|vpiLhs:
\_ref_obj: (data_out_b), line:67
|vpiName:data_out_b
|vpiFullName:work@tag_bank.data_out_b
|vpiRhs:
\_bit_select: (tag_entry), line:67
|vpiName:tag_entry
|vpiFullName:work@tag_bank.tag_entry
|vpiIndex:
\_ref_obj: (addr_b), line:67
|vpiName:addr_b
|vpiPort:
\_port: (clk), line:32
|vpiName:clk
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (clk), line:32
|vpiName:clk
|vpiFullName:work@tag_bank.clk
|vpiNetType:36
|vpiPort:
\_port: (rst), line:33
|vpiName:rst
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (rst), line:33
|vpiName:rst
|vpiFullName:work@tag_bank.rst
|vpiNetType:36
|vpiPort:
\_port: (addr_a), line:35
|vpiName:addr_a
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (addr_a), line:35
|vpiName:addr_a
|vpiFullName:work@tag_bank.addr_a
|vpiNetType:36
|vpiPort:
\_port: (addr_b), line:36
|vpiName:addr_b
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (addr_b), line:36
|vpiName:addr_b
|vpiFullName:work@tag_bank.addr_b
|vpiNetType:36
|vpiPort:
\_port: (en_a), line:37
|vpiName:en_a
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (en_a), line:37
|vpiName:en_a
|vpiFullName:work@tag_bank.en_a
|vpiNetType:36
|vpiPort:
\_port: (en_b), line:38
|vpiName:en_b
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (en_b), line:38
|vpiName:en_b
|vpiFullName:work@tag_bank.en_b
|vpiNetType:36
|vpiPort:
\_port: (wen_a), line:39
|vpiName:wen_a
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (wen_a), line:39
|vpiName:wen_a
|vpiFullName:work@tag_bank.wen_a
|vpiNetType:36
|vpiPort:
\_port: (wen_b), line:40
|vpiName:wen_b
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (wen_b), line:40
|vpiName:wen_b
|vpiFullName:work@tag_bank.wen_b
|vpiNetType:36
|vpiPort:
\_port: (data_in_a), line:41
|vpiName:data_in_a
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (data_in_a), line:41
|vpiName:data_in_a
|vpiFullName:work@tag_bank.data_in_a
|vpiNetType:36
|vpiPort:
\_port: (data_in_b), line:42
|vpiName:data_in_b
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (data_in_b), line:42
|vpiName:data_in_b
|vpiFullName:work@tag_bank.data_in_b
|vpiNetType:36
|vpiPort:
\_port: (data_out_a), line:43
|vpiName:data_out_a
|vpiDirection:2
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (data_out_a), line:43
|vpiName:data_out_a
|vpiFullName:work@tag_bank.data_out_a
|vpiNetType:36
|vpiPort:
\_port: (data_out_b), line:44
|vpiName:data_out_b
|vpiDirection:2
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (data_out_b), line:44
|vpiName:data_out_b
|vpiFullName:work@tag_bank.data_out_b
|vpiNetType:36
|vpiNet:
\_logic_net: (clk), line:32
|vpiNet:
\_logic_net: (rst), line:33
|vpiNet:
\_logic_net: (addr_a), line:35
|vpiNet:
\_logic_net: (addr_b), line:36
|vpiNet:
\_logic_net: (en_a), line:37
|vpiNet:
\_logic_net: (en_b), line:38
|vpiNet:
\_logic_net: (wen_a), line:39
|vpiNet:
\_logic_net: (wen_b), line:40
|vpiNet:
\_logic_net: (data_in_a), line:41
|vpiNet:
\_logic_net: (data_in_b), line:42
|vpiNet:
\_logic_net: (data_out_a), line:43
|vpiNet:
\_logic_net: (data_out_b), line:44
|vpiNet:
\_logic_net: (tag_entry), line:47
|vpiName:tag_entry
|vpiFullName:work@tag_bank.tag_entry
|vpiNetType:36
|vpiNet:
\_logic_net: (i), line:49
|vpiName:i
|vpiFullName:work@tag_bank.i
|vpiTypedef:
\_struct_typespec: (alu_inputs_t), line:301
|vpiTypedef:
\_enum_typespec: (alu_logic_op_t), line:84
|vpiTypedef:
\_enum_typespec: (alu_op_t), line:91
|vpiTypedef:
\_enum_typespec: (alu_rs1_op_t), line:97
|vpiTypedef:
\_enum_typespec: (alu_rs2_op_t), line:104
|vpiTypedef:
\_struct_typespec: (amo_alu_inputs_t), line:356
|vpiTypedef:
\_struct_typespec: (amo_details_t), line:362
|vpiTypedef:
\_enum_typespec: (amo_t), line:354
|vpiTypedef:
\_struct_typespec: (branch_inputs_t), line:313
|vpiTypedef:
\_logic_typespec: (branch_predictor_metadata_t), line:32
|vpiTypedef:
\_struct_typespec: (branch_results_t), line:330
|vpiTypedef:
\_enum_typespec: (bus_type_t), line:86
|vpiTypedef:
\_struct_typespec: (csr_inputs_t), line:396
|vpiTypedef:
\_enum_typespec: (csr_op_t), line:218
|vpiTypedef:
\_enum_typespec: (csr_t), line:201
|vpiTypedef:
\_struct_typespec: (data_access_shared_inputs_t), line:427
|vpiTypedef:
\_struct_typespec: (div_inputs_t), line:389
|vpiTypedef:
\_enum_typespec: (div_type), line:66
|vpiTypedef:
\_enum_typespec: (exception_code_t), line:245
|vpiTypedef:
\_struct_typespec: (exception_packet_t), line:263
|vpiTypedef:
\_struct_typespec: (fetch_buffer_packet_t), line:276
|vpiTypedef:
\_enum_typespec: (fifo_type_t), line:440
|vpiTypedef:
\_enum_typespec: (fn3_arith_t), line:76
|vpiTypedef:
\_enum_typespec: (fn3_branch_t), line:126
|vpiTypedef:
\_enum_typespec: (fn3_csr_t), line:212
|vpiTypedef:
\_enum_typespec: (fn3_ls_t), line:115
|vpiTypedef:
\_enum_typespec: (fn3_mul_div_t), line:138
|vpiTypedef:
\_struct_typespec: (gc_inputs_t), line:404
|vpiTypedef:
\_struct_typespec: (inflight_instruction_packet), line:271
|vpiTypedef:
\_logic_typespec: (instruction_id_t), line:30
|vpiTypedef:
\_enum_typespec: (interrupt_code_t), line:261
|vpiTypedef:
\_struct_typespec: (load_store_inputs_t), line:369
|vpiTypedef:
\_struct_typespec: (mul_inputs_t), line:383
|vpiTypedef:
\_enum_typespec: (opcodes_t), line:48
|vpiTypedef:
\_enum_typespec: (opcodes_trimmed_t), line:65
|vpiTypedef:
\_struct_typespec: (simulation_named_regfile), line:476
|vpiTypedef:
\_struct_typespec: (taiga_trace_events_t), line:442
|vpiTypedef:
\_struct_typespec: (to_l1_arbiter_packet), line:418
|vpiTypedef:
\_struct_typespec: (trace_outputs_t), line:469
|vpiTypedef:
\_logic_typespec: (unit_id_t), line:31
|vpiTypedef:
\_struct_typespec: (unit_writeback_t), line:295
|vpiTypedef:
\_enum_typespec: (vm_t), line:223
|vpiParamAssign:
\_param_assign: , line:27
|vpiRhs:
\_constant: , line:27
|vpiConstType:7
|vpiDecompile:32
|vpiSize:32
|INT:32
|vpiLhs:
\_parameter: (WIDTH), line:27
|vpiName:WIDTH
|vpiParamAssign:
\_param_assign: , line:28
|vpiRhs:
\_constant: , line:28
|vpiConstType:7
|vpiDecompile:512
|vpiSize:32
|INT:512
|vpiLhs:
\_parameter: (LINES), line:28
|vpiName:LINES
|vpiParameter:
\_parameter: (WIDTH), line:27
|vpiParameter:
\_parameter: (LINES), line:28
|uhdmallModules:
\_module: work@taiga, file:third_party/cores/taiga/core/taiga.sv, line:26, parent:work@div_unit_core_wrapper
|vpiDefName:work@taiga
|vpiFullName:work@taiga
|vpiPort:
\_port: (clk), line:27
|vpiName:clk
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (clk), line:27
|vpiName:clk
|vpiFullName:work@taiga.clk
|vpiNetType:36
|vpiPort:
\_port: (rst), line:28
|vpiName:rst
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (rst), line:28
|vpiName:rst
|vpiFullName:work@taiga.rst
|vpiNetType:36
|vpiPort:
\_port: (instruction_bram), line:30
|vpiName:instruction_bram
|vpiDirection:5
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_modport: (master)
|vpiPort:
\_port: (data_bram), line:31
|vpiName:data_bram
|vpiDirection:5
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_modport: (master)
|vpiPort:
\_port: (m_axi), line:33
|vpiName:m_axi
|vpiDirection:5
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_modport: (master)
|vpiPort:
\_port: (m_avalon), line:34
|vpiName:m_avalon
|vpiDirection:5
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_modport: (master)
|vpiPort:
\_port: (m_wishbone), line:35
|vpiName:m_wishbone
|vpiDirection:5
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_modport: (master)
|vpiPort:
\_port: (tr), line:37
|vpiName:tr
|vpiDirection:2
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (tr), line:37
|vpiName:tr
|vpiFullName:work@taiga.tr
|vpiPort:
\_port: (l2), line:39
|vpiName:l2
|vpiDirection:5
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_modport: (master)
|vpiPort:
\_port: (timer_interrupt), line:41
|vpiName:timer_interrupt
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (timer_interrupt), line:41
|vpiName:timer_interrupt
|vpiFullName:work@taiga.timer_interrupt
|vpiNetType:36
|vpiPort:
\_port: (interrupt), line:42
|vpiName:interrupt
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (interrupt), line:42
|vpiName:interrupt
|vpiFullName:work@taiga.interrupt
|vpiNetType:36
|vpiNet:
\_logic_net: (clk), line:27
|vpiNet:
\_logic_net: (rst), line:28
|vpiNet:
\_logic_net: (tr), line:37
|vpiNet:
\_logic_net: (timer_interrupt), line:41
|vpiNet:
\_logic_net: (interrupt), line:42
|vpiNet:
\_logic_net: (sc_complete), line:47
|vpiName:sc_complete
|vpiFullName:work@taiga.sc_complete
|vpiNetType:36
|vpiNet:
\_logic_net: (sc_success), line:48
|vpiName:sc_success
|vpiFullName:work@taiga.sc_success
|vpiNetType:36
|vpiNet:
\_logic_net: (br_results), line:51
|vpiName:br_results
|vpiFullName:work@taiga.br_results
|vpiNet:
\_logic_net: (branch_flush), line:52
|vpiName:branch_flush
|vpiFullName:work@taiga.branch_flush
|vpiNetType:36
|vpiNet:
\_logic_net: (alu_inputs), line:57
|vpiName:alu_inputs
|vpiFullName:work@taiga.alu_inputs
|vpiNet:
\_logic_net: (ls_inputs), line:58
|vpiName:ls_inputs
|vpiFullName:work@taiga.ls_inputs
|vpiNet:
\_logic_net: (branch_inputs), line:59
|vpiName:branch_inputs
|vpiFullName:work@taiga.branch_inputs
|vpiNet:
\_logic_net: (mul_inputs), line:60
|vpiName:mul_inputs
|vpiFullName:work@taiga.mul_inputs
|vpiNet:
\_logic_net: (div_inputs), line:61
|vpiName:div_inputs
|vpiFullName:work@taiga.div_inputs
|vpiNet:
\_logic_net: (gc_inputs), line:62
|vpiName:gc_inputs
|vpiFullName:work@taiga.gc_inputs
|vpiNet:
\_logic_net: (ls_exception), line:66
|vpiName:ls_exception
|vpiFullName:work@taiga.ls_exception
|vpiNet:
\_logic_net: (ls_exception_valid), line:67
|vpiName:ls_exception_valid
|vpiFullName:work@taiga.ls_exception_valid
|vpiNetType:36
|vpiNet:
\_logic_net: (unit_wb), line:70
|vpiName:unit_wb
|vpiFullName:work@taiga.unit_wb
|vpiNet:
\_logic_net: (tlb_on), line:78
|vpiName:tlb_on
|vpiFullName:work@taiga.tlb_on
|vpiNetType:36
|vpiNet:
\_logic_net: (asid), line:79
|vpiName:asid
|vpiFullName:work@taiga.asid
|vpiNetType:36
|vpiNet:
\_logic_net: (pre_decode_push), line:82
|vpiName:pre_decode_push
|vpiFullName:work@taiga.pre_decode_push
|vpiNetType:36
|vpiNet:
\_logic_net: (pre_decode_pop), line:83
|vpiName:pre_decode_pop
|vpiFullName:work@taiga.pre_decode_pop
|vpiNetType:36
|vpiNet:
\_logic_net: (pre_decode_instruction), line:84
|vpiName:pre_decode_instruction
|vpiFullName:work@taiga.pre_decode_instruction
|vpiNetType:36
|vpiNet:
\_logic_net: (pre_decode_pc), line:85
|vpiName:pre_decode_pc
|vpiFullName:work@taiga.pre_decode_pc
|vpiNetType:36
|vpiNet:
\_logic_net: (branch_metadata), line:86
|vpiName:branch_metadata
|vpiFullName:work@taiga.branch_metadata
|vpiNet:
\_logic_net: (branch_prediction_used), line:87
|vpiName:branch_prediction_used
|vpiFullName:work@taiga.branch_prediction_used
|vpiNetType:36
|vpiNet:
\_logic_net: (bp_update_way), line:88
|vpiName:bp_update_way
|vpiFullName:work@taiga.bp_update_way
|vpiNetType:36
|vpiNet:
\_logic_net: (fb_valid), line:89
|vpiName:fb_valid
|vpiFullName:work@taiga.fb_valid
|vpiNetType:36
|vpiNet:
\_logic_net: (fb), line:90
|vpiName:fb
|vpiFullName:work@taiga.fb
|vpiNet:
\_logic_net: (gc_issue_hold), line:93
|vpiName:gc_issue_hold
|vpiFullName:work@taiga.gc_issue_hold
|vpiNetType:36
|vpiNet:
\_logic_net: (gc_issue_flush), line:94
|vpiName:gc_issue_flush
|vpiFullName:work@taiga.gc_issue_flush
|vpiNetType:36
|vpiNet:
\_logic_net: (gc_fetch_flush), line:95
|vpiName:gc_fetch_flush
|vpiFullName:work@taiga.gc_fetch_flush
|vpiNetType:36
|vpiNet:
\_logic_net: (gc_fetch_pc_override), line:96
|vpiName:gc_fetch_pc_override
|vpiFullName:work@taiga.gc_fetch_pc_override
|vpiNetType:36
|vpiNet:
\_logic_net: (gc_supress_writeback), line:97
|vpiName:gc_supress_writeback
|vpiFullName:work@taiga.gc_supress_writeback
|vpiNetType:36
|vpiNet:
\_logic_net: (oldest_id), line:98
|vpiName:oldest_id
|vpiFullName:work@taiga.oldest_id
|vpiNet:
\_logic_net: (load_store_issue), line:99
|vpiName:load_store_issue
|vpiFullName:work@taiga.load_store_issue
|vpiNetType:36
|vpiNet:
\_logic_net: (gc_fetch_pc), line:100
|vpiName:gc_fetch_pc
|vpiFullName:work@taiga.gc_fetch_pc
|vpiNetType:36
|vpiNet:
\_logic_net: (csr_rd), line:103
|vpiName:csr_rd
|vpiFullName:work@taiga.csr_rd
|vpiNetType:36
|vpiNet:
\_logic_net: (csr_id), line:104
|vpiName:csr_id
|vpiFullName:work@taiga.csr_id
|vpiNet:
\_logic_net: (csr_done), line:105
|vpiName:csr_done
|vpiFullName:work@taiga.csr_done
|vpiNetType:36
|vpiNet:
\_logic_net: (illegal_instruction), line:108
|vpiName:illegal_instruction
|vpiFullName:work@taiga.illegal_instruction
|vpiNetType:36
|vpiNet:
\_logic_net: (instruction_queue_empty), line:109
|vpiName:instruction_queue_empty
|vpiFullName:work@taiga.instruction_queue_empty
|vpiNetType:36
|vpiNet:
\_logic_net: (instruction_issued), line:111
|vpiName:instruction_issued
|vpiFullName:work@taiga.instruction_issued
|vpiNetType:36
|vpiNet:
\_logic_net: (instruction_issued_no_rd), line:112
|vpiName:instruction_issued_no_rd
|vpiFullName:work@taiga.instruction_issued_no_rd
|vpiNetType:36
|vpiNet:
\_logic_net: (instruction_issued_with_rd), line:113
|vpiName:instruction_issued_with_rd
|vpiFullName:work@taiga.instruction_issued_with_rd
|vpiNetType:36
|vpiNet:
\_logic_net: (instruction_complete), line:114
|vpiName:instruction_complete
|vpiFullName:work@taiga.instruction_complete
|vpiNetType:36
|vpiNet:
\_logic_net: (gc_flush_required), line:115
|vpiName:gc_flush_required
|vpiFullName:work@taiga.gc_flush_required
|vpiNetType:36
|vpiNet:
\_logic_net: (store_done_id), line:118
|vpiName:store_done_id
|vpiFullName:work@taiga.store_done_id
|vpiNet:
\_logic_net: (store_complete), line:119
|vpiName:store_complete
|vpiFullName:work@taiga.store_complete
|vpiNetType:36
|vpiNet:
\_logic_net: (store_issued_with_data), line:122
|vpiName:store_issued_with_data
|vpiFullName:work@taiga.store_issued_with_data
|vpiNetType:36
|vpiNet:
\_logic_net: (store_data), line:123
|vpiName:store_data
|vpiFullName:work@taiga.store_data
|vpiNetType:36
|vpiNet:
\_logic_net: (tr_operand_stall), line:126
|vpiName:tr_operand_stall
|vpiFullName:work@taiga.tr_operand_stall
|vpiNetType:36
|vpiNet:
\_logic_net: (tr_unit_stall), line:127
|vpiName:tr_unit_stall
|vpiFullName:work@taiga.tr_unit_stall
|vpiNetType:36
|vpiNet:
\_logic_net: (tr_no_id_stall), line:128
|vpiName:tr_no_id_stall
|vpiFullName:work@taiga.tr_no_id_stall
|vpiNetType:36
|vpiNet:
\_logic_net: (tr_no_instruction_stall), line:129
|vpiName:tr_no_instruction_stall
|vpiFullName:work@taiga.tr_no_instruction_stall
|vpiNetType:36
|vpiNet:
\_logic_net: (tr_other_stall), line:130
|vpiName:tr_other_stall
|vpiFullName:work@taiga.tr_other_stall
|vpiNetType:36
|vpiNet:
\_logic_net: (tr_branch_operand_stall), line:131
|vpiName:tr_branch_operand_stall
|vpiFullName:work@taiga.tr_branch_operand_stall
|vpiNetType:36
|vpiNet:
\_logic_net: (tr_alu_operand_stall), line:132
|vpiName:tr_alu_operand_stall
|vpiFullName:work@taiga.tr_alu_operand_stall
|vpiNetType:36
|vpiNet:
\_logic_net: (tr_ls_operand_stall), line:133
|vpiName:tr_ls_operand_stall
|vpiFullName:work@taiga.tr_ls_operand_stall
|vpiNetType:36
|vpiNet:
\_logic_net: (tr_div_operand_stall), line:134
|vpiName:tr_div_operand_stall
|vpiFullName:work@taiga.tr_div_operand_stall
|vpiNetType:36
|vpiNet:
\_logic_net: (tr_instruction_issued_dec), line:136
|vpiName:tr_instruction_issued_dec
|vpiFullName:work@taiga.tr_instruction_issued_dec
|vpiNetType:36
|vpiNet:
\_logic_net: (tr_instruction_pc_dec), line:137
|vpiName:tr_instruction_pc_dec
|vpiFullName:work@taiga.tr_instruction_pc_dec
|vpiNetType:36
|vpiNet:
\_logic_net: (tr_instruction_data_dec), line:138
|vpiName:tr_instruction_data_dec
|vpiFullName:work@taiga.tr_instruction_data_dec
|vpiNetType:36
|vpiNet:
\_logic_net: (tr_branch_correct), line:140
|vpiName:tr_branch_correct
|vpiFullName:work@taiga.tr_branch_correct
|vpiNetType:36
|vpiNet:
\_logic_net: (tr_branch_misspredict), line:141
|vpiName:tr_branch_misspredict
|vpiFullName:work@taiga.tr_branch_misspredict
|vpiNetType:36
|vpiNet:
\_logic_net: (tr_return_misspredict), line:142
|vpiName:tr_return_misspredict
|vpiFullName:work@taiga.tr_return_misspredict
|vpiNetType:36
|vpiNet:
\_logic_net: (tr_wb_mux_contention), line:143
|vpiName:tr_wb_mux_contention
|vpiFullName:work@taiga.tr_wb_mux_contention
|vpiNetType:36
|vpiNet:
\_logic_net: (tr_rs1_forwarding_needed), line:145
|vpiName:tr_rs1_forwarding_needed
|vpiFullName:work@taiga.tr_rs1_forwarding_needed
|vpiNetType:36
|vpiNet:
\_logic_net: (tr_rs2_forwarding_needed), line:146
|vpiName:tr_rs2_forwarding_needed
|vpiFullName:work@taiga.tr_rs2_forwarding_needed
|vpiNetType:36
|vpiNet:
\_logic_net: (tr_rs1_and_rs2_forwarding_needed), line:147
|vpiName:tr_rs1_and_rs2_forwarding_needed
|vpiFullName:work@taiga.tr_rs1_and_rs2_forwarding_needed
|vpiNetType:36
|vpiNet:
\_logic_net: (instruction_bram), line:30
|vpiName:instruction_bram
|vpiFullName:work@taiga.instruction_bram
|vpiNet:
\_logic_net: (data_bram), line:31
|vpiName:data_bram
|vpiFullName:work@taiga.data_bram
|vpiNet:
\_logic_net: (m_axi), line:33
|vpiName:m_axi
|vpiFullName:work@taiga.m_axi
|vpiNet:
\_logic_net: (m_avalon), line:34
|vpiName:m_avalon
|vpiFullName:work@taiga.m_avalon
|vpiNet:
\_logic_net: (m_wishbone), line:35
|vpiName:m_wishbone
|vpiFullName:work@taiga.m_wishbone
|vpiNet:
\_logic_net: (l2), line:39
|vpiName:l2
|vpiFullName:work@taiga.l2
|vpiTypedef:
\_struct_typespec: (alu_inputs_t), line:301
|vpiTypedef:
\_enum_typespec: (alu_logic_op_t), line:84
|vpiTypedef:
\_enum_typespec: (alu_op_t), line:91
|vpiTypedef:
\_enum_typespec: (alu_rs1_op_t), line:97
|vpiTypedef:
\_enum_typespec: (alu_rs2_op_t), line:104
|vpiTypedef:
\_struct_typespec: (amo_alu_inputs_t), line:356
|vpiTypedef:
\_struct_typespec: (amo_details_t), line:362
|vpiTypedef:
\_enum_typespec: (amo_t), line:354
|vpiTypedef:
\_struct_typespec: (branch_inputs_t), line:313
|vpiTypedef:
\_logic_typespec: (branch_predictor_metadata_t), line:32
|vpiTypedef:
\_struct_typespec: (branch_results_t), line:330
|vpiTypedef:
\_enum_typespec: (bus_type_t), line:86
|vpiTypedef:
\_struct_typespec: (csr_inputs_t), line:396
|vpiTypedef:
\_enum_typespec: (csr_op_t), line:218
|vpiTypedef:
\_enum_typespec: (csr_t), line:201
|vpiTypedef:
\_struct_typespec: (data_access_shared_inputs_t), line:427
|vpiTypedef:
\_struct_typespec: (div_inputs_t), line:389
|vpiTypedef:
\_enum_typespec: (div_type), line:66
|vpiTypedef:
\_enum_typespec: (exception_code_t), line:245
|vpiTypedef:
\_struct_typespec: (exception_packet_t), line:263
|vpiTypedef:
\_struct_typespec: (fetch_buffer_packet_t), line:276
|vpiTypedef:
\_enum_typespec: (fifo_type_t), line:440
|vpiTypedef:
\_enum_typespec: (fn3_arith_t), line:76
|vpiTypedef:
\_enum_typespec: (fn3_branch_t), line:126
|vpiTypedef:
\_enum_typespec: (fn3_csr_t), line:212
|vpiTypedef:
\_enum_typespec: (fn3_ls_t), line:115
|vpiTypedef:
\_enum_typespec: (fn3_mul_div_t), line:138
|vpiTypedef:
\_struct_typespec: (gc_inputs_t), line:404
|vpiTypedef:
\_struct_typespec: (inflight_instruction_packet), line:271
|vpiTypedef:
\_logic_typespec: (instruction_id_t), line:30
|vpiTypedef:
\_enum_typespec: (interrupt_code_t), line:261
|vpiTypedef:
\_struct_typespec: (load_store_inputs_t), line:369
|vpiTypedef:
\_struct_typespec: (mul_inputs_t), line:383
|vpiTypedef:
\_enum_typespec: (opcodes_t), line:48
|vpiTypedef:
\_enum_typespec: (opcodes_trimmed_t), line:65
|vpiTypedef:
\_struct_typespec: (simulation_named_regfile), line:476
|vpiTypedef:
\_struct_typespec: (taiga_trace_events_t), line:442
|vpiTypedef:
\_struct_typespec: (to_l1_arbiter_packet), line:418
|vpiTypedef:
\_struct_typespec: (trace_outputs_t), line:469
|vpiTypedef:
\_logic_typespec: (unit_id_t), line:31
|vpiTypedef:
\_struct_typespec: (unit_writeback_t), line:295
|vpiTypedef:
\_enum_typespec: (vm_t), line:223
|uhdmallModules:
\_module: work@taiga_fifo, file:third_party/cores/taiga/core/taiga_fifo.sv, line:31, parent:work@div_unit_core_wrapper
|vpiDefName:work@taiga_fifo
|vpiFullName:work@taiga_fifo
|vpiProcess:
\_always: , line:99
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:99
|vpiCondition:
\_operation: , line:99
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:99
|vpiName:clk
|vpiFullName:work@taiga_fifo.clk
|vpiStmt:
\_begin: , line:99
|vpiFullName:work@taiga_fifo
|vpiStmt:
\_immediate_assert: , line:100
|vpiExpr:
\_operation: , line:100
|vpiOpType:3
|vpiOperand:
\_operation: , line:100
|vpiOpType:28
|vpiOperand:
\_operation: , line:100
|vpiOpType:28
|vpiOperand:
\_operation: , line:100
|vpiOpType:28
|vpiOperand:
\_operation: , line:100
|vpiOpType:4
|vpiOperand:
\_ref_obj: (rst), line:100
|vpiName:rst
|vpiFullName:work@taiga_fifo.rst
|vpiOperand:
\_ref_obj: (fifo.full), line:100
|vpiName:fifo.full
|vpiFullName:work@taiga_fifo.fifo.full
|vpiOperand:
\_ref_obj: (supressed_push), line:100
|vpiName:supressed_push
|vpiFullName:work@taiga_fifo.supressed_push
|vpiOperand:
\_operation: , line:100
|vpiOpType:4
|vpiOperand:
\_ref_obj: (fifo.pop), line:100
|vpiName:fifo.pop
|vpiFullName:work@taiga_fifo.fifo.pop
|vpiElseStmt:
\_sys_func_call: ($error), line:100
|vpiName:$error
|vpiArgument:
\_constant: , line:100
|vpiConstType:6
|vpiDecompile:"overflow"
|vpiSize:10
|STRING:"overflow"
|vpiPort:
\_port: (clk), line:33
|vpiName:clk
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (clk), line:33
|vpiName:clk
|vpiFullName:work@taiga_fifo.clk
|vpiNetType:36
|vpiPort:
\_port: (rst), line:34
|vpiName:rst
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (rst), line:34
|vpiName:rst
|vpiFullName:work@taiga_fifo.rst
|vpiNetType:36
|vpiPort:
\_port: (fifo), line:35
|vpiName:fifo
|vpiDirection:5
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_modport: (structure)
|vpiContAssign:
\_cont_assign: , line:48
|vpiRhs:
\_operation: , line:48
|vpiOpType:28
|vpiOperand:
\_ref_obj: (fifo.push), line:48
|vpiName:fifo.push
|vpiFullName:work@taiga_fifo.fifo.push
|vpiOperand:
\_operation: , line:48
|vpiOpType:4
|vpiOperand:
\_ref_obj: (fifo.supress_push), line:48
|vpiName:fifo.supress_push
|vpiFullName:work@taiga_fifo.fifo.supress_push
|vpiLhs:
\_ref_obj: (supressed_push), line:48
|vpiName:supressed_push
|vpiFullName:work@taiga_fifo.supressed_push
|vpiNet:
\_logic_net: (clk), line:33
|vpiNet:
\_logic_net: (rst), line:34
|vpiNet:
\_logic_net: (lut_ram), line:40
|vpiName:lut_ram
|vpiFullName:work@taiga_fifo.lut_ram
|vpiNetType:36
|vpiNet:
\_logic_net: (write_index), line:41
|vpiName:write_index
|vpiFullName:work@taiga_fifo.write_index
|vpiNetType:36
|vpiNet:
\_logic_net: (read_index), line:42
|vpiName:read_index
|vpiFullName:work@taiga_fifo.read_index
|vpiNetType:36
|vpiNet:
\_logic_net: (inflight_count), line:43
|vpiName:inflight_count
|vpiFullName:work@taiga_fifo.inflight_count
|vpiNetType:36
|vpiNet:
\_logic_net: (supressed_push), line:44
|vpiName:supressed_push
|vpiFullName:work@taiga_fifo.supressed_push
|vpiNetType:36
|vpiNet:
\_logic_net: (fifo), line:35
|vpiName:fifo
|vpiFullName:work@taiga_fifo.fifo
|vpiTypedef:
\_struct_typespec: (alu_inputs_t), line:301
|vpiTypedef:
\_enum_typespec: (alu_logic_op_t), line:84
|vpiTypedef:
\_enum_typespec: (alu_op_t), line:91
|vpiTypedef:
\_enum_typespec: (alu_rs1_op_t), line:97
|vpiTypedef:
\_enum_typespec: (alu_rs2_op_t), line:104
|vpiTypedef:
\_struct_typespec: (amo_alu_inputs_t), line:356
|vpiTypedef:
\_struct_typespec: (amo_details_t), line:362
|vpiTypedef:
\_enum_typespec: (amo_t), line:354
|vpiTypedef:
\_struct_typespec: (branch_inputs_t), line:313
|vpiTypedef:
\_logic_typespec: (branch_predictor_metadata_t), line:32
|vpiTypedef:
\_struct_typespec: (branch_results_t), line:330
|vpiTypedef:
\_enum_typespec: (bus_type_t), line:86
|vpiTypedef:
\_struct_typespec: (csr_inputs_t), line:396
|vpiTypedef:
\_enum_typespec: (csr_op_t), line:218
|vpiTypedef:
\_enum_typespec: (csr_t), line:201
|vpiTypedef:
\_struct_typespec: (data_access_shared_inputs_t), line:427
|vpiTypedef:
\_struct_typespec: (div_inputs_t), line:389
|vpiTypedef:
\_enum_typespec: (div_type), line:66
|vpiTypedef:
\_enum_typespec: (exception_code_t), line:245
|vpiTypedef:
\_struct_typespec: (exception_packet_t), line:263
|vpiTypedef:
\_struct_typespec: (fetch_buffer_packet_t), line:276
|vpiTypedef:
\_enum_typespec: (fifo_type_t), line:440
|vpiTypedef:
\_enum_typespec: (fn3_arith_t), line:76
|vpiTypedef:
\_enum_typespec: (fn3_branch_t), line:126
|vpiTypedef:
\_enum_typespec: (fn3_csr_t), line:212
|vpiTypedef:
\_enum_typespec: (fn3_ls_t), line:115
|vpiTypedef:
\_enum_typespec: (fn3_mul_div_t), line:138
|vpiTypedef:
\_struct_typespec: (gc_inputs_t), line:404
|vpiTypedef:
\_struct_typespec: (inflight_instruction_packet), line:271
|vpiTypedef:
\_logic_typespec: (instruction_id_t), line:30
|vpiTypedef:
\_enum_typespec: (interrupt_code_t), line:261
|vpiTypedef:
\_struct_typespec: (load_store_inputs_t), line:369
|vpiTypedef:
\_struct_typespec: (mul_inputs_t), line:383
|vpiTypedef:
\_enum_typespec: (opcodes_t), line:48
|vpiTypedef:
\_enum_typespec: (opcodes_trimmed_t), line:65
|vpiTypedef:
\_struct_typespec: (simulation_named_regfile), line:476
|vpiTypedef:
\_struct_typespec: (taiga_trace_events_t), line:442
|vpiTypedef:
\_struct_typespec: (to_l1_arbiter_packet), line:418
|vpiTypedef:
\_struct_typespec: (trace_outputs_t), line:469
|vpiTypedef:
\_logic_typespec: (unit_id_t), line:31
|vpiTypedef:
\_struct_typespec: (unit_writeback_t), line:295
|vpiTypedef:
\_enum_typespec: (vm_t), line:223
|vpiParamAssign:
\_param_assign: , line:31
|vpiRhs:
\_constant: , line:31
|vpiConstType:7
|vpiDecompile:70
|vpiSize:32
|INT:70
|vpiLhs:
\_parameter: (DATA_WIDTH), line:31
|vpiName:DATA_WIDTH
|vpiParamAssign:
\_param_assign: , line:31
|vpiRhs:
\_constant: , line:31
|vpiConstType:7
|vpiDecompile:4
|vpiSize:32
|INT:4
|vpiLhs:
\_parameter: (FIFO_DEPTH), line:31
|vpiName:FIFO_DEPTH
|vpiParamAssign:
\_param_assign: , line:38
|vpiRhs:
\_constant: , line:38
|vpiDecompile:2
|INT:2
|vpiLhs:
\_parameter: (LOG2_FIFO_DEPTH), line:38
|vpiName:LOG2_FIFO_DEPTH
|vpiLocalParam:1
|vpiParameter:
\_parameter: (DATA_WIDTH), line:31
|vpiParameter:
\_parameter: (FIFO_DEPTH), line:31
|vpiParameter:
\_parameter: (LOG2_FIFO_DEPTH), line:38
|uhdmallModules:
\_module: work@taiga_wrapper, file:third_party/cores/taiga/examples/zedboard/taiga_wrapper.sv, line:27, parent:work@div_unit_core_wrapper
|vpiDefName:work@taiga_wrapper
|vpiFullName:work@taiga_wrapper
|vpiPort:
\_port: (sys_clk), line:28
|vpiName:sys_clk
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (sys_clk), line:28
|vpiName:sys_clk
|vpiFullName:work@taiga_wrapper.sys_clk
|vpiNetType:36
|vpiPort:
\_port: (ext_reset), line:29
|vpiName:ext_reset
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (ext_reset), line:29
|vpiName:ext_reset
|vpiFullName:work@taiga_wrapper.ext_reset
|vpiNetType:36
|vpiPort:
\_port: (DDR_addr), line:32
|vpiName:DDR_addr
|vpiDirection:3
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (DDR_addr), line:32
|vpiName:DDR_addr
|vpiFullName:work@taiga_wrapper.DDR_addr
|vpiPort:
\_port: (DDR_ba), line:33
|vpiName:DDR_ba
|vpiDirection:3
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (DDR_ba), line:33
|vpiName:DDR_ba
|vpiFullName:work@taiga_wrapper.DDR_ba
|vpiPort:
\_port: (DDR_cas_n), line:34
|vpiName:DDR_cas_n
|vpiDirection:3
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (DDR_cas_n), line:34
|vpiName:DDR_cas_n
|vpiFullName:work@taiga_wrapper.DDR_cas_n
|vpiPort:
\_port: (DDR_ck_n), line:35
|vpiName:DDR_ck_n
|vpiDirection:3
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (DDR_ck_n), line:35
|vpiName:DDR_ck_n
|vpiFullName:work@taiga_wrapper.DDR_ck_n
|vpiPort:
\_port: (DDR_ck_p), line:36
|vpiName:DDR_ck_p
|vpiDirection:3
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (DDR_ck_p), line:36
|vpiName:DDR_ck_p
|vpiFullName:work@taiga_wrapper.DDR_ck_p
|vpiPort:
\_port: (DDR_cke), line:37
|vpiName:DDR_cke
|vpiDirection:3
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (DDR_cke), line:37
|vpiName:DDR_cke
|vpiFullName:work@taiga_wrapper.DDR_cke
|vpiPort:
\_port: (DDR_cs_n), line:38
|vpiName:DDR_cs_n
|vpiDirection:3
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (DDR_cs_n), line:38
|vpiName:DDR_cs_n
|vpiFullName:work@taiga_wrapper.DDR_cs_n
|vpiPort:
\_port: (DDR_dm), line:39
|vpiName:DDR_dm
|vpiDirection:3
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (DDR_dm), line:39
|vpiName:DDR_dm
|vpiFullName:work@taiga_wrapper.DDR_dm
|vpiPort:
\_port: (DDR_dq), line:40
|vpiName:DDR_dq
|vpiDirection:3
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (DDR_dq), line:40
|vpiName:DDR_dq
|vpiFullName:work@taiga_wrapper.DDR_dq
|vpiPort:
\_port: (DDR_dqs_n), line:41
|vpiName:DDR_dqs_n
|vpiDirection:3
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (DDR_dqs_n), line:41
|vpiName:DDR_dqs_n
|vpiFullName:work@taiga_wrapper.DDR_dqs_n
|vpiPort:
\_port: (DDR_dqs_p), line:42
|vpiName:DDR_dqs_p
|vpiDirection:3
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (DDR_dqs_p), line:42
|vpiName:DDR_dqs_p
|vpiFullName:work@taiga_wrapper.DDR_dqs_p
|vpiPort:
\_port: (DDR_odt), line:43
|vpiName:DDR_odt
|vpiDirection:3
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (DDR_odt), line:43
|vpiName:DDR_odt
|vpiFullName:work@taiga_wrapper.DDR_odt
|vpiPort:
\_port: (DDR_ras_n), line:44
|vpiName:DDR_ras_n
|vpiDirection:3
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (DDR_ras_n), line:44
|vpiName:DDR_ras_n
|vpiFullName:work@taiga_wrapper.DDR_ras_n
|vpiPort:
\_port: (DDR_reset_n), line:45
|vpiName:DDR_reset_n
|vpiDirection:3
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (DDR_reset_n), line:45
|vpiName:DDR_reset_n
|vpiFullName:work@taiga_wrapper.DDR_reset_n
|vpiPort:
\_port: (DDR_we_n), line:46
|vpiName:DDR_we_n
|vpiDirection:3
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (DDR_we_n), line:46
|vpiName:DDR_we_n
|vpiFullName:work@taiga_wrapper.DDR_we_n
|vpiPort:
\_port: (FIXED_IO_ddr_vrn), line:47
|vpiName:FIXED_IO_ddr_vrn
|vpiDirection:3
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (FIXED_IO_ddr_vrn), line:47
|vpiName:FIXED_IO_ddr_vrn
|vpiFullName:work@taiga_wrapper.FIXED_IO_ddr_vrn
|vpiPort:
\_port: (FIXED_IO_ddr_vrp), line:48
|vpiName:FIXED_IO_ddr_vrp
|vpiDirection:3
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (FIXED_IO_ddr_vrp), line:48
|vpiName:FIXED_IO_ddr_vrp
|vpiFullName:work@taiga_wrapper.FIXED_IO_ddr_vrp
|vpiPort:
\_port: (FIXED_IO_mio), line:49
|vpiName:FIXED_IO_mio
|vpiDirection:3
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (FIXED_IO_mio), line:49
|vpiName:FIXED_IO_mio
|vpiFullName:work@taiga_wrapper.FIXED_IO_mio
|vpiPort:
\_port: (FIXED_IO_ps_clk), line:50
|vpiName:FIXED_IO_ps_clk
|vpiDirection:3
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (FIXED_IO_ps_clk), line:50
|vpiName:FIXED_IO_ps_clk
|vpiFullName:work@taiga_wrapper.FIXED_IO_ps_clk
|vpiPort:
\_port: (FIXED_IO_ps_porb), line:51
|vpiName:FIXED_IO_ps_porb
|vpiDirection:3
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (FIXED_IO_ps_porb), line:51
|vpiName:FIXED_IO_ps_porb
|vpiFullName:work@taiga_wrapper.FIXED_IO_ps_porb
|vpiPort:
\_port: (FIXED_IO_ps_srstb), line:52
|vpiName:FIXED_IO_ps_srstb
|vpiDirection:3
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (FIXED_IO_ps_srstb), line:52
|vpiName:FIXED_IO_ps_srstb
|vpiFullName:work@taiga_wrapper.FIXED_IO_ps_srstb
|vpiPort:
\_port: (sin), line:54
|vpiName:sin
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (sin), line:54
|vpiName:sin
|vpiFullName:work@taiga_wrapper.sin
|vpiNetType:36
|vpiPort:
\_port: (sout), line:55
|vpiName:sout
|vpiDirection:2
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (sout), line:55
|vpiName:sout
|vpiFullName:work@taiga_wrapper.sout
|vpiNetType:36
|vpiContAssign:
\_cont_assign: , line:75
|vpiRhs:
\_constant: , line:75
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiLhs:
\_ref_obj: (interrupt), line:75
|vpiName:interrupt
|vpiFullName:work@taiga_wrapper.interrupt
|vpiContAssign:
\_cont_assign: , line:195
|vpiRhs:
\_ref_obj: (clk), line:195
|vpiName:clk
|vpiFullName:work@taiga_wrapper.clk
|vpiLhs:
\_ref_obj: (axi_clk), line:195
|vpiName:axi_clk
|vpiFullName:work@taiga_wrapper.axi_clk
|vpiContAssign:
\_cont_assign: , line:197
|vpiRhs:
\_ref_obj: (processor_reset), line:197
|vpiName:processor_reset
|vpiFullName:work@taiga_wrapper.processor_reset
|vpiLhs:
\_ref_obj: (rst), line:197
|vpiName:rst
|vpiFullName:work@taiga_wrapper.rst
|vpiContAssign:
\_cont_assign: , line:200
|vpiRhs:
\_ref_obj: (bus_axi_arready), line:200
|vpiName:bus_axi_arready
|vpiFullName:work@taiga_wrapper.bus_axi_arready
|vpiLhs:
\_ref_obj: (m_axi.arready), line:200
|vpiName:m_axi.arready
|vpiFullName:work@taiga_wrapper.m_axi.arready
|vpiContAssign:
\_cont_assign: , line:201
|vpiRhs:
\_ref_obj: (m_axi.arvalid), line:201
|vpiName:m_axi.arvalid
|vpiFullName:work@taiga_wrapper.m_axi.arvalid
|vpiLhs:
\_ref_obj: (bus_axi_arvalid), line:201
|vpiName:bus_axi_arvalid
|vpiFullName:work@taiga_wrapper.bus_axi_arvalid
|vpiContAssign:
\_cont_assign: , line:202
|vpiRhs:
\_ref_obj: (m_axi.araddr), line:202
|vpiName:m_axi.araddr
|vpiFullName:work@taiga_wrapper.m_axi.araddr
|vpiLhs:
\_ref_obj: (bus_axi_araddr), line:202
|vpiName:bus_axi_araddr
|vpiFullName:work@taiga_wrapper.bus_axi_araddr
|vpiContAssign:
\_cont_assign: , line:206
|vpiRhs:
\_ref_obj: (m_axi.rready), line:206
|vpiName:m_axi.rready
|vpiFullName:work@taiga_wrapper.m_axi.rready
|vpiLhs:
\_ref_obj: (bus_axi_rready), line:206
|vpiName:bus_axi_rready
|vpiFullName:work@taiga_wrapper.bus_axi_rready
|vpiContAssign:
\_cont_assign: , line:207
|vpiRhs:
\_ref_obj: (bus_axi_rvalid), line:207
|vpiName:bus_axi_rvalid
|vpiFullName:work@taiga_wrapper.bus_axi_rvalid
|vpiLhs:
\_ref_obj: (m_axi.rvalid), line:207
|vpiName:m_axi.rvalid
|vpiFullName:work@taiga_wrapper.m_axi.rvalid
|vpiContAssign:
\_cont_assign: , line:208
|vpiRhs:
\_ref_obj: (bus_axi_rdata), line:208
|vpiName:bus_axi_rdata
|vpiFullName:work@taiga_wrapper.bus_axi_rdata
|vpiLhs:
\_ref_obj: (m_axi.rdata), line:208
|vpiName:m_axi.rdata
|vpiFullName:work@taiga_wrapper.m_axi.rdata
|vpiContAssign:
\_cont_assign: , line:209
|vpiRhs:
\_ref_obj: (bus_axi_rresp), line:209
|vpiName:bus_axi_rresp
|vpiFullName:work@taiga_wrapper.bus_axi_rresp
|vpiLhs:
\_ref_obj: (m_axi.rresp), line:209
|vpiName:m_axi.rresp
|vpiFullName:work@taiga_wrapper.m_axi.rresp
|vpiContAssign:
\_cont_assign: , line:213
|vpiRhs:
\_ref_obj: (bus_axi_awready), line:213
|vpiName:bus_axi_awready
|vpiFullName:work@taiga_wrapper.bus_axi_awready
|vpiLhs:
\_ref_obj: (m_axi.awready), line:213
|vpiName:m_axi.awready
|vpiFullName:work@taiga_wrapper.m_axi.awready
|vpiContAssign:
\_cont_assign: , line:214
|vpiRhs:
\_ref_obj: (m_axi.awaddr), line:214
|vpiName:m_axi.awaddr
|vpiFullName:work@taiga_wrapper.m_axi.awaddr
|vpiLhs:
\_ref_obj: (bus_axi_awaddr), line:214
|vpiName:bus_axi_awaddr
|vpiFullName:work@taiga_wrapper.bus_axi_awaddr
|vpiContAssign:
\_cont_assign: , line:215
|vpiRhs:
\_ref_obj: (m_axi.awvalid), line:215
|vpiName:m_axi.awvalid
|vpiFullName:work@taiga_wrapper.m_axi.awvalid
|vpiLhs:
\_ref_obj: (bus_axi_awvalid), line:215
|vpiName:bus_axi_awvalid
|vpiFullName:work@taiga_wrapper.bus_axi_awvalid
|vpiContAssign:
\_cont_assign: , line:219
|vpiRhs:
\_ref_obj: (bus_axi_wready), line:219
|vpiName:bus_axi_wready
|vpiFullName:work@taiga_wrapper.bus_axi_wready
|vpiLhs:
\_ref_obj: (m_axi.wready), line:219
|vpiName:m_axi.wready
|vpiFullName:work@taiga_wrapper.m_axi.wready
|vpiContAssign:
\_cont_assign: , line:220
|vpiRhs:
\_ref_obj: (m_axi.wvalid), line:220
|vpiName:m_axi.wvalid
|vpiFullName:work@taiga_wrapper.m_axi.wvalid
|vpiLhs:
\_ref_obj: (bus_axi_wvalid), line:220
|vpiName:bus_axi_wvalid
|vpiFullName:work@taiga_wrapper.bus_axi_wvalid
|vpiContAssign:
\_cont_assign: , line:221
|vpiRhs:
\_ref_obj: (m_axi.wdata), line:221
|vpiName:m_axi.wdata
|vpiFullName:work@taiga_wrapper.m_axi.wdata
|vpiLhs:
\_ref_obj: (bus_axi_wdata), line:221
|vpiName:bus_axi_wdata
|vpiFullName:work@taiga_wrapper.bus_axi_wdata
|vpiContAssign:
\_cont_assign: , line:222
|vpiRhs:
\_ref_obj: (m_axi.wstrb), line:222
|vpiName:m_axi.wstrb
|vpiFullName:work@taiga_wrapper.m_axi.wstrb
|vpiLhs:
\_ref_obj: (bus_axi_wstrb), line:222
|vpiName:bus_axi_wstrb
|vpiFullName:work@taiga_wrapper.bus_axi_wstrb
|vpiContAssign:
\_cont_assign: , line:225
|vpiRhs:
\_ref_obj: (m_axi.bready), line:225
|vpiName:m_axi.bready
|vpiFullName:work@taiga_wrapper.m_axi.bready
|vpiLhs:
\_ref_obj: (bus_axi_bready), line:225
|vpiName:bus_axi_bready
|vpiFullName:work@taiga_wrapper.bus_axi_bready
|vpiContAssign:
\_cont_assign: , line:226
|vpiRhs:
\_ref_obj: (bus_axi_bvalid), line:226
|vpiName:bus_axi_bvalid
|vpiFullName:work@taiga_wrapper.bus_axi_bvalid
|vpiLhs:
\_ref_obj: (m_axi.bvalid), line:226
|vpiName:m_axi.bvalid
|vpiFullName:work@taiga_wrapper.m_axi.bvalid
|vpiContAssign:
\_cont_assign: , line:227
|vpiRhs:
\_ref_obj: (bus_axi_bresp), line:227
|vpiName:bus_axi_bresp
|vpiFullName:work@taiga_wrapper.bus_axi_bresp
|vpiLhs:
\_ref_obj: (m_axi.bresp), line:227
|vpiName:m_axi.bresp
|vpiFullName:work@taiga_wrapper.m_axi.bresp
|vpiNet:
\_logic_net: (sys_clk), line:28
|vpiNet:
\_logic_net: (ext_reset), line:29
|vpiNet:
\_logic_net: (DDR_addr), line:32
|vpiNet:
\_logic_net: (DDR_ba), line:33
|vpiNet:
\_logic_net: (DDR_cas_n), line:34
|vpiNet:
\_logic_net: (DDR_ck_n), line:35
|vpiNet:
\_logic_net: (DDR_ck_p), line:36
|vpiNet:
\_logic_net: (DDR_cke), line:37
|vpiNet:
\_logic_net: (DDR_cs_n), line:38
|vpiNet:
\_logic_net: (DDR_dm), line:39
|vpiNet:
\_logic_net: (DDR_dq), line:40
|vpiNet:
\_logic_net: (DDR_dqs_n), line:41
|vpiNet:
\_logic_net: (DDR_dqs_p), line:42
|vpiNet:
\_logic_net: (DDR_odt), line:43
|vpiNet:
\_logic_net: (DDR_ras_n), line:44
|vpiNet:
\_logic_net: (DDR_reset_n), line:45
|vpiNet:
\_logic_net: (DDR_we_n), line:46
|vpiNet:
\_logic_net: (FIXED_IO_ddr_vrn), line:47
|vpiNet:
\_logic_net: (FIXED_IO_ddr_vrp), line:48
|vpiNet:
\_logic_net: (FIXED_IO_mio), line:49
|vpiNet:
\_logic_net: (FIXED_IO_ps_clk), line:50
|vpiNet:
\_logic_net: (FIXED_IO_ps_porb), line:51
|vpiNet:
\_logic_net: (FIXED_IO_ps_srstb), line:52
|vpiNet:
\_logic_net: (sin), line:54
|vpiNet:
\_logic_net: (sout), line:55
|vpiNet:
\_logic_net: (clk), line:63
|vpiName:clk
|vpiFullName:work@taiga_wrapper.clk
|vpiNetType:36
|vpiNet:
\_logic_net: (rst), line:64
|vpiName:rst
|vpiFullName:work@taiga_wrapper.rst
|vpiNetType:36
|vpiNet:
\_logic_net: (resetn), line:65
|vpiName:resetn
|vpiFullName:work@taiga_wrapper.resetn
|vpiNetType:36
|vpiNet:
\_logic_net: (interrupt), line:73
|vpiName:interrupt
|vpiFullName:work@taiga_wrapper.interrupt
|vpiNetType:36
|vpiNet:
\_logic_net: (mem_axi_araddr), line:78
|vpiName:mem_axi_araddr
|vpiFullName:work@taiga_wrapper.mem_axi_araddr
|vpiNetType:36
|vpiNet:
\_logic_net: (mem_axi_arburst), line:79
|vpiName:mem_axi_arburst
|vpiFullName:work@taiga_wrapper.mem_axi_arburst
|vpiNetType:36
|vpiNet:
\_logic_net: (mem_axi_arcache), line:80
|vpiName:mem_axi_arcache
|vpiFullName:work@taiga_wrapper.mem_axi_arcache
|vpiNetType:36
|vpiNet:
\_logic_net: (mem_axi_arid), line:81
|vpiName:mem_axi_arid
|vpiFullName:work@taiga_wrapper.mem_axi_arid
|vpiNetType:36
|vpiNet:
\_logic_net: (mem_axi_arlen), line:82
|vpiName:mem_axi_arlen
|vpiFullName:work@taiga_wrapper.mem_axi_arlen
|vpiNetType:36
|vpiNet:
\_logic_net: (mem_axi_arlock), line:83
|vpiName:mem_axi_arlock
|vpiFullName:work@taiga_wrapper.mem_axi_arlock
|vpiNetType:36
|vpiNet:
\_logic_net: (mem_axi_arprot), line:84
|vpiName:mem_axi_arprot
|vpiFullName:work@taiga_wrapper.mem_axi_arprot
|vpiNetType:36
|vpiNet:
\_logic_net: (mem_axi_arqos), line:85
|vpiName:mem_axi_arqos
|vpiFullName:work@taiga_wrapper.mem_axi_arqos
|vpiNetType:36
|vpiNet:
\_logic_net: (mem_axi_arready), line:86
|vpiName:mem_axi_arready
|vpiFullName:work@taiga_wrapper.mem_axi_arready
|vpiNetType:36
|vpiNet:
\_logic_net: (mem_axi_arregion), line:87
|vpiName:mem_axi_arregion
|vpiFullName:work@taiga_wrapper.mem_axi_arregion
|vpiNetType:36
|vpiNet:
\_logic_net: (mem_axi_arsize), line:88
|vpiName:mem_axi_arsize
|vpiFullName:work@taiga_wrapper.mem_axi_arsize
|vpiNetType:36
|vpiNet:
\_logic_net: (mem_axi_arvalid), line:89
|vpiName:mem_axi_arvalid
|vpiFullName:work@taiga_wrapper.mem_axi_arvalid
|vpiNetType:36
|vpiNet:
\_logic_net: (mem_axi_awaddr), line:90
|vpiName:mem_axi_awaddr
|vpiFullName:work@taiga_wrapper.mem_axi_awaddr
|vpiNetType:36
|vpiNet:
\_logic_net: (mem_axi_awburst), line:91
|vpiName:mem_axi_awburst
|vpiFullName:work@taiga_wrapper.mem_axi_awburst
|vpiNetType:36
|vpiNet:
\_logic_net: (mem_axi_awcache), line:92
|vpiName:mem_axi_awcache
|vpiFullName:work@taiga_wrapper.mem_axi_awcache
|vpiNetType:36
|vpiNet:
\_logic_net: (mem_axi_awid), line:93
|vpiName:mem_axi_awid
|vpiFullName:work@taiga_wrapper.mem_axi_awid
|vpiNetType:36
|vpiNet:
\_logic_net: (mem_axi_awlen), line:94
|vpiName:mem_axi_awlen
|vpiFullName:work@taiga_wrapper.mem_axi_awlen
|vpiNetType:36
|vpiNet:
\_logic_net: (mem_axi_awlock), line:95
|vpiName:mem_axi_awlock
|vpiFullName:work@taiga_wrapper.mem_axi_awlock
|vpiNetType:36
|vpiNet:
\_logic_net: (mem_axi_awprot), line:96
|vpiName:mem_axi_awprot
|vpiFullName:work@taiga_wrapper.mem_axi_awprot
|vpiNetType:36
|vpiNet:
\_logic_net: (mem_axi_awqos), line:97
|vpiName:mem_axi_awqos
|vpiFullName:work@taiga_wrapper.mem_axi_awqos
|vpiNetType:36
|vpiNet:
\_logic_net: (mem_axi_awready), line:98
|vpiName:mem_axi_awready
|vpiFullName:work@taiga_wrapper.mem_axi_awready
|vpiNetType:36
|vpiNet:
\_logic_net: (mem_axi_awregion), line:99
|vpiName:mem_axi_awregion
|vpiFullName:work@taiga_wrapper.mem_axi_awregion
|vpiNetType:36
|vpiNet:
\_logic_net: (mem_axi_awsize), line:100
|vpiName:mem_axi_awsize
|vpiFullName:work@taiga_wrapper.mem_axi_awsize
|vpiNetType:36
|vpiNet:
\_logic_net: (mem_axi_awvalid), line:101
|vpiName:mem_axi_awvalid
|vpiFullName:work@taiga_wrapper.mem_axi_awvalid
|vpiNetType:36
|vpiNet:
\_logic_net: (mem_axi_bid), line:102
|vpiName:mem_axi_bid
|vpiFullName:work@taiga_wrapper.mem_axi_bid
|vpiNetType:36
|vpiNet:
\_logic_net: (mem_axi_bready), line:103
|vpiName:mem_axi_bready
|vpiFullName:work@taiga_wrapper.mem_axi_bready
|vpiNetType:36
|vpiNet:
\_logic_net: (mem_axi_bresp), line:104
|vpiName:mem_axi_bresp
|vpiFullName:work@taiga_wrapper.mem_axi_bresp
|vpiNetType:36
|vpiNet:
\_logic_net: (mem_axi_bvalid), line:105
|vpiName:mem_axi_bvalid
|vpiFullName:work@taiga_wrapper.mem_axi_bvalid
|vpiNetType:36
|vpiNet:
\_logic_net: (mem_axi_rdata), line:106
|vpiName:mem_axi_rdata
|vpiFullName:work@taiga_wrapper.mem_axi_rdata
|vpiNetType:36
|vpiNet:
\_logic_net: (mem_axi_rid), line:107
|vpiName:mem_axi_rid
|vpiFullName:work@taiga_wrapper.mem_axi_rid
|vpiNetType:36
|vpiNet:
\_logic_net: (mem_axi_rlast), line:108
|vpiName:mem_axi_rlast
|vpiFullName:work@taiga_wrapper.mem_axi_rlast
|vpiNetType:36
|vpiNet:
\_logic_net: (mem_axi_rready), line:109
|vpiName:mem_axi_rready
|vpiFullName:work@taiga_wrapper.mem_axi_rready
|vpiNetType:36
|vpiNet:
\_logic_net: (mem_axi_rresp), line:110
|vpiName:mem_axi_rresp
|vpiFullName:work@taiga_wrapper.mem_axi_rresp
|vpiNetType:36
|vpiNet:
\_logic_net: (mem_axi_rvalid), line:111
|vpiName:mem_axi_rvalid
|vpiFullName:work@taiga_wrapper.mem_axi_rvalid
|vpiNetType:36
|vpiNet:
\_logic_net: (mem_axi_wdata), line:112
|vpiName:mem_axi_wdata
|vpiFullName:work@taiga_wrapper.mem_axi_wdata
|vpiNetType:36
|vpiNet:
\_logic_net: (mem_axi_wlast), line:113
|vpiName:mem_axi_wlast
|vpiFullName:work@taiga_wrapper.mem_axi_wlast
|vpiNetType:36
|vpiNet:
\_logic_net: (mem_axi_wready), line:114
|vpiName:mem_axi_wready
|vpiFullName:work@taiga_wrapper.mem_axi_wready
|vpiNetType:36
|vpiNet:
\_logic_net: (mem_axi_wstrb), line:115
|vpiName:mem_axi_wstrb
|vpiFullName:work@taiga_wrapper.mem_axi_wstrb
|vpiNetType:36
|vpiNet:
\_logic_net: (mem_axi_wvalid), line:116
|vpiName:mem_axi_wvalid
|vpiFullName:work@taiga_wrapper.mem_axi_wvalid
|vpiNetType:36
|vpiNet:
\_logic_net: (mem_axi_wid), line:117
|vpiName:mem_axi_wid
|vpiFullName:work@taiga_wrapper.mem_axi_wid
|vpiNetType:36
|vpiNet:
\_logic_net: (ACLK), line:119
|vpiName:ACLK
|vpiFullName:work@taiga_wrapper.ACLK
|vpiNetType:36
|vpiNet:
\_logic_net: (bus_axi_araddr), line:120
|vpiName:bus_axi_araddr
|vpiFullName:work@taiga_wrapper.bus_axi_araddr
|vpiNetType:36
|vpiNet:
\_logic_net: (bus_axi_arready), line:121
|vpiName:bus_axi_arready
|vpiFullName:work@taiga_wrapper.bus_axi_arready
|vpiNetType:36
|vpiNet:
\_logic_net: (bus_axi_arvalid), line:122
|vpiName:bus_axi_arvalid
|vpiFullName:work@taiga_wrapper.bus_axi_arvalid
|vpiNetType:36
|vpiNet:
\_logic_net: (bus_axi_awaddr), line:123
|vpiName:bus_axi_awaddr
|vpiFullName:work@taiga_wrapper.bus_axi_awaddr
|vpiNetType:36
|vpiNet:
\_logic_net: (bus_axi_awready), line:124
|vpiName:bus_axi_awready
|vpiFullName:work@taiga_wrapper.bus_axi_awready
|vpiNetType:36
|vpiNet:
\_logic_net: (bus_axi_awvalid), line:125
|vpiName:bus_axi_awvalid
|vpiFullName:work@taiga_wrapper.bus_axi_awvalid
|vpiNetType:36
|vpiNet:
\_logic_net: (bus_axi_bready), line:126
|vpiName:bus_axi_bready
|vpiFullName:work@taiga_wrapper.bus_axi_bready
|vpiNetType:36
|vpiNet:
\_logic_net: (bus_axi_bresp), line:127
|vpiName:bus_axi_bresp
|vpiFullName:work@taiga_wrapper.bus_axi_bresp
|vpiNetType:36
|vpiNet:
\_logic_net: (bus_axi_bvalid), line:128
|vpiName:bus_axi_bvalid
|vpiFullName:work@taiga_wrapper.bus_axi_bvalid
|vpiNetType:36
|vpiNet:
\_logic_net: (bus_axi_rdata), line:129
|vpiName:bus_axi_rdata
|vpiFullName:work@taiga_wrapper.bus_axi_rdata
|vpiNetType:36
|vpiNet:
\_logic_net: (bus_axi_rready), line:130
|vpiName:bus_axi_rready
|vpiFullName:work@taiga_wrapper.bus_axi_rready
|vpiNetType:36
|vpiNet:
\_logic_net: (bus_axi_rresp), line:131
|vpiName:bus_axi_rresp
|vpiFullName:work@taiga_wrapper.bus_axi_rresp
|vpiNetType:36
|vpiNet:
\_logic_net: (bus_axi_rvalid), line:132
|vpiName:bus_axi_rvalid
|vpiFullName:work@taiga_wrapper.bus_axi_rvalid
|vpiNetType:36
|vpiNet:
\_logic_net: (bus_axi_wdata), line:133
|vpiName:bus_axi_wdata
|vpiFullName:work@taiga_wrapper.bus_axi_wdata
|vpiNetType:36
|vpiNet:
\_logic_net: (bus_axi_wready), line:134
|vpiName:bus_axi_wready
|vpiFullName:work@taiga_wrapper.bus_axi_wready
|vpiNetType:36
|vpiNet:
\_logic_net: (bus_axi_wstrb), line:135
|vpiName:bus_axi_wstrb
|vpiFullName:work@taiga_wrapper.bus_axi_wstrb
|vpiNetType:36
|vpiNet:
\_logic_net: (bus_axi_wvalid), line:136
|vpiName:bus_axi_wvalid
|vpiFullName:work@taiga_wrapper.bus_axi_wvalid
|vpiNetType:36
|vpiNet:
\_logic_net: (processor_reset), line:138
|vpiName:processor_reset
|vpiFullName:work@taiga_wrapper.processor_reset
|vpiNetType:36
|vpiNet:
\_logic_net: (axi_arready), line:142
|vpiName:axi_arready
|vpiFullName:work@taiga_wrapper.axi_arready
|vpiNetType:36
|vpiNet:
\_logic_net: (axi_arvalid), line:143
|vpiName:axi_arvalid
|vpiFullName:work@taiga_wrapper.axi_arvalid
|vpiNetType:36
|vpiNet:
\_logic_net: (axi_araddr), line:144
|vpiName:axi_araddr
|vpiFullName:work@taiga_wrapper.axi_araddr
|vpiNetType:36
|vpiNet:
\_logic_net: (axi_arlen), line:145
|vpiName:axi_arlen
|vpiFullName:work@taiga_wrapper.axi_arlen
|vpiNetType:36
|vpiNet:
\_logic_net: (axi_arsize), line:146
|vpiName:axi_arsize
|vpiFullName:work@taiga_wrapper.axi_arsize
|vpiNetType:36
|vpiNet:
\_logic_net: (axi_arburst), line:147
|vpiName:axi_arburst
|vpiFullName:work@taiga_wrapper.axi_arburst
|vpiNetType:36
|vpiNet:
\_logic_net: (axi_arprot), line:148
|vpiName:axi_arprot
|vpiFullName:work@taiga_wrapper.axi_arprot
|vpiNetType:36
|vpiNet:
\_logic_net: (axi_arcache), line:149
|vpiName:axi_arcache
|vpiFullName:work@taiga_wrapper.axi_arcache
|vpiNetType:36
|vpiNet:
\_logic_net: (axi_arid), line:150
|vpiName:axi_arid
|vpiFullName:work@taiga_wrapper.axi_arid
|vpiNetType:36
|vpiNet:
\_logic_net: (axi_arlock), line:151
|vpiName:axi_arlock
|vpiFullName:work@taiga_wrapper.axi_arlock
|vpiNetType:36
|vpiNet:
\_logic_net: (axi_arqos), line:152
|vpiName:axi_arqos
|vpiFullName:work@taiga_wrapper.axi_arqos
|vpiNetType:36
|vpiNet:
\_logic_net: (axi_rready), line:155
|vpiName:axi_rready
|vpiFullName:work@taiga_wrapper.axi_rready
|vpiNetType:36
|vpiNet:
\_logic_net: (axi_rvalid), line:156
|vpiName:axi_rvalid
|vpiFullName:work@taiga_wrapper.axi_rvalid
|vpiNetType:36
|vpiNet:
\_logic_net: (axi_rdata), line:157
|vpiName:axi_rdata
|vpiFullName:work@taiga_wrapper.axi_rdata
|vpiNetType:36
|vpiNet:
\_logic_net: (axi_rresp), line:158
|vpiName:axi_rresp
|vpiFullName:work@taiga_wrapper.axi_rresp
|vpiNetType:36
|vpiNet:
\_logic_net: (axi_rlast), line:159
|vpiName:axi_rlast
|vpiFullName:work@taiga_wrapper.axi_rlast
|vpiNetType:36
|vpiNet:
\_logic_net: (axi_rid), line:160
|vpiName:axi_rid
|vpiFullName:work@taiga_wrapper.axi_rid
|vpiNetType:36
|vpiNet:
\_logic_net: (axi_awready), line:163
|vpiName:axi_awready
|vpiFullName:work@taiga_wrapper.axi_awready
|vpiNetType:36
|vpiNet:
\_logic_net: (axi_awvalid), line:164
|vpiName:axi_awvalid
|vpiFullName:work@taiga_wrapper.axi_awvalid
|vpiNetType:36
|vpiNet:
\_logic_net: (axi_awaddr), line:165
|vpiName:axi_awaddr
|vpiFullName:work@taiga_wrapper.axi_awaddr
|vpiNetType:36
|vpiNet:
\_logic_net: (axi_awlen), line:166
|vpiName:axi_awlen
|vpiFullName:work@taiga_wrapper.axi_awlen
|vpiNetType:36
|vpiNet:
\_logic_net: (axi_awsize), line:167
|vpiName:axi_awsize
|vpiFullName:work@taiga_wrapper.axi_awsize
|vpiNetType:36
|vpiNet:
\_logic_net: (axi_awburst), line:168
|vpiName:axi_awburst
|vpiFullName:work@taiga_wrapper.axi_awburst
|vpiNetType:36
|vpiNet:
\_logic_net: (axi_awlock), line:169
|vpiName:axi_awlock
|vpiFullName:work@taiga_wrapper.axi_awlock
|vpiNetType:36
|vpiNet:
\_logic_net: (axi_awqos), line:170
|vpiName:axi_awqos
|vpiFullName:work@taiga_wrapper.axi_awqos
|vpiNetType:36
|vpiNet:
\_logic_net: (axi_awid), line:171
|vpiName:axi_awid
|vpiFullName:work@taiga_wrapper.axi_awid
|vpiNetType:36
|vpiNet:
\_logic_net: (axi_awcache), line:173
|vpiName:axi_awcache
|vpiFullName:work@taiga_wrapper.axi_awcache
|vpiNetType:36
|vpiNet:
\_logic_net: (axi_awprot), line:174
|vpiName:axi_awprot
|vpiFullName:work@taiga_wrapper.axi_awprot
|vpiNetType:36
|vpiNet:
\_logic_net: (axi_wready), line:177
|vpiName:axi_wready
|vpiFullName:work@taiga_wrapper.axi_wready
|vpiNetType:36
|vpiNet:
\_logic_net: (axi_wvalid), line:178
|vpiName:axi_wvalid
|vpiFullName:work@taiga_wrapper.axi_wvalid
|vpiNetType:36
|vpiNet:
\_logic_net: (axi_wdata), line:179
|vpiName:axi_wdata
|vpiFullName:work@taiga_wrapper.axi_wdata
|vpiNetType:36
|vpiNet:
\_logic_net: (axi_wstrb), line:180
|vpiName:axi_wstrb
|vpiFullName:work@taiga_wrapper.axi_wstrb
|vpiNetType:36
|vpiNet:
\_logic_net: (axi_wlast), line:181
|vpiName:axi_wlast
|vpiFullName:work@taiga_wrapper.axi_wlast
|vpiNetType:36
|vpiNet:
\_logic_net: (axi_wid), line:182
|vpiName:axi_wid
|vpiFullName:work@taiga_wrapper.axi_wid
|vpiNetType:36
|vpiNet:
\_logic_net: (axi_bready), line:186
|vpiName:axi_bready
|vpiFullName:work@taiga_wrapper.axi_bready
|vpiNetType:36
|vpiNet:
\_logic_net: (axi_bvalid), line:187
|vpiName:axi_bvalid
|vpiFullName:work@taiga_wrapper.axi_bvalid
|vpiNetType:36
|vpiNet:
\_logic_net: (axi_bresp), line:188
|vpiName:axi_bresp
|vpiFullName:work@taiga_wrapper.axi_bresp
|vpiNetType:36
|vpiNet:
\_logic_net: (axi_bid), line:189
|vpiName:axi_bid
|vpiFullName:work@taiga_wrapper.axi_bid
|vpiNetType:36
|vpiNet:
\_logic_net: (axi_clk), line:192
|vpiName:axi_clk
|vpiFullName:work@taiga_wrapper.axi_clk
|vpiNetType:36
|vpiNet:
\_logic_net: (processor_clk), line:193
|vpiName:processor_clk
|vpiFullName:work@taiga_wrapper.processor_clk
|vpiNetType:36
|vpiTypedef:
\_struct_typespec: (alu_inputs_t), line:301
|vpiTypedef:
\_enum_typespec: (alu_logic_op_t), line:84
|vpiTypedef:
\_enum_typespec: (alu_op_t), line:91
|vpiTypedef:
\_enum_typespec: (alu_rs1_op_t), line:97
|vpiTypedef:
\_enum_typespec: (alu_rs2_op_t), line:104
|vpiTypedef:
\_struct_typespec: (amo_alu_inputs_t), line:356
|vpiTypedef:
\_struct_typespec: (amo_details_t), line:362
|vpiTypedef:
\_enum_typespec: (amo_t), line:354
|vpiTypedef:
\_struct_typespec: (branch_inputs_t), line:313
|vpiTypedef:
\_logic_typespec: (branch_predictor_metadata_t), line:32
|vpiTypedef:
\_struct_typespec: (branch_results_t), line:330
|vpiTypedef:
\_enum_typespec: (bus_type_t), line:86
|vpiTypedef:
\_struct_typespec: (csr_inputs_t), line:396
|vpiTypedef:
\_enum_typespec: (csr_op_t), line:218
|vpiTypedef:
\_enum_typespec: (csr_t), line:201
|vpiTypedef:
\_struct_typespec: (data_access_shared_inputs_t), line:427
|vpiTypedef:
\_struct_typespec: (div_inputs_t), line:389
|vpiTypedef:
\_enum_typespec: (div_type), line:66
|vpiTypedef:
\_enum_typespec: (exception_code_t), line:245
|vpiTypedef:
\_struct_typespec: (exception_packet_t), line:263
|vpiTypedef:
\_struct_typespec: (fetch_buffer_packet_t), line:276
|vpiTypedef:
\_enum_typespec: (fifo_type_t), line:440
|vpiTypedef:
\_enum_typespec: (fn3_arith_t), line:76
|vpiTypedef:
\_enum_typespec: (fn3_branch_t), line:126
|vpiTypedef:
\_enum_typespec: (fn3_csr_t), line:212
|vpiTypedef:
\_enum_typespec: (fn3_ls_t), line:115
|vpiTypedef:
\_enum_typespec: (fn3_mul_div_t), line:138
|vpiTypedef:
\_struct_typespec: (gc_inputs_t), line:404
|vpiTypedef:
\_struct_typespec: (inflight_instruction_packet), line:271
|vpiTypedef:
\_logic_typespec: (instruction_id_t), line:30
|vpiTypedef:
\_enum_typespec: (interrupt_code_t), line:261
|vpiTypedef:
\_struct_typespec: (l2_data_attributes_t), line:68
|vpiTypedef:
\_struct_typespec: (l2_mem_request_t), line:58
|vpiTypedef:
\_struct_typespec: (l2_mem_return_data_t), line:75
|vpiTypedef:
\_struct_typespec: (l2_request_t), line:49
|vpiTypedef:
\_struct_typespec: (l2_return_data_t), line:81
|vpiTypedef:
\_struct_typespec: (load_store_inputs_t), line:369
|vpiTypedef:
\_struct_typespec: (mul_inputs_t), line:383
|vpiTypedef:
\_enum_typespec: (opcodes_t), line:48
|vpiTypedef:
\_enum_typespec: (opcodes_trimmed_t), line:65
|vpiTypedef:
\_struct_typespec: (simulation_named_regfile), line:476
|vpiTypedef:
\_struct_typespec: (taiga_trace_events_t), line:442
|vpiTypedef:
\_struct_typespec: (to_l1_arbiter_packet), line:418
|vpiTypedef:
\_struct_typespec: (trace_outputs_t), line:469
|vpiTypedef:
\_logic_typespec: (unit_id_t), line:31
|vpiTypedef:
\_struct_typespec: (unit_writeback_t), line:295
|vpiTypedef:
\_enum_typespec: (vm_t), line:223
|vpiParamAssign:
\_param_assign: , line:60
|vpiRhs:
\_constant: , line:60
|vpiConstType:7
|vpiDecompile:16
|vpiSize:32
|INT:16
|vpiLhs:
\_parameter: (SCRATCH_MEM_KB), line:60
|vpiName:SCRATCH_MEM_KB
|vpiParamAssign:
\_param_assign: , line:61
|vpiRhs:
\_constant: , line:61
|vpiDecompile:4096
|INT:4096
|vpiLhs:
\_parameter: (MEM_LINES), line:61
|vpiName:MEM_LINES
|vpiParameter:
\_parameter: (SCRATCH_MEM_KB), line:60
|vpiParameter:
\_parameter: (MEM_LINES), line:61
|uhdmallModules:
\_module: work@tlb_lut_ram, file:third_party/cores/taiga/core/tlb_lut_ram.sv, line:26, parent:work@div_unit_core_wrapper
|vpiDefName:work@tlb_lut_ram
|vpiFullName:work@tlb_lut_ram
|vpiProcess:
\_always: , line:91
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:91
|vpiCondition:
\_operation: , line:91
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:91
|vpiName:clk
|vpiFullName:work@tlb_lut_ram.clk
|vpiStmt:
\_begin: , line:91
|vpiFullName:work@tlb_lut_ram
|vpiStmt:
\_if_else: , line:92
|vpiCondition:
\_ref_obj: (rst), line:92
|vpiName:rst
|vpiFullName:work@tlb_lut_ram.rst
|vpiStmt:
\_assignment: , line:93
|vpiOpType:82
|vpiLhs:
\_ref_obj: (flush_in_progress), line:93
|vpiName:flush_in_progress
|vpiFullName:work@tlb_lut_ram.flush_in_progress
|vpiRhs:
\_constant: , line:93
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiElseStmt:
\_if_else: , line:94
|vpiCondition:
\_ref_obj: (tlb.flush_complete), line:94
|vpiName:tlb.flush_complete
|vpiFullName:work@tlb_lut_ram.tlb.flush_complete
|vpiStmt:
\_assignment: , line:95
|vpiOpType:82
|vpiLhs:
\_ref_obj: (flush_in_progress), line:95
|vpiName:flush_in_progress
|vpiFullName:work@tlb_lut_ram.flush_in_progress
|vpiRhs:
\_constant: , line:95
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiElseStmt:
\_if_stmt: , line:96
|vpiCondition:
\_ref_obj: (tlb.flush), line:96
|vpiName:tlb.flush
|vpiFullName:work@tlb_lut_ram.tlb.flush
|vpiStmt:
\_assignment: , line:97
|vpiOpType:82
|vpiLhs:
\_ref_obj: (flush_in_progress), line:97
|vpiName:flush_in_progress
|vpiFullName:work@tlb_lut_ram.flush_in_progress
|vpiRhs:
\_constant: , line:97
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiProcess:
\_always: , line:100
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:100
|vpiCondition:
\_operation: , line:100
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:100
|vpiName:clk
|vpiFullName:work@tlb_lut_ram.clk
|vpiStmt:
\_begin: , line:100
|vpiFullName:work@tlb_lut_ram
|vpiStmt:
\_if_else: , line:101
|vpiCondition:
\_ref_obj: (rst), line:101
|vpiName:rst
|vpiFullName:work@tlb_lut_ram.rst
|vpiStmt:
\_assignment: , line:102
|vpiOpType:82
|vpiLhs:
\_ref_obj: (flush_addr), line:102
|vpiName:flush_addr
|vpiFullName:work@tlb_lut_ram.flush_addr
|vpiRhs:
\_constant: , line:102
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiElseStmt:
\_if_stmt: , line:103
|vpiCondition:
\_ref_obj: (flush_in_progress), line:103
|vpiName:flush_in_progress
|vpiFullName:work@tlb_lut_ram.flush_in_progress
|vpiStmt:
\_assignment: , line:104
|vpiOpType:82
|vpiLhs:
\_ref_obj: (flush_addr), line:104
|vpiName:flush_addr
|vpiFullName:work@tlb_lut_ram.flush_addr
|vpiRhs:
\_operation: , line:104
|vpiOpType:24
|vpiOperand:
\_ref_obj: (flush_addr), line:104
|vpiName:flush_addr
|vpiFullName:work@tlb_lut_ram.flush_addr
|vpiOperand:
\_constant: , line:104
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiProcess:
\_always: , line:107
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:107
|vpiCondition:
\_operation: , line:107
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:107
|vpiName:clk
|vpiFullName:work@tlb_lut_ram.clk
|vpiStmt:
\_begin: , line:107
|vpiFullName:work@tlb_lut_ram
|vpiStmt:
\_if_else: , line:108
|vpiCondition:
\_ref_obj: (rst), line:108
|vpiName:rst
|vpiFullName:work@tlb_lut_ram.rst
|vpiStmt:
\_assignment: , line:109
|vpiOpType:82
|vpiLhs:
\_ref_obj: (tlb.flush_complete), line:109
|vpiName:tlb.flush_complete
|vpiFullName:work@tlb_lut_ram.tlb.flush_complete
|vpiRhs:
\_constant: , line:109
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiElseStmt:
\_assignment: , line:111
|vpiOpType:82
|vpiLhs:
\_ref_obj: (tlb.flush_complete), line:111
|vpiName:tlb.flush_complete
|vpiFullName:work@tlb_lut_ram.tlb.flush_complete
|vpiRhs:
\_operation: , line:111
|vpiOpType:14
|vpiOperand:
\_ref_obj: (flush_addr), line:111
|vpiName:flush_addr
|vpiFullName:work@tlb_lut_ram.flush_addr
|vpiOperand:
\_operation: , line:111
|vpiOpType:11
|vpiOperand:
\_ref_obj: (DEPTH), line:111
|vpiName:DEPTH
|vpiFullName:work@tlb_lut_ram.DEPTH
|vpiOperand:
\_constant: , line:111
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiProcess:
\_always: , line:115
|vpiAlwaysType:2
|vpiStmt:
\_begin: , line:115
|vpiFullName:work@tlb_lut_ram
|vpiStmt:
\_for_stmt: , line:116
|vpiFullName:work@tlb_lut_ram
|vpiCondition:
\_operation: , line:116
|vpiOpType:20
|vpiOperand:
\_ref_obj: (i), line:116
|vpiName:i
|vpiFullName:work@tlb_lut_ram.i
|vpiOperand:
\_ref_obj: (WAYS), line:116
|vpiName:WAYS
|vpiFullName:work@tlb_lut_ram.WAYS
|vpiForInitStmt:
\_assign_stmt:
|vpiRhs:
\_constant: , line:116
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiLhs:
\_int_var: (i), line:116
|vpiName:i
|vpiFullName:work@tlb_lut_ram.i
|vpiForIncStmt:
\_operation: , line:116
|vpiOpType:82
|vpiOperand:
\_ref_obj: (i), line:116
|vpiName:i
|vpiStmt:
\_begin: , line:116
|vpiFullName:work@tlb_lut_ram
|vpiStmt:
\_assignment: , line:117
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_bit_select: (tag_hit), line:117
|vpiName:tag_hit
|vpiFullName:work@tlb_lut_ram.tag_hit
|vpiIndex:
\_ref_obj: (i), line:117
|vpiName:i
|vpiRhs:
\_operation: , line:117
|vpiOpType:14
|vpiOperand:
\_operation: , line:117
|vpiOpType:33
|vpiOperand:
\_bit_select: (ram_data.valid), line:117
|vpiName:ram_data.valid
|vpiIndex:
\_ref_obj: (i), line:117
|vpiName:i
|vpiOperand:
\_bit_select: (ram_data.tag), line:117
|vpiName:ram_data.tag
|vpiIndex:
\_ref_obj: (i), line:117
|vpiName:i
|vpiOperand:
\_operation: , line:117
|vpiOpType:33
|vpiOperand:
\_constant: , line:117
|vpiConstType:3
|vpiDecompile:'b1
|vpiSize:1
|BIN:1
|vpiOperand:
\_ref_obj: (virtual_tag), line:117
|vpiName:virtual_tag
|vpiFullName:work@tlb_lut_ram.virtual_tag
|vpiProcess:
\_always: , line:121
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:121
|vpiCondition:
\_operation: , line:121
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:121
|vpiName:clk
|vpiFullName:work@tlb_lut_ram.clk
|vpiStmt:
\_begin: , line:121
|vpiFullName:work@tlb_lut_ram
|vpiStmt:
\_if_else: , line:122
|vpiCondition:
\_ref_obj: (rst), line:122
|vpiName:rst
|vpiFullName:work@tlb_lut_ram.rst
|vpiStmt:
\_assignment: , line:123
|vpiOpType:82
|vpiLhs:
\_ref_obj: (mmu.new_request), line:123
|vpiName:mmu.new_request
|vpiFullName:work@tlb_lut_ram.mmu.new_request
|vpiRhs:
\_constant: , line:123
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiElseStmt:
\_if_else: , line:124
|vpiCondition:
\_ref_obj: (mmu.write_entry), line:124
|vpiName:mmu.write_entry
|vpiFullName:work@tlb_lut_ram.mmu.write_entry
|vpiStmt:
\_assignment: , line:125
|vpiOpType:82
|vpiLhs:
\_ref_obj: (mmu.new_request), line:125
|vpiName:mmu.new_request
|vpiFullName:work@tlb_lut_ram.mmu.new_request
|vpiRhs:
\_constant: , line:125
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiElseStmt:
\_if_stmt: , line:126
|vpiCondition:
\_operation: , line:126
|vpiOpType:28
|vpiOperand:
\_operation: , line:126
|vpiOpType:28
|vpiOperand:
\_ref_obj: (tlb_on), line:126
|vpiName:tlb_on
|vpiFullName:work@tlb_lut_ram.tlb_on
|vpiOperand:
\_operation: , line:126
|vpiOpType:4
|vpiOperand:
\_ref_obj: (hit), line:126
|vpiName:hit
|vpiFullName:work@tlb_lut_ram.hit
|vpiOperand:
\_ref_obj: (tlb.new_request), line:126
|vpiName:tlb.new_request
|vpiFullName:work@tlb_lut_ram.tlb.new_request
|vpiStmt:
\_assignment: , line:127
|vpiOpType:82
|vpiLhs:
\_ref_obj: (mmu.new_request), line:127
|vpiName:mmu.new_request
|vpiFullName:work@tlb_lut_ram.mmu.new_request
|vpiRhs:
\_constant: , line:127
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiProcess:
\_always: , line:137
|vpiAlwaysType:2
|vpiStmt:
\_begin: , line:137
|vpiFullName:work@tlb_lut_ram
|vpiStmt:
\_assignment: , line:138
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_part_select: , line:138, parent:tlb.physical_address
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (tlb.physical_address)
|vpiLeftRange:
\_constant: , line:138
|vpiConstType:7
|vpiDecompile:11
|vpiSize:32
|INT:11
|vpiRightRange:
\_constant: , line:138
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiRhs:
\_ref_obj: (tlb.virtual_address), line:138
|vpiName:tlb.virtual_address
|vpiFullName:work@tlb_lut_ram.tlb.virtual_address
|vpiStmt:
\_assignment: , line:139
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_part_select: , line:139, parent:tlb.physical_address
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (tlb.physical_address)
|vpiLeftRange:
\_constant: , line:139
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:139
|vpiConstType:7
|vpiDecompile:12
|vpiSize:32
|INT:12
|vpiRhs:
\_ref_obj: (tlb.virtual_address), line:139
|vpiName:tlb.virtual_address
|vpiFullName:work@tlb_lut_ram.tlb.virtual_address
|vpiStmt:
\_for_stmt: , line:140
|vpiFullName:work@tlb_lut_ram
|vpiCondition:
\_operation: , line:140
|vpiOpType:20
|vpiOperand:
\_ref_obj: (i), line:140
|vpiName:i
|vpiFullName:work@tlb_lut_ram.i
|vpiOperand:
\_ref_obj: (WAYS), line:140
|vpiName:WAYS
|vpiFullName:work@tlb_lut_ram.WAYS
|vpiForInitStmt:
\_assign_stmt:
|vpiRhs:
\_constant: , line:140
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiLhs:
\_int_var: (i), line:140
|vpiName:i
|vpiFullName:work@tlb_lut_ram.i
|vpiForIncStmt:
\_operation: , line:140
|vpiOpType:82
|vpiOperand:
\_ref_obj: (i), line:140
|vpiName:i
|vpiStmt:
\_begin: , line:140
|vpiFullName:work@tlb_lut_ram
|vpiStmt:
\_if_stmt: , line:141
|vpiCondition:
\_operation: , line:141
|vpiOpType:28
|vpiOperand:
\_bit_select: (tag_hit), line:141
|vpiName:tag_hit
|vpiFullName:work@tlb_lut_ram.tag_hit
|vpiIndex:
\_ref_obj: (i), line:141
|vpiName:i
|vpiOperand:
\_ref_obj: (tlb_on), line:141
|vpiName:tlb_on
|vpiFullName:work@tlb_lut_ram.tlb_on
|vpiStmt:
\_assignment: , line:141
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_part_select: , line:141, parent:tlb.physical_address
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (tlb.physical_address)
|vpiLeftRange:
\_constant: , line:141
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:141
|vpiConstType:7
|vpiDecompile:12
|vpiSize:32
|INT:12
|vpiRhs:
\_bit_select: (ram_data.phys_addr), line:141
|vpiName:ram_data.phys_addr
|vpiFullName:work@tlb_lut_ram.ram_data.phys_addr
|vpiIndex:
\_ref_obj: (i), line:141
|vpiName:i
|vpiPort:
\_port: (clk), line:31
|vpiName:clk
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (clk), line:31
|vpiName:clk
|vpiFullName:work@tlb_lut_ram.clk
|vpiNetType:36
|vpiPort:
\_port: (rst), line:32
|vpiName:rst
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (rst), line:32
|vpiName:rst
|vpiFullName:work@tlb_lut_ram.rst
|vpiNetType:36
|vpiPort:
\_port: (tlb_on), line:33
|vpiName:tlb_on
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (tlb_on), line:33
|vpiName:tlb_on
|vpiFullName:work@tlb_lut_ram.tlb_on
|vpiNetType:36
|vpiPort:
\_port: (asid), line:34
|vpiName:asid
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (asid), line:34
|vpiName:asid
|vpiFullName:work@tlb_lut_ram.asid
|vpiNetType:36
|vpiPort:
\_port: (mmu), line:35
|vpiName:mmu
|vpiDirection:5
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_modport: (tlb)
|vpiPort:
\_port: (tlb), line:36
|vpiName:tlb
|vpiDirection:5
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_modport: (tlb)
|vpiContAssign:
\_cont_assign: , line:69
|vpiRhs:
\_ref_obj: (tlb.virtual_address), line:69
|vpiName:tlb.virtual_address
|vpiFullName:work@tlb_lut_ram.tlb.virtual_address
|vpiLhs:
\_ref_obj: (virtual_tag), line:69
|vpiName:virtual_tag
|vpiFullName:work@tlb_lut_ram.virtual_tag
|vpiContAssign:
\_cont_assign: , line:70
|vpiRhs:
\_ref_obj: (tlb.virtual_address), line:70
|vpiName:tlb.virtual_address
|vpiFullName:work@tlb_lut_ram.tlb.virtual_address
|vpiLhs:
\_ref_obj: (tlb_read_addr), line:70
|vpiName:tlb_read_addr
|vpiFullName:work@tlb_lut_ram.tlb_read_addr
|vpiContAssign:
\_cont_assign: , line:72
|vpiRhs:
\_operation: , line:72
|vpiOpType:32
|vpiOperand:
\_ref_obj: (tlb.flush), line:72
|vpiName:tlb.flush
|vpiFullName:work@tlb_lut_ram.tlb.flush
|vpiOperand:
\_ref_obj: (flush_addr), line:72
|vpiName:flush_addr
|vpiFullName:work@tlb_lut_ram.flush_addr
|vpiOperand:
\_ref_obj: (tlb_read_addr), line:72
|vpiName:tlb_read_addr
|vpiFullName:work@tlb_lut_ram.tlb_read_addr
|vpiLhs:
\_ref_obj: (tlb_write_addr), line:72
|vpiName:tlb_write_addr
|vpiFullName:work@tlb_lut_ram.tlb_write_addr
|vpiContAssign:
\_cont_assign: , line:73
|vpiRhs:
\_operation: , line:73
|vpiOpType:32
|vpiOperand:
\_ref_obj: (tlb.flush), line:73
|vpiName:tlb.flush
|vpiFullName:work@tlb_lut_ram.tlb.flush
|vpiOperand:
\_operation: , line:73
|vpiOpType:34
|vpiOperand:
\_ref_obj: (WAYS), line:73
|vpiName:WAYS
|vpiFullName:work@tlb_lut_ram.WAYS
|vpiOperand:
\_operation:
|vpiOpType:33
|vpiOperand:
\_ref_obj: (flush_in_progress), line:73
|vpiName:flush_in_progress
|vpiFullName:work@tlb_lut_ram.flush_in_progress
|vpiOperand:
\_operation: , line:73
|vpiOpType:28
|vpiOperand:
\_ref_obj: (replacement_way), line:73
|vpiName:replacement_way
|vpiFullName:work@tlb_lut_ram.replacement_way
|vpiOperand:
\_operation: , line:73
|vpiOpType:34
|vpiOperand:
\_ref_obj: (WAYS), line:73
|vpiName:WAYS
|vpiFullName:work@tlb_lut_ram.WAYS
|vpiOperand:
\_operation:
|vpiOpType:33
|vpiOperand:
\_ref_obj: (mmu.write_entry), line:73
|vpiName:mmu.write_entry
|vpiFullName:work@tlb_lut_ram.mmu.write_entry
|vpiLhs:
\_ref_obj: (tlb_write), line:73
|vpiName:tlb_write
|vpiFullName:work@tlb_lut_ram.tlb_write
|vpiContAssign:
\_cont_assign: , line:75
|vpiRhs:
\_operation: , line:75
|vpiOpType:4
|vpiOperand:
\_ref_obj: (tlb.flush), line:75
|vpiName:tlb.flush
|vpiFullName:work@tlb_lut_ram.tlb.flush
|vpiLhs:
\_ref_obj: (new_entry.valid), line:75
|vpiName:new_entry.valid
|vpiFullName:work@tlb_lut_ram.new_entry.valid
|vpiContAssign:
\_cont_assign: , line:76
|vpiRhs:
\_ref_obj: (virtual_tag), line:76
|vpiName:virtual_tag
|vpiFullName:work@tlb_lut_ram.virtual_tag
|vpiLhs:
\_ref_obj: (new_entry.tag), line:76
|vpiName:new_entry.tag
|vpiFullName:work@tlb_lut_ram.new_entry.tag
|vpiContAssign:
\_cont_assign: , line:77
|vpiRhs:
\_ref_obj: (mmu.new_phys_addr), line:77
|vpiName:mmu.new_phys_addr
|vpiFullName:work@tlb_lut_ram.mmu.new_phys_addr
|vpiLhs:
\_ref_obj: (new_entry.phys_addr), line:77
|vpiName:new_entry.phys_addr
|vpiFullName:work@tlb_lut_ram.new_entry.phys_addr
|vpiContAssign:
\_cont_assign: , line:130
|vpiRhs:
\_ref_obj: (tlb.virtual_address), line:130
|vpiName:tlb.virtual_address
|vpiFullName:work@tlb_lut_ram.tlb.virtual_address
|vpiLhs:
\_ref_obj: (mmu.virtual_address), line:130
|vpiName:mmu.virtual_address
|vpiFullName:work@tlb_lut_ram.mmu.virtual_address
|vpiContAssign:
\_cont_assign: , line:131
|vpiRhs:
\_ref_obj: (tlb.execute), line:131
|vpiName:tlb.execute
|vpiFullName:work@tlb_lut_ram.tlb.execute
|vpiLhs:
\_ref_obj: (mmu.execute), line:131
|vpiName:mmu.execute
|vpiFullName:work@tlb_lut_ram.mmu.execute
|vpiContAssign:
\_cont_assign: , line:132
|vpiRhs:
\_ref_obj: (tlb.rnw), line:132
|vpiName:tlb.rnw
|vpiFullName:work@tlb_lut_ram.tlb.rnw
|vpiLhs:
\_ref_obj: (mmu.rnw), line:132
|vpiName:mmu.rnw
|vpiFullName:work@tlb_lut_ram.mmu.rnw
|vpiContAssign:
\_cont_assign: , line:134
|vpiRhs:
\_operation: , line:134
|vpiOpType:7
|vpiOperand:
\_ref_obj: (tag_hit), line:134
|vpiName:tag_hit
|vpiFullName:work@tlb_lut_ram.tag_hit
|vpiLhs:
\_ref_obj: (hit), line:134
|vpiName:hit
|vpiFullName:work@tlb_lut_ram.hit
|vpiContAssign:
\_cont_assign: , line:135
|vpiRhs:
\_operation: , line:135
|vpiOpType:29
|vpiOperand:
\_ref_obj: (hit), line:135
|vpiName:hit
|vpiFullName:work@tlb_lut_ram.hit
|vpiOperand:
\_operation: , line:135
|vpiOpType:4
|vpiOperand:
\_ref_obj: (tlb_on), line:135
|vpiName:tlb_on
|vpiFullName:work@tlb_lut_ram.tlb_on
|vpiLhs:
\_ref_obj: (tlb.complete), line:135
|vpiName:tlb.complete
|vpiFullName:work@tlb_lut_ram.tlb.complete
|vpiNet:
\_logic_net: (clk), line:31
|vpiNet:
\_logic_net: (rst), line:32
|vpiNet:
\_logic_net: (tlb_on), line:33
|vpiNet:
\_logic_net: (asid), line:34
|vpiNet:
\_logic_net: (tlb_read_addr), line:48
|vpiName:tlb_read_addr
|vpiFullName:work@tlb_lut_ram.tlb_read_addr
|vpiNetType:36
|vpiNet:
\_logic_net: (tlb_write_addr), line:49
|vpiName:tlb_write_addr
|vpiFullName:work@tlb_lut_ram.tlb_write_addr
|vpiNetType:36
|vpiNet:
\_logic_net: (virtual_tag), line:51
|vpiName:virtual_tag
|vpiFullName:work@tlb_lut_ram.virtual_tag
|vpiNetType:36
|vpiNet:
\_logic_net: (ram), line:53
|vpiName:ram
|vpiFullName:work@tlb_lut_ram.ram
|vpiNet:
\_logic_net: (valid), line:54
|vpiName:valid
|vpiFullName:work@tlb_lut_ram.valid
|vpiNetType:36
|vpiNet:
\_logic_net: (tag_hit), line:56
|vpiName:tag_hit
|vpiFullName:work@tlb_lut_ram.tag_hit
|vpiNetType:36
|vpiNet:
\_logic_net: (replacement_way), line:57
|vpiName:replacement_way
|vpiFullName:work@tlb_lut_ram.replacement_way
|vpiNetType:36
|vpiNet:
\_logic_net: (ram_data), line:59
|vpiName:ram_data
|vpiFullName:work@tlb_lut_ram.ram_data
|vpiNet:
\_logic_net: (new_entry), line:60
|vpiName:new_entry
|vpiFullName:work@tlb_lut_ram.new_entry
|vpiNet:
\_logic_net: (flush_in_progress), line:62
|vpiName:flush_in_progress
|vpiFullName:work@tlb_lut_ram.flush_in_progress
|vpiNetType:36
|vpiNet:
\_logic_net: (flush_addr), line:63
|vpiName:flush_addr
|vpiFullName:work@tlb_lut_ram.flush_addr
|vpiNetType:36
|vpiNet:
\_logic_net: (hit), line:65
|vpiName:hit
|vpiFullName:work@tlb_lut_ram.hit
|vpiNetType:36
|vpiNet:
\_logic_net: (tlb_write), line:67
|vpiName:tlb_write
|vpiFullName:work@tlb_lut_ram.tlb_write
|vpiNetType:36
|vpiNet:
\_logic_net: (mmu), line:35
|vpiName:mmu
|vpiFullName:work@tlb_lut_ram.mmu
|vpiNet:
\_logic_net: (tlb), line:36
|vpiName:tlb
|vpiFullName:work@tlb_lut_ram.tlb
|vpiTypedef:
\_struct_typespec: (alu_inputs_t), line:301
|vpiTypedef:
\_enum_typespec: (alu_logic_op_t), line:84
|vpiTypedef:
\_enum_typespec: (alu_op_t), line:91
|vpiTypedef:
\_enum_typespec: (alu_rs1_op_t), line:97
|vpiTypedef:
\_enum_typespec: (alu_rs2_op_t), line:104
|vpiTypedef:
\_struct_typespec: (amo_alu_inputs_t), line:356
|vpiTypedef:
\_struct_typespec: (amo_details_t), line:362
|vpiTypedef:
\_enum_typespec: (amo_t), line:354
|vpiTypedef:
\_struct_typespec: (branch_inputs_t), line:313
|vpiTypedef:
\_logic_typespec: (branch_predictor_metadata_t), line:32
|vpiTypedef:
\_struct_typespec: (branch_results_t), line:330
|vpiTypedef:
\_enum_typespec: (bus_type_t), line:86
|vpiTypedef:
\_struct_typespec: (csr_inputs_t), line:396
|vpiTypedef:
\_enum_typespec: (csr_op_t), line:218
|vpiTypedef:
\_enum_typespec: (csr_t), line:201
|vpiTypedef:
\_struct_typespec: (data_access_shared_inputs_t), line:427
|vpiTypedef:
\_struct_typespec: (div_inputs_t), line:389
|vpiTypedef:
\_enum_typespec: (div_type), line:66
|vpiTypedef:
\_enum_typespec: (exception_code_t), line:245
|vpiTypedef:
\_struct_typespec: (exception_packet_t), line:263
|vpiTypedef:
\_struct_typespec: (fetch_buffer_packet_t), line:276
|vpiTypedef:
\_enum_typespec: (fifo_type_t), line:440
|vpiTypedef:
\_enum_typespec: (fn3_arith_t), line:76
|vpiTypedef:
\_enum_typespec: (fn3_branch_t), line:126
|vpiTypedef:
\_enum_typespec: (fn3_csr_t), line:212
|vpiTypedef:
\_enum_typespec: (fn3_ls_t), line:115
|vpiTypedef:
\_enum_typespec: (fn3_mul_div_t), line:138
|vpiTypedef:
\_struct_typespec: (gc_inputs_t), line:404
|vpiTypedef:
\_struct_typespec: (inflight_instruction_packet), line:271
|vpiTypedef:
\_logic_typespec: (instruction_id_t), line:30
|vpiTypedef:
\_enum_typespec: (interrupt_code_t), line:261
|vpiTypedef:
\_struct_typespec: (load_store_inputs_t), line:369
|vpiTypedef:
\_struct_typespec: (mul_inputs_t), line:383
|vpiTypedef:
\_enum_typespec: (opcodes_t), line:48
|vpiTypedef:
\_enum_typespec: (opcodes_trimmed_t), line:65
|vpiTypedef:
\_struct_typespec: (simulation_named_regfile), line:476
|vpiTypedef:
\_struct_typespec: (taiga_trace_events_t), line:442
|vpiTypedef:
\_struct_typespec: (tlb_entry_t), line:41
|vpiPacked:1
|vpiName:tlb_entry_t
|vpiTypespecMember:
\_typespec_member: (valid), line:42
|vpiName:valid
|vpiTypespec:
\_logic_typespec: , line:42
|vpiTypespecMember:
\_typespec_member: (tag), line:43
|vpiName:tag
|vpiTypespec:
\_logic_typespec: , line:43
|vpiRange:
\_range: , line:43, parent:tlb_entry_t
|vpiLeftRange:
\_constant: , line:43
|vpiDecompile:14
|INT:14
|vpiRightRange:
\_constant: , line:43
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiTypespecMember:
\_typespec_member: (phys_addr), line:44
|vpiName:phys_addr
|vpiTypespec:
\_logic_typespec: , line:44
|vpiRange:
\_range: , line:44, parent:tlb_entry_t
|vpiLeftRange:
\_constant: , line:44
|vpiConstType:7
|vpiDecompile:19
|vpiSize:32
|INT:19
|vpiRightRange:
\_constant: , line:44
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiTypedef:
\_struct_typespec: (to_l1_arbiter_packet), line:418
|vpiTypedef:
\_struct_typespec: (trace_outputs_t), line:469
|vpiTypedef:
\_logic_typespec: (unit_id_t), line:31
|vpiTypedef:
\_struct_typespec: (unit_writeback_t), line:295
|vpiTypedef:
\_enum_typespec: (vm_t), line:223
|vpiParamAssign:
\_param_assign: , line:27
|vpiRhs:
\_constant: , line:27
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiLhs:
\_parameter: (WAYS), line:27
|vpiName:WAYS
|vpiParamAssign:
\_param_assign: , line:28
|vpiRhs:
\_constant: , line:28
|vpiConstType:7
|vpiDecompile:32
|vpiSize:32
|INT:32
|vpiLhs:
\_parameter: (DEPTH), line:28
|vpiName:DEPTH
|vpiParamAssign:
\_param_assign: , line:39
|vpiRhs:
\_constant: , line:39
|vpiDecompile:15
|INT:15
|vpiLhs:
\_parameter: (TLB_TAG_W), line:39
|vpiName:TLB_TAG_W
|vpiLocalParam:1
|vpiParameter:
\_parameter: (WAYS), line:27
|vpiParameter:
\_parameter: (DEPTH), line:28
|vpiParameter:
\_parameter: (TLB_TAG_W), line:39
|uhdmallModules:
\_module: work@wishbone_master, file:third_party/cores/taiga/core/wishbone_master.sv, line:27, parent:work@div_unit_core_wrapper
|vpiDefName:work@wishbone_master
|vpiFullName:work@wishbone_master
|vpiProcess:
\_always: , line:42
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:42
|vpiCondition:
\_operation: , line:42
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:42
|vpiName:clk
|vpiFullName:work@wishbone_master.clk
|vpiStmt:
\_begin: , line:42
|vpiFullName:work@wishbone_master
|vpiStmt:
\_if_stmt: , line:43
|vpiCondition:
\_ref_obj: (ls.new_request), line:43
|vpiName:ls.new_request
|vpiFullName:work@wishbone_master.ls.new_request
|vpiStmt:
\_begin: , line:43
|vpiFullName:work@wishbone_master
|vpiStmt:
\_assignment: , line:44
|vpiOpType:82
|vpiLhs:
\_ref_obj: (m_wishbone.addr), line:44
|vpiName:m_wishbone.addr
|vpiFullName:work@wishbone_master.m_wishbone.addr
|vpiRhs:
\_ref_obj: (ls_inputs.addr), line:44
|vpiName:ls_inputs.addr
|vpiFullName:work@wishbone_master.ls_inputs.addr
|vpiStmt:
\_assignment: , line:45
|vpiOpType:82
|vpiLhs:
\_ref_obj: (m_wishbone.we), line:45
|vpiName:m_wishbone.we
|vpiFullName:work@wishbone_master.m_wishbone.we
|vpiRhs:
\_ref_obj: (ls_inputs.store), line:45
|vpiName:ls_inputs.store
|vpiFullName:work@wishbone_master.ls_inputs.store
|vpiStmt:
\_assignment: , line:46
|vpiOpType:82
|vpiLhs:
\_ref_obj: (m_wishbone.sel), line:46
|vpiName:m_wishbone.sel
|vpiFullName:work@wishbone_master.m_wishbone.sel
|vpiRhs:
\_ref_obj: (ls_inputs.be), line:46
|vpiName:ls_inputs.be
|vpiFullName:work@wishbone_master.ls_inputs.be
|vpiStmt:
\_assignment: , line:47
|vpiOpType:82
|vpiLhs:
\_ref_obj: (m_wishbone.writedata), line:47
|vpiName:m_wishbone.writedata
|vpiFullName:work@wishbone_master.m_wishbone.writedata
|vpiRhs:
\_ref_obj: (ls_inputs.data_in), line:47
|vpiName:ls_inputs.data_in
|vpiFullName:work@wishbone_master.ls_inputs.data_in
|vpiProcess:
\_always: , line:51
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:51
|vpiCondition:
\_operation: , line:51
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:51
|vpiName:clk
|vpiFullName:work@wishbone_master.clk
|vpiStmt:
\_begin: , line:51
|vpiFullName:work@wishbone_master
|vpiStmt:
\_if_else: , line:52
|vpiCondition:
\_ref_obj: (rst), line:52
|vpiName:rst
|vpiFullName:work@wishbone_master.rst
|vpiStmt:
\_assignment: , line:53
|vpiOpType:82
|vpiLhs:
\_ref_obj: (ls.ready), line:53
|vpiName:ls.ready
|vpiFullName:work@wishbone_master.ls.ready
|vpiRhs:
\_constant: , line:53
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiElseStmt:
\_if_else: , line:54
|vpiCondition:
\_ref_obj: (ls.new_request), line:54
|vpiName:ls.new_request
|vpiFullName:work@wishbone_master.ls.new_request
|vpiStmt:
\_assignment: , line:55
|vpiOpType:82
|vpiLhs:
\_ref_obj: (ls.ready), line:55
|vpiName:ls.ready
|vpiFullName:work@wishbone_master.ls.ready
|vpiRhs:
\_constant: , line:55
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiElseStmt:
\_if_stmt: , line:56
|vpiCondition:
\_ref_obj: (m_wishbone.ack), line:56
|vpiName:m_wishbone.ack
|vpiFullName:work@wishbone_master.m_wishbone.ack
|vpiStmt:
\_assignment: , line:57
|vpiOpType:82
|vpiLhs:
\_ref_obj: (ls.ready), line:57
|vpiName:ls.ready
|vpiFullName:work@wishbone_master.ls.ready
|vpiRhs:
\_constant: , line:57
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiProcess:
\_always: , line:60
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:60
|vpiCondition:
\_operation: , line:60
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:60
|vpiName:clk
|vpiFullName:work@wishbone_master.clk
|vpiStmt:
\_begin: , line:60
|vpiFullName:work@wishbone_master
|vpiStmt:
\_if_else: , line:61
|vpiCondition:
\_ref_obj: (rst), line:61
|vpiName:rst
|vpiFullName:work@wishbone_master.rst
|vpiStmt:
\_assignment: , line:62
|vpiOpType:82
|vpiLhs:
\_ref_obj: (ls.data_valid), line:62
|vpiName:ls.data_valid
|vpiFullName:work@wishbone_master.ls.data_valid
|vpiRhs:
\_constant: , line:62
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiElseStmt:
\_if_else: , line:63
|vpiCondition:
\_operation: , line:63
|vpiOpType:28
|vpiOperand:
\_operation: , line:63
|vpiOpType:4
|vpiOperand:
\_ref_obj: (m_wishbone.we), line:63
|vpiName:m_wishbone.we
|vpiFullName:work@wishbone_master.m_wishbone.we
|vpiOperand:
\_ref_obj: (m_wishbone.ack), line:63
|vpiName:m_wishbone.ack
|vpiFullName:work@wishbone_master.m_wishbone.ack
|vpiStmt:
\_assignment: , line:64
|vpiOpType:82
|vpiLhs:
\_ref_obj: (ls.data_valid), line:64
|vpiName:ls.data_valid
|vpiFullName:work@wishbone_master.ls.data_valid
|vpiRhs:
\_constant: , line:64
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiElseStmt:
\_assignment: , line:66
|vpiOpType:82
|vpiLhs:
\_ref_obj: (ls.data_valid), line:66
|vpiName:ls.data_valid
|vpiFullName:work@wishbone_master.ls.data_valid
|vpiRhs:
\_constant: , line:66
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiProcess:
\_always: , line:69
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:69
|vpiCondition:
\_operation: , line:69
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:69
|vpiName:clk
|vpiFullName:work@wishbone_master.clk
|vpiStmt:
\_begin: , line:69
|vpiFullName:work@wishbone_master
|vpiStmt:
\_if_else: , line:70
|vpiCondition:
\_ref_obj: (m_wishbone.ack), line:70
|vpiName:m_wishbone.ack
|vpiFullName:work@wishbone_master.m_wishbone.ack
|vpiStmt:
\_assignment: , line:71
|vpiOpType:82
|vpiLhs:
\_ref_obj: (data_out), line:71
|vpiName:data_out
|vpiFullName:work@wishbone_master.data_out
|vpiRhs:
\_ref_obj: (m_wishbone.readdata), line:71
|vpiName:m_wishbone.readdata
|vpiFullName:work@wishbone_master.m_wishbone.readdata
|vpiElseStmt:
\_assignment: , line:73
|vpiOpType:82
|vpiLhs:
\_ref_obj: (data_out), line:73
|vpiName:data_out
|vpiFullName:work@wishbone_master.data_out
|vpiRhs:
\_constant: , line:73
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiProcess:
\_always: , line:76
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:76
|vpiCondition:
\_operation: , line:76
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:76
|vpiName:clk
|vpiFullName:work@wishbone_master.clk
|vpiStmt:
\_begin: , line:76
|vpiFullName:work@wishbone_master
|vpiStmt:
\_if_else: , line:77
|vpiCondition:
\_ref_obj: (rst), line:77
|vpiName:rst
|vpiFullName:work@wishbone_master.rst
|vpiStmt:
\_begin: , line:77
|vpiFullName:work@wishbone_master
|vpiStmt:
\_assignment: , line:78
|vpiOpType:82
|vpiLhs:
\_ref_obj: (m_wishbone.stb), line:78
|vpiName:m_wishbone.stb
|vpiFullName:work@wishbone_master.m_wishbone.stb
|vpiRhs:
\_constant: , line:78
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiStmt:
\_assignment: , line:79
|vpiOpType:82
|vpiLhs:
\_ref_obj: (m_wishbone.cyc), line:79
|vpiName:m_wishbone.cyc
|vpiFullName:work@wishbone_master.m_wishbone.cyc
|vpiRhs:
\_constant: , line:79
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiElseStmt:
\_if_else: , line:81
|vpiCondition:
\_ref_obj: (ls.new_request), line:81
|vpiName:ls.new_request
|vpiFullName:work@wishbone_master.ls.new_request
|vpiStmt:
\_begin: , line:81
|vpiFullName:work@wishbone_master
|vpiStmt:
\_assignment: , line:82
|vpiOpType:82
|vpiLhs:
\_ref_obj: (m_wishbone.stb), line:82
|vpiName:m_wishbone.stb
|vpiFullName:work@wishbone_master.m_wishbone.stb
|vpiRhs:
\_constant: , line:82
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiStmt:
\_assignment: , line:83
|vpiOpType:82
|vpiLhs:
\_ref_obj: (m_wishbone.cyc), line:83
|vpiName:m_wishbone.cyc
|vpiFullName:work@wishbone_master.m_wishbone.cyc
|vpiRhs:
\_constant: , line:83
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiElseStmt:
\_if_stmt: , line:85
|vpiCondition:
\_ref_obj: (m_wishbone.ack), line:85
|vpiName:m_wishbone.ack
|vpiFullName:work@wishbone_master.m_wishbone.ack
|vpiStmt:
\_begin: , line:85
|vpiFullName:work@wishbone_master
|vpiStmt:
\_assignment: , line:86
|vpiOpType:82
|vpiLhs:
\_ref_obj: (m_wishbone.stb), line:86
|vpiName:m_wishbone.stb
|vpiFullName:work@wishbone_master.m_wishbone.stb
|vpiRhs:
\_constant: , line:86
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiStmt:
\_assignment: , line:87
|vpiOpType:82
|vpiLhs:
\_ref_obj: (m_wishbone.cyc), line:87
|vpiName:m_wishbone.cyc
|vpiFullName:work@wishbone_master.m_wishbone.cyc
|vpiRhs:
\_constant: , line:87
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiPort:
\_port: (clk), line:29
|vpiName:clk
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (clk), line:29
|vpiName:clk
|vpiFullName:work@wishbone_master.clk
|vpiNetType:36
|vpiPort:
\_port: (rst), line:30
|vpiName:rst
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (rst), line:30
|vpiName:rst
|vpiFullName:work@wishbone_master.rst
|vpiNetType:36
|vpiPort:
\_port: (m_wishbone), line:32
|vpiName:m_wishbone
|vpiDirection:5
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_modport: (master)
|vpiPort:
\_port: (data_out), line:33
|vpiName:data_out
|vpiDirection:2
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (data_out), line:33
|vpiName:data_out
|vpiFullName:work@wishbone_master.data_out
|vpiNetType:36
|vpiPort:
\_port: (ls_inputs), line:35
|vpiName:ls_inputs
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (ls_inputs), line:35
|vpiName:ls_inputs
|vpiFullName:work@wishbone_master.ls_inputs
|vpiPort:
\_port: (ls), line:36
|vpiName:ls
|vpiDirection:5
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_modport: (sub_unit)
|vpiNet:
\_logic_net: (clk), line:29
|vpiNet:
\_logic_net: (rst), line:30
|vpiNet:
\_logic_net: (data_out), line:33
|vpiNet:
\_logic_net: (ls_inputs), line:35
|vpiNet:
\_logic_net: (m_wishbone), line:32
|vpiName:m_wishbone
|vpiFullName:work@wishbone_master.m_wishbone
|vpiNet:
\_logic_net: (ls), line:36
|vpiName:ls
|vpiFullName:work@wishbone_master.ls
|vpiTypedef:
\_struct_typespec: (alu_inputs_t), line:301
|vpiTypedef:
\_enum_typespec: (alu_logic_op_t), line:84
|vpiTypedef:
\_enum_typespec: (alu_op_t), line:91
|vpiTypedef:
\_enum_typespec: (alu_rs1_op_t), line:97
|vpiTypedef:
\_enum_typespec: (alu_rs2_op_t), line:104
|vpiTypedef:
\_struct_typespec: (amo_alu_inputs_t), line:356
|vpiTypedef:
\_struct_typespec: (amo_details_t), line:362
|vpiTypedef:
\_enum_typespec: (amo_t), line:354
|vpiTypedef:
\_struct_typespec: (branch_inputs_t), line:313
|vpiTypedef:
\_logic_typespec: (branch_predictor_metadata_t), line:32
|vpiTypedef:
\_struct_typespec: (branch_results_t), line:330
|vpiTypedef:
\_enum_typespec: (bus_type_t), line:86
|vpiTypedef:
\_struct_typespec: (csr_inputs_t), line:396
|vpiTypedef:
\_enum_typespec: (csr_op_t), line:218
|vpiTypedef:
\_enum_typespec: (csr_t), line:201
|vpiTypedef:
\_struct_typespec: (data_access_shared_inputs_t), line:427
|vpiTypedef:
\_struct_typespec: (div_inputs_t), line:389
|vpiTypedef:
\_enum_typespec: (div_type), line:66
|vpiTypedef:
\_enum_typespec: (exception_code_t), line:245
|vpiTypedef:
\_struct_typespec: (exception_packet_t), line:263
|vpiTypedef:
\_struct_typespec: (fetch_buffer_packet_t), line:276
|vpiTypedef:
\_enum_typespec: (fifo_type_t), line:440
|vpiTypedef:
\_enum_typespec: (fn3_arith_t), line:76
|vpiTypedef:
\_enum_typespec: (fn3_branch_t), line:126
|vpiTypedef:
\_enum_typespec: (fn3_csr_t), line:212
|vpiTypedef:
\_enum_typespec: (fn3_ls_t), line:115
|vpiTypedef:
\_enum_typespec: (fn3_mul_div_t), line:138
|vpiTypedef:
\_struct_typespec: (gc_inputs_t), line:404
|vpiTypedef:
\_struct_typespec: (inflight_instruction_packet), line:271
|vpiTypedef:
\_logic_typespec: (instruction_id_t), line:30
|vpiTypedef:
\_enum_typespec: (interrupt_code_t), line:261
|vpiTypedef:
\_struct_typespec: (load_store_inputs_t), line:369
|vpiTypedef:
\_struct_typespec: (mul_inputs_t), line:383
|vpiTypedef:
\_enum_typespec: (opcodes_t), line:48
|vpiTypedef:
\_enum_typespec: (opcodes_trimmed_t), line:65
|vpiTypedef:
\_struct_typespec: (simulation_named_regfile), line:476
|vpiTypedef:
\_struct_typespec: (taiga_trace_events_t), line:442
|vpiTypedef:
\_struct_typespec: (to_l1_arbiter_packet), line:418
|vpiTypedef:
\_struct_typespec: (trace_outputs_t), line:469
|vpiTypedef:
\_logic_typespec: (unit_id_t), line:31
|vpiTypedef:
\_struct_typespec: (unit_writeback_t), line:295
|vpiTypedef:
\_enum_typespec: (vm_t), line:223
|uhdmallModules:
\_module: work@write_back, file:third_party/cores/taiga/core/write_back.sv, line:26, parent:work@div_unit_core_wrapper
|vpiDefName:work@write_back
|vpiFullName:work@write_back
|vpiProcess:
\_always: , line:101
|vpiAlwaysType:2
|vpiStmt:
\_begin: , line:101
|vpiFullName:work@write_back
|vpiStmt:
\_assignment: , line:102
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (id_writing_to_buffer), line:102
|vpiName:id_writing_to_buffer
|vpiFullName:work@write_back.id_writing_to_buffer
|vpiRhs:
\_constant: , line:102
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiStmt:
\_for_stmt: , line:103
|vpiFullName:work@write_back
|vpiCondition:
\_operation: , line:103
|vpiOpType:20
|vpiOperand:
\_ref_obj: (i), line:103
|vpiName:i
|vpiFullName:work@write_back.i
|vpiOperand:
\_ref_obj: (NUM_WB_UNITS), line:103
|vpiName:NUM_WB_UNITS
|vpiFullName:work@write_back.NUM_WB_UNITS
|vpiForInitStmt:
\_assign_stmt:
|vpiRhs:
\_constant: , line:103
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiLhs:
\_int_var: (i), line:103
|vpiName:i
|vpiFullName:work@write_back.i
|vpiForIncStmt:
\_operation: , line:103
|vpiOpType:62
|vpiOperand:
\_ref_obj: (i), line:103
|vpiName:i
|vpiStmt:
\_begin: , line:103
|vpiFullName:work@write_back
|vpiStmt:
\_if_stmt: , line:104
|vpiCondition:
\_bit_select: (unit_done), line:104
|vpiName:unit_done
|vpiFullName:work@write_back.unit_done
|vpiIndex:
\_ref_obj: (i), line:104
|vpiName:i
|vpiStmt:
\_assignment: , line:105
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_bit_select: (id_writing_to_buffer), line:105
|vpiName:id_writing_to_buffer
|vpiFullName:work@write_back.id_writing_to_buffer
|vpiIndex:
\_bit_select: (unit_instruction_id), line:105
|vpiName:unit_instruction_id
|vpiIndex:
\_ref_obj: (i), line:105
|vpiName:i
|vpiRhs:
\_constant: , line:105
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiStmt:
\_if_stmt: , line:107
|vpiCondition:
\_ref_obj: (store_complete), line:107
|vpiName:store_complete
|vpiFullName:work@write_back.store_complete
|vpiStmt:
\_assignment: , line:108
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_bit_select: (id_writing_to_buffer), line:108
|vpiName:id_writing_to_buffer
|vpiFullName:work@write_back.id_writing_to_buffer
|vpiIndex:
\_ref_obj: (store_done_id), line:108
|vpiName:store_done_id
|vpiRhs:
\_constant: , line:108
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiProcess:
\_always: , line:117
|vpiAlwaysType:2
|vpiStmt:
\_begin: , line:117
|vpiFullName:work@write_back
|vpiStmt:
\_assignment: , line:118
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (id_issued_one_hot), line:118
|vpiName:id_issued_one_hot
|vpiFullName:work@write_back.id_issued_one_hot
|vpiRhs:
\_constant: , line:118
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiStmt:
\_assignment: , line:119
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_bit_select: (id_issued_one_hot), line:119
|vpiName:id_issued_one_hot
|vpiFullName:work@write_back.id_issued_one_hot
|vpiIndex:
\_ref_obj: (ti.issue_id), line:119
|vpiName:ti.issue_id
|vpiRhs:
\_operation: , line:119
|vpiOpType:28
|vpiOperand:
\_ref_obj: (ti.issued), line:119
|vpiName:ti.issued
|vpiFullName:work@write_back.ti.issued
|vpiOperand:
\_operation: , line:119
|vpiOpType:4
|vpiOperand:
\_ref_obj: (ti.inflight_packet), line:119
|vpiName:ti.inflight_packet
|vpiFullName:work@write_back.ti.inflight_packet
|vpiProcess:
\_always: , line:135
|vpiAlwaysType:2
|vpiStmt:
\_begin: , line:135
|vpiFullName:work@write_back
|vpiStmt:
\_assignment: , line:136
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (store_mux), line:136
|vpiName:store_mux
|vpiFullName:work@write_back.store_mux
|vpiRhs:
\_constant: , line:136
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiStmt:
\_assignment: , line:137
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_bit_select: (store_mux), line:137
|vpiName:store_mux
|vpiFullName:work@write_back.store_mux
|vpiIndex:
\_ref_obj: (ti.issue_id), line:137
|vpiName:ti.issue_id
|vpiRhs:
\_ref_obj: (store_issued_with_data), line:137
|vpiName:store_issued_with_data
|vpiFullName:work@write_back.store_issued_with_data
|vpiProcess:
\_always: , line:150
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:150
|vpiCondition:
\_operation: , line:150
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:150
|vpiName:clk
|vpiFullName:work@write_back.clk
|vpiStmt:
\_begin: , line:150
|vpiFullName:work@write_back
|vpiStmt:
\_if_else: , line:151
|vpiCondition:
\_ref_obj: (rst), line:151
|vpiName:rst
|vpiFullName:work@write_back.rst
|vpiStmt:
\_assignment: , line:152
|vpiOpType:82
|vpiLhs:
\_ref_obj: (id_inuse), line:152
|vpiName:id_inuse
|vpiFullName:work@write_back.id_inuse
|vpiRhs:
\_constant: , line:152
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiElseStmt:
\_assignment: , line:154
|vpiOpType:82
|vpiLhs:
\_ref_obj: (id_inuse), line:154
|vpiName:id_inuse
|vpiFullName:work@write_back.id_inuse
|vpiRhs:
\_operation: , line:154
|vpiOpType:28
|vpiOperand:
\_operation: , line:154
|vpiOpType:29
|vpiOperand:
\_ref_obj: (id_issued_one_hot), line:154
|vpiName:id_issued_one_hot
|vpiFullName:work@write_back.id_issued_one_hot
|vpiOperand:
\_ref_obj: (id_inuse), line:154
|vpiName:id_inuse
|vpiFullName:work@write_back.id_inuse
|vpiOperand:
\_operation: , line:154
|vpiOpType:4
|vpiOperand:
\_ref_obj: (id_writing_to_buffer), line:154
|vpiName:id_writing_to_buffer
|vpiFullName:work@write_back.id_writing_to_buffer
|vpiProcess:
\_initial:
|vpiStmt:
\_begin: , line:171
|vpiFullName:work@write_back
|vpiStmt:
\_foreach_stmt: , line:172
|vpiFullName:work@write_back
|vpiVariables:
\_chandle_var: (id_metadata), line:172
|vpiName:id_metadata
|vpiFullName:work@write_back.id_metadata
|vpiLoopVars:
\_chandle_var: (i), line:172
|vpiName:i
|vpiFullName:work@write_back.i
|vpiStmt:
\_assignment: , line:173
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_bit_select: (id_metadata), line:173
|vpiName:id_metadata
|vpiFullName:work@write_back.id_metadata
|vpiIndex:
\_ref_obj: (i), line:173
|vpiName:i
|vpiRhs:
\_constant: , line:173
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiProcess:
\_always: , line:177
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:177
|vpiCondition:
\_operation: , line:177
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:177
|vpiName:clk
|vpiFullName:work@write_back.clk
|vpiStmt:
\_begin: , line:177
|vpiFullName:work@write_back
|vpiStmt:
\_if_stmt: , line:178
|vpiCondition:
\_ref_obj: (ti.id_available), line:178
|vpiName:ti.id_available
|vpiFullName:work@write_back.ti.id_available
|vpiStmt:
\_assignment: , line:179
|vpiOpType:82
|vpiLhs:
\_bit_select: (id_metadata), line:179
|vpiName:id_metadata
|vpiFullName:work@write_back.id_metadata
|vpiIndex:
\_ref_obj: (ti.issue_id), line:179
|vpiName:ti.issue_id
|vpiRhs:
\_ref_obj: (ti.inflight_packet), line:179
|vpiName:ti.inflight_packet
|vpiFullName:work@write_back.ti.inflight_packet
|vpiProcess:
\_always: , line:186
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:186
|vpiCondition:
\_operation: , line:186
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:186
|vpiName:clk
|vpiFullName:work@write_back.clk
|vpiStmt:
\_begin: , line:186
|vpiFullName:work@write_back
|vpiStmt:
\_if_else: , line:187
|vpiCondition:
\_ref_obj: (rst), line:187
|vpiName:rst
|vpiFullName:work@write_back.rst
|vpiStmt:
\_assignment: , line:188
|vpiOpType:82
|vpiLhs:
\_ref_obj: (id_writeback_pending_r), line:188
|vpiName:id_writeback_pending_r
|vpiFullName:work@write_back.id_writeback_pending_r
|vpiRhs:
\_constant: , line:188
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiElseStmt:
\_assignment: , line:190
|vpiOpType:82
|vpiLhs:
\_ref_obj: (id_writeback_pending_r), line:190
|vpiName:id_writeback_pending_r
|vpiFullName:work@write_back.id_writeback_pending_r
|vpiRhs:
\_ref_obj: (id_writeback_pending), line:190
|vpiName:id_writeback_pending
|vpiFullName:work@write_back.id_writeback_pending
|vpiProcess:
\_always: , line:198
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:198
|vpiCondition:
\_operation: , line:198
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:198
|vpiName:clk
|vpiFullName:work@write_back.clk
|vpiStmt:
\_begin: , line:198
|vpiFullName:work@write_back
|vpiStmt:
\_assignment: , line:199
|vpiOpType:82
|vpiLhs:
\_ref_obj: (retiring), line:199
|vpiName:retiring
|vpiFullName:work@write_back.retiring
|vpiRhs:
\_ref_obj: (retiring_next_cycle), line:199
|vpiName:retiring_next_cycle
|vpiFullName:work@write_back.retiring_next_cycle
|vpiStmt:
\_assignment: , line:200
|vpiOpType:82
|vpiLhs:
\_ref_obj: (id_retiring), line:200
|vpiName:id_retiring
|vpiFullName:work@write_back.id_retiring
|vpiRhs:
\_ref_obj: (oldest_id), line:200
|vpiName:oldest_id
|vpiFullName:work@write_back.oldest_id
|vpiProcess:
\_always: , line:203
|vpiAlwaysType:2
|vpiStmt:
\_begin: , line:203
|vpiFullName:work@write_back
|vpiStmt:
\_assignment: , line:204
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (id_retiring_one_hot), line:204
|vpiName:id_retiring_one_hot
|vpiFullName:work@write_back.id_retiring_one_hot
|vpiRhs:
\_constant: , line:204
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiStmt:
\_assignment: , line:205
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_bit_select: (id_retiring_one_hot), line:205
|vpiName:id_retiring_one_hot
|vpiFullName:work@write_back.id_retiring_one_hot
|vpiIndex:
\_ref_obj: (id_retiring), line:205
|vpiName:id_retiring
|vpiRhs:
\_ref_obj: (retiring), line:205
|vpiName:retiring
|vpiFullName:work@write_back.retiring
|vpiPort:
\_port: (clk), line:27
|vpiName:clk
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (clk), line:27
|vpiName:clk
|vpiFullName:work@write_back.clk
|vpiNetType:36
|vpiPort:
\_port: (rst), line:28
|vpiName:rst
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (rst), line:28
|vpiName:rst
|vpiFullName:work@write_back.rst
|vpiNetType:36
|vpiPort:
\_port: (gc_fetch_flush), line:30
|vpiName:gc_fetch_flush
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (gc_fetch_flush), line:30
|vpiName:gc_fetch_flush
|vpiFullName:work@write_back.gc_fetch_flush
|vpiNetType:36
|vpiPort:
\_port: (instruction_issued_with_rd), line:31
|vpiName:instruction_issued_with_rd
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (instruction_issued_with_rd), line:31
|vpiName:instruction_issued_with_rd
|vpiFullName:work@write_back.instruction_issued_with_rd
|vpiNetType:36
|vpiPort:
\_port: (unit_wb), line:33
|vpiName:unit_wb
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (unit_wb), line:33
|vpiName:unit_wb
|vpiFullName:work@write_back.unit_wb
|vpiPort:
\_port: (rf_wb), line:34
|vpiName:rf_wb
|vpiDirection:5
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_modport: (writeback)
|vpiPort:
\_port: (ti), line:35
|vpiName:ti
|vpiDirection:5
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_modport: (wb)
|vpiPort:
\_port: (instruction_complete), line:36
|vpiName:instruction_complete
|vpiDirection:2
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (instruction_complete), line:36
|vpiName:instruction_complete
|vpiFullName:work@write_back.instruction_complete
|vpiNetType:36
|vpiPort:
\_port: (instruction_queue_empty), line:37
|vpiName:instruction_queue_empty
|vpiDirection:2
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (instruction_queue_empty), line:37
|vpiName:instruction_queue_empty
|vpiFullName:work@write_back.instruction_queue_empty
|vpiNetType:36
|vpiPort:
\_port: (oldest_id), line:38
|vpiName:oldest_id
|vpiDirection:2
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (oldest_id), line:38
|vpiName:oldest_id
|vpiFullName:work@write_back.oldest_id
|vpiPort:
\_port: (store_done_id), line:40
|vpiName:store_done_id
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (store_done_id), line:40
|vpiName:store_done_id
|vpiFullName:work@write_back.store_done_id
|vpiPort:
\_port: (store_complete), line:41
|vpiName:store_complete
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (store_complete), line:41
|vpiName:store_complete
|vpiFullName:work@write_back.store_complete
|vpiNetType:36
|vpiPort:
\_port: (store_forwarding), line:42
|vpiName:store_forwarding
|vpiDirection:5
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_modport: (wb)
|vpiPort:
\_port: (store_issued_with_data), line:44
|vpiName:store_issued_with_data
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (store_issued_with_data), line:44
|vpiName:store_issued_with_data
|vpiFullName:work@write_back.store_issued_with_data
|vpiNetType:36
|vpiPort:
\_port: (store_data), line:45
|vpiName:store_data
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (store_data), line:45
|vpiName:store_data
|vpiFullName:work@write_back.store_data
|vpiNetType:36
|vpiPort:
\_port: (tr_wb_mux_contention), line:48
|vpiName:tr_wb_mux_contention
|vpiDirection:2
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (tr_wb_mux_contention), line:48
|vpiName:tr_wb_mux_contention
|vpiFullName:work@write_back.tr_wb_mux_contention
|vpiNetType:36
|vpiContAssign:
\_cont_assign: , line:159
|vpiRhs:
\_operation: , line:159
|vpiOpType:4
|vpiOperand:
\_bit_select: (id_inuse), line:159
|vpiName:id_inuse
|vpiIndex:
\_ref_obj: (store_forwarding.id), line:159
|vpiName:store_forwarding.id
|vpiFullName:work@write_back.store_forwarding.id
|vpiLhs:
\_ref_obj: (store_forwarding.data_valid), line:159
|vpiName:store_forwarding.data_valid
|vpiFullName:work@write_back.store_forwarding.data_valid
|vpiContAssign:
\_cont_assign: , line:160
|vpiRhs:
\_bit_select: (results_by_id), line:160
|vpiName:results_by_id
|vpiFullName:work@write_back.results_by_id
|vpiIndex:
\_ref_obj: (store_forwarding.id), line:160
|vpiName:store_forwarding.id
|vpiLhs:
\_ref_obj: (store_forwarding.data), line:160
|vpiName:store_forwarding.data
|vpiFullName:work@write_back.store_forwarding.data
|vpiContAssign:
\_cont_assign: , line:181
|vpiRhs:
\_bit_select: (id_metadata), line:181
|vpiName:id_metadata
|vpiFullName:work@write_back.id_metadata
|vpiIndex:
\_ref_obj: (id_retiring), line:181
|vpiName:id_retiring
|vpiLhs:
\_ref_obj: (retiring_instruction_packet), line:181
|vpiName:retiring_instruction_packet
|vpiFullName:work@write_back.retiring_instruction_packet
|vpiContAssign:
\_cont_assign: , line:193
|vpiRhs:
\_operation: , line:193
|vpiOpType:29
|vpiOperand:
\_ref_obj: (id_writing_to_buffer), line:193
|vpiName:id_writing_to_buffer
|vpiFullName:work@write_back.id_writing_to_buffer
|vpiOperand:
\_operation: , line:193
|vpiOpType:28
|vpiOperand:
\_ref_obj: (id_writeback_pending_r), line:193
|vpiName:id_writeback_pending_r
|vpiFullName:work@write_back.id_writeback_pending_r
|vpiOperand:
\_operation: , line:193
|vpiOpType:4
|vpiOperand:
\_ref_obj: (id_retiring_one_hot), line:193
|vpiName:id_retiring_one_hot
|vpiFullName:work@write_back.id_retiring_one_hot
|vpiLhs:
\_ref_obj: (id_writeback_pending), line:193
|vpiName:id_writeback_pending
|vpiFullName:work@write_back.id_writeback_pending
|vpiContAssign:
\_cont_assign: , line:196
|vpiRhs:
\_bit_select: (id_writeback_pending), line:196
|vpiName:id_writeback_pending
|vpiFullName:work@write_back.id_writeback_pending
|vpiIndex:
\_ref_obj: (oldest_id), line:196
|vpiName:oldest_id
|vpiLhs:
\_ref_obj: (retiring_next_cycle), line:196
|vpiName:retiring_next_cycle
|vpiFullName:work@write_back.retiring_next_cycle
|vpiContAssign:
\_cont_assign: , line:209
|vpiRhs:
\_operation: , line:209
|vpiOpType:28
|vpiOperand:
\_ref_obj: (retiring), line:209
|vpiName:retiring
|vpiFullName:work@write_back.retiring
|vpiOperand:
\_operation: , line:209
|vpiOpType:4
|vpiOperand:
\_ref_obj: (retiring_instruction_packet.is_store), line:209
|vpiName:retiring_instruction_packet.is_store
|vpiFullName:work@write_back.retiring_instruction_packet.is_store
|vpiLhs:
\_ref_obj: (instruction_complete), line:209
|vpiName:instruction_complete
|vpiFullName:work@write_back.instruction_complete
|vpiContAssign:
\_cont_assign: , line:211
|vpiRhs:
\_ref_obj: (retiring_instruction_packet.rd_addr), line:211
|vpiName:retiring_instruction_packet.rd_addr
|vpiFullName:work@write_back.retiring_instruction_packet.rd_addr
|vpiLhs:
\_ref_obj: (rf_wb.rd_addr), line:211
|vpiName:rf_wb.rd_addr
|vpiFullName:work@write_back.rf_wb.rd_addr
|vpiContAssign:
\_cont_assign: , line:212
|vpiRhs:
\_ref_obj: (id_retiring), line:212
|vpiName:id_retiring
|vpiFullName:work@write_back.id_retiring
|vpiLhs:
\_ref_obj: (rf_wb.id), line:212
|vpiName:rf_wb.id
|vpiFullName:work@write_back.rf_wb.id
|vpiContAssign:
\_cont_assign: , line:213
|vpiRhs:
\_ref_obj: (instruction_complete), line:213
|vpiName:instruction_complete
|vpiFullName:work@write_back.instruction_complete
|vpiLhs:
\_ref_obj: (rf_wb.retiring), line:213
|vpiName:rf_wb.retiring
|vpiFullName:work@write_back.rf_wb.retiring
|vpiContAssign:
\_cont_assign: , line:214
|vpiRhs:
\_operation: , line:214
|vpiOpType:7
|vpiOperand:
\_ref_obj: (retiring_instruction_packet.rd_addr), line:214
|vpiName:retiring_instruction_packet.rd_addr
|vpiFullName:work@write_back.retiring_instruction_packet.rd_addr
|vpiLhs:
\_ref_obj: (rf_wb.rd_nzero), line:214
|vpiName:rf_wb.rd_nzero
|vpiFullName:work@write_back.rf_wb.rd_nzero
|vpiContAssign:
\_cont_assign: , line:215
|vpiRhs:
\_bit_select: (results_by_id), line:215
|vpiName:results_by_id
|vpiFullName:work@write_back.results_by_id
|vpiIndex:
\_ref_obj: (id_retiring), line:215
|vpiName:id_retiring
|vpiLhs:
\_ref_obj: (rf_wb.rd_data), line:215
|vpiName:rf_wb.rd_data
|vpiFullName:work@write_back.rf_wb.rd_data
|vpiContAssign:
\_cont_assign: , line:218
|vpiRhs:
\_bit_select: (id_writeback_pending_r), line:218
|vpiName:id_writeback_pending_r
|vpiFullName:work@write_back.id_writeback_pending_r
|vpiIndex:
\_ref_obj: (rf_wb.rs1_id), line:218
|vpiName:rf_wb.rs1_id
|vpiLhs:
\_ref_obj: (rf_wb.rs1_valid), line:218
|vpiName:rf_wb.rs1_valid
|vpiFullName:work@write_back.rf_wb.rs1_valid
|vpiContAssign:
\_cont_assign: , line:219
|vpiRhs:
\_bit_select: (id_writeback_pending_r), line:219
|vpiName:id_writeback_pending_r
|vpiFullName:work@write_back.id_writeback_pending_r
|vpiIndex:
\_ref_obj: (rf_wb.rs2_id), line:219
|vpiName:rf_wb.rs2_id
|vpiLhs:
\_ref_obj: (rf_wb.rs2_valid), line:219
|vpiName:rf_wb.rs2_valid
|vpiFullName:work@write_back.rf_wb.rs2_valid
|vpiContAssign:
\_cont_assign: , line:220
|vpiRhs:
\_bit_select: (results_by_id), line:220
|vpiName:results_by_id
|vpiFullName:work@write_back.results_by_id
|vpiIndex:
\_ref_obj: (rf_wb.rs1_id), line:220
|vpiName:rf_wb.rs1_id
|vpiLhs:
\_ref_obj: (rf_wb.rs1_data), line:220
|vpiName:rf_wb.rs1_data
|vpiFullName:work@write_back.rf_wb.rs1_data
|vpiContAssign:
\_cont_assign: , line:221
|vpiRhs:
\_bit_select: (results_by_id), line:221
|vpiName:results_by_id
|vpiFullName:work@write_back.results_by_id
|vpiIndex:
\_ref_obj: (rf_wb.rs2_id), line:221
|vpiName:rf_wb.rs2_id
|vpiLhs:
\_ref_obj: (rf_wb.rs2_data), line:221
|vpiName:rf_wb.rs2_data
|vpiFullName:work@write_back.rf_wb.rs2_data
|vpiNet:
\_logic_net: (clk), line:27
|vpiNet:
\_logic_net: (rst), line:28
|vpiNet:
\_logic_net: (gc_fetch_flush), line:30
|vpiNet:
\_logic_net: (instruction_issued_with_rd), line:31
|vpiNet:
\_logic_net: (unit_wb), line:33
|vpiNet:
\_logic_net: (instruction_complete), line:36
|vpiNet:
\_logic_net: (instruction_queue_empty), line:37
|vpiNet:
\_logic_net: (oldest_id), line:38
|vpiNet:
\_logic_net: (store_done_id), line:40
|vpiNet:
\_logic_net: (store_complete), line:41
|vpiNet:
\_logic_net: (store_issued_with_data), line:44
|vpiNet:
\_logic_net: (store_data), line:45
|vpiNet:
\_logic_net: (tr_wb_mux_contention), line:48
|vpiNet:
\_logic_net: (id_metadata), line:53
|vpiName:id_metadata
|vpiFullName:work@write_back.id_metadata
|vpiNetType:36
|vpiNet:
\_logic_net: (unit_instruction_id), line:56
|vpiName:unit_instruction_id
|vpiFullName:work@write_back.unit_instruction_id
|vpiNet:
\_logic_net: (unit_done), line:57
|vpiName:unit_done
|vpiFullName:work@write_back.unit_done
|vpiNetType:36
|vpiNet:
\_logic_net: (unit_rd), line:59
|vpiName:unit_rd
|vpiFullName:work@write_back.unit_rd
|vpiNetType:36
|vpiNet:
\_logic_net: (id_unit_select), line:61
|vpiName:id_unit_select
|vpiFullName:work@write_back.id_unit_select
|vpiNetType:36
|vpiNet:
\_logic_net: (id_unit_select_r), line:62
|vpiName:id_unit_select_r
|vpiFullName:work@write_back.id_unit_select_r
|vpiNetType:36
|vpiNet:
\_logic_net: (results_by_id), line:64
|vpiName:results_by_id
|vpiFullName:work@write_back.results_by_id
|vpiNetType:36
|vpiNet:
\_logic_net: (results_by_id_new), line:65
|vpiName:results_by_id_new
|vpiFullName:work@write_back.results_by_id_new
|vpiNetType:36
|vpiNet:
\_logic_net: (id_retiring), line:66
|vpiName:id_retiring
|vpiFullName:work@write_back.id_retiring
|vpiNet:
\_logic_net: (retiring_instruction_packet), line:67
|vpiName:retiring_instruction_packet
|vpiFullName:work@write_back.retiring_instruction_packet
|vpiNet:
\_logic_net: (id_inuse), line:69
|vpiName:id_inuse
|vpiFullName:work@write_back.id_inuse
|vpiNetType:36
|vpiNet:
\_logic_net: (id_writeback_pending), line:71
|vpiName:id_writeback_pending
|vpiFullName:work@write_back.id_writeback_pending
|vpiNetType:36
|vpiNet:
\_logic_net: (id_writeback_pending_r), line:72
|vpiName:id_writeback_pending_r
|vpiFullName:work@write_back.id_writeback_pending_r
|vpiNetType:36
|vpiNet:
\_logic_net: (id_writing_to_buffer), line:74
|vpiName:id_writing_to_buffer
|vpiFullName:work@write_back.id_writing_to_buffer
|vpiNetType:36
|vpiNet:
\_logic_net: (id_retiring_one_hot), line:76
|vpiName:id_retiring_one_hot
|vpiFullName:work@write_back.id_retiring_one_hot
|vpiNetType:36
|vpiNet:
\_logic_net: (id_issued_one_hot), line:77
|vpiName:id_issued_one_hot
|vpiFullName:work@write_back.id_issued_one_hot
|vpiNetType:36
|vpiNet:
\_logic_net: (retiring_next_cycle), line:79
|vpiName:retiring_next_cycle
|vpiFullName:work@write_back.retiring_next_cycle
|vpiNetType:36
|vpiNet:
\_logic_net: (retiring), line:79
|vpiName:retiring
|vpiFullName:work@write_back.retiring
|vpiNetType:36
|vpiNet:
\_logic_net: (store_mux), line:134
|vpiName:store_mux
|vpiFullName:work@write_back.store_mux
|vpiNetType:36
|vpiNet:
\_logic_net: (rf_wb), line:34
|vpiName:rf_wb
|vpiFullName:work@write_back.rf_wb
|vpiNet:
\_logic_net: (ti), line:35
|vpiName:ti
|vpiFullName:work@write_back.ti
|vpiNet:
\_logic_net: (store_forwarding), line:42
|vpiName:store_forwarding
|vpiFullName:work@write_back.store_forwarding
|vpiTypedef:
\_struct_typespec: (alu_inputs_t), line:301
|vpiTypedef:
\_enum_typespec: (alu_logic_op_t), line:84
|vpiTypedef:
\_enum_typespec: (alu_op_t), line:91
|vpiTypedef:
\_enum_typespec: (alu_rs1_op_t), line:97
|vpiTypedef:
\_enum_typespec: (alu_rs2_op_t), line:104
|vpiTypedef:
\_struct_typespec: (amo_alu_inputs_t), line:356
|vpiTypedef:
\_struct_typespec: (amo_details_t), line:362
|vpiTypedef:
\_enum_typespec: (amo_t), line:354
|vpiTypedef:
\_struct_typespec: (branch_inputs_t), line:313
|vpiTypedef:
\_logic_typespec: (branch_predictor_metadata_t), line:32
|vpiTypedef:
\_struct_typespec: (branch_results_t), line:330
|vpiTypedef:
\_enum_typespec: (bus_type_t), line:86
|vpiTypedef:
\_struct_typespec: (csr_inputs_t), line:396
|vpiTypedef:
\_enum_typespec: (csr_op_t), line:218
|vpiTypedef:
\_enum_typespec: (csr_t), line:201
|vpiTypedef:
\_struct_typespec: (data_access_shared_inputs_t), line:427
|vpiTypedef:
\_struct_typespec: (div_inputs_t), line:389
|vpiTypedef:
\_enum_typespec: (div_type), line:66
|vpiTypedef:
\_enum_typespec: (exception_code_t), line:245
|vpiTypedef:
\_struct_typespec: (exception_packet_t), line:263
|vpiTypedef:
\_struct_typespec: (fetch_buffer_packet_t), line:276
|vpiTypedef:
\_enum_typespec: (fifo_type_t), line:440
|vpiTypedef:
\_enum_typespec: (fn3_arith_t), line:76
|vpiTypedef:
\_enum_typespec: (fn3_branch_t), line:126
|vpiTypedef:
\_enum_typespec: (fn3_csr_t), line:212
|vpiTypedef:
\_enum_typespec: (fn3_ls_t), line:115
|vpiTypedef:
\_enum_typespec: (fn3_mul_div_t), line:138
|vpiTypedef:
\_struct_typespec: (gc_inputs_t), line:404
|vpiTypedef:
\_struct_typespec: (inflight_instruction_packet), line:271
|vpiTypedef:
\_logic_typespec: (instruction_id_t), line:30
|vpiTypedef:
\_enum_typespec: (interrupt_code_t), line:261
|vpiTypedef:
\_struct_typespec: (load_store_inputs_t), line:369
|vpiTypedef:
\_struct_typespec: (mul_inputs_t), line:383
|vpiTypedef:
\_enum_typespec: (opcodes_t), line:48
|vpiTypedef:
\_enum_typespec: (opcodes_trimmed_t), line:65
|vpiTypedef:
\_struct_typespec: (simulation_named_regfile), line:476
|vpiTypedef:
\_struct_typespec: (taiga_trace_events_t), line:442
|vpiTypedef:
\_struct_typespec: (to_l1_arbiter_packet), line:418
|vpiTypedef:
\_struct_typespec: (trace_outputs_t), line:469
|vpiTypedef:
\_logic_typespec: (unit_id_t), line:31
|vpiTypedef:
\_struct_typespec: (unit_writeback_t), line:295
|vpiTypedef:
\_enum_typespec: (vm_t), line:223
|uhdmtopModules:
\_module: work@div_unit_core_wrapper (work@div_unit_core_wrapper), file:third_party/cores/taiga/core/div_unit_core_wrapper.sv, line:4
|vpiDefName:work@div_unit_core_wrapper
|vpiName:work@div_unit_core_wrapper
|vpiPort:
\_port: (clk), line:8, parent:work@div_unit_core_wrapper
|vpiName:clk
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (clk), line:8, parent:work@div_unit_core_wrapper
|vpiName:clk
|vpiFullName:work@div_unit_core_wrapper.clk
|vpiNetType:36
|vpiPort:
\_port: (rst), line:9, parent:work@div_unit_core_wrapper
|vpiName:rst
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (rst), line:9, parent:work@div_unit_core_wrapper
|vpiName:rst
|vpiFullName:work@div_unit_core_wrapper.rst
|vpiNetType:36
|vpiPort:
\_port: (start), line:10, parent:work@div_unit_core_wrapper
|vpiName:start
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (start), line:10, parent:work@div_unit_core_wrapper
|vpiName:start
|vpiFullName:work@div_unit_core_wrapper.start
|vpiNetType:36
|vpiPort:
\_port: (ack), line:11, parent:work@div_unit_core_wrapper
|vpiName:ack
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (ack), line:11, parent:work@div_unit_core_wrapper
|vpiName:ack
|vpiFullName:work@div_unit_core_wrapper.ack
|vpiNetType:36
|vpiPort:
\_port: (A), line:12, parent:work@div_unit_core_wrapper
|vpiName:A
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (A), line:12, parent:work@div_unit_core_wrapper
|vpiName:A
|vpiFullName:work@div_unit_core_wrapper.A
|vpiNetType:36
|vpiRange:
\_range: , line:12
|vpiLeftRange:
\_constant: , line:12
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:12
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiPort:
\_port: (B), line:13, parent:work@div_unit_core_wrapper
|vpiName:B
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (B), line:13, parent:work@div_unit_core_wrapper
|vpiName:B
|vpiFullName:work@div_unit_core_wrapper.B
|vpiNetType:36
|vpiRange:
\_range: , line:13
|vpiLeftRange:
\_constant: , line:13
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:13
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiPort:
\_port: (Q), line:14, parent:work@div_unit_core_wrapper
|vpiName:Q
|vpiDirection:2
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (Q), line:14, parent:work@div_unit_core_wrapper
|vpiName:Q
|vpiFullName:work@div_unit_core_wrapper.Q
|vpiNetType:36
|vpiRange:
\_range: , line:14
|vpiLeftRange:
\_constant: , line:14
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:14
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiPort:
\_port: (R), line:15, parent:work@div_unit_core_wrapper
|vpiName:R
|vpiDirection:2
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (R), line:15, parent:work@div_unit_core_wrapper
|vpiName:R
|vpiFullName:work@div_unit_core_wrapper.R
|vpiNetType:36
|vpiRange:
\_range: , line:15
|vpiLeftRange:
\_constant: , line:15
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:15
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiPort:
\_port: (complete), line:16, parent:work@div_unit_core_wrapper
|vpiName:complete
|vpiDirection:2
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (complete), line:16, parent:work@div_unit_core_wrapper
|vpiName:complete
|vpiFullName:work@div_unit_core_wrapper.complete
|vpiNetType:36
|vpiPort:
\_port: (B_is_zero), line:17, parent:work@div_unit_core_wrapper
|vpiName:B_is_zero
|vpiDirection:2
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (B_is_zero), line:17, parent:work@div_unit_core_wrapper
|vpiName:B_is_zero
|vpiFullName:work@div_unit_core_wrapper.B_is_zero
|vpiNetType:36
|vpiModule:
\_module: work@div_algorithm (div_core), file:third_party/cores/taiga/core/div_unit_core_wrapper.sv, line:44, parent:work@div_unit_core_wrapper
|vpiDefName:work@div_algorithm
|vpiName:div_core
|vpiFullName:work@div_unit_core_wrapper.div_core
|vpiPort:
\_port: (clk), line:29, parent:div_core
|vpiName:clk
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (clk), line:45
|vpiName:clk
|vpiActual:
\_logic_net: (clk), line:8, parent:work@div_unit_core_wrapper
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (clk), line:29, parent:div_core
|vpiName:clk
|vpiFullName:work@div_unit_core_wrapper.div_core.clk
|vpiNetType:36
|vpiPort:
\_port: (rst), line:30, parent:div_core
|vpiName:rst
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (rst), line:46
|vpiName:rst
|vpiActual:
\_logic_net: (rst), line:9, parent:work@div_unit_core_wrapper
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (rst), line:30, parent:div_core
|vpiName:rst
|vpiFullName:work@div_unit_core_wrapper.div_core.rst
|vpiNetType:36
|vpiPort:
\_port: (start), line:31, parent:div_core
|vpiName:start
|vpiDirection:5
|vpiHighConn:
\_ref_obj: (start_r), line:47
|vpiName:start_r
|vpiActual:
\_logic_net: (start_r), line:21, parent:work@div_unit_core_wrapper
|vpiName:start_r
|vpiFullName:work@div_unit_core_wrapper.start_r
|vpiNetType:36
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_modport: (divider)
|vpiName:divider
|vpiIODecl:
\_io_decl: (remainder)
|vpiName:remainder
|vpiDirection:2
|vpiExpr:
\_logic_net: (remainder), line:247
|vpiName:remainder
|vpiNetType:36
|vpiRange:
\_range: , line:247
|vpiLeftRange:
\_constant: , line:247
|vpiDecompile:31
|INT:31
|vpiRightRange:
\_constant: , line:247
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (quotient)
|vpiName:quotient
|vpiDirection:2
|vpiExpr:
\_logic_net: (quotient), line:248
|vpiName:quotient
|vpiNetType:36
|vpiRange:
\_range: , line:248
|vpiLeftRange:
\_constant: , line:248
|vpiDecompile:31
|INT:31
|vpiRightRange:
\_constant: , line:248
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (done)
|vpiName:done
|vpiDirection:2
|vpiExpr:
\_logic_net: (done), line:249
|vpiName:done
|vpiNetType:36
|vpiIODecl:
\_io_decl: (divisor_is_zero)
|vpiName:divisor_is_zero
|vpiDirection:2
|vpiExpr:
\_logic_net: (divisor_is_zero), line:250
|vpiName:divisor_is_zero
|vpiNetType:36
|vpiIODecl:
\_io_decl: (dividend)
|vpiName:dividend
|vpiDirection:1
|vpiExpr:
\_logic_net: (dividend), line:245
|vpiName:dividend
|vpiNetType:36
|vpiRange:
\_range: , line:245
|vpiLeftRange:
\_constant: , line:245
|vpiDecompile:31
|INT:31
|vpiRightRange:
\_constant: , line:245
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (divisor)
|vpiName:divisor
|vpiDirection:1
|vpiExpr:
\_logic_net: (divisor), line:246
|vpiName:divisor
|vpiNetType:36
|vpiRange:
\_range: , line:246
|vpiLeftRange:
\_constant: , line:246
|vpiDecompile:31
|INT:31
|vpiRightRange:
\_constant: , line:246
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (start)
|vpiName:start
|vpiDirection:1
|vpiExpr:
\_logic_net: (start), line:244
|vpiName:start
|vpiNetType:36
|vpiInterface:
\_interface: work@unsigned_division_interface (div), file:third_party/cores/taiga/core/div_unit_core_wrapper.sv, line:44
|vpiDefName:work@unsigned_division_interface
|vpiName:div
|vpiModport:
\_modport: (divider)
|vpiModport:
\_modport: (requester)
|vpiName:requester
|vpiIODecl:
\_io_decl: (remainder)
|vpiName:remainder
|vpiDirection:1
|vpiExpr:
\_logic_net: (remainder), line:247
|vpiIODecl:
\_io_decl: (quotient)
|vpiName:quotient
|vpiDirection:1
|vpiExpr:
\_logic_net: (quotient), line:248
|vpiIODecl:
\_io_decl: (done)
|vpiName:done
|vpiDirection:1
|vpiExpr:
\_logic_net: (done), line:249
|vpiIODecl:
\_io_decl: (divisor_is_zero)
|vpiName:divisor_is_zero
|vpiDirection:1
|vpiExpr:
\_logic_net: (divisor_is_zero), line:250
|vpiIODecl:
\_io_decl: (dividend)
|vpiName:dividend
|vpiDirection:2
|vpiExpr:
\_logic_net: (dividend), line:245
|vpiIODecl:
\_io_decl: (divisor)
|vpiName:divisor
|vpiDirection:2
|vpiExpr:
\_logic_net: (divisor), line:246
|vpiIODecl:
\_io_decl: (start)
|vpiName:start
|vpiDirection:2
|vpiExpr:
\_logic_net: (start), line:244
|vpiInterface:
\_interface: work@unsigned_division_interface (div), file:third_party/cores/taiga/core/div_unit_core_wrapper.sv, line:44
|vpiPort:
\_port: (ack), parent:div_core
|vpiName:ack
|vpiHighConn:
\_ref_obj: (ack_r), line:48
|vpiName:ack_r
|vpiActual:
\_logic_net: (ack_r), line:22, parent:work@div_unit_core_wrapper
|vpiName:ack_r
|vpiFullName:work@div_unit_core_wrapper.ack_r
|vpiNetType:36
|vpiPort:
\_port: (A), parent:div_core
|vpiName:A
|vpiHighConn:
\_ref_obj: (A_r), line:49
|vpiName:A_r
|vpiActual:
\_logic_net: (A_r), line:23, parent:work@div_unit_core_wrapper
|vpiName:A_r
|vpiFullName:work@div_unit_core_wrapper.A_r
|vpiNetType:36
|vpiRange:
\_range: , line:23
|vpiLeftRange:
\_constant: , line:23
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:23
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiPort:
\_port: (B), parent:div_core
|vpiName:B
|vpiHighConn:
\_ref_obj: (B_r), line:50
|vpiName:B_r
|vpiActual:
\_logic_net: (B_r), line:24, parent:work@div_unit_core_wrapper
|vpiName:B_r
|vpiFullName:work@div_unit_core_wrapper.B_r
|vpiNetType:36
|vpiRange:
\_range: , line:24
|vpiLeftRange:
\_constant: , line:24
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:24
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiPort:
\_port: (Q), parent:div_core
|vpiName:Q
|vpiHighConn:
\_ref_obj: (Q_o), line:51
|vpiName:Q_o
|vpiActual:
\_logic_net: (Q_o), line:29, parent:work@div_unit_core_wrapper
|vpiName:Q_o
|vpiFullName:work@div_unit_core_wrapper.Q_o
|vpiNetType:36
|vpiRange:
\_range: , line:29
|vpiLeftRange:
\_constant: , line:29
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:29
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiPort:
\_port: (R), parent:div_core
|vpiName:R
|vpiHighConn:
\_ref_obj: (R_o), line:52
|vpiName:R_o
|vpiActual:
\_logic_net: (R_o), line:30, parent:work@div_unit_core_wrapper
|vpiName:R_o
|vpiFullName:work@div_unit_core_wrapper.R_o
|vpiNetType:36
|vpiRange:
\_range: , line:30
|vpiLeftRange:
\_constant: , line:30
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:30
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiPort:
\_port: (complete), parent:div_core
|vpiName:complete
|vpiHighConn:
\_ref_obj: (complete_o), line:53
|vpiName:complete_o
|vpiActual:
\_logic_net: (complete_o), line:31, parent:work@div_unit_core_wrapper
|vpiName:complete_o
|vpiFullName:work@div_unit_core_wrapper.complete_o
|vpiNetType:36
|vpiPort:
\_port: (B_is_zero), parent:div_core
|vpiName:B_is_zero
|vpiHighConn:
\_ref_obj: (B_is_zero_o), line:54
|vpiName:B_is_zero_o
|vpiActual:
\_logic_net: (B_is_zero_o), line:32, parent:work@div_unit_core_wrapper
|vpiName:B_is_zero_o
|vpiFullName:work@div_unit_core_wrapper.B_is_zero_o
|vpiNetType:36
|vpiModule:
\_module: work@div_radix2 (div_block), file:third_party/cores/taiga/core/div_algorithms/div_algorithm.sv, line:36, parent:div_core
|vpiDefName:work@div_radix2
|vpiName:div_block
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block
|vpiPort:
\_port: (clk), line:27, parent:div_block
|vpiName:clk
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (clk), line:36
|vpiName:clk
|vpiActual:
\_logic_net: (clk), line:29, parent:div_core
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (clk), line:27, parent:div_block
|vpiName:clk
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.clk
|vpiNetType:36
|vpiPort:
\_port: (rst), line:28, parent:div_block
|vpiName:rst
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (rst), line:36
|vpiName:rst
|vpiActual:
\_logic_net: (rst), line:30, parent:div_core
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (rst), line:28, parent:div_block
|vpiName:rst
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.rst
|vpiNetType:36
|vpiPort:
\_port: (div), line:29, parent:div_block
|vpiName:div
|vpiDirection:5
|vpiHighConn:
\_ref_obj: (div), line:36
|vpiName:div
|vpiActual:
\_interface: work@unsigned_division_interface (div), file:third_party/cores/taiga/core/div_unit_core_wrapper.sv, line:44
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_modport: (divider)
|vpiName:divider
|vpiIODecl:
\_io_decl: (remainder)
|vpiName:remainder
|vpiDirection:2
|vpiExpr:
\_logic_net: (remainder), line:247
|vpiName:remainder
|vpiNetType:36
|vpiRange:
\_range: , line:247
|vpiLeftRange:
\_constant: , line:247
|vpiDecompile:31
|INT:31
|vpiRightRange:
\_constant: , line:247
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (quotient)
|vpiName:quotient
|vpiDirection:2
|vpiExpr:
\_logic_net: (quotient), line:248
|vpiName:quotient
|vpiNetType:36
|vpiRange:
\_range: , line:248
|vpiLeftRange:
\_constant: , line:248
|vpiDecompile:31
|INT:31
|vpiRightRange:
\_constant: , line:248
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (done)
|vpiName:done
|vpiDirection:2
|vpiExpr:
\_logic_net: (done), line:249
|vpiName:done
|vpiNetType:36
|vpiIODecl:
\_io_decl: (divisor_is_zero)
|vpiName:divisor_is_zero
|vpiDirection:2
|vpiExpr:
\_logic_net: (divisor_is_zero), line:250
|vpiName:divisor_is_zero
|vpiNetType:36
|vpiIODecl:
\_io_decl: (dividend)
|vpiName:dividend
|vpiDirection:1
|vpiExpr:
\_logic_net: (dividend), line:245
|vpiName:dividend
|vpiNetType:36
|vpiRange:
\_range: , line:245
|vpiLeftRange:
\_constant: , line:245
|vpiDecompile:31
|INT:31
|vpiRightRange:
\_constant: , line:245
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (divisor)
|vpiName:divisor
|vpiDirection:1
|vpiExpr:
\_logic_net: (divisor), line:246
|vpiName:divisor
|vpiNetType:36
|vpiRange:
\_range: , line:246
|vpiLeftRange:
\_constant: , line:246
|vpiDecompile:31
|INT:31
|vpiRightRange:
\_constant: , line:246
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (start)
|vpiName:start
|vpiDirection:1
|vpiExpr:
\_logic_net: (start), line:244
|vpiName:start
|vpiNetType:36
|vpiInterface:
\_interface: work@unsigned_division_interface (div), file:third_party/cores/taiga/core/div_algorithms/div_algorithm.sv, line:36
|vpiDefName:work@unsigned_division_interface
|vpiName:div
|vpiModport:
\_modport: (divider)
|vpiModport:
\_modport: (requester)
|vpiName:requester
|vpiIODecl:
\_io_decl: (remainder)
|vpiName:remainder
|vpiDirection:1
|vpiExpr:
\_logic_net: (remainder), line:247
|vpiIODecl:
\_io_decl: (quotient)
|vpiName:quotient
|vpiDirection:1
|vpiExpr:
\_logic_net: (quotient), line:248
|vpiIODecl:
\_io_decl: (done)
|vpiName:done
|vpiDirection:1
|vpiExpr:
\_logic_net: (done), line:249
|vpiIODecl:
\_io_decl: (divisor_is_zero)
|vpiName:divisor_is_zero
|vpiDirection:1
|vpiExpr:
\_logic_net: (divisor_is_zero), line:250
|vpiIODecl:
\_io_decl: (dividend)
|vpiName:dividend
|vpiDirection:2
|vpiExpr:
\_logic_net: (dividend), line:245
|vpiIODecl:
\_io_decl: (divisor)
|vpiName:divisor
|vpiDirection:2
|vpiExpr:
\_logic_net: (divisor), line:246
|vpiIODecl:
\_io_decl: (start)
|vpiName:start
|vpiDirection:2
|vpiExpr:
\_logic_net: (start), line:244
|vpiInterface:
\_interface: work@unsigned_division_interface (div), file:third_party/cores/taiga/core/div_algorithms/div_algorithm.sv, line:36
|vpiNet:
\_logic_net: (clk), line:27, parent:div_block
|vpiNet:
\_logic_net: (rst), line:28, parent:div_block
|vpiNet:
\_logic_net: (terminate), line:32, parent:div_block
|vpiName:terminate
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.terminate
|vpiNetType:36
|vpiNet:
\_logic_net: (new_PR), line:34, parent:div_block
|vpiName:new_PR
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.new_PR
|vpiNetType:36
|vpiRange:
\_range: , line:34
|vpiLeftRange:
\_ref_obj: (div.DATA_WIDTH), line:34
|vpiName:div.DATA_WIDTH
|vpiRightRange:
\_constant: , line:34
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (PR), line:35, parent:div_block
|vpiName:PR
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.PR
|vpiNetType:36
|vpiRange:
\_range: , line:35
|vpiLeftRange:
\_ref_obj: (div.DATA_WIDTH), line:35
|vpiName:div.DATA_WIDTH
|vpiRightRange:
\_constant: , line:35
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (shift_count), line:36, parent:div_block
|vpiName:shift_count
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.shift_count
|vpiNetType:36
|vpiRange:
\_range: , line:36
|vpiLeftRange:
\_operation: , line:36
|vpiOpType:11
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:36
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:36
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:36
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (negative_sub_rst), line:37, parent:div_block
|vpiName:negative_sub_rst
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.negative_sub_rst
|vpiNetType:36
|vpiNet:
\_logic_net: (div), line:29, parent:div_block
|vpiName:div
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.div
|vpiInstance:
\_module: work@div_algorithm (div_core), file:third_party/cores/taiga/core/div_unit_core_wrapper.sv, line:44, parent:work@div_unit_core_wrapper
|vpiModule:
\_module: work@div_radix2_ET (div_block), file:third_party/cores/taiga/core/div_algorithms/div_algorithm.sv, line:37, parent:div_core
|vpiDefName:work@div_radix2_ET
|vpiName:div_block
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block
|vpiPort:
\_port: (clk), line:27, parent:div_block
|vpiName:clk
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (clk), line:37
|vpiName:clk
|vpiActual:
\_logic_net: (clk), line:29, parent:div_core
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (clk), line:27, parent:div_block
|vpiName:clk
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.clk
|vpiNetType:36
|vpiPort:
\_port: (rst), line:28, parent:div_block
|vpiName:rst
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (rst), line:37
|vpiName:rst
|vpiActual:
\_logic_net: (rst), line:30, parent:div_core
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (rst), line:28, parent:div_block
|vpiName:rst
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.rst
|vpiNetType:36
|vpiPort:
\_port: (div), line:29, parent:div_block
|vpiName:div
|vpiDirection:5
|vpiHighConn:
\_ref_obj: (div), line:37
|vpiName:div
|vpiActual:
\_interface: work@unsigned_division_interface (div), file:third_party/cores/taiga/core/div_unit_core_wrapper.sv, line:44
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_modport: (divider)
|vpiName:divider
|vpiIODecl:
\_io_decl: (remainder)
|vpiName:remainder
|vpiDirection:2
|vpiExpr:
\_logic_net: (remainder), line:247
|vpiName:remainder
|vpiNetType:36
|vpiRange:
\_range: , line:247
|vpiLeftRange:
\_constant: , line:247
|vpiDecompile:31
|INT:31
|vpiRightRange:
\_constant: , line:247
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (quotient)
|vpiName:quotient
|vpiDirection:2
|vpiExpr:
\_logic_net: (quotient), line:248
|vpiName:quotient
|vpiNetType:36
|vpiRange:
\_range: , line:248
|vpiLeftRange:
\_constant: , line:248
|vpiDecompile:31
|INT:31
|vpiRightRange:
\_constant: , line:248
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (done)
|vpiName:done
|vpiDirection:2
|vpiExpr:
\_logic_net: (done), line:249
|vpiName:done
|vpiNetType:36
|vpiIODecl:
\_io_decl: (divisor_is_zero)
|vpiName:divisor_is_zero
|vpiDirection:2
|vpiExpr:
\_logic_net: (divisor_is_zero), line:250
|vpiName:divisor_is_zero
|vpiNetType:36
|vpiIODecl:
\_io_decl: (dividend)
|vpiName:dividend
|vpiDirection:1
|vpiExpr:
\_logic_net: (dividend), line:245
|vpiName:dividend
|vpiNetType:36
|vpiRange:
\_range: , line:245
|vpiLeftRange:
\_constant: , line:245
|vpiDecompile:31
|INT:31
|vpiRightRange:
\_constant: , line:245
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (divisor)
|vpiName:divisor
|vpiDirection:1
|vpiExpr:
\_logic_net: (divisor), line:246
|vpiName:divisor
|vpiNetType:36
|vpiRange:
\_range: , line:246
|vpiLeftRange:
\_constant: , line:246
|vpiDecompile:31
|INT:31
|vpiRightRange:
\_constant: , line:246
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (start)
|vpiName:start
|vpiDirection:1
|vpiExpr:
\_logic_net: (start), line:244
|vpiName:start
|vpiNetType:36
|vpiInterface:
\_interface: work@unsigned_division_interface (div), file:third_party/cores/taiga/core/div_algorithms/div_algorithm.sv, line:37
|vpiDefName:work@unsigned_division_interface
|vpiName:div
|vpiModport:
\_modport: (divider)
|vpiModport:
\_modport: (requester)
|vpiName:requester
|vpiIODecl:
\_io_decl: (remainder)
|vpiName:remainder
|vpiDirection:1
|vpiExpr:
\_logic_net: (remainder), line:247
|vpiIODecl:
\_io_decl: (quotient)
|vpiName:quotient
|vpiDirection:1
|vpiExpr:
\_logic_net: (quotient), line:248
|vpiIODecl:
\_io_decl: (done)
|vpiName:done
|vpiDirection:1
|vpiExpr:
\_logic_net: (done), line:249
|vpiIODecl:
\_io_decl: (divisor_is_zero)
|vpiName:divisor_is_zero
|vpiDirection:1
|vpiExpr:
\_logic_net: (divisor_is_zero), line:250
|vpiIODecl:
\_io_decl: (dividend)
|vpiName:dividend
|vpiDirection:2
|vpiExpr:
\_logic_net: (dividend), line:245
|vpiIODecl:
\_io_decl: (divisor)
|vpiName:divisor
|vpiDirection:2
|vpiExpr:
\_logic_net: (divisor), line:246
|vpiIODecl:
\_io_decl: (start)
|vpiName:start
|vpiDirection:2
|vpiExpr:
\_logic_net: (start), line:244
|vpiInterface:
\_interface: work@unsigned_division_interface (div), file:third_party/cores/taiga/core/div_algorithms/div_algorithm.sv, line:37
|vpiNet:
\_logic_net: (clk), line:27, parent:div_block
|vpiNet:
\_logic_net: (rst), line:28, parent:div_block
|vpiNet:
\_logic_net: (terminate), line:32, parent:div_block
|vpiName:terminate
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.terminate
|vpiNetType:36
|vpiNet:
\_logic_net: (terminate_early), line:33, parent:div_block
|vpiName:terminate_early
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.terminate_early
|vpiNetType:36
|vpiNet:
\_logic_net: (new_PR), line:35, parent:div_block
|vpiName:new_PR
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.new_PR
|vpiNetType:36
|vpiRange:
\_range: , line:35
|vpiLeftRange:
\_ref_obj: (div.DATA_WIDTH), line:35
|vpiName:div.DATA_WIDTH
|vpiRightRange:
\_constant: , line:35
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (PR), line:36, parent:div_block
|vpiName:PR
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.PR
|vpiNetType:36
|vpiRange:
\_range: , line:36
|vpiLeftRange:
\_ref_obj: (div.DATA_WIDTH), line:36
|vpiName:div.DATA_WIDTH
|vpiRightRange:
\_constant: , line:36
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (shift_count), line:38, parent:div_block
|vpiName:shift_count
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.shift_count
|vpiNetType:36
|vpiRange:
\_range: , line:38
|vpiLeftRange:
\_operation: , line:38
|vpiOpType:11
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:38
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:38
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:38
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (negative_sub_rst), line:40, parent:div_block
|vpiName:negative_sub_rst
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.negative_sub_rst
|vpiNetType:36
|vpiNet:
\_logic_net: (div), line:29, parent:div_block
|vpiName:div
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.div
|vpiInstance:
\_module: work@div_algorithm (div_core), file:third_party/cores/taiga/core/div_unit_core_wrapper.sv, line:44, parent:work@div_unit_core_wrapper
|vpiModule:
\_module: work@div_radix2_ET_full (div_block), file:third_party/cores/taiga/core/div_algorithms/div_algorithm.sv, line:38, parent:div_core
|vpiDefName:work@div_radix2_ET_full
|vpiName:div_block
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block
|vpiPort:
\_port: (clk), line:27, parent:div_block
|vpiName:clk
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (clk), line:38
|vpiName:clk
|vpiActual:
\_logic_net: (clk), line:29, parent:div_core
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (clk), line:27, parent:div_block
|vpiName:clk
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.clk
|vpiNetType:36
|vpiPort:
\_port: (rst), line:28, parent:div_block
|vpiName:rst
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (rst), line:38
|vpiName:rst
|vpiActual:
\_logic_net: (rst), line:30, parent:div_core
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (rst), line:28, parent:div_block
|vpiName:rst
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.rst
|vpiNetType:36
|vpiPort:
\_port: (div), line:29, parent:div_block
|vpiName:div
|vpiDirection:5
|vpiHighConn:
\_ref_obj: (div), line:38
|vpiName:div
|vpiActual:
\_interface: work@unsigned_division_interface (div), file:third_party/cores/taiga/core/div_unit_core_wrapper.sv, line:44
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_modport: (divider)
|vpiName:divider
|vpiIODecl:
\_io_decl: (remainder)
|vpiName:remainder
|vpiDirection:2
|vpiExpr:
\_logic_net: (remainder), line:247
|vpiName:remainder
|vpiNetType:36
|vpiRange:
\_range: , line:247
|vpiLeftRange:
\_constant: , line:247
|vpiDecompile:31
|INT:31
|vpiRightRange:
\_constant: , line:247
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (quotient)
|vpiName:quotient
|vpiDirection:2
|vpiExpr:
\_logic_net: (quotient), line:248
|vpiName:quotient
|vpiNetType:36
|vpiRange:
\_range: , line:248
|vpiLeftRange:
\_constant: , line:248
|vpiDecompile:31
|INT:31
|vpiRightRange:
\_constant: , line:248
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (done)
|vpiName:done
|vpiDirection:2
|vpiExpr:
\_logic_net: (done), line:249
|vpiName:done
|vpiNetType:36
|vpiIODecl:
\_io_decl: (divisor_is_zero)
|vpiName:divisor_is_zero
|vpiDirection:2
|vpiExpr:
\_logic_net: (divisor_is_zero), line:250
|vpiName:divisor_is_zero
|vpiNetType:36
|vpiIODecl:
\_io_decl: (dividend)
|vpiName:dividend
|vpiDirection:1
|vpiExpr:
\_logic_net: (dividend), line:245
|vpiName:dividend
|vpiNetType:36
|vpiRange:
\_range: , line:245
|vpiLeftRange:
\_constant: , line:245
|vpiDecompile:31
|INT:31
|vpiRightRange:
\_constant: , line:245
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (divisor)
|vpiName:divisor
|vpiDirection:1
|vpiExpr:
\_logic_net: (divisor), line:246
|vpiName:divisor
|vpiNetType:36
|vpiRange:
\_range: , line:246
|vpiLeftRange:
\_constant: , line:246
|vpiDecompile:31
|INT:31
|vpiRightRange:
\_constant: , line:246
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (start)
|vpiName:start
|vpiDirection:1
|vpiExpr:
\_logic_net: (start), line:244
|vpiName:start
|vpiNetType:36
|vpiInterface:
\_interface: work@unsigned_division_interface (div), file:third_party/cores/taiga/core/div_algorithms/div_algorithm.sv, line:38
|vpiDefName:work@unsigned_division_interface
|vpiName:div
|vpiModport:
\_modport: (divider)
|vpiModport:
\_modport: (requester)
|vpiName:requester
|vpiIODecl:
\_io_decl: (remainder)
|vpiName:remainder
|vpiDirection:1
|vpiExpr:
\_logic_net: (remainder), line:247
|vpiIODecl:
\_io_decl: (quotient)
|vpiName:quotient
|vpiDirection:1
|vpiExpr:
\_logic_net: (quotient), line:248
|vpiIODecl:
\_io_decl: (done)
|vpiName:done
|vpiDirection:1
|vpiExpr:
\_logic_net: (done), line:249
|vpiIODecl:
\_io_decl: (divisor_is_zero)
|vpiName:divisor_is_zero
|vpiDirection:1
|vpiExpr:
\_logic_net: (divisor_is_zero), line:250
|vpiIODecl:
\_io_decl: (dividend)
|vpiName:dividend
|vpiDirection:2
|vpiExpr:
\_logic_net: (dividend), line:245
|vpiIODecl:
\_io_decl: (divisor)
|vpiName:divisor
|vpiDirection:2
|vpiExpr:
\_logic_net: (divisor), line:246
|vpiIODecl:
\_io_decl: (start)
|vpiName:start
|vpiDirection:2
|vpiExpr:
\_logic_net: (start), line:244
|vpiInterface:
\_interface: work@unsigned_division_interface (div), file:third_party/cores/taiga/core/div_algorithms/div_algorithm.sv, line:38
|vpiNet:
\_logic_net: (clk), line:27, parent:div_block
|vpiNet:
\_logic_net: (rst), line:28, parent:div_block
|vpiNet:
\_logic_net: (terminate), line:32, parent:div_block
|vpiName:terminate
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.terminate
|vpiNetType:36
|vpiNet:
\_logic_net: (new_PR), line:34, parent:div_block
|vpiName:new_PR
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.new_PR
|vpiNetType:36
|vpiRange:
\_range: , line:34
|vpiLeftRange:
\_ref_obj: (div.DATA_WIDTH), line:34
|vpiName:div.DATA_WIDTH
|vpiRightRange:
\_constant: , line:34
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (PR), line:35, parent:div_block
|vpiName:PR
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.PR
|vpiNetType:36
|vpiRange:
\_range: , line:35
|vpiLeftRange:
\_ref_obj: (div.DATA_WIDTH), line:35
|vpiName:div.DATA_WIDTH
|vpiRightRange:
\_constant: , line:35
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (shift_count), line:37, parent:div_block
|vpiName:shift_count
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.shift_count
|vpiNetType:36
|vpiRange:
\_range: , line:37
|vpiLeftRange:
\_operation: , line:37
|vpiOpType:11
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:37
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:37
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:37
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (negative_sub_rst), line:39, parent:div_block
|vpiName:negative_sub_rst
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.negative_sub_rst
|vpiNetType:36
|vpiNet:
\_logic_net: (AR_r), line:40, parent:div_block
|vpiName:AR_r
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.AR_r
|vpiNetType:36
|vpiRange:
\_range: , line:40
|vpiLeftRange:
\_operation: , line:40
|vpiOpType:11
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:40
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:40
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:40
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (Q_temp), line:41, parent:div_block
|vpiName:Q_temp
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.Q_temp
|vpiNetType:36
|vpiRange:
\_range: , line:41
|vpiLeftRange:
\_operation: , line:41
|vpiOpType:11
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:41
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:41
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:41
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (shift_num_R), line:42, parent:div_block
|vpiName:shift_num_R
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.shift_num_R
|vpiNetType:36
|vpiRange:
\_range: , line:42
|vpiLeftRange:
\_constant: , line:42
|vpiConstType:7
|vpiDecompile:5
|vpiSize:32
|INT:5
|vpiRightRange:
\_constant: , line:42
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (shift_num_Q), line:43, parent:div_block
|vpiName:shift_num_Q
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.shift_num_Q
|vpiNetType:36
|vpiRange:
\_range: , line:43
|vpiLeftRange:
\_constant: , line:43
|vpiConstType:7
|vpiDecompile:5
|vpiSize:32
|INT:5
|vpiRightRange:
\_constant: , line:43
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (combined), line:44, parent:div_block
|vpiName:combined
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.combined
|vpiNetType:36
|vpiRange:
\_range: , line:44
|vpiLeftRange:
\_operation: , line:44
|vpiOpType:25
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:44
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:44
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiRightRange:
\_constant: , line:44
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (combined_r), line:45, parent:div_block
|vpiName:combined_r
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.combined_r
|vpiNetType:36
|vpiRange:
\_range: , line:45
|vpiLeftRange:
\_operation: , line:45
|vpiOpType:25
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:45
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:45
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiRightRange:
\_constant: , line:45
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (terminate_early), line:46, parent:div_block
|vpiName:terminate_early
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.terminate_early
|vpiNetType:36
|vpiNet:
\_logic_net: (terminate_early_r), line:47, parent:div_block
|vpiName:terminate_early_r
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.terminate_early_r
|vpiNetType:36
|vpiNet:
\_logic_net: (div), line:29, parent:div_block
|vpiName:div
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.div
|vpiInstance:
\_module: work@div_algorithm (div_core), file:third_party/cores/taiga/core/div_unit_core_wrapper.sv, line:44, parent:work@div_unit_core_wrapper
|vpiModule:
\_module: work@div_radix4 (div_block), file:third_party/cores/taiga/core/div_algorithms/div_algorithm.sv, line:39, parent:div_core
|vpiDefName:work@div_radix4
|vpiName:div_block
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block
|vpiPort:
\_port: (clk), line:27, parent:div_block
|vpiName:clk
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (clk), line:39
|vpiName:clk
|vpiActual:
\_logic_net: (clk), line:29, parent:div_core
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (clk), line:27, parent:div_block
|vpiName:clk
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.clk
|vpiNetType:36
|vpiPort:
\_port: (rst), line:28, parent:div_block
|vpiName:rst
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (rst), line:39
|vpiName:rst
|vpiActual:
\_logic_net: (rst), line:30, parent:div_core
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (rst), line:28, parent:div_block
|vpiName:rst
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.rst
|vpiNetType:36
|vpiPort:
\_port: (div), line:29, parent:div_block
|vpiName:div
|vpiDirection:5
|vpiHighConn:
\_ref_obj: (div), line:39
|vpiName:div
|vpiActual:
\_interface: work@unsigned_division_interface (div), file:third_party/cores/taiga/core/div_unit_core_wrapper.sv, line:44
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_modport: (divider)
|vpiName:divider
|vpiIODecl:
\_io_decl: (remainder)
|vpiName:remainder
|vpiDirection:2
|vpiExpr:
\_logic_net: (remainder), line:247
|vpiName:remainder
|vpiNetType:36
|vpiRange:
\_range: , line:247
|vpiLeftRange:
\_constant: , line:247
|vpiDecompile:31
|INT:31
|vpiRightRange:
\_constant: , line:247
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (quotient)
|vpiName:quotient
|vpiDirection:2
|vpiExpr:
\_logic_net: (quotient), line:248
|vpiName:quotient
|vpiNetType:36
|vpiRange:
\_range: , line:248
|vpiLeftRange:
\_constant: , line:248
|vpiDecompile:31
|INT:31
|vpiRightRange:
\_constant: , line:248
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (done)
|vpiName:done
|vpiDirection:2
|vpiExpr:
\_logic_net: (done), line:249
|vpiName:done
|vpiNetType:36
|vpiIODecl:
\_io_decl: (divisor_is_zero)
|vpiName:divisor_is_zero
|vpiDirection:2
|vpiExpr:
\_logic_net: (divisor_is_zero), line:250
|vpiName:divisor_is_zero
|vpiNetType:36
|vpiIODecl:
\_io_decl: (dividend)
|vpiName:dividend
|vpiDirection:1
|vpiExpr:
\_logic_net: (dividend), line:245
|vpiName:dividend
|vpiNetType:36
|vpiRange:
\_range: , line:245
|vpiLeftRange:
\_constant: , line:245
|vpiDecompile:31
|INT:31
|vpiRightRange:
\_constant: , line:245
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (divisor)
|vpiName:divisor
|vpiDirection:1
|vpiExpr:
\_logic_net: (divisor), line:246
|vpiName:divisor
|vpiNetType:36
|vpiRange:
\_range: , line:246
|vpiLeftRange:
\_constant: , line:246
|vpiDecompile:31
|INT:31
|vpiRightRange:
\_constant: , line:246
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (start)
|vpiName:start
|vpiDirection:1
|vpiExpr:
\_logic_net: (start), line:244
|vpiName:start
|vpiNetType:36
|vpiInterface:
\_interface: work@unsigned_division_interface (div), file:third_party/cores/taiga/core/div_algorithms/div_algorithm.sv, line:39
|vpiDefName:work@unsigned_division_interface
|vpiName:div
|vpiModport:
\_modport: (divider)
|vpiModport:
\_modport: (requester)
|vpiName:requester
|vpiIODecl:
\_io_decl: (remainder)
|vpiName:remainder
|vpiDirection:1
|vpiExpr:
\_logic_net: (remainder), line:247
|vpiIODecl:
\_io_decl: (quotient)
|vpiName:quotient
|vpiDirection:1
|vpiExpr:
\_logic_net: (quotient), line:248
|vpiIODecl:
\_io_decl: (done)
|vpiName:done
|vpiDirection:1
|vpiExpr:
\_logic_net: (done), line:249
|vpiIODecl:
\_io_decl: (divisor_is_zero)
|vpiName:divisor_is_zero
|vpiDirection:1
|vpiExpr:
\_logic_net: (divisor_is_zero), line:250
|vpiIODecl:
\_io_decl: (dividend)
|vpiName:dividend
|vpiDirection:2
|vpiExpr:
\_logic_net: (dividend), line:245
|vpiIODecl:
\_io_decl: (divisor)
|vpiName:divisor
|vpiDirection:2
|vpiExpr:
\_logic_net: (divisor), line:246
|vpiIODecl:
\_io_decl: (start)
|vpiName:start
|vpiDirection:2
|vpiExpr:
\_logic_net: (start), line:244
|vpiInterface:
\_interface: work@unsigned_division_interface (div), file:third_party/cores/taiga/core/div_algorithms/div_algorithm.sv, line:39
|vpiNet:
\_logic_net: (clk), line:27, parent:div_block
|vpiNet:
\_logic_net: (rst), line:28, parent:div_block
|vpiNet:
\_logic_net: (terminate), line:32, parent:div_block
|vpiName:terminate
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.terminate
|vpiNetType:36
|vpiNet:
\_logic_net: (shift_count), line:33, parent:div_block
|vpiName:shift_count
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.shift_count
|vpiNetType:36
|vpiRange:
\_range: , line:33
|vpiLeftRange:
\_operation: , line:33
|vpiOpType:11
|vpiOperand:
\_operation: , line:33
|vpiOpType:12
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:33
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:33
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiOperand:
\_constant: , line:33
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:33
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (PR), line:35, parent:div_block
|vpiName:PR
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.PR
|vpiNetType:36
|vpiRange:
\_range: , line:35
|vpiLeftRange:
\_operation: , line:35
|vpiOpType:24
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:35
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:35
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:35
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (new_PR_sign), line:36, parent:div_block
|vpiName:new_PR_sign
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.new_PR_sign
|vpiNetType:36
|vpiRange:
\_range: , line:36
|vpiLeftRange:
\_constant: , line:36
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiRightRange:
\_constant: , line:36
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (new_PR_1), line:37, parent:div_block
|vpiName:new_PR_1
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.new_PR_1
|vpiNetType:36
|vpiRange:
\_range: , line:37
|vpiLeftRange:
\_operation: , line:37
|vpiOpType:24
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:37
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:37
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiRightRange:
\_constant: , line:37
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (new_PR_2), line:38, parent:div_block
|vpiName:new_PR_2
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.new_PR_2
|vpiNetType:36
|vpiRange:
\_range: , line:38
|vpiLeftRange:
\_operation: , line:38
|vpiOpType:24
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:38
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:38
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiRightRange:
\_constant: , line:38
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (new_PR_3), line:39, parent:div_block
|vpiName:new_PR_3
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.new_PR_3
|vpiNetType:36
|vpiRange:
\_range: , line:39
|vpiLeftRange:
\_operation: , line:39
|vpiOpType:24
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:39
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:39
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiRightRange:
\_constant: , line:39
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (B_1), line:40, parent:div_block
|vpiName:B_1
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.B_1
|vpiNetType:36
|vpiRange:
\_range: , line:40
|vpiLeftRange:
\_operation: , line:40
|vpiOpType:24
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:40
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:40
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:40
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (B_2), line:41, parent:div_block
|vpiName:B_2
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.B_2
|vpiNetType:36
|vpiRange:
\_range: , line:41
|vpiLeftRange:
\_operation: , line:41
|vpiOpType:24
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:41
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:41
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:41
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (B_3), line:42, parent:div_block
|vpiName:B_3
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.B_3
|vpiNetType:36
|vpiRange:
\_range: , line:42
|vpiLeftRange:
\_operation: , line:42
|vpiOpType:24
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:42
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:42
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:42
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (div), line:29, parent:div_block
|vpiName:div
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.div
|vpiInstance:
\_module: work@div_algorithm (div_core), file:third_party/cores/taiga/core/div_unit_core_wrapper.sv, line:44, parent:work@div_unit_core_wrapper
|vpiModule:
\_module: work@div_radix4_ET (div_block), file:third_party/cores/taiga/core/div_algorithms/div_algorithm.sv, line:40, parent:div_core
|vpiDefName:work@div_radix4_ET
|vpiName:div_block
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block
|vpiPort:
\_port: (clk), line:27, parent:div_block
|vpiName:clk
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (clk), line:40
|vpiName:clk
|vpiActual:
\_logic_net: (clk), line:29, parent:div_core
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (clk), line:27, parent:div_block
|vpiName:clk
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.clk
|vpiNetType:36
|vpiPort:
\_port: (rst), line:28, parent:div_block
|vpiName:rst
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (rst), line:40
|vpiName:rst
|vpiActual:
\_logic_net: (rst), line:30, parent:div_core
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (rst), line:28, parent:div_block
|vpiName:rst
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.rst
|vpiNetType:36
|vpiPort:
\_port: (div), line:29, parent:div_block
|vpiName:div
|vpiDirection:5
|vpiHighConn:
\_ref_obj: (div), line:40
|vpiName:div
|vpiActual:
\_interface: work@unsigned_division_interface (div), file:third_party/cores/taiga/core/div_unit_core_wrapper.sv, line:44
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_modport: (divider)
|vpiName:divider
|vpiIODecl:
\_io_decl: (remainder)
|vpiName:remainder
|vpiDirection:2
|vpiExpr:
\_logic_net: (remainder), line:247
|vpiName:remainder
|vpiNetType:36
|vpiRange:
\_range: , line:247
|vpiLeftRange:
\_constant: , line:247
|vpiDecompile:31
|INT:31
|vpiRightRange:
\_constant: , line:247
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (quotient)
|vpiName:quotient
|vpiDirection:2
|vpiExpr:
\_logic_net: (quotient), line:248
|vpiName:quotient
|vpiNetType:36
|vpiRange:
\_range: , line:248
|vpiLeftRange:
\_constant: , line:248
|vpiDecompile:31
|INT:31
|vpiRightRange:
\_constant: , line:248
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (done)
|vpiName:done
|vpiDirection:2
|vpiExpr:
\_logic_net: (done), line:249
|vpiName:done
|vpiNetType:36
|vpiIODecl:
\_io_decl: (divisor_is_zero)
|vpiName:divisor_is_zero
|vpiDirection:2
|vpiExpr:
\_logic_net: (divisor_is_zero), line:250
|vpiName:divisor_is_zero
|vpiNetType:36
|vpiIODecl:
\_io_decl: (dividend)
|vpiName:dividend
|vpiDirection:1
|vpiExpr:
\_logic_net: (dividend), line:245
|vpiName:dividend
|vpiNetType:36
|vpiRange:
\_range: , line:245
|vpiLeftRange:
\_constant: , line:245
|vpiDecompile:31
|INT:31
|vpiRightRange:
\_constant: , line:245
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (divisor)
|vpiName:divisor
|vpiDirection:1
|vpiExpr:
\_logic_net: (divisor), line:246
|vpiName:divisor
|vpiNetType:36
|vpiRange:
\_range: , line:246
|vpiLeftRange:
\_constant: , line:246
|vpiDecompile:31
|INT:31
|vpiRightRange:
\_constant: , line:246
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (start)
|vpiName:start
|vpiDirection:1
|vpiExpr:
\_logic_net: (start), line:244
|vpiName:start
|vpiNetType:36
|vpiInterface:
\_interface: work@unsigned_division_interface (div), file:third_party/cores/taiga/core/div_algorithms/div_algorithm.sv, line:40
|vpiDefName:work@unsigned_division_interface
|vpiName:div
|vpiModport:
\_modport: (divider)
|vpiModport:
\_modport: (requester)
|vpiName:requester
|vpiIODecl:
\_io_decl: (remainder)
|vpiName:remainder
|vpiDirection:1
|vpiExpr:
\_logic_net: (remainder), line:247
|vpiIODecl:
\_io_decl: (quotient)
|vpiName:quotient
|vpiDirection:1
|vpiExpr:
\_logic_net: (quotient), line:248
|vpiIODecl:
\_io_decl: (done)
|vpiName:done
|vpiDirection:1
|vpiExpr:
\_logic_net: (done), line:249
|vpiIODecl:
\_io_decl: (divisor_is_zero)
|vpiName:divisor_is_zero
|vpiDirection:1
|vpiExpr:
\_logic_net: (divisor_is_zero), line:250
|vpiIODecl:
\_io_decl: (dividend)
|vpiName:dividend
|vpiDirection:2
|vpiExpr:
\_logic_net: (dividend), line:245
|vpiIODecl:
\_io_decl: (divisor)
|vpiName:divisor
|vpiDirection:2
|vpiExpr:
\_logic_net: (divisor), line:246
|vpiIODecl:
\_io_decl: (start)
|vpiName:start
|vpiDirection:2
|vpiExpr:
\_logic_net: (start), line:244
|vpiInterface:
\_interface: work@unsigned_division_interface (div), file:third_party/cores/taiga/core/div_algorithms/div_algorithm.sv, line:40
|vpiNet:
\_logic_net: (clk), line:27, parent:div_block
|vpiNet:
\_logic_net: (rst), line:28, parent:div_block
|vpiNet:
\_logic_net: (terminate), line:32, parent:div_block
|vpiName:terminate
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.terminate
|vpiNetType:36
|vpiNet:
\_logic_net: (terminate_early), line:33, parent:div_block
|vpiName:terminate_early
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.terminate_early
|vpiNetType:36
|vpiNet:
\_logic_net: (shift_count), line:34, parent:div_block
|vpiName:shift_count
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.shift_count
|vpiNetType:36
|vpiRange:
\_range: , line:34
|vpiLeftRange:
\_operation: , line:34
|vpiOpType:11
|vpiOperand:
\_operation: , line:34
|vpiOpType:12
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:34
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:34
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiOperand:
\_constant: , line:34
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:34
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (PR), line:36, parent:div_block
|vpiName:PR
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.PR
|vpiNetType:36
|vpiRange:
\_range: , line:36
|vpiLeftRange:
\_operation: , line:36
|vpiOpType:24
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:36
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:36
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:36
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (new_PR_sign), line:37, parent:div_block
|vpiName:new_PR_sign
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.new_PR_sign
|vpiNetType:36
|vpiRange:
\_range: , line:37
|vpiLeftRange:
\_constant: , line:37
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiRightRange:
\_constant: , line:37
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (new_PR_1), line:38, parent:div_block
|vpiName:new_PR_1
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.new_PR_1
|vpiNetType:36
|vpiRange:
\_range: , line:38
|vpiLeftRange:
\_operation: , line:38
|vpiOpType:24
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:38
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:38
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiRightRange:
\_constant: , line:38
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (new_PR_2), line:39, parent:div_block
|vpiName:new_PR_2
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.new_PR_2
|vpiNetType:36
|vpiRange:
\_range: , line:39
|vpiLeftRange:
\_operation: , line:39
|vpiOpType:24
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:39
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:39
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiRightRange:
\_constant: , line:39
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (new_PR_3), line:40, parent:div_block
|vpiName:new_PR_3
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.new_PR_3
|vpiNetType:36
|vpiRange:
\_range: , line:40
|vpiLeftRange:
\_operation: , line:40
|vpiOpType:24
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:40
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:40
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiRightRange:
\_constant: , line:40
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (B_1), line:41, parent:div_block
|vpiName:B_1
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.B_1
|vpiNetType:36
|vpiRange:
\_range: , line:41
|vpiLeftRange:
\_operation: , line:41
|vpiOpType:24
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:41
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:41
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:41
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (B_2), line:42, parent:div_block
|vpiName:B_2
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.B_2
|vpiNetType:36
|vpiRange:
\_range: , line:42
|vpiLeftRange:
\_operation: , line:42
|vpiOpType:24
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:42
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:42
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:42
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (B_3), line:43, parent:div_block
|vpiName:B_3
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.B_3
|vpiNetType:36
|vpiRange:
\_range: , line:43
|vpiLeftRange:
\_operation: , line:43
|vpiOpType:24
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:43
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:43
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:43
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (div), line:29, parent:div_block
|vpiName:div
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.div
|vpiInstance:
\_module: work@div_algorithm (div_core), file:third_party/cores/taiga/core/div_unit_core_wrapper.sv, line:44, parent:work@div_unit_core_wrapper
|vpiModule:
\_module: work@div_radix4_ET_full (div_block), file:third_party/cores/taiga/core/div_algorithms/div_algorithm.sv, line:41, parent:div_core
|vpiDefName:work@div_radix4_ET_full
|vpiName:div_block
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block
|vpiPort:
\_port: (clk), line:27, parent:div_block
|vpiName:clk
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (clk), line:41
|vpiName:clk
|vpiActual:
\_logic_net: (clk), line:29, parent:div_core
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (clk), line:27, parent:div_block
|vpiName:clk
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.clk
|vpiNetType:36
|vpiPort:
\_port: (rst), line:28, parent:div_block
|vpiName:rst
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (rst), line:41
|vpiName:rst
|vpiActual:
\_logic_net: (rst), line:30, parent:div_core
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (rst), line:28, parent:div_block
|vpiName:rst
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.rst
|vpiNetType:36
|vpiPort:
\_port: (div), line:29, parent:div_block
|vpiName:div
|vpiDirection:5
|vpiHighConn:
\_ref_obj: (div), line:41
|vpiName:div
|vpiActual:
\_interface: work@unsigned_division_interface (div), file:third_party/cores/taiga/core/div_unit_core_wrapper.sv, line:44
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_modport: (divider)
|vpiName:divider
|vpiIODecl:
\_io_decl: (remainder)
|vpiName:remainder
|vpiDirection:2
|vpiExpr:
\_logic_net: (remainder), line:247
|vpiName:remainder
|vpiNetType:36
|vpiRange:
\_range: , line:247
|vpiLeftRange:
\_constant: , line:247
|vpiDecompile:31
|INT:31
|vpiRightRange:
\_constant: , line:247
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (quotient)
|vpiName:quotient
|vpiDirection:2
|vpiExpr:
\_logic_net: (quotient), line:248
|vpiName:quotient
|vpiNetType:36
|vpiRange:
\_range: , line:248
|vpiLeftRange:
\_constant: , line:248
|vpiDecompile:31
|INT:31
|vpiRightRange:
\_constant: , line:248
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (done)
|vpiName:done
|vpiDirection:2
|vpiExpr:
\_logic_net: (done), line:249
|vpiName:done
|vpiNetType:36
|vpiIODecl:
\_io_decl: (divisor_is_zero)
|vpiName:divisor_is_zero
|vpiDirection:2
|vpiExpr:
\_logic_net: (divisor_is_zero), line:250
|vpiName:divisor_is_zero
|vpiNetType:36
|vpiIODecl:
\_io_decl: (dividend)
|vpiName:dividend
|vpiDirection:1
|vpiExpr:
\_logic_net: (dividend), line:245
|vpiName:dividend
|vpiNetType:36
|vpiRange:
\_range: , line:245
|vpiLeftRange:
\_constant: , line:245
|vpiDecompile:31
|INT:31
|vpiRightRange:
\_constant: , line:245
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (divisor)
|vpiName:divisor
|vpiDirection:1
|vpiExpr:
\_logic_net: (divisor), line:246
|vpiName:divisor
|vpiNetType:36
|vpiRange:
\_range: , line:246
|vpiLeftRange:
\_constant: , line:246
|vpiDecompile:31
|INT:31
|vpiRightRange:
\_constant: , line:246
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (start)
|vpiName:start
|vpiDirection:1
|vpiExpr:
\_logic_net: (start), line:244
|vpiName:start
|vpiNetType:36
|vpiInterface:
\_interface: work@unsigned_division_interface (div), file:third_party/cores/taiga/core/div_algorithms/div_algorithm.sv, line:41
|vpiDefName:work@unsigned_division_interface
|vpiName:div
|vpiModport:
\_modport: (divider)
|vpiModport:
\_modport: (requester)
|vpiName:requester
|vpiIODecl:
\_io_decl: (remainder)
|vpiName:remainder
|vpiDirection:1
|vpiExpr:
\_logic_net: (remainder), line:247
|vpiIODecl:
\_io_decl: (quotient)
|vpiName:quotient
|vpiDirection:1
|vpiExpr:
\_logic_net: (quotient), line:248
|vpiIODecl:
\_io_decl: (done)
|vpiName:done
|vpiDirection:1
|vpiExpr:
\_logic_net: (done), line:249
|vpiIODecl:
\_io_decl: (divisor_is_zero)
|vpiName:divisor_is_zero
|vpiDirection:1
|vpiExpr:
\_logic_net: (divisor_is_zero), line:250
|vpiIODecl:
\_io_decl: (dividend)
|vpiName:dividend
|vpiDirection:2
|vpiExpr:
\_logic_net: (dividend), line:245
|vpiIODecl:
\_io_decl: (divisor)
|vpiName:divisor
|vpiDirection:2
|vpiExpr:
\_logic_net: (divisor), line:246
|vpiIODecl:
\_io_decl: (start)
|vpiName:start
|vpiDirection:2
|vpiExpr:
\_logic_net: (start), line:244
|vpiInterface:
\_interface: work@unsigned_division_interface (div), file:third_party/cores/taiga/core/div_algorithms/div_algorithm.sv, line:41
|vpiNet:
\_logic_net: (clk), line:27, parent:div_block
|vpiNet:
\_logic_net: (rst), line:28, parent:div_block
|vpiNet:
\_logic_net: (terminate), line:32, parent:div_block
|vpiName:terminate
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.terminate
|vpiNetType:36
|vpiNet:
\_logic_net: (shift_count), line:33, parent:div_block
|vpiName:shift_count
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.shift_count
|vpiNetType:36
|vpiRange:
\_range: , line:33
|vpiLeftRange:
\_operation: , line:33
|vpiOpType:11
|vpiOperand:
\_operation: , line:33
|vpiOpType:12
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:33
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:33
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiOperand:
\_constant: , line:33
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:33
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (PR), line:35, parent:div_block
|vpiName:PR
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.PR
|vpiNetType:36
|vpiRange:
\_range: , line:35
|vpiLeftRange:
\_operation: , line:35
|vpiOpType:24
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:35
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:35
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:35
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (new_PR_sign), line:36, parent:div_block
|vpiName:new_PR_sign
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.new_PR_sign
|vpiNetType:36
|vpiRange:
\_range: , line:36
|vpiLeftRange:
\_constant: , line:36
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiRightRange:
\_constant: , line:36
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (new_PR_1), line:37, parent:div_block
|vpiName:new_PR_1
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.new_PR_1
|vpiNetType:36
|vpiRange:
\_range: , line:37
|vpiLeftRange:
\_operation: , line:37
|vpiOpType:24
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:37
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:37
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiRightRange:
\_constant: , line:37
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (new_PR_2), line:38, parent:div_block
|vpiName:new_PR_2
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.new_PR_2
|vpiNetType:36
|vpiRange:
\_range: , line:38
|vpiLeftRange:
\_operation: , line:38
|vpiOpType:24
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:38
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:38
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiRightRange:
\_constant: , line:38
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (new_PR_3), line:39, parent:div_block
|vpiName:new_PR_3
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.new_PR_3
|vpiNetType:36
|vpiRange:
\_range: , line:39
|vpiLeftRange:
\_operation: , line:39
|vpiOpType:24
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:39
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:39
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiRightRange:
\_constant: , line:39
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (B_1), line:40, parent:div_block
|vpiName:B_1
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.B_1
|vpiNetType:36
|vpiRange:
\_range: , line:40
|vpiLeftRange:
\_operation: , line:40
|vpiOpType:24
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:40
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:40
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:40
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (B_2), line:41, parent:div_block
|vpiName:B_2
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.B_2
|vpiNetType:36
|vpiRange:
\_range: , line:41
|vpiLeftRange:
\_operation: , line:41
|vpiOpType:24
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:41
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:41
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:41
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (B_3), line:42, parent:div_block
|vpiName:B_3
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.B_3
|vpiNetType:36
|vpiRange:
\_range: , line:42
|vpiLeftRange:
\_operation: , line:42
|vpiOpType:24
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:42
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:42
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:42
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (B_r), line:44, parent:div_block
|vpiName:B_r
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.B_r
|vpiNetType:36
|vpiRange:
\_range: , line:44
|vpiLeftRange:
\_operation: , line:44
|vpiOpType:11
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:44
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:44
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:44
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (AR_r), line:45, parent:div_block
|vpiName:AR_r
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.AR_r
|vpiNetType:36
|vpiRange:
\_range: , line:45
|vpiLeftRange:
\_operation: , line:45
|vpiOpType:11
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:45
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:45
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:45
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (Q_temp), line:46, parent:div_block
|vpiName:Q_temp
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.Q_temp
|vpiNetType:36
|vpiRange:
\_range: , line:46
|vpiLeftRange:
\_operation: , line:46
|vpiOpType:11
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:46
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:46
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:46
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (shift_num_R), line:47, parent:div_block
|vpiName:shift_num_R
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.shift_num_R
|vpiNetType:36
|vpiRange:
\_range: , line:47
|vpiLeftRange:
\_constant: , line:47
|vpiConstType:7
|vpiDecompile:5
|vpiSize:32
|INT:5
|vpiRightRange:
\_constant: , line:47
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (shift_num_Q), line:48, parent:div_block
|vpiName:shift_num_Q
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.shift_num_Q
|vpiNetType:36
|vpiRange:
\_range: , line:48
|vpiLeftRange:
\_constant: , line:48
|vpiConstType:7
|vpiDecompile:5
|vpiSize:32
|INT:5
|vpiRightRange:
\_constant: , line:48
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (combined), line:49, parent:div_block
|vpiName:combined
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.combined
|vpiNetType:36
|vpiRange:
\_range: , line:49
|vpiLeftRange:
\_operation: , line:49
|vpiOpType:25
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:49
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:49
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiRightRange:
\_constant: , line:49
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (terminate_early), line:50, parent:div_block
|vpiName:terminate_early
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.terminate_early
|vpiNetType:36
|vpiNet:
\_logic_net: (div), line:29, parent:div_block
|vpiName:div
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.div
|vpiInstance:
\_module: work@div_algorithm (div_core), file:third_party/cores/taiga/core/div_unit_core_wrapper.sv, line:44, parent:work@div_unit_core_wrapper
|vpiModule:
\_module: work@div_radix8 (div_block), file:third_party/cores/taiga/core/div_algorithms/div_algorithm.sv, line:42, parent:div_core
|vpiDefName:work@div_radix8
|vpiName:div_block
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block
|vpiPort:
\_port: (clk), line:27, parent:div_block
|vpiName:clk
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (clk), line:42
|vpiName:clk
|vpiActual:
\_logic_net: (clk), line:29, parent:div_core
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (clk), line:27, parent:div_block
|vpiName:clk
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.clk
|vpiNetType:36
|vpiPort:
\_port: (rst), line:28, parent:div_block
|vpiName:rst
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (rst), line:42
|vpiName:rst
|vpiActual:
\_logic_net: (rst), line:30, parent:div_core
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (rst), line:28, parent:div_block
|vpiName:rst
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.rst
|vpiNetType:36
|vpiPort:
\_port: (div), line:29, parent:div_block
|vpiName:div
|vpiDirection:5
|vpiHighConn:
\_ref_obj: (div), line:42
|vpiName:div
|vpiActual:
\_interface: work@unsigned_division_interface (div), file:third_party/cores/taiga/core/div_unit_core_wrapper.sv, line:44
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_modport: (divider)
|vpiName:divider
|vpiIODecl:
\_io_decl: (remainder)
|vpiName:remainder
|vpiDirection:2
|vpiExpr:
\_logic_net: (remainder), line:247
|vpiName:remainder
|vpiNetType:36
|vpiRange:
\_range: , line:247
|vpiLeftRange:
\_constant: , line:247
|vpiDecompile:31
|INT:31
|vpiRightRange:
\_constant: , line:247
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (quotient)
|vpiName:quotient
|vpiDirection:2
|vpiExpr:
\_logic_net: (quotient), line:248
|vpiName:quotient
|vpiNetType:36
|vpiRange:
\_range: , line:248
|vpiLeftRange:
\_constant: , line:248
|vpiDecompile:31
|INT:31
|vpiRightRange:
\_constant: , line:248
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (done)
|vpiName:done
|vpiDirection:2
|vpiExpr:
\_logic_net: (done), line:249
|vpiName:done
|vpiNetType:36
|vpiIODecl:
\_io_decl: (divisor_is_zero)
|vpiName:divisor_is_zero
|vpiDirection:2
|vpiExpr:
\_logic_net: (divisor_is_zero), line:250
|vpiName:divisor_is_zero
|vpiNetType:36
|vpiIODecl:
\_io_decl: (dividend)
|vpiName:dividend
|vpiDirection:1
|vpiExpr:
\_logic_net: (dividend), line:245
|vpiName:dividend
|vpiNetType:36
|vpiRange:
\_range: , line:245
|vpiLeftRange:
\_constant: , line:245
|vpiDecompile:31
|INT:31
|vpiRightRange:
\_constant: , line:245
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (divisor)
|vpiName:divisor
|vpiDirection:1
|vpiExpr:
\_logic_net: (divisor), line:246
|vpiName:divisor
|vpiNetType:36
|vpiRange:
\_range: , line:246
|vpiLeftRange:
\_constant: , line:246
|vpiDecompile:31
|INT:31
|vpiRightRange:
\_constant: , line:246
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (start)
|vpiName:start
|vpiDirection:1
|vpiExpr:
\_logic_net: (start), line:244
|vpiName:start
|vpiNetType:36
|vpiInterface:
\_interface: work@unsigned_division_interface (div), file:third_party/cores/taiga/core/div_algorithms/div_algorithm.sv, line:42
|vpiDefName:work@unsigned_division_interface
|vpiName:div
|vpiModport:
\_modport: (divider)
|vpiModport:
\_modport: (requester)
|vpiName:requester
|vpiIODecl:
\_io_decl: (remainder)
|vpiName:remainder
|vpiDirection:1
|vpiExpr:
\_logic_net: (remainder), line:247
|vpiIODecl:
\_io_decl: (quotient)
|vpiName:quotient
|vpiDirection:1
|vpiExpr:
\_logic_net: (quotient), line:248
|vpiIODecl:
\_io_decl: (done)
|vpiName:done
|vpiDirection:1
|vpiExpr:
\_logic_net: (done), line:249
|vpiIODecl:
\_io_decl: (divisor_is_zero)
|vpiName:divisor_is_zero
|vpiDirection:1
|vpiExpr:
\_logic_net: (divisor_is_zero), line:250
|vpiIODecl:
\_io_decl: (dividend)
|vpiName:dividend
|vpiDirection:2
|vpiExpr:
\_logic_net: (dividend), line:245
|vpiIODecl:
\_io_decl: (divisor)
|vpiName:divisor
|vpiDirection:2
|vpiExpr:
\_logic_net: (divisor), line:246
|vpiIODecl:
\_io_decl: (start)
|vpiName:start
|vpiDirection:2
|vpiExpr:
\_logic_net: (start), line:244
|vpiInterface:
\_interface: work@unsigned_division_interface (div), file:third_party/cores/taiga/core/div_algorithms/div_algorithm.sv, line:42
|vpiNet:
\_logic_net: (clk), line:27, parent:div_block
|vpiNet:
\_logic_net: (rst), line:28, parent:div_block
|vpiNet:
\_logic_net: (terminate), line:32, parent:div_block
|vpiName:terminate
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.terminate
|vpiNetType:36
|vpiNet:
\_logic_net: (shift_count), line:33, parent:div_block
|vpiName:shift_count
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.shift_count
|vpiNetType:36
|vpiRange:
\_range: , line:33
|vpiLeftRange:
\_constant: , line:33
|vpiConstType:7
|vpiDecompile:10
|vpiSize:32
|INT:10
|vpiRightRange:
\_constant: , line:33
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (PR), line:35, parent:div_block
|vpiName:PR
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.PR
|vpiNetType:36
|vpiRange:
\_range: , line:35
|vpiLeftRange:
\_operation: , line:35
|vpiOpType:24
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:35
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:35
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiRightRange:
\_constant: , line:35
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (Q_33), line:36, parent:div_block
|vpiName:Q_33
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.Q_33
|vpiNetType:36
|vpiRange:
\_range: , line:36
|vpiLeftRange:
\_ref_obj: (div.DATA_WIDTH), line:36
|vpiName:div.DATA_WIDTH
|vpiRightRange:
\_constant: , line:36
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (new_PR_sign), line:37, parent:div_block
|vpiName:new_PR_sign
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.new_PR_sign
|vpiNetType:36
|vpiRange:
\_range: , line:37
|vpiLeftRange:
\_constant: , line:37
|vpiConstType:7
|vpiDecompile:6
|vpiSize:32
|INT:6
|vpiRightRange:
\_constant: , line:37
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (new_PR_1), line:39, parent:div_block
|vpiName:new_PR_1
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.new_PR_1
|vpiNetType:36
|vpiRange:
\_range: , line:39
|vpiLeftRange:
\_operation: , line:39
|vpiOpType:24
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:39
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:39
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiRightRange:
\_constant: , line:39
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (new_PR_2), line:40, parent:div_block
|vpiName:new_PR_2
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.new_PR_2
|vpiNetType:36
|vpiRange:
\_range: , line:40
|vpiLeftRange:
\_operation: , line:40
|vpiOpType:24
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:40
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:40
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiRightRange:
\_constant: , line:40
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (new_PR_3), line:41, parent:div_block
|vpiName:new_PR_3
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.new_PR_3
|vpiNetType:36
|vpiRange:
\_range: , line:41
|vpiLeftRange:
\_operation: , line:41
|vpiOpType:24
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:41
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:41
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiRightRange:
\_constant: , line:41
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (new_PR_4), line:42, parent:div_block
|vpiName:new_PR_4
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.new_PR_4
|vpiNetType:36
|vpiRange:
\_range: , line:42
|vpiLeftRange:
\_operation: , line:42
|vpiOpType:24
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:42
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:42
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiRightRange:
\_constant: , line:42
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (new_PR_5), line:43, parent:div_block
|vpiName:new_PR_5
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.new_PR_5
|vpiNetType:36
|vpiRange:
\_range: , line:43
|vpiLeftRange:
\_operation: , line:43
|vpiOpType:24
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:43
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:43
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiRightRange:
\_constant: , line:43
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (new_PR_6), line:44, parent:div_block
|vpiName:new_PR_6
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.new_PR_6
|vpiNetType:36
|vpiRange:
\_range: , line:44
|vpiLeftRange:
\_operation: , line:44
|vpiOpType:24
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:44
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:44
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiRightRange:
\_constant: , line:44
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (new_PR_7), line:45, parent:div_block
|vpiName:new_PR_7
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.new_PR_7
|vpiNetType:36
|vpiRange:
\_range: , line:45
|vpiLeftRange:
\_operation: , line:45
|vpiOpType:24
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:45
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:45
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiRightRange:
\_constant: , line:45
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (B_1), line:46, parent:div_block
|vpiName:B_1
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.B_1
|vpiNetType:36
|vpiRange:
\_range: , line:46
|vpiLeftRange:
\_operation: , line:46
|vpiOpType:24
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:46
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:46
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiRightRange:
\_constant: , line:46
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (B_2), line:47, parent:div_block
|vpiName:B_2
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.B_2
|vpiNetType:36
|vpiRange:
\_range: , line:47
|vpiLeftRange:
\_operation: , line:47
|vpiOpType:24
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:47
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:47
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiRightRange:
\_constant: , line:47
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (B_3), line:48, parent:div_block
|vpiName:B_3
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.B_3
|vpiNetType:36
|vpiRange:
\_range: , line:48
|vpiLeftRange:
\_operation: , line:48
|vpiOpType:24
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:48
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:48
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiRightRange:
\_constant: , line:48
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (B_4), line:49, parent:div_block
|vpiName:B_4
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.B_4
|vpiNetType:36
|vpiRange:
\_range: , line:49
|vpiLeftRange:
\_operation: , line:49
|vpiOpType:24
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:49
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:49
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiRightRange:
\_constant: , line:49
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (B_5), line:50, parent:div_block
|vpiName:B_5
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.B_5
|vpiNetType:36
|vpiRange:
\_range: , line:50
|vpiLeftRange:
\_operation: , line:50
|vpiOpType:24
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:50
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:50
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiRightRange:
\_constant: , line:50
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (B_6), line:51, parent:div_block
|vpiName:B_6
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.B_6
|vpiNetType:36
|vpiRange:
\_range: , line:51
|vpiLeftRange:
\_operation: , line:51
|vpiOpType:24
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:51
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:51
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiRightRange:
\_constant: , line:51
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (B_7), line:52, parent:div_block
|vpiName:B_7
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.B_7
|vpiNetType:36
|vpiRange:
\_range: , line:52
|vpiLeftRange:
\_operation: , line:52
|vpiOpType:24
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:52
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:52
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiRightRange:
\_constant: , line:52
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (div), line:29, parent:div_block
|vpiName:div
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.div
|vpiInstance:
\_module: work@div_algorithm (div_core), file:third_party/cores/taiga/core/div_unit_core_wrapper.sv, line:44, parent:work@div_unit_core_wrapper
|vpiModule:
\_module: work@div_radix8_ET (div_block), file:third_party/cores/taiga/core/div_algorithms/div_algorithm.sv, line:43, parent:div_core
|vpiDefName:work@div_radix8_ET
|vpiName:div_block
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block
|vpiPort:
\_port: (clk), line:27, parent:div_block
|vpiName:clk
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (clk), line:43
|vpiName:clk
|vpiActual:
\_logic_net: (clk), line:29, parent:div_core
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (clk), line:27, parent:div_block
|vpiName:clk
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.clk
|vpiNetType:36
|vpiPort:
\_port: (rst), line:28, parent:div_block
|vpiName:rst
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (rst), line:43
|vpiName:rst
|vpiActual:
\_logic_net: (rst), line:30, parent:div_core
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (rst), line:28, parent:div_block
|vpiName:rst
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.rst
|vpiNetType:36
|vpiPort:
\_port: (div), line:29, parent:div_block
|vpiName:div
|vpiDirection:5
|vpiHighConn:
\_ref_obj: (div), line:43
|vpiName:div
|vpiActual:
\_interface: work@unsigned_division_interface (div), file:third_party/cores/taiga/core/div_unit_core_wrapper.sv, line:44
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_modport: (divider)
|vpiName:divider
|vpiIODecl:
\_io_decl: (remainder)
|vpiName:remainder
|vpiDirection:2
|vpiExpr:
\_logic_net: (remainder), line:247
|vpiName:remainder
|vpiNetType:36
|vpiRange:
\_range: , line:247
|vpiLeftRange:
\_constant: , line:247
|vpiDecompile:31
|INT:31
|vpiRightRange:
\_constant: , line:247
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (quotient)
|vpiName:quotient
|vpiDirection:2
|vpiExpr:
\_logic_net: (quotient), line:248
|vpiName:quotient
|vpiNetType:36
|vpiRange:
\_range: , line:248
|vpiLeftRange:
\_constant: , line:248
|vpiDecompile:31
|INT:31
|vpiRightRange:
\_constant: , line:248
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (done)
|vpiName:done
|vpiDirection:2
|vpiExpr:
\_logic_net: (done), line:249
|vpiName:done
|vpiNetType:36
|vpiIODecl:
\_io_decl: (divisor_is_zero)
|vpiName:divisor_is_zero
|vpiDirection:2
|vpiExpr:
\_logic_net: (divisor_is_zero), line:250
|vpiName:divisor_is_zero
|vpiNetType:36
|vpiIODecl:
\_io_decl: (dividend)
|vpiName:dividend
|vpiDirection:1
|vpiExpr:
\_logic_net: (dividend), line:245
|vpiName:dividend
|vpiNetType:36
|vpiRange:
\_range: , line:245
|vpiLeftRange:
\_constant: , line:245
|vpiDecompile:31
|INT:31
|vpiRightRange:
\_constant: , line:245
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (divisor)
|vpiName:divisor
|vpiDirection:1
|vpiExpr:
\_logic_net: (divisor), line:246
|vpiName:divisor
|vpiNetType:36
|vpiRange:
\_range: , line:246
|vpiLeftRange:
\_constant: , line:246
|vpiDecompile:31
|INT:31
|vpiRightRange:
\_constant: , line:246
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (start)
|vpiName:start
|vpiDirection:1
|vpiExpr:
\_logic_net: (start), line:244
|vpiName:start
|vpiNetType:36
|vpiInterface:
\_interface: work@unsigned_division_interface (div), file:third_party/cores/taiga/core/div_algorithms/div_algorithm.sv, line:43
|vpiDefName:work@unsigned_division_interface
|vpiName:div
|vpiModport:
\_modport: (divider)
|vpiModport:
\_modport: (requester)
|vpiName:requester
|vpiIODecl:
\_io_decl: (remainder)
|vpiName:remainder
|vpiDirection:1
|vpiExpr:
\_logic_net: (remainder), line:247
|vpiIODecl:
\_io_decl: (quotient)
|vpiName:quotient
|vpiDirection:1
|vpiExpr:
\_logic_net: (quotient), line:248
|vpiIODecl:
\_io_decl: (done)
|vpiName:done
|vpiDirection:1
|vpiExpr:
\_logic_net: (done), line:249
|vpiIODecl:
\_io_decl: (divisor_is_zero)
|vpiName:divisor_is_zero
|vpiDirection:1
|vpiExpr:
\_logic_net: (divisor_is_zero), line:250
|vpiIODecl:
\_io_decl: (dividend)
|vpiName:dividend
|vpiDirection:2
|vpiExpr:
\_logic_net: (dividend), line:245
|vpiIODecl:
\_io_decl: (divisor)
|vpiName:divisor
|vpiDirection:2
|vpiExpr:
\_logic_net: (divisor), line:246
|vpiIODecl:
\_io_decl: (start)
|vpiName:start
|vpiDirection:2
|vpiExpr:
\_logic_net: (start), line:244
|vpiInterface:
\_interface: work@unsigned_division_interface (div), file:third_party/cores/taiga/core/div_algorithms/div_algorithm.sv, line:43
|vpiNet:
\_logic_net: (clk), line:27, parent:div_block
|vpiNet:
\_logic_net: (rst), line:28, parent:div_block
|vpiNet:
\_logic_net: (terminate), line:32, parent:div_block
|vpiName:terminate
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.terminate
|vpiNetType:36
|vpiNet:
\_logic_net: (terminate_early), line:33, parent:div_block
|vpiName:terminate_early
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.terminate_early
|vpiNetType:36
|vpiNet:
\_logic_net: (shift_count), line:34, parent:div_block
|vpiName:shift_count
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.shift_count
|vpiNetType:36
|vpiRange:
\_range: , line:34
|vpiLeftRange:
\_constant: , line:34
|vpiConstType:7
|vpiDecompile:10
|vpiSize:32
|INT:10
|vpiRightRange:
\_constant: , line:34
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (PR), line:36, parent:div_block
|vpiName:PR
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.PR
|vpiNetType:36
|vpiRange:
\_range: , line:36
|vpiLeftRange:
\_operation: , line:36
|vpiOpType:24
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:36
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:36
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiRightRange:
\_constant: , line:36
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (Q_33), line:37, parent:div_block
|vpiName:Q_33
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.Q_33
|vpiNetType:36
|vpiRange:
\_range: , line:37
|vpiLeftRange:
\_ref_obj: (div.DATA_WIDTH), line:37
|vpiName:div.DATA_WIDTH
|vpiRightRange:
\_constant: , line:37
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (new_PR_sign), line:38, parent:div_block
|vpiName:new_PR_sign
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.new_PR_sign
|vpiNetType:36
|vpiRange:
\_range: , line:38
|vpiLeftRange:
\_constant: , line:38
|vpiConstType:7
|vpiDecompile:6
|vpiSize:32
|INT:6
|vpiRightRange:
\_constant: , line:38
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (new_PR_1), line:40, parent:div_block
|vpiName:new_PR_1
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.new_PR_1
|vpiNetType:36
|vpiRange:
\_range: , line:40
|vpiLeftRange:
\_operation: , line:40
|vpiOpType:24
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:40
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:40
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiRightRange:
\_constant: , line:40
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (new_PR_2), line:41, parent:div_block
|vpiName:new_PR_2
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.new_PR_2
|vpiNetType:36
|vpiRange:
\_range: , line:41
|vpiLeftRange:
\_operation: , line:41
|vpiOpType:24
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:41
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:41
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiRightRange:
\_constant: , line:41
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (new_PR_3), line:42, parent:div_block
|vpiName:new_PR_3
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.new_PR_3
|vpiNetType:36
|vpiRange:
\_range: , line:42
|vpiLeftRange:
\_operation: , line:42
|vpiOpType:24
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:42
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:42
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiRightRange:
\_constant: , line:42
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (new_PR_4), line:43, parent:div_block
|vpiName:new_PR_4
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.new_PR_4
|vpiNetType:36
|vpiRange:
\_range: , line:43
|vpiLeftRange:
\_operation: , line:43
|vpiOpType:24
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:43
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:43
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiRightRange:
\_constant: , line:43
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (new_PR_5), line:44, parent:div_block
|vpiName:new_PR_5
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.new_PR_5
|vpiNetType:36
|vpiRange:
\_range: , line:44
|vpiLeftRange:
\_operation: , line:44
|vpiOpType:24
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:44
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:44
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiRightRange:
\_constant: , line:44
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (new_PR_6), line:45, parent:div_block
|vpiName:new_PR_6
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.new_PR_6
|vpiNetType:36
|vpiRange:
\_range: , line:45
|vpiLeftRange:
\_operation: , line:45
|vpiOpType:24
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:45
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:45
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiRightRange:
\_constant: , line:45
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (new_PR_7), line:46, parent:div_block
|vpiName:new_PR_7
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.new_PR_7
|vpiNetType:36
|vpiRange:
\_range: , line:46
|vpiLeftRange:
\_operation: , line:46
|vpiOpType:24
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:46
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:46
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiRightRange:
\_constant: , line:46
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (div), line:29, parent:div_block
|vpiName:div
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.div
|vpiInstance:
\_module: work@div_algorithm (div_core), file:third_party/cores/taiga/core/div_unit_core_wrapper.sv, line:44, parent:work@div_unit_core_wrapper
|vpiModule:
\_module: work@div_radix16 (div_block), file:third_party/cores/taiga/core/div_algorithms/div_algorithm.sv, line:44, parent:div_core
|vpiDefName:work@div_radix16
|vpiName:div_block
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block
|vpiPort:
\_port: (clk), line:27, parent:div_block
|vpiName:clk
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (clk), line:44
|vpiName:clk
|vpiActual:
\_logic_net: (clk), line:29, parent:div_core
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (clk), line:27, parent:div_block
|vpiName:clk
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.clk
|vpiNetType:36
|vpiPort:
\_port: (rst), line:28, parent:div_block
|vpiName:rst
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (rst), line:44
|vpiName:rst
|vpiActual:
\_logic_net: (rst), line:30, parent:div_core
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (rst), line:28, parent:div_block
|vpiName:rst
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.rst
|vpiNetType:36
|vpiPort:
\_port: (div), line:29, parent:div_block
|vpiName:div
|vpiDirection:5
|vpiHighConn:
\_ref_obj: (div), line:44
|vpiName:div
|vpiActual:
\_interface: work@unsigned_division_interface (div), file:third_party/cores/taiga/core/div_unit_core_wrapper.sv, line:44
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_modport: (divider)
|vpiName:divider
|vpiIODecl:
\_io_decl: (remainder)
|vpiName:remainder
|vpiDirection:2
|vpiExpr:
\_logic_net: (remainder), line:247
|vpiName:remainder
|vpiNetType:36
|vpiRange:
\_range: , line:247
|vpiLeftRange:
\_constant: , line:247
|vpiDecompile:31
|INT:31
|vpiRightRange:
\_constant: , line:247
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (quotient)
|vpiName:quotient
|vpiDirection:2
|vpiExpr:
\_logic_net: (quotient), line:248
|vpiName:quotient
|vpiNetType:36
|vpiRange:
\_range: , line:248
|vpiLeftRange:
\_constant: , line:248
|vpiDecompile:31
|INT:31
|vpiRightRange:
\_constant: , line:248
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (done)
|vpiName:done
|vpiDirection:2
|vpiExpr:
\_logic_net: (done), line:249
|vpiName:done
|vpiNetType:36
|vpiIODecl:
\_io_decl: (divisor_is_zero)
|vpiName:divisor_is_zero
|vpiDirection:2
|vpiExpr:
\_logic_net: (divisor_is_zero), line:250
|vpiName:divisor_is_zero
|vpiNetType:36
|vpiIODecl:
\_io_decl: (dividend)
|vpiName:dividend
|vpiDirection:1
|vpiExpr:
\_logic_net: (dividend), line:245
|vpiName:dividend
|vpiNetType:36
|vpiRange:
\_range: , line:245
|vpiLeftRange:
\_constant: , line:245
|vpiDecompile:31
|INT:31
|vpiRightRange:
\_constant: , line:245
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (divisor)
|vpiName:divisor
|vpiDirection:1
|vpiExpr:
\_logic_net: (divisor), line:246
|vpiName:divisor
|vpiNetType:36
|vpiRange:
\_range: , line:246
|vpiLeftRange:
\_constant: , line:246
|vpiDecompile:31
|INT:31
|vpiRightRange:
\_constant: , line:246
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (start)
|vpiName:start
|vpiDirection:1
|vpiExpr:
\_logic_net: (start), line:244
|vpiName:start
|vpiNetType:36
|vpiInterface:
\_interface: work@unsigned_division_interface (div), file:third_party/cores/taiga/core/div_algorithms/div_algorithm.sv, line:44
|vpiDefName:work@unsigned_division_interface
|vpiName:div
|vpiModport:
\_modport: (divider)
|vpiModport:
\_modport: (requester)
|vpiName:requester
|vpiIODecl:
\_io_decl: (remainder)
|vpiName:remainder
|vpiDirection:1
|vpiExpr:
\_logic_net: (remainder), line:247
|vpiIODecl:
\_io_decl: (quotient)
|vpiName:quotient
|vpiDirection:1
|vpiExpr:
\_logic_net: (quotient), line:248
|vpiIODecl:
\_io_decl: (done)
|vpiName:done
|vpiDirection:1
|vpiExpr:
\_logic_net: (done), line:249
|vpiIODecl:
\_io_decl: (divisor_is_zero)
|vpiName:divisor_is_zero
|vpiDirection:1
|vpiExpr:
\_logic_net: (divisor_is_zero), line:250
|vpiIODecl:
\_io_decl: (dividend)
|vpiName:dividend
|vpiDirection:2
|vpiExpr:
\_logic_net: (dividend), line:245
|vpiIODecl:
\_io_decl: (divisor)
|vpiName:divisor
|vpiDirection:2
|vpiExpr:
\_logic_net: (divisor), line:246
|vpiIODecl:
\_io_decl: (start)
|vpiName:start
|vpiDirection:2
|vpiExpr:
\_logic_net: (start), line:244
|vpiInterface:
\_interface: work@unsigned_division_interface (div), file:third_party/cores/taiga/core/div_algorithms/div_algorithm.sv, line:44
|vpiNet:
\_logic_net: (clk), line:27, parent:div_block
|vpiNet:
\_logic_net: (rst), line:28, parent:div_block
|vpiNet:
\_logic_net: (terminate), line:33, parent:div_block
|vpiName:terminate
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.terminate
|vpiNetType:36
|vpiNet:
\_logic_net: (shift_count), line:34, parent:div_block
|vpiName:shift_count
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.shift_count
|vpiNetType:36
|vpiRange:
\_range: , line:34
|vpiLeftRange:
\_operation: , line:34
|vpiOpType:11
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:34
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:34
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:34
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (PR), line:36, parent:div_block
|vpiName:PR
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.PR
|vpiNetType:36
|vpiRange:
\_range: , line:36
|vpiLeftRange:
\_operation: , line:36
|vpiOpType:24
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:36
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:36
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiRightRange:
\_constant: , line:36
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (PR_lower), line:37, parent:div_block
|vpiName:PR_lower
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.PR_lower
|vpiNetType:36
|vpiRange:
\_range: , line:37
|vpiLeftRange:
\_operation: , line:37
|vpiOpType:24
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:37
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:37
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiRightRange:
\_constant: , line:37
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (PR_upper), line:38, parent:div_block
|vpiName:PR_upper
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.PR_upper
|vpiNetType:36
|vpiRange:
\_range: , line:38
|vpiLeftRange:
\_operation: , line:38
|vpiOpType:24
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:38
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:38
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiRightRange:
\_constant: , line:38
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (Q_lower), line:39, parent:div_block
|vpiName:Q_lower
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.Q_lower
|vpiNetType:36
|vpiRange:
\_range: , line:39
|vpiLeftRange:
\_operation: , line:39
|vpiOpType:11
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:39
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:39
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:39
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (Q_upper), line:40, parent:div_block
|vpiName:Q_upper
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.Q_upper
|vpiNetType:36
|vpiRange:
\_range: , line:40
|vpiLeftRange:
\_operation: , line:40
|vpiOpType:11
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:40
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:40
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:40
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (new_PR_sign), line:42, parent:div_block
|vpiName:new_PR_sign
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.new_PR_sign
|vpiNetType:36
|vpiRange:
\_range: , line:42
|vpiLeftRange:
\_constant: , line:42
|vpiConstType:7
|vpiDecompile:6
|vpiSize:32
|INT:6
|vpiRightRange:
\_constant: , line:42
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (new_PR_8), line:43, parent:div_block
|vpiName:new_PR_8
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.new_PR_8
|vpiNetType:36
|vpiRange:
\_range: , line:43
|vpiLeftRange:
\_operation: , line:43
|vpiOpType:24
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:43
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:43
|vpiConstType:7
|vpiDecompile:4
|vpiSize:32
|INT:4
|vpiRightRange:
\_constant: , line:43
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (B_6), line:46, parent:div_block
|vpiName:B_6
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.B_6
|vpiNetType:36
|vpiRange:
\_range: , line:46
|vpiLeftRange:
\_operation: , line:46
|vpiOpType:24
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:46
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:46
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiRightRange:
\_constant: , line:46
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (B_10), line:47, parent:div_block
|vpiName:B_10
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.B_10
|vpiNetType:36
|vpiRange:
\_range: , line:47
|vpiLeftRange:
\_operation: , line:47
|vpiOpType:24
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:47
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:47
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiRightRange:
\_constant: , line:47
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (B_12), line:48, parent:div_block
|vpiName:B_12
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.B_12
|vpiNetType:36
|vpiRange:
\_range: , line:48
|vpiLeftRange:
\_operation: , line:48
|vpiOpType:24
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:48
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:48
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiRightRange:
\_constant: , line:48
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (B_14), line:49, parent:div_block
|vpiName:B_14
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.B_14
|vpiNetType:36
|vpiRange:
\_range: , line:49
|vpiLeftRange:
\_operation: , line:49
|vpiOpType:24
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:49
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:49
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiRightRange:
\_constant: , line:49
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (div), line:29, parent:div_block
|vpiName:div
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.div
|vpiInstance:
\_module: work@div_algorithm (div_core), file:third_party/cores/taiga/core/div_unit_core_wrapper.sv, line:44, parent:work@div_unit_core_wrapper
|vpiArrayNet:
\_array_net: (new_PR), line:44, parent:div_block
|vpiName:new_PR
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.new_PR
|vpiSize:7
|vpiNet:
\_logic_net: , parent:new_PR
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.new_PR
|vpiNetType:36
|vpiRange:
\_range: , line:44
|vpiLeftRange:
\_operation: , line:44
|vpiOpType:24
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:44
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:44
|vpiConstType:7
|vpiDecompile:4
|vpiSize:32
|INT:4
|vpiRightRange:
\_constant: , line:44
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiRange:
\_range: , line:44
|vpiLeftRange:
\_constant: , line:44
|vpiConstType:7
|vpiDecompile:6
|vpiSize:32
|INT:6
|vpiRightRange:
\_constant: , line:44
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiModule:
\_module: work@div_quick_naive (div_block), file:third_party/cores/taiga/core/div_algorithms/div_algorithm.sv, line:45, parent:div_core
|vpiDefName:work@div_quick_naive
|vpiName:div_block
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block
|vpiPort:
\_port: (clk), line:27, parent:div_block
|vpiName:clk
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (clk), line:45
|vpiName:clk
|vpiActual:
\_logic_net: (clk), line:29, parent:div_core
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (clk), line:27, parent:div_block
|vpiName:clk
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.clk
|vpiNetType:36
|vpiPort:
\_port: (rst), line:28, parent:div_block
|vpiName:rst
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (rst), line:45
|vpiName:rst
|vpiActual:
\_logic_net: (rst), line:30, parent:div_core
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (rst), line:28, parent:div_block
|vpiName:rst
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.rst
|vpiNetType:36
|vpiPort:
\_port: (div), line:29, parent:div_block
|vpiName:div
|vpiDirection:5
|vpiHighConn:
\_ref_obj: (div), line:45
|vpiName:div
|vpiActual:
\_interface: work@unsigned_division_interface (div), file:third_party/cores/taiga/core/div_unit_core_wrapper.sv, line:44
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_modport: (divider)
|vpiName:divider
|vpiIODecl:
\_io_decl: (remainder)
|vpiName:remainder
|vpiDirection:2
|vpiExpr:
\_logic_net: (remainder), line:247
|vpiName:remainder
|vpiNetType:36
|vpiRange:
\_range: , line:247
|vpiLeftRange:
\_constant: , line:247
|vpiDecompile:31
|INT:31
|vpiRightRange:
\_constant: , line:247
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (quotient)
|vpiName:quotient
|vpiDirection:2
|vpiExpr:
\_logic_net: (quotient), line:248
|vpiName:quotient
|vpiNetType:36
|vpiRange:
\_range: , line:248
|vpiLeftRange:
\_constant: , line:248
|vpiDecompile:31
|INT:31
|vpiRightRange:
\_constant: , line:248
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (done)
|vpiName:done
|vpiDirection:2
|vpiExpr:
\_logic_net: (done), line:249
|vpiName:done
|vpiNetType:36
|vpiIODecl:
\_io_decl: (divisor_is_zero)
|vpiName:divisor_is_zero
|vpiDirection:2
|vpiExpr:
\_logic_net: (divisor_is_zero), line:250
|vpiName:divisor_is_zero
|vpiNetType:36
|vpiIODecl:
\_io_decl: (dividend)
|vpiName:dividend
|vpiDirection:1
|vpiExpr:
\_logic_net: (dividend), line:245
|vpiName:dividend
|vpiNetType:36
|vpiRange:
\_range: , line:245
|vpiLeftRange:
\_constant: , line:245
|vpiDecompile:31
|INT:31
|vpiRightRange:
\_constant: , line:245
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (divisor)
|vpiName:divisor
|vpiDirection:1
|vpiExpr:
\_logic_net: (divisor), line:246
|vpiName:divisor
|vpiNetType:36
|vpiRange:
\_range: , line:246
|vpiLeftRange:
\_constant: , line:246
|vpiDecompile:31
|INT:31
|vpiRightRange:
\_constant: , line:246
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (start)
|vpiName:start
|vpiDirection:1
|vpiExpr:
\_logic_net: (start), line:244
|vpiName:start
|vpiNetType:36
|vpiInterface:
\_interface: work@unsigned_division_interface (div), file:third_party/cores/taiga/core/div_algorithms/div_algorithm.sv, line:45
|vpiDefName:work@unsigned_division_interface
|vpiName:div
|vpiModport:
\_modport: (divider)
|vpiModport:
\_modport: (requester)
|vpiName:requester
|vpiIODecl:
\_io_decl: (remainder)
|vpiName:remainder
|vpiDirection:1
|vpiExpr:
\_logic_net: (remainder), line:247
|vpiIODecl:
\_io_decl: (quotient)
|vpiName:quotient
|vpiDirection:1
|vpiExpr:
\_logic_net: (quotient), line:248
|vpiIODecl:
\_io_decl: (done)
|vpiName:done
|vpiDirection:1
|vpiExpr:
\_logic_net: (done), line:249
|vpiIODecl:
\_io_decl: (divisor_is_zero)
|vpiName:divisor_is_zero
|vpiDirection:1
|vpiExpr:
\_logic_net: (divisor_is_zero), line:250
|vpiIODecl:
\_io_decl: (dividend)
|vpiName:dividend
|vpiDirection:2
|vpiExpr:
\_logic_net: (dividend), line:245
|vpiIODecl:
\_io_decl: (divisor)
|vpiName:divisor
|vpiDirection:2
|vpiExpr:
\_logic_net: (divisor), line:246
|vpiIODecl:
\_io_decl: (start)
|vpiName:start
|vpiDirection:2
|vpiExpr:
\_logic_net: (start), line:244
|vpiInterface:
\_interface: work@unsigned_division_interface (div), file:third_party/cores/taiga/core/div_algorithms/div_algorithm.sv, line:45
|vpiModule:
\_module: work@msb_naive (msb_r), file:third_party/cores/taiga/core/div_algorithms/div_quick_naive.sv, line:53, parent:div_block
|vpiDefName:work@msb_naive
|vpiName:msb_r
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.msb_r
|vpiPort:
\_port: (msb_input), line:27, parent:msb_r
|vpiName:msb_input
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (div.remainder), line:53
|vpiName:div.remainder
|vpiActual:
\_logic_net: (remainder), line:247
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (msb_input), line:27, parent:msb_r
|vpiName:msb_input
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.msb_r.msb_input
|vpiNetType:36
|vpiRange:
\_range: , line:27
|vpiLeftRange:
\_constant: , line:27
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:27
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiPort:
\_port: (msb), line:28, parent:msb_r
|vpiName:msb
|vpiDirection:2
|vpiHighConn:
\_ref_obj: (R_MSB), line:53
|vpiName:R_MSB
|vpiActual:
\_logic_net: (R_MSB), line:48, parent:div_block
|vpiName:R_MSB
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.R_MSB
|vpiNetType:36
|vpiRange:
\_range: , line:48
|vpiLeftRange:
\_constant: , line:48
|vpiDecompile:-1
|INT:-1
|vpiRightRange:
\_constant: , line:48
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (msb), line:28, parent:msb_r
|vpiName:msb
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.msb_r.msb
|vpiNetType:36
|vpiRange:
\_range: , line:28
|vpiLeftRange:
\_constant: , line:28
|vpiConstType:7
|vpiDecompile:4
|vpiSize:32
|INT:4
|vpiRightRange:
\_constant: , line:28
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (msb_input), line:27, parent:msb_r
|vpiNet:
\_logic_net: (msb), line:28, parent:msb_r
|vpiInstance:
\_module: work@div_quick_naive (div_block), file:third_party/cores/taiga/core/div_algorithms/div_algorithm.sv, line:45, parent:div_core
|vpiModule:
\_module: work@msb_naive (msb_b), file:third_party/cores/taiga/core/div_algorithms/div_quick_naive.sv, line:54, parent:div_block
|vpiDefName:work@msb_naive
|vpiName:msb_b
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.msb_b
|vpiPort:
\_port: (msb_input), line:27, parent:msb_b
|vpiName:msb_input
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (div.divisor), line:54
|vpiName:div.divisor
|vpiActual:
\_logic_net: (divisor), line:246
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (msb_input), line:27, parent:msb_b
|vpiName:msb_input
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.msb_b.msb_input
|vpiNetType:36
|vpiRange:
\_range: , line:27
|vpiLeftRange:
\_constant: , line:27
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:27
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiPort:
\_port: (msb), line:28, parent:msb_b
|vpiName:msb
|vpiDirection:2
|vpiHighConn:
\_ref_obj: (B_MSB), line:54
|vpiName:B_MSB
|vpiActual:
\_logic_net: (B_MSB), line:49, parent:div_block
|vpiName:B_MSB
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.B_MSB
|vpiNetType:36
|vpiRange:
\_range: , line:49
|vpiLeftRange:
\_constant: , line:49
|vpiDecompile:-1
|INT:-1
|vpiRightRange:
\_constant: , line:49
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (msb), line:28, parent:msb_b
|vpiName:msb
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.msb_b.msb
|vpiNetType:36
|vpiRange:
\_range: , line:28
|vpiLeftRange:
\_constant: , line:28
|vpiConstType:7
|vpiDecompile:4
|vpiSize:32
|INT:4
|vpiRightRange:
\_constant: , line:28
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (msb_input), line:27, parent:msb_b
|vpiNet:
\_logic_net: (msb), line:28, parent:msb_b
|vpiInstance:
\_module: work@div_quick_naive (div_block), file:third_party/cores/taiga/core/div_algorithms/div_algorithm.sv, line:45, parent:div_core
|vpiNet:
\_logic_net: (clk), line:27, parent:div_block
|vpiNet:
\_logic_net: (rst), line:28, parent:div_block
|vpiNet:
\_logic_net: (running), line:32, parent:div_block
|vpiName:running
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.running
|vpiNetType:36
|vpiNet:
\_logic_net: (terminate), line:33, parent:div_block
|vpiName:terminate
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.terminate
|vpiNetType:36
|vpiNet:
\_logic_net: (A1), line:35, parent:div_block
|vpiName:A1
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.A1
|vpiNetType:36
|vpiRange:
\_range: , line:35
|vpiLeftRange:
\_ref_obj: (div.DATA_WIDTH), line:35
|vpiName:div.DATA_WIDTH
|vpiRightRange:
\_constant: , line:35
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (A2), line:36, parent:div_block
|vpiName:A2
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.A2
|vpiNetType:36
|vpiRange:
\_range: , line:36
|vpiLeftRange:
\_operation: , line:36
|vpiOpType:11
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:36
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:36
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:36
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (new_R), line:38, parent:div_block
|vpiName:new_R
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.new_R
|vpiNetType:36
|vpiRange:
\_range: , line:38
|vpiLeftRange:
\_operation: , line:38
|vpiOpType:11
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:38
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:38
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:38
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (new_Q_bit), line:39, parent:div_block
|vpiName:new_Q_bit
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.new_Q_bit
|vpiNetType:36
|vpiRange:
\_range: , line:39
|vpiLeftRange:
\_operation: , line:39
|vpiOpType:11
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:39
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:39
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:39
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (Q_bit1), line:41, parent:div_block
|vpiName:Q_bit1
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.Q_bit1
|vpiNetType:36
|vpiRange:
\_range: , line:41
|vpiLeftRange:
\_operation: , line:41
|vpiOpType:11
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:41
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:41
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:41
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (Q_bit2), line:42, parent:div_block
|vpiName:Q_bit2
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.Q_bit2
|vpiNetType:36
|vpiRange:
\_range: , line:42
|vpiLeftRange:
\_operation: , line:42
|vpiOpType:11
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:42
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:42
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:42
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (B1), line:44, parent:div_block
|vpiName:B1
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.B1
|vpiNetType:36
|vpiRange:
\_range: , line:44
|vpiLeftRange:
\_operation: , line:44
|vpiOpType:11
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:44
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:44
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:44
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (B2), line:45, parent:div_block
|vpiName:B2
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.B2
|vpiNetType:36
|vpiRange:
\_range: , line:45
|vpiLeftRange:
\_operation: , line:45
|vpiOpType:11
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:45
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:45
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:45
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (R_MSB), line:48, parent:div_block
|vpiNet:
\_logic_net: (B_MSB), line:49, parent:div_block
|vpiNet:
\_logic_net: (B_MSB_r), line:50, parent:div_block
|vpiName:B_MSB_r
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.B_MSB_r
|vpiNetType:36
|vpiRange:
\_range: , line:50
|vpiLeftRange:
\_constant: , line:50
|vpiDecompile:-1
|INT:-1
|vpiRightRange:
\_constant: , line:50
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (MSB_delta), line:51, parent:div_block
|vpiName:MSB_delta
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.MSB_delta
|vpiNetType:36
|vpiRange:
\_range: , line:51
|vpiLeftRange:
\_constant: , line:51
|vpiDecompile:-1
|INT:-1
|vpiRightRange:
\_constant: , line:51
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (div), line:29, parent:div_block
|vpiName:div
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.div
|vpiInstance:
\_module: work@div_algorithm (div_core), file:third_party/cores/taiga/core/div_unit_core_wrapper.sv, line:44, parent:work@div_unit_core_wrapper
|vpiParameter:
\_parameter: (MSB_W), line:47
|vpiName:MSB_W
|INT:0
|vpiModule:
\_module: work@div_quick_clz (div_block), file:third_party/cores/taiga/core/div_algorithms/div_algorithm.sv, line:46, parent:div_core
|vpiDefName:work@div_quick_clz
|vpiName:div_block
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block
|vpiPort:
\_port: (clk), line:27, parent:div_block
|vpiName:clk
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (clk), line:46
|vpiName:clk
|vpiActual:
\_logic_net: (clk), line:29, parent:div_core
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (clk), line:27, parent:div_block
|vpiName:clk
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.clk
|vpiNetType:36
|vpiPort:
\_port: (rst), line:28, parent:div_block
|vpiName:rst
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (rst), line:46
|vpiName:rst
|vpiActual:
\_logic_net: (rst), line:30, parent:div_core
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (rst), line:28, parent:div_block
|vpiName:rst
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.rst
|vpiNetType:36
|vpiPort:
\_port: (div), line:29, parent:div_block
|vpiName:div
|vpiDirection:5
|vpiHighConn:
\_ref_obj: (div), line:46
|vpiName:div
|vpiActual:
\_interface: work@unsigned_division_interface (div), file:third_party/cores/taiga/core/div_unit_core_wrapper.sv, line:44
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_modport: (divider)
|vpiName:divider
|vpiIODecl:
\_io_decl: (remainder)
|vpiName:remainder
|vpiDirection:2
|vpiExpr:
\_logic_net: (remainder), line:247
|vpiName:remainder
|vpiNetType:36
|vpiRange:
\_range: , line:247
|vpiLeftRange:
\_constant: , line:247
|vpiDecompile:31
|INT:31
|vpiRightRange:
\_constant: , line:247
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (quotient)
|vpiName:quotient
|vpiDirection:2
|vpiExpr:
\_logic_net: (quotient), line:248
|vpiName:quotient
|vpiNetType:36
|vpiRange:
\_range: , line:248
|vpiLeftRange:
\_constant: , line:248
|vpiDecompile:31
|INT:31
|vpiRightRange:
\_constant: , line:248
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (done)
|vpiName:done
|vpiDirection:2
|vpiExpr:
\_logic_net: (done), line:249
|vpiName:done
|vpiNetType:36
|vpiIODecl:
\_io_decl: (divisor_is_zero)
|vpiName:divisor_is_zero
|vpiDirection:2
|vpiExpr:
\_logic_net: (divisor_is_zero), line:250
|vpiName:divisor_is_zero
|vpiNetType:36
|vpiIODecl:
\_io_decl: (dividend)
|vpiName:dividend
|vpiDirection:1
|vpiExpr:
\_logic_net: (dividend), line:245
|vpiName:dividend
|vpiNetType:36
|vpiRange:
\_range: , line:245
|vpiLeftRange:
\_constant: , line:245
|vpiDecompile:31
|INT:31
|vpiRightRange:
\_constant: , line:245
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (divisor)
|vpiName:divisor
|vpiDirection:1
|vpiExpr:
\_logic_net: (divisor), line:246
|vpiName:divisor
|vpiNetType:36
|vpiRange:
\_range: , line:246
|vpiLeftRange:
\_constant: , line:246
|vpiDecompile:31
|INT:31
|vpiRightRange:
\_constant: , line:246
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (start)
|vpiName:start
|vpiDirection:1
|vpiExpr:
\_logic_net: (start), line:244
|vpiName:start
|vpiNetType:36
|vpiInterface:
\_interface: work@unsigned_division_interface (div), file:third_party/cores/taiga/core/div_algorithms/div_algorithm.sv, line:46
|vpiDefName:work@unsigned_division_interface
|vpiName:div
|vpiModport:
\_modport: (divider)
|vpiModport:
\_modport: (requester)
|vpiName:requester
|vpiIODecl:
\_io_decl: (remainder)
|vpiName:remainder
|vpiDirection:1
|vpiExpr:
\_logic_net: (remainder), line:247
|vpiIODecl:
\_io_decl: (quotient)
|vpiName:quotient
|vpiDirection:1
|vpiExpr:
\_logic_net: (quotient), line:248
|vpiIODecl:
\_io_decl: (done)
|vpiName:done
|vpiDirection:1
|vpiExpr:
\_logic_net: (done), line:249
|vpiIODecl:
\_io_decl: (divisor_is_zero)
|vpiName:divisor_is_zero
|vpiDirection:1
|vpiExpr:
\_logic_net: (divisor_is_zero), line:250
|vpiIODecl:
\_io_decl: (dividend)
|vpiName:dividend
|vpiDirection:2
|vpiExpr:
\_logic_net: (dividend), line:245
|vpiIODecl:
\_io_decl: (divisor)
|vpiName:divisor
|vpiDirection:2
|vpiExpr:
\_logic_net: (divisor), line:246
|vpiIODecl:
\_io_decl: (start)
|vpiName:start
|vpiDirection:2
|vpiExpr:
\_logic_net: (start), line:244
|vpiInterface:
\_interface: work@unsigned_division_interface (div), file:third_party/cores/taiga/core/div_algorithms/div_algorithm.sv, line:46
|vpiModule:
\_module: work@clz (remainder_clz_block), file:third_party/cores/taiga/core/div_algorithms/div_quick_clz.sv, line:57, parent:div_block
|vpiDefName:work@clz
|vpiName:remainder_clz_block
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.remainder_clz_block
|vpiPort:
\_port: (clz_input), line:25, parent:remainder_clz_block
|vpiName:clz_input
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (div.remainder), line:57
|vpiName:div.remainder
|vpiActual:
\_logic_net: (remainder), line:247
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (clz_input), line:25, parent:remainder_clz_block
|vpiName:clz_input
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.remainder_clz_block.clz_input
|vpiNetType:36
|vpiRange:
\_range: , line:25
|vpiLeftRange:
\_constant: , line:25
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:25
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiPort:
\_port: (clz), line:26, parent:remainder_clz_block
|vpiName:clz
|vpiDirection:2
|vpiHighConn:
\_ref_obj: (remainder_CLZ), line:57
|vpiName:remainder_CLZ
|vpiActual:
\_logic_net: (remainder_CLZ), line:51, parent:div_block
|vpiName:remainder_CLZ
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.remainder_CLZ
|vpiNetType:36
|vpiRange:
\_range: , line:51
|vpiLeftRange:
\_constant: , line:51
|vpiDecompile:-1
|INT:-1
|vpiRightRange:
\_constant: , line:51
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (clz), line:26, parent:remainder_clz_block
|vpiName:clz
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.remainder_clz_block.clz
|vpiNetType:36
|vpiRange:
\_range: , line:26
|vpiLeftRange:
\_constant: , line:26
|vpiConstType:7
|vpiDecompile:4
|vpiSize:32
|INT:4
|vpiRightRange:
\_constant: , line:26
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (clz_input), line:25, parent:remainder_clz_block
|vpiNet:
\_logic_net: (clz), line:26, parent:remainder_clz_block
|vpiNet:
\_logic_net: (sub_clz), line:30, parent:remainder_clz_block
|vpiName:sub_clz
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.remainder_clz_block.sub_clz
|vpiNetType:36
|vpiRange:
\_range: , line:30
|vpiLeftRange:
\_constant: , line:30
|vpiConstType:7
|vpiDecompile:7
|vpiSize:32
|INT:7
|vpiRightRange:
\_constant: , line:30
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiInstance:
\_module: work@div_quick_clz (div_block), file:third_party/cores/taiga/core/div_algorithms/div_algorithm.sv, line:46, parent:div_core
|vpiArrayNet:
\_array_net: (low_order_clz), line:29, parent:remainder_clz_block
|vpiName:low_order_clz
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.remainder_clz_block.low_order_clz
|vpiSize:8
|vpiNet:
\_logic_net: , parent:low_order_clz
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.remainder_clz_block.low_order_clz
|vpiNetType:36
|vpiRange:
\_range: , line:29
|vpiLeftRange:
\_constant: , line:29
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:29
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiRange:
\_range: , line:29
|vpiLeftRange:
\_constant: , line:29
|vpiConstType:7
|vpiDecompile:7
|vpiSize:32
|INT:7
|vpiRightRange:
\_constant: , line:29
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiArrayNet:
\_array_net: (upper_lower), line:32, parent:remainder_clz_block
|vpiName:upper_lower
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.remainder_clz_block.upper_lower
|vpiSize:4
|vpiNet:
\_logic_net: , parent:upper_lower
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.remainder_clz_block.upper_lower
|vpiNetType:36
|vpiRange:
\_range: , line:32
|vpiLeftRange:
\_constant: , line:32
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:32
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiRange:
\_range: , line:32
|vpiLeftRange:
\_constant: , line:32
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiRightRange:
\_constant: , line:32
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiModule:
\_module: work@clz (divisor_clz_block), file:third_party/cores/taiga/core/div_algorithms/div_quick_clz.sv, line:58, parent:div_block
|vpiDefName:work@clz
|vpiName:divisor_clz_block
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.divisor_clz_block
|vpiPort:
\_port: (clz_input), line:25, parent:divisor_clz_block
|vpiName:clz_input
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (div.divisor), line:58
|vpiName:div.divisor
|vpiActual:
\_logic_net: (divisor), line:246
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (clz_input), line:25, parent:divisor_clz_block
|vpiName:clz_input
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.divisor_clz_block.clz_input
|vpiNetType:36
|vpiRange:
\_range: , line:25
|vpiLeftRange:
\_constant: , line:25
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:25
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiPort:
\_port: (clz), line:26, parent:divisor_clz_block
|vpiName:clz
|vpiDirection:2
|vpiHighConn:
\_ref_obj: (divisor_CLZ), line:58
|vpiName:divisor_CLZ
|vpiActual:
\_logic_net: (divisor_CLZ), line:52, parent:div_block
|vpiName:divisor_CLZ
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.divisor_CLZ
|vpiNetType:36
|vpiRange:
\_range: , line:52
|vpiLeftRange:
\_constant: , line:52
|vpiDecompile:-1
|INT:-1
|vpiRightRange:
\_constant: , line:52
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (clz), line:26, parent:divisor_clz_block
|vpiName:clz
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.divisor_clz_block.clz
|vpiNetType:36
|vpiRange:
\_range: , line:26
|vpiLeftRange:
\_constant: , line:26
|vpiConstType:7
|vpiDecompile:4
|vpiSize:32
|INT:4
|vpiRightRange:
\_constant: , line:26
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (clz_input), line:25, parent:divisor_clz_block
|vpiNet:
\_logic_net: (clz), line:26, parent:divisor_clz_block
|vpiNet:
\_logic_net: (sub_clz), line:30, parent:divisor_clz_block
|vpiName:sub_clz
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.divisor_clz_block.sub_clz
|vpiNetType:36
|vpiRange:
\_range: , line:30
|vpiLeftRange:
\_constant: , line:30
|vpiConstType:7
|vpiDecompile:7
|vpiSize:32
|INT:7
|vpiRightRange:
\_constant: , line:30
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiInstance:
\_module: work@div_quick_clz (div_block), file:third_party/cores/taiga/core/div_algorithms/div_algorithm.sv, line:46, parent:div_core
|vpiArrayNet:
\_array_net: (low_order_clz), line:29, parent:divisor_clz_block
|vpiName:low_order_clz
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.divisor_clz_block.low_order_clz
|vpiSize:8
|vpiNet:
\_logic_net: , parent:low_order_clz
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.divisor_clz_block.low_order_clz
|vpiNetType:36
|vpiRange:
\_range: , line:29
|vpiLeftRange:
\_constant: , line:29
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:29
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiRange:
\_range: , line:29
|vpiLeftRange:
\_constant: , line:29
|vpiConstType:7
|vpiDecompile:7
|vpiSize:32
|INT:7
|vpiRightRange:
\_constant: , line:29
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiArrayNet:
\_array_net: (upper_lower), line:32, parent:divisor_clz_block
|vpiName:upper_lower
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.divisor_clz_block.upper_lower
|vpiSize:4
|vpiNet:
\_logic_net: , parent:upper_lower
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.divisor_clz_block.upper_lower
|vpiNetType:36
|vpiRange:
\_range: , line:32
|vpiLeftRange:
\_constant: , line:32
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:32
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiRange:
\_range: , line:32
|vpiLeftRange:
\_constant: , line:32
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiRightRange:
\_constant: , line:32
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (clk), line:27, parent:div_block
|vpiNet:
\_logic_net: (rst), line:28, parent:div_block
|vpiNet:
\_logic_net: (running), line:32, parent:div_block
|vpiName:running
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.running
|vpiNetType:36
|vpiNet:
\_logic_net: (terminate), line:33, parent:div_block
|vpiName:terminate
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.terminate
|vpiNetType:36
|vpiNet:
\_logic_net: (normalized_divisor), line:35, parent:div_block
|vpiName:normalized_divisor
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.normalized_divisor
|vpiNetType:36
|vpiRange:
\_range: , line:35
|vpiLeftRange:
\_operation: , line:35
|vpiOpType:11
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:35
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:35
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:35
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (overflow), line:37, parent:div_block
|vpiName:overflow
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.overflow
|vpiNetType:36
|vpiNet:
\_logic_net: (subtraction1), line:38, parent:div_block
|vpiName:subtraction1
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.subtraction1
|vpiNetType:36
|vpiRange:
\_range: , line:38
|vpiLeftRange:
\_operation: , line:38
|vpiOpType:11
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:38
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:38
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:38
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (subtraction2), line:39, parent:div_block
|vpiName:subtraction2
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.subtraction2
|vpiNetType:36
|vpiRange:
\_range: , line:39
|vpiLeftRange:
\_operation: , line:39
|vpiOpType:11
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:39
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:39
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:39
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (new_remainder), line:41, parent:div_block
|vpiName:new_remainder
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.new_remainder
|vpiNetType:36
|vpiRange:
\_range: , line:41
|vpiLeftRange:
\_operation: , line:41
|vpiOpType:11
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:41
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:41
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:41
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (new_quotient), line:42, parent:div_block
|vpiName:new_quotient
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.new_quotient
|vpiNetType:36
|vpiRange:
\_range: , line:42
|vpiLeftRange:
\_operation: , line:42
|vpiOpType:11
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:42
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:42
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:42
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (new_Q_bit1), line:44, parent:div_block
|vpiName:new_Q_bit1
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.new_Q_bit1
|vpiNetType:36
|vpiRange:
\_range: , line:44
|vpiLeftRange:
\_operation: , line:44
|vpiOpType:11
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:44
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:44
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:44
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (new_Q_bit2), line:45, parent:div_block
|vpiName:new_Q_bit2
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.new_Q_bit2
|vpiNetType:36
|vpiRange:
\_range: , line:45
|vpiLeftRange:
\_operation: , line:45
|vpiOpType:11
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:45
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:45
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:45
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (test_multiple1), line:47, parent:div_block
|vpiName:test_multiple1
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.test_multiple1
|vpiNetType:36
|vpiRange:
\_range: , line:47
|vpiLeftRange:
\_operation: , line:47
|vpiOpType:11
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:47
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:47
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:47
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (test_multiple2), line:48, parent:div_block
|vpiName:test_multiple2
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.test_multiple2
|vpiNetType:36
|vpiRange:
\_range: , line:48
|vpiLeftRange:
\_operation: , line:48
|vpiOpType:11
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:48
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:48
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:48
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (remainder_CLZ), line:51, parent:div_block
|vpiNet:
\_logic_net: (divisor_CLZ), line:52, parent:div_block
|vpiNet:
\_logic_net: (divisor_CLZ_r), line:53, parent:div_block
|vpiName:divisor_CLZ_r
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.divisor_CLZ_r
|vpiNetType:36
|vpiRange:
\_range: , line:53
|vpiLeftRange:
\_constant: , line:53
|vpiDecompile:-1
|INT:-1
|vpiRightRange:
\_constant: , line:53
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (CLZ_delta), line:54, parent:div_block
|vpiName:CLZ_delta
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.CLZ_delta
|vpiNetType:36
|vpiRange:
\_range: , line:54
|vpiLeftRange:
\_constant: , line:54
|vpiDecompile:-1
|INT:-1
|vpiRightRange:
\_constant: , line:54
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (div), line:29, parent:div_block
|vpiName:div
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.div
|vpiInstance:
\_module: work@div_algorithm (div_core), file:third_party/cores/taiga/core/div_unit_core_wrapper.sv, line:44, parent:work@div_unit_core_wrapper
|vpiParameter:
\_parameter: (CLZ_W), line:50
|vpiName:CLZ_W
|INT:0
|vpiModule:
\_module: work@div_quick_clz_mk2 (div_block), file:third_party/cores/taiga/core/div_algorithms/div_algorithm.sv, line:47, parent:div_core
|vpiDefName:work@div_quick_clz_mk2
|vpiName:div_block
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block
|vpiPort:
\_port: (clk), line:27, parent:div_block
|vpiName:clk
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (clk), line:47
|vpiName:clk
|vpiActual:
\_logic_net: (clk), line:29, parent:div_core
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (clk), line:27, parent:div_block
|vpiName:clk
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.clk
|vpiNetType:36
|vpiPort:
\_port: (rst), line:28, parent:div_block
|vpiName:rst
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (rst), line:47
|vpiName:rst
|vpiActual:
\_logic_net: (rst), line:30, parent:div_core
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (rst), line:28, parent:div_block
|vpiName:rst
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.rst
|vpiNetType:36
|vpiPort:
\_port: (div), line:29, parent:div_block
|vpiName:div
|vpiDirection:5
|vpiHighConn:
\_ref_obj: (div), line:47
|vpiName:div
|vpiActual:
\_interface: work@unsigned_division_interface (div), file:third_party/cores/taiga/core/div_unit_core_wrapper.sv, line:44
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_modport: (divider)
|vpiName:divider
|vpiIODecl:
\_io_decl: (remainder)
|vpiName:remainder
|vpiDirection:2
|vpiExpr:
\_logic_net: (remainder), line:247
|vpiName:remainder
|vpiNetType:36
|vpiRange:
\_range: , line:247
|vpiLeftRange:
\_constant: , line:247
|vpiDecompile:31
|INT:31
|vpiRightRange:
\_constant: , line:247
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (quotient)
|vpiName:quotient
|vpiDirection:2
|vpiExpr:
\_logic_net: (quotient), line:248
|vpiName:quotient
|vpiNetType:36
|vpiRange:
\_range: , line:248
|vpiLeftRange:
\_constant: , line:248
|vpiDecompile:31
|INT:31
|vpiRightRange:
\_constant: , line:248
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (done)
|vpiName:done
|vpiDirection:2
|vpiExpr:
\_logic_net: (done), line:249
|vpiName:done
|vpiNetType:36
|vpiIODecl:
\_io_decl: (divisor_is_zero)
|vpiName:divisor_is_zero
|vpiDirection:2
|vpiExpr:
\_logic_net: (divisor_is_zero), line:250
|vpiName:divisor_is_zero
|vpiNetType:36
|vpiIODecl:
\_io_decl: (dividend)
|vpiName:dividend
|vpiDirection:1
|vpiExpr:
\_logic_net: (dividend), line:245
|vpiName:dividend
|vpiNetType:36
|vpiRange:
\_range: , line:245
|vpiLeftRange:
\_constant: , line:245
|vpiDecompile:31
|INT:31
|vpiRightRange:
\_constant: , line:245
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (divisor)
|vpiName:divisor
|vpiDirection:1
|vpiExpr:
\_logic_net: (divisor), line:246
|vpiName:divisor
|vpiNetType:36
|vpiRange:
\_range: , line:246
|vpiLeftRange:
\_constant: , line:246
|vpiDecompile:31
|INT:31
|vpiRightRange:
\_constant: , line:246
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (start)
|vpiName:start
|vpiDirection:1
|vpiExpr:
\_logic_net: (start), line:244
|vpiName:start
|vpiNetType:36
|vpiInterface:
\_interface: work@unsigned_division_interface (div), file:third_party/cores/taiga/core/div_algorithms/div_algorithm.sv, line:47
|vpiDefName:work@unsigned_division_interface
|vpiName:div
|vpiModport:
\_modport: (divider)
|vpiModport:
\_modport: (requester)
|vpiName:requester
|vpiIODecl:
\_io_decl: (remainder)
|vpiName:remainder
|vpiDirection:1
|vpiExpr:
\_logic_net: (remainder), line:247
|vpiIODecl:
\_io_decl: (quotient)
|vpiName:quotient
|vpiDirection:1
|vpiExpr:
\_logic_net: (quotient), line:248
|vpiIODecl:
\_io_decl: (done)
|vpiName:done
|vpiDirection:1
|vpiExpr:
\_logic_net: (done), line:249
|vpiIODecl:
\_io_decl: (divisor_is_zero)
|vpiName:divisor_is_zero
|vpiDirection:1
|vpiExpr:
\_logic_net: (divisor_is_zero), line:250
|vpiIODecl:
\_io_decl: (dividend)
|vpiName:dividend
|vpiDirection:2
|vpiExpr:
\_logic_net: (dividend), line:245
|vpiIODecl:
\_io_decl: (divisor)
|vpiName:divisor
|vpiDirection:2
|vpiExpr:
\_logic_net: (divisor), line:246
|vpiIODecl:
\_io_decl: (start)
|vpiName:start
|vpiDirection:2
|vpiExpr:
\_logic_net: (start), line:244
|vpiInterface:
\_interface: work@unsigned_division_interface (div), file:third_party/cores/taiga/core/div_algorithms/div_algorithm.sv, line:47
|vpiModule:
\_module: work@clz (clz_r), file:third_party/cores/taiga/core/div_algorithms/div_quick_clz_mk2.sv, line:58, parent:div_block
|vpiDefName:work@clz
|vpiName:clz_r
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.clz_r
|vpiPort:
\_port: (clz_input), line:25, parent:clz_r
|vpiName:clz_input
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (div.remainder), line:58
|vpiName:div.remainder
|vpiActual:
\_logic_net: (remainder), line:247
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (clz_input), line:25, parent:clz_r
|vpiName:clz_input
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.clz_r.clz_input
|vpiNetType:36
|vpiRange:
\_range: , line:25
|vpiLeftRange:
\_constant: , line:25
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:25
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiPort:
\_port: (clz), line:26, parent:clz_r
|vpiName:clz
|vpiDirection:2
|vpiHighConn:
\_ref_obj: (R_CLZ), line:58
|vpiName:R_CLZ
|vpiActual:
\_logic_net: (R_CLZ), line:50, parent:div_block
|vpiName:R_CLZ
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.R_CLZ
|vpiNetType:36
|vpiRange:
\_range: , line:50
|vpiLeftRange:
\_constant: , line:50
|vpiDecompile:-1
|INT:-1
|vpiRightRange:
\_constant: , line:50
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (clz), line:26, parent:clz_r
|vpiName:clz
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.clz_r.clz
|vpiNetType:36
|vpiRange:
\_range: , line:26
|vpiLeftRange:
\_constant: , line:26
|vpiConstType:7
|vpiDecompile:4
|vpiSize:32
|INT:4
|vpiRightRange:
\_constant: , line:26
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (clz_input), line:25, parent:clz_r
|vpiNet:
\_logic_net: (clz), line:26, parent:clz_r
|vpiNet:
\_logic_net: (sub_clz), line:30, parent:clz_r
|vpiName:sub_clz
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.clz_r.sub_clz
|vpiNetType:36
|vpiRange:
\_range: , line:30
|vpiLeftRange:
\_constant: , line:30
|vpiConstType:7
|vpiDecompile:7
|vpiSize:32
|INT:7
|vpiRightRange:
\_constant: , line:30
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiInstance:
\_module: work@div_quick_clz_mk2 (div_block), file:third_party/cores/taiga/core/div_algorithms/div_algorithm.sv, line:47, parent:div_core
|vpiArrayNet:
\_array_net: (low_order_clz), line:29, parent:clz_r
|vpiName:low_order_clz
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.clz_r.low_order_clz
|vpiSize:8
|vpiNet:
\_logic_net: , parent:low_order_clz
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.clz_r.low_order_clz
|vpiNetType:36
|vpiRange:
\_range: , line:29
|vpiLeftRange:
\_constant: , line:29
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:29
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiRange:
\_range: , line:29
|vpiLeftRange:
\_constant: , line:29
|vpiConstType:7
|vpiDecompile:7
|vpiSize:32
|INT:7
|vpiRightRange:
\_constant: , line:29
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiArrayNet:
\_array_net: (upper_lower), line:32, parent:clz_r
|vpiName:upper_lower
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.clz_r.upper_lower
|vpiSize:4
|vpiNet:
\_logic_net: , parent:upper_lower
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.clz_r.upper_lower
|vpiNetType:36
|vpiRange:
\_range: , line:32
|vpiLeftRange:
\_constant: , line:32
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:32
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiRange:
\_range: , line:32
|vpiLeftRange:
\_constant: , line:32
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiRightRange:
\_constant: , line:32
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiModule:
\_module: work@clz (clz_b), file:third_party/cores/taiga/core/div_algorithms/div_quick_clz_mk2.sv, line:59, parent:div_block
|vpiDefName:work@clz
|vpiName:clz_b
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.clz_b
|vpiPort:
\_port: (clz_input), line:25, parent:clz_b
|vpiName:clz_input
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (div.divisor), line:59
|vpiName:div.divisor
|vpiActual:
\_logic_net: (divisor), line:246
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (clz_input), line:25, parent:clz_b
|vpiName:clz_input
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.clz_b.clz_input
|vpiNetType:36
|vpiRange:
\_range: , line:25
|vpiLeftRange:
\_constant: , line:25
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:25
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiPort:
\_port: (clz), line:26, parent:clz_b
|vpiName:clz
|vpiDirection:2
|vpiHighConn:
\_ref_obj: (B_CLZ), line:59
|vpiName:B_CLZ
|vpiActual:
\_logic_net: (B_CLZ), line:51, parent:div_block
|vpiName:B_CLZ
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.B_CLZ
|vpiNetType:36
|vpiRange:
\_range: , line:51
|vpiLeftRange:
\_constant: , line:51
|vpiDecompile:-1
|INT:-1
|vpiRightRange:
\_constant: , line:51
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (clz), line:26, parent:clz_b
|vpiName:clz
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.clz_b.clz
|vpiNetType:36
|vpiRange:
\_range: , line:26
|vpiLeftRange:
\_constant: , line:26
|vpiConstType:7
|vpiDecompile:4
|vpiSize:32
|INT:4
|vpiRightRange:
\_constant: , line:26
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (clz_input), line:25, parent:clz_b
|vpiNet:
\_logic_net: (clz), line:26, parent:clz_b
|vpiNet:
\_logic_net: (sub_clz), line:30, parent:clz_b
|vpiName:sub_clz
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.clz_b.sub_clz
|vpiNetType:36
|vpiRange:
\_range: , line:30
|vpiLeftRange:
\_constant: , line:30
|vpiConstType:7
|vpiDecompile:7
|vpiSize:32
|INT:7
|vpiRightRange:
\_constant: , line:30
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiInstance:
\_module: work@div_quick_clz_mk2 (div_block), file:third_party/cores/taiga/core/div_algorithms/div_algorithm.sv, line:47, parent:div_core
|vpiArrayNet:
\_array_net: (low_order_clz), line:29, parent:clz_b
|vpiName:low_order_clz
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.clz_b.low_order_clz
|vpiSize:8
|vpiNet:
\_logic_net: , parent:low_order_clz
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.clz_b.low_order_clz
|vpiNetType:36
|vpiRange:
\_range: , line:29
|vpiLeftRange:
\_constant: , line:29
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:29
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiRange:
\_range: , line:29
|vpiLeftRange:
\_constant: , line:29
|vpiConstType:7
|vpiDecompile:7
|vpiSize:32
|INT:7
|vpiRightRange:
\_constant: , line:29
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiArrayNet:
\_array_net: (upper_lower), line:32, parent:clz_b
|vpiName:upper_lower
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.clz_b.upper_lower
|vpiSize:4
|vpiNet:
\_logic_net: , parent:upper_lower
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.clz_b.upper_lower
|vpiNetType:36
|vpiRange:
\_range: , line:32
|vpiLeftRange:
\_constant: , line:32
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:32
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiRange:
\_range: , line:32
|vpiLeftRange:
\_constant: , line:32
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiRightRange:
\_constant: , line:32
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (clk), line:27, parent:div_block
|vpiNet:
\_logic_net: (rst), line:28, parent:div_block
|vpiNet:
\_logic_net: (running), line:32, parent:div_block
|vpiName:running
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.running
|vpiNetType:36
|vpiNet:
\_logic_net: (terminate), line:33, parent:div_block
|vpiName:terminate
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.terminate
|vpiNetType:36
|vpiNet:
\_logic_net: (A0), line:35, parent:div_block
|vpiName:A0
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.A0
|vpiNetType:36
|vpiRange:
\_range: , line:35
|vpiLeftRange:
\_ref_obj: (div.DATA_WIDTH), line:35
|vpiName:div.DATA_WIDTH
|vpiRightRange:
\_constant: , line:35
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (A1), line:36, parent:div_block
|vpiName:A1
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.A1
|vpiNetType:36
|vpiRange:
\_range: , line:36
|vpiLeftRange:
\_ref_obj: (div.DATA_WIDTH), line:36
|vpiName:div.DATA_WIDTH
|vpiRightRange:
\_constant: , line:36
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (A2), line:37, parent:div_block
|vpiName:A2
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.A2
|vpiNetType:36
|vpiRange:
\_range: , line:37
|vpiLeftRange:
\_operation: , line:37
|vpiOpType:11
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:37
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:37
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:37
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (new_R), line:39, parent:div_block
|vpiName:new_R
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.new_R
|vpiNetType:36
|vpiRange:
\_range: , line:39
|vpiLeftRange:
\_operation: , line:39
|vpiOpType:11
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:39
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:39
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:39
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (new_Q_bit), line:40, parent:div_block
|vpiName:new_Q_bit
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.new_Q_bit
|vpiNetType:36
|vpiRange:
\_range: , line:40
|vpiLeftRange:
\_operation: , line:40
|vpiOpType:11
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:40
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:40
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:40
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (new_R2), line:41, parent:div_block
|vpiName:new_R2
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.new_R2
|vpiNetType:36
|vpiRange:
\_range: , line:41
|vpiLeftRange:
\_operation: , line:41
|vpiOpType:11
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:41
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:41
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:41
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (Q_bit1), line:43, parent:div_block
|vpiName:Q_bit1
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.Q_bit1
|vpiNetType:36
|vpiRange:
\_range: , line:43
|vpiLeftRange:
\_operation: , line:43
|vpiOpType:11
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:43
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:43
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:43
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (Q_bit2), line:44, parent:div_block
|vpiName:Q_bit2
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.Q_bit2
|vpiNetType:36
|vpiRange:
\_range: , line:44
|vpiLeftRange:
\_operation: , line:44
|vpiOpType:11
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:44
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:44
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:44
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (B1), line:46, parent:div_block
|vpiName:B1
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.B1
|vpiNetType:36
|vpiRange:
\_range: , line:46
|vpiLeftRange:
\_operation: , line:46
|vpiOpType:11
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:46
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:46
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:46
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (B2), line:47, parent:div_block
|vpiName:B2
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.B2
|vpiNetType:36
|vpiRange:
\_range: , line:47
|vpiLeftRange:
\_operation: , line:47
|vpiOpType:11
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:47
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:47
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:47
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (R_CLZ), line:50, parent:div_block
|vpiNet:
\_logic_net: (B_CLZ), line:51, parent:div_block
|vpiNet:
\_logic_net: (B_CLZ_r), line:52, parent:div_block
|vpiName:B_CLZ_r
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.B_CLZ_r
|vpiNetType:36
|vpiRange:
\_range: , line:52
|vpiLeftRange:
\_constant: , line:52
|vpiDecompile:-1
|INT:-1
|vpiRightRange:
\_constant: , line:52
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (CLZ_delta), line:53, parent:div_block
|vpiName:CLZ_delta
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.CLZ_delta
|vpiNetType:36
|vpiRange:
\_range: , line:53
|vpiLeftRange:
\_constant: , line:53
|vpiDecompile:-1
|INT:-1
|vpiRightRange:
\_constant: , line:53
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (shiftedB), line:55, parent:div_block
|vpiName:shiftedB
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.shiftedB
|vpiNetType:36
|vpiRange:
\_range: , line:55
|vpiLeftRange:
\_operation: , line:55
|vpiOpType:11
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:55
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:55
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:55
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (div), line:29, parent:div_block
|vpiName:div
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.div
|vpiInstance:
\_module: work@div_algorithm (div_core), file:third_party/cores/taiga/core/div_unit_core_wrapper.sv, line:44, parent:work@div_unit_core_wrapper
|vpiParameter:
\_parameter: (CLZ_W), line:49
|vpiName:CLZ_W
|INT:0
|vpiModule:
\_module: work@div_quick_radix_4 (div_block), file:third_party/cores/taiga/core/div_algorithms/div_algorithm.sv, line:48, parent:div_core
|vpiDefName:work@div_quick_radix_4
|vpiName:div_block
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block
|vpiPort:
\_port: (clk), line:27, parent:div_block
|vpiName:clk
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (clk), line:48
|vpiName:clk
|vpiActual:
\_logic_net: (clk), line:29, parent:div_core
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (clk), line:27, parent:div_block
|vpiName:clk
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.clk
|vpiNetType:36
|vpiPort:
\_port: (rst), line:28, parent:div_block
|vpiName:rst
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (rst), line:48
|vpiName:rst
|vpiActual:
\_logic_net: (rst), line:30, parent:div_core
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (rst), line:28, parent:div_block
|vpiName:rst
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.rst
|vpiNetType:36
|vpiPort:
\_port: (div), line:29, parent:div_block
|vpiName:div
|vpiDirection:5
|vpiHighConn:
\_ref_obj: (div), line:48
|vpiName:div
|vpiActual:
\_interface: work@unsigned_division_interface (div), file:third_party/cores/taiga/core/div_unit_core_wrapper.sv, line:44
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_modport: (divider)
|vpiName:divider
|vpiIODecl:
\_io_decl: (remainder)
|vpiName:remainder
|vpiDirection:2
|vpiExpr:
\_logic_net: (remainder), line:247
|vpiName:remainder
|vpiNetType:36
|vpiRange:
\_range: , line:247
|vpiLeftRange:
\_constant: , line:247
|vpiDecompile:31
|INT:31
|vpiRightRange:
\_constant: , line:247
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (quotient)
|vpiName:quotient
|vpiDirection:2
|vpiExpr:
\_logic_net: (quotient), line:248
|vpiName:quotient
|vpiNetType:36
|vpiRange:
\_range: , line:248
|vpiLeftRange:
\_constant: , line:248
|vpiDecompile:31
|INT:31
|vpiRightRange:
\_constant: , line:248
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (done)
|vpiName:done
|vpiDirection:2
|vpiExpr:
\_logic_net: (done), line:249
|vpiName:done
|vpiNetType:36
|vpiIODecl:
\_io_decl: (divisor_is_zero)
|vpiName:divisor_is_zero
|vpiDirection:2
|vpiExpr:
\_logic_net: (divisor_is_zero), line:250
|vpiName:divisor_is_zero
|vpiNetType:36
|vpiIODecl:
\_io_decl: (dividend)
|vpiName:dividend
|vpiDirection:1
|vpiExpr:
\_logic_net: (dividend), line:245
|vpiName:dividend
|vpiNetType:36
|vpiRange:
\_range: , line:245
|vpiLeftRange:
\_constant: , line:245
|vpiDecompile:31
|INT:31
|vpiRightRange:
\_constant: , line:245
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (divisor)
|vpiName:divisor
|vpiDirection:1
|vpiExpr:
\_logic_net: (divisor), line:246
|vpiName:divisor
|vpiNetType:36
|vpiRange:
\_range: , line:246
|vpiLeftRange:
\_constant: , line:246
|vpiDecompile:31
|INT:31
|vpiRightRange:
\_constant: , line:246
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (start)
|vpiName:start
|vpiDirection:1
|vpiExpr:
\_logic_net: (start), line:244
|vpiName:start
|vpiNetType:36
|vpiInterface:
\_interface: work@unsigned_division_interface (div), file:third_party/cores/taiga/core/div_algorithms/div_algorithm.sv, line:48
|vpiDefName:work@unsigned_division_interface
|vpiName:div
|vpiModport:
\_modport: (divider)
|vpiModport:
\_modport: (requester)
|vpiName:requester
|vpiIODecl:
\_io_decl: (remainder)
|vpiName:remainder
|vpiDirection:1
|vpiExpr:
\_logic_net: (remainder), line:247
|vpiIODecl:
\_io_decl: (quotient)
|vpiName:quotient
|vpiDirection:1
|vpiExpr:
\_logic_net: (quotient), line:248
|vpiIODecl:
\_io_decl: (done)
|vpiName:done
|vpiDirection:1
|vpiExpr:
\_logic_net: (done), line:249
|vpiIODecl:
\_io_decl: (divisor_is_zero)
|vpiName:divisor_is_zero
|vpiDirection:1
|vpiExpr:
\_logic_net: (divisor_is_zero), line:250
|vpiIODecl:
\_io_decl: (dividend)
|vpiName:dividend
|vpiDirection:2
|vpiExpr:
\_logic_net: (dividend), line:245
|vpiIODecl:
\_io_decl: (divisor)
|vpiName:divisor
|vpiDirection:2
|vpiExpr:
\_logic_net: (divisor), line:246
|vpiIODecl:
\_io_decl: (start)
|vpiName:start
|vpiDirection:2
|vpiExpr:
\_logic_net: (start), line:244
|vpiInterface:
\_interface: work@unsigned_division_interface (div), file:third_party/cores/taiga/core/div_algorithms/div_algorithm.sv, line:48
|vpiModule:
\_module: work@clz (clz_r), file:third_party/cores/taiga/core/div_algorithms/div_quick_radix4.sv, line:69, parent:div_block
|vpiDefName:work@clz
|vpiName:clz_r
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.clz_r
|vpiPort:
\_port: (clz_input), line:25, parent:clz_r
|vpiName:clz_input
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (div.dividend), line:69
|vpiName:div.dividend
|vpiActual:
\_logic_net: (dividend), line:245
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (clz_input), line:25, parent:clz_r
|vpiName:clz_input
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.clz_r.clz_input
|vpiNetType:36
|vpiRange:
\_range: , line:25
|vpiLeftRange:
\_constant: , line:25
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:25
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiPort:
\_port: (clz), line:26, parent:clz_r
|vpiName:clz
|vpiDirection:2
|vpiHighConn:
\_ref_obj: (A_CLZ), line:69
|vpiName:A_CLZ
|vpiActual:
\_logic_net: (A_CLZ), line:54, parent:div_block
|vpiName:A_CLZ
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.A_CLZ
|vpiNetType:36
|vpiRange:
\_range: , line:54
|vpiLeftRange:
\_constant: , line:54
|vpiDecompile:-1
|INT:-1
|vpiRightRange:
\_constant: , line:54
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (clz), line:26, parent:clz_r
|vpiName:clz
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.clz_r.clz
|vpiNetType:36
|vpiRange:
\_range: , line:26
|vpiLeftRange:
\_constant: , line:26
|vpiConstType:7
|vpiDecompile:4
|vpiSize:32
|INT:4
|vpiRightRange:
\_constant: , line:26
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (clz_input), line:25, parent:clz_r
|vpiNet:
\_logic_net: (clz), line:26, parent:clz_r
|vpiNet:
\_logic_net: (sub_clz), line:30, parent:clz_r
|vpiName:sub_clz
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.clz_r.sub_clz
|vpiNetType:36
|vpiRange:
\_range: , line:30
|vpiLeftRange:
\_constant: , line:30
|vpiConstType:7
|vpiDecompile:7
|vpiSize:32
|INT:7
|vpiRightRange:
\_constant: , line:30
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiInstance:
\_module: work@div_quick_radix_4 (div_block), file:third_party/cores/taiga/core/div_algorithms/div_algorithm.sv, line:48, parent:div_core
|vpiArrayNet:
\_array_net: (low_order_clz), line:29, parent:clz_r
|vpiName:low_order_clz
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.clz_r.low_order_clz
|vpiSize:8
|vpiNet:
\_logic_net: , parent:low_order_clz
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.clz_r.low_order_clz
|vpiNetType:36
|vpiRange:
\_range: , line:29
|vpiLeftRange:
\_constant: , line:29
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:29
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiRange:
\_range: , line:29
|vpiLeftRange:
\_constant: , line:29
|vpiConstType:7
|vpiDecompile:7
|vpiSize:32
|INT:7
|vpiRightRange:
\_constant: , line:29
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiArrayNet:
\_array_net: (upper_lower), line:32, parent:clz_r
|vpiName:upper_lower
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.clz_r.upper_lower
|vpiSize:4
|vpiNet:
\_logic_net: , parent:upper_lower
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.clz_r.upper_lower
|vpiNetType:36
|vpiRange:
\_range: , line:32
|vpiLeftRange:
\_constant: , line:32
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:32
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiRange:
\_range: , line:32
|vpiLeftRange:
\_constant: , line:32
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiRightRange:
\_constant: , line:32
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiModule:
\_module: work@clz (clz_b), file:third_party/cores/taiga/core/div_algorithms/div_quick_radix4.sv, line:70, parent:div_block
|vpiDefName:work@clz
|vpiName:clz_b
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.clz_b
|vpiPort:
\_port: (clz_input), line:25, parent:clz_b
|vpiName:clz_input
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (div.divisor), line:70
|vpiName:div.divisor
|vpiActual:
\_logic_net: (divisor), line:246
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (clz_input), line:25, parent:clz_b
|vpiName:clz_input
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.clz_b.clz_input
|vpiNetType:36
|vpiRange:
\_range: , line:25
|vpiLeftRange:
\_constant: , line:25
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:25
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiPort:
\_port: (clz), line:26, parent:clz_b
|vpiName:clz
|vpiDirection:2
|vpiHighConn:
\_ref_obj: (B_CLZ), line:70
|vpiName:B_CLZ
|vpiActual:
\_logic_net: (B_CLZ), line:55, parent:div_block
|vpiName:B_CLZ
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.B_CLZ
|vpiNetType:36
|vpiRange:
\_range: , line:55
|vpiLeftRange:
\_constant: , line:55
|vpiDecompile:-1
|INT:-1
|vpiRightRange:
\_constant: , line:55
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (clz), line:26, parent:clz_b
|vpiName:clz
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.clz_b.clz
|vpiNetType:36
|vpiRange:
\_range: , line:26
|vpiLeftRange:
\_constant: , line:26
|vpiConstType:7
|vpiDecompile:4
|vpiSize:32
|INT:4
|vpiRightRange:
\_constant: , line:26
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (clz_input), line:25, parent:clz_b
|vpiNet:
\_logic_net: (clz), line:26, parent:clz_b
|vpiNet:
\_logic_net: (sub_clz), line:30, parent:clz_b
|vpiName:sub_clz
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.clz_b.sub_clz
|vpiNetType:36
|vpiRange:
\_range: , line:30
|vpiLeftRange:
\_constant: , line:30
|vpiConstType:7
|vpiDecompile:7
|vpiSize:32
|INT:7
|vpiRightRange:
\_constant: , line:30
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiInstance:
\_module: work@div_quick_radix_4 (div_block), file:third_party/cores/taiga/core/div_algorithms/div_algorithm.sv, line:48, parent:div_core
|vpiArrayNet:
\_array_net: (low_order_clz), line:29, parent:clz_b
|vpiName:low_order_clz
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.clz_b.low_order_clz
|vpiSize:8
|vpiNet:
\_logic_net: , parent:low_order_clz
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.clz_b.low_order_clz
|vpiNetType:36
|vpiRange:
\_range: , line:29
|vpiLeftRange:
\_constant: , line:29
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:29
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiRange:
\_range: , line:29
|vpiLeftRange:
\_constant: , line:29
|vpiConstType:7
|vpiDecompile:7
|vpiSize:32
|INT:7
|vpiRightRange:
\_constant: , line:29
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiArrayNet:
\_array_net: (upper_lower), line:32, parent:clz_b
|vpiName:upper_lower
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.clz_b.upper_lower
|vpiSize:4
|vpiNet:
\_logic_net: , parent:upper_lower
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.clz_b.upper_lower
|vpiNetType:36
|vpiRange:
\_range: , line:32
|vpiLeftRange:
\_constant: , line:32
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:32
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiRange:
\_range: , line:32
|vpiLeftRange:
\_constant: , line:32
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiRightRange:
\_constant: , line:32
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (clk), line:27, parent:div_block
|vpiNet:
\_logic_net: (rst), line:28, parent:div_block
|vpiNet:
\_logic_net: (terminate), line:32, parent:div_block
|vpiName:terminate
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.terminate
|vpiNetType:36
|vpiNet:
\_logic_net: (shift_count), line:33, parent:div_block
|vpiName:shift_count
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.shift_count
|vpiNetType:36
|vpiRange:
\_range: , line:33
|vpiLeftRange:
\_operation: , line:33
|vpiOpType:11
|vpiOperand:
\_operation: , line:33
|vpiOpType:12
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:33
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:33
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiOperand:
\_constant: , line:33
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:33
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (PR), line:35, parent:div_block
|vpiName:PR
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.PR
|vpiNetType:36
|vpiRange:
\_range: , line:35
|vpiLeftRange:
\_operation: , line:35
|vpiOpType:24
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:35
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:35
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:35
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (new_PR_sign), line:36, parent:div_block
|vpiName:new_PR_sign
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.new_PR_sign
|vpiNetType:36
|vpiRange:
\_range: , line:36
|vpiLeftRange:
\_constant: , line:36
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiRightRange:
\_constant: , line:36
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (new_PR_1), line:37, parent:div_block
|vpiName:new_PR_1
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.new_PR_1
|vpiNetType:36
|vpiRange:
\_range: , line:37
|vpiLeftRange:
\_operation: , line:37
|vpiOpType:24
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:37
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:37
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiRightRange:
\_constant: , line:37
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (new_PR_2), line:38, parent:div_block
|vpiName:new_PR_2
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.new_PR_2
|vpiNetType:36
|vpiRange:
\_range: , line:38
|vpiLeftRange:
\_operation: , line:38
|vpiOpType:24
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:38
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:38
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiRightRange:
\_constant: , line:38
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (new_PR_3), line:39, parent:div_block
|vpiName:new_PR_3
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.new_PR_3
|vpiNetType:36
|vpiRange:
\_range: , line:39
|vpiLeftRange:
\_operation: , line:39
|vpiOpType:24
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:39
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:39
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiRightRange:
\_constant: , line:39
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (B_1), line:40, parent:div_block
|vpiName:B_1
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.B_1
|vpiNetType:36
|vpiRange:
\_range: , line:40
|vpiLeftRange:
\_operation: , line:40
|vpiOpType:24
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:40
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:40
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:40
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (B_2), line:41, parent:div_block
|vpiName:B_2
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.B_2
|vpiNetType:36
|vpiRange:
\_range: , line:41
|vpiLeftRange:
\_operation: , line:41
|vpiOpType:24
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:41
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:41
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:41
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (B_3), line:42, parent:div_block
|vpiName:B_3
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.B_3
|vpiNetType:36
|vpiRange:
\_range: , line:42
|vpiLeftRange:
\_operation: , line:42
|vpiOpType:24
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:42
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:42
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:42
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (AR_r), line:44, parent:div_block
|vpiName:AR_r
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.AR_r
|vpiNetType:36
|vpiRange:
\_range: , line:44
|vpiLeftRange:
\_operation: , line:44
|vpiOpType:11
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:44
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:44
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:44
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (Q_temp), line:45, parent:div_block
|vpiName:Q_temp
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.Q_temp
|vpiNetType:36
|vpiRange:
\_range: , line:45
|vpiLeftRange:
\_operation: , line:45
|vpiOpType:11
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:45
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:45
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:45
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (shift_num_R), line:46, parent:div_block
|vpiName:shift_num_R
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.shift_num_R
|vpiNetType:36
|vpiRange:
\_range: , line:46
|vpiLeftRange:
\_constant: , line:46
|vpiConstType:7
|vpiDecompile:5
|vpiSize:32
|INT:5
|vpiRightRange:
\_constant: , line:46
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (shift_num_R_normalized), line:47, parent:div_block
|vpiName:shift_num_R_normalized
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.shift_num_R_normalized
|vpiNetType:36
|vpiRange:
\_range: , line:47
|vpiLeftRange:
\_constant: , line:47
|vpiConstType:7
|vpiDecompile:6
|vpiSize:32
|INT:6
|vpiRightRange:
\_constant: , line:47
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (shift_num_Q), line:48, parent:div_block
|vpiName:shift_num_Q
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.shift_num_Q
|vpiNetType:36
|vpiRange:
\_range: , line:48
|vpiLeftRange:
\_constant: , line:48
|vpiConstType:7
|vpiDecompile:5
|vpiSize:32
|INT:5
|vpiRightRange:
\_constant: , line:48
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (combined), line:49, parent:div_block
|vpiName:combined
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.combined
|vpiNetType:36
|vpiRange:
\_range: , line:49
|vpiLeftRange:
\_operation: , line:49
|vpiOpType:24
|vpiOperand:
\_operation: , line:49
|vpiOpType:25
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:49
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:49
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiOperand:
\_constant: , line:49
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:49
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (combined_normalized), line:50, parent:div_block
|vpiName:combined_normalized
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.combined_normalized
|vpiNetType:36
|vpiRange:
\_range: , line:50
|vpiLeftRange:
\_operation: , line:50
|vpiOpType:24
|vpiOperand:
\_operation: , line:50
|vpiOpType:25
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:50
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:50
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiOperand:
\_constant: , line:50
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:50
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (terminate_early), line:51, parent:div_block
|vpiName:terminate_early
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.terminate_early
|vpiNetType:36
|vpiNet:
\_logic_net: (A_CLZ), line:54, parent:div_block
|vpiNet:
\_logic_net: (B_CLZ), line:55, parent:div_block
|vpiNet:
\_logic_net: (A_CLZ_r), line:56, parent:div_block
|vpiName:A_CLZ_r
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.A_CLZ_r
|vpiNetType:36
|vpiRange:
\_range: , line:56
|vpiLeftRange:
\_constant: , line:56
|vpiDecompile:-1
|INT:-1
|vpiRightRange:
\_constant: , line:56
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (B_CLZ_r), line:57, parent:div_block
|vpiName:B_CLZ_r
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.B_CLZ_r
|vpiNetType:36
|vpiRange:
\_range: , line:57
|vpiLeftRange:
\_constant: , line:57
|vpiDecompile:-1
|INT:-1
|vpiRightRange:
\_constant: , line:57
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (CLZ_delta), line:58, parent:div_block
|vpiName:CLZ_delta
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.CLZ_delta
|vpiNetType:36
|vpiRange:
\_range: , line:58
|vpiLeftRange:
\_constant: , line:58
|vpiDecompile:-1
|INT:-1
|vpiRightRange:
\_constant: , line:58
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (firstCycle), line:60, parent:div_block
|vpiName:firstCycle
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.firstCycle
|vpiNetType:36
|vpiNet:
\_logic_net: (greaterDivisor), line:61, parent:div_block
|vpiName:greaterDivisor
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.greaterDivisor
|vpiNetType:36
|vpiNet:
\_logic_net: (A_shifted), line:62, parent:div_block
|vpiName:A_shifted
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.A_shifted
|vpiNetType:36
|vpiRange:
\_range: , line:62
|vpiLeftRange:
\_operation: , line:62
|vpiOpType:11
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:62
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:62
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:62
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (B_shifted), line:63, parent:div_block
|vpiName:B_shifted
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.B_shifted
|vpiNetType:36
|vpiRange:
\_range: , line:63
|vpiLeftRange:
\_operation: , line:63
|vpiOpType:11
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:63
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:63
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:63
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (R_shifted), line:64, parent:div_block
|vpiName:R_shifted
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.R_shifted
|vpiNetType:36
|vpiRange:
\_range: , line:64
|vpiLeftRange:
\_operation: , line:64
|vpiOpType:11
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:64
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:64
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:64
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (B_shifted_r), line:65, parent:div_block
|vpiName:B_shifted_r
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.B_shifted_r
|vpiNetType:36
|vpiRange:
\_range: , line:65
|vpiLeftRange:
\_operation: , line:65
|vpiOpType:11
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:65
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:65
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:65
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (div), line:29, parent:div_block
|vpiName:div
|vpiFullName:work@div_unit_core_wrapper.div_core.div_block.div
|vpiInstance:
\_module: work@div_algorithm (div_core), file:third_party/cores/taiga/core/div_unit_core_wrapper.sv, line:44, parent:work@div_unit_core_wrapper
|vpiParameter:
\_parameter: (CLZ_W), line:53
|vpiName:CLZ_W
|INT:0
|vpiNet:
\_logic_net: (clk), line:29, parent:div_core
|vpiNet:
\_logic_net: (rst), line:30, parent:div_core
|vpiNet:
\_logic_net: (div), line:31, parent:div_core
|vpiName:div
|vpiFullName:work@div_unit_core_wrapper.div_core.div
|vpiInstance:
\_module: work@div_unit_core_wrapper (work@div_unit_core_wrapper), file:third_party/cores/taiga/core/div_unit_core_wrapper.sv, line:4
|vpiParameter:
\_parameter: (ALU_UNIT_WB_ID), line:190
|vpiName:ALU_UNIT_WB_ID
|INT:32
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (BRANCH_PREDICTOR_WAYS), line:159
|vpiName:BRANCH_PREDICTOR_WAYS
|INT:9
|vpiParameter:
\_parameter: (BRANCH_TABLE_ENTRIES), line:160
|vpiName:BRANCH_TABLE_ENTRIES
|INT:4
|vpiParameter:
\_parameter: (BRANCH_UNIT_ID), line:195
|vpiName:BRANCH_UNIT_ID
|INT:8
|vpiParameter:
\_parameter: (BUS_ADDR_H), line:107
|vpiName:BUS_ADDR_H
|INT:1
|vpiParameter:
\_parameter: (BUS_ADDR_L), line:106
|vpiName:BUS_ADDR_L
|INT:0
|vpiParameter:
\_parameter: (BUS_BIT_CHECK), line:108
|vpiName:BUS_BIT_CHECK
|INT:1
|vpiParameter:
\_parameter: (BUS_TYPE), line:89
|vpiName:BUS_TYPE
|INT:5
|vpiParameter:
\_parameter: (COUNTER_W), line:42
|vpiName:COUNTER_W
|INT:33
|vpiParameter:
\_parameter: (CPU_ID), line:38
|vpiName:CPU_ID
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_ADDR_WIDTH), line:113
|vpiName:C_M_AXI_ADDR_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_DATA_WIDTH), line:114
|vpiName:C_M_AXI_DATA_WIDTH
|INT:1
|vpiParameter:
\_parameter: (DCACHE_LINES), line:133
|vpiName:DCACHE_LINES
|INT:-2146435073
|vpiParameter:
\_parameter: (DCACHE_LINE_ADDR_W), line:135
|vpiName:DCACHE_LINE_ADDR_W
|INT:1073741824
|vpiParameter:
\_parameter: (DCACHE_LINE_W), line:136
|vpiName:DCACHE_LINE_W
|INT:1342177279
|vpiParameter:
\_parameter: (DCACHE_SUB_LINE_ADDR_W), line:137
|vpiName:DCACHE_SUB_LINE_ADDR_W
|INT:4
|vpiParameter:
\_parameter: (DCACHE_TAG_W), line:138
|vpiName:DCACHE_TAG_W
|INT:1610612736
|vpiParameter:
\_parameter: (DCACHE_WAYS), line:134
|vpiName:DCACHE_WAYS
|INT:4
|vpiParameter:
\_parameter: (DIV_ALGORITHM), line:67
|vpiName:DIV_ALGORITHM
|INT:0
|vpiParameter:
\_parameter: (DIV_UNIT_WB_ID), line:192
|vpiName:DIV_UNIT_WB_ID
|INT:2
|vpiParameter:
\_parameter: (DTLB_DEPTH), line:152
|vpiName:DTLB_DEPTH
|INT:512
|vpiParameter:
\_parameter: (DTLB_WAYS), line:151
|vpiName:DTLB_WAYS
|INT:32
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (ENABLE_M_MODE), line:34
|vpiName:ENABLE_M_MODE
|INT:1
|vpiParameter:
\_parameter: (ENABLE_S_MODE), line:36
|vpiName:ENABLE_S_MODE
|INT:0
|vpiParameter:
\_parameter: (ENABLE_TRACE_INTERFACE), line:172
|vpiName:ENABLE_TRACE_INTERFACE
|INT:2
|vpiParameter:
\_parameter: (FETCH_BUFFER_DEPTH), line:168
|vpiName:FETCH_BUFFER_DEPTH
|INT:512
|vpiParameter:
\_parameter: (FPGA_VENDOR), line:44
|vpiName:FPGA_VENDOR
|INT:32
|vpiParameter:
\_parameter: (GC_UNIT_ID), line:196
|vpiName:GC_UNIT_ID
|INT:4
|vpiParameter:
\_parameter: (ICACHE_LINES), line:121
|vpiName:ICACHE_LINES
|INT:2
|vpiParameter:
\_parameter: (ICACHE_LINE_ADDR_W), line:123
|vpiName:ICACHE_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_LINE_W), line:124
|vpiName:ICACHE_LINE_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_SUB_LINE_ADDR_W), line:125
|vpiName:ICACHE_SUB_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_TAG_W), line:126
|vpiName:ICACHE_TAG_W
|INT:-2147483648
|vpiParameter:
\_parameter: (ICACHE_WAYS), line:122
|vpiName:ICACHE_WAYS
|INT:1
|vpiParameter:
\_parameter: (ITLB_DEPTH), line:146
|vpiName:ITLB_DEPTH
|INT:32
|vpiParameter:
\_parameter: (ITLB_WAYS), line:145
|vpiName:ITLB_WAYS
|INT:4
|vpiParameter:
\_parameter: (L1_CONNECTIONS), line:177
|vpiName:L1_CONNECTIONS
|INT:9
|vpiParameter:
\_parameter: (L1_DCACHE_ID), line:178
|vpiName:L1_DCACHE_ID
|INT:4
|vpiParameter:
\_parameter: (L1_DMMU_ID), line:179
|vpiName:L1_DMMU_ID
|INT:2
|vpiParameter:
\_parameter: (L1_ICACHE_ID), line:180
|vpiName:L1_ICACHE_ID
|INT:19
|vpiParameter:
\_parameter: (L1_IMMU_ID), line:181
|vpiName:L1_IMMU_ID
|INT:0
|vpiParameter:
\_parameter: (LS_UNIT_WB_ID), line:191
|vpiName:LS_UNIT_WB_ID
|INT:1
|vpiParameter:
\_parameter: (MAX_INFLIGHT_COUNT), line:167
|vpiName:MAX_INFLIGHT_COUNT
|INT:19
|vpiParameter:
\_parameter: (MEMORY_ADDR_H), line:103
|vpiName:MEMORY_ADDR_H
|INT:12
|vpiParameter:
\_parameter: (MEMORY_ADDR_L), line:102
|vpiName:MEMORY_ADDR_L
|INT:11
|vpiParameter:
\_parameter: (MEMORY_BIT_CHECK), line:104
|vpiName:MEMORY_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (MUL_UNIT_WB_ID), line:193
|vpiName:MUL_UNIT_WB_ID
|INT:512
|vpiParameter:
\_parameter: (NUM_UNITS), line:188
|vpiName:NUM_UNITS
|INT:2
|vpiParameter:
\_parameter: (NUM_WB_UNITS), line:186
|vpiName:NUM_WB_UNITS
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (RAS_DEPTH), line:161
|vpiName:RAS_DEPTH
|INT:2
|vpiParameter:
\_parameter: (RESET_VEC), line:39
|vpiName:RESET_VEC
|INT:-2147483648
|vpiParameter:
\_parameter: (SCRATCH_ADDR_H), line:99
|vpiName:SCRATCH_ADDR_H
|INT:9
|vpiParameter:
\_parameter: (SCRATCH_ADDR_L), line:98
|vpiName:SCRATCH_ADDR_L
|INT:8
|vpiParameter:
\_parameter: (SCRATCH_BIT_CHECK), line:100
|vpiName:SCRATCH_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (USE_AMO), line:70
|vpiName:USE_AMO
|INT:1
|vpiParameter:
\_parameter: (USE_BRANCH_PREDICTOR), line:158
|vpiName:USE_BRANCH_PREDICTOR
|INT:2
|vpiParameter:
\_parameter: (USE_BUS), line:88
|vpiName:USE_BUS
|INT:4
|vpiParameter:
\_parameter: (USE_DCACHE), line:92
|vpiName:USE_DCACHE
|INT:6
|vpiParameter:
\_parameter: (USE_DIV), line:49
|vpiName:USE_DIV
|INT:1
|vpiParameter:
\_parameter: (USE_DTAG_INVALIDATIONS), line:140
|vpiName:USE_DTAG_INVALIDATIONS
|INT:1879048191
|vpiParameter:
\_parameter: (USE_D_SCRATCH_MEM), line:79
|vpiName:USE_D_SCRATCH_MEM
|INT:3
|vpiParameter:
\_parameter: (USE_ICACHE), line:93
|vpiName:USE_ICACHE
|INT:7
|vpiParameter:
\_parameter: (USE_I_SCRATCH_MEM), line:78
|vpiName:USE_I_SCRATCH_MEM
|INT:2
|vpiParameter:
\_parameter: (USE_MUL), line:48
|vpiName:USE_MUL
|INT:1
|vpiParameter:
\_parameter: (WB_UNITS_WIDTH), line:187
|vpiName:WB_UNITS_WIDTH
|INT:32
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiNet:
\_logic_net: (clk), line:8, parent:work@div_unit_core_wrapper
|vpiNet:
\_logic_net: (rst), line:9, parent:work@div_unit_core_wrapper
|vpiNet:
\_logic_net: (start), line:10, parent:work@div_unit_core_wrapper
|vpiNet:
\_logic_net: (ack), line:11, parent:work@div_unit_core_wrapper
|vpiNet:
\_logic_net: (A), line:12, parent:work@div_unit_core_wrapper
|vpiNet:
\_logic_net: (B), line:13, parent:work@div_unit_core_wrapper
|vpiNet:
\_logic_net: (Q), line:14, parent:work@div_unit_core_wrapper
|vpiNet:
\_logic_net: (R), line:15, parent:work@div_unit_core_wrapper
|vpiNet:
\_logic_net: (complete), line:16, parent:work@div_unit_core_wrapper
|vpiNet:
\_logic_net: (B_is_zero), line:17, parent:work@div_unit_core_wrapper
|vpiNet:
\_logic_net: (start_r), line:21, parent:work@div_unit_core_wrapper
|vpiNet:
\_logic_net: (ack_r), line:22, parent:work@div_unit_core_wrapper
|vpiNet:
\_logic_net: (A_r), line:23, parent:work@div_unit_core_wrapper
|vpiNet:
\_logic_net: (B_r), line:24, parent:work@div_unit_core_wrapper
|vpiNet:
\_logic_net: (Q_r), line:25, parent:work@div_unit_core_wrapper
|vpiName:Q_r
|vpiFullName:work@div_unit_core_wrapper.Q_r
|vpiNetType:36
|vpiRange:
\_range: , line:25
|vpiLeftRange:
\_constant: , line:25
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:25
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (R_r), line:26, parent:work@div_unit_core_wrapper
|vpiName:R_r
|vpiFullName:work@div_unit_core_wrapper.R_r
|vpiNetType:36
|vpiRange:
\_range: , line:26
|vpiLeftRange:
\_constant: , line:26
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:26
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (complete_r), line:27, parent:work@div_unit_core_wrapper
|vpiName:complete_r
|vpiFullName:work@div_unit_core_wrapper.complete_r
|vpiNetType:36
|vpiNet:
\_logic_net: (B_is_zero_r), line:28, parent:work@div_unit_core_wrapper
|vpiName:B_is_zero_r
|vpiFullName:work@div_unit_core_wrapper.B_is_zero_r
|vpiNetType:36
|vpiNet:
\_logic_net: (Q_o), line:29, parent:work@div_unit_core_wrapper
|vpiNet:
\_logic_net: (R_o), line:30, parent:work@div_unit_core_wrapper
|vpiNet:
\_logic_net: (complete_o), line:31, parent:work@div_unit_core_wrapper
|vpiNet:
\_logic_net: (B_is_zero_o), line:32, parent:work@div_unit_core_wrapper
|vpiParameter:
\_parameter: (ALU_UNIT_WB_ID), line:190
|vpiName:ALU_UNIT_WB_ID
|INT:32
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (BRANCH_PREDICTOR_WAYS), line:159
|vpiName:BRANCH_PREDICTOR_WAYS
|INT:9
|vpiParameter:
\_parameter: (BRANCH_TABLE_ENTRIES), line:160
|vpiName:BRANCH_TABLE_ENTRIES
|INT:4
|vpiParameter:
\_parameter: (BRANCH_UNIT_ID), line:195
|vpiName:BRANCH_UNIT_ID
|INT:8
|vpiParameter:
\_parameter: (BUS_ADDR_H), line:107
|vpiName:BUS_ADDR_H
|INT:1
|vpiParameter:
\_parameter: (BUS_ADDR_L), line:106
|vpiName:BUS_ADDR_L
|INT:0
|vpiParameter:
\_parameter: (BUS_BIT_CHECK), line:108
|vpiName:BUS_BIT_CHECK
|INT:1
|vpiParameter:
\_parameter: (BUS_TYPE), line:89
|vpiName:BUS_TYPE
|INT:5
|vpiParameter:
\_parameter: (COUNTER_W), line:42
|vpiName:COUNTER_W
|INT:33
|vpiParameter:
\_parameter: (CPU_ID), line:38
|vpiName:CPU_ID
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_ADDR_WIDTH), line:113
|vpiName:C_M_AXI_ADDR_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_DATA_WIDTH), line:114
|vpiName:C_M_AXI_DATA_WIDTH
|INT:1
|vpiParameter:
\_parameter: (C_WIDTH), line:6
|vpiName:C_WIDTH
|INT:32
|vpiParameter:
\_parameter: (DCACHE_LINES), line:133
|vpiName:DCACHE_LINES
|INT:-2146435073
|vpiParameter:
\_parameter: (DCACHE_LINE_ADDR_W), line:135
|vpiName:DCACHE_LINE_ADDR_W
|INT:1073741824
|vpiParameter:
\_parameter: (DCACHE_LINE_W), line:136
|vpiName:DCACHE_LINE_W
|INT:1342177279
|vpiParameter:
\_parameter: (DCACHE_SUB_LINE_ADDR_W), line:137
|vpiName:DCACHE_SUB_LINE_ADDR_W
|INT:4
|vpiParameter:
\_parameter: (DCACHE_TAG_W), line:138
|vpiName:DCACHE_TAG_W
|INT:1610612736
|vpiParameter:
\_parameter: (DCACHE_WAYS), line:134
|vpiName:DCACHE_WAYS
|INT:4
|vpiParameter:
\_parameter: (DIV_ALGORITHM), line:67
|vpiName:DIV_ALGORITHM
|INT:0
|vpiParameter:
\_parameter: (DIV_UNIT_WB_ID), line:192
|vpiName:DIV_UNIT_WB_ID
|INT:2
|vpiParameter:
\_parameter: (DTLB_DEPTH), line:152
|vpiName:DTLB_DEPTH
|INT:512
|vpiParameter:
\_parameter: (DTLB_WAYS), line:151
|vpiName:DTLB_WAYS
|INT:32
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (ENABLE_M_MODE), line:34
|vpiName:ENABLE_M_MODE
|INT:1
|vpiParameter:
\_parameter: (ENABLE_S_MODE), line:36
|vpiName:ENABLE_S_MODE
|INT:0
|vpiParameter:
\_parameter: (ENABLE_TRACE_INTERFACE), line:172
|vpiName:ENABLE_TRACE_INTERFACE
|INT:2
|vpiParameter:
\_parameter: (FETCH_BUFFER_DEPTH), line:168
|vpiName:FETCH_BUFFER_DEPTH
|INT:512
|vpiParameter:
\_parameter: (FPGA_VENDOR), line:27
|vpiName:FPGA_VENDOR
|STRING:"xilinx"
|vpiParameter:
\_parameter: (GC_UNIT_ID), line:196
|vpiName:GC_UNIT_ID
|INT:4
|vpiParameter:
\_parameter: (ICACHE_LINES), line:121
|vpiName:ICACHE_LINES
|INT:2
|vpiParameter:
\_parameter: (ICACHE_LINE_ADDR_W), line:123
|vpiName:ICACHE_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_LINE_W), line:124
|vpiName:ICACHE_LINE_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_SUB_LINE_ADDR_W), line:125
|vpiName:ICACHE_SUB_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_TAG_W), line:126
|vpiName:ICACHE_TAG_W
|INT:-2147483648
|vpiParameter:
\_parameter: (ICACHE_WAYS), line:122
|vpiName:ICACHE_WAYS
|INT:1
|vpiParameter:
\_parameter: (ITLB_DEPTH), line:146
|vpiName:ITLB_DEPTH
|INT:32
|vpiParameter:
\_parameter: (ITLB_WAYS), line:145
|vpiName:ITLB_WAYS
|INT:4
|vpiParameter:
\_parameter: (L1_CONNECTIONS), line:177
|vpiName:L1_CONNECTIONS
|INT:9
|vpiParameter:
\_parameter: (L1_DCACHE_ID), line:178
|vpiName:L1_DCACHE_ID
|INT:4
|vpiParameter:
\_parameter: (L1_DMMU_ID), line:179
|vpiName:L1_DMMU_ID
|INT:2
|vpiParameter:
\_parameter: (L1_ICACHE_ID), line:180
|vpiName:L1_ICACHE_ID
|INT:19
|vpiParameter:
\_parameter: (L1_IMMU_ID), line:181
|vpiName:L1_IMMU_ID
|INT:0
|vpiParameter:
\_parameter: (LS_UNIT_WB_ID), line:191
|vpiName:LS_UNIT_WB_ID
|INT:1
|vpiParameter:
\_parameter: (MAX_INFLIGHT_COUNT), line:167
|vpiName:MAX_INFLIGHT_COUNT
|INT:19
|vpiParameter:
\_parameter: (MEMORY_ADDR_H), line:103
|vpiName:MEMORY_ADDR_H
|INT:12
|vpiParameter:
\_parameter: (MEMORY_ADDR_L), line:102
|vpiName:MEMORY_ADDR_L
|INT:11
|vpiParameter:
\_parameter: (MEMORY_BIT_CHECK), line:104
|vpiName:MEMORY_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (MUL_UNIT_WB_ID), line:193
|vpiName:MUL_UNIT_WB_ID
|INT:512
|vpiParameter:
\_parameter: (NUM_UNITS), line:188
|vpiName:NUM_UNITS
|INT:2
|vpiParameter:
\_parameter: (NUM_WB_UNITS), line:186
|vpiName:NUM_WB_UNITS
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (RAS_DEPTH), line:161
|vpiName:RAS_DEPTH
|INT:2
|vpiParameter:
\_parameter: (RESET_VEC), line:39
|vpiName:RESET_VEC
|INT:-2147483648
|vpiParameter:
\_parameter: (SCRATCH_ADDR_H), line:99
|vpiName:SCRATCH_ADDR_H
|INT:9
|vpiParameter:
\_parameter: (SCRATCH_ADDR_L), line:98
|vpiName:SCRATCH_ADDR_L
|INT:8
|vpiParameter:
\_parameter: (SCRATCH_BIT_CHECK), line:100
|vpiName:SCRATCH_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (USE_AMO), line:70
|vpiName:USE_AMO
|INT:1
|vpiParameter:
\_parameter: (USE_BRANCH_PREDICTOR), line:158
|vpiName:USE_BRANCH_PREDICTOR
|INT:2
|vpiParameter:
\_parameter: (USE_BUS), line:88
|vpiName:USE_BUS
|INT:4
|vpiParameter:
\_parameter: (USE_DCACHE), line:92
|vpiName:USE_DCACHE
|INT:6
|vpiParameter:
\_parameter: (USE_DIV), line:49
|vpiName:USE_DIV
|INT:1
|vpiParameter:
\_parameter: (USE_DTAG_INVALIDATIONS), line:140
|vpiName:USE_DTAG_INVALIDATIONS
|INT:1879048191
|vpiParameter:
\_parameter: (USE_D_SCRATCH_MEM), line:79
|vpiName:USE_D_SCRATCH_MEM
|INT:3
|vpiParameter:
\_parameter: (USE_ICACHE), line:93
|vpiName:USE_ICACHE
|INT:7
|vpiParameter:
\_parameter: (USE_I_SCRATCH_MEM), line:78
|vpiName:USE_I_SCRATCH_MEM
|INT:2
|vpiParameter:
\_parameter: (USE_MUL), line:48
|vpiName:USE_MUL
|INT:1
|vpiParameter:
\_parameter: (WB_UNITS_WIDTH), line:187
|vpiName:WB_UNITS_WIDTH
|INT:32
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|uhdmtopModules:
\_module: work@placer_randomizer (work@placer_randomizer), file:third_party/cores/taiga/core/placer_randomizer.sv, line:1
|vpiDefName:work@placer_randomizer
|vpiName:work@placer_randomizer
|vpiPort:
\_port: (clk), line:5, parent:work@placer_randomizer
|vpiName:clk
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (clk), line:5, parent:work@placer_randomizer
|vpiName:clk
|vpiFullName:work@placer_randomizer.clk
|vpiNetType:36
|vpiPort:
\_port: (samples), line:6, parent:work@placer_randomizer
|vpiName:samples
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (samples), line:6, parent:work@placer_randomizer
|vpiName:samples
|vpiFullName:work@placer_randomizer.samples
|vpiNetType:36
|vpiRange:
\_range: , line:6
|vpiLeftRange:
\_constant: , line:6
|vpiConstType:7
|vpiDecompile:7
|vpiSize:32
|INT:7
|vpiRightRange:
\_constant: , line:6
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiPort:
\_port: (result), line:7, parent:work@placer_randomizer
|vpiName:result
|vpiDirection:2
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (result), line:7, parent:work@placer_randomizer
|vpiName:result
|vpiFullName:work@placer_randomizer.result
|vpiNetType:36
|vpiNet:
\_logic_net: (clk), line:5, parent:work@placer_randomizer
|vpiNet:
\_logic_net: (samples), line:6, parent:work@placer_randomizer
|vpiNet:
\_logic_net: (result), line:7, parent:work@placer_randomizer
|vpiParameter:
\_parameter: (PLACER_SEED), line:2
|vpiName:PLACER_SEED
|INT:43
|uhdmtopModules:
\_module: work@msb (work@msb), file:third_party/cores/taiga/core/msb.sv, line:23
|vpiDefName:work@msb
|vpiName:work@msb
|vpiPort:
\_port: (msb_input), line:25, parent:work@msb
|vpiName:msb_input
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (msb_input), line:25, parent:work@msb
|vpiName:msb_input
|vpiFullName:work@msb.msb_input
|vpiNetType:36
|vpiRange:
\_range: , line:25
|vpiLeftRange:
\_constant: , line:25
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:25
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiPort:
\_port: (msb), line:26, parent:work@msb
|vpiName:msb
|vpiDirection:2
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (msb), line:26, parent:work@msb
|vpiName:msb
|vpiFullName:work@msb.msb
|vpiNetType:36
|vpiRange:
\_range: , line:26
|vpiLeftRange:
\_constant: , line:26
|vpiConstType:7
|vpiDecompile:4
|vpiSize:32
|INT:4
|vpiRightRange:
\_constant: , line:26
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (msb_input), line:25, parent:work@msb
|vpiNet:
\_logic_net: (msb), line:26, parent:work@msb
|vpiNet:
\_logic_net: (sub_sub_msb), line:30, parent:work@msb
|vpiName:sub_sub_msb
|vpiFullName:work@msb.sub_sub_msb
|vpiNetType:36
|vpiRange:
\_range: , line:30
|vpiLeftRange:
\_constant: , line:30
|vpiConstType:7
|vpiDecompile:7
|vpiSize:32
|INT:7
|vpiRightRange:
\_constant: , line:30
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (quadrant), line:31, parent:work@msb
|vpiName:quadrant
|vpiFullName:work@msb.quadrant
|vpiNetType:36
|vpiRange:
\_range: , line:31
|vpiLeftRange:
\_constant: , line:31
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiRightRange:
\_constant: , line:31
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiArrayNet:
\_array_net: (sub_msb), line:29, parent:work@msb
|vpiName:sub_msb
|vpiFullName:work@msb.sub_msb
|vpiSize:4
|vpiNet:
\_logic_net: , parent:sub_msb
|vpiFullName:work@msb.sub_msb
|vpiNetType:36
|vpiRange:
\_range: , line:29
|vpiLeftRange:
\_constant: , line:29
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiRightRange:
\_constant: , line:29
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiRange:
\_range: , line:29
|vpiLeftRange:
\_constant: , line:29
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiRightRange:
\_constant: , line:29
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|uhdmtopModules:
\_module: work@one_hot_occupancy (work@one_hot_occupancy), file:third_party/cores/taiga/core/one_hot_occupancy.sv, line:26
|vpiDefName:work@one_hot_occupancy
|vpiName:work@one_hot_occupancy
|vpiPort:
\_port: (clk), line:28, parent:work@one_hot_occupancy
|vpiName:clk
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (clk), line:28, parent:work@one_hot_occupancy
|vpiName:clk
|vpiFullName:work@one_hot_occupancy.clk
|vpiNetType:36
|vpiPort:
\_port: (rst), line:29, parent:work@one_hot_occupancy
|vpiName:rst
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (rst), line:29, parent:work@one_hot_occupancy
|vpiName:rst
|vpiFullName:work@one_hot_occupancy.rst
|vpiNetType:36
|vpiPort:
\_port: (push), line:30, parent:work@one_hot_occupancy
|vpiName:push
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (push), line:30, parent:work@one_hot_occupancy
|vpiName:push
|vpiFullName:work@one_hot_occupancy.push
|vpiNetType:36
|vpiPort:
\_port: (pop), line:31, parent:work@one_hot_occupancy
|vpiName:pop
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (pop), line:31, parent:work@one_hot_occupancy
|vpiName:pop
|vpiFullName:work@one_hot_occupancy.pop
|vpiNetType:36
|vpiPort:
\_port: (almost_full), line:32, parent:work@one_hot_occupancy
|vpiName:almost_full
|vpiDirection:2
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (almost_full), line:32, parent:work@one_hot_occupancy
|vpiName:almost_full
|vpiFullName:work@one_hot_occupancy.almost_full
|vpiNetType:36
|vpiPort:
\_port: (full), line:33, parent:work@one_hot_occupancy
|vpiName:full
|vpiDirection:2
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (full), line:33, parent:work@one_hot_occupancy
|vpiName:full
|vpiFullName:work@one_hot_occupancy.full
|vpiNetType:36
|vpiPort:
\_port: (empty), line:34, parent:work@one_hot_occupancy
|vpiName:empty
|vpiDirection:2
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (empty), line:34, parent:work@one_hot_occupancy
|vpiName:empty
|vpiFullName:work@one_hot_occupancy.empty
|vpiNetType:36
|vpiPort:
\_port: (almost_empty), line:35, parent:work@one_hot_occupancy
|vpiName:almost_empty
|vpiDirection:2
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (almost_empty), line:35, parent:work@one_hot_occupancy
|vpiName:almost_empty
|vpiFullName:work@one_hot_occupancy.almost_empty
|vpiNetType:36
|vpiPort:
\_port: (valid), line:36, parent:work@one_hot_occupancy
|vpiName:valid
|vpiDirection:2
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (valid), line:36, parent:work@one_hot_occupancy
|vpiName:valid
|vpiFullName:work@one_hot_occupancy.valid
|vpiNetType:36
|vpiNet:
\_logic_net: (clk), line:28, parent:work@one_hot_occupancy
|vpiNet:
\_logic_net: (rst), line:29, parent:work@one_hot_occupancy
|vpiNet:
\_logic_net: (push), line:30, parent:work@one_hot_occupancy
|vpiNet:
\_logic_net: (pop), line:31, parent:work@one_hot_occupancy
|vpiNet:
\_logic_net: (almost_full), line:32, parent:work@one_hot_occupancy
|vpiNet:
\_logic_net: (full), line:33, parent:work@one_hot_occupancy
|vpiNet:
\_logic_net: (empty), line:34, parent:work@one_hot_occupancy
|vpiNet:
\_logic_net: (almost_empty), line:35, parent:work@one_hot_occupancy
|vpiNet:
\_logic_net: (valid), line:36, parent:work@one_hot_occupancy
|vpiNet:
\_logic_net: (valid_chain), line:39, parent:work@one_hot_occupancy
|vpiName:valid_chain
|vpiFullName:work@one_hot_occupancy.valid_chain
|vpiNetType:36
|vpiRange:
\_range: , line:39
|vpiLeftRange:
\_constant: , line:39
|vpiConstType:7
|vpiDecompile:4
|vpiSize:32
|INT:4
|vpiRightRange:
\_constant: , line:39
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiParameter:
\_parameter: (ALU_UNIT_WB_ID), line:190
|vpiName:ALU_UNIT_WB_ID
|INT:32
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (BRANCH_PREDICTOR_WAYS), line:159
|vpiName:BRANCH_PREDICTOR_WAYS
|INT:9
|vpiParameter:
\_parameter: (BRANCH_TABLE_ENTRIES), line:160
|vpiName:BRANCH_TABLE_ENTRIES
|INT:4
|vpiParameter:
\_parameter: (BRANCH_UNIT_ID), line:195
|vpiName:BRANCH_UNIT_ID
|INT:8
|vpiParameter:
\_parameter: (BUS_ADDR_H), line:107
|vpiName:BUS_ADDR_H
|INT:1
|vpiParameter:
\_parameter: (BUS_ADDR_L), line:106
|vpiName:BUS_ADDR_L
|INT:0
|vpiParameter:
\_parameter: (BUS_BIT_CHECK), line:108
|vpiName:BUS_BIT_CHECK
|INT:1
|vpiParameter:
\_parameter: (BUS_TYPE), line:89
|vpiName:BUS_TYPE
|INT:5
|vpiParameter:
\_parameter: (COUNTER_W), line:42
|vpiName:COUNTER_W
|INT:33
|vpiParameter:
\_parameter: (CPU_ID), line:38
|vpiName:CPU_ID
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_ADDR_WIDTH), line:113
|vpiName:C_M_AXI_ADDR_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_DATA_WIDTH), line:114
|vpiName:C_M_AXI_DATA_WIDTH
|INT:1
|vpiParameter:
\_parameter: (DCACHE_LINES), line:133
|vpiName:DCACHE_LINES
|INT:-2146435073
|vpiParameter:
\_parameter: (DCACHE_LINE_ADDR_W), line:135
|vpiName:DCACHE_LINE_ADDR_W
|INT:1073741824
|vpiParameter:
\_parameter: (DCACHE_LINE_W), line:136
|vpiName:DCACHE_LINE_W
|INT:1342177279
|vpiParameter:
\_parameter: (DCACHE_SUB_LINE_ADDR_W), line:137
|vpiName:DCACHE_SUB_LINE_ADDR_W
|INT:4
|vpiParameter:
\_parameter: (DCACHE_TAG_W), line:138
|vpiName:DCACHE_TAG_W
|INT:1610612736
|vpiParameter:
\_parameter: (DCACHE_WAYS), line:134
|vpiName:DCACHE_WAYS
|INT:4
|vpiParameter:
\_parameter: (DEPTH), line:26
|vpiName:DEPTH
|INT:4
|vpiParameter:
\_parameter: (DIV_ALGORITHM), line:67
|vpiName:DIV_ALGORITHM
|INT:0
|vpiParameter:
\_parameter: (DIV_UNIT_WB_ID), line:192
|vpiName:DIV_UNIT_WB_ID
|INT:2
|vpiParameter:
\_parameter: (DTLB_DEPTH), line:152
|vpiName:DTLB_DEPTH
|INT:512
|vpiParameter:
\_parameter: (DTLB_WAYS), line:151
|vpiName:DTLB_WAYS
|INT:32
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (ENABLE_M_MODE), line:34
|vpiName:ENABLE_M_MODE
|INT:1
|vpiParameter:
\_parameter: (ENABLE_S_MODE), line:36
|vpiName:ENABLE_S_MODE
|INT:0
|vpiParameter:
\_parameter: (ENABLE_TRACE_INTERFACE), line:172
|vpiName:ENABLE_TRACE_INTERFACE
|INT:2
|vpiParameter:
\_parameter: (FETCH_BUFFER_DEPTH), line:168
|vpiName:FETCH_BUFFER_DEPTH
|INT:512
|vpiParameter:
\_parameter: (FPGA_VENDOR), line:27
|vpiName:FPGA_VENDOR
|STRING:"xilinx"
|vpiParameter:
\_parameter: (GC_UNIT_ID), line:196
|vpiName:GC_UNIT_ID
|INT:4
|vpiParameter:
\_parameter: (ICACHE_LINES), line:121
|vpiName:ICACHE_LINES
|INT:2
|vpiParameter:
\_parameter: (ICACHE_LINE_ADDR_W), line:123
|vpiName:ICACHE_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_LINE_W), line:124
|vpiName:ICACHE_LINE_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_SUB_LINE_ADDR_W), line:125
|vpiName:ICACHE_SUB_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_TAG_W), line:126
|vpiName:ICACHE_TAG_W
|INT:-2147483648
|vpiParameter:
\_parameter: (ICACHE_WAYS), line:122
|vpiName:ICACHE_WAYS
|INT:1
|vpiParameter:
\_parameter: (ITLB_DEPTH), line:146
|vpiName:ITLB_DEPTH
|INT:32
|vpiParameter:
\_parameter: (ITLB_WAYS), line:145
|vpiName:ITLB_WAYS
|INT:4
|vpiParameter:
\_parameter: (L1_CONNECTIONS), line:177
|vpiName:L1_CONNECTIONS
|INT:9
|vpiParameter:
\_parameter: (L1_DCACHE_ID), line:178
|vpiName:L1_DCACHE_ID
|INT:4
|vpiParameter:
\_parameter: (L1_DMMU_ID), line:179
|vpiName:L1_DMMU_ID
|INT:2
|vpiParameter:
\_parameter: (L1_ICACHE_ID), line:180
|vpiName:L1_ICACHE_ID
|INT:19
|vpiParameter:
\_parameter: (L1_IMMU_ID), line:181
|vpiName:L1_IMMU_ID
|INT:0
|vpiParameter:
\_parameter: (LS_UNIT_WB_ID), line:191
|vpiName:LS_UNIT_WB_ID
|INT:1
|vpiParameter:
\_parameter: (MAX_INFLIGHT_COUNT), line:167
|vpiName:MAX_INFLIGHT_COUNT
|INT:19
|vpiParameter:
\_parameter: (MEMORY_ADDR_H), line:103
|vpiName:MEMORY_ADDR_H
|INT:12
|vpiParameter:
\_parameter: (MEMORY_ADDR_L), line:102
|vpiName:MEMORY_ADDR_L
|INT:11
|vpiParameter:
\_parameter: (MEMORY_BIT_CHECK), line:104
|vpiName:MEMORY_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (MUL_UNIT_WB_ID), line:193
|vpiName:MUL_UNIT_WB_ID
|INT:512
|vpiParameter:
\_parameter: (NUM_UNITS), line:188
|vpiName:NUM_UNITS
|INT:2
|vpiParameter:
\_parameter: (NUM_WB_UNITS), line:186
|vpiName:NUM_WB_UNITS
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (RAS_DEPTH), line:161
|vpiName:RAS_DEPTH
|INT:2
|vpiParameter:
\_parameter: (RESET_VEC), line:39
|vpiName:RESET_VEC
|INT:-2147483648
|vpiParameter:
\_parameter: (SCRATCH_ADDR_H), line:99
|vpiName:SCRATCH_ADDR_H
|INT:9
|vpiParameter:
\_parameter: (SCRATCH_ADDR_L), line:98
|vpiName:SCRATCH_ADDR_L
|INT:8
|vpiParameter:
\_parameter: (SCRATCH_BIT_CHECK), line:100
|vpiName:SCRATCH_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (USE_AMO), line:70
|vpiName:USE_AMO
|INT:1
|vpiParameter:
\_parameter: (USE_BRANCH_PREDICTOR), line:158
|vpiName:USE_BRANCH_PREDICTOR
|INT:2
|vpiParameter:
\_parameter: (USE_BUS), line:88
|vpiName:USE_BUS
|INT:4
|vpiParameter:
\_parameter: (USE_DCACHE), line:92
|vpiName:USE_DCACHE
|INT:6
|vpiParameter:
\_parameter: (USE_DIV), line:49
|vpiName:USE_DIV
|INT:1
|vpiParameter:
\_parameter: (USE_DTAG_INVALIDATIONS), line:140
|vpiName:USE_DTAG_INVALIDATIONS
|INT:1879048191
|vpiParameter:
\_parameter: (USE_D_SCRATCH_MEM), line:79
|vpiName:USE_D_SCRATCH_MEM
|INT:3
|vpiParameter:
\_parameter: (USE_ICACHE), line:93
|vpiName:USE_ICACHE
|INT:7
|vpiParameter:
\_parameter: (USE_I_SCRATCH_MEM), line:78
|vpiName:USE_I_SCRATCH_MEM
|INT:2
|vpiParameter:
\_parameter: (USE_MUL), line:48
|vpiName:USE_MUL
|INT:1
|vpiParameter:
\_parameter: (WB_UNITS_WIDTH), line:187
|vpiName:WB_UNITS_WIDTH
|INT:32
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|uhdmtopModules:
\_module: work@binary_occupancy (work@binary_occupancy), file:third_party/cores/taiga/core/binary_occupancy.sv, line:26
|vpiDefName:work@binary_occupancy
|vpiName:work@binary_occupancy
|vpiPort:
\_port: (clk), line:28, parent:work@binary_occupancy
|vpiName:clk
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (clk), line:28, parent:work@binary_occupancy
|vpiName:clk
|vpiFullName:work@binary_occupancy.clk
|vpiNetType:36
|vpiPort:
\_port: (rst), line:29, parent:work@binary_occupancy
|vpiName:rst
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (rst), line:29, parent:work@binary_occupancy
|vpiName:rst
|vpiFullName:work@binary_occupancy.rst
|vpiNetType:36
|vpiPort:
\_port: (push), line:30, parent:work@binary_occupancy
|vpiName:push
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (push), line:30, parent:work@binary_occupancy
|vpiName:push
|vpiFullName:work@binary_occupancy.push
|vpiNetType:36
|vpiPort:
\_port: (pop), line:31, parent:work@binary_occupancy
|vpiName:pop
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (pop), line:31, parent:work@binary_occupancy
|vpiName:pop
|vpiFullName:work@binary_occupancy.pop
|vpiNetType:36
|vpiPort:
\_port: (almost_full), line:32, parent:work@binary_occupancy
|vpiName:almost_full
|vpiDirection:2
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (almost_full), line:32, parent:work@binary_occupancy
|vpiName:almost_full
|vpiFullName:work@binary_occupancy.almost_full
|vpiNetType:36
|vpiPort:
\_port: (full), line:33, parent:work@binary_occupancy
|vpiName:full
|vpiDirection:2
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (full), line:33, parent:work@binary_occupancy
|vpiName:full
|vpiFullName:work@binary_occupancy.full
|vpiNetType:36
|vpiPort:
\_port: (empty), line:34, parent:work@binary_occupancy
|vpiName:empty
|vpiDirection:2
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (empty), line:34, parent:work@binary_occupancy
|vpiName:empty
|vpiFullName:work@binary_occupancy.empty
|vpiNetType:36
|vpiPort:
\_port: (almost_empty), line:35, parent:work@binary_occupancy
|vpiName:almost_empty
|vpiDirection:2
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (almost_empty), line:35, parent:work@binary_occupancy
|vpiName:almost_empty
|vpiFullName:work@binary_occupancy.almost_empty
|vpiNetType:36
|vpiPort:
\_port: (valid), line:36, parent:work@binary_occupancy
|vpiName:valid
|vpiDirection:2
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (valid), line:36, parent:work@binary_occupancy
|vpiName:valid
|vpiFullName:work@binary_occupancy.valid
|vpiNetType:36
|vpiNet:
\_logic_net: (clk), line:28, parent:work@binary_occupancy
|vpiNet:
\_logic_net: (rst), line:29, parent:work@binary_occupancy
|vpiNet:
\_logic_net: (push), line:30, parent:work@binary_occupancy
|vpiNet:
\_logic_net: (pop), line:31, parent:work@binary_occupancy
|vpiNet:
\_logic_net: (almost_full), line:32, parent:work@binary_occupancy
|vpiNet:
\_logic_net: (full), line:33, parent:work@binary_occupancy
|vpiNet:
\_logic_net: (empty), line:34, parent:work@binary_occupancy
|vpiNet:
\_logic_net: (almost_empty), line:35, parent:work@binary_occupancy
|vpiNet:
\_logic_net: (valid), line:36, parent:work@binary_occupancy
|vpiNet:
\_logic_net: (count), line:39, parent:work@binary_occupancy
|vpiName:count
|vpiFullName:work@binary_occupancy.count
|vpiNetType:36
|vpiRange:
\_range: , line:39
|vpiLeftRange:
\_constant: , line:39
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:39
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiParameter:
\_parameter: (ALU_UNIT_WB_ID), line:190
|vpiName:ALU_UNIT_WB_ID
|INT:32
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (BRANCH_PREDICTOR_WAYS), line:159
|vpiName:BRANCH_PREDICTOR_WAYS
|INT:9
|vpiParameter:
\_parameter: (BRANCH_TABLE_ENTRIES), line:160
|vpiName:BRANCH_TABLE_ENTRIES
|INT:4
|vpiParameter:
\_parameter: (BRANCH_UNIT_ID), line:195
|vpiName:BRANCH_UNIT_ID
|INT:8
|vpiParameter:
\_parameter: (BUS_ADDR_H), line:107
|vpiName:BUS_ADDR_H
|INT:1
|vpiParameter:
\_parameter: (BUS_ADDR_L), line:106
|vpiName:BUS_ADDR_L
|INT:0
|vpiParameter:
\_parameter: (BUS_BIT_CHECK), line:108
|vpiName:BUS_BIT_CHECK
|INT:1
|vpiParameter:
\_parameter: (BUS_TYPE), line:89
|vpiName:BUS_TYPE
|INT:5
|vpiParameter:
\_parameter: (COUNTER_W), line:42
|vpiName:COUNTER_W
|INT:33
|vpiParameter:
\_parameter: (CPU_ID), line:38
|vpiName:CPU_ID
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_ADDR_WIDTH), line:113
|vpiName:C_M_AXI_ADDR_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_DATA_WIDTH), line:114
|vpiName:C_M_AXI_DATA_WIDTH
|INT:1
|vpiParameter:
\_parameter: (DCACHE_LINES), line:133
|vpiName:DCACHE_LINES
|INT:-2146435073
|vpiParameter:
\_parameter: (DCACHE_LINE_ADDR_W), line:135
|vpiName:DCACHE_LINE_ADDR_W
|INT:1073741824
|vpiParameter:
\_parameter: (DCACHE_LINE_W), line:136
|vpiName:DCACHE_LINE_W
|INT:1342177279
|vpiParameter:
\_parameter: (DCACHE_SUB_LINE_ADDR_W), line:137
|vpiName:DCACHE_SUB_LINE_ADDR_W
|INT:4
|vpiParameter:
\_parameter: (DCACHE_TAG_W), line:138
|vpiName:DCACHE_TAG_W
|INT:1610612736
|vpiParameter:
\_parameter: (DCACHE_WAYS), line:134
|vpiName:DCACHE_WAYS
|INT:4
|vpiParameter:
\_parameter: (DEPTH), line:26
|vpiName:DEPTH
|INT:4
|vpiParameter:
\_parameter: (DIV_ALGORITHM), line:67
|vpiName:DIV_ALGORITHM
|INT:0
|vpiParameter:
\_parameter: (DIV_UNIT_WB_ID), line:192
|vpiName:DIV_UNIT_WB_ID
|INT:2
|vpiParameter:
\_parameter: (DTLB_DEPTH), line:152
|vpiName:DTLB_DEPTH
|INT:512
|vpiParameter:
\_parameter: (DTLB_WAYS), line:151
|vpiName:DTLB_WAYS
|INT:32
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (ENABLE_M_MODE), line:34
|vpiName:ENABLE_M_MODE
|INT:1
|vpiParameter:
\_parameter: (ENABLE_S_MODE), line:36
|vpiName:ENABLE_S_MODE
|INT:0
|vpiParameter:
\_parameter: (ENABLE_TRACE_INTERFACE), line:172
|vpiName:ENABLE_TRACE_INTERFACE
|INT:2
|vpiParameter:
\_parameter: (FETCH_BUFFER_DEPTH), line:168
|vpiName:FETCH_BUFFER_DEPTH
|INT:512
|vpiParameter:
\_parameter: (FPGA_VENDOR), line:27
|vpiName:FPGA_VENDOR
|STRING:"xilinx"
|vpiParameter:
\_parameter: (GC_UNIT_ID), line:196
|vpiName:GC_UNIT_ID
|INT:4
|vpiParameter:
\_parameter: (ICACHE_LINES), line:121
|vpiName:ICACHE_LINES
|INT:2
|vpiParameter:
\_parameter: (ICACHE_LINE_ADDR_W), line:123
|vpiName:ICACHE_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_LINE_W), line:124
|vpiName:ICACHE_LINE_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_SUB_LINE_ADDR_W), line:125
|vpiName:ICACHE_SUB_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_TAG_W), line:126
|vpiName:ICACHE_TAG_W
|INT:-2147483648
|vpiParameter:
\_parameter: (ICACHE_WAYS), line:122
|vpiName:ICACHE_WAYS
|INT:1
|vpiParameter:
\_parameter: (ITLB_DEPTH), line:146
|vpiName:ITLB_DEPTH
|INT:32
|vpiParameter:
\_parameter: (ITLB_WAYS), line:145
|vpiName:ITLB_WAYS
|INT:4
|vpiParameter:
\_parameter: (L1_CONNECTIONS), line:177
|vpiName:L1_CONNECTIONS
|INT:9
|vpiParameter:
\_parameter: (L1_DCACHE_ID), line:178
|vpiName:L1_DCACHE_ID
|INT:4
|vpiParameter:
\_parameter: (L1_DMMU_ID), line:179
|vpiName:L1_DMMU_ID
|INT:2
|vpiParameter:
\_parameter: (L1_ICACHE_ID), line:180
|vpiName:L1_ICACHE_ID
|INT:19
|vpiParameter:
\_parameter: (L1_IMMU_ID), line:181
|vpiName:L1_IMMU_ID
|INT:0
|vpiParameter:
\_parameter: (LS_UNIT_WB_ID), line:191
|vpiName:LS_UNIT_WB_ID
|INT:1
|vpiParameter:
\_parameter: (MAX_INFLIGHT_COUNT), line:167
|vpiName:MAX_INFLIGHT_COUNT
|INT:19
|vpiParameter:
\_parameter: (MEMORY_ADDR_H), line:103
|vpiName:MEMORY_ADDR_H
|INT:12
|vpiParameter:
\_parameter: (MEMORY_ADDR_L), line:102
|vpiName:MEMORY_ADDR_L
|INT:11
|vpiParameter:
\_parameter: (MEMORY_BIT_CHECK), line:104
|vpiName:MEMORY_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (MUL_UNIT_WB_ID), line:193
|vpiName:MUL_UNIT_WB_ID
|INT:512
|vpiParameter:
\_parameter: (NUM_UNITS), line:188
|vpiName:NUM_UNITS
|INT:2
|vpiParameter:
\_parameter: (NUM_WB_UNITS), line:186
|vpiName:NUM_WB_UNITS
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (RAS_DEPTH), line:161
|vpiName:RAS_DEPTH
|INT:2
|vpiParameter:
\_parameter: (RESET_VEC), line:39
|vpiName:RESET_VEC
|INT:-2147483648
|vpiParameter:
\_parameter: (SCRATCH_ADDR_H), line:99
|vpiName:SCRATCH_ADDR_H
|INT:9
|vpiParameter:
\_parameter: (SCRATCH_ADDR_L), line:98
|vpiName:SCRATCH_ADDR_L
|INT:8
|vpiParameter:
\_parameter: (SCRATCH_BIT_CHECK), line:100
|vpiName:SCRATCH_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (USE_AMO), line:70
|vpiName:USE_AMO
|INT:1
|vpiParameter:
\_parameter: (USE_BRANCH_PREDICTOR), line:158
|vpiName:USE_BRANCH_PREDICTOR
|INT:2
|vpiParameter:
\_parameter: (USE_BUS), line:88
|vpiName:USE_BUS
|INT:4
|vpiParameter:
\_parameter: (USE_DCACHE), line:92
|vpiName:USE_DCACHE
|INT:6
|vpiParameter:
\_parameter: (USE_DIV), line:49
|vpiName:USE_DIV
|INT:1
|vpiParameter:
\_parameter: (USE_DTAG_INVALIDATIONS), line:140
|vpiName:USE_DTAG_INVALIDATIONS
|INT:1879048191
|vpiParameter:
\_parameter: (USE_D_SCRATCH_MEM), line:79
|vpiName:USE_D_SCRATCH_MEM
|INT:3
|vpiParameter:
\_parameter: (USE_ICACHE), line:93
|vpiName:USE_ICACHE
|INT:7
|vpiParameter:
\_parameter: (USE_I_SCRATCH_MEM), line:78
|vpiName:USE_I_SCRATCH_MEM
|INT:2
|vpiParameter:
\_parameter: (USE_MUL), line:48
|vpiName:USE_MUL
|INT:1
|vpiParameter:
\_parameter: (WB_UNITS_WIDTH), line:187
|vpiName:WB_UNITS_WIDTH
|INT:32
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|uhdmtopModules:
\_module: work@mstatus_priv_reg (work@mstatus_priv_reg), file:third_party/cores/taiga/core/mstatus_priv_reg.sv, line:27
|vpiDefName:work@mstatus_priv_reg
|vpiName:work@mstatus_priv_reg
|vpiPort:
\_port: (clk), line:28, parent:work@mstatus_priv_reg
|vpiName:clk
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (clk), line:28, parent:work@mstatus_priv_reg
|vpiName:clk
|vpiFullName:work@mstatus_priv_reg.clk
|vpiNetType:36
|vpiPort:
\_port: (rst), line:29, parent:work@mstatus_priv_reg
|vpiName:rst
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (rst), line:29, parent:work@mstatus_priv_reg
|vpiName:rst
|vpiFullName:work@mstatus_priv_reg.rst
|vpiNetType:36
|vpiPort:
\_port: (exception), line:31, parent:work@mstatus_priv_reg
|vpiName:exception
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (exception), line:31, parent:work@mstatus_priv_reg
|vpiName:exception
|vpiFullName:work@mstatus_priv_reg.exception
|vpiNetType:36
|vpiPort:
\_port: (interrupt), line:32, parent:work@mstatus_priv_reg
|vpiName:interrupt
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (interrupt), line:32, parent:work@mstatus_priv_reg
|vpiName:interrupt
|vpiFullName:work@mstatus_priv_reg.interrupt
|vpiNetType:36
|vpiPort:
\_port: (mret), line:33, parent:work@mstatus_priv_reg
|vpiName:mret
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (mret), line:33, parent:work@mstatus_priv_reg
|vpiName:mret
|vpiFullName:work@mstatus_priv_reg.mret
|vpiNetType:36
|vpiPort:
\_port: (sret), line:34, parent:work@mstatus_priv_reg
|vpiName:sret
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (sret), line:34, parent:work@mstatus_priv_reg
|vpiName:sret
|vpiFullName:work@mstatus_priv_reg.sret
|vpiNetType:36
|vpiPort:
\_port: (write_msr_m), line:35, parent:work@mstatus_priv_reg
|vpiName:write_msr_m
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (write_msr_m), line:35, parent:work@mstatus_priv_reg
|vpiName:write_msr_m
|vpiFullName:work@mstatus_priv_reg.write_msr_m
|vpiNetType:36
|vpiPort:
\_port: (write_msr_s), line:36, parent:work@mstatus_priv_reg
|vpiName:write_msr_s
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (write_msr_s), line:36, parent:work@mstatus_priv_reg
|vpiName:write_msr_s
|vpiFullName:work@mstatus_priv_reg.write_msr_s
|vpiNetType:36
|vpiPort:
\_port: (updated_csr), line:37, parent:work@mstatus_priv_reg
|vpiName:updated_csr
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (updated_csr), line:37, parent:work@mstatus_priv_reg
|vpiName:updated_csr
|vpiFullName:work@mstatus_priv_reg.updated_csr
|vpiNetType:36
|vpiRange:
\_range: , line:37
|vpiLeftRange:
\_constant: , line:37
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiRightRange:
\_constant: , line:37
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiPort:
\_port: (interrupt_delegated), line:38, parent:work@mstatus_priv_reg
|vpiName:interrupt_delegated
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (interrupt_delegated), line:38, parent:work@mstatus_priv_reg
|vpiName:interrupt_delegated
|vpiFullName:work@mstatus_priv_reg.interrupt_delegated
|vpiNetType:36
|vpiPort:
\_port: (exception_delegated), line:39, parent:work@mstatus_priv_reg
|vpiName:exception_delegated
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (exception_delegated), line:39, parent:work@mstatus_priv_reg
|vpiName:exception_delegated
|vpiFullName:work@mstatus_priv_reg.exception_delegated
|vpiNetType:36
|vpiPort:
\_port: (privilege_level), line:40, parent:work@mstatus_priv_reg
|vpiName:privilege_level
|vpiDirection:2
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (privilege_level), line:40, parent:work@mstatus_priv_reg
|vpiName:privilege_level
|vpiFullName:work@mstatus_priv_reg.privilege_level
|vpiNetType:36
|vpiRange:
\_range: , line:40
|vpiLeftRange:
\_constant: , line:40
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:40
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiPort:
\_port: (next_privilege_level), line:41, parent:work@mstatus_priv_reg
|vpiName:next_privilege_level
|vpiDirection:2
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (next_privilege_level), line:41, parent:work@mstatus_priv_reg
|vpiName:next_privilege_level
|vpiFullName:work@mstatus_priv_reg.next_privilege_level
|vpiNetType:36
|vpiRange:
\_range: , line:41
|vpiLeftRange:
\_constant: , line:41
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:41
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiPort:
\_port: (mstatus), line:43, parent:work@mstatus_priv_reg
|vpiName:mstatus
|vpiDirection:2
|vpiTypedef:
\_struct_typespec: (mstatus_t), line:78
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (mstatus), line:43, parent:work@mstatus_priv_reg
|vpiName:mstatus
|vpiFullName:work@mstatus_priv_reg.mstatus
|vpiPort:
\_port: (mstatus_smask), line:44, parent:work@mstatus_priv_reg
|vpiName:mstatus_smask
|vpiDirection:2
|vpiTypedef:
\_struct_typespec: (mstatus_t), line:78
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (mstatus_smask), line:44, parent:work@mstatus_priv_reg
|vpiName:mstatus_smask
|vpiFullName:work@mstatus_priv_reg.mstatus_smask
|vpiNet:
\_logic_net: (clk), line:28, parent:work@mstatus_priv_reg
|vpiNet:
\_logic_net: (rst), line:29, parent:work@mstatus_priv_reg
|vpiNet:
\_logic_net: (exception), line:31, parent:work@mstatus_priv_reg
|vpiNet:
\_logic_net: (interrupt), line:32, parent:work@mstatus_priv_reg
|vpiNet:
\_logic_net: (mret), line:33, parent:work@mstatus_priv_reg
|vpiNet:
\_logic_net: (sret), line:34, parent:work@mstatus_priv_reg
|vpiNet:
\_logic_net: (write_msr_m), line:35, parent:work@mstatus_priv_reg
|vpiNet:
\_logic_net: (write_msr_s), line:36, parent:work@mstatus_priv_reg
|vpiNet:
\_logic_net: (updated_csr), line:37, parent:work@mstatus_priv_reg
|vpiNet:
\_logic_net: (interrupt_delegated), line:38, parent:work@mstatus_priv_reg
|vpiNet:
\_logic_net: (exception_delegated), line:39, parent:work@mstatus_priv_reg
|vpiNet:
\_logic_net: (privilege_level), line:40, parent:work@mstatus_priv_reg
|vpiNet:
\_logic_net: (next_privilege_level), line:41, parent:work@mstatus_priv_reg
|vpiNet:
\_logic_net: (mstatus), line:43, parent:work@mstatus_priv_reg
|vpiNet:
\_logic_net: (mstatus_smask), line:44, parent:work@mstatus_priv_reg
|vpiNet:
\_logic_net: (trap_return_privilege_level), line:47, parent:work@mstatus_priv_reg
|vpiName:trap_return_privilege_level
|vpiFullName:work@mstatus_priv_reg.trap_return_privilege_level
|vpiNetType:36
|vpiRange:
\_range: , line:47
|vpiLeftRange:
\_constant: , line:47
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:47
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (exception_privilege_level), line:47, parent:work@mstatus_priv_reg
|vpiName:exception_privilege_level
|vpiFullName:work@mstatus_priv_reg.exception_privilege_level
|vpiNetType:36
|vpiRange:
\_range: , line:47
|vpiLeftRange:
\_constant: , line:47
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:47
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (interrupt_privilege_level), line:47, parent:work@mstatus_priv_reg
|vpiName:interrupt_privilege_level
|vpiFullName:work@mstatus_priv_reg.interrupt_privilege_level
|vpiNetType:36
|vpiRange:
\_range: , line:47
|vpiLeftRange:
\_constant: , line:47
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:47
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiVariables:
\_struct_var: (mstatus_exception), line:48, parent:work@mstatus_priv_reg
|vpiName:mstatus_exception
|vpiFullName:work@mstatus_priv_reg.mstatus_exception
|vpiTypespec:
\_struct_typespec: (mstatus_t), line:78
|vpiVariables:
\_struct_var: (mstatus_return), line:48, parent:work@mstatus_priv_reg
|vpiName:mstatus_return
|vpiFullName:work@mstatus_priv_reg.mstatus_return
|vpiTypespec:
\_struct_typespec: (mstatus_t), line:78
|vpiVariables:
\_struct_var: (mstatus_rst), line:48, parent:work@mstatus_priv_reg
|vpiName:mstatus_rst
|vpiFullName:work@mstatus_priv_reg.mstatus_rst
|vpiTypespec:
\_struct_typespec: (mstatus_t), line:78
|vpiVariables:
\_struct_var: (mstatus_new), line:48, parent:work@mstatus_priv_reg
|vpiName:mstatus_new
|vpiFullName:work@mstatus_priv_reg.mstatus_new
|vpiTypespec:
\_struct_typespec: (mstatus_t), line:78
|vpiVariables:
\_struct_var: (mstatus_mmask), line:49, parent:work@mstatus_priv_reg
|vpiName:mstatus_mmask
|vpiFullName:work@mstatus_priv_reg.mstatus_mmask
|vpiTypespec:
\_struct_typespec: (mstatus_t), line:78
|vpiVariables:
\_struct_var: (mstatus_mask), line:49, parent:work@mstatus_priv_reg
|vpiName:mstatus_mask
|vpiFullName:work@mstatus_priv_reg.mstatus_mask
|vpiTypespec:
\_struct_typespec: (mstatus_t), line:78
|vpiParameter:
\_parameter: (ALU_UNIT_WB_ID), line:190
|vpiName:ALU_UNIT_WB_ID
|INT:32
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (BRANCH_PREDICTOR_WAYS), line:159
|vpiName:BRANCH_PREDICTOR_WAYS
|INT:9
|vpiParameter:
\_parameter: (BRANCH_TABLE_ENTRIES), line:160
|vpiName:BRANCH_TABLE_ENTRIES
|INT:4
|vpiParameter:
\_parameter: (BRANCH_UNIT_ID), line:195
|vpiName:BRANCH_UNIT_ID
|INT:8
|vpiParameter:
\_parameter: (BUS_ADDR_H), line:107
|vpiName:BUS_ADDR_H
|INT:1
|vpiParameter:
\_parameter: (BUS_ADDR_L), line:106
|vpiName:BUS_ADDR_L
|INT:0
|vpiParameter:
\_parameter: (BUS_BIT_CHECK), line:108
|vpiName:BUS_BIT_CHECK
|INT:1
|vpiParameter:
\_parameter: (BUS_TYPE), line:89
|vpiName:BUS_TYPE
|INT:5
|vpiParameter:
\_parameter: (COUNTER_W), line:42
|vpiName:COUNTER_W
|INT:33
|vpiParameter:
\_parameter: (CPU_ID), line:38
|vpiName:CPU_ID
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_ADDR_WIDTH), line:113
|vpiName:C_M_AXI_ADDR_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_DATA_WIDTH), line:114
|vpiName:C_M_AXI_DATA_WIDTH
|INT:1
|vpiParameter:
\_parameter: (DCACHE_LINES), line:133
|vpiName:DCACHE_LINES
|INT:-2146435073
|vpiParameter:
\_parameter: (DCACHE_LINE_ADDR_W), line:135
|vpiName:DCACHE_LINE_ADDR_W
|INT:1073741824
|vpiParameter:
\_parameter: (DCACHE_LINE_W), line:136
|vpiName:DCACHE_LINE_W
|INT:1342177279
|vpiParameter:
\_parameter: (DCACHE_SUB_LINE_ADDR_W), line:137
|vpiName:DCACHE_SUB_LINE_ADDR_W
|INT:4
|vpiParameter:
\_parameter: (DCACHE_TAG_W), line:138
|vpiName:DCACHE_TAG_W
|INT:1610612736
|vpiParameter:
\_parameter: (DCACHE_WAYS), line:134
|vpiName:DCACHE_WAYS
|INT:4
|vpiParameter:
\_parameter: (DIV_ALGORITHM), line:67
|vpiName:DIV_ALGORITHM
|INT:0
|vpiParameter:
\_parameter: (DIV_UNIT_WB_ID), line:192
|vpiName:DIV_UNIT_WB_ID
|INT:2
|vpiParameter:
\_parameter: (DTLB_DEPTH), line:152
|vpiName:DTLB_DEPTH
|INT:512
|vpiParameter:
\_parameter: (DTLB_WAYS), line:151
|vpiName:DTLB_WAYS
|INT:32
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (ENABLE_M_MODE), line:34
|vpiName:ENABLE_M_MODE
|INT:1
|vpiParameter:
\_parameter: (ENABLE_S_MODE), line:36
|vpiName:ENABLE_S_MODE
|INT:0
|vpiParameter:
\_parameter: (ENABLE_TRACE_INTERFACE), line:172
|vpiName:ENABLE_TRACE_INTERFACE
|INT:2
|vpiParameter:
\_parameter: (FETCH_BUFFER_DEPTH), line:168
|vpiName:FETCH_BUFFER_DEPTH
|INT:512
|vpiParameter:
\_parameter: (FPGA_VENDOR), line:27
|vpiName:FPGA_VENDOR
|STRING:"xilinx"
|vpiParameter:
\_parameter: (GC_UNIT_ID), line:196
|vpiName:GC_UNIT_ID
|INT:4
|vpiParameter:
\_parameter: (ICACHE_LINES), line:121
|vpiName:ICACHE_LINES
|INT:2
|vpiParameter:
\_parameter: (ICACHE_LINE_ADDR_W), line:123
|vpiName:ICACHE_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_LINE_W), line:124
|vpiName:ICACHE_LINE_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_SUB_LINE_ADDR_W), line:125
|vpiName:ICACHE_SUB_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_TAG_W), line:126
|vpiName:ICACHE_TAG_W
|INT:-2147483648
|vpiParameter:
\_parameter: (ICACHE_WAYS), line:122
|vpiName:ICACHE_WAYS
|INT:1
|vpiParameter:
\_parameter: (ITLB_DEPTH), line:146
|vpiName:ITLB_DEPTH
|INT:32
|vpiParameter:
\_parameter: (ITLB_WAYS), line:145
|vpiName:ITLB_WAYS
|INT:4
|vpiParameter:
\_parameter: (L1_CONNECTIONS), line:177
|vpiName:L1_CONNECTIONS
|INT:9
|vpiParameter:
\_parameter: (L1_DCACHE_ID), line:178
|vpiName:L1_DCACHE_ID
|INT:4
|vpiParameter:
\_parameter: (L1_DMMU_ID), line:179
|vpiName:L1_DMMU_ID
|INT:2
|vpiParameter:
\_parameter: (L1_ICACHE_ID), line:180
|vpiName:L1_ICACHE_ID
|INT:19
|vpiParameter:
\_parameter: (L1_IMMU_ID), line:181
|vpiName:L1_IMMU_ID
|INT:0
|vpiParameter:
\_parameter: (LS_UNIT_WB_ID), line:191
|vpiName:LS_UNIT_WB_ID
|INT:1
|vpiParameter:
\_parameter: (MAX_INFLIGHT_COUNT), line:167
|vpiName:MAX_INFLIGHT_COUNT
|INT:19
|vpiParameter:
\_parameter: (MEMORY_ADDR_H), line:103
|vpiName:MEMORY_ADDR_H
|INT:12
|vpiParameter:
\_parameter: (MEMORY_ADDR_L), line:102
|vpiName:MEMORY_ADDR_L
|INT:11
|vpiParameter:
\_parameter: (MEMORY_BIT_CHECK), line:104
|vpiName:MEMORY_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (MUL_UNIT_WB_ID), line:193
|vpiName:MUL_UNIT_WB_ID
|INT:512
|vpiParameter:
\_parameter: (NUM_UNITS), line:188
|vpiName:NUM_UNITS
|INT:2
|vpiParameter:
\_parameter: (NUM_WB_UNITS), line:186
|vpiName:NUM_WB_UNITS
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (RAS_DEPTH), line:161
|vpiName:RAS_DEPTH
|INT:2
|vpiParameter:
\_parameter: (RESET_VEC), line:39
|vpiName:RESET_VEC
|INT:-2147483648
|vpiParameter:
\_parameter: (SCRATCH_ADDR_H), line:99
|vpiName:SCRATCH_ADDR_H
|INT:9
|vpiParameter:
\_parameter: (SCRATCH_ADDR_L), line:98
|vpiName:SCRATCH_ADDR_L
|INT:8
|vpiParameter:
\_parameter: (SCRATCH_BIT_CHECK), line:100
|vpiName:SCRATCH_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (USE_AMO), line:70
|vpiName:USE_AMO
|INT:1
|vpiParameter:
\_parameter: (USE_BRANCH_PREDICTOR), line:158
|vpiName:USE_BRANCH_PREDICTOR
|INT:2
|vpiParameter:
\_parameter: (USE_BUS), line:88
|vpiName:USE_BUS
|INT:4
|vpiParameter:
\_parameter: (USE_DCACHE), line:92
|vpiName:USE_DCACHE
|INT:6
|vpiParameter:
\_parameter: (USE_DIV), line:49
|vpiName:USE_DIV
|INT:1
|vpiParameter:
\_parameter: (USE_DTAG_INVALIDATIONS), line:140
|vpiName:USE_DTAG_INVALIDATIONS
|INT:1879048191
|vpiParameter:
\_parameter: (USE_D_SCRATCH_MEM), line:79
|vpiName:USE_D_SCRATCH_MEM
|INT:3
|vpiParameter:
\_parameter: (USE_ICACHE), line:93
|vpiName:USE_ICACHE
|INT:7
|vpiParameter:
\_parameter: (USE_I_SCRATCH_MEM), line:78
|vpiName:USE_I_SCRATCH_MEM
|INT:2
|vpiParameter:
\_parameter: (USE_MUL), line:48
|vpiName:USE_MUL
|INT:1
|vpiParameter:
\_parameter: (WB_UNITS_WIDTH), line:187
|vpiName:WB_UNITS_WIDTH
|INT:32
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|uhdmtopModules:
\_module: work@local_mem (work@local_mem), file:third_party/cores/taiga/local_memory/local_mem.sv, line:24
|vpiDefName:work@local_mem
|vpiName:work@local_mem
|vpiPort:
\_port: (clk), line:31, parent:work@local_mem
|vpiName:clk
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (clk), line:31, parent:work@local_mem
|vpiName:clk
|vpiFullName:work@local_mem.clk
|vpiNetType:36
|vpiPort:
\_port: (rst), line:32, parent:work@local_mem
|vpiName:rst
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (rst), line:32, parent:work@local_mem
|vpiName:rst
|vpiFullName:work@local_mem.rst
|vpiNetType:36
|vpiPort:
\_port: (portA), line:33, parent:work@local_mem
|vpiName:portA
|vpiDirection:5
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_modport: (slave)
|vpiName:slave
|vpiIODecl:
\_io_decl: (addr)
|vpiName:addr
|vpiDirection:1
|vpiExpr:
\_logic_net: (addr), line:25
|vpiName:addr
|vpiNetType:36
|vpiRange:
\_range: , line:25
|vpiLeftRange:
\_constant: , line:25
|vpiConstType:7
|vpiDecompile:29
|vpiSize:32
|INT:29
|vpiRightRange:
\_constant: , line:25
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (en)
|vpiName:en
|vpiDirection:1
|vpiExpr:
\_logic_net: (en), line:26
|vpiName:en
|vpiNetType:36
|vpiIODecl:
\_io_decl: (be)
|vpiName:be
|vpiDirection:1
|vpiExpr:
\_logic_net: (be), line:27
|vpiName:be
|vpiNetType:36
|vpiRange:
\_range: , line:27
|vpiLeftRange:
\_constant: , line:27
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiRightRange:
\_constant: , line:27
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (data_in)
|vpiName:data_in
|vpiDirection:1
|vpiExpr:
\_logic_net: (data_in), line:28
|vpiName:data_in
|vpiNetType:36
|vpiRange:
\_range: , line:28
|vpiLeftRange:
\_constant: , line:28
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:28
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (data_out)
|vpiName:data_out
|vpiDirection:2
|vpiExpr:
\_logic_net: (data_out), line:29
|vpiName:data_out
|vpiNetType:36
|vpiRange:
\_range: , line:29
|vpiLeftRange:
\_constant: , line:29
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:29
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiInterface:
\_interface: work@local_memory_interface (portA), file:third_party/cores/taiga/local_memory/local_mem.sv, line:24
|vpiDefName:work@local_memory_interface
|vpiName:portA
|vpiModport:
\_modport: (master)
|vpiName:master
|vpiIODecl:
\_io_decl: (addr)
|vpiName:addr
|vpiDirection:2
|vpiExpr:
\_logic_net: (addr), line:25
|vpiIODecl:
\_io_decl: (en)
|vpiName:en
|vpiDirection:2
|vpiExpr:
\_logic_net: (en), line:26
|vpiIODecl:
\_io_decl: (be)
|vpiName:be
|vpiDirection:2
|vpiExpr:
\_logic_net: (be), line:27
|vpiIODecl:
\_io_decl: (data_in)
|vpiName:data_in
|vpiDirection:2
|vpiExpr:
\_logic_net: (data_in), line:28
|vpiIODecl:
\_io_decl: (data_out)
|vpiName:data_out
|vpiDirection:1
|vpiExpr:
\_logic_net: (data_out), line:29
|vpiInterface:
\_interface: work@local_memory_interface (portA), file:third_party/cores/taiga/local_memory/local_mem.sv, line:24
|vpiModport:
\_modport: (slave)
|vpiPort:
\_port: (portB), line:34, parent:work@local_mem
|vpiName:portB
|vpiDirection:5
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_modport: (slave)
|vpiName:slave
|vpiIODecl:
\_io_decl: (addr)
|vpiName:addr
|vpiDirection:1
|vpiExpr:
\_logic_net: (addr), line:25
|vpiIODecl:
\_io_decl: (en)
|vpiName:en
|vpiDirection:1
|vpiExpr:
\_logic_net: (en), line:26
|vpiIODecl:
\_io_decl: (be)
|vpiName:be
|vpiDirection:1
|vpiExpr:
\_logic_net: (be), line:27
|vpiIODecl:
\_io_decl: (data_in)
|vpiName:data_in
|vpiDirection:1
|vpiExpr:
\_logic_net: (data_in), line:28
|vpiIODecl:
\_io_decl: (data_out)
|vpiName:data_out
|vpiDirection:2
|vpiExpr:
\_logic_net: (data_out), line:29
|vpiInterface:
\_interface: work@local_memory_interface (portB), file:third_party/cores/taiga/local_memory/local_mem.sv, line:24
|vpiDefName:work@local_memory_interface
|vpiName:portB
|vpiModport:
\_modport: (master)
|vpiName:master
|vpiIODecl:
\_io_decl: (addr)
|vpiName:addr
|vpiDirection:2
|vpiExpr:
\_logic_net: (addr), line:25
|vpiIODecl:
\_io_decl: (en)
|vpiName:en
|vpiDirection:2
|vpiExpr:
\_logic_net: (en), line:26
|vpiIODecl:
\_io_decl: (be)
|vpiName:be
|vpiDirection:2
|vpiExpr:
\_logic_net: (be), line:27
|vpiIODecl:
\_io_decl: (data_in)
|vpiName:data_in
|vpiDirection:2
|vpiExpr:
\_logic_net: (data_in), line:28
|vpiIODecl:
\_io_decl: (data_out)
|vpiName:data_out
|vpiDirection:1
|vpiExpr:
\_logic_net: (data_out), line:29
|vpiInterface:
\_interface: work@local_memory_interface (portB), file:third_party/cores/taiga/local_memory/local_mem.sv, line:24
|vpiModport:
\_modport: (slave)
|vpiModule:
\_module: work@byte_en_BRAM (inst_data_ram), file:third_party/cores/taiga/local_memory/local_mem.sv, line:39, parent:work@local_mem
|vpiDefName:work@byte_en_BRAM
|vpiName:inst_data_ram
|vpiFullName:work@local_mem.inst_data_ram
|vpiPort:
\_port: (clk), line:32, parent:inst_data_ram
|vpiName:clk
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (clk), line:40
|vpiName:clk
|vpiActual:
\_logic_net: (clk), line:31, parent:work@local_mem
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (clk), line:32, parent:inst_data_ram
|vpiName:clk
|vpiFullName:work@local_mem.inst_data_ram.clk
|vpiNetType:36
|vpiPort:
\_port: (addr_a), line:33, parent:inst_data_ram
|vpiName:addr_a
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (portA.addr), line:41
|vpiName:portA.addr
|vpiActual:
\_logic_net: (addr), line:25
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (addr_a), line:33, parent:inst_data_ram
|vpiName:addr_a
|vpiFullName:work@local_mem.inst_data_ram.addr_a
|vpiNetType:36
|vpiRange:
\_range: , line:33
|vpiLeftRange:
\_constant: , line:33
|vpiConstType:7
|vpiDecompile:11
|vpiSize:32
|INT:11
|vpiRightRange:
\_constant: , line:33
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiPort:
\_port: (en_a), line:34, parent:inst_data_ram
|vpiName:en_a
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (portA.en), line:42
|vpiName:portA.en
|vpiActual:
\_logic_net: (en), line:26
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (en_a), line:34, parent:inst_data_ram
|vpiName:en_a
|vpiFullName:work@local_mem.inst_data_ram.en_a
|vpiNetType:36
|vpiPort:
\_port: (be_a), line:35, parent:inst_data_ram
|vpiName:be_a
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (portA.be), line:43
|vpiName:portA.be
|vpiActual:
\_logic_net: (be), line:27
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (be_a), line:35, parent:inst_data_ram
|vpiName:be_a
|vpiFullName:work@local_mem.inst_data_ram.be_a
|vpiNetType:36
|vpiRange:
\_range: , line:35
|vpiLeftRange:
\_constant: , line:35
|vpiConstType:7
|vpiDecompile:18446744073709551615
|vpiSize:32
|INT:-1
|vpiRightRange:
\_constant: , line:35
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiPort:
\_port: (data_in_a), line:36, parent:inst_data_ram
|vpiName:data_in_a
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (portA.data_in), line:44
|vpiName:portA.data_in
|vpiActual:
\_logic_net: (data_in), line:28
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (data_in_a), line:36, parent:inst_data_ram
|vpiName:data_in_a
|vpiFullName:work@local_mem.inst_data_ram.data_in_a
|vpiNetType:36
|vpiRange:
\_range: , line:36
|vpiLeftRange:
\_constant: , line:36
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiRightRange:
\_constant: , line:36
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiPort:
\_port: (data_out_a), line:37, parent:inst_data_ram
|vpiName:data_out_a
|vpiDirection:2
|vpiHighConn:
\_ref_obj: (portA.data_out), line:45
|vpiName:portA.data_out
|vpiActual:
\_logic_net: (data_out), line:29
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (data_out_a), line:37, parent:inst_data_ram
|vpiName:data_out_a
|vpiFullName:work@local_mem.inst_data_ram.data_out_a
|vpiNetType:36
|vpiRange:
\_range: , line:37
|vpiLeftRange:
\_constant: , line:37
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiRightRange:
\_constant: , line:37
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiPort:
\_port: (addr_b), line:39, parent:inst_data_ram
|vpiName:addr_b
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (portB.addr), line:47
|vpiName:portB.addr
|vpiActual:
\_logic_net: (addr), line:25
|vpiName:addr
|vpiNetType:36
|vpiRange:
\_range: , line:25
|vpiLeftRange:
\_constant: , line:25
|vpiConstType:7
|vpiDecompile:29
|vpiSize:32
|INT:29
|vpiRightRange:
\_constant: , line:25
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (addr_b), line:39, parent:inst_data_ram
|vpiName:addr_b
|vpiFullName:work@local_mem.inst_data_ram.addr_b
|vpiNetType:36
|vpiRange:
\_range: , line:39
|vpiLeftRange:
\_constant: , line:39
|vpiConstType:7
|vpiDecompile:11
|vpiSize:32
|INT:11
|vpiRightRange:
\_constant: , line:39
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiPort:
\_port: (en_b), line:40, parent:inst_data_ram
|vpiName:en_b
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (portB.en), line:48
|vpiName:portB.en
|vpiActual:
\_logic_net: (en), line:26
|vpiName:en
|vpiNetType:36
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (en_b), line:40, parent:inst_data_ram
|vpiName:en_b
|vpiFullName:work@local_mem.inst_data_ram.en_b
|vpiNetType:36
|vpiPort:
\_port: (be_b), line:41, parent:inst_data_ram
|vpiName:be_b
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (portB.be), line:49
|vpiName:portB.be
|vpiActual:
\_logic_net: (be), line:27
|vpiName:be
|vpiNetType:36
|vpiRange:
\_range: , line:27
|vpiLeftRange:
\_constant: , line:27
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiRightRange:
\_constant: , line:27
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (be_b), line:41, parent:inst_data_ram
|vpiName:be_b
|vpiFullName:work@local_mem.inst_data_ram.be_b
|vpiNetType:36
|vpiRange:
\_range: , line:41
|vpiLeftRange:
\_constant: , line:41
|vpiConstType:7
|vpiDecompile:18446744073709551615
|vpiSize:32
|INT:-1
|vpiRightRange:
\_constant: , line:41
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiPort:
\_port: (data_in_b), line:42, parent:inst_data_ram
|vpiName:data_in_b
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (portB.data_in), line:50
|vpiName:portB.data_in
|vpiActual:
\_logic_net: (data_in), line:28
|vpiName:data_in
|vpiNetType:36
|vpiRange:
\_range: , line:28
|vpiLeftRange:
\_constant: , line:28
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:28
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (data_in_b), line:42, parent:inst_data_ram
|vpiName:data_in_b
|vpiFullName:work@local_mem.inst_data_ram.data_in_b
|vpiNetType:36
|vpiRange:
\_range: , line:42
|vpiLeftRange:
\_constant: , line:42
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiRightRange:
\_constant: , line:42
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiPort:
\_port: (data_out_b), line:43, parent:inst_data_ram
|vpiName:data_out_b
|vpiDirection:2
|vpiHighConn:
\_ref_obj: (portB.data_out), line:51
|vpiName:portB.data_out
|vpiActual:
\_logic_net: (data_out), line:29
|vpiName:data_out
|vpiNetType:36
|vpiRange:
\_range: , line:29
|vpiLeftRange:
\_constant: , line:29
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:29
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (data_out_b), line:43, parent:inst_data_ram
|vpiName:data_out_b
|vpiFullName:work@local_mem.inst_data_ram.data_out_b
|vpiNetType:36
|vpiRange:
\_range: , line:43
|vpiLeftRange:
\_constant: , line:43
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiRightRange:
\_constant: , line:43
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiGenScopeArray:
\_gen_scope_array: (genblk1), line:47, parent:inst_data_ram
|vpiName:genblk1
|vpiFullName:work@local_mem.inst_data_ram.genblk1
|vpiGenScope:
\_gen_scope: , parent:genblk1
|vpiFullName:work@local_mem.inst_data_ram.genblk1
|vpiModule:
\_module: work@local_mem.inst_data_ram.genblk1::intel_byte_enable_ram (ram_block), file:third_party/cores/taiga/core/byte_en_BRAM.sv, line:50
|vpiDefName:work@local_mem.inst_data_ram.genblk1::intel_byte_enable_ram
|vpiName:ram_block
|vpiFullName:work@local_mem.inst_data_ram.genblk1.ram_block
|vpiParameter:
\_parameter: (ALU_UNIT_WB_ID), line:190
|vpiName:ALU_UNIT_WB_ID
|INT:32
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (BRANCH_PREDICTOR_WAYS), line:159
|vpiName:BRANCH_PREDICTOR_WAYS
|INT:9
|vpiParameter:
\_parameter: (BRANCH_TABLE_ENTRIES), line:160
|vpiName:BRANCH_TABLE_ENTRIES
|INT:4
|vpiParameter:
\_parameter: (BRANCH_UNIT_ID), line:195
|vpiName:BRANCH_UNIT_ID
|INT:8
|vpiParameter:
\_parameter: (BUS_ADDR_H), line:107
|vpiName:BUS_ADDR_H
|INT:1
|vpiParameter:
\_parameter: (BUS_ADDR_L), line:106
|vpiName:BUS_ADDR_L
|INT:0
|vpiParameter:
\_parameter: (BUS_BIT_CHECK), line:108
|vpiName:BUS_BIT_CHECK
|INT:1
|vpiParameter:
\_parameter: (BUS_TYPE), line:89
|vpiName:BUS_TYPE
|INT:5
|vpiParameter:
\_parameter: (COUNTER_W), line:42
|vpiName:COUNTER_W
|INT:33
|vpiParameter:
\_parameter: (CPU_ID), line:38
|vpiName:CPU_ID
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_ADDR_WIDTH), line:113
|vpiName:C_M_AXI_ADDR_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_DATA_WIDTH), line:114
|vpiName:C_M_AXI_DATA_WIDTH
|INT:1
|vpiParameter:
\_parameter: (DCACHE_LINES), line:133
|vpiName:DCACHE_LINES
|INT:-2146435073
|vpiParameter:
\_parameter: (DCACHE_LINE_ADDR_W), line:135
|vpiName:DCACHE_LINE_ADDR_W
|INT:1073741824
|vpiParameter:
\_parameter: (DCACHE_LINE_W), line:136
|vpiName:DCACHE_LINE_W
|INT:1342177279
|vpiParameter:
\_parameter: (DCACHE_SUB_LINE_ADDR_W), line:137
|vpiName:DCACHE_SUB_LINE_ADDR_W
|INT:4
|vpiParameter:
\_parameter: (DCACHE_TAG_W), line:138
|vpiName:DCACHE_TAG_W
|INT:1610612736
|vpiParameter:
\_parameter: (DCACHE_WAYS), line:134
|vpiName:DCACHE_WAYS
|INT:4
|vpiParameter:
\_parameter: (DIV_ALGORITHM), line:67
|vpiName:DIV_ALGORITHM
|INT:0
|vpiParameter:
\_parameter: (DIV_UNIT_WB_ID), line:192
|vpiName:DIV_UNIT_WB_ID
|INT:2
|vpiParameter:
\_parameter: (DTLB_DEPTH), line:152
|vpiName:DTLB_DEPTH
|INT:512
|vpiParameter:
\_parameter: (DTLB_WAYS), line:151
|vpiName:DTLB_WAYS
|INT:32
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (ENABLE_M_MODE), line:34
|vpiName:ENABLE_M_MODE
|INT:1
|vpiParameter:
\_parameter: (ENABLE_S_MODE), line:36
|vpiName:ENABLE_S_MODE
|INT:0
|vpiParameter:
\_parameter: (ENABLE_TRACE_INTERFACE), line:172
|vpiName:ENABLE_TRACE_INTERFACE
|INT:2
|vpiParameter:
\_parameter: (FETCH_BUFFER_DEPTH), line:168
|vpiName:FETCH_BUFFER_DEPTH
|INT:512
|vpiParameter:
\_parameter: (FPGA_VENDOR), line:27
|vpiName:FPGA_VENDOR
|STRING:"xilinx"
|vpiParameter:
\_parameter: (GC_UNIT_ID), line:196
|vpiName:GC_UNIT_ID
|INT:4
|vpiParameter:
\_parameter: (ICACHE_LINES), line:121
|vpiName:ICACHE_LINES
|INT:2
|vpiParameter:
\_parameter: (ICACHE_LINE_ADDR_W), line:123
|vpiName:ICACHE_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_LINE_W), line:124
|vpiName:ICACHE_LINE_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_SUB_LINE_ADDR_W), line:125
|vpiName:ICACHE_SUB_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_TAG_W), line:126
|vpiName:ICACHE_TAG_W
|INT:-2147483648
|vpiParameter:
\_parameter: (ICACHE_WAYS), line:122
|vpiName:ICACHE_WAYS
|INT:1
|vpiParameter:
\_parameter: (ITLB_DEPTH), line:146
|vpiName:ITLB_DEPTH
|INT:32
|vpiParameter:
\_parameter: (ITLB_WAYS), line:145
|vpiName:ITLB_WAYS
|INT:4
|vpiParameter:
\_parameter: (L1_CONNECTIONS), line:177
|vpiName:L1_CONNECTIONS
|INT:9
|vpiParameter:
\_parameter: (L1_DCACHE_ID), line:178
|vpiName:L1_DCACHE_ID
|INT:4
|vpiParameter:
\_parameter: (L1_DMMU_ID), line:179
|vpiName:L1_DMMU_ID
|INT:2
|vpiParameter:
\_parameter: (L1_ICACHE_ID), line:180
|vpiName:L1_ICACHE_ID
|INT:19
|vpiParameter:
\_parameter: (L1_IMMU_ID), line:181
|vpiName:L1_IMMU_ID
|INT:0
|vpiParameter:
\_parameter: (LS_UNIT_WB_ID), line:191
|vpiName:LS_UNIT_WB_ID
|INT:1
|vpiParameter:
\_parameter: (MAX_INFLIGHT_COUNT), line:167
|vpiName:MAX_INFLIGHT_COUNT
|INT:19
|vpiParameter:
\_parameter: (MEMORY_ADDR_H), line:103
|vpiName:MEMORY_ADDR_H
|INT:12
|vpiParameter:
\_parameter: (MEMORY_ADDR_L), line:102
|vpiName:MEMORY_ADDR_L
|INT:11
|vpiParameter:
\_parameter: (MEMORY_BIT_CHECK), line:104
|vpiName:MEMORY_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (MUL_UNIT_WB_ID), line:193
|vpiName:MUL_UNIT_WB_ID
|INT:512
|vpiParameter:
\_parameter: (NUM_UNITS), line:188
|vpiName:NUM_UNITS
|INT:2
|vpiParameter:
\_parameter: (NUM_WB_UNITS), line:186
|vpiName:NUM_WB_UNITS
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (RAS_DEPTH), line:161
|vpiName:RAS_DEPTH
|INT:2
|vpiParameter:
\_parameter: (RESET_VEC), line:39
|vpiName:RESET_VEC
|INT:-2147483648
|vpiParameter:
\_parameter: (SCRATCH_ADDR_H), line:99
|vpiName:SCRATCH_ADDR_H
|INT:9
|vpiParameter:
\_parameter: (SCRATCH_ADDR_L), line:98
|vpiName:SCRATCH_ADDR_L
|INT:8
|vpiParameter:
\_parameter: (SCRATCH_BIT_CHECK), line:100
|vpiName:SCRATCH_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (USE_AMO), line:70
|vpiName:USE_AMO
|INT:1
|vpiParameter:
\_parameter: (USE_BRANCH_PREDICTOR), line:158
|vpiName:USE_BRANCH_PREDICTOR
|INT:2
|vpiParameter:
\_parameter: (USE_BUS), line:88
|vpiName:USE_BUS
|INT:4
|vpiParameter:
\_parameter: (USE_DCACHE), line:92
|vpiName:USE_DCACHE
|INT:6
|vpiParameter:
\_parameter: (USE_DIV), line:49
|vpiName:USE_DIV
|INT:1
|vpiParameter:
\_parameter: (USE_DTAG_INVALIDATIONS), line:140
|vpiName:USE_DTAG_INVALIDATIONS
|INT:1879048191
|vpiParameter:
\_parameter: (USE_D_SCRATCH_MEM), line:79
|vpiName:USE_D_SCRATCH_MEM
|INT:3
|vpiParameter:
\_parameter: (USE_ICACHE), line:93
|vpiName:USE_ICACHE
|INT:7
|vpiParameter:
\_parameter: (USE_I_SCRATCH_MEM), line:78
|vpiName:USE_I_SCRATCH_MEM
|INT:2
|vpiParameter:
\_parameter: (USE_MUL), line:48
|vpiName:USE_MUL
|INT:1
|vpiParameter:
\_parameter: (WB_UNITS_WIDTH), line:187
|vpiName:WB_UNITS_WIDTH
|INT:32
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiNet:
\_logic_net: (clk), line:32, parent:inst_data_ram
|vpiNet:
\_logic_net: (addr_a), line:33, parent:inst_data_ram
|vpiNet:
\_logic_net: (en_a), line:34, parent:inst_data_ram
|vpiNet:
\_logic_net: (be_a), line:35, parent:inst_data_ram
|vpiNet:
\_logic_net: (data_in_a), line:36, parent:inst_data_ram
|vpiNet:
\_logic_net: (data_out_a), line:37, parent:inst_data_ram
|vpiNet:
\_logic_net: (addr_b), line:39, parent:inst_data_ram
|vpiNet:
\_logic_net: (en_b), line:40, parent:inst_data_ram
|vpiNet:
\_logic_net: (be_b), line:41, parent:inst_data_ram
|vpiNet:
\_logic_net: (data_in_b), line:42, parent:inst_data_ram
|vpiNet:
\_logic_net: (data_out_b), line:43, parent:inst_data_ram
|vpiInstance:
\_module: work@local_mem (work@local_mem), file:third_party/cores/taiga/local_memory/local_mem.sv, line:24
|vpiParameter:
\_parameter: (ALU_UNIT_WB_ID), line:190
|vpiName:ALU_UNIT_WB_ID
|INT:32
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (BRANCH_PREDICTOR_WAYS), line:159
|vpiName:BRANCH_PREDICTOR_WAYS
|INT:9
|vpiParameter:
\_parameter: (BRANCH_TABLE_ENTRIES), line:160
|vpiName:BRANCH_TABLE_ENTRIES
|INT:4
|vpiParameter:
\_parameter: (BRANCH_UNIT_ID), line:195
|vpiName:BRANCH_UNIT_ID
|INT:8
|vpiParameter:
\_parameter: (BUS_ADDR_H), line:107
|vpiName:BUS_ADDR_H
|INT:1
|vpiParameter:
\_parameter: (BUS_ADDR_L), line:106
|vpiName:BUS_ADDR_L
|INT:0
|vpiParameter:
\_parameter: (BUS_BIT_CHECK), line:108
|vpiName:BUS_BIT_CHECK
|INT:1
|vpiParameter:
\_parameter: (BUS_TYPE), line:89
|vpiName:BUS_TYPE
|INT:5
|vpiParameter:
\_parameter: (COUNTER_W), line:42
|vpiName:COUNTER_W
|INT:33
|vpiParameter:
\_parameter: (CPU_ID), line:38
|vpiName:CPU_ID
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_ADDR_WIDTH), line:113
|vpiName:C_M_AXI_ADDR_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_DATA_WIDTH), line:114
|vpiName:C_M_AXI_DATA_WIDTH
|INT:1
|vpiParameter:
\_parameter: (DCACHE_LINES), line:133
|vpiName:DCACHE_LINES
|INT:-2146435073
|vpiParameter:
\_parameter: (DCACHE_LINE_ADDR_W), line:135
|vpiName:DCACHE_LINE_ADDR_W
|INT:1073741824
|vpiParameter:
\_parameter: (DCACHE_LINE_W), line:136
|vpiName:DCACHE_LINE_W
|INT:1342177279
|vpiParameter:
\_parameter: (DCACHE_SUB_LINE_ADDR_W), line:137
|vpiName:DCACHE_SUB_LINE_ADDR_W
|INT:4
|vpiParameter:
\_parameter: (DCACHE_TAG_W), line:138
|vpiName:DCACHE_TAG_W
|INT:1610612736
|vpiParameter:
\_parameter: (DCACHE_WAYS), line:134
|vpiName:DCACHE_WAYS
|INT:4
|vpiParameter:
\_parameter: (DIV_ALGORITHM), line:67
|vpiName:DIV_ALGORITHM
|INT:0
|vpiParameter:
\_parameter: (DIV_UNIT_WB_ID), line:192
|vpiName:DIV_UNIT_WB_ID
|INT:2
|vpiParameter:
\_parameter: (DTLB_DEPTH), line:152
|vpiName:DTLB_DEPTH
|INT:512
|vpiParameter:
\_parameter: (DTLB_WAYS), line:151
|vpiName:DTLB_WAYS
|INT:32
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (ENABLE_M_MODE), line:39
|vpiName:ENABLE_M_MODE
|STRING:""
|vpiParameter:
\_parameter: (ENABLE_S_MODE), line:39
|vpiName:ENABLE_S_MODE
|INT:0
|vpiParameter:
\_parameter: (ENABLE_TRACE_INTERFACE), line:172
|vpiName:ENABLE_TRACE_INTERFACE
|INT:2
|vpiParameter:
\_parameter: (FETCH_BUFFER_DEPTH), line:168
|vpiName:FETCH_BUFFER_DEPTH
|INT:512
|vpiParameter:
\_parameter: (FPGA_VENDOR), line:39
|vpiName:FPGA_VENDOR
|INT:16384
|vpiParameter:
\_parameter: (GC_UNIT_ID), line:196
|vpiName:GC_UNIT_ID
|INT:4
|vpiParameter:
\_parameter: (ICACHE_LINES), line:121
|vpiName:ICACHE_LINES
|INT:2
|vpiParameter:
\_parameter: (ICACHE_LINE_ADDR_W), line:123
|vpiName:ICACHE_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_LINE_W), line:124
|vpiName:ICACHE_LINE_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_SUB_LINE_ADDR_W), line:125
|vpiName:ICACHE_SUB_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_TAG_W), line:126
|vpiName:ICACHE_TAG_W
|INT:-2147483648
|vpiParameter:
\_parameter: (ICACHE_WAYS), line:122
|vpiName:ICACHE_WAYS
|INT:1
|vpiParameter:
\_parameter: (ITLB_DEPTH), line:146
|vpiName:ITLB_DEPTH
|INT:32
|vpiParameter:
\_parameter: (ITLB_WAYS), line:145
|vpiName:ITLB_WAYS
|INT:4
|vpiParameter:
\_parameter: (L1_CONNECTIONS), line:177
|vpiName:L1_CONNECTIONS
|INT:9
|vpiParameter:
\_parameter: (L1_DCACHE_ID), line:178
|vpiName:L1_DCACHE_ID
|INT:4
|vpiParameter:
\_parameter: (L1_DMMU_ID), line:179
|vpiName:L1_DMMU_ID
|INT:2
|vpiParameter:
\_parameter: (L1_ICACHE_ID), line:180
|vpiName:L1_ICACHE_ID
|INT:19
|vpiParameter:
\_parameter: (L1_IMMU_ID), line:181
|vpiName:L1_IMMU_ID
|INT:0
|vpiParameter:
\_parameter: (LINES), line:27
|vpiName:LINES
|INT:4096
|vpiParameter:
\_parameter: (LS_UNIT_WB_ID), line:191
|vpiName:LS_UNIT_WB_ID
|INT:1
|vpiParameter:
\_parameter: (MAX_INFLIGHT_COUNT), line:167
|vpiName:MAX_INFLIGHT_COUNT
|INT:19
|vpiParameter:
\_parameter: (MEMORY_ADDR_H), line:103
|vpiName:MEMORY_ADDR_H
|INT:12
|vpiParameter:
\_parameter: (MEMORY_ADDR_L), line:102
|vpiName:MEMORY_ADDR_L
|INT:11
|vpiParameter:
\_parameter: (MEMORY_BIT_CHECK), line:104
|vpiName:MEMORY_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (MUL_UNIT_WB_ID), line:193
|vpiName:MUL_UNIT_WB_ID
|INT:512
|vpiParameter:
\_parameter: (NUM_UNITS), line:188
|vpiName:NUM_UNITS
|INT:2
|vpiParameter:
\_parameter: (NUM_WB_UNITS), line:186
|vpiName:NUM_WB_UNITS
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (RAS_DEPTH), line:161
|vpiName:RAS_DEPTH
|INT:2
|vpiParameter:
\_parameter: (RESET_VEC), line:39
|vpiName:RESET_VEC
|INT:-2147483648
|vpiParameter:
\_parameter: (SCRATCH_ADDR_H), line:99
|vpiName:SCRATCH_ADDR_H
|INT:9
|vpiParameter:
\_parameter: (SCRATCH_ADDR_L), line:98
|vpiName:SCRATCH_ADDR_L
|INT:8
|vpiParameter:
\_parameter: (SCRATCH_BIT_CHECK), line:100
|vpiName:SCRATCH_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (USE_AMO), line:70
|vpiName:USE_AMO
|INT:1
|vpiParameter:
\_parameter: (USE_BRANCH_PREDICTOR), line:158
|vpiName:USE_BRANCH_PREDICTOR
|INT:2
|vpiParameter:
\_parameter: (USE_BUS), line:88
|vpiName:USE_BUS
|INT:4
|vpiParameter:
\_parameter: (USE_DCACHE), line:92
|vpiName:USE_DCACHE
|INT:6
|vpiParameter:
\_parameter: (USE_DIV), line:49
|vpiName:USE_DIV
|INT:1
|vpiParameter:
\_parameter: (USE_DTAG_INVALIDATIONS), line:140
|vpiName:USE_DTAG_INVALIDATIONS
|INT:1879048191
|vpiParameter:
\_parameter: (USE_D_SCRATCH_MEM), line:79
|vpiName:USE_D_SCRATCH_MEM
|INT:3
|vpiParameter:
\_parameter: (USE_ICACHE), line:93
|vpiName:USE_ICACHE
|INT:7
|vpiParameter:
\_parameter: (USE_I_SCRATCH_MEM), line:78
|vpiName:USE_I_SCRATCH_MEM
|INT:2
|vpiParameter:
\_parameter: (USE_MUL), line:48
|vpiName:USE_MUL
|INT:1
|vpiParameter:
\_parameter: (USE_PRELOAD_FILE), line:29
|vpiName:USE_PRELOAD_FILE
|INT:0
|vpiParameter:
\_parameter: (WB_UNITS_WIDTH), line:187
|vpiName:WB_UNITS_WIDTH
|INT:32
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiParameter:
\_parameter: (preload_file), line:28
|vpiName:preload_file
|STRING:""
|vpiNet:
\_logic_net: (clk), line:31, parent:work@local_mem
|vpiNet:
\_logic_net: (rst), line:32, parent:work@local_mem
|vpiNet:
\_logic_net: (portA), line:33, parent:work@local_mem
|vpiName:portA
|vpiFullName:work@local_mem.portA
|vpiNet:
\_logic_net: (portB), line:34, parent:work@local_mem
|vpiName:portB
|vpiFullName:work@local_mem.portB
|vpiParameter:
\_parameter: (LINES), line:37
|vpiName:LINES
|INT:16384
|vpiParameter:
\_parameter: (RAM_SIZE), line:26
|vpiName:RAM_SIZE
|INT:64
|vpiParameter:
\_parameter: (USE_PRELOAD_FILE), line:28
|vpiName:USE_PRELOAD_FILE
|INT:0
|vpiParameter:
\_parameter: (preload_file), line:27
|vpiName:preload_file
|STRING:""
|uhdmtopModules:
\_module: work@taiga_wrapper (work@taiga_wrapper), file:third_party/cores/taiga/examples/zedboard/taiga_wrapper.sv, line:27
|vpiDefName:work@taiga_wrapper
|vpiName:work@taiga_wrapper
|vpiPort:
\_port: (sys_clk), line:28, parent:work@taiga_wrapper
|vpiName:sys_clk
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (sys_clk), line:28, parent:work@taiga_wrapper
|vpiName:sys_clk
|vpiFullName:work@taiga_wrapper.sys_clk
|vpiNetType:36
|vpiPort:
\_port: (ext_reset), line:29, parent:work@taiga_wrapper
|vpiName:ext_reset
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (ext_reset), line:29, parent:work@taiga_wrapper
|vpiName:ext_reset
|vpiFullName:work@taiga_wrapper.ext_reset
|vpiNetType:36
|vpiPort:
\_port: (DDR_addr), line:32, parent:work@taiga_wrapper
|vpiName:DDR_addr
|vpiDirection:3
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (DDR_addr), line:32, parent:work@taiga_wrapper
|vpiName:DDR_addr
|vpiFullName:work@taiga_wrapper.DDR_addr
|vpiRange:
\_range: , line:32
|vpiLeftRange:
\_constant: , line:32
|vpiConstType:7
|vpiDecompile:14
|vpiSize:32
|INT:14
|vpiRightRange:
\_constant: , line:32
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiPort:
\_port: (DDR_ba), line:33, parent:work@taiga_wrapper
|vpiName:DDR_ba
|vpiDirection:3
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (DDR_ba), line:33, parent:work@taiga_wrapper
|vpiName:DDR_ba
|vpiFullName:work@taiga_wrapper.DDR_ba
|vpiRange:
\_range: , line:33
|vpiLeftRange:
\_constant: , line:33
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiRightRange:
\_constant: , line:33
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiPort:
\_port: (DDR_cas_n), line:34, parent:work@taiga_wrapper
|vpiName:DDR_cas_n
|vpiDirection:3
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (DDR_cas_n), line:34, parent:work@taiga_wrapper
|vpiName:DDR_cas_n
|vpiFullName:work@taiga_wrapper.DDR_cas_n
|vpiPort:
\_port: (DDR_ck_n), line:35, parent:work@taiga_wrapper
|vpiName:DDR_ck_n
|vpiDirection:3
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (DDR_ck_n), line:35, parent:work@taiga_wrapper
|vpiName:DDR_ck_n
|vpiFullName:work@taiga_wrapper.DDR_ck_n
|vpiPort:
\_port: (DDR_ck_p), line:36, parent:work@taiga_wrapper
|vpiName:DDR_ck_p
|vpiDirection:3
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (DDR_ck_p), line:36, parent:work@taiga_wrapper
|vpiName:DDR_ck_p
|vpiFullName:work@taiga_wrapper.DDR_ck_p
|vpiPort:
\_port: (DDR_cke), line:37, parent:work@taiga_wrapper
|vpiName:DDR_cke
|vpiDirection:3
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (DDR_cke), line:37, parent:work@taiga_wrapper
|vpiName:DDR_cke
|vpiFullName:work@taiga_wrapper.DDR_cke
|vpiPort:
\_port: (DDR_cs_n), line:38, parent:work@taiga_wrapper
|vpiName:DDR_cs_n
|vpiDirection:3
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (DDR_cs_n), line:38, parent:work@taiga_wrapper
|vpiName:DDR_cs_n
|vpiFullName:work@taiga_wrapper.DDR_cs_n
|vpiPort:
\_port: (DDR_dm), line:39, parent:work@taiga_wrapper
|vpiName:DDR_dm
|vpiDirection:3
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (DDR_dm), line:39, parent:work@taiga_wrapper
|vpiName:DDR_dm
|vpiFullName:work@taiga_wrapper.DDR_dm
|vpiRange:
\_range: , line:39
|vpiLeftRange:
\_constant: , line:39
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiRightRange:
\_constant: , line:39
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiPort:
\_port: (DDR_dq), line:40, parent:work@taiga_wrapper
|vpiName:DDR_dq
|vpiDirection:3
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (DDR_dq), line:40, parent:work@taiga_wrapper
|vpiName:DDR_dq
|vpiFullName:work@taiga_wrapper.DDR_dq
|vpiRange:
\_range: , line:40
|vpiLeftRange:
\_constant: , line:40
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:40
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiPort:
\_port: (DDR_dqs_n), line:41, parent:work@taiga_wrapper
|vpiName:DDR_dqs_n
|vpiDirection:3
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (DDR_dqs_n), line:41, parent:work@taiga_wrapper
|vpiName:DDR_dqs_n
|vpiFullName:work@taiga_wrapper.DDR_dqs_n
|vpiRange:
\_range: , line:41
|vpiLeftRange:
\_constant: , line:41
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiRightRange:
\_constant: , line:41
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiPort:
\_port: (DDR_dqs_p), line:42, parent:work@taiga_wrapper
|vpiName:DDR_dqs_p
|vpiDirection:3
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (DDR_dqs_p), line:42, parent:work@taiga_wrapper
|vpiName:DDR_dqs_p
|vpiFullName:work@taiga_wrapper.DDR_dqs_p
|vpiRange:
\_range: , line:42
|vpiLeftRange:
\_constant: , line:42
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiRightRange:
\_constant: , line:42
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiPort:
\_port: (DDR_odt), line:43, parent:work@taiga_wrapper
|vpiName:DDR_odt
|vpiDirection:3
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (DDR_odt), line:43, parent:work@taiga_wrapper
|vpiName:DDR_odt
|vpiFullName:work@taiga_wrapper.DDR_odt
|vpiPort:
\_port: (DDR_ras_n), line:44, parent:work@taiga_wrapper
|vpiName:DDR_ras_n
|vpiDirection:3
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (DDR_ras_n), line:44, parent:work@taiga_wrapper
|vpiName:DDR_ras_n
|vpiFullName:work@taiga_wrapper.DDR_ras_n
|vpiPort:
\_port: (DDR_reset_n), line:45, parent:work@taiga_wrapper
|vpiName:DDR_reset_n
|vpiDirection:3
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (DDR_reset_n), line:45, parent:work@taiga_wrapper
|vpiName:DDR_reset_n
|vpiFullName:work@taiga_wrapper.DDR_reset_n
|vpiPort:
\_port: (DDR_we_n), line:46, parent:work@taiga_wrapper
|vpiName:DDR_we_n
|vpiDirection:3
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (DDR_we_n), line:46, parent:work@taiga_wrapper
|vpiName:DDR_we_n
|vpiFullName:work@taiga_wrapper.DDR_we_n
|vpiPort:
\_port: (FIXED_IO_ddr_vrn), line:47, parent:work@taiga_wrapper
|vpiName:FIXED_IO_ddr_vrn
|vpiDirection:3
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (FIXED_IO_ddr_vrn), line:47, parent:work@taiga_wrapper
|vpiName:FIXED_IO_ddr_vrn
|vpiFullName:work@taiga_wrapper.FIXED_IO_ddr_vrn
|vpiPort:
\_port: (FIXED_IO_ddr_vrp), line:48, parent:work@taiga_wrapper
|vpiName:FIXED_IO_ddr_vrp
|vpiDirection:3
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (FIXED_IO_ddr_vrp), line:48, parent:work@taiga_wrapper
|vpiName:FIXED_IO_ddr_vrp
|vpiFullName:work@taiga_wrapper.FIXED_IO_ddr_vrp
|vpiPort:
\_port: (FIXED_IO_mio), line:49, parent:work@taiga_wrapper
|vpiName:FIXED_IO_mio
|vpiDirection:3
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (FIXED_IO_mio), line:49, parent:work@taiga_wrapper
|vpiName:FIXED_IO_mio
|vpiFullName:work@taiga_wrapper.FIXED_IO_mio
|vpiRange:
\_range: , line:49
|vpiLeftRange:
\_constant: , line:49
|vpiConstType:7
|vpiDecompile:53
|vpiSize:32
|INT:53
|vpiRightRange:
\_constant: , line:49
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiPort:
\_port: (FIXED_IO_ps_clk), line:50, parent:work@taiga_wrapper
|vpiName:FIXED_IO_ps_clk
|vpiDirection:3
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (FIXED_IO_ps_clk), line:50, parent:work@taiga_wrapper
|vpiName:FIXED_IO_ps_clk
|vpiFullName:work@taiga_wrapper.FIXED_IO_ps_clk
|vpiPort:
\_port: (FIXED_IO_ps_porb), line:51, parent:work@taiga_wrapper
|vpiName:FIXED_IO_ps_porb
|vpiDirection:3
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (FIXED_IO_ps_porb), line:51, parent:work@taiga_wrapper
|vpiName:FIXED_IO_ps_porb
|vpiFullName:work@taiga_wrapper.FIXED_IO_ps_porb
|vpiPort:
\_port: (FIXED_IO_ps_srstb), line:52, parent:work@taiga_wrapper
|vpiName:FIXED_IO_ps_srstb
|vpiDirection:3
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (FIXED_IO_ps_srstb), line:52, parent:work@taiga_wrapper
|vpiName:FIXED_IO_ps_srstb
|vpiFullName:work@taiga_wrapper.FIXED_IO_ps_srstb
|vpiPort:
\_port: (sin), line:54, parent:work@taiga_wrapper
|vpiName:sin
|vpiDirection:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (sin), line:54, parent:work@taiga_wrapper
|vpiName:sin
|vpiFullName:work@taiga_wrapper.sin
|vpiNetType:36
|vpiPort:
\_port: (sout), line:55, parent:work@taiga_wrapper
|vpiName:sout
|vpiDirection:2
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (sout), line:55, parent:work@taiga_wrapper
|vpiName:sout
|vpiFullName:work@taiga_wrapper.sout
|vpiNetType:36
|vpiInterface:
\_interface: work@axi_interface (m_axi), file:third_party/cores/taiga/examples/zedboard/taiga_wrapper.sv, line:67, parent:work@taiga_wrapper
|vpiDefName:work@axi_interface
|vpiName:m_axi
|vpiFullName:work@taiga_wrapper.m_axi
|vpiModport:
\_modport: (master), parent:m_axi
|vpiName:master
|vpiIODecl:
\_io_decl: (arready), parent:master
|vpiName:arready
|vpiDirection:1
|vpiIODecl:
\_io_decl: (rvalid), parent:master
|vpiName:rvalid
|vpiDirection:1
|vpiIODecl:
\_io_decl: (rdata), parent:master
|vpiName:rdata
|vpiDirection:1
|vpiIODecl:
\_io_decl: (rresp), parent:master
|vpiName:rresp
|vpiDirection:1
|vpiIODecl:
\_io_decl: (rlast), parent:master
|vpiName:rlast
|vpiDirection:1
|vpiIODecl:
\_io_decl: (rid), parent:master
|vpiName:rid
|vpiDirection:1
|vpiIODecl:
\_io_decl: (awready), parent:master
|vpiName:awready
|vpiDirection:1
|vpiIODecl:
\_io_decl: (wready), parent:master
|vpiName:wready
|vpiDirection:1
|vpiIODecl:
\_io_decl: (bvalid), parent:master
|vpiName:bvalid
|vpiDirection:1
|vpiIODecl:
\_io_decl: (bresp), parent:master
|vpiName:bresp
|vpiDirection:1
|vpiIODecl:
\_io_decl: (bid), parent:master
|vpiName:bid
|vpiDirection:1
|vpiIODecl:
\_io_decl: (arvalid), parent:master
|vpiName:arvalid
|vpiDirection:2
|vpiIODecl:
\_io_decl: (araddr), parent:master
|vpiName:araddr
|vpiDirection:2
|vpiIODecl:
\_io_decl: (arlen), parent:master
|vpiName:arlen
|vpiDirection:2
|vpiIODecl:
\_io_decl: (arsize), parent:master
|vpiName:arsize
|vpiDirection:2
|vpiIODecl:
\_io_decl: (arburst), parent:master
|vpiName:arburst
|vpiDirection:2
|vpiIODecl:
\_io_decl: (arcache), parent:master
|vpiName:arcache
|vpiDirection:2
|vpiIODecl:
\_io_decl: (arid), parent:master
|vpiName:arid
|vpiDirection:2
|vpiIODecl:
\_io_decl: (rready), parent:master
|vpiName:rready
|vpiDirection:2
|vpiIODecl:
\_io_decl: (awvalid), parent:master
|vpiName:awvalid
|vpiDirection:2
|vpiIODecl:
\_io_decl: (awaddr), parent:master
|vpiName:awaddr
|vpiDirection:2
|vpiIODecl:
\_io_decl: (awlen), parent:master
|vpiName:awlen
|vpiDirection:2
|vpiIODecl:
\_io_decl: (awsize), parent:master
|vpiName:awsize
|vpiDirection:2
|vpiIODecl:
\_io_decl: (awburst), parent:master
|vpiName:awburst
|vpiDirection:2
|vpiIODecl:
\_io_decl: (awcache), parent:master
|vpiName:awcache
|vpiDirection:2
|vpiIODecl:
\_io_decl: (awid), parent:master
|vpiName:awid
|vpiDirection:2
|vpiIODecl:
\_io_decl: (wvalid), parent:master
|vpiName:wvalid
|vpiDirection:2
|vpiIODecl:
\_io_decl: (wdata), parent:master
|vpiName:wdata
|vpiDirection:2
|vpiIODecl:
\_io_decl: (wstrb), parent:master
|vpiName:wstrb
|vpiDirection:2
|vpiIODecl:
\_io_decl: (wlast), parent:master
|vpiName:wlast
|vpiDirection:2
|vpiIODecl:
\_io_decl: (bready), parent:master
|vpiName:bready
|vpiDirection:2
|vpiInterface:
\_interface: work@axi_interface (m_axi), file:third_party/cores/taiga/examples/zedboard/taiga_wrapper.sv, line:67, parent:work@taiga_wrapper
|vpiModport:
\_modport: (slave), parent:m_axi
|vpiName:slave
|vpiIODecl:
\_io_decl: (arvalid), parent:slave
|vpiName:arvalid
|vpiDirection:1
|vpiIODecl:
\_io_decl: (araddr), parent:slave
|vpiName:araddr
|vpiDirection:1
|vpiIODecl:
\_io_decl: (arlen), parent:slave
|vpiName:arlen
|vpiDirection:1
|vpiIODecl:
\_io_decl: (arsize), parent:slave
|vpiName:arsize
|vpiDirection:1
|vpiIODecl:
\_io_decl: (arburst), parent:slave
|vpiName:arburst
|vpiDirection:1
|vpiIODecl:
\_io_decl: (arcache), parent:slave
|vpiName:arcache
|vpiDirection:1
|vpiIODecl:
\_io_decl: (rready), parent:slave
|vpiName:rready
|vpiDirection:1
|vpiIODecl:
\_io_decl: (awvalid), parent:slave
|vpiName:awvalid
|vpiDirection:1
|vpiIODecl:
\_io_decl: (awaddr), parent:slave
|vpiName:awaddr
|vpiDirection:1
|vpiIODecl:
\_io_decl: (awlen), parent:slave
|vpiName:awlen
|vpiDirection:1
|vpiIODecl:
\_io_decl: (awsize), parent:slave
|vpiName:awsize
|vpiDirection:1
|vpiIODecl:
\_io_decl: (awburst), parent:slave
|vpiName:awburst
|vpiDirection:1
|vpiIODecl:
\_io_decl: (awcache), parent:slave
|vpiName:awcache
|vpiDirection:1
|vpiIODecl:
\_io_decl: (arid), parent:slave
|vpiName:arid
|vpiDirection:1
|vpiIODecl:
\_io_decl: (wvalid), parent:slave
|vpiName:wvalid
|vpiDirection:1
|vpiIODecl:
\_io_decl: (wdata), parent:slave
|vpiName:wdata
|vpiDirection:1
|vpiIODecl:
\_io_decl: (wstrb), parent:slave
|vpiName:wstrb
|vpiDirection:1
|vpiIODecl:
\_io_decl: (wlast), parent:slave
|vpiName:wlast
|vpiDirection:1
|vpiIODecl:
\_io_decl: (awid), parent:slave
|vpiName:awid
|vpiDirection:1
|vpiIODecl:
\_io_decl: (bready), parent:slave
|vpiName:bready
|vpiDirection:1
|vpiIODecl:
\_io_decl: (arready), parent:slave
|vpiName:arready
|vpiDirection:2
|vpiIODecl:
\_io_decl: (rvalid), parent:slave
|vpiName:rvalid
|vpiDirection:2
|vpiIODecl:
\_io_decl: (rdata), parent:slave
|vpiName:rdata
|vpiDirection:2
|vpiIODecl:
\_io_decl: (rresp), parent:slave
|vpiName:rresp
|vpiDirection:2
|vpiIODecl:
\_io_decl: (rlast), parent:slave
|vpiName:rlast
|vpiDirection:2
|vpiIODecl:
\_io_decl: (rid), parent:slave
|vpiName:rid
|vpiDirection:2
|vpiIODecl:
\_io_decl: (awready), parent:slave
|vpiName:awready
|vpiDirection:2
|vpiIODecl:
\_io_decl: (wready), parent:slave
|vpiName:wready
|vpiDirection:2
|vpiIODecl:
\_io_decl: (bvalid), parent:slave
|vpiName:bvalid
|vpiDirection:2
|vpiIODecl:
\_io_decl: (bresp), parent:slave
|vpiName:bresp
|vpiDirection:2
|vpiIODecl:
\_io_decl: (bid), parent:slave
|vpiName:bid
|vpiDirection:2
|vpiInterface:
\_interface: work@axi_interface (m_axi), file:third_party/cores/taiga/examples/zedboard/taiga_wrapper.sv, line:67, parent:work@taiga_wrapper
|vpiNet:
\_logic_net: (arready), line:29, parent:m_axi
|vpiName:arready
|vpiFullName:work@taiga_wrapper.m_axi.arready
|vpiNetType:36
|vpiNet:
\_logic_net: (arvalid), line:30, parent:m_axi
|vpiName:arvalid
|vpiFullName:work@taiga_wrapper.m_axi.arvalid
|vpiNetType:36
|vpiNet:
\_logic_net: (araddr), line:31, parent:m_axi
|vpiName:araddr
|vpiFullName:work@taiga_wrapper.m_axi.araddr
|vpiNetType:36
|vpiRange:
\_range: , line:31
|vpiLeftRange:
\_constant: , line:31
|vpiConstType:7
|vpiDecompile:18446744073709551615
|vpiSize:32
|INT:-1
|vpiRightRange:
\_constant: , line:31
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (arlen), line:32, parent:m_axi
|vpiName:arlen
|vpiFullName:work@taiga_wrapper.m_axi.arlen
|vpiNetType:36
|vpiRange:
\_range: , line:32
|vpiLeftRange:
\_constant: , line:32
|vpiConstType:7
|vpiDecompile:7
|vpiSize:32
|INT:7
|vpiRightRange:
\_constant: , line:32
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (arsize), line:33, parent:m_axi
|vpiName:arsize
|vpiFullName:work@taiga_wrapper.m_axi.arsize
|vpiNetType:36
|vpiRange:
\_range: , line:33
|vpiLeftRange:
\_constant: , line:33
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiRightRange:
\_constant: , line:33
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (arburst), line:34, parent:m_axi
|vpiName:arburst
|vpiFullName:work@taiga_wrapper.m_axi.arburst
|vpiNetType:36
|vpiRange:
\_range: , line:34
|vpiLeftRange:
\_constant: , line:34
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:34
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (arcache), line:35, parent:m_axi
|vpiName:arcache
|vpiFullName:work@taiga_wrapper.m_axi.arcache
|vpiNetType:36
|vpiRange:
\_range: , line:35
|vpiLeftRange:
\_constant: , line:35
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiRightRange:
\_constant: , line:35
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (arid), line:36, parent:m_axi
|vpiName:arid
|vpiFullName:work@taiga_wrapper.m_axi.arid
|vpiNetType:36
|vpiRange:
\_range: , line:36
|vpiLeftRange:
\_constant: , line:36
|vpiConstType:7
|vpiDecompile:5
|vpiSize:32
|INT:5
|vpiRightRange:
\_constant: , line:36
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (rready), line:39, parent:m_axi
|vpiName:rready
|vpiFullName:work@taiga_wrapper.m_axi.rready
|vpiNetType:36
|vpiNet:
\_logic_net: (rvalid), line:40, parent:m_axi
|vpiName:rvalid
|vpiFullName:work@taiga_wrapper.m_axi.rvalid
|vpiNetType:36
|vpiNet:
\_logic_net: (rdata), line:41, parent:m_axi
|vpiName:rdata
|vpiFullName:work@taiga_wrapper.m_axi.rdata
|vpiNetType:36
|vpiRange:
\_range: , line:41
|vpiLeftRange:
\_constant: , line:41
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiRightRange:
\_constant: , line:41
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (rresp), line:42, parent:m_axi
|vpiName:rresp
|vpiFullName:work@taiga_wrapper.m_axi.rresp
|vpiNetType:36
|vpiRange:
\_range: , line:42
|vpiLeftRange:
\_constant: , line:42
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:42
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (rlast), line:43, parent:m_axi
|vpiName:rlast
|vpiFullName:work@taiga_wrapper.m_axi.rlast
|vpiNetType:36
|vpiNet:
\_logic_net: (rid), line:44, parent:m_axi
|vpiName:rid
|vpiFullName:work@taiga_wrapper.m_axi.rid
|vpiNetType:36
|vpiRange:
\_range: , line:44
|vpiLeftRange:
\_constant: , line:44
|vpiConstType:7
|vpiDecompile:5
|vpiSize:32
|INT:5
|vpiRightRange:
\_constant: , line:44
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (awready), line:48, parent:m_axi
|vpiName:awready
|vpiFullName:work@taiga_wrapper.m_axi.awready
|vpiNetType:36
|vpiNet:
\_logic_net: (awvalid), line:49, parent:m_axi
|vpiName:awvalid
|vpiFullName:work@taiga_wrapper.m_axi.awvalid
|vpiNetType:36
|vpiNet:
\_logic_net: (awaddr), line:50, parent:m_axi
|vpiName:awaddr
|vpiFullName:work@taiga_wrapper.m_axi.awaddr
|vpiNetType:36
|vpiRange:
\_range: , line:50
|vpiLeftRange:
\_constant: , line:50
|vpiConstType:7
|vpiDecompile:18446744073709551615
|vpiSize:32
|INT:-1
|vpiRightRange:
\_constant: , line:50
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (awlen), line:51, parent:m_axi
|vpiName:awlen
|vpiFullName:work@taiga_wrapper.m_axi.awlen
|vpiNetType:36
|vpiRange:
\_range: , line:51
|vpiLeftRange:
\_constant: , line:51
|vpiConstType:7
|vpiDecompile:7
|vpiSize:32
|INT:7
|vpiRightRange:
\_constant: , line:51
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (awsize), line:52, parent:m_axi
|vpiName:awsize
|vpiFullName:work@taiga_wrapper.m_axi.awsize
|vpiNetType:36
|vpiRange:
\_range: , line:52
|vpiLeftRange:
\_constant: , line:52
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiRightRange:
\_constant: , line:52
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (awburst), line:53, parent:m_axi
|vpiName:awburst
|vpiFullName:work@taiga_wrapper.m_axi.awburst
|vpiNetType:36
|vpiRange:
\_range: , line:53
|vpiLeftRange:
\_constant: , line:53
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:53
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (awcache), line:54, parent:m_axi
|vpiName:awcache
|vpiFullName:work@taiga_wrapper.m_axi.awcache
|vpiNetType:36
|vpiRange:
\_range: , line:54
|vpiLeftRange:
\_constant: , line:54
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiRightRange:
\_constant: , line:54
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (awid), line:55, parent:m_axi
|vpiName:awid
|vpiFullName:work@taiga_wrapper.m_axi.awid
|vpiNetType:36
|vpiRange:
\_range: , line:55
|vpiLeftRange:
\_constant: , line:55
|vpiConstType:7
|vpiDecompile:5
|vpiSize:32
|INT:5
|vpiRightRange:
\_constant: , line:55
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (wready), line:58, parent:m_axi
|vpiName:wready
|vpiFullName:work@taiga_wrapper.m_axi.wready
|vpiNetType:36
|vpiNet:
\_logic_net: (wvalid), line:59, parent:m_axi
|vpiName:wvalid
|vpiFullName:work@taiga_wrapper.m_axi.wvalid
|vpiNetType:36
|vpiNet:
\_logic_net: (wdata), line:60, parent:m_axi
|vpiName:wdata
|vpiFullName:work@taiga_wrapper.m_axi.wdata
|vpiNetType:36
|vpiRange:
\_range: , line:60
|vpiLeftRange:
\_constant: , line:60
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiRightRange:
\_constant: , line:60
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (wstrb), line:61, parent:m_axi
|vpiName:wstrb
|vpiFullName:work@taiga_wrapper.m_axi.wstrb
|vpiNetType:36
|vpiRange:
\_range: , line:61
|vpiLeftRange:
\_constant: , line:61
|vpiConstType:7
|vpiDecompile:18446744073709551615
|vpiSize:32
|INT:-1
|vpiRightRange:
\_constant: , line:61
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (wlast), line:62, parent:m_axi
|vpiName:wlast
|vpiFullName:work@taiga_wrapper.m_axi.wlast
|vpiNetType:36
|vpiNet:
\_logic_net: (bready), line:65, parent:m_axi
|vpiName:bready
|vpiFullName:work@taiga_wrapper.m_axi.bready
|vpiNetType:36
|vpiNet:
\_logic_net: (bvalid), line:66, parent:m_axi
|vpiName:bvalid
|vpiFullName:work@taiga_wrapper.m_axi.bvalid
|vpiNetType:36
|vpiNet:
\_logic_net: (bresp), line:67, parent:m_axi
|vpiName:bresp
|vpiFullName:work@taiga_wrapper.m_axi.bresp
|vpiNetType:36
|vpiRange:
\_range: , line:67
|vpiLeftRange:
\_constant: , line:67
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:67
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (bid), line:68, parent:m_axi
|vpiName:bid
|vpiFullName:work@taiga_wrapper.m_axi.bid
|vpiNetType:36
|vpiRange:
\_range: , line:68
|vpiLeftRange:
\_constant: , line:68
|vpiConstType:7
|vpiDecompile:5
|vpiSize:32
|INT:5
|vpiRightRange:
\_constant: , line:68
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiInstance:
\_module: work@taiga_wrapper (work@taiga_wrapper), file:third_party/cores/taiga/examples/zedboard/taiga_wrapper.sv, line:27
|vpiInterface:
\_interface: work@avalon_interface (m_avalon), file:third_party/cores/taiga/examples/zedboard/taiga_wrapper.sv, line:68, parent:work@taiga_wrapper
|vpiDefName:work@avalon_interface
|vpiName:m_avalon
|vpiFullName:work@taiga_wrapper.m_avalon
|vpiModport:
\_modport: (master), parent:m_avalon
|vpiName:master
|vpiIODecl:
\_io_decl: (readdata), parent:master
|vpiName:readdata
|vpiDirection:1
|vpiIODecl:
\_io_decl: (waitrequest), parent:master
|vpiName:waitrequest
|vpiDirection:1
|vpiIODecl:
\_io_decl: (readdatavalid), parent:master
|vpiName:readdatavalid
|vpiDirection:1
|vpiIODecl:
\_io_decl: (writeresponsevalid), parent:master
|vpiName:writeresponsevalid
|vpiDirection:1
|vpiIODecl:
\_io_decl: (addr), parent:master
|vpiName:addr
|vpiDirection:2
|vpiIODecl:
\_io_decl: (read), parent:master
|vpiName:read
|vpiDirection:2
|vpiIODecl:
\_io_decl: (write), parent:master
|vpiName:write
|vpiDirection:2
|vpiIODecl:
\_io_decl: (byteenable), parent:master
|vpiName:byteenable
|vpiDirection:2
|vpiIODecl:
\_io_decl: (writedata), parent:master
|vpiName:writedata
|vpiDirection:2
|vpiInterface:
\_interface: work@avalon_interface (m_avalon), file:third_party/cores/taiga/examples/zedboard/taiga_wrapper.sv, line:68, parent:work@taiga_wrapper
|vpiModport:
\_modport: (slave), parent:m_avalon
|vpiName:slave
|vpiIODecl:
\_io_decl: (readdata), parent:slave
|vpiName:readdata
|vpiDirection:2
|vpiIODecl:
\_io_decl: (waitrequest), parent:slave
|vpiName:waitrequest
|vpiDirection:2
|vpiIODecl:
\_io_decl: (readdatavalid), parent:slave
|vpiName:readdatavalid
|vpiDirection:2
|vpiIODecl:
\_io_decl: (writeresponsevalid), parent:slave
|vpiName:writeresponsevalid
|vpiDirection:2
|vpiIODecl:
\_io_decl: (addr), parent:slave
|vpiName:addr
|vpiDirection:1
|vpiIODecl:
\_io_decl: (read), parent:slave
|vpiName:read
|vpiDirection:1
|vpiIODecl:
\_io_decl: (write), parent:slave
|vpiName:write
|vpiDirection:1
|vpiIODecl:
\_io_decl: (byteenable), parent:slave
|vpiName:byteenable
|vpiDirection:1
|vpiIODecl:
\_io_decl: (writedata), parent:slave
|vpiName:writedata
|vpiDirection:1
|vpiInterface:
\_interface: work@avalon_interface (m_avalon), file:third_party/cores/taiga/examples/zedboard/taiga_wrapper.sv, line:68, parent:work@taiga_wrapper
|vpiNet:
\_logic_net: (addr), line:88, parent:m_avalon
|vpiName:addr
|vpiFullName:work@taiga_wrapper.m_avalon.addr
|vpiNetType:36
|vpiRange:
\_range: , line:88
|vpiLeftRange:
\_constant: , line:88
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:88
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (read), line:89, parent:m_avalon
|vpiName:read
|vpiFullName:work@taiga_wrapper.m_avalon.read
|vpiNetType:36
|vpiNet:
\_logic_net: (write), line:90, parent:m_avalon
|vpiName:write
|vpiFullName:work@taiga_wrapper.m_avalon.write
|vpiNetType:36
|vpiNet:
\_logic_net: (byteenable), line:91, parent:m_avalon
|vpiName:byteenable
|vpiFullName:work@taiga_wrapper.m_avalon.byteenable
|vpiNetType:36
|vpiRange:
\_range: , line:91
|vpiLeftRange:
\_constant: , line:91
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiRightRange:
\_constant: , line:91
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (readdata), line:92, parent:m_avalon
|vpiName:readdata
|vpiFullName:work@taiga_wrapper.m_avalon.readdata
|vpiNetType:36
|vpiRange:
\_range: , line:92
|vpiLeftRange:
\_constant: , line:92
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:92
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (writedata), line:93, parent:m_avalon
|vpiName:writedata
|vpiFullName:work@taiga_wrapper.m_avalon.writedata
|vpiNetType:36
|vpiRange:
\_range: , line:93
|vpiLeftRange:
\_constant: , line:93
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:93
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (waitrequest), line:94, parent:m_avalon
|vpiName:waitrequest
|vpiFullName:work@taiga_wrapper.m_avalon.waitrequest
|vpiNetType:36
|vpiNet:
\_logic_net: (readdatavalid), line:95, parent:m_avalon
|vpiName:readdatavalid
|vpiFullName:work@taiga_wrapper.m_avalon.readdatavalid
|vpiNetType:36
|vpiNet:
\_logic_net: (writeresponsevalid), line:96, parent:m_avalon
|vpiName:writeresponsevalid
|vpiFullName:work@taiga_wrapper.m_avalon.writeresponsevalid
|vpiNetType:36
|vpiInstance:
\_module: work@taiga_wrapper (work@taiga_wrapper), file:third_party/cores/taiga/examples/zedboard/taiga_wrapper.sv, line:27
|vpiInterface:
\_interface: work@wishbone_interface (m_wishbone), file:third_party/cores/taiga/examples/zedboard/taiga_wrapper.sv, line:69, parent:work@taiga_wrapper
|vpiDefName:work@wishbone_interface
|vpiName:m_wishbone
|vpiFullName:work@taiga_wrapper.m_wishbone
|vpiModport:
\_modport: (master), parent:m_wishbone
|vpiName:master
|vpiIODecl:
\_io_decl: (readdata), parent:master
|vpiName:readdata
|vpiDirection:1
|vpiIODecl:
\_io_decl: (ack), parent:master
|vpiName:ack
|vpiDirection:1
|vpiIODecl:
\_io_decl: (addr), parent:master
|vpiName:addr
|vpiDirection:2
|vpiIODecl:
\_io_decl: (we), parent:master
|vpiName:we
|vpiDirection:2
|vpiIODecl:
\_io_decl: (sel), parent:master
|vpiName:sel
|vpiDirection:2
|vpiIODecl:
\_io_decl: (writedata), parent:master
|vpiName:writedata
|vpiDirection:2
|vpiIODecl:
\_io_decl: (stb), parent:master
|vpiName:stb
|vpiDirection:2
|vpiIODecl:
\_io_decl: (cyc), parent:master
|vpiName:cyc
|vpiDirection:2
|vpiInterface:
\_interface: work@wishbone_interface (m_wishbone), file:third_party/cores/taiga/examples/zedboard/taiga_wrapper.sv, line:69, parent:work@taiga_wrapper
|vpiModport:
\_modport: (slave), parent:m_wishbone
|vpiName:slave
|vpiIODecl:
\_io_decl: (readdata), parent:slave
|vpiName:readdata
|vpiDirection:2
|vpiIODecl:
\_io_decl: (ack), parent:slave
|vpiName:ack
|vpiDirection:2
|vpiIODecl:
\_io_decl: (addr), parent:slave
|vpiName:addr
|vpiDirection:1
|vpiIODecl:
\_io_decl: (we), parent:slave
|vpiName:we
|vpiDirection:1
|vpiIODecl:
\_io_decl: (sel), parent:slave
|vpiName:sel
|vpiDirection:1
|vpiIODecl:
\_io_decl: (writedata), parent:slave
|vpiName:writedata
|vpiDirection:1
|vpiIODecl:
\_io_decl: (stb), parent:slave
|vpiName:stb
|vpiDirection:1
|vpiIODecl:
\_io_decl: (cyc), parent:slave
|vpiName:cyc
|vpiDirection:1
|vpiInterface:
\_interface: work@wishbone_interface (m_wishbone), file:third_party/cores/taiga/examples/zedboard/taiga_wrapper.sv, line:69, parent:work@taiga_wrapper
|vpiNet:
\_logic_net: (addr), line:106, parent:m_wishbone
|vpiName:addr
|vpiFullName:work@taiga_wrapper.m_wishbone.addr
|vpiNetType:36
|vpiRange:
\_range: , line:106
|vpiLeftRange:
\_constant: , line:106
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:106
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (we), line:107, parent:m_wishbone
|vpiName:we
|vpiFullName:work@taiga_wrapper.m_wishbone.we
|vpiNetType:36
|vpiNet:
\_logic_net: (sel), line:108, parent:m_wishbone
|vpiName:sel
|vpiFullName:work@taiga_wrapper.m_wishbone.sel
|vpiNetType:36
|vpiRange:
\_range: , line:108
|vpiLeftRange:
\_constant: , line:108
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiRightRange:
\_constant: , line:108
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (readdata), line:109, parent:m_wishbone
|vpiName:readdata
|vpiFullName:work@taiga_wrapper.m_wishbone.readdata
|vpiNetType:36
|vpiRange:
\_range: , line:109
|vpiLeftRange:
\_constant: , line:109
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:109
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (writedata), line:110, parent:m_wishbone
|vpiName:writedata
|vpiFullName:work@taiga_wrapper.m_wishbone.writedata
|vpiNetType:36
|vpiRange:
\_range: , line:110
|vpiLeftRange:
\_constant: , line:110
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:110
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (stb), line:111, parent:m_wishbone
|vpiName:stb
|vpiFullName:work@taiga_wrapper.m_wishbone.stb
|vpiNetType:36
|vpiNet:
\_logic_net: (cyc), line:112, parent:m_wishbone
|vpiName:cyc
|vpiFullName:work@taiga_wrapper.m_wishbone.cyc
|vpiNetType:36
|vpiNet:
\_logic_net: (ack), line:113, parent:m_wishbone
|vpiName:ack
|vpiFullName:work@taiga_wrapper.m_wishbone.ack
|vpiNetType:36
|vpiInstance:
\_module: work@taiga_wrapper (work@taiga_wrapper), file:third_party/cores/taiga/examples/zedboard/taiga_wrapper.sv, line:27
|vpiInterface:
\_interface: work@l2_requester_interface (l20), file:third_party/cores/taiga/examples/zedboard/taiga_wrapper.sv, line:70, parent:work@taiga_wrapper
|vpiDefName:work@l2_requester_interface
|vpiName:l20
|vpiFullName:work@taiga_wrapper.l20
|vpiModport:
\_modport: (master), parent:l20
|vpiName:master
|vpiIODecl:
\_io_decl: (addr), parent:master
|vpiName:addr
|vpiDirection:2
|vpiIODecl:
\_io_decl: (be), parent:master
|vpiName:be
|vpiDirection:2
|vpiIODecl:
\_io_decl: (rnw), parent:master
|vpiName:rnw
|vpiDirection:2
|vpiIODecl:
\_io_decl: (is_amo), parent:master
|vpiName:is_amo
|vpiDirection:2
|vpiIODecl:
\_io_decl: (amo_type_or_burst_size), parent:master
|vpiName:amo_type_or_burst_size
|vpiDirection:2
|vpiIODecl:
\_io_decl: (sub_id), parent:master
|vpiName:sub_id
|vpiDirection:2
|vpiIODecl:
\_io_decl: (request_push), parent:master
|vpiName:request_push
|vpiDirection:2
|vpiIODecl:
\_io_decl: (request_full), parent:master
|vpiName:request_full
|vpiDirection:1
|vpiIODecl:
\_io_decl: (inv_addr), parent:master
|vpiName:inv_addr
|vpiDirection:1
|vpiIODecl:
\_io_decl: (inv_valid), parent:master
|vpiName:inv_valid
|vpiDirection:1
|vpiIODecl:
\_io_decl: (inv_ack), parent:master
|vpiName:inv_ack
|vpiDirection:2
|vpiIODecl:
\_io_decl: (con_result), parent:master
|vpiName:con_result
|vpiDirection:1
|vpiIODecl:
\_io_decl: (con_valid), parent:master
|vpiName:con_valid
|vpiDirection:1
|vpiIODecl:
\_io_decl: (wr_data), parent:master
|vpiName:wr_data
|vpiDirection:2
|vpiIODecl:
\_io_decl: (wr_data_push), parent:master
|vpiName:wr_data_push
|vpiDirection:2
|vpiIODecl:
\_io_decl: (data_full), parent:master
|vpiName:data_full
|vpiDirection:1
|vpiIODecl:
\_io_decl: (rd_data), parent:master
|vpiName:rd_data
|vpiDirection:1
|vpiIODecl:
\_io_decl: (rd_sub_id), parent:master
|vpiName:rd_sub_id
|vpiDirection:1
|vpiIODecl:
\_io_decl: (rd_data_valid), parent:master
|vpiName:rd_data_valid
|vpiDirection:1
|vpiIODecl:
\_io_decl: (rd_data_ack), parent:master
|vpiName:rd_data_ack
|vpiDirection:2
|vpiInterface:
\_interface: work@l2_requester_interface (l20), file:third_party/cores/taiga/examples/zedboard/taiga_wrapper.sv, line:70, parent:work@taiga_wrapper
|vpiModport:
\_modport: (slave), parent:l20
|vpiName:slave
|vpiIODecl:
\_io_decl: (addr), parent:slave
|vpiName:addr
|vpiDirection:1
|vpiIODecl:
\_io_decl: (be), parent:slave
|vpiName:be
|vpiDirection:1
|vpiIODecl:
\_io_decl: (rnw), parent:slave
|vpiName:rnw
|vpiDirection:1
|vpiIODecl:
\_io_decl: (is_amo), parent:slave
|vpiName:is_amo
|vpiDirection:1
|vpiIODecl:
\_io_decl: (amo_type_or_burst_size), parent:slave
|vpiName:amo_type_or_burst_size
|vpiDirection:1
|vpiIODecl:
\_io_decl: (sub_id), parent:slave
|vpiName:sub_id
|vpiDirection:1
|vpiIODecl:
\_io_decl: (request_push), parent:slave
|vpiName:request_push
|vpiDirection:1
|vpiIODecl:
\_io_decl: (request_full), parent:slave
|vpiName:request_full
|vpiDirection:2
|vpiIODecl:
\_io_decl: (inv_addr), parent:slave
|vpiName:inv_addr
|vpiDirection:2
|vpiIODecl:
\_io_decl: (inv_valid), parent:slave
|vpiName:inv_valid
|vpiDirection:2
|vpiIODecl:
\_io_decl: (inv_ack), parent:slave
|vpiName:inv_ack
|vpiDirection:1
|vpiIODecl:
\_io_decl: (con_result), parent:slave
|vpiName:con_result
|vpiDirection:2
|vpiIODecl:
\_io_decl: (con_valid), parent:slave
|vpiName:con_valid
|vpiDirection:2
|vpiIODecl:
\_io_decl: (wr_data), parent:slave
|vpiName:wr_data
|vpiDirection:1
|vpiIODecl:
\_io_decl: (wr_data_push), parent:slave
|vpiName:wr_data_push
|vpiDirection:1
|vpiIODecl:
\_io_decl: (data_full), parent:slave
|vpiName:data_full
|vpiDirection:2
|vpiIODecl:
\_io_decl: (rd_data), parent:slave
|vpiName:rd_data
|vpiDirection:2
|vpiIODecl:
\_io_decl: (rd_sub_id), parent:slave
|vpiName:rd_sub_id
|vpiDirection:2
|vpiIODecl:
\_io_decl: (rd_data_valid), parent:slave
|vpiName:rd_data_valid
|vpiDirection:2
|vpiIODecl:
\_io_decl: (rd_data_ack), parent:slave
|vpiName:rd_data_ack
|vpiDirection:1
|vpiInterface:
\_interface: work@l2_requester_interface (l20), file:third_party/cores/taiga/examples/zedboard/taiga_wrapper.sv, line:70, parent:work@taiga_wrapper
|vpiNet:
\_logic_net: (addr), line:27, parent:l20
|vpiName:addr
|vpiFullName:work@taiga_wrapper.l20.addr
|vpiNetType:36
|vpiRange:
\_range: , line:27
|vpiLeftRange:
\_constant: , line:27
|vpiConstType:7
|vpiDecompile:29
|vpiSize:32
|INT:29
|vpiRightRange:
\_constant: , line:27
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (be), line:28, parent:l20
|vpiName:be
|vpiFullName:work@taiga_wrapper.l20.be
|vpiNetType:36
|vpiRange:
\_range: , line:28
|vpiLeftRange:
\_constant: , line:28
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiRightRange:
\_constant: , line:28
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (rnw), line:29, parent:l20
|vpiName:rnw
|vpiFullName:work@taiga_wrapper.l20.rnw
|vpiNetType:36
|vpiNet:
\_logic_net: (is_amo), line:30, parent:l20
|vpiName:is_amo
|vpiFullName:work@taiga_wrapper.l20.is_amo
|vpiNetType:36
|vpiNet:
\_logic_net: (amo_type_or_burst_size), line:31, parent:l20
|vpiName:amo_type_or_burst_size
|vpiFullName:work@taiga_wrapper.l20.amo_type_or_burst_size
|vpiNetType:36
|vpiRange:
\_range: , line:31
|vpiLeftRange:
\_constant: , line:31
|vpiConstType:7
|vpiDecompile:4
|vpiSize:32
|INT:4
|vpiRightRange:
\_constant: , line:31
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (sub_id), line:32, parent:l20
|vpiName:sub_id
|vpiFullName:work@taiga_wrapper.l20.sub_id
|vpiNetType:36
|vpiRange:
\_range: , line:32
|vpiLeftRange:
\_constant: , line:32
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:32
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (request_push), line:34, parent:l20
|vpiName:request_push
|vpiFullName:work@taiga_wrapper.l20.request_push
|vpiNetType:36
|vpiNet:
\_logic_net: (request_full), line:35, parent:l20
|vpiName:request_full
|vpiFullName:work@taiga_wrapper.l20.request_full
|vpiNetType:36
|vpiNet:
\_logic_net: (inv_addr), line:37, parent:l20
|vpiName:inv_addr
|vpiFullName:work@taiga_wrapper.l20.inv_addr
|vpiNetType:36
|vpiRange:
\_range: , line:37
|vpiLeftRange:
\_constant: , line:37
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:37
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiNet:
\_logic_net: (inv_valid), line:38, parent:l20
|vpiName:inv_valid
|vpiFullName:work@taiga_wrapper.l20.inv_valid
|vpiNetType:36
|vpiNet:
\_logic_net: (inv_ack), line:39, parent:l20
|vpiName:inv_ack
|vpiFullName:work@taiga_wrapper.l20.inv_ack
|vpiNetType:36
|vpiNet:
\_logic_net: (con_result), line:41, parent:l20
|vpiName:con_result
|vpiFullName:work@taiga_wrapper.l20.con_result
|vpiNetType:36
|vpiNet:
\_logic_net: (con_valid), line:42, parent:l20
|vpiName:con_valid
|vpiFullName:work@taiga_wrapper.l20.con_valid
|vpiNetType:36
|vpiNet:
\_logic_net: (wr_data), line:44, parent:l20
|vpiName:wr_data
|vpiFullName:work@taiga_wrapper.l20.wr_data
|vpiNetType:36
|vpiRange:
\_range: , line:44
|vpiLeftRange:
\_constant: , line:44
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:44
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (wr_data_push), line:45, parent:l20
|vpiName:wr_data_push
|vpiFullName:work@taiga_wrapper.l20.wr_data_push
|vpiNetType:36
|vpiNet:
\_logic_net: (data_full), line:46, parent:l20
|vpiName:data_full
|vpiFullName:work@taiga_wrapper.l20.data_full
|vpiNetType:36
|vpiNet:
\_logic_net: (rd_data), line:48, parent:l20
|vpiName:rd_data
|vpiFullName:work@taiga_wrapper.l20.rd_data
|vpiNetType:36
|vpiRange:
\_range: , line:48
|vpiLeftRange:
\_constant: , line:48
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:48
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (rd_sub_id), line:49, parent:l20
|vpiName:rd_sub_id
|vpiFullName:work@taiga_wrapper.l20.rd_sub_id
|vpiNetType:36
|vpiRange:
\_range: , line:49
|vpiLeftRange:
\_constant: , line:49
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:49
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (rd_data_valid), line:50, parent:l20
|vpiName:rd_data_valid
|vpiFullName:work@taiga_wrapper.l20.rd_data_valid
|vpiNetType:36
|vpiNet:
\_logic_net: (rd_data_ack), line:51, parent:l20
|vpiName:rd_data_ack
|vpiFullName:work@taiga_wrapper.l20.rd_data_ack
|vpiNetType:36
|vpiInstance:
\_module: work@taiga_wrapper (work@taiga_wrapper), file:third_party/cores/taiga/examples/zedboard/taiga_wrapper.sv, line:27
|vpiInterface:
\_interface: work@l2_requester_interface (l21), file:third_party/cores/taiga/examples/zedboard/taiga_wrapper.sv, line:70, parent:work@taiga_wrapper
|vpiDefName:work@l2_requester_interface
|vpiName:l21
|vpiFullName:work@taiga_wrapper.l21
|vpiModport:
\_modport: (master), parent:l21
|vpiName:master
|vpiIODecl:
\_io_decl: (addr), parent:master
|vpiName:addr
|vpiDirection:2
|vpiIODecl:
\_io_decl: (be), parent:master
|vpiName:be
|vpiDirection:2
|vpiIODecl:
\_io_decl: (rnw), parent:master
|vpiName:rnw
|vpiDirection:2
|vpiIODecl:
\_io_decl: (is_amo), parent:master
|vpiName:is_amo
|vpiDirection:2
|vpiIODecl:
\_io_decl: (amo_type_or_burst_size), parent:master
|vpiName:amo_type_or_burst_size
|vpiDirection:2
|vpiIODecl:
\_io_decl: (sub_id), parent:master
|vpiName:sub_id
|vpiDirection:2
|vpiIODecl:
\_io_decl: (request_push), parent:master
|vpiName:request_push
|vpiDirection:2
|vpiIODecl:
\_io_decl: (request_full), parent:master
|vpiName:request_full
|vpiDirection:1
|vpiIODecl:
\_io_decl: (inv_addr), parent:master
|vpiName:inv_addr
|vpiDirection:1
|vpiIODecl:
\_io_decl: (inv_valid), parent:master
|vpiName:inv_valid
|vpiDirection:1
|vpiIODecl:
\_io_decl: (inv_ack), parent:master
|vpiName:inv_ack
|vpiDirection:2
|vpiIODecl:
\_io_decl: (con_result), parent:master
|vpiName:con_result
|vpiDirection:1
|vpiIODecl:
\_io_decl: (con_valid), parent:master
|vpiName:con_valid
|vpiDirection:1
|vpiIODecl:
\_io_decl: (wr_data), parent:master
|vpiName:wr_data
|vpiDirection:2
|vpiIODecl:
\_io_decl: (wr_data_push), parent:master
|vpiName:wr_data_push
|vpiDirection:2
|vpiIODecl:
\_io_decl: (data_full), parent:master
|vpiName:data_full
|vpiDirection:1
|vpiIODecl:
\_io_decl: (rd_data), parent:master
|vpiName:rd_data
|vpiDirection:1
|vpiIODecl:
\_io_decl: (rd_sub_id), parent:master
|vpiName:rd_sub_id
|vpiDirection:1
|vpiIODecl:
\_io_decl: (rd_data_valid), parent:master
|vpiName:rd_data_valid
|vpiDirection:1
|vpiIODecl:
\_io_decl: (rd_data_ack), parent:master
|vpiName:rd_data_ack
|vpiDirection:2
|vpiInterface:
\_interface: work@l2_requester_interface (l21), file:third_party/cores/taiga/examples/zedboard/taiga_wrapper.sv, line:70, parent:work@taiga_wrapper
|vpiModport:
\_modport: (slave), parent:l21
|vpiName:slave
|vpiIODecl:
\_io_decl: (addr), parent:slave
|vpiName:addr
|vpiDirection:1
|vpiIODecl:
\_io_decl: (be), parent:slave
|vpiName:be
|vpiDirection:1
|vpiIODecl:
\_io_decl: (rnw), parent:slave
|vpiName:rnw
|vpiDirection:1
|vpiIODecl:
\_io_decl: (is_amo), parent:slave
|vpiName:is_amo
|vpiDirection:1
|vpiIODecl:
\_io_decl: (amo_type_or_burst_size), parent:slave
|vpiName:amo_type_or_burst_size
|vpiDirection:1
|vpiIODecl:
\_io_decl: (sub_id), parent:slave
|vpiName:sub_id
|vpiDirection:1
|vpiIODecl:
\_io_decl: (request_push), parent:slave
|vpiName:request_push
|vpiDirection:1
|vpiIODecl:
\_io_decl: (request_full), parent:slave
|vpiName:request_full
|vpiDirection:2
|vpiIODecl:
\_io_decl: (inv_addr), parent:slave
|vpiName:inv_addr
|vpiDirection:2
|vpiIODecl:
\_io_decl: (inv_valid), parent:slave
|vpiName:inv_valid
|vpiDirection:2
|vpiIODecl:
\_io_decl: (inv_ack), parent:slave
|vpiName:inv_ack
|vpiDirection:1
|vpiIODecl:
\_io_decl: (con_result), parent:slave
|vpiName:con_result
|vpiDirection:2
|vpiIODecl:
\_io_decl: (con_valid), parent:slave
|vpiName:con_valid
|vpiDirection:2
|vpiIODecl:
\_io_decl: (wr_data), parent:slave
|vpiName:wr_data
|vpiDirection:1
|vpiIODecl:
\_io_decl: (wr_data_push), parent:slave
|vpiName:wr_data_push
|vpiDirection:1
|vpiIODecl:
\_io_decl: (data_full), parent:slave
|vpiName:data_full
|vpiDirection:2
|vpiIODecl:
\_io_decl: (rd_data), parent:slave
|vpiName:rd_data
|vpiDirection:2
|vpiIODecl:
\_io_decl: (rd_sub_id), parent:slave
|vpiName:rd_sub_id
|vpiDirection:2
|vpiIODecl:
\_io_decl: (rd_data_valid), parent:slave
|vpiName:rd_data_valid
|vpiDirection:2
|vpiIODecl:
\_io_decl: (rd_data_ack), parent:slave
|vpiName:rd_data_ack
|vpiDirection:1
|vpiInterface:
\_interface: work@l2_requester_interface (l21), file:third_party/cores/taiga/examples/zedboard/taiga_wrapper.sv, line:70, parent:work@taiga_wrapper
|vpiNet:
\_logic_net: (addr), line:27, parent:l21
|vpiName:addr
|vpiFullName:work@taiga_wrapper.l21.addr
|vpiNetType:36
|vpiRange:
\_range: , line:27
|vpiLeftRange:
\_constant: , line:27
|vpiConstType:7
|vpiDecompile:29
|vpiSize:32
|INT:29
|vpiRightRange:
\_constant: , line:27
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (be), line:28, parent:l21
|vpiName:be
|vpiFullName:work@taiga_wrapper.l21.be
|vpiNetType:36
|vpiRange:
\_range: , line:28
|vpiLeftRange:
\_constant: , line:28
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiRightRange:
\_constant: , line:28
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (rnw), line:29, parent:l21
|vpiName:rnw
|vpiFullName:work@taiga_wrapper.l21.rnw
|vpiNetType:36
|vpiNet:
\_logic_net: (is_amo), line:30, parent:l21
|vpiName:is_amo
|vpiFullName:work@taiga_wrapper.l21.is_amo
|vpiNetType:36
|vpiNet:
\_logic_net: (amo_type_or_burst_size), line:31, parent:l21
|vpiName:amo_type_or_burst_size
|vpiFullName:work@taiga_wrapper.l21.amo_type_or_burst_size
|vpiNetType:36
|vpiRange:
\_range: , line:31
|vpiLeftRange:
\_constant: , line:31
|vpiConstType:7
|vpiDecompile:4
|vpiSize:32
|INT:4
|vpiRightRange:
\_constant: , line:31
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (sub_id), line:32, parent:l21
|vpiName:sub_id
|vpiFullName:work@taiga_wrapper.l21.sub_id
|vpiNetType:36
|vpiRange:
\_range: , line:32
|vpiLeftRange:
\_constant: , line:32
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:32
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (request_push), line:34, parent:l21
|vpiName:request_push
|vpiFullName:work@taiga_wrapper.l21.request_push
|vpiNetType:36
|vpiNet:
\_logic_net: (request_full), line:35, parent:l21
|vpiName:request_full
|vpiFullName:work@taiga_wrapper.l21.request_full
|vpiNetType:36
|vpiNet:
\_logic_net: (inv_addr), line:37, parent:l21
|vpiName:inv_addr
|vpiFullName:work@taiga_wrapper.l21.inv_addr
|vpiNetType:36
|vpiRange:
\_range: , line:37
|vpiLeftRange:
\_constant: , line:37
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:37
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiNet:
\_logic_net: (inv_valid), line:38, parent:l21
|vpiName:inv_valid
|vpiFullName:work@taiga_wrapper.l21.inv_valid
|vpiNetType:36
|vpiNet:
\_logic_net: (inv_ack), line:39, parent:l21
|vpiName:inv_ack
|vpiFullName:work@taiga_wrapper.l21.inv_ack
|vpiNetType:36
|vpiNet:
\_logic_net: (con_result), line:41, parent:l21
|vpiName:con_result
|vpiFullName:work@taiga_wrapper.l21.con_result
|vpiNetType:36
|vpiNet:
\_logic_net: (con_valid), line:42, parent:l21
|vpiName:con_valid
|vpiFullName:work@taiga_wrapper.l21.con_valid
|vpiNetType:36
|vpiNet:
\_logic_net: (wr_data), line:44, parent:l21
|vpiName:wr_data
|vpiFullName:work@taiga_wrapper.l21.wr_data
|vpiNetType:36
|vpiRange:
\_range: , line:44
|vpiLeftRange:
\_constant: , line:44
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:44
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (wr_data_push), line:45, parent:l21
|vpiName:wr_data_push
|vpiFullName:work@taiga_wrapper.l21.wr_data_push
|vpiNetType:36
|vpiNet:
\_logic_net: (data_full), line:46, parent:l21
|vpiName:data_full
|vpiFullName:work@taiga_wrapper.l21.data_full
|vpiNetType:36
|vpiNet:
\_logic_net: (rd_data), line:48, parent:l21
|vpiName:rd_data
|vpiFullName:work@taiga_wrapper.l21.rd_data
|vpiNetType:36
|vpiRange:
\_range: , line:48
|vpiLeftRange:
\_constant: , line:48
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:48
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (rd_sub_id), line:49, parent:l21
|vpiName:rd_sub_id
|vpiFullName:work@taiga_wrapper.l21.rd_sub_id
|vpiNetType:36
|vpiRange:
\_range: , line:49
|vpiLeftRange:
\_constant: , line:49
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:49
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (rd_data_valid), line:50, parent:l21
|vpiName:rd_data_valid
|vpiFullName:work@taiga_wrapper.l21.rd_data_valid
|vpiNetType:36
|vpiNet:
\_logic_net: (rd_data_ack), line:51, parent:l21
|vpiName:rd_data_ack
|vpiFullName:work@taiga_wrapper.l21.rd_data_ack
|vpiNetType:36
|vpiInstance:
\_module: work@taiga_wrapper (work@taiga_wrapper), file:third_party/cores/taiga/examples/zedboard/taiga_wrapper.sv, line:27
|vpiInterface:
\_interface: work@l2_memory_interface (mem), file:third_party/cores/taiga/examples/zedboard/taiga_wrapper.sv, line:71, parent:work@taiga_wrapper
|vpiDefName:work@l2_memory_interface
|vpiName:mem
|vpiFullName:work@taiga_wrapper.mem
|vpiModport:
\_modport: (master), parent:mem
|vpiName:master
|vpiIODecl:
\_io_decl: (addr), parent:master
|vpiName:addr
|vpiDirection:2
|vpiIODecl:
\_io_decl: (be), parent:master
|vpiName:be
|vpiDirection:2
|vpiIODecl:
\_io_decl: (rnw), parent:master
|vpiName:rnw
|vpiDirection:2
|vpiIODecl:
\_io_decl: (is_amo), parent:master
|vpiName:is_amo
|vpiDirection:2
|vpiIODecl:
\_io_decl: (amo_type_or_burst_size), parent:master
|vpiName:amo_type_or_burst_size
|vpiDirection:2
|vpiIODecl:
\_io_decl: (id), parent:master
|vpiName:id
|vpiDirection:2
|vpiIODecl:
\_io_decl: (request_valid), parent:master
|vpiName:request_valid
|vpiDirection:2
|vpiIODecl:
\_io_decl: (abort), parent:master
|vpiName:abort
|vpiDirection:2
|vpiIODecl:
\_io_decl: (request_pop), parent:master
|vpiName:request_pop
|vpiDirection:1
|vpiIODecl:
\_io_decl: (wr_data), parent:master
|vpiName:wr_data
|vpiDirection:2
|vpiIODecl:
\_io_decl: (wr_data_valid), parent:master
|vpiName:wr_data_valid
|vpiDirection:2
|vpiIODecl:
\_io_decl: (wr_data_read), parent:master
|vpiName:wr_data_read
|vpiDirection:1
|vpiIODecl:
\_io_decl: (rd_data), parent:master
|vpiName:rd_data
|vpiDirection:1
|vpiIODecl:
\_io_decl: (rd_id), parent:master
|vpiName:rd_id
|vpiDirection:1
|vpiIODecl:
\_io_decl: (rd_data_valid), parent:master
|vpiName:rd_data_valid
|vpiDirection:1
|vpiInterface:
\_interface: work@l2_memory_interface (mem), file:third_party/cores/taiga/examples/zedboard/taiga_wrapper.sv, line:71, parent:work@taiga_wrapper
|vpiModport:
\_modport: (slave), parent:mem
|vpiName:slave
|vpiIODecl:
\_io_decl: (addr), parent:slave
|vpiName:addr
|vpiDirection:1
|vpiIODecl:
\_io_decl: (be), parent:slave
|vpiName:be
|vpiDirection:1
|vpiIODecl:
\_io_decl: (rnw), parent:slave
|vpiName:rnw
|vpiDirection:1
|vpiIODecl:
\_io_decl: (is_amo), parent:slave
|vpiName:is_amo
|vpiDirection:1
|vpiIODecl:
\_io_decl: (amo_type_or_burst_size), parent:slave
|vpiName:amo_type_or_burst_size
|vpiDirection:1
|vpiIODecl:
\_io_decl: (id), parent:slave
|vpiName:id
|vpiDirection:1
|vpiIODecl:
\_io_decl: (request_valid), parent:slave
|vpiName:request_valid
|vpiDirection:1
|vpiIODecl:
\_io_decl: (abort), parent:slave
|vpiName:abort
|vpiDirection:1
|vpiIODecl:
\_io_decl: (request_pop), parent:slave
|vpiName:request_pop
|vpiDirection:2
|vpiIODecl:
\_io_decl: (wr_data), parent:slave
|vpiName:wr_data
|vpiDirection:1
|vpiIODecl:
\_io_decl: (wr_data_valid), parent:slave
|vpiName:wr_data_valid
|vpiDirection:1
|vpiIODecl:
\_io_decl: (wr_data_read), parent:slave
|vpiName:wr_data_read
|vpiDirection:2
|vpiIODecl:
\_io_decl: (rd_data), parent:slave
|vpiName:rd_data
|vpiDirection:2
|vpiIODecl:
\_io_decl: (rd_id), parent:slave
|vpiName:rd_id
|vpiDirection:2
|vpiIODecl:
\_io_decl: (rd_data_valid), parent:slave
|vpiName:rd_data_valid
|vpiDirection:2
|vpiInterface:
\_interface: work@l2_memory_interface (mem), file:third_party/cores/taiga/examples/zedboard/taiga_wrapper.sv, line:71, parent:work@taiga_wrapper
|vpiNet:
\_logic_net: (addr), line:70, parent:mem
|vpiName:addr
|vpiFullName:work@taiga_wrapper.mem.addr
|vpiNetType:36
|vpiRange:
\_range: , line:70
|vpiLeftRange:
\_constant: , line:70
|vpiConstType:7
|vpiDecompile:29
|vpiSize:32
|INT:29
|vpiRightRange:
\_constant: , line:70
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (be), line:71, parent:mem
|vpiName:be
|vpiFullName:work@taiga_wrapper.mem.be
|vpiNetType:36
|vpiRange:
\_range: , line:71
|vpiLeftRange:
\_constant: , line:71
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiRightRange:
\_constant: , line:71
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (rnw), line:72, parent:mem
|vpiName:rnw
|vpiFullName:work@taiga_wrapper.mem.rnw
|vpiNetType:36
|vpiNet:
\_logic_net: (is_amo), line:73, parent:mem
|vpiName:is_amo
|vpiFullName:work@taiga_wrapper.mem.is_amo
|vpiNetType:36
|vpiNet:
\_logic_net: (amo_type_or_burst_size), line:74, parent:mem
|vpiName:amo_type_or_burst_size
|vpiFullName:work@taiga_wrapper.mem.amo_type_or_burst_size
|vpiNetType:36
|vpiRange:
\_range: , line:74
|vpiLeftRange:
\_constant: , line:74
|vpiConstType:7
|vpiDecompile:4
|vpiSize:32
|INT:4
|vpiRightRange:
\_constant: , line:74
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (id), line:75, parent:mem
|vpiName:id
|vpiFullName:work@taiga_wrapper.mem.id
|vpiNetType:36
|vpiRange:
\_range: , line:75
|vpiLeftRange:
\_constant: , line:75
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiRightRange:
\_constant: , line:75
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (request_pop), line:77, parent:mem
|vpiName:request_pop
|vpiFullName:work@taiga_wrapper.mem.request_pop
|vpiNetType:36
|vpiNet:
\_logic_net: (request_valid), line:78, parent:mem
|vpiName:request_valid
|vpiFullName:work@taiga_wrapper.mem.request_valid
|vpiNetType:36
|vpiNet:
\_logic_net: (abort), line:80, parent:mem
|vpiName:abort
|vpiFullName:work@taiga_wrapper.mem.abort
|vpiNetType:36
|vpiNet:
\_logic_net: (wr_data), line:82, parent:mem
|vpiName:wr_data
|vpiFullName:work@taiga_wrapper.mem.wr_data
|vpiNetType:36
|vpiRange:
\_range: , line:82
|vpiLeftRange:
\_constant: , line:82
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:82
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (wr_data_valid), line:83, parent:mem
|vpiName:wr_data_valid
|vpiFullName:work@taiga_wrapper.mem.wr_data_valid
|vpiNetType:36
|vpiNet:
\_logic_net: (wr_data_read), line:84, parent:mem
|vpiName:wr_data_read
|vpiFullName:work@taiga_wrapper.mem.wr_data_read
|vpiNetType:36
|vpiNet:
\_logic_net: (rd_data), line:86, parent:mem
|vpiName:rd_data
|vpiFullName:work@taiga_wrapper.mem.rd_data
|vpiNetType:36
|vpiRange:
\_range: , line:86
|vpiLeftRange:
\_constant: , line:86
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:86
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (rd_id), line:87, parent:mem
|vpiName:rd_id
|vpiFullName:work@taiga_wrapper.mem.rd_id
|vpiNetType:36
|vpiRange:
\_range: , line:87
|vpiLeftRange:
\_constant: , line:87
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiRightRange:
\_constant: , line:87
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (rd_data_valid), line:88, parent:mem
|vpiName:rd_data_valid
|vpiFullName:work@taiga_wrapper.mem.rd_data_valid
|vpiNetType:36
|vpiInstance:
\_module: work@taiga_wrapper (work@taiga_wrapper), file:third_party/cores/taiga/examples/zedboard/taiga_wrapper.sv, line:27
|vpiInterface:
\_interface: work@local_memory_interface (instruction_bram), file:third_party/cores/taiga/examples/zedboard/taiga_wrapper.sv, line:230, parent:work@taiga_wrapper
|vpiDefName:work@local_memory_interface
|vpiName:instruction_bram
|vpiFullName:work@taiga_wrapper.instruction_bram
|vpiModport:
\_modport: (master), parent:instruction_bram
|vpiName:master
|vpiIODecl:
\_io_decl: (addr), parent:master
|vpiName:addr
|vpiDirection:2
|vpiIODecl:
\_io_decl: (en), parent:master
|vpiName:en
|vpiDirection:2
|vpiIODecl:
\_io_decl: (be), parent:master
|vpiName:be
|vpiDirection:2
|vpiIODecl:
\_io_decl: (data_in), parent:master
|vpiName:data_in
|vpiDirection:2
|vpiIODecl:
\_io_decl: (data_out), parent:master
|vpiName:data_out
|vpiDirection:1
|vpiInterface:
\_interface: work@local_memory_interface (instruction_bram), file:third_party/cores/taiga/examples/zedboard/taiga_wrapper.sv, line:230, parent:work@taiga_wrapper
|vpiModport:
\_modport: (slave), parent:instruction_bram
|vpiName:slave
|vpiIODecl:
\_io_decl: (addr), parent:slave
|vpiName:addr
|vpiDirection:1
|vpiIODecl:
\_io_decl: (en), parent:slave
|vpiName:en
|vpiDirection:1
|vpiIODecl:
\_io_decl: (be), parent:slave
|vpiName:be
|vpiDirection:1
|vpiIODecl:
\_io_decl: (data_in), parent:slave
|vpiName:data_in
|vpiDirection:1
|vpiIODecl:
\_io_decl: (data_out), parent:slave
|vpiName:data_out
|vpiDirection:2
|vpiInterface:
\_interface: work@local_memory_interface (instruction_bram), file:third_party/cores/taiga/examples/zedboard/taiga_wrapper.sv, line:230, parent:work@taiga_wrapper
|vpiNet:
\_logic_net: (addr), line:25, parent:instruction_bram
|vpiName:addr
|vpiFullName:work@taiga_wrapper.instruction_bram.addr
|vpiNetType:36
|vpiRange:
\_range: , line:25
|vpiLeftRange:
\_constant: , line:25
|vpiConstType:7
|vpiDecompile:29
|vpiSize:32
|INT:29
|vpiRightRange:
\_constant: , line:25
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (en), line:26, parent:instruction_bram
|vpiName:en
|vpiFullName:work@taiga_wrapper.instruction_bram.en
|vpiNetType:36
|vpiNet:
\_logic_net: (be), line:27, parent:instruction_bram
|vpiName:be
|vpiFullName:work@taiga_wrapper.instruction_bram.be
|vpiNetType:36
|vpiRange:
\_range: , line:27
|vpiLeftRange:
\_constant: , line:27
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiRightRange:
\_constant: , line:27
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (data_in), line:28, parent:instruction_bram
|vpiName:data_in
|vpiFullName:work@taiga_wrapper.instruction_bram.data_in
|vpiNetType:36
|vpiRange:
\_range: , line:28
|vpiLeftRange:
\_constant: , line:28
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:28
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (data_out), line:29, parent:instruction_bram
|vpiName:data_out
|vpiFullName:work@taiga_wrapper.instruction_bram.data_out
|vpiNetType:36
|vpiRange:
\_range: , line:29
|vpiLeftRange:
\_constant: , line:29
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:29
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiInstance:
\_module: work@taiga_wrapper (work@taiga_wrapper), file:third_party/cores/taiga/examples/zedboard/taiga_wrapper.sv, line:27
|vpiInterface:
\_interface: work@local_memory_interface (data_bram), file:third_party/cores/taiga/examples/zedboard/taiga_wrapper.sv, line:231, parent:work@taiga_wrapper
|vpiDefName:work@local_memory_interface
|vpiName:data_bram
|vpiFullName:work@taiga_wrapper.data_bram
|vpiModport:
\_modport: (master), parent:data_bram
|vpiName:master
|vpiIODecl:
\_io_decl: (addr), parent:master
|vpiName:addr
|vpiDirection:2
|vpiIODecl:
\_io_decl: (en), parent:master
|vpiName:en
|vpiDirection:2
|vpiIODecl:
\_io_decl: (be), parent:master
|vpiName:be
|vpiDirection:2
|vpiIODecl:
\_io_decl: (data_in), parent:master
|vpiName:data_in
|vpiDirection:2
|vpiIODecl:
\_io_decl: (data_out), parent:master
|vpiName:data_out
|vpiDirection:1
|vpiInterface:
\_interface: work@local_memory_interface (data_bram), file:third_party/cores/taiga/examples/zedboard/taiga_wrapper.sv, line:231, parent:work@taiga_wrapper
|vpiModport:
\_modport: (slave), parent:data_bram
|vpiName:slave
|vpiIODecl:
\_io_decl: (addr), parent:slave
|vpiName:addr
|vpiDirection:1
|vpiIODecl:
\_io_decl: (en), parent:slave
|vpiName:en
|vpiDirection:1
|vpiIODecl:
\_io_decl: (be), parent:slave
|vpiName:be
|vpiDirection:1
|vpiIODecl:
\_io_decl: (data_in), parent:slave
|vpiName:data_in
|vpiDirection:1
|vpiIODecl:
\_io_decl: (data_out), parent:slave
|vpiName:data_out
|vpiDirection:2
|vpiInterface:
\_interface: work@local_memory_interface (data_bram), file:third_party/cores/taiga/examples/zedboard/taiga_wrapper.sv, line:231, parent:work@taiga_wrapper
|vpiNet:
\_logic_net: (addr), line:25, parent:data_bram
|vpiName:addr
|vpiFullName:work@taiga_wrapper.data_bram.addr
|vpiNetType:36
|vpiRange:
\_range: , line:25
|vpiLeftRange:
\_constant: , line:25
|vpiConstType:7
|vpiDecompile:29
|vpiSize:32
|INT:29
|vpiRightRange:
\_constant: , line:25
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (en), line:26, parent:data_bram
|vpiName:en
|vpiFullName:work@taiga_wrapper.data_bram.en
|vpiNetType:36
|vpiNet:
\_logic_net: (be), line:27, parent:data_bram
|vpiName:be
|vpiFullName:work@taiga_wrapper.data_bram.be
|vpiNetType:36
|vpiRange:
\_range: , line:27
|vpiLeftRange:
\_constant: , line:27
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiRightRange:
\_constant: , line:27
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (data_in), line:28, parent:data_bram
|vpiName:data_in
|vpiFullName:work@taiga_wrapper.data_bram.data_in
|vpiNetType:36
|vpiRange:
\_range: , line:28
|vpiLeftRange:
\_constant: , line:28
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:28
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (data_out), line:29, parent:data_bram
|vpiName:data_out
|vpiFullName:work@taiga_wrapper.data_bram.data_out
|vpiNetType:36
|vpiRange:
\_range: , line:29
|vpiLeftRange:
\_constant: , line:29
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:29
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiInstance:
\_module: work@taiga_wrapper (work@taiga_wrapper), file:third_party/cores/taiga/examples/zedboard/taiga_wrapper.sv, line:27
|vpiModule:
\_module: work@taiga (cpu), file:third_party/cores/taiga/examples/zedboard/taiga_wrapper.sv, line:233, parent:work@taiga_wrapper
|vpiDefName:work@taiga
|vpiName:cpu
|vpiFullName:work@taiga_wrapper.cpu
|vpiPort:
\_port: (clk), line:27, parent:cpu
|vpiName:clk
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (clk), line:233
|vpiName:clk
|vpiActual:
\_logic_net: (clk), line:63, parent:work@taiga_wrapper
|vpiName:clk
|vpiFullName:work@taiga_wrapper.clk
|vpiNetType:36
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (clk), line:27, parent:cpu
|vpiName:clk
|vpiFullName:work@taiga_wrapper.cpu.clk
|vpiNetType:36
|vpiPort:
\_port: (rst), line:28, parent:cpu
|vpiName:rst
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (rst), line:233
|vpiName:rst
|vpiActual:
\_logic_net: (rst), line:64, parent:work@taiga_wrapper
|vpiName:rst
|vpiFullName:work@taiga_wrapper.rst
|vpiNetType:36
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (rst), line:28, parent:cpu
|vpiName:rst
|vpiFullName:work@taiga_wrapper.cpu.rst
|vpiNetType:36
|vpiPort:
\_port: (instruction_bram), line:30, parent:cpu
|vpiName:instruction_bram
|vpiDirection:5
|vpiHighConn:
\_ref_obj: (instruction_bram), line:233
|vpiName:instruction_bram
|vpiActual:
\_interface: work@local_memory_interface (instruction_bram), file:third_party/cores/taiga/examples/zedboard/taiga_wrapper.sv, line:230
|vpiDefName:work@local_memory_interface
|vpiName:instruction_bram
|vpiModport:
\_modport: (master)
|vpiName:master
|vpiIODecl:
\_io_decl: (addr)
|vpiName:addr
|vpiDirection:2
|vpiIODecl:
\_io_decl: (en)
|vpiName:en
|vpiDirection:2
|vpiIODecl:
\_io_decl: (be)
|vpiName:be
|vpiDirection:2
|vpiIODecl:
\_io_decl: (data_in)
|vpiName:data_in
|vpiDirection:2
|vpiIODecl:
\_io_decl: (data_out)
|vpiName:data_out
|vpiDirection:1
|vpiInterface:
\_interface: work@local_memory_interface (instruction_bram), file:third_party/cores/taiga/examples/zedboard/taiga_wrapper.sv, line:230
|vpiModport:
\_modport: (slave)
|vpiName:slave
|vpiIODecl:
\_io_decl: (addr)
|vpiName:addr
|vpiDirection:1
|vpiIODecl:
\_io_decl: (en)
|vpiName:en
|vpiDirection:1
|vpiIODecl:
\_io_decl: (be)
|vpiName:be
|vpiDirection:1
|vpiIODecl:
\_io_decl: (data_in)
|vpiName:data_in
|vpiDirection:1
|vpiIODecl:
\_io_decl: (data_out)
|vpiName:data_out
|vpiDirection:2
|vpiInterface:
\_interface: work@local_memory_interface (instruction_bram), file:third_party/cores/taiga/examples/zedboard/taiga_wrapper.sv, line:230
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_modport: (master)
|vpiName:master
|vpiIODecl:
\_io_decl: (addr)
|vpiName:addr
|vpiDirection:2
|vpiExpr:
\_logic_net: (addr), line:25
|vpiName:addr
|vpiNetType:36
|vpiRange:
\_range: , line:25
|vpiLeftRange:
\_constant: , line:25
|vpiConstType:7
|vpiDecompile:29
|vpiSize:32
|INT:29
|vpiRightRange:
\_constant: , line:25
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (en)
|vpiName:en
|vpiDirection:2
|vpiExpr:
\_logic_net: (en), line:26
|vpiName:en
|vpiNetType:36
|vpiIODecl:
\_io_decl: (be)
|vpiName:be
|vpiDirection:2
|vpiExpr:
\_logic_net: (be), line:27
|vpiName:be
|vpiNetType:36
|vpiRange:
\_range: , line:27
|vpiLeftRange:
\_constant: , line:27
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiRightRange:
\_constant: , line:27
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (data_in)
|vpiName:data_in
|vpiDirection:2
|vpiExpr:
\_logic_net: (data_in), line:28
|vpiName:data_in
|vpiNetType:36
|vpiRange:
\_range: , line:28
|vpiLeftRange:
\_constant: , line:28
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:28
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (data_out)
|vpiName:data_out
|vpiDirection:1
|vpiExpr:
\_logic_net: (data_out), line:29
|vpiName:data_out
|vpiNetType:36
|vpiRange:
\_range: , line:29
|vpiLeftRange:
\_constant: , line:29
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:29
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiInterface:
\_interface: work@local_memory_interface (instruction_bram), file:third_party/cores/taiga/examples/zedboard/taiga_wrapper.sv, line:233
|vpiDefName:work@local_memory_interface
|vpiName:instruction_bram
|vpiModport:
\_modport: (master)
|vpiModport:
\_modport: (slave)
|vpiName:slave
|vpiIODecl:
\_io_decl: (addr)
|vpiName:addr
|vpiDirection:1
|vpiExpr:
\_logic_net: (addr), line:25
|vpiIODecl:
\_io_decl: (en)
|vpiName:en
|vpiDirection:1
|vpiExpr:
\_logic_net: (en), line:26
|vpiIODecl:
\_io_decl: (be)
|vpiName:be
|vpiDirection:1
|vpiExpr:
\_logic_net: (be), line:27
|vpiIODecl:
\_io_decl: (data_in)
|vpiName:data_in
|vpiDirection:1
|vpiExpr:
\_logic_net: (data_in), line:28
|vpiIODecl:
\_io_decl: (data_out)
|vpiName:data_out
|vpiDirection:2
|vpiExpr:
\_logic_net: (data_out), line:29
|vpiInterface:
\_interface: work@local_memory_interface (instruction_bram), file:third_party/cores/taiga/examples/zedboard/taiga_wrapper.sv, line:233
|vpiPort:
\_port: (data_bram), line:31, parent:cpu
|vpiName:data_bram
|vpiDirection:5
|vpiHighConn:
\_ref_obj: (data_bram), line:233
|vpiName:data_bram
|vpiActual:
\_interface: work@local_memory_interface (data_bram), file:third_party/cores/taiga/examples/zedboard/taiga_wrapper.sv, line:231
|vpiDefName:work@local_memory_interface
|vpiName:data_bram
|vpiModport:
\_modport: (master)
|vpiName:master
|vpiIODecl:
\_io_decl: (addr)
|vpiName:addr
|vpiDirection:2
|vpiIODecl:
\_io_decl: (en)
|vpiName:en
|vpiDirection:2
|vpiIODecl:
\_io_decl: (be)
|vpiName:be
|vpiDirection:2
|vpiIODecl:
\_io_decl: (data_in)
|vpiName:data_in
|vpiDirection:2
|vpiIODecl:
\_io_decl: (data_out)
|vpiName:data_out
|vpiDirection:1
|vpiInterface:
\_interface: work@local_memory_interface (data_bram), file:third_party/cores/taiga/examples/zedboard/taiga_wrapper.sv, line:231
|vpiModport:
\_modport: (slave)
|vpiName:slave
|vpiIODecl:
\_io_decl: (addr)
|vpiName:addr
|vpiDirection:1
|vpiIODecl:
\_io_decl: (en)
|vpiName:en
|vpiDirection:1
|vpiIODecl:
\_io_decl: (be)
|vpiName:be
|vpiDirection:1
|vpiIODecl:
\_io_decl: (data_in)
|vpiName:data_in
|vpiDirection:1
|vpiIODecl:
\_io_decl: (data_out)
|vpiName:data_out
|vpiDirection:2
|vpiInterface:
\_interface: work@local_memory_interface (data_bram), file:third_party/cores/taiga/examples/zedboard/taiga_wrapper.sv, line:231
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_modport: (master)
|vpiName:master
|vpiIODecl:
\_io_decl: (addr)
|vpiName:addr
|vpiDirection:2
|vpiExpr:
\_logic_net: (addr), line:25
|vpiIODecl:
\_io_decl: (en)
|vpiName:en
|vpiDirection:2
|vpiExpr:
\_logic_net: (en), line:26
|vpiIODecl:
\_io_decl: (be)
|vpiName:be
|vpiDirection:2
|vpiExpr:
\_logic_net: (be), line:27
|vpiIODecl:
\_io_decl: (data_in)
|vpiName:data_in
|vpiDirection:2
|vpiExpr:
\_logic_net: (data_in), line:28
|vpiIODecl:
\_io_decl: (data_out)
|vpiName:data_out
|vpiDirection:1
|vpiExpr:
\_logic_net: (data_out), line:29
|vpiInterface:
\_interface: work@local_memory_interface (data_bram), file:third_party/cores/taiga/examples/zedboard/taiga_wrapper.sv, line:233
|vpiDefName:work@local_memory_interface
|vpiName:data_bram
|vpiModport:
\_modport: (master)
|vpiModport:
\_modport: (slave)
|vpiName:slave
|vpiIODecl:
\_io_decl: (addr)
|vpiName:addr
|vpiDirection:1
|vpiExpr:
\_logic_net: (addr), line:25
|vpiIODecl:
\_io_decl: (en)
|vpiName:en
|vpiDirection:1
|vpiExpr:
\_logic_net: (en), line:26
|vpiIODecl:
\_io_decl: (be)
|vpiName:be
|vpiDirection:1
|vpiExpr:
\_logic_net: (be), line:27
|vpiIODecl:
\_io_decl: (data_in)
|vpiName:data_in
|vpiDirection:1
|vpiExpr:
\_logic_net: (data_in), line:28
|vpiIODecl:
\_io_decl: (data_out)
|vpiName:data_out
|vpiDirection:2
|vpiExpr:
\_logic_net: (data_out), line:29
|vpiInterface:
\_interface: work@local_memory_interface (data_bram), file:third_party/cores/taiga/examples/zedboard/taiga_wrapper.sv, line:233
|vpiPort:
\_port: (m_axi), line:33, parent:cpu
|vpiName:m_axi
|vpiDirection:5
|vpiHighConn:
\_ref_obj: (m_axi), line:233
|vpiName:m_axi
|vpiActual:
\_interface: work@axi_interface (m_axi), file:third_party/cores/taiga/examples/zedboard/taiga_wrapper.sv, line:67
|vpiDefName:work@axi_interface
|vpiName:m_axi
|vpiModport:
\_modport: (master)
|vpiName:master
|vpiIODecl:
\_io_decl: (arready)
|vpiName:arready
|vpiDirection:1
|vpiIODecl:
\_io_decl: (rvalid)
|vpiName:rvalid
|vpiDirection:1
|vpiIODecl:
\_io_decl: (rdata)
|vpiName:rdata
|vpiDirection:1
|vpiIODecl:
\_io_decl: (rresp)
|vpiName:rresp
|vpiDirection:1
|vpiIODecl:
\_io_decl: (rlast)
|vpiName:rlast
|vpiDirection:1
|vpiIODecl:
\_io_decl: (rid)
|vpiName:rid
|vpiDirection:1
|vpiIODecl:
\_io_decl: (awready)
|vpiName:awready
|vpiDirection:1
|vpiIODecl:
\_io_decl: (wready)
|vpiName:wready
|vpiDirection:1
|vpiIODecl:
\_io_decl: (bvalid)
|vpiName:bvalid
|vpiDirection:1
|vpiIODecl:
\_io_decl: (bresp)
|vpiName:bresp
|vpiDirection:1
|vpiIODecl:
\_io_decl: (bid)
|vpiName:bid
|vpiDirection:1
|vpiIODecl:
\_io_decl: (arvalid)
|vpiName:arvalid
|vpiDirection:2
|vpiIODecl:
\_io_decl: (araddr)
|vpiName:araddr
|vpiDirection:2
|vpiIODecl:
\_io_decl: (arlen)
|vpiName:arlen
|vpiDirection:2
|vpiIODecl:
\_io_decl: (arsize)
|vpiName:arsize
|vpiDirection:2
|vpiIODecl:
\_io_decl: (arburst)
|vpiName:arburst
|vpiDirection:2
|vpiIODecl:
\_io_decl: (arcache)
|vpiName:arcache
|vpiDirection:2
|vpiIODecl:
\_io_decl: (arid)
|vpiName:arid
|vpiDirection:2
|vpiIODecl:
\_io_decl: (rready)
|vpiName:rready
|vpiDirection:2
|vpiIODecl:
\_io_decl: (awvalid)
|vpiName:awvalid
|vpiDirection:2
|vpiIODecl:
\_io_decl: (awaddr)
|vpiName:awaddr
|vpiDirection:2
|vpiIODecl:
\_io_decl: (awlen)
|vpiName:awlen
|vpiDirection:2
|vpiIODecl:
\_io_decl: (awsize)
|vpiName:awsize
|vpiDirection:2
|vpiIODecl:
\_io_decl: (awburst)
|vpiName:awburst
|vpiDirection:2
|vpiIODecl:
\_io_decl: (awcache)
|vpiName:awcache
|vpiDirection:2
|vpiIODecl:
\_io_decl: (awid)
|vpiName:awid
|vpiDirection:2
|vpiIODecl:
\_io_decl: (wvalid)
|vpiName:wvalid
|vpiDirection:2
|vpiIODecl:
\_io_decl: (wdata)
|vpiName:wdata
|vpiDirection:2
|vpiIODecl:
\_io_decl: (wstrb)
|vpiName:wstrb
|vpiDirection:2
|vpiIODecl:
\_io_decl: (wlast)
|vpiName:wlast
|vpiDirection:2
|vpiIODecl:
\_io_decl: (bready)
|vpiName:bready
|vpiDirection:2
|vpiInterface:
\_interface: work@axi_interface (m_axi), file:third_party/cores/taiga/examples/zedboard/taiga_wrapper.sv, line:67
|vpiModport:
\_modport: (slave)
|vpiName:slave
|vpiIODecl:
\_io_decl: (arvalid)
|vpiName:arvalid
|vpiDirection:1
|vpiIODecl:
\_io_decl: (araddr)
|vpiName:araddr
|vpiDirection:1
|vpiIODecl:
\_io_decl: (arlen)
|vpiName:arlen
|vpiDirection:1
|vpiIODecl:
\_io_decl: (arsize)
|vpiName:arsize
|vpiDirection:1
|vpiIODecl:
\_io_decl: (arburst)
|vpiName:arburst
|vpiDirection:1
|vpiIODecl:
\_io_decl: (arcache)
|vpiName:arcache
|vpiDirection:1
|vpiIODecl:
\_io_decl: (rready)
|vpiName:rready
|vpiDirection:1
|vpiIODecl:
\_io_decl: (awvalid)
|vpiName:awvalid
|vpiDirection:1
|vpiIODecl:
\_io_decl: (awaddr)
|vpiName:awaddr
|vpiDirection:1
|vpiIODecl:
\_io_decl: (awlen)
|vpiName:awlen
|vpiDirection:1
|vpiIODecl:
\_io_decl: (awsize)
|vpiName:awsize
|vpiDirection:1
|vpiIODecl:
\_io_decl: (awburst)
|vpiName:awburst
|vpiDirection:1
|vpiIODecl:
\_io_decl: (awcache)
|vpiName:awcache
|vpiDirection:1
|vpiIODecl:
\_io_decl: (arid)
|vpiName:arid
|vpiDirection:1
|vpiIODecl:
\_io_decl: (wvalid)
|vpiName:wvalid
|vpiDirection:1
|vpiIODecl:
\_io_decl: (wdata)
|vpiName:wdata
|vpiDirection:1
|vpiIODecl:
\_io_decl: (wstrb)
|vpiName:wstrb
|vpiDirection:1
|vpiIODecl:
\_io_decl: (wlast)
|vpiName:wlast
|vpiDirection:1
|vpiIODecl:
\_io_decl: (awid)
|vpiName:awid
|vpiDirection:1
|vpiIODecl:
\_io_decl: (bready)
|vpiName:bready
|vpiDirection:1
|vpiIODecl:
\_io_decl: (arready)
|vpiName:arready
|vpiDirection:2
|vpiIODecl:
\_io_decl: (rvalid)
|vpiName:rvalid
|vpiDirection:2
|vpiIODecl:
\_io_decl: (rdata)
|vpiName:rdata
|vpiDirection:2
|vpiIODecl:
\_io_decl: (rresp)
|vpiName:rresp
|vpiDirection:2
|vpiIODecl:
\_io_decl: (rlast)
|vpiName:rlast
|vpiDirection:2
|vpiIODecl:
\_io_decl: (rid)
|vpiName:rid
|vpiDirection:2
|vpiIODecl:
\_io_decl: (awready)
|vpiName:awready
|vpiDirection:2
|vpiIODecl:
\_io_decl: (wready)
|vpiName:wready
|vpiDirection:2
|vpiIODecl:
\_io_decl: (bvalid)
|vpiName:bvalid
|vpiDirection:2
|vpiIODecl:
\_io_decl: (bresp)
|vpiName:bresp
|vpiDirection:2
|vpiIODecl:
\_io_decl: (bid)
|vpiName:bid
|vpiDirection:2
|vpiInterface:
\_interface: work@axi_interface (m_axi), file:third_party/cores/taiga/examples/zedboard/taiga_wrapper.sv, line:67
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_modport: (master)
|vpiName:master
|vpiIODecl:
\_io_decl: (arready)
|vpiName:arready
|vpiDirection:1
|vpiExpr:
\_logic_net: (arready), line:29
|vpiName:arready
|vpiNetType:36
|vpiIODecl:
\_io_decl: (rvalid)
|vpiName:rvalid
|vpiDirection:1
|vpiExpr:
\_logic_net: (rvalid), line:40
|vpiName:rvalid
|vpiNetType:36
|vpiIODecl:
\_io_decl: (rdata)
|vpiName:rdata
|vpiDirection:1
|vpiExpr:
\_logic_net: (rdata), line:41
|vpiName:rdata
|vpiNetType:36
|vpiRange:
\_range: , line:41
|vpiLeftRange:
\_constant: , line:41
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiRightRange:
\_constant: , line:41
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (rresp)
|vpiName:rresp
|vpiDirection:1
|vpiExpr:
\_logic_net: (rresp), line:42
|vpiName:rresp
|vpiNetType:36
|vpiRange:
\_range: , line:42
|vpiLeftRange:
\_constant: , line:42
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:42
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (rlast)
|vpiName:rlast
|vpiDirection:1
|vpiExpr:
\_logic_net: (rlast), line:43
|vpiName:rlast
|vpiNetType:36
|vpiIODecl:
\_io_decl: (rid)
|vpiName:rid
|vpiDirection:1
|vpiExpr:
\_logic_net: (rid), line:44
|vpiName:rid
|vpiNetType:36
|vpiRange:
\_range: , line:44
|vpiLeftRange:
\_constant: , line:44
|vpiConstType:7
|vpiDecompile:5
|vpiSize:32
|INT:5
|vpiRightRange:
\_constant: , line:44
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (awready)
|vpiName:awready
|vpiDirection:1
|vpiExpr:
\_logic_net: (awready), line:48
|vpiName:awready
|vpiNetType:36
|vpiIODecl:
\_io_decl: (wready)
|vpiName:wready
|vpiDirection:1
|vpiExpr:
\_logic_net: (wready), line:58
|vpiName:wready
|vpiNetType:36
|vpiIODecl:
\_io_decl: (bvalid)
|vpiName:bvalid
|vpiDirection:1
|vpiExpr:
\_logic_net: (bvalid), line:66
|vpiName:bvalid
|vpiNetType:36
|vpiIODecl:
\_io_decl: (bresp)
|vpiName:bresp
|vpiDirection:1
|vpiExpr:
\_logic_net: (bresp), line:67
|vpiName:bresp
|vpiNetType:36
|vpiRange:
\_range: , line:67
|vpiLeftRange:
\_constant: , line:67
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:67
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (bid)
|vpiName:bid
|vpiDirection:1
|vpiExpr:
\_logic_net: (bid), line:68
|vpiName:bid
|vpiNetType:36
|vpiRange:
\_range: , line:68
|vpiLeftRange:
\_constant: , line:68
|vpiConstType:7
|vpiDecompile:5
|vpiSize:32
|INT:5
|vpiRightRange:
\_constant: , line:68
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (arvalid)
|vpiName:arvalid
|vpiDirection:2
|vpiExpr:
\_logic_net: (arvalid), line:30
|vpiName:arvalid
|vpiNetType:36
|vpiIODecl:
\_io_decl: (araddr)
|vpiName:araddr
|vpiDirection:2
|vpiExpr:
\_logic_net: (araddr), line:31
|vpiName:araddr
|vpiNetType:36
|vpiRange:
\_range: , line:31
|vpiLeftRange:
\_constant: , line:31
|vpiConstType:7
|vpiDecompile:18446744073709551615
|vpiSize:32
|INT:-1
|vpiRightRange:
\_constant: , line:31
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (arlen)
|vpiName:arlen
|vpiDirection:2
|vpiExpr:
\_logic_net: (arlen), line:32
|vpiName:arlen
|vpiNetType:36
|vpiRange:
\_range: , line:32
|vpiLeftRange:
\_constant: , line:32
|vpiConstType:7
|vpiDecompile:7
|vpiSize:32
|INT:7
|vpiRightRange:
\_constant: , line:32
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (arsize)
|vpiName:arsize
|vpiDirection:2
|vpiExpr:
\_logic_net: (arsize), line:33
|vpiName:arsize
|vpiNetType:36
|vpiRange:
\_range: , line:33
|vpiLeftRange:
\_constant: , line:33
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiRightRange:
\_constant: , line:33
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (arburst)
|vpiName:arburst
|vpiDirection:2
|vpiExpr:
\_logic_net: (arburst), line:34
|vpiName:arburst
|vpiNetType:36
|vpiRange:
\_range: , line:34
|vpiLeftRange:
\_constant: , line:34
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:34
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (arcache)
|vpiName:arcache
|vpiDirection:2
|vpiExpr:
\_logic_net: (arcache), line:35
|vpiName:arcache
|vpiNetType:36
|vpiRange:
\_range: , line:35
|vpiLeftRange:
\_constant: , line:35
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiRightRange:
\_constant: , line:35
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (arid)
|vpiName:arid
|vpiDirection:2
|vpiExpr:
\_logic_net: (arid), line:36
|vpiName:arid
|vpiNetType:36
|vpiRange:
\_range: , line:36
|vpiLeftRange:
\_constant: , line:36
|vpiConstType:7
|vpiDecompile:5
|vpiSize:32
|INT:5
|vpiRightRange:
\_constant: , line:36
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (rready)
|vpiName:rready
|vpiDirection:2
|vpiExpr:
\_logic_net: (rready), line:39
|vpiName:rready
|vpiNetType:36
|vpiIODecl:
\_io_decl: (awvalid)
|vpiName:awvalid
|vpiDirection:2
|vpiExpr:
\_logic_net: (awvalid), line:49
|vpiName:awvalid
|vpiNetType:36
|vpiIODecl:
\_io_decl: (awaddr)
|vpiName:awaddr
|vpiDirection:2
|vpiExpr:
\_logic_net: (awaddr), line:50
|vpiName:awaddr
|vpiNetType:36
|vpiRange:
\_range: , line:50
|vpiLeftRange:
\_constant: , line:50
|vpiConstType:7
|vpiDecompile:18446744073709551615
|vpiSize:32
|INT:-1
|vpiRightRange:
\_constant: , line:50
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (awlen)
|vpiName:awlen
|vpiDirection:2
|vpiExpr:
\_logic_net: (awlen), line:51
|vpiName:awlen
|vpiNetType:36
|vpiRange:
\_range: , line:51
|vpiLeftRange:
\_constant: , line:51
|vpiConstType:7
|vpiDecompile:7
|vpiSize:32
|INT:7
|vpiRightRange:
\_constant: , line:51
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (awsize)
|vpiName:awsize
|vpiDirection:2
|vpiExpr:
\_logic_net: (awsize), line:52
|vpiName:awsize
|vpiNetType:36
|vpiRange:
\_range: , line:52
|vpiLeftRange:
\_constant: , line:52
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiRightRange:
\_constant: , line:52
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (awburst)
|vpiName:awburst
|vpiDirection:2
|vpiExpr:
\_logic_net: (awburst), line:53
|vpiName:awburst
|vpiNetType:36
|vpiRange:
\_range: , line:53
|vpiLeftRange:
\_constant: , line:53
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:53
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (awcache)
|vpiName:awcache
|vpiDirection:2
|vpiExpr:
\_logic_net: (awcache), line:54
|vpiName:awcache
|vpiNetType:36
|vpiRange:
\_range: , line:54
|vpiLeftRange:
\_constant: , line:54
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiRightRange:
\_constant: , line:54
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (awid)
|vpiName:awid
|vpiDirection:2
|vpiExpr:
\_logic_net: (awid), line:55
|vpiName:awid
|vpiNetType:36
|vpiRange:
\_range: , line:55
|vpiLeftRange:
\_constant: , line:55
|vpiConstType:7
|vpiDecompile:5
|vpiSize:32
|INT:5
|vpiRightRange:
\_constant: , line:55
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (wvalid)
|vpiName:wvalid
|vpiDirection:2
|vpiExpr:
\_logic_net: (wvalid), line:59
|vpiName:wvalid
|vpiNetType:36
|vpiIODecl:
\_io_decl: (wdata)
|vpiName:wdata
|vpiDirection:2
|vpiExpr:
\_logic_net: (wdata), line:60
|vpiName:wdata
|vpiNetType:36
|vpiRange:
\_range: , line:60
|vpiLeftRange:
\_constant: , line:60
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiRightRange:
\_constant: , line:60
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (wstrb)
|vpiName:wstrb
|vpiDirection:2
|vpiExpr:
\_logic_net: (wstrb), line:61
|vpiName:wstrb
|vpiNetType:36
|vpiRange:
\_range: , line:61
|vpiLeftRange:
\_constant: , line:61
|vpiConstType:7
|vpiDecompile:18446744073709551615
|vpiSize:32
|INT:-1
|vpiRightRange:
\_constant: , line:61
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (wlast)
|vpiName:wlast
|vpiDirection:2
|vpiExpr:
\_logic_net: (wlast), line:62
|vpiName:wlast
|vpiNetType:36
|vpiIODecl:
\_io_decl: (bready)
|vpiName:bready
|vpiDirection:2
|vpiExpr:
\_logic_net: (bready), line:65
|vpiName:bready
|vpiNetType:36
|vpiInterface:
\_interface: work@axi_interface (m_axi), file:third_party/cores/taiga/examples/zedboard/taiga_wrapper.sv, line:233
|vpiDefName:work@axi_interface
|vpiName:m_axi
|vpiModport:
\_modport: (master)
|vpiModport:
\_modport: (slave)
|vpiName:slave
|vpiIODecl:
\_io_decl: (arvalid)
|vpiName:arvalid
|vpiDirection:1
|vpiExpr:
\_logic_net: (arvalid), line:30
|vpiIODecl:
\_io_decl: (araddr)
|vpiName:araddr
|vpiDirection:1
|vpiExpr:
\_logic_net: (araddr), line:31
|vpiIODecl:
\_io_decl: (arlen)
|vpiName:arlen
|vpiDirection:1
|vpiExpr:
\_logic_net: (arlen), line:32
|vpiIODecl:
\_io_decl: (arsize)
|vpiName:arsize
|vpiDirection:1
|vpiExpr:
\_logic_net: (arsize), line:33
|vpiIODecl:
\_io_decl: (arburst)
|vpiName:arburst
|vpiDirection:1
|vpiExpr:
\_logic_net: (arburst), line:34
|vpiIODecl:
\_io_decl: (arcache)
|vpiName:arcache
|vpiDirection:1
|vpiExpr:
\_logic_net: (arcache), line:35
|vpiIODecl:
\_io_decl: (rready)
|vpiName:rready
|vpiDirection:1
|vpiExpr:
\_logic_net: (rready), line:39
|vpiIODecl:
\_io_decl: (awvalid)
|vpiName:awvalid
|vpiDirection:1
|vpiExpr:
\_logic_net: (awvalid), line:49
|vpiIODecl:
\_io_decl: (awaddr)
|vpiName:awaddr
|vpiDirection:1
|vpiExpr:
\_logic_net: (awaddr), line:50
|vpiIODecl:
\_io_decl: (awlen)
|vpiName:awlen
|vpiDirection:1
|vpiExpr:
\_logic_net: (awlen), line:51
|vpiIODecl:
\_io_decl: (awsize)
|vpiName:awsize
|vpiDirection:1
|vpiExpr:
\_logic_net: (awsize), line:52
|vpiIODecl:
\_io_decl: (awburst)
|vpiName:awburst
|vpiDirection:1
|vpiExpr:
\_logic_net: (awburst), line:53
|vpiIODecl:
\_io_decl: (awcache)
|vpiName:awcache
|vpiDirection:1
|vpiExpr:
\_logic_net: (awcache), line:54
|vpiIODecl:
\_io_decl: (arid)
|vpiName:arid
|vpiDirection:1
|vpiExpr:
\_logic_net: (arid), line:36
|vpiIODecl:
\_io_decl: (wvalid)
|vpiName:wvalid
|vpiDirection:1
|vpiExpr:
\_logic_net: (wvalid), line:59
|vpiIODecl:
\_io_decl: (wdata)
|vpiName:wdata
|vpiDirection:1
|vpiExpr:
\_logic_net: (wdata), line:60
|vpiIODecl:
\_io_decl: (wstrb)
|vpiName:wstrb
|vpiDirection:1
|vpiExpr:
\_logic_net: (wstrb), line:61
|vpiIODecl:
\_io_decl: (wlast)
|vpiName:wlast
|vpiDirection:1
|vpiExpr:
\_logic_net: (wlast), line:62
|vpiIODecl:
\_io_decl: (awid)
|vpiName:awid
|vpiDirection:1
|vpiExpr:
\_logic_net: (awid), line:55
|vpiIODecl:
\_io_decl: (bready)
|vpiName:bready
|vpiDirection:1
|vpiExpr:
\_logic_net: (bready), line:65
|vpiIODecl:
\_io_decl: (arready)
|vpiName:arready
|vpiDirection:2
|vpiExpr:
\_logic_net: (arready), line:29
|vpiIODecl:
\_io_decl: (rvalid)
|vpiName:rvalid
|vpiDirection:2
|vpiExpr:
\_logic_net: (rvalid), line:40
|vpiIODecl:
\_io_decl: (rdata)
|vpiName:rdata
|vpiDirection:2
|vpiExpr:
\_logic_net: (rdata), line:41
|vpiIODecl:
\_io_decl: (rresp)
|vpiName:rresp
|vpiDirection:2
|vpiExpr:
\_logic_net: (rresp), line:42
|vpiIODecl:
\_io_decl: (rlast)
|vpiName:rlast
|vpiDirection:2
|vpiExpr:
\_logic_net: (rlast), line:43
|vpiIODecl:
\_io_decl: (rid)
|vpiName:rid
|vpiDirection:2
|vpiExpr:
\_logic_net: (rid), line:44
|vpiIODecl:
\_io_decl: (awready)
|vpiName:awready
|vpiDirection:2
|vpiExpr:
\_logic_net: (awready), line:48
|vpiIODecl:
\_io_decl: (wready)
|vpiName:wready
|vpiDirection:2
|vpiExpr:
\_logic_net: (wready), line:58
|vpiIODecl:
\_io_decl: (bvalid)
|vpiName:bvalid
|vpiDirection:2
|vpiExpr:
\_logic_net: (bvalid), line:66
|vpiIODecl:
\_io_decl: (bresp)
|vpiName:bresp
|vpiDirection:2
|vpiExpr:
\_logic_net: (bresp), line:67
|vpiIODecl:
\_io_decl: (bid)
|vpiName:bid
|vpiDirection:2
|vpiExpr:
\_logic_net: (bid), line:68
|vpiInterface:
\_interface: work@axi_interface (m_axi), file:third_party/cores/taiga/examples/zedboard/taiga_wrapper.sv, line:233
|vpiPort:
\_port: (m_avalon), line:34, parent:cpu
|vpiName:m_avalon
|vpiDirection:5
|vpiHighConn:
\_ref_obj: (m_avalon), line:233
|vpiName:m_avalon
|vpiActual:
\_interface: work@avalon_interface (m_avalon), file:third_party/cores/taiga/examples/zedboard/taiga_wrapper.sv, line:68
|vpiDefName:work@avalon_interface
|vpiName:m_avalon
|vpiModport:
\_modport: (master)
|vpiName:master
|vpiIODecl:
\_io_decl: (readdata)
|vpiName:readdata
|vpiDirection:1
|vpiIODecl:
\_io_decl: (waitrequest)
|vpiName:waitrequest
|vpiDirection:1
|vpiIODecl:
\_io_decl: (readdatavalid)
|vpiName:readdatavalid
|vpiDirection:1
|vpiIODecl:
\_io_decl: (writeresponsevalid)
|vpiName:writeresponsevalid
|vpiDirection:1
|vpiIODecl:
\_io_decl: (addr)
|vpiName:addr
|vpiDirection:2
|vpiIODecl:
\_io_decl: (read)
|vpiName:read
|vpiDirection:2
|vpiIODecl:
\_io_decl: (write)
|vpiName:write
|vpiDirection:2
|vpiIODecl:
\_io_decl: (byteenable)
|vpiName:byteenable
|vpiDirection:2
|vpiIODecl:
\_io_decl: (writedata)
|vpiName:writedata
|vpiDirection:2
|vpiInterface:
\_interface: work@avalon_interface (m_avalon), file:third_party/cores/taiga/examples/zedboard/taiga_wrapper.sv, line:68
|vpiModport:
\_modport: (slave)
|vpiName:slave
|vpiIODecl:
\_io_decl: (readdata)
|vpiName:readdata
|vpiDirection:2
|vpiIODecl:
\_io_decl: (waitrequest)
|vpiName:waitrequest
|vpiDirection:2
|vpiIODecl:
\_io_decl: (readdatavalid)
|vpiName:readdatavalid
|vpiDirection:2
|vpiIODecl:
\_io_decl: (writeresponsevalid)
|vpiName:writeresponsevalid
|vpiDirection:2
|vpiIODecl:
\_io_decl: (addr)
|vpiName:addr
|vpiDirection:1
|vpiIODecl:
\_io_decl: (read)
|vpiName:read
|vpiDirection:1
|vpiIODecl:
\_io_decl: (write)
|vpiName:write
|vpiDirection:1
|vpiIODecl:
\_io_decl: (byteenable)
|vpiName:byteenable
|vpiDirection:1
|vpiIODecl:
\_io_decl: (writedata)
|vpiName:writedata
|vpiDirection:1
|vpiInterface:
\_interface: work@avalon_interface (m_avalon), file:third_party/cores/taiga/examples/zedboard/taiga_wrapper.sv, line:68
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_modport: (master)
|vpiName:master
|vpiIODecl:
\_io_decl: (readdata)
|vpiName:readdata
|vpiDirection:1
|vpiExpr:
\_logic_net: (readdata), line:92
|vpiName:readdata
|vpiNetType:36
|vpiRange:
\_range: , line:92
|vpiLeftRange:
\_constant: , line:92
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:92
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (waitrequest)
|vpiName:waitrequest
|vpiDirection:1
|vpiExpr:
\_logic_net: (waitrequest), line:94
|vpiName:waitrequest
|vpiNetType:36
|vpiIODecl:
\_io_decl: (readdatavalid)
|vpiName:readdatavalid
|vpiDirection:1
|vpiExpr:
\_logic_net: (readdatavalid), line:95
|vpiName:readdatavalid
|vpiNetType:36
|vpiIODecl:
\_io_decl: (writeresponsevalid)
|vpiName:writeresponsevalid
|vpiDirection:1
|vpiExpr:
\_logic_net: (writeresponsevalid), line:96
|vpiName:writeresponsevalid
|vpiNetType:36
|vpiIODecl:
\_io_decl: (addr)
|vpiName:addr
|vpiDirection:2
|vpiExpr:
\_logic_net: (addr), line:25
|vpiIODecl:
\_io_decl: (read)
|vpiName:read
|vpiDirection:2
|vpiExpr:
\_logic_net: (read), line:89
|vpiName:read
|vpiNetType:36
|vpiIODecl:
\_io_decl: (write)
|vpiName:write
|vpiDirection:2
|vpiExpr:
\_logic_net: (write), line:90
|vpiName:write
|vpiNetType:36
|vpiIODecl:
\_io_decl: (byteenable)
|vpiName:byteenable
|vpiDirection:2
|vpiExpr:
\_logic_net: (byteenable), line:91
|vpiName:byteenable
|vpiNetType:36
|vpiRange:
\_range: , line:91
|vpiLeftRange:
\_constant: , line:91
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiRightRange:
\_constant: , line:91
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (writedata)
|vpiName:writedata
|vpiDirection:2
|vpiExpr:
\_logic_net: (writedata), line:93
|vpiName:writedata
|vpiNetType:36
|vpiRange:
\_range: , line:93
|vpiLeftRange:
\_constant: , line:93
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:93
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiInterface:
\_interface: work@avalon_interface (m_avalon), file:third_party/cores/taiga/examples/zedboard/taiga_wrapper.sv, line:233
|vpiDefName:work@avalon_interface
|vpiName:m_avalon
|vpiModport:
\_modport: (master)
|vpiModport:
\_modport: (slave)
|vpiName:slave
|vpiIODecl:
\_io_decl: (readdata)
|vpiName:readdata
|vpiDirection:2
|vpiExpr:
\_logic_net: (readdata), line:92
|vpiIODecl:
\_io_decl: (waitrequest)
|vpiName:waitrequest
|vpiDirection:2
|vpiExpr:
\_logic_net: (waitrequest), line:94
|vpiIODecl:
\_io_decl: (readdatavalid)
|vpiName:readdatavalid
|vpiDirection:2
|vpiExpr:
\_logic_net: (readdatavalid), line:95
|vpiIODecl:
\_io_decl: (writeresponsevalid)
|vpiName:writeresponsevalid
|vpiDirection:2
|vpiExpr:
\_logic_net: (writeresponsevalid), line:96
|vpiIODecl:
\_io_decl: (addr)
|vpiName:addr
|vpiDirection:1
|vpiExpr:
\_logic_net: (addr), line:25
|vpiIODecl:
\_io_decl: (read)
|vpiName:read
|vpiDirection:1
|vpiExpr:
\_logic_net: (read), line:89
|vpiIODecl:
\_io_decl: (write)
|vpiName:write
|vpiDirection:1
|vpiExpr:
\_logic_net: (write), line:90
|vpiIODecl:
\_io_decl: (byteenable)
|vpiName:byteenable
|vpiDirection:1
|vpiExpr:
\_logic_net: (byteenable), line:91
|vpiIODecl:
\_io_decl: (writedata)
|vpiName:writedata
|vpiDirection:1
|vpiExpr:
\_logic_net: (writedata), line:93
|vpiInterface:
\_interface: work@avalon_interface (m_avalon), file:third_party/cores/taiga/examples/zedboard/taiga_wrapper.sv, line:233
|vpiPort:
\_port: (m_wishbone), line:35, parent:cpu
|vpiName:m_wishbone
|vpiDirection:5
|vpiHighConn:
\_ref_obj: (m_wishbone), line:233
|vpiName:m_wishbone
|vpiActual:
\_interface: work@wishbone_interface (m_wishbone), file:third_party/cores/taiga/examples/zedboard/taiga_wrapper.sv, line:69
|vpiDefName:work@wishbone_interface
|vpiName:m_wishbone
|vpiModport:
\_modport: (master)
|vpiName:master
|vpiIODecl:
\_io_decl: (readdata)
|vpiName:readdata
|vpiDirection:1
|vpiIODecl:
\_io_decl: (ack)
|vpiName:ack
|vpiDirection:1
|vpiIODecl:
\_io_decl: (addr)
|vpiName:addr
|vpiDirection:2
|vpiIODecl:
\_io_decl: (we)
|vpiName:we
|vpiDirection:2
|vpiIODecl:
\_io_decl: (sel)
|vpiName:sel
|vpiDirection:2
|vpiIODecl:
\_io_decl: (writedata)
|vpiName:writedata
|vpiDirection:2
|vpiIODecl:
\_io_decl: (stb)
|vpiName:stb
|vpiDirection:2
|vpiIODecl:
\_io_decl: (cyc)
|vpiName:cyc
|vpiDirection:2
|vpiInterface:
\_interface: work@wishbone_interface (m_wishbone), file:third_party/cores/taiga/examples/zedboard/taiga_wrapper.sv, line:69
|vpiModport:
\_modport: (slave)
|vpiName:slave
|vpiIODecl:
\_io_decl: (readdata)
|vpiName:readdata
|vpiDirection:2
|vpiIODecl:
\_io_decl: (ack)
|vpiName:ack
|vpiDirection:2
|vpiIODecl:
\_io_decl: (addr)
|vpiName:addr
|vpiDirection:1
|vpiIODecl:
\_io_decl: (we)
|vpiName:we
|vpiDirection:1
|vpiIODecl:
\_io_decl: (sel)
|vpiName:sel
|vpiDirection:1
|vpiIODecl:
\_io_decl: (writedata)
|vpiName:writedata
|vpiDirection:1
|vpiIODecl:
\_io_decl: (stb)
|vpiName:stb
|vpiDirection:1
|vpiIODecl:
\_io_decl: (cyc)
|vpiName:cyc
|vpiDirection:1
|vpiInterface:
\_interface: work@wishbone_interface (m_wishbone), file:third_party/cores/taiga/examples/zedboard/taiga_wrapper.sv, line:69
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_modport: (master)
|vpiName:master
|vpiIODecl:
\_io_decl: (readdata)
|vpiName:readdata
|vpiDirection:1
|vpiExpr:
\_logic_net: (readdata), line:92
|vpiIODecl:
\_io_decl: (ack)
|vpiName:ack
|vpiDirection:1
|vpiExpr:
\_logic_net: (ack), line:113
|vpiName:ack
|vpiNetType:36
|vpiIODecl:
\_io_decl: (addr)
|vpiName:addr
|vpiDirection:2
|vpiExpr:
\_logic_net: (addr), line:25
|vpiIODecl:
\_io_decl: (we)
|vpiName:we
|vpiDirection:2
|vpiExpr:
\_logic_net: (we), line:107
|vpiName:we
|vpiNetType:36
|vpiIODecl:
\_io_decl: (sel)
|vpiName:sel
|vpiDirection:2
|vpiExpr:
\_logic_net: (sel), line:108
|vpiName:sel
|vpiNetType:36
|vpiRange:
\_range: , line:108
|vpiLeftRange:
\_constant: , line:108
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiRightRange:
\_constant: , line:108
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (writedata)
|vpiName:writedata
|vpiDirection:2
|vpiExpr:
\_logic_net: (writedata), line:93
|vpiIODecl:
\_io_decl: (stb)
|vpiName:stb
|vpiDirection:2
|vpiExpr:
\_logic_net: (stb), line:111
|vpiName:stb
|vpiNetType:36
|vpiIODecl:
\_io_decl: (cyc)
|vpiName:cyc
|vpiDirection:2
|vpiExpr:
\_logic_net: (cyc), line:112
|vpiName:cyc
|vpiNetType:36
|vpiInterface:
\_interface: work@wishbone_interface (m_wishbone), file:third_party/cores/taiga/examples/zedboard/taiga_wrapper.sv, line:233
|vpiDefName:work@wishbone_interface
|vpiName:m_wishbone
|vpiModport:
\_modport: (master)
|vpiModport:
\_modport: (slave)
|vpiName:slave
|vpiIODecl:
\_io_decl: (readdata)
|vpiName:readdata
|vpiDirection:2
|vpiExpr:
\_logic_net: (readdata), line:92
|vpiIODecl:
\_io_decl: (ack)
|vpiName:ack
|vpiDirection:2
|vpiExpr:
\_logic_net: (ack), line:113
|vpiIODecl:
\_io_decl: (addr)
|vpiName:addr
|vpiDirection:1
|vpiExpr:
\_logic_net: (addr), line:25
|vpiIODecl:
\_io_decl: (we)
|vpiName:we
|vpiDirection:1
|vpiExpr:
\_logic_net: (we), line:107
|vpiIODecl:
\_io_decl: (sel)
|vpiName:sel
|vpiDirection:1
|vpiExpr:
\_logic_net: (sel), line:108
|vpiIODecl:
\_io_decl: (writedata)
|vpiName:writedata
|vpiDirection:1
|vpiExpr:
\_logic_net: (writedata), line:93
|vpiIODecl:
\_io_decl: (stb)
|vpiName:stb
|vpiDirection:1
|vpiExpr:
\_logic_net: (stb), line:111
|vpiIODecl:
\_io_decl: (cyc)
|vpiName:cyc
|vpiDirection:1
|vpiExpr:
\_logic_net: (cyc), line:112
|vpiInterface:
\_interface: work@wishbone_interface (m_wishbone), file:third_party/cores/taiga/examples/zedboard/taiga_wrapper.sv, line:233
|vpiPort:
\_port: (tr), line:37, parent:cpu
|vpiName:tr
|vpiDirection:2
|vpiTypedef:
\_struct_typespec: (trace_outputs_t), line:469
|vpiHighConn:
\_ref_obj: (tr), line:233
|vpiName:tr
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (tr), line:37, parent:cpu
|vpiName:tr
|vpiFullName:work@taiga_wrapper.cpu.tr
|vpiPort:
\_port: (l2), line:39, parent:cpu
|vpiName:l2
|vpiDirection:5
|vpiHighConn:
\_ref_obj: (l2), line:233
|vpiName:l2
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_modport: (master)
|vpiName:master
|vpiIODecl:
\_io_decl: (addr)
|vpiName:addr
|vpiDirection:2
|vpiExpr:
\_logic_net: (addr), line:25
|vpiIODecl:
\_io_decl: (be)
|vpiName:be
|vpiDirection:2
|vpiExpr:
\_logic_net: (be), line:27
|vpiIODecl:
\_io_decl: (rnw)
|vpiName:rnw
|vpiDirection:2
|vpiExpr:
\_logic_net: (rnw), line:29
|vpiName:rnw
|vpiNetType:36
|vpiIODecl:
\_io_decl: (is_amo)
|vpiName:is_amo
|vpiDirection:2
|vpiExpr:
\_logic_net: (is_amo), line:30
|vpiName:is_amo
|vpiNetType:36
|vpiIODecl:
\_io_decl: (amo_type_or_burst_size)
|vpiName:amo_type_or_burst_size
|vpiDirection:2
|vpiExpr:
\_logic_net: (amo_type_or_burst_size), line:31
|vpiName:amo_type_or_burst_size
|vpiNetType:36
|vpiRange:
\_range: , line:31
|vpiLeftRange:
\_constant: , line:31
|vpiConstType:7
|vpiDecompile:4
|vpiSize:32
|INT:4
|vpiRightRange:
\_constant: , line:31
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (sub_id)
|vpiName:sub_id
|vpiDirection:2
|vpiExpr:
\_logic_net: (sub_id), line:32
|vpiName:sub_id
|vpiNetType:36
|vpiRange:
\_range: , line:32
|vpiLeftRange:
\_constant: , line:32
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:32
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (request_push)
|vpiName:request_push
|vpiDirection:2
|vpiExpr:
\_logic_net: (request_push), line:34
|vpiName:request_push
|vpiNetType:36
|vpiIODecl:
\_io_decl: (request_full)
|vpiName:request_full
|vpiDirection:1
|vpiExpr:
\_logic_net: (request_full), line:35
|vpiName:request_full
|vpiNetType:36
|vpiIODecl:
\_io_decl: (inv_addr)
|vpiName:inv_addr
|vpiDirection:1
|vpiExpr:
\_logic_net: (inv_addr), line:37
|vpiName:inv_addr
|vpiNetType:36
|vpiRange:
\_range: , line:37
|vpiLeftRange:
\_constant: , line:37
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:37
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiIODecl:
\_io_decl: (inv_valid)
|vpiName:inv_valid
|vpiDirection:1
|vpiExpr:
\_logic_net: (inv_valid), line:38
|vpiName:inv_valid
|vpiNetType:36
|vpiIODecl:
\_io_decl: (inv_ack)
|vpiName:inv_ack
|vpiDirection:2
|vpiExpr:
\_logic_net: (inv_ack), line:39
|vpiName:inv_ack
|vpiNetType:36
|vpiIODecl:
\_io_decl: (con_result)
|vpiName:con_result
|vpiDirection:1
|vpiExpr:
\_logic_net: (con_result), line:41
|vpiName:con_result
|vpiNetType:36
|vpiIODecl:
\_io_decl: (con_valid)
|vpiName:con_valid
|vpiDirection:1
|vpiExpr:
\_logic_net: (con_valid), line:42
|vpiName:con_valid
|vpiNetType:36
|vpiIODecl:
\_io_decl: (wr_data)
|vpiName:wr_data
|vpiDirection:2
|vpiExpr:
\_logic_net: (wr_data), line:44
|vpiName:wr_data
|vpiNetType:36
|vpiRange:
\_range: , line:44
|vpiLeftRange:
\_constant: , line:44
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:44
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (wr_data_push)
|vpiName:wr_data_push
|vpiDirection:2
|vpiExpr:
\_logic_net: (wr_data_push), line:45
|vpiName:wr_data_push
|vpiNetType:36
|vpiIODecl:
\_io_decl: (data_full)
|vpiName:data_full
|vpiDirection:1
|vpiExpr:
\_logic_net: (data_full), line:46
|vpiName:data_full
|vpiNetType:36
|vpiIODecl:
\_io_decl: (rd_data)
|vpiName:rd_data
|vpiDirection:1
|vpiExpr:
\_logic_net: (rd_data), line:48
|vpiName:rd_data
|vpiNetType:36
|vpiRange:
\_range: , line:48
|vpiLeftRange:
\_constant: , line:48
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:48
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (rd_sub_id)
|vpiName:rd_sub_id
|vpiDirection:1
|vpiExpr:
\_logic_net: (rd_sub_id), line:49
|vpiName:rd_sub_id
|vpiNetType:36
|vpiRange:
\_range: , line:49
|vpiLeftRange:
\_constant: , line:49
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:49
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (rd_data_valid)
|vpiName:rd_data_valid
|vpiDirection:1
|vpiExpr:
\_logic_net: (rd_data_valid), line:50
|vpiName:rd_data_valid
|vpiNetType:36
|vpiIODecl:
\_io_decl: (rd_data_ack)
|vpiName:rd_data_ack
|vpiDirection:2
|vpiExpr:
\_logic_net: (rd_data_ack), line:51
|vpiName:rd_data_ack
|vpiNetType:36
|vpiInterface:
\_interface: work@l2_requester_interface (l2), file:third_party/cores/taiga/examples/zedboard/taiga_wrapper.sv, line:233
|vpiDefName:work@l2_requester_interface
|vpiName:l2
|vpiModport:
\_modport: (master)
|vpiModport:
\_modport: (slave)
|vpiName:slave
|vpiIODecl:
\_io_decl: (addr)
|vpiName:addr
|vpiDirection:1
|vpiExpr:
\_logic_net: (addr), line:25
|vpiIODecl:
\_io_decl: (be)
|vpiName:be
|vpiDirection:1
|vpiExpr:
\_logic_net: (be), line:27
|vpiIODecl:
\_io_decl: (rnw)
|vpiName:rnw
|vpiDirection:1
|vpiExpr:
\_logic_net: (rnw), line:29
|vpiIODecl:
\_io_decl: (is_amo)
|vpiName:is_amo
|vpiDirection:1
|vpiExpr:
\_logic_net: (is_amo), line:30
|vpiIODecl:
\_io_decl: (amo_type_or_burst_size)
|vpiName:amo_type_or_burst_size
|vpiDirection:1
|vpiExpr:
\_logic_net: (amo_type_or_burst_size), line:31
|vpiIODecl:
\_io_decl: (sub_id)
|vpiName:sub_id
|vpiDirection:1
|vpiExpr:
\_logic_net: (sub_id), line:32
|vpiIODecl:
\_io_decl: (request_push)
|vpiName:request_push
|vpiDirection:1
|vpiExpr:
\_logic_net: (request_push), line:34
|vpiIODecl:
\_io_decl: (request_full)
|vpiName:request_full
|vpiDirection:2
|vpiExpr:
\_logic_net: (request_full), line:35
|vpiIODecl:
\_io_decl: (inv_addr)
|vpiName:inv_addr
|vpiDirection:2
|vpiExpr:
\_logic_net: (inv_addr), line:37
|vpiIODecl:
\_io_decl: (inv_valid)
|vpiName:inv_valid
|vpiDirection:2
|vpiExpr:
\_logic_net: (inv_valid), line:38
|vpiIODecl:
\_io_decl: (inv_ack)
|vpiName:inv_ack
|vpiDirection:1
|vpiExpr:
\_logic_net: (inv_ack), line:39
|vpiIODecl:
\_io_decl: (con_result)
|vpiName:con_result
|vpiDirection:2
|vpiExpr:
\_logic_net: (con_result), line:41
|vpiIODecl:
\_io_decl: (con_valid)
|vpiName:con_valid
|vpiDirection:2
|vpiExpr:
\_logic_net: (con_valid), line:42
|vpiIODecl:
\_io_decl: (wr_data)
|vpiName:wr_data
|vpiDirection:1
|vpiExpr:
\_logic_net: (wr_data), line:44
|vpiIODecl:
\_io_decl: (wr_data_push)
|vpiName:wr_data_push
|vpiDirection:1
|vpiExpr:
\_logic_net: (wr_data_push), line:45
|vpiIODecl:
\_io_decl: (data_full)
|vpiName:data_full
|vpiDirection:2
|vpiExpr:
\_logic_net: (data_full), line:46
|vpiIODecl:
\_io_decl: (rd_data)
|vpiName:rd_data
|vpiDirection:2
|vpiExpr:
\_logic_net: (rd_data), line:48
|vpiIODecl:
\_io_decl: (rd_sub_id)
|vpiName:rd_sub_id
|vpiDirection:2
|vpiExpr:
\_logic_net: (rd_sub_id), line:49
|vpiIODecl:
\_io_decl: (rd_data_valid)
|vpiName:rd_data_valid
|vpiDirection:2
|vpiExpr:
\_logic_net: (rd_data_valid), line:50
|vpiIODecl:
\_io_decl: (rd_data_ack)
|vpiName:rd_data_ack
|vpiDirection:1
|vpiExpr:
\_logic_net: (rd_data_ack), line:51
|vpiInterface:
\_interface: work@l2_requester_interface (l2), file:third_party/cores/taiga/examples/zedboard/taiga_wrapper.sv, line:233
|vpiPort:
\_port: (timer_interrupt), line:41, parent:cpu
|vpiName:timer_interrupt
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (timer_interrupt), line:233
|vpiName:timer_interrupt
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (timer_interrupt), line:41, parent:cpu
|vpiName:timer_interrupt
|vpiFullName:work@taiga_wrapper.cpu.timer_interrupt
|vpiNetType:36
|vpiPort:
\_port: (interrupt), line:42, parent:cpu
|vpiName:interrupt
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (interrupt), line:233
|vpiName:interrupt
|vpiActual:
\_logic_net: (interrupt), line:73, parent:work@taiga_wrapper
|vpiName:interrupt
|vpiFullName:work@taiga_wrapper.interrupt
|vpiNetType:36
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (interrupt), line:42, parent:cpu
|vpiName:interrupt
|vpiFullName:work@taiga_wrapper.cpu.interrupt
|vpiNetType:36
|vpiInterface:
\_interface: work@l1_arbiter_request_interface (l1_request0), file:third_party/cores/taiga/core/taiga.sv, line:45, parent:cpu
|vpiDefName:work@l1_arbiter_request_interface
|vpiName:l1_request0
|vpiFullName:work@taiga_wrapper.cpu.l1_request0
|vpiModport:
\_modport: (master), parent:l1_request0
|vpiName:master
|vpiIODecl:
\_io_decl: (addr), parent:master
|vpiName:addr
|vpiDirection:2
|vpiIODecl:
\_io_decl: (data), parent:master
|vpiName:data
|vpiDirection:2
|vpiIODecl:
\_io_decl: (rnw), parent:master
|vpiName:rnw
|vpiDirection:2
|vpiIODecl:
\_io_decl: (be), parent:master
|vpiName:be
|vpiDirection:2
|vpiIODecl:
\_io_decl: (size), parent:master
|vpiName:size
|vpiDirection:2
|vpiIODecl:
\_io_decl: (is_amo), parent:master
|vpiName:is_amo
|vpiDirection:2
|vpiIODecl:
\_io_decl: (amo), parent:master
|vpiName:amo
|vpiDirection:2
|vpiIODecl:
\_io_decl: (request), parent:master
|vpiName:request
|vpiDirection:2
|vpiIODecl:
\_io_decl: (ack), parent:master
|vpiName:ack
|vpiDirection:1
|vpiInterface:
\_interface: work@l1_arbiter_request_interface (l1_request0), file:third_party/cores/taiga/core/taiga.sv, line:45, parent:cpu
|vpiModport:
\_modport: (slave), parent:l1_request0
|vpiName:slave
|vpiIODecl:
\_io_decl: (addr), parent:slave
|vpiName:addr
|vpiDirection:1
|vpiIODecl:
\_io_decl: (data), parent:slave
|vpiName:data
|vpiDirection:1
|vpiIODecl:
\_io_decl: (rnw), parent:slave
|vpiName:rnw
|vpiDirection:1
|vpiIODecl:
\_io_decl: (be), parent:slave
|vpiName:be
|vpiDirection:1
|vpiIODecl:
\_io_decl: (size), parent:slave
|vpiName:size
|vpiDirection:1
|vpiIODecl:
\_io_decl: (is_amo), parent:slave
|vpiName:is_amo
|vpiDirection:1
|vpiIODecl:
\_io_decl: (amo), parent:slave
|vpiName:amo
|vpiDirection:1
|vpiIODecl:
\_io_decl: (request), parent:slave
|vpiName:request
|vpiDirection:1
|vpiIODecl:
\_io_decl: (ack), parent:slave
|vpiName:ack
|vpiDirection:2
|vpiInterface:
\_interface: work@l1_arbiter_request_interface (l1_request0), file:third_party/cores/taiga/core/taiga.sv, line:45, parent:cpu
|vpiNet:
\_logic_net: (addr), line:123, parent:l1_request0
|vpiName:addr
|vpiFullName:work@taiga_wrapper.cpu.l1_request0.addr
|vpiNetType:36
|vpiRange:
\_range: , line:123
|vpiLeftRange:
\_constant: , line:123
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:123
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (data), line:124, parent:l1_request0
|vpiName:data
|vpiFullName:work@taiga_wrapper.cpu.l1_request0.data
|vpiNetType:36
|vpiRange:
\_range: , line:124
|vpiLeftRange:
\_constant: , line:124
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:124
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (rnw), line:125, parent:l1_request0
|vpiName:rnw
|vpiFullName:work@taiga_wrapper.cpu.l1_request0.rnw
|vpiNetType:36
|vpiNet:
\_logic_net: (be), line:126, parent:l1_request0
|vpiName:be
|vpiFullName:work@taiga_wrapper.cpu.l1_request0.be
|vpiNetType:36
|vpiRange:
\_range: , line:126
|vpiLeftRange:
\_constant: , line:126
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiRightRange:
\_constant: , line:126
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (size), line:127, parent:l1_request0
|vpiName:size
|vpiFullName:work@taiga_wrapper.cpu.l1_request0.size
|vpiNetType:36
|vpiRange:
\_range: , line:127
|vpiLeftRange:
\_constant: , line:127
|vpiConstType:7
|vpiDecompile:4
|vpiSize:32
|INT:4
|vpiRightRange:
\_constant: , line:127
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (is_amo), line:128, parent:l1_request0
|vpiName:is_amo
|vpiFullName:work@taiga_wrapper.cpu.l1_request0.is_amo
|vpiNetType:36
|vpiNet:
\_logic_net: (amo), line:129, parent:l1_request0
|vpiName:amo
|vpiFullName:work@taiga_wrapper.cpu.l1_request0.amo
|vpiNetType:36
|vpiRange:
\_range: , line:129
|vpiLeftRange:
\_constant: , line:129
|vpiConstType:7
|vpiDecompile:4
|vpiSize:32
|INT:4
|vpiRightRange:
\_constant: , line:129
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (request), line:131, parent:l1_request0
|vpiName:request
|vpiFullName:work@taiga_wrapper.cpu.l1_request0.request
|vpiNetType:36
|vpiNet:
\_logic_net: (ack), line:132, parent:l1_request0
|vpiName:ack
|vpiFullName:work@taiga_wrapper.cpu.l1_request0.ack
|vpiNetType:36
|vpiInstance:
\_module: work@taiga (cpu), file:third_party/cores/taiga/examples/zedboard/taiga_wrapper.sv, line:233, parent:work@taiga_wrapper
|vpiInterface:
\_interface: work@l1_arbiter_request_interface (l1_request1), file:third_party/cores/taiga/core/taiga.sv, line:45, parent:cpu
|vpiDefName:work@l1_arbiter_request_interface
|vpiName:l1_request1
|vpiFullName:work@taiga_wrapper.cpu.l1_request1
|vpiModport:
\_modport: (master), parent:l1_request1
|vpiName:master
|vpiIODecl:
\_io_decl: (addr), parent:master
|vpiName:addr
|vpiDirection:2
|vpiIODecl:
\_io_decl: (data), parent:master
|vpiName:data
|vpiDirection:2
|vpiIODecl:
\_io_decl: (rnw), parent:master
|vpiName:rnw
|vpiDirection:2
|vpiIODecl:
\_io_decl: (be), parent:master
|vpiName:be
|vpiDirection:2
|vpiIODecl:
\_io_decl: (size), parent:master
|vpiName:size
|vpiDirection:2
|vpiIODecl:
\_io_decl: (is_amo), parent:master
|vpiName:is_amo
|vpiDirection:2
|vpiIODecl:
\_io_decl: (amo), parent:master
|vpiName:amo
|vpiDirection:2
|vpiIODecl:
\_io_decl: (request), parent:master
|vpiName:request
|vpiDirection:2
|vpiIODecl:
\_io_decl: (ack), parent:master
|vpiName:ack
|vpiDirection:1
|vpiInterface:
\_interface: work@l1_arbiter_request_interface (l1_request1), file:third_party/cores/taiga/core/taiga.sv, line:45, parent:cpu
|vpiModport:
\_modport: (slave), parent:l1_request1
|vpiName:slave
|vpiIODecl:
\_io_decl: (addr), parent:slave
|vpiName:addr
|vpiDirection:1
|vpiIODecl:
\_io_decl: (data), parent:slave
|vpiName:data
|vpiDirection:1
|vpiIODecl:
\_io_decl: (rnw), parent:slave
|vpiName:rnw
|vpiDirection:1
|vpiIODecl:
\_io_decl: (be), parent:slave
|vpiName:be
|vpiDirection:1
|vpiIODecl:
\_io_decl: (size), parent:slave
|vpiName:size
|vpiDirection:1
|vpiIODecl:
\_io_decl: (is_amo), parent:slave
|vpiName:is_amo
|vpiDirection:1
|vpiIODecl:
\_io_decl: (amo), parent:slave
|vpiName:amo
|vpiDirection:1
|vpiIODecl:
\_io_decl: (request), parent:slave
|vpiName:request
|vpiDirection:1
|vpiIODecl:
\_io_decl: (ack), parent:slave
|vpiName:ack
|vpiDirection:2
|vpiInterface:
\_interface: work@l1_arbiter_request_interface (l1_request1), file:third_party/cores/taiga/core/taiga.sv, line:45, parent:cpu
|vpiNet:
\_logic_net: (addr), line:123, parent:l1_request1
|vpiName:addr
|vpiFullName:work@taiga_wrapper.cpu.l1_request1.addr
|vpiNetType:36
|vpiRange:
\_range: , line:123
|vpiLeftRange:
\_constant: , line:123
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:123
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (data), line:124, parent:l1_request1
|vpiName:data
|vpiFullName:work@taiga_wrapper.cpu.l1_request1.data
|vpiNetType:36
|vpiRange:
\_range: , line:124
|vpiLeftRange:
\_constant: , line:124
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:124
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (rnw), line:125, parent:l1_request1
|vpiName:rnw
|vpiFullName:work@taiga_wrapper.cpu.l1_request1.rnw
|vpiNetType:36
|vpiNet:
\_logic_net: (be), line:126, parent:l1_request1
|vpiName:be
|vpiFullName:work@taiga_wrapper.cpu.l1_request1.be
|vpiNetType:36
|vpiRange:
\_range: , line:126
|vpiLeftRange:
\_constant: , line:126
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiRightRange:
\_constant: , line:126
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (size), line:127, parent:l1_request1
|vpiName:size
|vpiFullName:work@taiga_wrapper.cpu.l1_request1.size
|vpiNetType:36
|vpiRange:
\_range: , line:127
|vpiLeftRange:
\_constant: , line:127
|vpiConstType:7
|vpiDecompile:4
|vpiSize:32
|INT:4
|vpiRightRange:
\_constant: , line:127
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (is_amo), line:128, parent:l1_request1
|vpiName:is_amo
|vpiFullName:work@taiga_wrapper.cpu.l1_request1.is_amo
|vpiNetType:36
|vpiNet:
\_logic_net: (amo), line:129, parent:l1_request1
|vpiName:amo
|vpiFullName:work@taiga_wrapper.cpu.l1_request1.amo
|vpiNetType:36
|vpiRange:
\_range: , line:129
|vpiLeftRange:
\_constant: , line:129
|vpiConstType:7
|vpiDecompile:4
|vpiSize:32
|INT:4
|vpiRightRange:
\_constant: , line:129
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (request), line:131, parent:l1_request1
|vpiName:request
|vpiFullName:work@taiga_wrapper.cpu.l1_request1.request
|vpiNetType:36
|vpiNet:
\_logic_net: (ack), line:132, parent:l1_request1
|vpiName:ack
|vpiFullName:work@taiga_wrapper.cpu.l1_request1.ack
|vpiNetType:36
|vpiInstance:
\_module: work@taiga (cpu), file:third_party/cores/taiga/examples/zedboard/taiga_wrapper.sv, line:233, parent:work@taiga_wrapper
|vpiInterface:
\_interface: work@l1_arbiter_request_interface (l1_request2), file:third_party/cores/taiga/core/taiga.sv, line:45, parent:cpu
|vpiDefName:work@l1_arbiter_request_interface
|vpiName:l1_request2
|vpiFullName:work@taiga_wrapper.cpu.l1_request2
|vpiModport:
\_modport: (master), parent:l1_request2
|vpiName:master
|vpiIODecl:
\_io_decl: (addr), parent:master
|vpiName:addr
|vpiDirection:2
|vpiIODecl:
\_io_decl: (data), parent:master
|vpiName:data
|vpiDirection:2
|vpiIODecl:
\_io_decl: (rnw), parent:master
|vpiName:rnw
|vpiDirection:2
|vpiIODecl:
\_io_decl: (be), parent:master
|vpiName:be
|vpiDirection:2
|vpiIODecl:
\_io_decl: (size), parent:master
|vpiName:size
|vpiDirection:2
|vpiIODecl:
\_io_decl: (is_amo), parent:master
|vpiName:is_amo
|vpiDirection:2
|vpiIODecl:
\_io_decl: (amo), parent:master
|vpiName:amo
|vpiDirection:2
|vpiIODecl:
\_io_decl: (request), parent:master
|vpiName:request
|vpiDirection:2
|vpiIODecl:
\_io_decl: (ack), parent:master
|vpiName:ack
|vpiDirection:1
|vpiInterface:
\_interface: work@l1_arbiter_request_interface (l1_request2), file:third_party/cores/taiga/core/taiga.sv, line:45, parent:cpu
|vpiModport:
\_modport: (slave), parent:l1_request2
|vpiName:slave
|vpiIODecl:
\_io_decl: (addr), parent:slave
|vpiName:addr
|vpiDirection:1
|vpiIODecl:
\_io_decl: (data), parent:slave
|vpiName:data
|vpiDirection:1
|vpiIODecl:
\_io_decl: (rnw), parent:slave
|vpiName:rnw
|vpiDirection:1
|vpiIODecl:
\_io_decl: (be), parent:slave
|vpiName:be
|vpiDirection:1
|vpiIODecl:
\_io_decl: (size), parent:slave
|vpiName:size
|vpiDirection:1
|vpiIODecl:
\_io_decl: (is_amo), parent:slave
|vpiName:is_amo
|vpiDirection:1
|vpiIODecl:
\_io_decl: (amo), parent:slave
|vpiName:amo
|vpiDirection:1
|vpiIODecl:
\_io_decl: (request), parent:slave
|vpiName:request
|vpiDirection:1
|vpiIODecl:
\_io_decl: (ack), parent:slave
|vpiName:ack
|vpiDirection:2
|vpiInterface:
\_interface: work@l1_arbiter_request_interface (l1_request2), file:third_party/cores/taiga/core/taiga.sv, line:45, parent:cpu
|vpiNet:
\_logic_net: (addr), line:123, parent:l1_request2
|vpiName:addr
|vpiFullName:work@taiga_wrapper.cpu.l1_request2.addr
|vpiNetType:36
|vpiRange:
\_range: , line:123
|vpiLeftRange:
\_constant: , line:123
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:123
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (data), line:124, parent:l1_request2
|vpiName:data
|vpiFullName:work@taiga_wrapper.cpu.l1_request2.data
|vpiNetType:36
|vpiRange:
\_range: , line:124
|vpiLeftRange:
\_constant: , line:124
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:124
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (rnw), line:125, parent:l1_request2
|vpiName:rnw
|vpiFullName:work@taiga_wrapper.cpu.l1_request2.rnw
|vpiNetType:36
|vpiNet:
\_logic_net: (be), line:126, parent:l1_request2
|vpiName:be
|vpiFullName:work@taiga_wrapper.cpu.l1_request2.be
|vpiNetType:36
|vpiRange:
\_range: , line:126
|vpiLeftRange:
\_constant: , line:126
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiRightRange:
\_constant: , line:126
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (size), line:127, parent:l1_request2
|vpiName:size
|vpiFullName:work@taiga_wrapper.cpu.l1_request2.size
|vpiNetType:36
|vpiRange:
\_range: , line:127
|vpiLeftRange:
\_constant: , line:127
|vpiConstType:7
|vpiDecompile:4
|vpiSize:32
|INT:4
|vpiRightRange:
\_constant: , line:127
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (is_amo), line:128, parent:l1_request2
|vpiName:is_amo
|vpiFullName:work@taiga_wrapper.cpu.l1_request2.is_amo
|vpiNetType:36
|vpiNet:
\_logic_net: (amo), line:129, parent:l1_request2
|vpiName:amo
|vpiFullName:work@taiga_wrapper.cpu.l1_request2.amo
|vpiNetType:36
|vpiRange:
\_range: , line:129
|vpiLeftRange:
\_constant: , line:129
|vpiConstType:7
|vpiDecompile:4
|vpiSize:32
|INT:4
|vpiRightRange:
\_constant: , line:129
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (request), line:131, parent:l1_request2
|vpiName:request
|vpiFullName:work@taiga_wrapper.cpu.l1_request2.request
|vpiNetType:36
|vpiNet:
\_logic_net: (ack), line:132, parent:l1_request2
|vpiName:ack
|vpiFullName:work@taiga_wrapper.cpu.l1_request2.ack
|vpiNetType:36
|vpiInstance:
\_module: work@taiga (cpu), file:third_party/cores/taiga/examples/zedboard/taiga_wrapper.sv, line:233, parent:work@taiga_wrapper
|vpiInterface:
\_interface: work@l1_arbiter_request_interface (l1_request3), file:third_party/cores/taiga/core/taiga.sv, line:45, parent:cpu
|vpiDefName:work@l1_arbiter_request_interface
|vpiName:l1_request3
|vpiFullName:work@taiga_wrapper.cpu.l1_request3
|vpiModport:
\_modport: (master), parent:l1_request3
|vpiName:master
|vpiIODecl:
\_io_decl: (addr), parent:master
|vpiName:addr
|vpiDirection:2
|vpiIODecl:
\_io_decl: (data), parent:master
|vpiName:data
|vpiDirection:2
|vpiIODecl:
\_io_decl: (rnw), parent:master
|vpiName:rnw
|vpiDirection:2
|vpiIODecl:
\_io_decl: (be), parent:master
|vpiName:be
|vpiDirection:2
|vpiIODecl:
\_io_decl: (size), parent:master
|vpiName:size
|vpiDirection:2
|vpiIODecl:
\_io_decl: (is_amo), parent:master
|vpiName:is_amo
|vpiDirection:2
|vpiIODecl:
\_io_decl: (amo), parent:master
|vpiName:amo
|vpiDirection:2
|vpiIODecl:
\_io_decl: (request), parent:master
|vpiName:request
|vpiDirection:2
|vpiIODecl:
\_io_decl: (ack), parent:master
|vpiName:ack
|vpiDirection:1
|vpiInterface:
\_interface: work@l1_arbiter_request_interface (l1_request3), file:third_party/cores/taiga/core/taiga.sv, line:45, parent:cpu
|vpiModport:
\_modport: (slave), parent:l1_request3
|vpiName:slave
|vpiIODecl:
\_io_decl: (addr), parent:slave
|vpiName:addr
|vpiDirection:1
|vpiIODecl:
\_io_decl: (data), parent:slave
|vpiName:data
|vpiDirection:1
|vpiIODecl:
\_io_decl: (rnw), parent:slave
|vpiName:rnw
|vpiDirection:1
|vpiIODecl:
\_io_decl: (be), parent:slave
|vpiName:be
|vpiDirection:1
|vpiIODecl:
\_io_decl: (size), parent:slave
|vpiName:size
|vpiDirection:1
|vpiIODecl:
\_io_decl: (is_amo), parent:slave
|vpiName:is_amo
|vpiDirection:1
|vpiIODecl:
\_io_decl: (amo), parent:slave
|vpiName:amo
|vpiDirection:1
|vpiIODecl:
\_io_decl: (request), parent:slave
|vpiName:request
|vpiDirection:1
|vpiIODecl:
\_io_decl: (ack), parent:slave
|vpiName:ack
|vpiDirection:2
|vpiInterface:
\_interface: work@l1_arbiter_request_interface (l1_request3), file:third_party/cores/taiga/core/taiga.sv, line:45, parent:cpu
|vpiNet:
\_logic_net: (addr), line:123, parent:l1_request3
|vpiName:addr
|vpiFullName:work@taiga_wrapper.cpu.l1_request3.addr
|vpiNetType:36
|vpiRange:
\_range: , line:123
|vpiLeftRange:
\_constant: , line:123
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:123
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (data), line:124, parent:l1_request3
|vpiName:data
|vpiFullName:work@taiga_wrapper.cpu.l1_request3.data
|vpiNetType:36
|vpiRange:
\_range: , line:124
|vpiLeftRange:
\_constant: , line:124
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:124
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (rnw), line:125, parent:l1_request3
|vpiName:rnw
|vpiFullName:work@taiga_wrapper.cpu.l1_request3.rnw
|vpiNetType:36
|vpiNet:
\_logic_net: (be), line:126, parent:l1_request3
|vpiName:be
|vpiFullName:work@taiga_wrapper.cpu.l1_request3.be
|vpiNetType:36
|vpiRange:
\_range: , line:126
|vpiLeftRange:
\_constant: , line:126
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiRightRange:
\_constant: , line:126
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (size), line:127, parent:l1_request3
|vpiName:size
|vpiFullName:work@taiga_wrapper.cpu.l1_request3.size
|vpiNetType:36
|vpiRange:
\_range: , line:127
|vpiLeftRange:
\_constant: , line:127
|vpiConstType:7
|vpiDecompile:4
|vpiSize:32
|INT:4
|vpiRightRange:
\_constant: , line:127
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (is_amo), line:128, parent:l1_request3
|vpiName:is_amo
|vpiFullName:work@taiga_wrapper.cpu.l1_request3.is_amo
|vpiNetType:36
|vpiNet:
\_logic_net: (amo), line:129, parent:l1_request3
|vpiName:amo
|vpiFullName:work@taiga_wrapper.cpu.l1_request3.amo
|vpiNetType:36
|vpiRange:
\_range: , line:129
|vpiLeftRange:
\_constant: , line:129
|vpiConstType:7
|vpiDecompile:4
|vpiSize:32
|INT:4
|vpiRightRange:
\_constant: , line:129
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (request), line:131, parent:l1_request3
|vpiName:request
|vpiFullName:work@taiga_wrapper.cpu.l1_request3.request
|vpiNetType:36
|vpiNet:
\_logic_net: (ack), line:132, parent:l1_request3
|vpiName:ack
|vpiFullName:work@taiga_wrapper.cpu.l1_request3.ack
|vpiNetType:36
|vpiInstance:
\_module: work@taiga (cpu), file:third_party/cores/taiga/examples/zedboard/taiga_wrapper.sv, line:233, parent:work@taiga_wrapper
|vpiInterface:
\_interface: work@l1_arbiter_request_interface (l1_request4), file:third_party/cores/taiga/core/taiga.sv, line:45, parent:cpu
|vpiDefName:work@l1_arbiter_request_interface
|vpiName:l1_request4
|vpiFullName:work@taiga_wrapper.cpu.l1_request4
|vpiModport:
\_modport: (master), parent:l1_request4
|vpiName:master
|vpiIODecl:
\_io_decl: (addr), parent:master
|vpiName:addr
|vpiDirection:2
|vpiIODecl:
\_io_decl: (data), parent:master
|vpiName:data
|vpiDirection:2
|vpiIODecl:
\_io_decl: (rnw), parent:master
|vpiName:rnw
|vpiDirection:2
|vpiIODecl:
\_io_decl: (be), parent:master
|vpiName:be
|vpiDirection:2
|vpiIODecl:
\_io_decl: (size), parent:master
|vpiName:size
|vpiDirection:2
|vpiIODecl:
\_io_decl: (is_amo), parent:master
|vpiName:is_amo
|vpiDirection:2
|vpiIODecl:
\_io_decl: (amo), parent:master
|vpiName:amo
|vpiDirection:2
|vpiIODecl:
\_io_decl: (request), parent:master
|vpiName:request
|vpiDirection:2
|vpiIODecl:
\_io_decl: (ack), parent:master
|vpiName:ack
|vpiDirection:1
|vpiInterface:
\_interface: work@l1_arbiter_request_interface (l1_request4), file:third_party/cores/taiga/core/taiga.sv, line:45, parent:cpu
|vpiModport:
\_modport: (slave), parent:l1_request4
|vpiName:slave
|vpiIODecl:
\_io_decl: (addr), parent:slave
|vpiName:addr
|vpiDirection:1
|vpiIODecl:
\_io_decl: (data), parent:slave
|vpiName:data
|vpiDirection:1
|vpiIODecl:
\_io_decl: (rnw), parent:slave
|vpiName:rnw
|vpiDirection:1
|vpiIODecl:
\_io_decl: (be), parent:slave
|vpiName:be
|vpiDirection:1
|vpiIODecl:
\_io_decl: (size), parent:slave
|vpiName:size
|vpiDirection:1
|vpiIODecl:
\_io_decl: (is_amo), parent:slave
|vpiName:is_amo
|vpiDirection:1
|vpiIODecl:
\_io_decl: (amo), parent:slave
|vpiName:amo
|vpiDirection:1
|vpiIODecl:
\_io_decl: (request), parent:slave
|vpiName:request
|vpiDirection:1
|vpiIODecl:
\_io_decl: (ack), parent:slave
|vpiName:ack
|vpiDirection:2
|vpiInterface:
\_interface: work@l1_arbiter_request_interface (l1_request4), file:third_party/cores/taiga/core/taiga.sv, line:45, parent:cpu
|vpiNet:
\_logic_net: (addr), line:123, parent:l1_request4
|vpiName:addr
|vpiFullName:work@taiga_wrapper.cpu.l1_request4.addr
|vpiNetType:36
|vpiRange:
\_range: , line:123
|vpiLeftRange:
\_constant: , line:123
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:123
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (data), line:124, parent:l1_request4
|vpiName:data
|vpiFullName:work@taiga_wrapper.cpu.l1_request4.data
|vpiNetType:36
|vpiRange:
\_range: , line:124
|vpiLeftRange:
\_constant: , line:124
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:124
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (rnw), line:125, parent:l1_request4
|vpiName:rnw
|vpiFullName:work@taiga_wrapper.cpu.l1_request4.rnw
|vpiNetType:36
|vpiNet:
\_logic_net: (be), line:126, parent:l1_request4
|vpiName:be
|vpiFullName:work@taiga_wrapper.cpu.l1_request4.be
|vpiNetType:36
|vpiRange:
\_range: , line:126
|vpiLeftRange:
\_constant: , line:126
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiRightRange:
\_constant: , line:126
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (size), line:127, parent:l1_request4
|vpiName:size
|vpiFullName:work@taiga_wrapper.cpu.l1_request4.size
|vpiNetType:36
|vpiRange:
\_range: , line:127
|vpiLeftRange:
\_constant: , line:127
|vpiConstType:7
|vpiDecompile:4
|vpiSize:32
|INT:4
|vpiRightRange:
\_constant: , line:127
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (is_amo), line:128, parent:l1_request4
|vpiName:is_amo
|vpiFullName:work@taiga_wrapper.cpu.l1_request4.is_amo
|vpiNetType:36
|vpiNet:
\_logic_net: (amo), line:129, parent:l1_request4
|vpiName:amo
|vpiFullName:work@taiga_wrapper.cpu.l1_request4.amo
|vpiNetType:36
|vpiRange:
\_range: , line:129
|vpiLeftRange:
\_constant: , line:129
|vpiConstType:7
|vpiDecompile:4
|vpiSize:32
|INT:4
|vpiRightRange:
\_constant: , line:129
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (request), line:131, parent:l1_request4
|vpiName:request
|vpiFullName:work@taiga_wrapper.cpu.l1_request4.request
|vpiNetType:36
|vpiNet:
\_logic_net: (ack), line:132, parent:l1_request4
|vpiName:ack
|vpiFullName:work@taiga_wrapper.cpu.l1_request4.ack
|vpiNetType:36
|vpiInstance:
\_module: work@taiga (cpu), file:third_party/cores/taiga/examples/zedboard/taiga_wrapper.sv, line:233, parent:work@taiga_wrapper
|vpiInterface:
\_interface: work@l1_arbiter_request_interface (l1_request5), file:third_party/cores/taiga/core/taiga.sv, line:45, parent:cpu
|vpiDefName:work@l1_arbiter_request_interface
|vpiName:l1_request5
|vpiFullName:work@taiga_wrapper.cpu.l1_request5
|vpiModport:
\_modport: (master), parent:l1_request5
|vpiName:master
|vpiIODecl:
\_io_decl: (addr), parent:master
|vpiName:addr
|vpiDirection:2
|vpiIODecl:
\_io_decl: (data), parent:master
|vpiName:data
|vpiDirection:2
|vpiIODecl:
\_io_decl: (rnw), parent:master
|vpiName:rnw
|vpiDirection:2
|vpiIODecl:
\_io_decl: (be), parent:master
|vpiName:be
|vpiDirection:2
|vpiIODecl:
\_io_decl: (size), parent:master
|vpiName:size
|vpiDirection:2
|vpiIODecl:
\_io_decl: (is_amo), parent:master
|vpiName:is_amo
|vpiDirection:2
|vpiIODecl:
\_io_decl: (amo), parent:master
|vpiName:amo
|vpiDirection:2
|vpiIODecl:
\_io_decl: (request), parent:master
|vpiName:request
|vpiDirection:2
|vpiIODecl:
\_io_decl: (ack), parent:master
|vpiName:ack
|vpiDirection:1
|vpiInterface:
\_interface: work@l1_arbiter_request_interface (l1_request5), file:third_party/cores/taiga/core/taiga.sv, line:45, parent:cpu
|vpiModport:
\_modport: (slave), parent:l1_request5
|vpiName:slave
|vpiIODecl:
\_io_decl: (addr), parent:slave
|vpiName:addr
|vpiDirection:1
|vpiIODecl:
\_io_decl: (data), parent:slave
|vpiName:data
|vpiDirection:1
|vpiIODecl:
\_io_decl: (rnw), parent:slave
|vpiName:rnw
|vpiDirection:1
|vpiIODecl:
\_io_decl: (be), parent:slave
|vpiName:be
|vpiDirection:1
|vpiIODecl:
\_io_decl: (size), parent:slave
|vpiName:size
|vpiDirection:1
|vpiIODecl:
\_io_decl: (is_amo), parent:slave
|vpiName:is_amo
|vpiDirection:1
|vpiIODecl:
\_io_decl: (amo), parent:slave
|vpiName:amo
|vpiDirection:1
|vpiIODecl:
\_io_decl: (request), parent:slave
|vpiName:request
|vpiDirection:1
|vpiIODecl:
\_io_decl: (ack), parent:slave
|vpiName:ack
|vpiDirection:2
|vpiInterface:
\_interface: work@l1_arbiter_request_interface (l1_request5), file:third_party/cores/taiga/core/taiga.sv, line:45, parent:cpu
|vpiNet:
\_logic_net: (addr), line:123, parent:l1_request5
|vpiName:addr
|vpiFullName:work@taiga_wrapper.cpu.l1_request5.addr
|vpiNetType:36
|vpiRange:
\_range: , line:123
|vpiLeftRange:
\_constant: , line:123
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:123
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (data), line:124, parent:l1_request5
|vpiName:data
|vpiFullName:work@taiga_wrapper.cpu.l1_request5.data
|vpiNetType:36
|vpiRange:
\_range: , line:124
|vpiLeftRange:
\_constant: , line:124
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:124
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (rnw), line:125, parent:l1_request5
|vpiName:rnw
|vpiFullName:work@taiga_wrapper.cpu.l1_request5.rnw
|vpiNetType:36
|vpiNet:
\_logic_net: (be), line:126, parent:l1_request5
|vpiName:be
|vpiFullName:work@taiga_wrapper.cpu.l1_request5.be
|vpiNetType:36
|vpiRange:
\_range: , line:126
|vpiLeftRange:
\_constant: , line:126
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiRightRange:
\_constant: , line:126
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (size), line:127, parent:l1_request5
|vpiName:size
|vpiFullName:work@taiga_wrapper.cpu.l1_request5.size
|vpiNetType:36
|vpiRange:
\_range: , line:127
|vpiLeftRange:
\_constant: , line:127
|vpiConstType:7
|vpiDecompile:4
|vpiSize:32
|INT:4
|vpiRightRange:
\_constant: , line:127
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (is_amo), line:128, parent:l1_request5
|vpiName:is_amo
|vpiFullName:work@taiga_wrapper.cpu.l1_request5.is_amo
|vpiNetType:36
|vpiNet:
\_logic_net: (amo), line:129, parent:l1_request5
|vpiName:amo
|vpiFullName:work@taiga_wrapper.cpu.l1_request5.amo
|vpiNetType:36
|vpiRange:
\_range: , line:129
|vpiLeftRange:
\_constant: , line:129
|vpiConstType:7
|vpiDecompile:4
|vpiSize:32
|INT:4
|vpiRightRange:
\_constant: , line:129
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (request), line:131, parent:l1_request5
|vpiName:request
|vpiFullName:work@taiga_wrapper.cpu.l1_request5.request
|vpiNetType:36
|vpiNet:
\_logic_net: (ack), line:132, parent:l1_request5
|vpiName:ack
|vpiFullName:work@taiga_wrapper.cpu.l1_request5.ack
|vpiNetType:36
|vpiInstance:
\_module: work@taiga (cpu), file:third_party/cores/taiga/examples/zedboard/taiga_wrapper.sv, line:233, parent:work@taiga_wrapper
|vpiInterface:
\_interface: work@l1_arbiter_request_interface (l1_request6), file:third_party/cores/taiga/core/taiga.sv, line:45, parent:cpu
|vpiDefName:work@l1_arbiter_request_interface
|vpiName:l1_request6
|vpiFullName:work@taiga_wrapper.cpu.l1_request6
|vpiModport:
\_modport: (master), parent:l1_request6
|vpiName:master
|vpiIODecl:
\_io_decl: (addr), parent:master
|vpiName:addr
|vpiDirection:2
|vpiIODecl:
\_io_decl: (data), parent:master
|vpiName:data
|vpiDirection:2
|vpiIODecl:
\_io_decl: (rnw), parent:master
|vpiName:rnw
|vpiDirection:2
|vpiIODecl:
\_io_decl: (be), parent:master
|vpiName:be
|vpiDirection:2
|vpiIODecl:
\_io_decl: (size), parent:master
|vpiName:size
|vpiDirection:2
|vpiIODecl:
\_io_decl: (is_amo), parent:master
|vpiName:is_amo
|vpiDirection:2
|vpiIODecl:
\_io_decl: (amo), parent:master
|vpiName:amo
|vpiDirection:2
|vpiIODecl:
\_io_decl: (request), parent:master
|vpiName:request
|vpiDirection:2
|vpiIODecl:
\_io_decl: (ack), parent:master
|vpiName:ack
|vpiDirection:1
|vpiInterface:
\_interface: work@l1_arbiter_request_interface (l1_request6), file:third_party/cores/taiga/core/taiga.sv, line:45, parent:cpu
|vpiModport:
\_modport: (slave), parent:l1_request6
|vpiName:slave
|vpiIODecl:
\_io_decl: (addr), parent:slave
|vpiName:addr
|vpiDirection:1
|vpiIODecl:
\_io_decl: (data), parent:slave
|vpiName:data
|vpiDirection:1
|vpiIODecl:
\_io_decl: (rnw), parent:slave
|vpiName:rnw
|vpiDirection:1
|vpiIODecl:
\_io_decl: (be), parent:slave
|vpiName:be
|vpiDirection:1
|vpiIODecl:
\_io_decl: (size), parent:slave
|vpiName:size
|vpiDirection:1
|vpiIODecl:
\_io_decl: (is_amo), parent:slave
|vpiName:is_amo
|vpiDirection:1
|vpiIODecl:
\_io_decl: (amo), parent:slave
|vpiName:amo
|vpiDirection:1
|vpiIODecl:
\_io_decl: (request), parent:slave
|vpiName:request
|vpiDirection:1
|vpiIODecl:
\_io_decl: (ack), parent:slave
|vpiName:ack
|vpiDirection:2
|vpiInterface:
\_interface: work@l1_arbiter_request_interface (l1_request6), file:third_party/cores/taiga/core/taiga.sv, line:45, parent:cpu
|vpiNet:
\_logic_net: (addr), line:123, parent:l1_request6
|vpiName:addr
|vpiFullName:work@taiga_wrapper.cpu.l1_request6.addr
|vpiNetType:36
|vpiRange:
\_range: , line:123
|vpiLeftRange:
\_constant: , line:123
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:123
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (data), line:124, parent:l1_request6
|vpiName:data
|vpiFullName:work@taiga_wrapper.cpu.l1_request6.data
|vpiNetType:36
|vpiRange:
\_range: , line:124
|vpiLeftRange:
\_constant: , line:124
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:124
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (rnw), line:125, parent:l1_request6
|vpiName:rnw
|vpiFullName:work@taiga_wrapper.cpu.l1_request6.rnw
|vpiNetType:36
|vpiNet:
\_logic_net: (be), line:126, parent:l1_request6
|vpiName:be
|vpiFullName:work@taiga_wrapper.cpu.l1_request6.be
|vpiNetType:36
|vpiRange:
\_range: , line:126
|vpiLeftRange:
\_constant: , line:126
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiRightRange:
\_constant: , line:126
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (size), line:127, parent:l1_request6
|vpiName:size
|vpiFullName:work@taiga_wrapper.cpu.l1_request6.size
|vpiNetType:36
|vpiRange:
\_range: , line:127
|vpiLeftRange:
\_constant: , line:127
|vpiConstType:7
|vpiDecompile:4
|vpiSize:32
|INT:4
|vpiRightRange:
\_constant: , line:127
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (is_amo), line:128, parent:l1_request6
|vpiName:is_amo
|vpiFullName:work@taiga_wrapper.cpu.l1_request6.is_amo
|vpiNetType:36
|vpiNet:
\_logic_net: (amo), line:129, parent:l1_request6
|vpiName:amo
|vpiFullName:work@taiga_wrapper.cpu.l1_request6.amo
|vpiNetType:36
|vpiRange:
\_range: , line:129
|vpiLeftRange:
\_constant: , line:129
|vpiConstType:7
|vpiDecompile:4
|vpiSize:32
|INT:4
|vpiRightRange:
\_constant: , line:129
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (request), line:131, parent:l1_request6
|vpiName:request
|vpiFullName:work@taiga_wrapper.cpu.l1_request6.request
|vpiNetType:36
|vpiNet:
\_logic_net: (ack), line:132, parent:l1_request6
|vpiName:ack
|vpiFullName:work@taiga_wrapper.cpu.l1_request6.ack
|vpiNetType:36
|vpiInstance:
\_module: work@taiga (cpu), file:third_party/cores/taiga/examples/zedboard/taiga_wrapper.sv, line:233, parent:work@taiga_wrapper
|vpiInterface:
\_interface: work@l1_arbiter_request_interface (l1_request7), file:third_party/cores/taiga/core/taiga.sv, line:45, parent:cpu
|vpiDefName:work@l1_arbiter_request_interface
|vpiName:l1_request7
|vpiFullName:work@taiga_wrapper.cpu.l1_request7
|vpiModport:
\_modport: (master), parent:l1_request7
|vpiName:master
|vpiIODecl:
\_io_decl: (addr), parent:master
|vpiName:addr
|vpiDirection:2
|vpiIODecl:
\_io_decl: (data), parent:master
|vpiName:data
|vpiDirection:2
|vpiIODecl:
\_io_decl: (rnw), parent:master
|vpiName:rnw
|vpiDirection:2
|vpiIODecl:
\_io_decl: (be), parent:master
|vpiName:be
|vpiDirection:2
|vpiIODecl:
\_io_decl: (size), parent:master
|vpiName:size
|vpiDirection:2
|vpiIODecl:
\_io_decl: (is_amo), parent:master
|vpiName:is_amo
|vpiDirection:2
|vpiIODecl:
\_io_decl: (amo), parent:master
|vpiName:amo
|vpiDirection:2
|vpiIODecl:
\_io_decl: (request), parent:master
|vpiName:request
|vpiDirection:2
|vpiIODecl:
\_io_decl: (ack), parent:master
|vpiName:ack
|vpiDirection:1
|vpiInterface:
\_interface: work@l1_arbiter_request_interface (l1_request7), file:third_party/cores/taiga/core/taiga.sv, line:45, parent:cpu
|vpiModport:
\_modport: (slave), parent:l1_request7
|vpiName:slave
|vpiIODecl:
\_io_decl: (addr), parent:slave
|vpiName:addr
|vpiDirection:1
|vpiIODecl:
\_io_decl: (data), parent:slave
|vpiName:data
|vpiDirection:1
|vpiIODecl:
\_io_decl: (rnw), parent:slave
|vpiName:rnw
|vpiDirection:1
|vpiIODecl:
\_io_decl: (be), parent:slave
|vpiName:be
|vpiDirection:1
|vpiIODecl:
\_io_decl: (size), parent:slave
|vpiName:size
|vpiDirection:1
|vpiIODecl:
\_io_decl: (is_amo), parent:slave
|vpiName:is_amo
|vpiDirection:1
|vpiIODecl:
\_io_decl: (amo), parent:slave
|vpiName:amo
|vpiDirection:1
|vpiIODecl:
\_io_decl: (request), parent:slave
|vpiName:request
|vpiDirection:1
|vpiIODecl:
\_io_decl: (ack), parent:slave
|vpiName:ack
|vpiDirection:2
|vpiInterface:
\_interface: work@l1_arbiter_request_interface (l1_request7), file:third_party/cores/taiga/core/taiga.sv, line:45, parent:cpu
|vpiNet:
\_logic_net: (addr), line:123, parent:l1_request7
|vpiName:addr
|vpiFullName:work@taiga_wrapper.cpu.l1_request7.addr
|vpiNetType:36
|vpiRange:
\_range: , line:123
|vpiLeftRange:
\_constant: , line:123
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:123
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (data), line:124, parent:l1_request7
|vpiName:data
|vpiFullName:work@taiga_wrapper.cpu.l1_request7.data
|vpiNetType:36
|vpiRange:
\_range: , line:124
|vpiLeftRange:
\_constant: , line:124
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:124
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (rnw), line:125, parent:l1_request7
|vpiName:rnw
|vpiFullName:work@taiga_wrapper.cpu.l1_request7.rnw
|vpiNetType:36
|vpiNet:
\_logic_net: (be), line:126, parent:l1_request7
|vpiName:be
|vpiFullName:work@taiga_wrapper.cpu.l1_request7.be
|vpiNetType:36
|vpiRange:
\_range: , line:126
|vpiLeftRange:
\_constant: , line:126
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiRightRange:
\_constant: , line:126
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (size), line:127, parent:l1_request7
|vpiName:size
|vpiFullName:work@taiga_wrapper.cpu.l1_request7.size
|vpiNetType:36
|vpiRange:
\_range: , line:127
|vpiLeftRange:
\_constant: , line:127
|vpiConstType:7
|vpiDecompile:4
|vpiSize:32
|INT:4
|vpiRightRange:
\_constant: , line:127
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (is_amo), line:128, parent:l1_request7
|vpiName:is_amo
|vpiFullName:work@taiga_wrapper.cpu.l1_request7.is_amo
|vpiNetType:36
|vpiNet:
\_logic_net: (amo), line:129, parent:l1_request7
|vpiName:amo
|vpiFullName:work@taiga_wrapper.cpu.l1_request7.amo
|vpiNetType:36
|vpiRange:
\_range: , line:129
|vpiLeftRange:
\_constant: , line:129
|vpiConstType:7
|vpiDecompile:4
|vpiSize:32
|INT:4
|vpiRightRange:
\_constant: , line:129
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (request), line:131, parent:l1_request7
|vpiName:request
|vpiFullName:work@taiga_wrapper.cpu.l1_request7.request
|vpiNetType:36
|vpiNet:
\_logic_net: (ack), line:132, parent:l1_request7
|vpiName:ack
|vpiFullName:work@taiga_wrapper.cpu.l1_request7.ack
|vpiNetType:36
|vpiInstance:
\_module: work@taiga (cpu), file:third_party/cores/taiga/examples/zedboard/taiga_wrapper.sv, line:233, parent:work@taiga_wrapper
|vpiInterface:
\_interface: work@l1_arbiter_request_interface (l1_request8), file:third_party/cores/taiga/core/taiga.sv, line:45, parent:cpu
|vpiDefName:work@l1_arbiter_request_interface
|vpiName:l1_request8
|vpiFullName:work@taiga_wrapper.cpu.l1_request8
|vpiModport:
\_modport: (master), parent:l1_request8
|vpiName:master
|vpiIODecl:
\_io_decl: (addr), parent:master
|vpiName:addr
|vpiDirection:2
|vpiIODecl:
\_io_decl: (data), parent:master
|vpiName:data
|vpiDirection:2
|vpiIODecl:
\_io_decl: (rnw), parent:master
|vpiName:rnw
|vpiDirection:2
|vpiIODecl:
\_io_decl: (be), parent:master
|vpiName:be
|vpiDirection:2
|vpiIODecl:
\_io_decl: (size), parent:master
|vpiName:size
|vpiDirection:2
|vpiIODecl:
\_io_decl: (is_amo), parent:master
|vpiName:is_amo
|vpiDirection:2
|vpiIODecl:
\_io_decl: (amo), parent:master
|vpiName:amo
|vpiDirection:2
|vpiIODecl:
\_io_decl: (request), parent:master
|vpiName:request
|vpiDirection:2
|vpiIODecl:
\_io_decl: (ack), parent:master
|vpiName:ack
|vpiDirection:1
|vpiInterface:
\_interface: work@l1_arbiter_request_interface (l1_request8), file:third_party/cores/taiga/core/taiga.sv, line:45, parent:cpu
|vpiModport:
\_modport: (slave), parent:l1_request8
|vpiName:slave
|vpiIODecl:
\_io_decl: (addr), parent:slave
|vpiName:addr
|vpiDirection:1
|vpiIODecl:
\_io_decl: (data), parent:slave
|vpiName:data
|vpiDirection:1
|vpiIODecl:
\_io_decl: (rnw), parent:slave
|vpiName:rnw
|vpiDirection:1
|vpiIODecl:
\_io_decl: (be), parent:slave
|vpiName:be
|vpiDirection:1
|vpiIODecl:
\_io_decl: (size), parent:slave
|vpiName:size
|vpiDirection:1
|vpiIODecl:
\_io_decl: (is_amo), parent:slave
|vpiName:is_amo
|vpiDirection:1
|vpiIODecl:
\_io_decl: (amo), parent:slave
|vpiName:amo
|vpiDirection:1
|vpiIODecl:
\_io_decl: (request), parent:slave
|vpiName:request
|vpiDirection:1
|vpiIODecl:
\_io_decl: (ack), parent:slave
|vpiName:ack
|vpiDirection:2
|vpiInterface:
\_interface: work@l1_arbiter_request_interface (l1_request8), file:third_party/cores/taiga/core/taiga.sv, line:45, parent:cpu
|vpiNet:
\_logic_net: (addr), line:123, parent:l1_request8
|vpiName:addr
|vpiFullName:work@taiga_wrapper.cpu.l1_request8.addr
|vpiNetType:36
|vpiRange:
\_range: , line:123
|vpiLeftRange:
\_constant: , line:123
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:123
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (data), line:124, parent:l1_request8
|vpiName:data
|vpiFullName:work@taiga_wrapper.cpu.l1_request8.data
|vpiNetType:36
|vpiRange:
\_range: , line:124
|vpiLeftRange:
\_constant: , line:124
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:124
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (rnw), line:125, parent:l1_request8
|vpiName:rnw
|vpiFullName:work@taiga_wrapper.cpu.l1_request8.rnw
|vpiNetType:36
|vpiNet:
\_logic_net: (be), line:126, parent:l1_request8
|vpiName:be
|vpiFullName:work@taiga_wrapper.cpu.l1_request8.be
|vpiNetType:36
|vpiRange:
\_range: , line:126
|vpiLeftRange:
\_constant: , line:126
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiRightRange:
\_constant: , line:126
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (size), line:127, parent:l1_request8
|vpiName:size
|vpiFullName:work@taiga_wrapper.cpu.l1_request8.size
|vpiNetType:36
|vpiRange:
\_range: , line:127
|vpiLeftRange:
\_constant: , line:127
|vpiConstType:7
|vpiDecompile:4
|vpiSize:32
|INT:4
|vpiRightRange:
\_constant: , line:127
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (is_amo), line:128, parent:l1_request8
|vpiName:is_amo
|vpiFullName:work@taiga_wrapper.cpu.l1_request8.is_amo
|vpiNetType:36
|vpiNet:
\_logic_net: (amo), line:129, parent:l1_request8
|vpiName:amo
|vpiFullName:work@taiga_wrapper.cpu.l1_request8.amo
|vpiNetType:36
|vpiRange:
\_range: , line:129
|vpiLeftRange:
\_constant: , line:129
|vpiConstType:7
|vpiDecompile:4
|vpiSize:32
|INT:4
|vpiRightRange:
\_constant: , line:129
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (request), line:131, parent:l1_request8
|vpiName:request
|vpiFullName:work@taiga_wrapper.cpu.l1_request8.request
|vpiNetType:36
|vpiNet:
\_logic_net: (ack), line:132, parent:l1_request8
|vpiName:ack
|vpiFullName:work@taiga_wrapper.cpu.l1_request8.ack
|vpiNetType:36
|vpiInstance:
\_module: work@taiga (cpu), file:third_party/cores/taiga/examples/zedboard/taiga_wrapper.sv, line:233, parent:work@taiga_wrapper
|vpiInterface:
\_interface: work@l1_arbiter_return_interface (l1_response0), file:third_party/cores/taiga/core/taiga.sv, line:46, parent:cpu
|vpiDefName:work@l1_arbiter_return_interface
|vpiName:l1_response0
|vpiFullName:work@taiga_wrapper.cpu.l1_response0
|vpiModport:
\_modport: (master), parent:l1_response0
|vpiName:master
|vpiIODecl:
\_io_decl: (inv_addr), parent:master
|vpiName:inv_addr
|vpiDirection:1
|vpiIODecl:
\_io_decl: (inv_valid), parent:master
|vpiName:inv_valid
|vpiDirection:1
|vpiIODecl:
\_io_decl: (data), parent:master
|vpiName:data
|vpiDirection:1
|vpiIODecl:
\_io_decl: (data_valid), parent:master
|vpiName:data_valid
|vpiDirection:1
|vpiIODecl:
\_io_decl: (inv_ack), parent:master
|vpiName:inv_ack
|vpiDirection:2
|vpiInterface:
\_interface: work@l1_arbiter_return_interface (l1_response0), file:third_party/cores/taiga/core/taiga.sv, line:46, parent:cpu
|vpiModport:
\_modport: (slave), parent:l1_response0
|vpiName:slave
|vpiIODecl:
\_io_decl: (inv_addr), parent:slave
|vpiName:inv_addr
|vpiDirection:2
|vpiIODecl:
\_io_decl: (inv_valid), parent:slave
|vpiName:inv_valid
|vpiDirection:2
|vpiIODecl:
\_io_decl: (data), parent:slave
|vpiName:data
|vpiDirection:2
|vpiIODecl:
\_io_decl: (data_valid), parent:slave
|vpiName:data_valid
|vpiDirection:2
|vpiIODecl:
\_io_decl: (inv_ack), parent:slave
|vpiName:inv_ack
|vpiDirection:1
|vpiInterface:
\_interface: work@l1_arbiter_return_interface (l1_response0), file:third_party/cores/taiga/core/taiga.sv, line:46, parent:cpu
|vpiNet:
\_logic_net: (inv_addr), line:149, parent:l1_response0
|vpiName:inv_addr
|vpiFullName:work@taiga_wrapper.cpu.l1_response0.inv_addr
|vpiNetType:36
|vpiRange:
\_range: , line:149
|vpiLeftRange:
\_constant: , line:149
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:149
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiNet:
\_logic_net: (inv_valid), line:150, parent:l1_response0
|vpiName:inv_valid
|vpiFullName:work@taiga_wrapper.cpu.l1_response0.inv_valid
|vpiNetType:36
|vpiNet:
\_logic_net: (inv_ack), line:151, parent:l1_response0
|vpiName:inv_ack
|vpiFullName:work@taiga_wrapper.cpu.l1_response0.inv_ack
|vpiNetType:36
|vpiNet:
\_logic_net: (data), line:152, parent:l1_response0
|vpiName:data
|vpiFullName:work@taiga_wrapper.cpu.l1_response0.data
|vpiNetType:36
|vpiRange:
\_range: , line:152
|vpiLeftRange:
\_constant: , line:152
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:152
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (data_valid), line:153, parent:l1_response0
|vpiName:data_valid
|vpiFullName:work@taiga_wrapper.cpu.l1_response0.data_valid
|vpiNetType:36
|vpiInstance:
\_module: work@taiga (cpu), file:third_party/cores/taiga/examples/zedboard/taiga_wrapper.sv, line:233, parent:work@taiga_wrapper
|vpiInterface:
\_interface: work@l1_arbiter_return_interface (l1_response1), file:third_party/cores/taiga/core/taiga.sv, line:46, parent:cpu
|vpiDefName:work@l1_arbiter_return_interface
|vpiName:l1_response1
|vpiFullName:work@taiga_wrapper.cpu.l1_response1
|vpiModport:
\_modport: (master), parent:l1_response1
|vpiName:master
|vpiIODecl:
\_io_decl: (inv_addr), parent:master
|vpiName:inv_addr
|vpiDirection:1
|vpiIODecl:
\_io_decl: (inv_valid), parent:master
|vpiName:inv_valid
|vpiDirection:1
|vpiIODecl:
\_io_decl: (data), parent:master
|vpiName:data
|vpiDirection:1
|vpiIODecl:
\_io_decl: (data_valid), parent:master
|vpiName:data_valid
|vpiDirection:1
|vpiIODecl:
\_io_decl: (inv_ack), parent:master
|vpiName:inv_ack
|vpiDirection:2
|vpiInterface:
\_interface: work@l1_arbiter_return_interface (l1_response1), file:third_party/cores/taiga/core/taiga.sv, line:46, parent:cpu
|vpiModport:
\_modport: (slave), parent:l1_response1
|vpiName:slave
|vpiIODecl:
\_io_decl: (inv_addr), parent:slave
|vpiName:inv_addr
|vpiDirection:2
|vpiIODecl:
\_io_decl: (inv_valid), parent:slave
|vpiName:inv_valid
|vpiDirection:2
|vpiIODecl:
\_io_decl: (data), parent:slave
|vpiName:data
|vpiDirection:2
|vpiIODecl:
\_io_decl: (data_valid), parent:slave
|vpiName:data_valid
|vpiDirection:2
|vpiIODecl:
\_io_decl: (inv_ack), parent:slave
|vpiName:inv_ack
|vpiDirection:1
|vpiInterface:
\_interface: work@l1_arbiter_return_interface (l1_response1), file:third_party/cores/taiga/core/taiga.sv, line:46, parent:cpu
|vpiNet:
\_logic_net: (inv_addr), line:149, parent:l1_response1
|vpiName:inv_addr
|vpiFullName:work@taiga_wrapper.cpu.l1_response1.inv_addr
|vpiNetType:36
|vpiRange:
\_range: , line:149
|vpiLeftRange:
\_constant: , line:149
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:149
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiNet:
\_logic_net: (inv_valid), line:150, parent:l1_response1
|vpiName:inv_valid
|vpiFullName:work@taiga_wrapper.cpu.l1_response1.inv_valid
|vpiNetType:36
|vpiNet:
\_logic_net: (inv_ack), line:151, parent:l1_response1
|vpiName:inv_ack
|vpiFullName:work@taiga_wrapper.cpu.l1_response1.inv_ack
|vpiNetType:36
|vpiNet:
\_logic_net: (data), line:152, parent:l1_response1
|vpiName:data
|vpiFullName:work@taiga_wrapper.cpu.l1_response1.data
|vpiNetType:36
|vpiRange:
\_range: , line:152
|vpiLeftRange:
\_constant: , line:152
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:152
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (data_valid), line:153, parent:l1_response1
|vpiName:data_valid
|vpiFullName:work@taiga_wrapper.cpu.l1_response1.data_valid
|vpiNetType:36
|vpiInstance:
\_module: work@taiga (cpu), file:third_party/cores/taiga/examples/zedboard/taiga_wrapper.sv, line:233, parent:work@taiga_wrapper
|vpiInterface:
\_interface: work@l1_arbiter_return_interface (l1_response2), file:third_party/cores/taiga/core/taiga.sv, line:46, parent:cpu
|vpiDefName:work@l1_arbiter_return_interface
|vpiName:l1_response2
|vpiFullName:work@taiga_wrapper.cpu.l1_response2
|vpiModport:
\_modport: (master), parent:l1_response2
|vpiName:master
|vpiIODecl:
\_io_decl: (inv_addr), parent:master
|vpiName:inv_addr
|vpiDirection:1
|vpiIODecl:
\_io_decl: (inv_valid), parent:master
|vpiName:inv_valid
|vpiDirection:1
|vpiIODecl:
\_io_decl: (data), parent:master
|vpiName:data
|vpiDirection:1
|vpiIODecl:
\_io_decl: (data_valid), parent:master
|vpiName:data_valid
|vpiDirection:1
|vpiIODecl:
\_io_decl: (inv_ack), parent:master
|vpiName:inv_ack
|vpiDirection:2
|vpiInterface:
\_interface: work@l1_arbiter_return_interface (l1_response2), file:third_party/cores/taiga/core/taiga.sv, line:46, parent:cpu
|vpiModport:
\_modport: (slave), parent:l1_response2
|vpiName:slave
|vpiIODecl:
\_io_decl: (inv_addr), parent:slave
|vpiName:inv_addr
|vpiDirection:2
|vpiIODecl:
\_io_decl: (inv_valid), parent:slave
|vpiName:inv_valid
|vpiDirection:2
|vpiIODecl:
\_io_decl: (data), parent:slave
|vpiName:data
|vpiDirection:2
|vpiIODecl:
\_io_decl: (data_valid), parent:slave
|vpiName:data_valid
|vpiDirection:2
|vpiIODecl:
\_io_decl: (inv_ack), parent:slave
|vpiName:inv_ack
|vpiDirection:1
|vpiInterface:
\_interface: work@l1_arbiter_return_interface (l1_response2), file:third_party/cores/taiga/core/taiga.sv, line:46, parent:cpu
|vpiNet:
\_logic_net: (inv_addr), line:149, parent:l1_response2
|vpiName:inv_addr
|vpiFullName:work@taiga_wrapper.cpu.l1_response2.inv_addr
|vpiNetType:36
|vpiRange:
\_range: , line:149
|vpiLeftRange:
\_constant: , line:149
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:149
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiNet:
\_logic_net: (inv_valid), line:150, parent:l1_response2
|vpiName:inv_valid
|vpiFullName:work@taiga_wrapper.cpu.l1_response2.inv_valid
|vpiNetType:36
|vpiNet:
\_logic_net: (inv_ack), line:151, parent:l1_response2
|vpiName:inv_ack
|vpiFullName:work@taiga_wrapper.cpu.l1_response2.inv_ack
|vpiNetType:36
|vpiNet:
\_logic_net: (data), line:152, parent:l1_response2
|vpiName:data
|vpiFullName:work@taiga_wrapper.cpu.l1_response2.data
|vpiNetType:36
|vpiRange:
\_range: , line:152
|vpiLeftRange:
\_constant: , line:152
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:152
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (data_valid), line:153, parent:l1_response2
|vpiName:data_valid
|vpiFullName:work@taiga_wrapper.cpu.l1_response2.data_valid
|vpiNetType:36
|vpiInstance:
\_module: work@taiga (cpu), file:third_party/cores/taiga/examples/zedboard/taiga_wrapper.sv, line:233, parent:work@taiga_wrapper
|vpiInterface:
\_interface: work@l1_arbiter_return_interface (l1_response3), file:third_party/cores/taiga/core/taiga.sv, line:46, parent:cpu
|vpiDefName:work@l1_arbiter_return_interface
|vpiName:l1_response3
|vpiFullName:work@taiga_wrapper.cpu.l1_response3
|vpiModport:
\_modport: (master), parent:l1_response3
|vpiName:master
|vpiIODecl:
\_io_decl: (inv_addr), parent:master
|vpiName:inv_addr
|vpiDirection:1
|vpiIODecl:
\_io_decl: (inv_valid), parent:master
|vpiName:inv_valid
|vpiDirection:1
|vpiIODecl:
\_io_decl: (data), parent:master
|vpiName:data
|vpiDirection:1
|vpiIODecl:
\_io_decl: (data_valid), parent:master
|vpiName:data_valid
|vpiDirection:1
|vpiIODecl:
\_io_decl: (inv_ack), parent:master
|vpiName:inv_ack
|vpiDirection:2
|vpiInterface:
\_interface: work@l1_arbiter_return_interface (l1_response3), file:third_party/cores/taiga/core/taiga.sv, line:46, parent:cpu
|vpiModport:
\_modport: (slave), parent:l1_response3
|vpiName:slave
|vpiIODecl:
\_io_decl: (inv_addr), parent:slave
|vpiName:inv_addr
|vpiDirection:2
|vpiIODecl:
\_io_decl: (inv_valid), parent:slave
|vpiName:inv_valid
|vpiDirection:2
|vpiIODecl:
\_io_decl: (data), parent:slave
|vpiName:data
|vpiDirection:2
|vpiIODecl:
\_io_decl: (data_valid), parent:slave
|vpiName:data_valid
|vpiDirection:2
|vpiIODecl:
\_io_decl: (inv_ack), parent:slave
|vpiName:inv_ack
|vpiDirection:1
|vpiInterface:
\_interface: work@l1_arbiter_return_interface (l1_response3), file:third_party/cores/taiga/core/taiga.sv, line:46, parent:cpu
|vpiNet:
\_logic_net: (inv_addr), line:149, parent:l1_response3
|vpiName:inv_addr
|vpiFullName:work@taiga_wrapper.cpu.l1_response3.inv_addr
|vpiNetType:36
|vpiRange:
\_range: , line:149
|vpiLeftRange:
\_constant: , line:149
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:149
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiNet:
\_logic_net: (inv_valid), line:150, parent:l1_response3
|vpiName:inv_valid
|vpiFullName:work@taiga_wrapper.cpu.l1_response3.inv_valid
|vpiNetType:36
|vpiNet:
\_logic_net: (inv_ack), line:151, parent:l1_response3
|vpiName:inv_ack
|vpiFullName:work@taiga_wrapper.cpu.l1_response3.inv_ack
|vpiNetType:36
|vpiNet:
\_logic_net: (data), line:152, parent:l1_response3
|vpiName:data
|vpiFullName:work@taiga_wrapper.cpu.l1_response3.data
|vpiNetType:36
|vpiRange:
\_range: , line:152
|vpiLeftRange:
\_constant: , line:152
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:152
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (data_valid), line:153, parent:l1_response3
|vpiName:data_valid
|vpiFullName:work@taiga_wrapper.cpu.l1_response3.data_valid
|vpiNetType:36
|vpiInstance:
\_module: work@taiga (cpu), file:third_party/cores/taiga/examples/zedboard/taiga_wrapper.sv, line:233, parent:work@taiga_wrapper
|vpiInterface:
\_interface: work@l1_arbiter_return_interface (l1_response4), file:third_party/cores/taiga/core/taiga.sv, line:46, parent:cpu
|vpiDefName:work@l1_arbiter_return_interface
|vpiName:l1_response4
|vpiFullName:work@taiga_wrapper.cpu.l1_response4
|vpiModport:
\_modport: (master), parent:l1_response4
|vpiName:master
|vpiIODecl:
\_io_decl: (inv_addr), parent:master
|vpiName:inv_addr
|vpiDirection:1
|vpiIODecl:
\_io_decl: (inv_valid), parent:master
|vpiName:inv_valid
|vpiDirection:1
|vpiIODecl:
\_io_decl: (data), parent:master
|vpiName:data
|vpiDirection:1
|vpiIODecl:
\_io_decl: (data_valid), parent:master
|vpiName:data_valid
|vpiDirection:1
|vpiIODecl:
\_io_decl: (inv_ack), parent:master
|vpiName:inv_ack
|vpiDirection:2
|vpiInterface:
\_interface: work@l1_arbiter_return_interface (l1_response4), file:third_party/cores/taiga/core/taiga.sv, line:46, parent:cpu
|vpiModport:
\_modport: (slave), parent:l1_response4
|vpiName:slave
|vpiIODecl:
\_io_decl: (inv_addr), parent:slave
|vpiName:inv_addr
|vpiDirection:2
|vpiIODecl:
\_io_decl: (inv_valid), parent:slave
|vpiName:inv_valid
|vpiDirection:2
|vpiIODecl:
\_io_decl: (data), parent:slave
|vpiName:data
|vpiDirection:2
|vpiIODecl:
\_io_decl: (data_valid), parent:slave
|vpiName:data_valid
|vpiDirection:2
|vpiIODecl:
\_io_decl: (inv_ack), parent:slave
|vpiName:inv_ack
|vpiDirection:1
|vpiInterface:
\_interface: work@l1_arbiter_return_interface (l1_response4), file:third_party/cores/taiga/core/taiga.sv, line:46, parent:cpu
|vpiNet:
\_logic_net: (inv_addr), line:149, parent:l1_response4
|vpiName:inv_addr
|vpiFullName:work@taiga_wrapper.cpu.l1_response4.inv_addr
|vpiNetType:36
|vpiRange:
\_range: , line:149
|vpiLeftRange:
\_constant: , line:149
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:149
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiNet:
\_logic_net: (inv_valid), line:150, parent:l1_response4
|vpiName:inv_valid
|vpiFullName:work@taiga_wrapper.cpu.l1_response4.inv_valid
|vpiNetType:36
|vpiNet:
\_logic_net: (inv_ack), line:151, parent:l1_response4
|vpiName:inv_ack
|vpiFullName:work@taiga_wrapper.cpu.l1_response4.inv_ack
|vpiNetType:36
|vpiNet:
\_logic_net: (data), line:152, parent:l1_response4
|vpiName:data
|vpiFullName:work@taiga_wrapper.cpu.l1_response4.data
|vpiNetType:36
|vpiRange:
\_range: , line:152
|vpiLeftRange:
\_constant: , line:152
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:152
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (data_valid), line:153, parent:l1_response4
|vpiName:data_valid
|vpiFullName:work@taiga_wrapper.cpu.l1_response4.data_valid
|vpiNetType:36
|vpiInstance:
\_module: work@taiga (cpu), file:third_party/cores/taiga/examples/zedboard/taiga_wrapper.sv, line:233, parent:work@taiga_wrapper
|vpiInterface:
\_interface: work@l1_arbiter_return_interface (l1_response5), file:third_party/cores/taiga/core/taiga.sv, line:46, parent:cpu
|vpiDefName:work@l1_arbiter_return_interface
|vpiName:l1_response5
|vpiFullName:work@taiga_wrapper.cpu.l1_response5
|vpiModport:
\_modport: (master), parent:l1_response5
|vpiName:master
|vpiIODecl:
\_io_decl: (inv_addr), parent:master
|vpiName:inv_addr
|vpiDirection:1
|vpiIODecl:
\_io_decl: (inv_valid), parent:master
|vpiName:inv_valid
|vpiDirection:1
|vpiIODecl:
\_io_decl: (data), parent:master
|vpiName:data
|vpiDirection:1
|vpiIODecl:
\_io_decl: (data_valid), parent:master
|vpiName:data_valid
|vpiDirection:1
|vpiIODecl:
\_io_decl: (inv_ack), parent:master
|vpiName:inv_ack
|vpiDirection:2
|vpiInterface:
\_interface: work@l1_arbiter_return_interface (l1_response5), file:third_party/cores/taiga/core/taiga.sv, line:46, parent:cpu
|vpiModport:
\_modport: (slave), parent:l1_response5
|vpiName:slave
|vpiIODecl:
\_io_decl: (inv_addr), parent:slave
|vpiName:inv_addr
|vpiDirection:2
|vpiIODecl:
\_io_decl: (inv_valid), parent:slave
|vpiName:inv_valid
|vpiDirection:2
|vpiIODecl:
\_io_decl: (data), parent:slave
|vpiName:data
|vpiDirection:2
|vpiIODecl:
\_io_decl: (data_valid), parent:slave
|vpiName:data_valid
|vpiDirection:2
|vpiIODecl:
\_io_decl: (inv_ack), parent:slave
|vpiName:inv_ack
|vpiDirection:1
|vpiInterface:
\_interface: work@l1_arbiter_return_interface (l1_response5), file:third_party/cores/taiga/core/taiga.sv, line:46, parent:cpu
|vpiNet:
\_logic_net: (inv_addr), line:149, parent:l1_response5
|vpiName:inv_addr
|vpiFullName:work@taiga_wrapper.cpu.l1_response5.inv_addr
|vpiNetType:36
|vpiRange:
\_range: , line:149
|vpiLeftRange:
\_constant: , line:149
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:149
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiNet:
\_logic_net: (inv_valid), line:150, parent:l1_response5
|vpiName:inv_valid
|vpiFullName:work@taiga_wrapper.cpu.l1_response5.inv_valid
|vpiNetType:36
|vpiNet:
\_logic_net: (inv_ack), line:151, parent:l1_response5
|vpiName:inv_ack
|vpiFullName:work@taiga_wrapper.cpu.l1_response5.inv_ack
|vpiNetType:36
|vpiNet:
\_logic_net: (data), line:152, parent:l1_response5
|vpiName:data
|vpiFullName:work@taiga_wrapper.cpu.l1_response5.data
|vpiNetType:36
|vpiRange:
\_range: , line:152
|vpiLeftRange:
\_constant: , line:152
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:152
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (data_valid), line:153, parent:l1_response5
|vpiName:data_valid
|vpiFullName:work@taiga_wrapper.cpu.l1_response5.data_valid
|vpiNetType:36
|vpiInstance:
\_module: work@taiga (cpu), file:third_party/cores/taiga/examples/zedboard/taiga_wrapper.sv, line:233, parent:work@taiga_wrapper
|vpiInterface:
\_interface: work@l1_arbiter_return_interface (l1_response6), file:third_party/cores/taiga/core/taiga.sv, line:46, parent:cpu
|vpiDefName:work@l1_arbiter_return_interface
|vpiName:l1_response6
|vpiFullName:work@taiga_wrapper.cpu.l1_response6
|vpiModport:
\_modport: (master), parent:l1_response6
|vpiName:master
|vpiIODecl:
\_io_decl: (inv_addr), parent:master
|vpiName:inv_addr
|vpiDirection:1
|vpiIODecl:
\_io_decl: (inv_valid), parent:master
|vpiName:inv_valid
|vpiDirection:1
|vpiIODecl:
\_io_decl: (data), parent:master
|vpiName:data
|vpiDirection:1
|vpiIODecl:
\_io_decl: (data_valid), parent:master
|vpiName:data_valid
|vpiDirection:1
|vpiIODecl:
\_io_decl: (inv_ack), parent:master
|vpiName:inv_ack
|vpiDirection:2
|vpiInterface:
\_interface: work@l1_arbiter_return_interface (l1_response6), file:third_party/cores/taiga/core/taiga.sv, line:46, parent:cpu
|vpiModport:
\_modport: (slave), parent:l1_response6
|vpiName:slave
|vpiIODecl:
\_io_decl: (inv_addr), parent:slave
|vpiName:inv_addr
|vpiDirection:2
|vpiIODecl:
\_io_decl: (inv_valid), parent:slave
|vpiName:inv_valid
|vpiDirection:2
|vpiIODecl:
\_io_decl: (data), parent:slave
|vpiName:data
|vpiDirection:2
|vpiIODecl:
\_io_decl: (data_valid), parent:slave
|vpiName:data_valid
|vpiDirection:2
|vpiIODecl:
\_io_decl: (inv_ack), parent:slave
|vpiName:inv_ack
|vpiDirection:1
|vpiInterface:
\_interface: work@l1_arbiter_return_interface (l1_response6), file:third_party/cores/taiga/core/taiga.sv, line:46, parent:cpu
|vpiNet:
\_logic_net: (inv_addr), line:149, parent:l1_response6
|vpiName:inv_addr
|vpiFullName:work@taiga_wrapper.cpu.l1_response6.inv_addr
|vpiNetType:36
|vpiRange:
\_range: , line:149
|vpiLeftRange:
\_constant: , line:149
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:149
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiNet:
\_logic_net: (inv_valid), line:150, parent:l1_response6
|vpiName:inv_valid
|vpiFullName:work@taiga_wrapper.cpu.l1_response6.inv_valid
|vpiNetType:36
|vpiNet:
\_logic_net: (inv_ack), line:151, parent:l1_response6
|vpiName:inv_ack
|vpiFullName:work@taiga_wrapper.cpu.l1_response6.inv_ack
|vpiNetType:36
|vpiNet:
\_logic_net: (data), line:152, parent:l1_response6
|vpiName:data
|vpiFullName:work@taiga_wrapper.cpu.l1_response6.data
|vpiNetType:36
|vpiRange:
\_range: , line:152
|vpiLeftRange:
\_constant: , line:152
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:152
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (data_valid), line:153, parent:l1_response6
|vpiName:data_valid
|vpiFullName:work@taiga_wrapper.cpu.l1_response6.data_valid
|vpiNetType:36
|vpiInstance:
\_module: work@taiga (cpu), file:third_party/cores/taiga/examples/zedboard/taiga_wrapper.sv, line:233, parent:work@taiga_wrapper
|vpiInterface:
\_interface: work@l1_arbiter_return_interface (l1_response7), file:third_party/cores/taiga/core/taiga.sv, line:46, parent:cpu
|vpiDefName:work@l1_arbiter_return_interface
|vpiName:l1_response7
|vpiFullName:work@taiga_wrapper.cpu.l1_response7
|vpiModport:
\_modport: (master), parent:l1_response7
|vpiName:master
|vpiIODecl:
\_io_decl: (inv_addr), parent:master
|vpiName:inv_addr
|vpiDirection:1
|vpiIODecl:
\_io_decl: (inv_valid), parent:master
|vpiName:inv_valid
|vpiDirection:1
|vpiIODecl:
\_io_decl: (data), parent:master
|vpiName:data
|vpiDirection:1
|vpiIODecl:
\_io_decl: (data_valid), parent:master
|vpiName:data_valid
|vpiDirection:1
|vpiIODecl:
\_io_decl: (inv_ack), parent:master
|vpiName:inv_ack
|vpiDirection:2
|vpiInterface:
\_interface: work@l1_arbiter_return_interface (l1_response7), file:third_party/cores/taiga/core/taiga.sv, line:46, parent:cpu
|vpiModport:
\_modport: (slave), parent:l1_response7
|vpiName:slave
|vpiIODecl:
\_io_decl: (inv_addr), parent:slave
|vpiName:inv_addr
|vpiDirection:2
|vpiIODecl:
\_io_decl: (inv_valid), parent:slave
|vpiName:inv_valid
|vpiDirection:2
|vpiIODecl:
\_io_decl: (data), parent:slave
|vpiName:data
|vpiDirection:2
|vpiIODecl:
\_io_decl: (data_valid), parent:slave
|vpiName:data_valid
|vpiDirection:2
|vpiIODecl:
\_io_decl: (inv_ack), parent:slave
|vpiName:inv_ack
|vpiDirection:1
|vpiInterface:
\_interface: work@l1_arbiter_return_interface (l1_response7), file:third_party/cores/taiga/core/taiga.sv, line:46, parent:cpu
|vpiNet:
\_logic_net: (inv_addr), line:149, parent:l1_response7
|vpiName:inv_addr
|vpiFullName:work@taiga_wrapper.cpu.l1_response7.inv_addr
|vpiNetType:36
|vpiRange:
\_range: , line:149
|vpiLeftRange:
\_constant: , line:149
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:149
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiNet:
\_logic_net: (inv_valid), line:150, parent:l1_response7
|vpiName:inv_valid
|vpiFullName:work@taiga_wrapper.cpu.l1_response7.inv_valid
|vpiNetType:36
|vpiNet:
\_logic_net: (inv_ack), line:151, parent:l1_response7
|vpiName:inv_ack
|vpiFullName:work@taiga_wrapper.cpu.l1_response7.inv_ack
|vpiNetType:36
|vpiNet:
\_logic_net: (data), line:152, parent:l1_response7
|vpiName:data
|vpiFullName:work@taiga_wrapper.cpu.l1_response7.data
|vpiNetType:36
|vpiRange:
\_range: , line:152
|vpiLeftRange:
\_constant: , line:152
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:152
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (data_valid), line:153, parent:l1_response7
|vpiName:data_valid
|vpiFullName:work@taiga_wrapper.cpu.l1_response7.data_valid
|vpiNetType:36
|vpiInstance:
\_module: work@taiga (cpu), file:third_party/cores/taiga/examples/zedboard/taiga_wrapper.sv, line:233, parent:work@taiga_wrapper
|vpiInterface:
\_interface: work@l1_arbiter_return_interface (l1_response8), file:third_party/cores/taiga/core/taiga.sv, line:46, parent:cpu
|vpiDefName:work@l1_arbiter_return_interface
|vpiName:l1_response8
|vpiFullName:work@taiga_wrapper.cpu.l1_response8
|vpiModport:
\_modport: (master), parent:l1_response8
|vpiName:master
|vpiIODecl:
\_io_decl: (inv_addr), parent:master
|vpiName:inv_addr
|vpiDirection:1
|vpiIODecl:
\_io_decl: (inv_valid), parent:master
|vpiName:inv_valid
|vpiDirection:1
|vpiIODecl:
\_io_decl: (data), parent:master
|vpiName:data
|vpiDirection:1
|vpiIODecl:
\_io_decl: (data_valid), parent:master
|vpiName:data_valid
|vpiDirection:1
|vpiIODecl:
\_io_decl: (inv_ack), parent:master
|vpiName:inv_ack
|vpiDirection:2
|vpiInterface:
\_interface: work@l1_arbiter_return_interface (l1_response8), file:third_party/cores/taiga/core/taiga.sv, line:46, parent:cpu
|vpiModport:
\_modport: (slave), parent:l1_response8
|vpiName:slave
|vpiIODecl:
\_io_decl: (inv_addr), parent:slave
|vpiName:inv_addr
|vpiDirection:2
|vpiIODecl:
\_io_decl: (inv_valid), parent:slave
|vpiName:inv_valid
|vpiDirection:2
|vpiIODecl:
\_io_decl: (data), parent:slave
|vpiName:data
|vpiDirection:2
|vpiIODecl:
\_io_decl: (data_valid), parent:slave
|vpiName:data_valid
|vpiDirection:2
|vpiIODecl:
\_io_decl: (inv_ack), parent:slave
|vpiName:inv_ack
|vpiDirection:1
|vpiInterface:
\_interface: work@l1_arbiter_return_interface (l1_response8), file:third_party/cores/taiga/core/taiga.sv, line:46, parent:cpu
|vpiNet:
\_logic_net: (inv_addr), line:149, parent:l1_response8
|vpiName:inv_addr
|vpiFullName:work@taiga_wrapper.cpu.l1_response8.inv_addr
|vpiNetType:36
|vpiRange:
\_range: , line:149
|vpiLeftRange:
\_constant: , line:149
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:149
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiNet:
\_logic_net: (inv_valid), line:150, parent:l1_response8
|vpiName:inv_valid
|vpiFullName:work@taiga_wrapper.cpu.l1_response8.inv_valid
|vpiNetType:36
|vpiNet:
\_logic_net: (inv_ack), line:151, parent:l1_response8
|vpiName:inv_ack
|vpiFullName:work@taiga_wrapper.cpu.l1_response8.inv_ack
|vpiNetType:36
|vpiNet:
\_logic_net: (data), line:152, parent:l1_response8
|vpiName:data
|vpiFullName:work@taiga_wrapper.cpu.l1_response8.data
|vpiNetType:36
|vpiRange:
\_range: , line:152
|vpiLeftRange:
\_constant: , line:152
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:152
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (data_valid), line:153, parent:l1_response8
|vpiName:data_valid
|vpiFullName:work@taiga_wrapper.cpu.l1_response8.data_valid
|vpiNetType:36
|vpiInstance:
\_module: work@taiga (cpu), file:third_party/cores/taiga/examples/zedboard/taiga_wrapper.sv, line:233, parent:work@taiga_wrapper
|vpiInterface:
\_interface: work@branch_predictor_interface (bp), file:third_party/cores/taiga/core/taiga.sv, line:50, parent:cpu
|vpiDefName:work@branch_predictor_interface
|vpiName:bp
|vpiFullName:work@taiga_wrapper.cpu.bp
|vpiModport:
\_modport: (branch_predictor), parent:bp
|vpiName:branch_predictor
|vpiIODecl:
\_io_decl: (if_pc), parent:branch_predictor
|vpiName:if_pc
|vpiDirection:1
|vpiIODecl:
\_io_decl: (new_mem_request), parent:branch_predictor
|vpiName:new_mem_request
|vpiDirection:1
|vpiIODecl:
\_io_decl: (next_pc), parent:branch_predictor
|vpiName:next_pc
|vpiDirection:1
|vpiIODecl:
\_io_decl: (branch_flush_pc), parent:branch_predictor
|vpiName:branch_flush_pc
|vpiDirection:2
|vpiIODecl:
\_io_decl: (predicted_pc), parent:branch_predictor
|vpiName:predicted_pc
|vpiDirection:2
|vpiIODecl:
\_io_decl: (use_prediction), parent:branch_predictor
|vpiName:use_prediction
|vpiDirection:2
|vpiIODecl:
\_io_decl: (update_way), parent:branch_predictor
|vpiName:update_way
|vpiDirection:2
|vpiIODecl:
\_io_decl: (use_ras), parent:branch_predictor
|vpiName:use_ras
|vpiDirection:2
|vpiIODecl:
\_io_decl: (metadata), parent:branch_predictor
|vpiName:metadata
|vpiDirection:2
|vpiInterface:
\_interface: work@branch_predictor_interface (bp), file:third_party/cores/taiga/core/taiga.sv, line:50, parent:cpu
|vpiModport:
\_modport: (fetch), parent:bp
|vpiName:fetch
|vpiIODecl:
\_io_decl: (branch_flush_pc), parent:fetch
|vpiName:branch_flush_pc
|vpiDirection:1
|vpiIODecl:
\_io_decl: (predicted_pc), parent:fetch
|vpiName:predicted_pc
|vpiDirection:1
|vpiIODecl:
\_io_decl: (use_prediction), parent:fetch
|vpiName:use_prediction
|vpiDirection:1
|vpiIODecl:
\_io_decl: (update_way), parent:fetch
|vpiName:update_way
|vpiDirection:1
|vpiIODecl:
\_io_decl: (use_ras), parent:fetch
|vpiName:use_ras
|vpiDirection:1
|vpiIODecl:
\_io_decl: (metadata), parent:fetch
|vpiName:metadata
|vpiDirection:1
|vpiIODecl:
\_io_decl: (if_pc), parent:fetch
|vpiName:if_pc
|vpiDirection:2
|vpiIODecl:
\_io_decl: (new_mem_request), parent:fetch
|vpiName:new_mem_request
|vpiDirection:2
|vpiIODecl:
\_io_decl: (next_pc), parent:fetch
|vpiName:next_pc
|vpiDirection:2
|vpiInterface:
\_interface: work@branch_predictor_interface (bp), file:third_party/cores/taiga/core/taiga.sv, line:50, parent:cpu
|vpiNet:
\_logic_net: (if_pc), line:29, parent:bp
|vpiName:if_pc
|vpiFullName:work@taiga_wrapper.cpu.bp.if_pc
|vpiNetType:36
|vpiRange:
\_range: , line:29
|vpiLeftRange:
\_constant: , line:29
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:29
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (new_mem_request), line:30, parent:bp
|vpiName:new_mem_request
|vpiFullName:work@taiga_wrapper.cpu.bp.new_mem_request
|vpiNetType:36
|vpiNet:
\_logic_net: (next_pc), line:31, parent:bp
|vpiName:next_pc
|vpiFullName:work@taiga_wrapper.cpu.bp.next_pc
|vpiNetType:36
|vpiRange:
\_range: , line:31
|vpiLeftRange:
\_constant: , line:31
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:31
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (branch_flush_pc), line:34, parent:bp
|vpiName:branch_flush_pc
|vpiFullName:work@taiga_wrapper.cpu.bp.branch_flush_pc
|vpiNetType:36
|vpiRange:
\_range: , line:34
|vpiLeftRange:
\_constant: , line:34
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:34
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (predicted_pc), line:35, parent:bp
|vpiName:predicted_pc
|vpiFullName:work@taiga_wrapper.cpu.bp.predicted_pc
|vpiNetType:36
|vpiRange:
\_range: , line:35
|vpiLeftRange:
\_constant: , line:35
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:35
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (use_prediction), line:36, parent:bp
|vpiName:use_prediction
|vpiFullName:work@taiga_wrapper.cpu.bp.use_prediction
|vpiNetType:36
|vpiNet:
\_logic_net: (update_way), line:37, parent:bp
|vpiName:update_way
|vpiFullName:work@taiga_wrapper.cpu.bp.update_way
|vpiNetType:36
|vpiRange:
\_range: , line:37
|vpiLeftRange:
\_constant: , line:37
|vpiConstType:7
|vpiDecompile:8
|vpiSize:32
|INT:8
|vpiRightRange:
\_constant: , line:37
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (use_ras), line:38, parent:bp
|vpiName:use_ras
|vpiFullName:work@taiga_wrapper.cpu.bp.use_ras
|vpiNetType:36
|vpiInstance:
\_module: work@taiga (cpu), file:third_party/cores/taiga/examples/zedboard/taiga_wrapper.sv, line:233, parent:work@taiga_wrapper
|vpiVariables:
\_logic_var: (metadata), line:39, parent:bp
|vpiName:metadata
|vpiFullName:work@taiga_wrapper.cpu.bp.metadata
|vpiInterface:
\_interface: work@ras_interface (ras), file:third_party/cores/taiga/core/taiga.sv, line:54, parent:cpu
|vpiDefName:work@ras_interface
|vpiName:ras
|vpiFullName:work@taiga_wrapper.cpu.ras
|vpiModport:
\_modport: (branch_unit), parent:ras
|vpiName:branch_unit
|vpiIODecl:
\_io_decl: (push), parent:branch_unit
|vpiName:push
|vpiDirection:2
|vpiIODecl:
\_io_decl: (pop), parent:branch_unit
|vpiName:pop
|vpiDirection:2
|vpiIODecl:
\_io_decl: (new_addr), parent:branch_unit
|vpiName:new_addr
|vpiDirection:2
|vpiInterface:
\_interface: work@ras_interface (ras), file:third_party/cores/taiga/core/taiga.sv, line:54, parent:cpu
|vpiModport:
\_modport: (fetch), parent:ras
|vpiName:fetch
|vpiIODecl:
\_io_decl: (addr), parent:fetch
|vpiName:addr
|vpiDirection:1
|vpiIODecl:
\_io_decl: (valid), parent:fetch
|vpiName:valid
|vpiDirection:1
|vpiInterface:
\_interface: work@ras_interface (ras), file:third_party/cores/taiga/core/taiga.sv, line:54, parent:cpu
|vpiModport:
\_modport: (self), parent:ras
|vpiName:self
|vpiIODecl:
\_io_decl: (push), parent:self
|vpiName:push
|vpiDirection:1
|vpiIODecl:
\_io_decl: (pop), parent:self
|vpiName:pop
|vpiDirection:1
|vpiIODecl:
\_io_decl: (new_addr), parent:self
|vpiName:new_addr
|vpiDirection:1
|vpiIODecl:
\_io_decl: (addr), parent:self
|vpiName:addr
|vpiDirection:2
|vpiIODecl:
\_io_decl: (valid), parent:self
|vpiName:valid
|vpiDirection:2
|vpiInterface:
\_interface: work@ras_interface (ras), file:third_party/cores/taiga/core/taiga.sv, line:54, parent:cpu
|vpiNet:
\_logic_net: (push), line:65, parent:ras
|vpiName:push
|vpiFullName:work@taiga_wrapper.cpu.ras.push
|vpiNetType:36
|vpiNet:
\_logic_net: (pop), line:66, parent:ras
|vpiName:pop
|vpiFullName:work@taiga_wrapper.cpu.ras.pop
|vpiNetType:36
|vpiNet:
\_logic_net: (new_addr), line:67, parent:ras
|vpiName:new_addr
|vpiFullName:work@taiga_wrapper.cpu.ras.new_addr
|vpiNetType:36
|vpiRange:
\_range: , line:67
|vpiLeftRange:
\_constant: , line:67
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:67
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (addr), line:68, parent:ras
|vpiName:addr
|vpiFullName:work@taiga_wrapper.cpu.ras.addr
|vpiNetType:36
|vpiRange:
\_range: , line:68
|vpiLeftRange:
\_constant: , line:68
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:68
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (valid), line:69, parent:ras
|vpiName:valid
|vpiFullName:work@taiga_wrapper.cpu.ras.valid
|vpiNetType:36
|vpiInstance:
\_module: work@taiga (cpu), file:third_party/cores/taiga/examples/zedboard/taiga_wrapper.sv, line:233, parent:work@taiga_wrapper
|vpiInterface:
\_interface: work@register_file_decode_interface (rf_decode), file:third_party/cores/taiga/core/taiga.sv, line:56, parent:cpu
|vpiDefName:work@register_file_decode_interface
|vpiName:rf_decode
|vpiFullName:work@taiga_wrapper.cpu.rf_decode
|vpiModport:
\_modport: (decode), parent:rf_decode
|vpiName:decode
|vpiIODecl:
\_io_decl: (future_rd_addr), parent:decode
|vpiName:future_rd_addr
|vpiDirection:2
|vpiIODecl:
\_io_decl: (rs1_addr), parent:decode
|vpiName:rs1_addr
|vpiDirection:2
|vpiIODecl:
\_io_decl: (rs2_addr), parent:decode
|vpiName:rs2_addr
|vpiDirection:2
|vpiIODecl:
\_io_decl: (instruction_issued), parent:decode
|vpiName:instruction_issued
|vpiDirection:2
|vpiIODecl:
\_io_decl: (id), parent:decode
|vpiName:id
|vpiDirection:2
|vpiIODecl:
\_io_decl: (uses_rs1), parent:decode
|vpiName:uses_rs1
|vpiDirection:2
|vpiIODecl:
\_io_decl: (uses_rs2), parent:decode
|vpiName:uses_rs2
|vpiDirection:2
|vpiIODecl:
\_io_decl: (rs1_conflict), parent:decode
|vpiName:rs1_conflict
|vpiDirection:1
|vpiIODecl:
\_io_decl: (rs2_conflict), parent:decode
|vpiName:rs2_conflict
|vpiDirection:1
|vpiIODecl:
\_io_decl: (rs1_data), parent:decode
|vpiName:rs1_data
|vpiDirection:1
|vpiIODecl:
\_io_decl: (rs2_data), parent:decode
|vpiName:rs2_data
|vpiDirection:1
|vpiIODecl:
\_io_decl: (rs2_id), parent:decode
|vpiName:rs2_id
|vpiDirection:1
|vpiInterface:
\_interface: work@register_file_decode_interface (rf_decode), file:third_party/cores/taiga/core/taiga.sv, line:56, parent:cpu
|vpiModport:
\_modport: (unit), parent:rf_decode
|vpiName:unit
|vpiIODecl:
\_io_decl: (future_rd_addr), parent:unit
|vpiName:future_rd_addr
|vpiDirection:1
|vpiIODecl:
\_io_decl: (rs1_addr), parent:unit
|vpiName:rs1_addr
|vpiDirection:1
|vpiIODecl:
\_io_decl: (rs2_addr), parent:unit
|vpiName:rs2_addr
|vpiDirection:1
|vpiIODecl:
\_io_decl: (instruction_issued), parent:unit
|vpiName:instruction_issued
|vpiDirection:1
|vpiIODecl:
\_io_decl: (id), parent:unit
|vpiName:id
|vpiDirection:1
|vpiIODecl:
\_io_decl: (uses_rs1), parent:unit
|vpiName:uses_rs1
|vpiDirection:1
|vpiIODecl:
\_io_decl: (uses_rs2), parent:unit
|vpiName:uses_rs2
|vpiDirection:1
|vpiIODecl:
\_io_decl: (rs1_conflict), parent:unit
|vpiName:rs1_conflict
|vpiDirection:2
|vpiIODecl:
\_io_decl: (rs2_conflict), parent:unit
|vpiName:rs2_conflict
|vpiDirection:2
|vpiIODecl:
\_io_decl: (rs1_data), parent:unit
|vpiName:rs1_data
|vpiDirection:2
|vpiIODecl:
\_io_decl: (rs2_data), parent:unit
|vpiName:rs2_data
|vpiDirection:2
|vpiIODecl:
\_io_decl: (rs2_id), parent:unit
|vpiName:rs2_id
|vpiDirection:2
|vpiInterface:
\_interface: work@register_file_decode_interface (rf_decode), file:third_party/cores/taiga/core/taiga.sv, line:56, parent:cpu
|vpiNet:
\_logic_net: (future_rd_addr), line:104, parent:rf_decode
|vpiName:future_rd_addr
|vpiFullName:work@taiga_wrapper.cpu.rf_decode.future_rd_addr
|vpiNetType:36
|vpiRange:
\_range: , line:104
|vpiLeftRange:
\_constant: , line:104
|vpiConstType:7
|vpiDecompile:4
|vpiSize:32
|INT:4
|vpiRightRange:
\_constant: , line:104
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (rs1_addr), line:105, parent:rf_decode
|vpiName:rs1_addr
|vpiFullName:work@taiga_wrapper.cpu.rf_decode.rs1_addr
|vpiNetType:36
|vpiRange:
\_range: , line:105
|vpiLeftRange:
\_constant: , line:105
|vpiConstType:7
|vpiDecompile:4
|vpiSize:32
|INT:4
|vpiRightRange:
\_constant: , line:105
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (rs1_data), line:106, parent:rf_decode
|vpiName:rs1_data
|vpiFullName:work@taiga_wrapper.cpu.rf_decode.rs1_data
|vpiNetType:36
|vpiRange:
\_range: , line:106
|vpiLeftRange:
\_constant: , line:106
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiRightRange:
\_constant: , line:106
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (rs2_addr), line:107, parent:rf_decode
|vpiName:rs2_addr
|vpiFullName:work@taiga_wrapper.cpu.rf_decode.rs2_addr
|vpiNetType:36
|vpiRange:
\_range: , line:107
|vpiLeftRange:
\_constant: , line:107
|vpiConstType:7
|vpiDecompile:4
|vpiSize:32
|INT:4
|vpiRightRange:
\_constant: , line:107
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (rs2_data), line:108, parent:rf_decode
|vpiName:rs2_data
|vpiFullName:work@taiga_wrapper.cpu.rf_decode.rs2_data
|vpiNetType:36
|vpiRange:
\_range: , line:108
|vpiLeftRange:
\_constant: , line:108
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiRightRange:
\_constant: , line:108
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (uses_rs1), line:111, parent:rf_decode
|vpiName:uses_rs1
|vpiFullName:work@taiga_wrapper.cpu.rf_decode.uses_rs1
|vpiNetType:36
|vpiNet:
\_logic_net: (uses_rs2), line:112, parent:rf_decode
|vpiName:uses_rs2
|vpiFullName:work@taiga_wrapper.cpu.rf_decode.uses_rs2
|vpiNetType:36
|vpiNet:
\_logic_net: (rs1_conflict), line:113, parent:rf_decode
|vpiName:rs1_conflict
|vpiFullName:work@taiga_wrapper.cpu.rf_decode.rs1_conflict
|vpiNetType:36
|vpiNet:
\_logic_net: (rs2_conflict), line:114, parent:rf_decode
|vpiName:rs2_conflict
|vpiFullName:work@taiga_wrapper.cpu.rf_decode.rs2_conflict
|vpiNetType:36
|vpiNet:
\_logic_net: (instruction_issued), line:116, parent:rf_decode
|vpiName:instruction_issued
|vpiFullName:work@taiga_wrapper.cpu.rf_decode.instruction_issued
|vpiNetType:36
|vpiInstance:
\_module: work@taiga (cpu), file:third_party/cores/taiga/examples/zedboard/taiga_wrapper.sv, line:233, parent:work@taiga_wrapper
|vpiVariables:
\_logic_var: (id), line:109, parent:rf_decode
|vpiName:id
|vpiFullName:work@taiga_wrapper.cpu.rf_decode.id
|vpiVariables:
\_logic_var: (rs2_id), line:115, parent:rf_decode
|vpiName:rs2_id
|vpiFullName:work@taiga_wrapper.cpu.rf_decode.rs2_id
|vpiInterface:
\_interface: work@unit_issue_interface (unit_issue0), file:third_party/cores/taiga/core/taiga.sv, line:64, parent:cpu
|vpiDefName:work@unit_issue_interface
|vpiName:unit_issue0
|vpiFullName:work@taiga_wrapper.cpu.unit_issue0
|vpiModport:
\_modport: (decode), parent:unit_issue0
|vpiName:decode
|vpiIODecl:
\_io_decl: (ready), parent:decode
|vpiName:ready
|vpiDirection:1
|vpiIODecl:
\_io_decl: (possible_issue), parent:decode
|vpiName:possible_issue
|vpiDirection:2
|vpiIODecl:
\_io_decl: (new_request), parent:decode
|vpiName:new_request
|vpiDirection:2
|vpiIODecl:
\_io_decl: (new_request_r), parent:decode
|vpiName:new_request_r
|vpiDirection:2
|vpiIODecl:
\_io_decl: (instruction_id), parent:decode
|vpiName:instruction_id
|vpiDirection:2
|vpiInterface:
\_interface: work@unit_issue_interface (unit_issue0), file:third_party/cores/taiga/core/taiga.sv, line:64, parent:cpu
|vpiModport:
\_modport: (unit), parent:unit_issue0
|vpiName:unit
|vpiIODecl:
\_io_decl: (ready), parent:unit
|vpiName:ready
|vpiDirection:2
|vpiIODecl:
\_io_decl: (possible_issue), parent:unit
|vpiName:possible_issue
|vpiDirection:1
|vpiIODecl:
\_io_decl: (new_request), parent:unit
|vpiName:new_request
|vpiDirection:1
|vpiIODecl:
\_io_decl: (new_request_r), parent:unit
|vpiName:new_request_r
|vpiDirection:1
|vpiIODecl:
\_io_decl: (instruction_id), parent:unit
|vpiName:instruction_id
|vpiDirection:1
|vpiInterface:
\_interface: work@unit_issue_interface (unit_issue0), file:third_party/cores/taiga/core/taiga.sv, line:64, parent:cpu
|vpiNet:
\_logic_net: (possible_issue), line:53, parent:unit_issue0
|vpiName:possible_issue
|vpiFullName:work@taiga_wrapper.cpu.unit_issue0.possible_issue
|vpiNetType:36
|vpiNet:
\_logic_net: (new_request), line:54, parent:unit_issue0
|vpiName:new_request
|vpiFullName:work@taiga_wrapper.cpu.unit_issue0.new_request
|vpiNetType:36
|vpiNet:
\_logic_net: (new_request_r), line:55, parent:unit_issue0
|vpiName:new_request_r
|vpiFullName:work@taiga_wrapper.cpu.unit_issue0.new_request_r
|vpiNetType:36
|vpiNet:
\_logic_net: (ready), line:58, parent:unit_issue0
|vpiName:ready
|vpiFullName:work@taiga_wrapper.cpu.unit_issue0.ready
|vpiNetType:36
|vpiInstance:
\_module: work@taiga (cpu), file:third_party/cores/taiga/examples/zedboard/taiga_wrapper.sv, line:233, parent:work@taiga_wrapper
|vpiVariables:
\_logic_var: (instruction_id), line:56, parent:unit_issue0
|vpiName:instruction_id
|vpiFullName:work@taiga_wrapper.cpu.unit_issue0.instruction_id
|vpiInterface:
\_interface: work@unit_issue_interface (unit_issue1), file:third_party/cores/taiga/core/taiga.sv, line:64, parent:cpu
|vpiDefName:work@unit_issue_interface
|vpiName:unit_issue1
|vpiFullName:work@taiga_wrapper.cpu.unit_issue1
|vpiModport:
\_modport: (decode), parent:unit_issue1
|vpiName:decode
|vpiIODecl:
\_io_decl: (ready), parent:decode
|vpiName:ready
|vpiDirection:1
|vpiIODecl:
\_io_decl: (possible_issue), parent:decode
|vpiName:possible_issue
|vpiDirection:2
|vpiIODecl:
\_io_decl: (new_request), parent:decode
|vpiName:new_request
|vpiDirection:2
|vpiIODecl:
\_io_decl: (new_request_r), parent:decode
|vpiName:new_request_r
|vpiDirection:2
|vpiIODecl:
\_io_decl: (instruction_id), parent:decode
|vpiName:instruction_id
|vpiDirection:2
|vpiInterface:
\_interface: work@unit_issue_interface (unit_issue1), file:third_party/cores/taiga/core/taiga.sv, line:64, parent:cpu
|vpiModport:
\_modport: (unit), parent:unit_issue1
|vpiName:unit
|vpiIODecl:
\_io_decl: (ready), parent:unit
|vpiName:ready
|vpiDirection:2
|vpiIODecl:
\_io_decl: (possible_issue), parent:unit
|vpiName:possible_issue
|vpiDirection:1
|vpiIODecl:
\_io_decl: (new_request), parent:unit
|vpiName:new_request
|vpiDirection:1
|vpiIODecl:
\_io_decl: (new_request_r), parent:unit
|vpiName:new_request_r
|vpiDirection:1
|vpiIODecl:
\_io_decl: (instruction_id), parent:unit
|vpiName:instruction_id
|vpiDirection:1
|vpiInterface:
\_interface: work@unit_issue_interface (unit_issue1), file:third_party/cores/taiga/core/taiga.sv, line:64, parent:cpu
|vpiNet:
\_logic_net: (possible_issue), line:53, parent:unit_issue1
|vpiName:possible_issue
|vpiFullName:work@taiga_wrapper.cpu.unit_issue1.possible_issue
|vpiNetType:36
|vpiNet:
\_logic_net: (new_request), line:54, parent:unit_issue1
|vpiName:new_request
|vpiFullName:work@taiga_wrapper.cpu.unit_issue1.new_request
|vpiNetType:36
|vpiNet:
\_logic_net: (new_request_r), line:55, parent:unit_issue1
|vpiName:new_request_r
|vpiFullName:work@taiga_wrapper.cpu.unit_issue1.new_request_r
|vpiNetType:36
|vpiNet:
\_logic_net: (ready), line:58, parent:unit_issue1
|vpiName:ready
|vpiFullName:work@taiga_wrapper.cpu.unit_issue1.ready
|vpiNetType:36
|vpiInstance:
\_module: work@taiga (cpu), file:third_party/cores/taiga/examples/zedboard/taiga_wrapper.sv, line:233, parent:work@taiga_wrapper
|vpiVariables:
\_logic_var: (instruction_id), line:56, parent:unit_issue1
|vpiName:instruction_id
|vpiFullName:work@taiga_wrapper.cpu.unit_issue1.instruction_id
|vpiInterface:
\_interface: work@tracking_interface (ti), file:third_party/cores/taiga/core/taiga.sv, line:69, parent:cpu
|vpiDefName:work@tracking_interface
|vpiName:ti
|vpiFullName:work@taiga_wrapper.cpu.ti
|vpiModport:
\_modport: (decode), parent:ti
|vpiName:decode
|vpiIODecl:
\_io_decl: (issue_id), parent:decode
|vpiName:issue_id
|vpiDirection:1
|vpiIODecl:
\_io_decl: (id_available), parent:decode
|vpiName:id_available
|vpiDirection:1
|vpiIODecl:
\_io_decl: (inflight_packet), parent:decode
|vpiName:inflight_packet
|vpiDirection:2
|vpiIODecl:
\_io_decl: (issued), parent:decode
|vpiName:issued
|vpiDirection:2
|vpiIODecl:
\_io_decl: (issue_unit_id), parent:decode
|vpiName:issue_unit_id
|vpiDirection:2
|vpiInterface:
\_interface: work@tracking_interface (ti), file:third_party/cores/taiga/core/taiga.sv, line:69, parent:cpu
|vpiModport:
\_modport: (wb), parent:ti
|vpiName:wb
|vpiIODecl:
\_io_decl: (issue_id), parent:wb
|vpiName:issue_id
|vpiDirection:2
|vpiIODecl:
\_io_decl: (id_available), parent:wb
|vpiName:id_available
|vpiDirection:2
|vpiIODecl:
\_io_decl: (inflight_packet), parent:wb
|vpiName:inflight_packet
|vpiDirection:1
|vpiIODecl:
\_io_decl: (issued), parent:wb
|vpiName:issued
|vpiDirection:1
|vpiIODecl:
\_io_decl: (issue_unit_id), parent:wb
|vpiName:issue_unit_id
|vpiDirection:1
|vpiInterface:
\_interface: work@tracking_interface (ti), file:third_party/cores/taiga/core/taiga.sv, line:69, parent:cpu
|vpiNet:
\_logic_net: (id_available), line:147, parent:ti
|vpiName:id_available
|vpiFullName:work@taiga_wrapper.cpu.ti.id_available
|vpiNetType:36
|vpiNet:
\_logic_net: (issued), line:150, parent:ti
|vpiName:issued
|vpiFullName:work@taiga_wrapper.cpu.ti.issued
|vpiNetType:36
|vpiNet:
\_logic_net: (issue_unit_id), line:151, parent:ti
|vpiName:issue_unit_id
|vpiFullName:work@taiga_wrapper.cpu.ti.issue_unit_id
|vpiNetType:36
|vpiRange:
\_range: , line:151
|vpiLeftRange:
\_constant: , line:151
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:151
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiInstance:
\_module: work@taiga (cpu), file:third_party/cores/taiga/examples/zedboard/taiga_wrapper.sv, line:233, parent:work@taiga_wrapper
|vpiVariables:
\_logic_var: (issue_id), line:146, parent:ti
|vpiName:issue_id
|vpiFullName:work@taiga_wrapper.cpu.ti.issue_id
|vpiVariables:
\_struct_var: (inflight_packet), line:149, parent:ti
|vpiName:inflight_packet
|vpiFullName:work@taiga_wrapper.cpu.ti.inflight_packet
|vpiTypespec:
\_struct_typespec: (inflight_instruction_packet), line:271
|vpiInterface:
\_interface: work@register_file_writeback_interface (rf_wb), file:third_party/cores/taiga/core/taiga.sv, line:71, parent:cpu
|vpiDefName:work@register_file_writeback_interface
|vpiName:rf_wb
|vpiFullName:work@taiga_wrapper.cpu.rf_wb
|vpiModport:
\_modport: (unit), parent:rf_wb
|vpiName:unit
|vpiIODecl:
\_io_decl: (rd_addr), parent:unit
|vpiName:rd_addr
|vpiDirection:1
|vpiIODecl:
\_io_decl: (retiring), parent:unit
|vpiName:retiring
|vpiDirection:1
|vpiIODecl:
\_io_decl: (rd_nzero), parent:unit
|vpiName:rd_nzero
|vpiDirection:1
|vpiIODecl:
\_io_decl: (rd_data), parent:unit
|vpiName:rd_data
|vpiDirection:1
|vpiIODecl:
\_io_decl: (id), parent:unit
|vpiName:id
|vpiDirection:1
|vpiIODecl:
\_io_decl: (rs1_data), parent:unit
|vpiName:rs1_data
|vpiDirection:1
|vpiIODecl:
\_io_decl: (rs2_data), parent:unit
|vpiName:rs2_data
|vpiDirection:1
|vpiIODecl:
\_io_decl: (rs1_valid), parent:unit
|vpiName:rs1_valid
|vpiDirection:1
|vpiIODecl:
\_io_decl: (rs2_valid), parent:unit
|vpiName:rs2_valid
|vpiDirection:1
|vpiIODecl:
\_io_decl: (rs1_id), parent:unit
|vpiName:rs1_id
|vpiDirection:2
|vpiIODecl:
\_io_decl: (rs2_id), parent:unit
|vpiName:rs2_id
|vpiDirection:2
|vpiInterface:
\_interface: work@register_file_writeback_interface (rf_wb), file:third_party/cores/taiga/core/taiga.sv, line:71, parent:cpu
|vpiModport:
\_modport: (writeback), parent:rf_wb
|vpiName:writeback
|vpiIODecl:
\_io_decl: (rd_addr), parent:writeback
|vpiName:rd_addr
|vpiDirection:2
|vpiIODecl:
\_io_decl: (retiring), parent:writeback
|vpiName:retiring
|vpiDirection:2
|vpiIODecl:
\_io_decl: (rd_nzero), parent:writeback
|vpiName:rd_nzero
|vpiDirection:2
|vpiIODecl:
\_io_decl: (rd_data), parent:writeback
|vpiName:rd_data
|vpiDirection:2
|vpiIODecl:
\_io_decl: (id), parent:writeback
|vpiName:id
|vpiDirection:2
|vpiIODecl:
\_io_decl: (rs1_data), parent:writeback
|vpiName:rs1_data
|vpiDirection:2
|vpiIODecl:
\_io_decl: (rs2_data), parent:writeback
|vpiName:rs2_data
|vpiDirection:2
|vpiIODecl:
\_io_decl: (rs1_valid), parent:writeback
|vpiName:rs1_valid
|vpiDirection:2
|vpiIODecl:
\_io_decl: (rs2_valid), parent:writeback
|vpiName:rs2_valid
|vpiDirection:2
|vpiIODecl:
\_io_decl: (rs1_id), parent:writeback
|vpiName:rs1_id
|vpiDirection:1
|vpiIODecl:
\_io_decl: (rs2_id), parent:writeback
|vpiName:rs2_id
|vpiDirection:1
|vpiInterface:
\_interface: work@register_file_writeback_interface (rf_wb), file:third_party/cores/taiga/core/taiga.sv, line:71, parent:cpu
|vpiNet:
\_logic_net: (rd_addr), line:124, parent:rf_wb
|vpiName:rd_addr
|vpiFullName:work@taiga_wrapper.cpu.rf_wb.rd_addr
|vpiNetType:36
|vpiRange:
\_range: , line:124
|vpiLeftRange:
\_constant: , line:124
|vpiConstType:7
|vpiDecompile:4
|vpiSize:32
|INT:4
|vpiRightRange:
\_constant: , line:124
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (retiring), line:125, parent:rf_wb
|vpiName:retiring
|vpiFullName:work@taiga_wrapper.cpu.rf_wb.retiring
|vpiNetType:36
|vpiNet:
\_logic_net: (rd_nzero), line:126, parent:rf_wb
|vpiName:rd_nzero
|vpiFullName:work@taiga_wrapper.cpu.rf_wb.rd_nzero
|vpiNetType:36
|vpiNet:
\_logic_net: (rd_data), line:128, parent:rf_wb
|vpiName:rd_data
|vpiFullName:work@taiga_wrapper.cpu.rf_wb.rd_data
|vpiNetType:36
|vpiRange:
\_range: , line:128
|vpiLeftRange:
\_constant: , line:128
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiRightRange:
\_constant: , line:128
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (rs1_data), line:134, parent:rf_wb
|vpiName:rs1_data
|vpiFullName:work@taiga_wrapper.cpu.rf_wb.rs1_data
|vpiNetType:36
|vpiRange:
\_range: , line:134
|vpiLeftRange:
\_constant: , line:134
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiRightRange:
\_constant: , line:134
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (rs2_data), line:135, parent:rf_wb
|vpiName:rs2_data
|vpiFullName:work@taiga_wrapper.cpu.rf_wb.rs2_data
|vpiNetType:36
|vpiRange:
\_range: , line:135
|vpiLeftRange:
\_constant: , line:135
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiRightRange:
\_constant: , line:135
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (rs1_valid), line:136, parent:rf_wb
|vpiName:rs1_valid
|vpiFullName:work@taiga_wrapper.cpu.rf_wb.rs1_valid
|vpiNetType:36
|vpiNet:
\_logic_net: (rs2_valid), line:137, parent:rf_wb
|vpiName:rs2_valid
|vpiFullName:work@taiga_wrapper.cpu.rf_wb.rs2_valid
|vpiNetType:36
|vpiInstance:
\_module: work@taiga (cpu), file:third_party/cores/taiga/examples/zedboard/taiga_wrapper.sv, line:233, parent:work@taiga_wrapper
|vpiVariables:
\_logic_var: (id), line:129, parent:rf_wb
|vpiName:id
|vpiFullName:work@taiga_wrapper.cpu.rf_wb.id
|vpiVariables:
\_logic_var: (rs1_id), line:131, parent:rf_wb
|vpiName:rs1_id
|vpiFullName:work@taiga_wrapper.cpu.rf_wb.rs1_id
|vpiVariables:
\_logic_var: (rs2_id), line:132, parent:rf_wb
|vpiName:rs2_id
|vpiFullName:work@taiga_wrapper.cpu.rf_wb.rs2_id
|vpiInterface:
\_interface: work@mmu_interface (immu), file:third_party/cores/taiga/core/taiga.sv, line:73, parent:cpu
|vpiDefName:work@mmu_interface
|vpiName:immu
|vpiFullName:work@taiga_wrapper.cpu.immu
|vpiModport:
\_modport: (csr), parent:immu
|vpiName:csr
|vpiIODecl:
\_io_decl: (ppn), parent:csr
|vpiName:ppn
|vpiDirection:2
|vpiIODecl:
\_io_decl: (mxr), parent:csr
|vpiName:mxr
|vpiDirection:2
|vpiIODecl:
\_io_decl: (pum), parent:csr
|vpiName:pum
|vpiDirection:2
|vpiIODecl:
\_io_decl: (privilege), parent:csr
|vpiName:privilege
|vpiDirection:2
|vpiInterface:
\_interface: work@mmu_interface (immu), file:third_party/cores/taiga/core/taiga.sv, line:73, parent:cpu
|vpiModport:
\_modport: (mmu), parent:immu
|vpiName:mmu
|vpiIODecl:
\_io_decl: (virtual_address), parent:mmu
|vpiName:virtual_address
|vpiDirection:1
|vpiIODecl:
\_io_decl: (new_request), parent:mmu
|vpiName:new_request
|vpiDirection:1
|vpiIODecl:
\_io_decl: (execute), parent:mmu
|vpiName:execute
|vpiDirection:1
|vpiIODecl:
\_io_decl: (rnw), parent:mmu
|vpiName:rnw
|vpiDirection:1
|vpiIODecl:
\_io_decl: (ppn), parent:mmu
|vpiName:ppn
|vpiDirection:1
|vpiIODecl:
\_io_decl: (mxr), parent:mmu
|vpiName:mxr
|vpiDirection:1
|vpiIODecl:
\_io_decl: (pum), parent:mmu
|vpiName:pum
|vpiDirection:1
|vpiIODecl:
\_io_decl: (privilege), parent:mmu
|vpiName:privilege
|vpiDirection:1
|vpiIODecl:
\_io_decl: (write_entry), parent:mmu
|vpiName:write_entry
|vpiDirection:2
|vpiIODecl:
\_io_decl: (new_phys_addr), parent:mmu
|vpiName:new_phys_addr
|vpiDirection:2
|vpiInterface:
\_interface: work@mmu_interface (immu), file:third_party/cores/taiga/core/taiga.sv, line:73, parent:cpu
|vpiModport:
\_modport: (tlb), parent:immu
|vpiName:tlb
|vpiIODecl:
\_io_decl: (write_entry), parent:tlb
|vpiName:write_entry
|vpiDirection:1
|vpiIODecl:
\_io_decl: (new_phys_addr), parent:tlb
|vpiName:new_phys_addr
|vpiDirection:1
|vpiIODecl:
\_io_decl: (new_request), parent:tlb
|vpiName:new_request
|vpiDirection:2
|vpiIODecl:
\_io_decl: (virtual_address), parent:tlb
|vpiName:virtual_address
|vpiDirection:2
|vpiIODecl:
\_io_decl: (execute), parent:tlb
|vpiName:execute
|vpiDirection:2
|vpiIODecl:
\_io_decl: (rnw), parent:tlb
|vpiName:rnw
|vpiDirection:2
|vpiInterface:
\_interface: work@mmu_interface (immu), file:third_party/cores/taiga/core/taiga.sv, line:73, parent:cpu
|vpiNet:
\_logic_net: (new_request), line:172, parent:immu
|vpiName:new_request
|vpiFullName:work@taiga_wrapper.cpu.immu.new_request
|vpiNetType:36
|vpiNet:
\_logic_net: (execute), line:173, parent:immu
|vpiName:execute
|vpiFullName:work@taiga_wrapper.cpu.immu.execute
|vpiNetType:36
|vpiNet:
\_logic_net: (rnw), line:174, parent:immu
|vpiName:rnw
|vpiFullName:work@taiga_wrapper.cpu.immu.rnw
|vpiNetType:36
|vpiNet:
\_logic_net: (virtual_address), line:175, parent:immu
|vpiName:virtual_address
|vpiFullName:work@taiga_wrapper.cpu.immu.virtual_address
|vpiNetType:36
|vpiRange:
\_range: , line:175
|vpiLeftRange:
\_constant: , line:175
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:175
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (write_entry), line:178, parent:immu
|vpiName:write_entry
|vpiFullName:work@taiga_wrapper.cpu.immu.write_entry
|vpiNetType:36
|vpiNet:
\_logic_net: (new_phys_addr), line:179, parent:immu
|vpiName:new_phys_addr
|vpiFullName:work@taiga_wrapper.cpu.immu.new_phys_addr
|vpiNetType:36
|vpiRange:
\_range: , line:179
|vpiLeftRange:
\_constant: , line:179
|vpiConstType:7
|vpiDecompile:19
|vpiSize:32
|INT:19
|vpiRightRange:
\_constant: , line:179
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (ppn), line:182, parent:immu
|vpiName:ppn
|vpiFullName:work@taiga_wrapper.cpu.immu.ppn
|vpiNetType:36
|vpiRange:
\_range: , line:182
|vpiLeftRange:
\_constant: , line:182
|vpiConstType:7
|vpiDecompile:21
|vpiSize:32
|INT:21
|vpiRightRange:
\_constant: , line:182
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (mxr), line:183, parent:immu
|vpiName:mxr
|vpiFullName:work@taiga_wrapper.cpu.immu.mxr
|vpiNetType:36
|vpiNet:
\_logic_net: (pum), line:184, parent:immu
|vpiName:pum
|vpiFullName:work@taiga_wrapper.cpu.immu.pum
|vpiNetType:36
|vpiNet:
\_logic_net: (privilege), line:185, parent:immu
|vpiName:privilege
|vpiFullName:work@taiga_wrapper.cpu.immu.privilege
|vpiNetType:36
|vpiRange:
\_range: , line:185
|vpiLeftRange:
\_constant: , line:185
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:185
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiInstance:
\_module: work@taiga (cpu), file:third_party/cores/taiga/examples/zedboard/taiga_wrapper.sv, line:233, parent:work@taiga_wrapper
|vpiInterface:
\_interface: work@mmu_interface (dmmu), file:third_party/cores/taiga/core/taiga.sv, line:74, parent:cpu
|vpiDefName:work@mmu_interface
|vpiName:dmmu
|vpiFullName:work@taiga_wrapper.cpu.dmmu
|vpiModport:
\_modport: (csr), parent:dmmu
|vpiName:csr
|vpiIODecl:
\_io_decl: (ppn), parent:csr
|vpiName:ppn
|vpiDirection:2
|vpiIODecl:
\_io_decl: (mxr), parent:csr
|vpiName:mxr
|vpiDirection:2
|vpiIODecl:
\_io_decl: (pum), parent:csr
|vpiName:pum
|vpiDirection:2
|vpiIODecl:
\_io_decl: (privilege), parent:csr
|vpiName:privilege
|vpiDirection:2
|vpiInterface:
\_interface: work@mmu_interface (dmmu), file:third_party/cores/taiga/core/taiga.sv, line:74, parent:cpu
|vpiModport:
\_modport: (mmu), parent:dmmu
|vpiName:mmu
|vpiIODecl:
\_io_decl: (virtual_address), parent:mmu
|vpiName:virtual_address
|vpiDirection:1
|vpiIODecl:
\_io_decl: (new_request), parent:mmu
|vpiName:new_request
|vpiDirection:1
|vpiIODecl:
\_io_decl: (execute), parent:mmu
|vpiName:execute
|vpiDirection:1
|vpiIODecl:
\_io_decl: (rnw), parent:mmu
|vpiName:rnw
|vpiDirection:1
|vpiIODecl:
\_io_decl: (ppn), parent:mmu
|vpiName:ppn
|vpiDirection:1
|vpiIODecl:
\_io_decl: (mxr), parent:mmu
|vpiName:mxr
|vpiDirection:1
|vpiIODecl:
\_io_decl: (pum), parent:mmu
|vpiName:pum
|vpiDirection:1
|vpiIODecl:
\_io_decl: (privilege), parent:mmu
|vpiName:privilege
|vpiDirection:1
|vpiIODecl:
\_io_decl: (write_entry), parent:mmu
|vpiName:write_entry
|vpiDirection:2
|vpiIODecl:
\_io_decl: (new_phys_addr), parent:mmu
|vpiName:new_phys_addr
|vpiDirection:2
|vpiInterface:
\_interface: work@mmu_interface (dmmu), file:third_party/cores/taiga/core/taiga.sv, line:74, parent:cpu
|vpiModport:
\_modport: (tlb), parent:dmmu
|vpiName:tlb
|vpiIODecl:
\_io_decl: (write_entry), parent:tlb
|vpiName:write_entry
|vpiDirection:1
|vpiIODecl:
\_io_decl: (new_phys_addr), parent:tlb
|vpiName:new_phys_addr
|vpiDirection:1
|vpiIODecl:
\_io_decl: (new_request), parent:tlb
|vpiName:new_request
|vpiDirection:2
|vpiIODecl:
\_io_decl: (virtual_address), parent:tlb
|vpiName:virtual_address
|vpiDirection:2
|vpiIODecl:
\_io_decl: (execute), parent:tlb
|vpiName:execute
|vpiDirection:2
|vpiIODecl:
\_io_decl: (rnw), parent:tlb
|vpiName:rnw
|vpiDirection:2
|vpiInterface:
\_interface: work@mmu_interface (dmmu), file:third_party/cores/taiga/core/taiga.sv, line:74, parent:cpu
|vpiNet:
\_logic_net: (new_request), line:172, parent:dmmu
|vpiName:new_request
|vpiFullName:work@taiga_wrapper.cpu.dmmu.new_request
|vpiNetType:36
|vpiNet:
\_logic_net: (execute), line:173, parent:dmmu
|vpiName:execute
|vpiFullName:work@taiga_wrapper.cpu.dmmu.execute
|vpiNetType:36
|vpiNet:
\_logic_net: (rnw), line:174, parent:dmmu
|vpiName:rnw
|vpiFullName:work@taiga_wrapper.cpu.dmmu.rnw
|vpiNetType:36
|vpiNet:
\_logic_net: (virtual_address), line:175, parent:dmmu
|vpiName:virtual_address
|vpiFullName:work@taiga_wrapper.cpu.dmmu.virtual_address
|vpiNetType:36
|vpiRange:
\_range: , line:175
|vpiLeftRange:
\_constant: , line:175
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:175
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (write_entry), line:178, parent:dmmu
|vpiName:write_entry
|vpiFullName:work@taiga_wrapper.cpu.dmmu.write_entry
|vpiNetType:36
|vpiNet:
\_logic_net: (new_phys_addr), line:179, parent:dmmu
|vpiName:new_phys_addr
|vpiFullName:work@taiga_wrapper.cpu.dmmu.new_phys_addr
|vpiNetType:36
|vpiRange:
\_range: , line:179
|vpiLeftRange:
\_constant: , line:179
|vpiConstType:7
|vpiDecompile:19
|vpiSize:32
|INT:19
|vpiRightRange:
\_constant: , line:179
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (ppn), line:182, parent:dmmu
|vpiName:ppn
|vpiFullName:work@taiga_wrapper.cpu.dmmu.ppn
|vpiNetType:36
|vpiRange:
\_range: , line:182
|vpiLeftRange:
\_constant: , line:182
|vpiConstType:7
|vpiDecompile:21
|vpiSize:32
|INT:21
|vpiRightRange:
\_constant: , line:182
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (mxr), line:183, parent:dmmu
|vpiName:mxr
|vpiFullName:work@taiga_wrapper.cpu.dmmu.mxr
|vpiNetType:36
|vpiNet:
\_logic_net: (pum), line:184, parent:dmmu
|vpiName:pum
|vpiFullName:work@taiga_wrapper.cpu.dmmu.pum
|vpiNetType:36
|vpiNet:
\_logic_net: (privilege), line:185, parent:dmmu
|vpiName:privilege
|vpiFullName:work@taiga_wrapper.cpu.dmmu.privilege
|vpiNetType:36
|vpiRange:
\_range: , line:185
|vpiLeftRange:
\_constant: , line:185
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:185
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiInstance:
\_module: work@taiga (cpu), file:third_party/cores/taiga/examples/zedboard/taiga_wrapper.sv, line:233, parent:work@taiga_wrapper
|vpiInterface:
\_interface: work@tlb_interface (itlb), file:third_party/cores/taiga/core/taiga.sv, line:76, parent:cpu
|vpiDefName:work@tlb_interface
|vpiName:itlb
|vpiFullName:work@taiga_wrapper.cpu.itlb
|vpiModport:
\_modport: (fence), parent:itlb
|vpiName:fence
|vpiIODecl:
\_io_decl: (flush), parent:fence
|vpiName:flush
|vpiDirection:2
|vpiIODecl:
\_io_decl: (flush_complete), parent:fence
|vpiName:flush_complete
|vpiDirection:1
|vpiInterface:
\_interface: work@tlb_interface (itlb), file:third_party/cores/taiga/core/taiga.sv, line:76, parent:cpu
|vpiModport:
\_modport: (mem), parent:itlb
|vpiName:mem
|vpiIODecl:
\_io_decl: (new_request), parent:mem
|vpiName:new_request
|vpiDirection:2
|vpiIODecl:
\_io_decl: (virtual_address), parent:mem
|vpiName:virtual_address
|vpiDirection:2
|vpiIODecl:
\_io_decl: (rnw), parent:mem
|vpiName:rnw
|vpiDirection:2
|vpiIODecl:
\_io_decl: (execute), parent:mem
|vpiName:execute
|vpiDirection:2
|vpiIODecl:
\_io_decl: (complete), parent:mem
|vpiName:complete
|vpiDirection:1
|vpiIODecl:
\_io_decl: (physical_address), parent:mem
|vpiName:physical_address
|vpiDirection:1
|vpiInterface:
\_interface: work@tlb_interface (itlb), file:third_party/cores/taiga/core/taiga.sv, line:76, parent:cpu
|vpiModport:
\_modport: (tlb), parent:itlb
|vpiName:tlb
|vpiIODecl:
\_io_decl: (virtual_address), parent:tlb
|vpiName:virtual_address
|vpiDirection:1
|vpiIODecl:
\_io_decl: (new_request), parent:tlb
|vpiName:new_request
|vpiDirection:1
|vpiIODecl:
\_io_decl: (flush), parent:tlb
|vpiName:flush
|vpiDirection:1
|vpiIODecl:
\_io_decl: (rnw), parent:tlb
|vpiName:rnw
|vpiDirection:1
|vpiIODecl:
\_io_decl: (execute), parent:tlb
|vpiName:execute
|vpiDirection:1
|vpiIODecl:
\_io_decl: (complete), parent:tlb
|vpiName:complete
|vpiDirection:2
|vpiIODecl:
\_io_decl: (physical_address), parent:tlb
|vpiName:physical_address
|vpiDirection:2
|vpiIODecl:
\_io_decl: (flush_complete), parent:tlb
|vpiName:flush_complete
|vpiDirection:2
|vpiInterface:
\_interface: work@tlb_interface (itlb), file:third_party/cores/taiga/core/taiga.sv, line:76, parent:cpu
|vpiNet:
\_logic_net: (virtual_address), line:194, parent:itlb
|vpiName:virtual_address
|vpiFullName:work@taiga_wrapper.cpu.itlb.virtual_address
|vpiNetType:36
|vpiRange:
\_range: , line:194
|vpiLeftRange:
\_constant: , line:194
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:194
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (new_request), line:195, parent:itlb
|vpiName:new_request
|vpiFullName:work@taiga_wrapper.cpu.itlb.new_request
|vpiNetType:36
|vpiNet:
\_logic_net: (rnw), line:196, parent:itlb
|vpiName:rnw
|vpiFullName:work@taiga_wrapper.cpu.itlb.rnw
|vpiNetType:36
|vpiNet:
\_logic_net: (execute), line:197, parent:itlb
|vpiName:execute
|vpiFullName:work@taiga_wrapper.cpu.itlb.execute
|vpiNetType:36
|vpiNet:
\_logic_net: (complete), line:199, parent:itlb
|vpiName:complete
|vpiFullName:work@taiga_wrapper.cpu.itlb.complete
|vpiNetType:36
|vpiNet:
\_logic_net: (physical_address), line:200, parent:itlb
|vpiName:physical_address
|vpiFullName:work@taiga_wrapper.cpu.itlb.physical_address
|vpiNetType:36
|vpiRange:
\_range: , line:200
|vpiLeftRange:
\_constant: , line:200
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:200
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (flush), line:202, parent:itlb
|vpiName:flush
|vpiFullName:work@taiga_wrapper.cpu.itlb.flush
|vpiNetType:36
|vpiNet:
\_logic_net: (flush_complete), line:203, parent:itlb
|vpiName:flush_complete
|vpiFullName:work@taiga_wrapper.cpu.itlb.flush_complete
|vpiNetType:36
|vpiInstance:
\_module: work@taiga (cpu), file:third_party/cores/taiga/examples/zedboard/taiga_wrapper.sv, line:233, parent:work@taiga_wrapper
|vpiInterface:
\_interface: work@tlb_interface (dtlb), file:third_party/cores/taiga/core/taiga.sv, line:77, parent:cpu
|vpiDefName:work@tlb_interface
|vpiName:dtlb
|vpiFullName:work@taiga_wrapper.cpu.dtlb
|vpiModport:
\_modport: (fence), parent:dtlb
|vpiName:fence
|vpiIODecl:
\_io_decl: (flush), parent:fence
|vpiName:flush
|vpiDirection:2
|vpiIODecl:
\_io_decl: (flush_complete), parent:fence
|vpiName:flush_complete
|vpiDirection:1
|vpiInterface:
\_interface: work@tlb_interface (dtlb), file:third_party/cores/taiga/core/taiga.sv, line:77, parent:cpu
|vpiModport:
\_modport: (mem), parent:dtlb
|vpiName:mem
|vpiIODecl:
\_io_decl: (new_request), parent:mem
|vpiName:new_request
|vpiDirection:2
|vpiIODecl:
\_io_decl: (virtual_address), parent:mem
|vpiName:virtual_address
|vpiDirection:2
|vpiIODecl:
\_io_decl: (rnw), parent:mem
|vpiName:rnw
|vpiDirection:2
|vpiIODecl:
\_io_decl: (execute), parent:mem
|vpiName:execute
|vpiDirection:2
|vpiIODecl:
\_io_decl: (complete), parent:mem
|vpiName:complete
|vpiDirection:1
|vpiIODecl:
\_io_decl: (physical_address), parent:mem
|vpiName:physical_address
|vpiDirection:1
|vpiInterface:
\_interface: work@tlb_interface (dtlb), file:third_party/cores/taiga/core/taiga.sv, line:77, parent:cpu
|vpiModport:
\_modport: (tlb), parent:dtlb
|vpiName:tlb
|vpiIODecl:
\_io_decl: (virtual_address), parent:tlb
|vpiName:virtual_address
|vpiDirection:1
|vpiIODecl:
\_io_decl: (new_request), parent:tlb
|vpiName:new_request
|vpiDirection:1
|vpiIODecl:
\_io_decl: (flush), parent:tlb
|vpiName:flush
|vpiDirection:1
|vpiIODecl:
\_io_decl: (rnw), parent:tlb
|vpiName:rnw
|vpiDirection:1
|vpiIODecl:
\_io_decl: (execute), parent:tlb
|vpiName:execute
|vpiDirection:1
|vpiIODecl:
\_io_decl: (complete), parent:tlb
|vpiName:complete
|vpiDirection:2
|vpiIODecl:
\_io_decl: (physical_address), parent:tlb
|vpiName:physical_address
|vpiDirection:2
|vpiIODecl:
\_io_decl: (flush_complete), parent:tlb
|vpiName:flush_complete
|vpiDirection:2
|vpiInterface:
\_interface: work@tlb_interface (dtlb), file:third_party/cores/taiga/core/taiga.sv, line:77, parent:cpu
|vpiNet:
\_logic_net: (virtual_address), line:194, parent:dtlb
|vpiName:virtual_address
|vpiFullName:work@taiga_wrapper.cpu.dtlb.virtual_address
|vpiNetType:36
|vpiRange:
\_range: , line:194
|vpiLeftRange:
\_constant: , line:194
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:194
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (new_request), line:195, parent:dtlb
|vpiName:new_request
|vpiFullName:work@taiga_wrapper.cpu.dtlb.new_request
|vpiNetType:36
|vpiNet:
\_logic_net: (rnw), line:196, parent:dtlb
|vpiName:rnw
|vpiFullName:work@taiga_wrapper.cpu.dtlb.rnw
|vpiNetType:36
|vpiNet:
\_logic_net: (execute), line:197, parent:dtlb
|vpiName:execute
|vpiFullName:work@taiga_wrapper.cpu.dtlb.execute
|vpiNetType:36
|vpiNet:
\_logic_net: (complete), line:199, parent:dtlb
|vpiName:complete
|vpiFullName:work@taiga_wrapper.cpu.dtlb.complete
|vpiNetType:36
|vpiNet:
\_logic_net: (physical_address), line:200, parent:dtlb
|vpiName:physical_address
|vpiFullName:work@taiga_wrapper.cpu.dtlb.physical_address
|vpiNetType:36
|vpiRange:
\_range: , line:200
|vpiLeftRange:
\_constant: , line:200
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:200
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (flush), line:202, parent:dtlb
|vpiName:flush
|vpiFullName:work@taiga_wrapper.cpu.dtlb.flush
|vpiNetType:36
|vpiNet:
\_logic_net: (flush_complete), line:203, parent:dtlb
|vpiName:flush_complete
|vpiFullName:work@taiga_wrapper.cpu.dtlb.flush_complete
|vpiNetType:36
|vpiInstance:
\_module: work@taiga (cpu), file:third_party/cores/taiga/examples/zedboard/taiga_wrapper.sv, line:233, parent:work@taiga_wrapper
|vpiInterface:
\_interface: work@post_issue_forwarding_interface (store_forwarding), file:third_party/cores/taiga/core/taiga.sv, line:120, parent:cpu
|vpiDefName:work@post_issue_forwarding_interface
|vpiName:store_forwarding
|vpiFullName:work@taiga_wrapper.cpu.store_forwarding
|vpiModport:
\_modport: (unit), parent:store_forwarding
|vpiName:unit
|vpiIODecl:
\_io_decl: (data), parent:unit
|vpiName:data
|vpiDirection:1
|vpiIODecl:
\_io_decl: (data_valid), parent:unit
|vpiName:data_valid
|vpiDirection:1
|vpiIODecl:
\_io_decl: (id), parent:unit
|vpiName:id
|vpiDirection:2
|vpiInterface:
\_interface: work@post_issue_forwarding_interface (store_forwarding), file:third_party/cores/taiga/core/taiga.sv, line:120, parent:cpu
|vpiModport:
\_modport: (wb), parent:store_forwarding
|vpiName:wb
|vpiIODecl:
\_io_decl: (data), parent:wb
|vpiName:data
|vpiDirection:2
|vpiIODecl:
\_io_decl: (data_valid), parent:wb
|vpiName:data_valid
|vpiDirection:2
|vpiIODecl:
\_io_decl: (id), parent:wb
|vpiName:id
|vpiDirection:1
|vpiInterface:
\_interface: work@post_issue_forwarding_interface (store_forwarding), file:third_party/cores/taiga/core/taiga.sv, line:120, parent:cpu
|vpiNet:
\_logic_net: (data), line:260, parent:store_forwarding
|vpiName:data
|vpiFullName:work@taiga_wrapper.cpu.store_forwarding.data
|vpiNetType:36
|vpiRange:
\_range: , line:260
|vpiLeftRange:
\_constant: , line:260
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:260
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (data_valid), line:261, parent:store_forwarding
|vpiName:data_valid
|vpiFullName:work@taiga_wrapper.cpu.store_forwarding.data_valid
|vpiNetType:36
|vpiInstance:
\_module: work@taiga (cpu), file:third_party/cores/taiga/examples/zedboard/taiga_wrapper.sv, line:233, parent:work@taiga_wrapper
|vpiVariables:
\_logic_var: (id), line:258, parent:store_forwarding
|vpiName:id
|vpiFullName:work@taiga_wrapper.cpu.store_forwarding.id
|vpiModule:
\_module: work@fetch (fetch_block), file:third_party/cores/taiga/core/taiga.sv, line:160, parent:cpu
|vpiDefName:work@fetch
|vpiName:fetch_block
|vpiFullName:work@taiga_wrapper.cpu.fetch_block
|vpiPort:
\_port: (clk), line:27, parent:fetch_block
|vpiName:clk
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (clk), line:160
|vpiName:clk
|vpiActual:
\_logic_net: (clk), line:27, parent:cpu
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (clk), line:27, parent:fetch_block
|vpiName:clk
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.clk
|vpiNetType:36
|vpiPort:
\_port: (rst), line:28, parent:fetch_block
|vpiName:rst
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (rst), line:160
|vpiName:rst
|vpiActual:
\_logic_net: (rst), line:28, parent:cpu
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (rst), line:28, parent:fetch_block
|vpiName:rst
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.rst
|vpiNetType:36
|vpiPort:
\_port: (branch_flush), line:30, parent:fetch_block
|vpiName:branch_flush
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (branch_flush), line:160
|vpiName:branch_flush
|vpiActual:
\_logic_net: (branch_flush), line:52, parent:cpu
|vpiName:branch_flush
|vpiFullName:work@taiga_wrapper.cpu.branch_flush
|vpiNetType:36
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (branch_flush), line:30, parent:fetch_block
|vpiName:branch_flush
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.branch_flush
|vpiNetType:36
|vpiPort:
\_port: (gc_fetch_flush), line:31, parent:fetch_block
|vpiName:gc_fetch_flush
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (gc_fetch_flush), line:160
|vpiName:gc_fetch_flush
|vpiActual:
\_logic_net: (gc_fetch_flush), line:95, parent:cpu
|vpiName:gc_fetch_flush
|vpiFullName:work@taiga_wrapper.cpu.gc_fetch_flush
|vpiNetType:36
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (gc_fetch_flush), line:31, parent:fetch_block
|vpiName:gc_fetch_flush
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.gc_fetch_flush
|vpiNetType:36
|vpiPort:
\_port: (gc_fetch_pc_override), line:32, parent:fetch_block
|vpiName:gc_fetch_pc_override
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (gc_fetch_pc_override), line:160
|vpiName:gc_fetch_pc_override
|vpiActual:
\_logic_net: (gc_fetch_pc_override), line:96, parent:cpu
|vpiName:gc_fetch_pc_override
|vpiFullName:work@taiga_wrapper.cpu.gc_fetch_pc_override
|vpiNetType:36
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (gc_fetch_pc_override), line:32, parent:fetch_block
|vpiName:gc_fetch_pc_override
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.gc_fetch_pc_override
|vpiNetType:36
|vpiPort:
\_port: (exception), line:33, parent:fetch_block
|vpiName:exception
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (exception), line:160
|vpiName:exception
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (exception), line:33, parent:fetch_block
|vpiName:exception
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.exception
|vpiNetType:36
|vpiPort:
\_port: (gc_fetch_pc), line:34, parent:fetch_block
|vpiName:gc_fetch_pc
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (gc_fetch_pc), line:160
|vpiName:gc_fetch_pc
|vpiActual:
\_logic_net: (gc_fetch_pc), line:100, parent:cpu
|vpiName:gc_fetch_pc
|vpiFullName:work@taiga_wrapper.cpu.gc_fetch_pc
|vpiNetType:36
|vpiRange:
\_range: , line:100
|vpiLeftRange:
\_constant: , line:100
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:100
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (gc_fetch_pc), line:34, parent:fetch_block
|vpiName:gc_fetch_pc
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.gc_fetch_pc
|vpiNetType:36
|vpiRange:
\_range: , line:34
|vpiLeftRange:
\_constant: , line:34
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:34
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiPort:
\_port: (bp), line:36, parent:fetch_block
|vpiName:bp
|vpiDirection:5
|vpiHighConn:
\_ref_obj: (bp), line:160
|vpiName:bp
|vpiActual:
\_interface: work@branch_predictor_interface (bp), file:third_party/cores/taiga/core/taiga.sv, line:50
|vpiDefName:work@branch_predictor_interface
|vpiName:bp
|vpiModport:
\_modport: (branch_predictor)
|vpiName:branch_predictor
|vpiIODecl:
\_io_decl: (if_pc)
|vpiName:if_pc
|vpiDirection:1
|vpiIODecl:
\_io_decl: (new_mem_request)
|vpiName:new_mem_request
|vpiDirection:1
|vpiIODecl:
\_io_decl: (next_pc)
|vpiName:next_pc
|vpiDirection:1
|vpiIODecl:
\_io_decl: (branch_flush_pc)
|vpiName:branch_flush_pc
|vpiDirection:2
|vpiIODecl:
\_io_decl: (predicted_pc)
|vpiName:predicted_pc
|vpiDirection:2
|vpiIODecl:
\_io_decl: (use_prediction)
|vpiName:use_prediction
|vpiDirection:2
|vpiIODecl:
\_io_decl: (update_way)
|vpiName:update_way
|vpiDirection:2
|vpiIODecl:
\_io_decl: (use_ras)
|vpiName:use_ras
|vpiDirection:2
|vpiIODecl:
\_io_decl: (metadata)
|vpiName:metadata
|vpiDirection:2
|vpiInterface:
\_interface: work@branch_predictor_interface (bp), file:third_party/cores/taiga/core/taiga.sv, line:50
|vpiModport:
\_modport: (fetch)
|vpiName:fetch
|vpiIODecl:
\_io_decl: (branch_flush_pc)
|vpiName:branch_flush_pc
|vpiDirection:1
|vpiIODecl:
\_io_decl: (predicted_pc)
|vpiName:predicted_pc
|vpiDirection:1
|vpiIODecl:
\_io_decl: (use_prediction)
|vpiName:use_prediction
|vpiDirection:1
|vpiIODecl:
\_io_decl: (update_way)
|vpiName:update_way
|vpiDirection:1
|vpiIODecl:
\_io_decl: (use_ras)
|vpiName:use_ras
|vpiDirection:1
|vpiIODecl:
\_io_decl: (metadata)
|vpiName:metadata
|vpiDirection:1
|vpiIODecl:
\_io_decl: (if_pc)
|vpiName:if_pc
|vpiDirection:2
|vpiIODecl:
\_io_decl: (new_mem_request)
|vpiName:new_mem_request
|vpiDirection:2
|vpiIODecl:
\_io_decl: (next_pc)
|vpiName:next_pc
|vpiDirection:2
|vpiInterface:
\_interface: work@branch_predictor_interface (bp), file:third_party/cores/taiga/core/taiga.sv, line:50
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_modport: (fetch)
|vpiName:fetch
|vpiIODecl:
\_io_decl: (branch_flush_pc)
|vpiName:branch_flush_pc
|vpiDirection:1
|vpiExpr:
\_logic_net: (branch_flush_pc), line:34
|vpiName:branch_flush_pc
|vpiNetType:36
|vpiRange:
\_range: , line:34
|vpiLeftRange:
\_constant: , line:34
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:34
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (predicted_pc)
|vpiName:predicted_pc
|vpiDirection:1
|vpiExpr:
\_logic_net: (predicted_pc), line:35
|vpiName:predicted_pc
|vpiNetType:36
|vpiRange:
\_range: , line:35
|vpiLeftRange:
\_constant: , line:35
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:35
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (use_prediction)
|vpiName:use_prediction
|vpiDirection:1
|vpiExpr:
\_logic_net: (use_prediction), line:36
|vpiName:use_prediction
|vpiNetType:36
|vpiIODecl:
\_io_decl: (update_way)
|vpiName:update_way
|vpiDirection:1
|vpiExpr:
\_logic_net: (update_way), line:37
|vpiName:update_way
|vpiNetType:36
|vpiRange:
\_range: , line:37
|vpiLeftRange:
\_constant: , line:37
|vpiConstType:7
|vpiDecompile:8
|vpiSize:32
|INT:8
|vpiRightRange:
\_constant: , line:37
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (use_ras)
|vpiName:use_ras
|vpiDirection:1
|vpiExpr:
\_logic_net: (use_ras), line:38
|vpiName:use_ras
|vpiNetType:36
|vpiIODecl:
\_io_decl: (metadata)
|vpiName:metadata
|vpiDirection:1
|vpiIODecl:
\_io_decl: (if_pc)
|vpiName:if_pc
|vpiDirection:2
|vpiExpr:
\_logic_net: (if_pc), line:29
|vpiName:if_pc
|vpiNetType:36
|vpiRange:
\_range: , line:29
|vpiLeftRange:
\_constant: , line:29
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:29
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (new_mem_request)
|vpiName:new_mem_request
|vpiDirection:2
|vpiExpr:
\_logic_net: (new_mem_request), line:30
|vpiName:new_mem_request
|vpiNetType:36
|vpiIODecl:
\_io_decl: (next_pc)
|vpiName:next_pc
|vpiDirection:2
|vpiExpr:
\_logic_net: (next_pc), line:31
|vpiName:next_pc
|vpiNetType:36
|vpiRange:
\_range: , line:31
|vpiLeftRange:
\_constant: , line:31
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:31
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiInterface:
\_interface: work@branch_predictor_interface (bp), file:third_party/cores/taiga/core/taiga.sv, line:160
|vpiDefName:work@branch_predictor_interface
|vpiName:bp
|vpiModport:
\_modport: (branch_predictor)
|vpiName:branch_predictor
|vpiIODecl:
\_io_decl: (if_pc)
|vpiName:if_pc
|vpiDirection:1
|vpiExpr:
\_logic_net: (if_pc), line:29
|vpiIODecl:
\_io_decl: (new_mem_request)
|vpiName:new_mem_request
|vpiDirection:1
|vpiExpr:
\_logic_net: (new_mem_request), line:30
|vpiIODecl:
\_io_decl: (next_pc)
|vpiName:next_pc
|vpiDirection:1
|vpiExpr:
\_logic_net: (next_pc), line:31
|vpiIODecl:
\_io_decl: (branch_flush_pc)
|vpiName:branch_flush_pc
|vpiDirection:2
|vpiExpr:
\_logic_net: (branch_flush_pc), line:34
|vpiIODecl:
\_io_decl: (predicted_pc)
|vpiName:predicted_pc
|vpiDirection:2
|vpiExpr:
\_logic_net: (predicted_pc), line:35
|vpiIODecl:
\_io_decl: (use_prediction)
|vpiName:use_prediction
|vpiDirection:2
|vpiExpr:
\_logic_net: (use_prediction), line:36
|vpiIODecl:
\_io_decl: (update_way)
|vpiName:update_way
|vpiDirection:2
|vpiExpr:
\_logic_net: (update_way), line:37
|vpiIODecl:
\_io_decl: (use_ras)
|vpiName:use_ras
|vpiDirection:2
|vpiExpr:
\_logic_net: (use_ras), line:38
|vpiIODecl:
\_io_decl: (metadata)
|vpiName:metadata
|vpiDirection:2
|vpiInterface:
\_interface: work@branch_predictor_interface (bp), file:third_party/cores/taiga/core/taiga.sv, line:160
|vpiModport:
\_modport: (fetch)
|vpiPort:
\_port: (ras), line:37, parent:fetch_block
|vpiName:ras
|vpiDirection:5
|vpiHighConn:
\_ref_obj: (ras), line:160
|vpiName:ras
|vpiActual:
\_interface: work@ras_interface (ras), file:third_party/cores/taiga/core/taiga.sv, line:54
|vpiDefName:work@ras_interface
|vpiName:ras
|vpiModport:
\_modport: (branch_unit)
|vpiName:branch_unit
|vpiIODecl:
\_io_decl: (push)
|vpiName:push
|vpiDirection:2
|vpiIODecl:
\_io_decl: (pop)
|vpiName:pop
|vpiDirection:2
|vpiIODecl:
\_io_decl: (new_addr)
|vpiName:new_addr
|vpiDirection:2
|vpiInterface:
\_interface: work@ras_interface (ras), file:third_party/cores/taiga/core/taiga.sv, line:54
|vpiModport:
\_modport: (fetch)
|vpiName:fetch
|vpiIODecl:
\_io_decl: (addr)
|vpiName:addr
|vpiDirection:1
|vpiIODecl:
\_io_decl: (valid)
|vpiName:valid
|vpiDirection:1
|vpiInterface:
\_interface: work@ras_interface (ras), file:third_party/cores/taiga/core/taiga.sv, line:54
|vpiModport:
\_modport: (self)
|vpiName:self
|vpiIODecl:
\_io_decl: (push)
|vpiName:push
|vpiDirection:1
|vpiIODecl:
\_io_decl: (pop)
|vpiName:pop
|vpiDirection:1
|vpiIODecl:
\_io_decl: (new_addr)
|vpiName:new_addr
|vpiDirection:1
|vpiIODecl:
\_io_decl: (addr)
|vpiName:addr
|vpiDirection:2
|vpiIODecl:
\_io_decl: (valid)
|vpiName:valid
|vpiDirection:2
|vpiInterface:
\_interface: work@ras_interface (ras), file:third_party/cores/taiga/core/taiga.sv, line:54
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_modport: (fetch)
|vpiName:fetch
|vpiIODecl:
\_io_decl: (addr)
|vpiName:addr
|vpiDirection:1
|vpiExpr:
\_logic_net: (addr), line:68
|vpiName:addr
|vpiNetType:36
|vpiRange:
\_range: , line:68
|vpiLeftRange:
\_constant: , line:68
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:68
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (valid)
|vpiName:valid
|vpiDirection:1
|vpiExpr:
\_logic_net: (valid), line:69
|vpiName:valid
|vpiNetType:36
|vpiInterface:
\_interface: work@ras_interface (ras), file:third_party/cores/taiga/core/taiga.sv, line:160
|vpiDefName:work@ras_interface
|vpiName:ras
|vpiModport:
\_modport: (branch_unit)
|vpiName:branch_unit
|vpiIODecl:
\_io_decl: (push)
|vpiName:push
|vpiDirection:2
|vpiExpr:
\_logic_net: (push), line:65
|vpiName:push
|vpiNetType:36
|vpiIODecl:
\_io_decl: (pop)
|vpiName:pop
|vpiDirection:2
|vpiExpr:
\_logic_net: (pop), line:66
|vpiName:pop
|vpiNetType:36
|vpiIODecl:
\_io_decl: (new_addr)
|vpiName:new_addr
|vpiDirection:2
|vpiExpr:
\_logic_net: (new_addr), line:67
|vpiName:new_addr
|vpiNetType:36
|vpiRange:
\_range: , line:67
|vpiLeftRange:
\_constant: , line:67
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:67
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiInterface:
\_interface: work@ras_interface (ras), file:third_party/cores/taiga/core/taiga.sv, line:160
|vpiModport:
\_modport: (fetch)
|vpiModport:
\_modport: (self)
|vpiName:self
|vpiIODecl:
\_io_decl: (push)
|vpiName:push
|vpiDirection:1
|vpiExpr:
\_logic_net: (push), line:65
|vpiIODecl:
\_io_decl: (pop)
|vpiName:pop
|vpiDirection:1
|vpiExpr:
\_logic_net: (pop), line:66
|vpiIODecl:
\_io_decl: (new_addr)
|vpiName:new_addr
|vpiDirection:1
|vpiExpr:
\_logic_net: (new_addr), line:67
|vpiIODecl:
\_io_decl: (addr)
|vpiName:addr
|vpiDirection:2
|vpiExpr:
\_logic_net: (addr), line:68
|vpiIODecl:
\_io_decl: (valid)
|vpiName:valid
|vpiDirection:2
|vpiExpr:
\_logic_net: (valid), line:69
|vpiInterface:
\_interface: work@ras_interface (ras), file:third_party/cores/taiga/core/taiga.sv, line:160
|vpiPort:
\_port: (tlb), line:39, parent:fetch_block
|vpiName:tlb
|vpiDirection:5
|vpiHighConn:
\_ref_obj: (tlb), line:160
|vpiName:tlb
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_modport: (mem)
|vpiName:mem
|vpiIODecl:
\_io_decl: (new_request)
|vpiName:new_request
|vpiDirection:2
|vpiExpr:
\_logic_net: (new_request), line:195
|vpiName:new_request
|vpiNetType:36
|vpiIODecl:
\_io_decl: (virtual_address)
|vpiName:virtual_address
|vpiDirection:2
|vpiExpr:
\_logic_net: (virtual_address), line:194
|vpiName:virtual_address
|vpiNetType:36
|vpiRange:
\_range: , line:194
|vpiLeftRange:
\_constant: , line:194
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:194
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (rnw)
|vpiName:rnw
|vpiDirection:2
|vpiExpr:
\_logic_net: (rnw), line:196
|vpiName:rnw
|vpiNetType:36
|vpiIODecl:
\_io_decl: (execute)
|vpiName:execute
|vpiDirection:2
|vpiExpr:
\_logic_net: (execute), line:197
|vpiName:execute
|vpiNetType:36
|vpiIODecl:
\_io_decl: (complete)
|vpiName:complete
|vpiDirection:1
|vpiExpr:
\_logic_net: (complete), line:199
|vpiName:complete
|vpiNetType:36
|vpiIODecl:
\_io_decl: (physical_address)
|vpiName:physical_address
|vpiDirection:1
|vpiExpr:
\_logic_net: (physical_address), line:200
|vpiName:physical_address
|vpiNetType:36
|vpiRange:
\_range: , line:200
|vpiLeftRange:
\_constant: , line:200
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:200
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiInterface:
\_interface: work@tlb_interface (tlb), file:third_party/cores/taiga/core/taiga.sv, line:160
|vpiDefName:work@tlb_interface
|vpiName:tlb
|vpiModport:
\_modport: (fence)
|vpiName:fence
|vpiIODecl:
\_io_decl: (flush)
|vpiName:flush
|vpiDirection:2
|vpiExpr:
\_logic_net: (flush), line:202
|vpiName:flush
|vpiNetType:36
|vpiIODecl:
\_io_decl: (flush_complete)
|vpiName:flush_complete
|vpiDirection:1
|vpiExpr:
\_logic_net: (flush_complete), line:203
|vpiName:flush_complete
|vpiNetType:36
|vpiInterface:
\_interface: work@tlb_interface (tlb), file:third_party/cores/taiga/core/taiga.sv, line:160
|vpiModport:
\_modport: (mem)
|vpiModport:
\_modport: (tlb)
|vpiName:tlb
|vpiIODecl:
\_io_decl: (virtual_address)
|vpiName:virtual_address
|vpiDirection:1
|vpiExpr:
\_logic_net: (virtual_address), line:194
|vpiIODecl:
\_io_decl: (new_request)
|vpiName:new_request
|vpiDirection:1
|vpiExpr:
\_logic_net: (new_request), line:195
|vpiIODecl:
\_io_decl: (flush)
|vpiName:flush
|vpiDirection:1
|vpiExpr:
\_logic_net: (flush), line:202
|vpiIODecl:
\_io_decl: (rnw)
|vpiName:rnw
|vpiDirection:1
|vpiExpr:
\_logic_net: (rnw), line:196
|vpiIODecl:
\_io_decl: (execute)
|vpiName:execute
|vpiDirection:1
|vpiExpr:
\_logic_net: (execute), line:197
|vpiIODecl:
\_io_decl: (complete)
|vpiName:complete
|vpiDirection:2
|vpiExpr:
\_logic_net: (complete), line:199
|vpiIODecl:
\_io_decl: (physical_address)
|vpiName:physical_address
|vpiDirection:2
|vpiExpr:
\_logic_net: (physical_address), line:200
|vpiIODecl:
\_io_decl: (flush_complete)
|vpiName:flush_complete
|vpiDirection:2
|vpiExpr:
\_logic_net: (flush_complete), line:203
|vpiInterface:
\_interface: work@tlb_interface (tlb), file:third_party/cores/taiga/core/taiga.sv, line:160
|vpiPort:
\_port: (instruction_bram), line:40, parent:fetch_block
|vpiName:instruction_bram
|vpiDirection:5
|vpiHighConn:
\_ref_obj: (instruction_bram), line:160
|vpiName:instruction_bram
|vpiActual:
\_interface: work@local_memory_interface (instruction_bram), file:third_party/cores/taiga/examples/zedboard/taiga_wrapper.sv, line:233
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_modport: (master)
|vpiName:master
|vpiIODecl:
\_io_decl: (addr)
|vpiName:addr
|vpiDirection:2
|vpiExpr:
\_logic_net: (addr), line:68
|vpiIODecl:
\_io_decl: (en)
|vpiName:en
|vpiDirection:2
|vpiExpr:
\_logic_net: (en), line:26
|vpiName:en
|vpiNetType:36
|vpiIODecl:
\_io_decl: (be)
|vpiName:be
|vpiDirection:2
|vpiExpr:
\_logic_net: (be), line:27
|vpiName:be
|vpiNetType:36
|vpiRange:
\_range: , line:27
|vpiLeftRange:
\_constant: , line:27
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiRightRange:
\_constant: , line:27
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (data_in)
|vpiName:data_in
|vpiDirection:2
|vpiExpr:
\_logic_net: (data_in), line:28
|vpiName:data_in
|vpiNetType:36
|vpiRange:
\_range: , line:28
|vpiLeftRange:
\_constant: , line:28
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:28
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (data_out)
|vpiName:data_out
|vpiDirection:1
|vpiExpr:
\_logic_net: (data_out), line:29
|vpiName:data_out
|vpiNetType:36
|vpiRange:
\_range: , line:29
|vpiLeftRange:
\_constant: , line:29
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:29
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiInterface:
\_interface: work@local_memory_interface (instruction_bram), file:third_party/cores/taiga/core/taiga.sv, line:160
|vpiDefName:work@local_memory_interface
|vpiName:instruction_bram
|vpiModport:
\_modport: (master)
|vpiModport:
\_modport: (slave)
|vpiName:slave
|vpiIODecl:
\_io_decl: (addr)
|vpiName:addr
|vpiDirection:1
|vpiExpr:
\_logic_net: (addr), line:68
|vpiIODecl:
\_io_decl: (en)
|vpiName:en
|vpiDirection:1
|vpiExpr:
\_logic_net: (en), line:26
|vpiIODecl:
\_io_decl: (be)
|vpiName:be
|vpiDirection:1
|vpiExpr:
\_logic_net: (be), line:27
|vpiIODecl:
\_io_decl: (data_in)
|vpiName:data_in
|vpiDirection:1
|vpiExpr:
\_logic_net: (data_in), line:28
|vpiIODecl:
\_io_decl: (data_out)
|vpiName:data_out
|vpiDirection:2
|vpiExpr:
\_logic_net: (data_out), line:29
|vpiInterface:
\_interface: work@local_memory_interface (instruction_bram), file:third_party/cores/taiga/core/taiga.sv, line:160
|vpiPort:
\_port: (icache_on), line:41, parent:fetch_block
|vpiName:icache_on
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (icache_on), line:160
|vpiName:icache_on
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (icache_on), line:41, parent:fetch_block
|vpiName:icache_on
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.icache_on
|vpiNetType:36
|vpiPort:
\_port: (l1_request), line:42, parent:fetch_block
|vpiName:l1_request
|vpiDirection:5
|vpiHighConn:
\_ref_obj: (l1_request), line:160
|vpiName:l1_request
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_modport: (master)
|vpiName:master
|vpiIODecl:
\_io_decl: (addr)
|vpiName:addr
|vpiDirection:2
|vpiExpr:
\_logic_net: (addr), line:68
|vpiIODecl:
\_io_decl: (data)
|vpiName:data
|vpiDirection:2
|vpiExpr:
\_logic_net: (data), line:124
|vpiName:data
|vpiNetType:36
|vpiRange:
\_range: , line:124
|vpiLeftRange:
\_constant: , line:124
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:124
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (rnw)
|vpiName:rnw
|vpiDirection:2
|vpiExpr:
\_logic_net: (rnw), line:196
|vpiIODecl:
\_io_decl: (be)
|vpiName:be
|vpiDirection:2
|vpiExpr:
\_logic_net: (be), line:27
|vpiIODecl:
\_io_decl: (size)
|vpiName:size
|vpiDirection:2
|vpiExpr:
\_logic_net: (size), line:127
|vpiName:size
|vpiNetType:36
|vpiRange:
\_range: , line:127
|vpiLeftRange:
\_constant: , line:127
|vpiConstType:7
|vpiDecompile:4
|vpiSize:32
|INT:4
|vpiRightRange:
\_constant: , line:127
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (is_amo)
|vpiName:is_amo
|vpiDirection:2
|vpiExpr:
\_logic_net: (is_amo), line:128
|vpiName:is_amo
|vpiNetType:36
|vpiIODecl:
\_io_decl: (amo)
|vpiName:amo
|vpiDirection:2
|vpiExpr:
\_logic_net: (amo), line:129
|vpiName:amo
|vpiNetType:36
|vpiRange:
\_range: , line:129
|vpiLeftRange:
\_constant: , line:129
|vpiConstType:7
|vpiDecompile:4
|vpiSize:32
|INT:4
|vpiRightRange:
\_constant: , line:129
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (request)
|vpiName:request
|vpiDirection:2
|vpiExpr:
\_logic_net: (request), line:131
|vpiName:request
|vpiNetType:36
|vpiIODecl:
\_io_decl: (ack)
|vpiName:ack
|vpiDirection:1
|vpiExpr:
\_logic_net: (ack), line:132
|vpiName:ack
|vpiNetType:36
|vpiInterface:
\_interface: work@l1_arbiter_request_interface (l1_request), file:third_party/cores/taiga/core/taiga.sv, line:160
|vpiDefName:work@l1_arbiter_request_interface
|vpiName:l1_request
|vpiModport:
\_modport: (master)
|vpiModport:
\_modport: (slave)
|vpiName:slave
|vpiIODecl:
\_io_decl: (addr)
|vpiName:addr
|vpiDirection:1
|vpiExpr:
\_logic_net: (addr), line:68
|vpiIODecl:
\_io_decl: (data)
|vpiName:data
|vpiDirection:1
|vpiExpr:
\_logic_net: (data), line:124
|vpiIODecl:
\_io_decl: (rnw)
|vpiName:rnw
|vpiDirection:1
|vpiExpr:
\_logic_net: (rnw), line:196
|vpiIODecl:
\_io_decl: (be)
|vpiName:be
|vpiDirection:1
|vpiExpr:
\_logic_net: (be), line:27
|vpiIODecl:
\_io_decl: (size)
|vpiName:size
|vpiDirection:1
|vpiExpr:
\_logic_net: (size), line:127
|vpiIODecl:
\_io_decl: (is_amo)
|vpiName:is_amo
|vpiDirection:1
|vpiExpr:
\_logic_net: (is_amo), line:128
|vpiIODecl:
\_io_decl: (amo)
|vpiName:amo
|vpiDirection:1
|vpiExpr:
\_logic_net: (amo), line:129
|vpiIODecl:
\_io_decl: (request)
|vpiName:request
|vpiDirection:1
|vpiExpr:
\_logic_net: (request), line:131
|vpiIODecl:
\_io_decl: (ack)
|vpiName:ack
|vpiDirection:2
|vpiExpr:
\_logic_net: (ack), line:132
|vpiInterface:
\_interface: work@l1_arbiter_request_interface (l1_request), file:third_party/cores/taiga/core/taiga.sv, line:160
|vpiPort:
\_port: (l1_response), line:43, parent:fetch_block
|vpiName:l1_response
|vpiDirection:5
|vpiHighConn:
\_ref_obj: (l1_response), line:160
|vpiName:l1_response
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_modport: (master)
|vpiName:master
|vpiIODecl:
\_io_decl: (inv_addr)
|vpiName:inv_addr
|vpiDirection:1
|vpiExpr:
\_logic_net: (inv_addr), line:149
|vpiName:inv_addr
|vpiNetType:36
|vpiRange:
\_range: , line:149
|vpiLeftRange:
\_constant: , line:149
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:149
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiIODecl:
\_io_decl: (inv_valid)
|vpiName:inv_valid
|vpiDirection:1
|vpiExpr:
\_logic_net: (inv_valid), line:150
|vpiName:inv_valid
|vpiNetType:36
|vpiIODecl:
\_io_decl: (data)
|vpiName:data
|vpiDirection:1
|vpiExpr:
\_logic_net: (data), line:124
|vpiIODecl:
\_io_decl: (data_valid)
|vpiName:data_valid
|vpiDirection:1
|vpiExpr:
\_logic_net: (data_valid), line:153
|vpiName:data_valid
|vpiNetType:36
|vpiIODecl:
\_io_decl: (inv_ack)
|vpiName:inv_ack
|vpiDirection:2
|vpiExpr:
\_logic_net: (inv_ack), line:151
|vpiName:inv_ack
|vpiNetType:36
|vpiInterface:
\_interface: work@l1_arbiter_return_interface (l1_response), file:third_party/cores/taiga/core/taiga.sv, line:160
|vpiDefName:work@l1_arbiter_return_interface
|vpiName:l1_response
|vpiModport:
\_modport: (master)
|vpiModport:
\_modport: (slave)
|vpiName:slave
|vpiIODecl:
\_io_decl: (inv_addr)
|vpiName:inv_addr
|vpiDirection:2
|vpiExpr:
\_logic_net: (inv_addr), line:149
|vpiIODecl:
\_io_decl: (inv_valid)
|vpiName:inv_valid
|vpiDirection:2
|vpiExpr:
\_logic_net: (inv_valid), line:150
|vpiIODecl:
\_io_decl: (data)
|vpiName:data
|vpiDirection:2
|vpiExpr:
\_logic_net: (data), line:124
|vpiIODecl:
\_io_decl: (data_valid)
|vpiName:data_valid
|vpiDirection:2
|vpiExpr:
\_logic_net: (data_valid), line:153
|vpiIODecl:
\_io_decl: (inv_ack)
|vpiName:inv_ack
|vpiDirection:1
|vpiExpr:
\_logic_net: (inv_ack), line:151
|vpiInterface:
\_interface: work@l1_arbiter_return_interface (l1_response), file:third_party/cores/taiga/core/taiga.sv, line:160
|vpiPort:
\_port: (pre_decode_pop), line:45, parent:fetch_block
|vpiName:pre_decode_pop
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (pre_decode_pop), line:160
|vpiName:pre_decode_pop
|vpiActual:
\_logic_net: (pre_decode_pop), line:83, parent:cpu
|vpiName:pre_decode_pop
|vpiFullName:work@taiga_wrapper.cpu.pre_decode_pop
|vpiNetType:36
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (pre_decode_pop), line:45, parent:fetch_block
|vpiName:pre_decode_pop
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.pre_decode_pop
|vpiNetType:36
|vpiPort:
\_port: (pre_decode_instruction), line:47, parent:fetch_block
|vpiName:pre_decode_instruction
|vpiDirection:2
|vpiHighConn:
\_ref_obj: (pre_decode_instruction), line:160
|vpiName:pre_decode_instruction
|vpiActual:
\_logic_net: (pre_decode_instruction), line:84, parent:cpu
|vpiName:pre_decode_instruction
|vpiFullName:work@taiga_wrapper.cpu.pre_decode_instruction
|vpiNetType:36
|vpiRange:
\_range: , line:84
|vpiLeftRange:
\_constant: , line:84
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:84
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (pre_decode_instruction), line:47, parent:fetch_block
|vpiName:pre_decode_instruction
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.pre_decode_instruction
|vpiNetType:36
|vpiRange:
\_range: , line:47
|vpiLeftRange:
\_constant: , line:47
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:47
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiPort:
\_port: (pre_decode_pc), line:48, parent:fetch_block
|vpiName:pre_decode_pc
|vpiDirection:2
|vpiHighConn:
\_ref_obj: (pre_decode_pc), line:160
|vpiName:pre_decode_pc
|vpiActual:
\_logic_net: (pre_decode_pc), line:85, parent:cpu
|vpiName:pre_decode_pc
|vpiFullName:work@taiga_wrapper.cpu.pre_decode_pc
|vpiNetType:36
|vpiRange:
\_range: , line:85
|vpiLeftRange:
\_constant: , line:85
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:85
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (pre_decode_pc), line:48, parent:fetch_block
|vpiName:pre_decode_pc
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.pre_decode_pc
|vpiNetType:36
|vpiRange:
\_range: , line:48
|vpiLeftRange:
\_constant: , line:48
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:48
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiPort:
\_port: (branch_metadata), line:49, parent:fetch_block
|vpiName:branch_metadata
|vpiDirection:2
|vpiTypedef:
\_logic_typespec: (branch_predictor_metadata_t), line:32
|vpiHighConn:
\_ref_obj: (branch_metadata), line:160
|vpiName:branch_metadata
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (branch_metadata), line:49, parent:fetch_block
|vpiName:branch_metadata
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.branch_metadata
|vpiPort:
\_port: (branch_prediction_used), line:50, parent:fetch_block
|vpiName:branch_prediction_used
|vpiDirection:2
|vpiHighConn:
\_ref_obj: (branch_prediction_used), line:160
|vpiName:branch_prediction_used
|vpiActual:
\_logic_net: (branch_prediction_used), line:87, parent:cpu
|vpiName:branch_prediction_used
|vpiFullName:work@taiga_wrapper.cpu.branch_prediction_used
|vpiNetType:36
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (branch_prediction_used), line:50, parent:fetch_block
|vpiName:branch_prediction_used
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.branch_prediction_used
|vpiNetType:36
|vpiPort:
\_port: (bp_update_way), line:51, parent:fetch_block
|vpiName:bp_update_way
|vpiDirection:2
|vpiHighConn:
\_ref_obj: (bp_update_way), line:160
|vpiName:bp_update_way
|vpiActual:
\_logic_net: (bp_update_way), line:88, parent:cpu
|vpiName:bp_update_way
|vpiFullName:work@taiga_wrapper.cpu.bp_update_way
|vpiNetType:36
|vpiRange:
\_range: , line:88
|vpiLeftRange:
\_constant: , line:88
|vpiConstType:7
|vpiDecompile:8
|vpiSize:32
|INT:8
|vpiRightRange:
\_constant: , line:88
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (bp_update_way), line:51, parent:fetch_block
|vpiName:bp_update_way
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.bp_update_way
|vpiNetType:36
|vpiRange:
\_range: , line:51
|vpiLeftRange:
\_constant: , line:51
|vpiConstType:7
|vpiDecompile:8
|vpiSize:32
|INT:8
|vpiRightRange:
\_constant: , line:51
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiPort:
\_port: (pre_decode_push), line:52, parent:fetch_block
|vpiName:pre_decode_push
|vpiDirection:2
|vpiHighConn:
\_ref_obj: (pre_decode_push), line:160
|vpiName:pre_decode_push
|vpiActual:
\_logic_net: (pre_decode_push), line:82, parent:cpu
|vpiName:pre_decode_push
|vpiFullName:work@taiga_wrapper.cpu.pre_decode_push
|vpiNetType:36
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (pre_decode_push), line:52, parent:fetch_block
|vpiName:pre_decode_push
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.pre_decode_push
|vpiNetType:36
|vpiInterface:
\_interface: work@fetch_sub_unit_interface (fetch_sub0), file:third_party/cores/taiga/core/fetch.sv, line:65, parent:fetch_block
|vpiDefName:work@fetch_sub_unit_interface
|vpiName:fetch_sub0
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.fetch_sub0
|vpiModport:
\_modport: (fetch), parent:fetch_sub0
|vpiName:fetch
|vpiIODecl:
\_io_decl: (stage1_addr), parent:fetch
|vpiName:stage1_addr
|vpiDirection:2
|vpiIODecl:
\_io_decl: (stage2_addr), parent:fetch
|vpiName:stage2_addr
|vpiDirection:2
|vpiIODecl:
\_io_decl: (new_request), parent:fetch
|vpiName:new_request
|vpiDirection:2
|vpiIODecl:
\_io_decl: (flush), parent:fetch
|vpiName:flush
|vpiDirection:2
|vpiIODecl:
\_io_decl: (data_out), parent:fetch
|vpiName:data_out
|vpiDirection:1
|vpiIODecl:
\_io_decl: (data_valid), parent:fetch
|vpiName:data_valid
|vpiDirection:1
|vpiIODecl:
\_io_decl: (ready), parent:fetch
|vpiName:ready
|vpiDirection:1
|vpiInterface:
\_interface: work@fetch_sub_unit_interface (fetch_sub0), file:third_party/cores/taiga/core/fetch.sv, line:65, parent:fetch_block
|vpiModport:
\_modport: (sub_unit), parent:fetch_sub0
|vpiName:sub_unit
|vpiIODecl:
\_io_decl: (stage1_addr), parent:sub_unit
|vpiName:stage1_addr
|vpiDirection:1
|vpiIODecl:
\_io_decl: (stage2_addr), parent:sub_unit
|vpiName:stage2_addr
|vpiDirection:1
|vpiIODecl:
\_io_decl: (new_request), parent:sub_unit
|vpiName:new_request
|vpiDirection:1
|vpiIODecl:
\_io_decl: (flush), parent:sub_unit
|vpiName:flush
|vpiDirection:1
|vpiIODecl:
\_io_decl: (data_out), parent:sub_unit
|vpiName:data_out
|vpiDirection:2
|vpiIODecl:
\_io_decl: (data_valid), parent:sub_unit
|vpiName:data_valid
|vpiDirection:2
|vpiIODecl:
\_io_decl: (ready), parent:sub_unit
|vpiName:ready
|vpiDirection:2
|vpiInterface:
\_interface: work@fetch_sub_unit_interface (fetch_sub0), file:third_party/cores/taiga/core/fetch.sv, line:65, parent:fetch_block
|vpiNet:
\_logic_net: (stage1_addr), line:228, parent:fetch_sub0
|vpiName:stage1_addr
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.fetch_sub0.stage1_addr
|vpiNetType:36
|vpiRange:
\_range: , line:228
|vpiLeftRange:
\_constant: , line:228
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:228
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (stage2_addr), line:229, parent:fetch_sub0
|vpiName:stage2_addr
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.fetch_sub0.stage2_addr
|vpiNetType:36
|vpiRange:
\_range: , line:229
|vpiLeftRange:
\_constant: , line:229
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:229
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (data_out), line:231, parent:fetch_sub0
|vpiName:data_out
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.fetch_sub0.data_out
|vpiNetType:36
|vpiRange:
\_range: , line:231
|vpiLeftRange:
\_constant: , line:231
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:231
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (data_valid), line:232, parent:fetch_sub0
|vpiName:data_valid
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.fetch_sub0.data_valid
|vpiNetType:36
|vpiNet:
\_logic_net: (ready), line:233, parent:fetch_sub0
|vpiName:ready
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.fetch_sub0.ready
|vpiNetType:36
|vpiNet:
\_logic_net: (new_request), line:234, parent:fetch_sub0
|vpiName:new_request
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.fetch_sub0.new_request
|vpiNetType:36
|vpiNet:
\_logic_net: (flush), line:235, parent:fetch_sub0
|vpiName:flush
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.fetch_sub0.flush
|vpiNetType:36
|vpiInstance:
\_module: work@fetch (fetch_block), file:third_party/cores/taiga/core/taiga.sv, line:160, parent:cpu
|vpiInterface:
\_interface: work@fetch_sub_unit_interface (fetch_sub1), file:third_party/cores/taiga/core/fetch.sv, line:65, parent:fetch_block
|vpiDefName:work@fetch_sub_unit_interface
|vpiName:fetch_sub1
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.fetch_sub1
|vpiModport:
\_modport: (fetch), parent:fetch_sub1
|vpiName:fetch
|vpiIODecl:
\_io_decl: (stage1_addr), parent:fetch
|vpiName:stage1_addr
|vpiDirection:2
|vpiIODecl:
\_io_decl: (stage2_addr), parent:fetch
|vpiName:stage2_addr
|vpiDirection:2
|vpiIODecl:
\_io_decl: (new_request), parent:fetch
|vpiName:new_request
|vpiDirection:2
|vpiIODecl:
\_io_decl: (flush), parent:fetch
|vpiName:flush
|vpiDirection:2
|vpiIODecl:
\_io_decl: (data_out), parent:fetch
|vpiName:data_out
|vpiDirection:1
|vpiIODecl:
\_io_decl: (data_valid), parent:fetch
|vpiName:data_valid
|vpiDirection:1
|vpiIODecl:
\_io_decl: (ready), parent:fetch
|vpiName:ready
|vpiDirection:1
|vpiInterface:
\_interface: work@fetch_sub_unit_interface (fetch_sub1), file:third_party/cores/taiga/core/fetch.sv, line:65, parent:fetch_block
|vpiModport:
\_modport: (sub_unit), parent:fetch_sub1
|vpiName:sub_unit
|vpiIODecl:
\_io_decl: (stage1_addr), parent:sub_unit
|vpiName:stage1_addr
|vpiDirection:1
|vpiIODecl:
\_io_decl: (stage2_addr), parent:sub_unit
|vpiName:stage2_addr
|vpiDirection:1
|vpiIODecl:
\_io_decl: (new_request), parent:sub_unit
|vpiName:new_request
|vpiDirection:1
|vpiIODecl:
\_io_decl: (flush), parent:sub_unit
|vpiName:flush
|vpiDirection:1
|vpiIODecl:
\_io_decl: (data_out), parent:sub_unit
|vpiName:data_out
|vpiDirection:2
|vpiIODecl:
\_io_decl: (data_valid), parent:sub_unit
|vpiName:data_valid
|vpiDirection:2
|vpiIODecl:
\_io_decl: (ready), parent:sub_unit
|vpiName:ready
|vpiDirection:2
|vpiInterface:
\_interface: work@fetch_sub_unit_interface (fetch_sub1), file:third_party/cores/taiga/core/fetch.sv, line:65, parent:fetch_block
|vpiNet:
\_logic_net: (stage1_addr), line:228, parent:fetch_sub1
|vpiName:stage1_addr
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.fetch_sub1.stage1_addr
|vpiNetType:36
|vpiRange:
\_range: , line:228
|vpiLeftRange:
\_constant: , line:228
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:228
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (stage2_addr), line:229, parent:fetch_sub1
|vpiName:stage2_addr
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.fetch_sub1.stage2_addr
|vpiNetType:36
|vpiRange:
\_range: , line:229
|vpiLeftRange:
\_constant: , line:229
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:229
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (data_out), line:231, parent:fetch_sub1
|vpiName:data_out
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.fetch_sub1.data_out
|vpiNetType:36
|vpiRange:
\_range: , line:231
|vpiLeftRange:
\_constant: , line:231
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:231
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (data_valid), line:232, parent:fetch_sub1
|vpiName:data_valid
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.fetch_sub1.data_valid
|vpiNetType:36
|vpiNet:
\_logic_net: (ready), line:233, parent:fetch_sub1
|vpiName:ready
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.fetch_sub1.ready
|vpiNetType:36
|vpiNet:
\_logic_net: (new_request), line:234, parent:fetch_sub1
|vpiName:new_request
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.fetch_sub1.new_request
|vpiNetType:36
|vpiNet:
\_logic_net: (flush), line:235, parent:fetch_sub1
|vpiName:flush
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.fetch_sub1.flush
|vpiNetType:36
|vpiInstance:
\_module: work@fetch (fetch_block), file:third_party/cores/taiga/core/taiga.sv, line:160, parent:cpu
|vpiInterface:
\_interface: work@fetch_sub_unit_interface (fetch_sub2), file:third_party/cores/taiga/core/fetch.sv, line:65, parent:fetch_block
|vpiDefName:work@fetch_sub_unit_interface
|vpiName:fetch_sub2
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.fetch_sub2
|vpiModport:
\_modport: (fetch), parent:fetch_sub2
|vpiName:fetch
|vpiIODecl:
\_io_decl: (stage1_addr), parent:fetch
|vpiName:stage1_addr
|vpiDirection:2
|vpiIODecl:
\_io_decl: (stage2_addr), parent:fetch
|vpiName:stage2_addr
|vpiDirection:2
|vpiIODecl:
\_io_decl: (new_request), parent:fetch
|vpiName:new_request
|vpiDirection:2
|vpiIODecl:
\_io_decl: (flush), parent:fetch
|vpiName:flush
|vpiDirection:2
|vpiIODecl:
\_io_decl: (data_out), parent:fetch
|vpiName:data_out
|vpiDirection:1
|vpiIODecl:
\_io_decl: (data_valid), parent:fetch
|vpiName:data_valid
|vpiDirection:1
|vpiIODecl:
\_io_decl: (ready), parent:fetch
|vpiName:ready
|vpiDirection:1
|vpiInterface:
\_interface: work@fetch_sub_unit_interface (fetch_sub2), file:third_party/cores/taiga/core/fetch.sv, line:65, parent:fetch_block
|vpiModport:
\_modport: (sub_unit), parent:fetch_sub2
|vpiName:sub_unit
|vpiIODecl:
\_io_decl: (stage1_addr), parent:sub_unit
|vpiName:stage1_addr
|vpiDirection:1
|vpiIODecl:
\_io_decl: (stage2_addr), parent:sub_unit
|vpiName:stage2_addr
|vpiDirection:1
|vpiIODecl:
\_io_decl: (new_request), parent:sub_unit
|vpiName:new_request
|vpiDirection:1
|vpiIODecl:
\_io_decl: (flush), parent:sub_unit
|vpiName:flush
|vpiDirection:1
|vpiIODecl:
\_io_decl: (data_out), parent:sub_unit
|vpiName:data_out
|vpiDirection:2
|vpiIODecl:
\_io_decl: (data_valid), parent:sub_unit
|vpiName:data_valid
|vpiDirection:2
|vpiIODecl:
\_io_decl: (ready), parent:sub_unit
|vpiName:ready
|vpiDirection:2
|vpiInterface:
\_interface: work@fetch_sub_unit_interface (fetch_sub2), file:third_party/cores/taiga/core/fetch.sv, line:65, parent:fetch_block
|vpiNet:
\_logic_net: (stage1_addr), line:228, parent:fetch_sub2
|vpiName:stage1_addr
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.fetch_sub2.stage1_addr
|vpiNetType:36
|vpiRange:
\_range: , line:228
|vpiLeftRange:
\_constant: , line:228
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:228
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (stage2_addr), line:229, parent:fetch_sub2
|vpiName:stage2_addr
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.fetch_sub2.stage2_addr
|vpiNetType:36
|vpiRange:
\_range: , line:229
|vpiLeftRange:
\_constant: , line:229
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:229
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (data_out), line:231, parent:fetch_sub2
|vpiName:data_out
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.fetch_sub2.data_out
|vpiNetType:36
|vpiRange:
\_range: , line:231
|vpiLeftRange:
\_constant: , line:231
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:231
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (data_valid), line:232, parent:fetch_sub2
|vpiName:data_valid
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.fetch_sub2.data_valid
|vpiNetType:36
|vpiNet:
\_logic_net: (ready), line:233, parent:fetch_sub2
|vpiName:ready
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.fetch_sub2.ready
|vpiNetType:36
|vpiNet:
\_logic_net: (new_request), line:234, parent:fetch_sub2
|vpiName:new_request
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.fetch_sub2.new_request
|vpiNetType:36
|vpiNet:
\_logic_net: (flush), line:235, parent:fetch_sub2
|vpiName:flush
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.fetch_sub2.flush
|vpiNetType:36
|vpiInstance:
\_module: work@fetch (fetch_block), file:third_party/cores/taiga/core/taiga.sv, line:160, parent:cpu
|vpiInterface:
\_interface: work@fetch_sub_unit_interface (fetch_sub3), file:third_party/cores/taiga/core/fetch.sv, line:65, parent:fetch_block
|vpiDefName:work@fetch_sub_unit_interface
|vpiName:fetch_sub3
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.fetch_sub3
|vpiModport:
\_modport: (fetch), parent:fetch_sub3
|vpiName:fetch
|vpiIODecl:
\_io_decl: (stage1_addr), parent:fetch
|vpiName:stage1_addr
|vpiDirection:2
|vpiIODecl:
\_io_decl: (stage2_addr), parent:fetch
|vpiName:stage2_addr
|vpiDirection:2
|vpiIODecl:
\_io_decl: (new_request), parent:fetch
|vpiName:new_request
|vpiDirection:2
|vpiIODecl:
\_io_decl: (flush), parent:fetch
|vpiName:flush
|vpiDirection:2
|vpiIODecl:
\_io_decl: (data_out), parent:fetch
|vpiName:data_out
|vpiDirection:1
|vpiIODecl:
\_io_decl: (data_valid), parent:fetch
|vpiName:data_valid
|vpiDirection:1
|vpiIODecl:
\_io_decl: (ready), parent:fetch
|vpiName:ready
|vpiDirection:1
|vpiInterface:
\_interface: work@fetch_sub_unit_interface (fetch_sub3), file:third_party/cores/taiga/core/fetch.sv, line:65, parent:fetch_block
|vpiModport:
\_modport: (sub_unit), parent:fetch_sub3
|vpiName:sub_unit
|vpiIODecl:
\_io_decl: (stage1_addr), parent:sub_unit
|vpiName:stage1_addr
|vpiDirection:1
|vpiIODecl:
\_io_decl: (stage2_addr), parent:sub_unit
|vpiName:stage2_addr
|vpiDirection:1
|vpiIODecl:
\_io_decl: (new_request), parent:sub_unit
|vpiName:new_request
|vpiDirection:1
|vpiIODecl:
\_io_decl: (flush), parent:sub_unit
|vpiName:flush
|vpiDirection:1
|vpiIODecl:
\_io_decl: (data_out), parent:sub_unit
|vpiName:data_out
|vpiDirection:2
|vpiIODecl:
\_io_decl: (data_valid), parent:sub_unit
|vpiName:data_valid
|vpiDirection:2
|vpiIODecl:
\_io_decl: (ready), parent:sub_unit
|vpiName:ready
|vpiDirection:2
|vpiInterface:
\_interface: work@fetch_sub_unit_interface (fetch_sub3), file:third_party/cores/taiga/core/fetch.sv, line:65, parent:fetch_block
|vpiNet:
\_logic_net: (stage1_addr), line:228, parent:fetch_sub3
|vpiName:stage1_addr
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.fetch_sub3.stage1_addr
|vpiNetType:36
|vpiRange:
\_range: , line:228
|vpiLeftRange:
\_constant: , line:228
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:228
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (stage2_addr), line:229, parent:fetch_sub3
|vpiName:stage2_addr
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.fetch_sub3.stage2_addr
|vpiNetType:36
|vpiRange:
\_range: , line:229
|vpiLeftRange:
\_constant: , line:229
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:229
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (data_out), line:231, parent:fetch_sub3
|vpiName:data_out
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.fetch_sub3.data_out
|vpiNetType:36
|vpiRange:
\_range: , line:231
|vpiLeftRange:
\_constant: , line:231
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:231
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (data_valid), line:232, parent:fetch_sub3
|vpiName:data_valid
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.fetch_sub3.data_valid
|vpiNetType:36
|vpiNet:
\_logic_net: (ready), line:233, parent:fetch_sub3
|vpiName:ready
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.fetch_sub3.ready
|vpiNetType:36
|vpiNet:
\_logic_net: (new_request), line:234, parent:fetch_sub3
|vpiName:new_request
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.fetch_sub3.new_request
|vpiNetType:36
|vpiNet:
\_logic_net: (flush), line:235, parent:fetch_sub3
|vpiName:flush
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.fetch_sub3.flush
|vpiNetType:36
|vpiInstance:
\_module: work@fetch (fetch_block), file:third_party/cores/taiga/core/taiga.sv, line:160, parent:cpu
|vpiInterface:
\_interface: work@fetch_sub_unit_interface (fetch_sub4), file:third_party/cores/taiga/core/fetch.sv, line:65, parent:fetch_block
|vpiDefName:work@fetch_sub_unit_interface
|vpiName:fetch_sub4
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.fetch_sub4
|vpiModport:
\_modport: (fetch), parent:fetch_sub4
|vpiName:fetch
|vpiIODecl:
\_io_decl: (stage1_addr), parent:fetch
|vpiName:stage1_addr
|vpiDirection:2
|vpiIODecl:
\_io_decl: (stage2_addr), parent:fetch
|vpiName:stage2_addr
|vpiDirection:2
|vpiIODecl:
\_io_decl: (new_request), parent:fetch
|vpiName:new_request
|vpiDirection:2
|vpiIODecl:
\_io_decl: (flush), parent:fetch
|vpiName:flush
|vpiDirection:2
|vpiIODecl:
\_io_decl: (data_out), parent:fetch
|vpiName:data_out
|vpiDirection:1
|vpiIODecl:
\_io_decl: (data_valid), parent:fetch
|vpiName:data_valid
|vpiDirection:1
|vpiIODecl:
\_io_decl: (ready), parent:fetch
|vpiName:ready
|vpiDirection:1
|vpiInterface:
\_interface: work@fetch_sub_unit_interface (fetch_sub4), file:third_party/cores/taiga/core/fetch.sv, line:65, parent:fetch_block
|vpiModport:
\_modport: (sub_unit), parent:fetch_sub4
|vpiName:sub_unit
|vpiIODecl:
\_io_decl: (stage1_addr), parent:sub_unit
|vpiName:stage1_addr
|vpiDirection:1
|vpiIODecl:
\_io_decl: (stage2_addr), parent:sub_unit
|vpiName:stage2_addr
|vpiDirection:1
|vpiIODecl:
\_io_decl: (new_request), parent:sub_unit
|vpiName:new_request
|vpiDirection:1
|vpiIODecl:
\_io_decl: (flush), parent:sub_unit
|vpiName:flush
|vpiDirection:1
|vpiIODecl:
\_io_decl: (data_out), parent:sub_unit
|vpiName:data_out
|vpiDirection:2
|vpiIODecl:
\_io_decl: (data_valid), parent:sub_unit
|vpiName:data_valid
|vpiDirection:2
|vpiIODecl:
\_io_decl: (ready), parent:sub_unit
|vpiName:ready
|vpiDirection:2
|vpiInterface:
\_interface: work@fetch_sub_unit_interface (fetch_sub4), file:third_party/cores/taiga/core/fetch.sv, line:65, parent:fetch_block
|vpiNet:
\_logic_net: (stage1_addr), line:228, parent:fetch_sub4
|vpiName:stage1_addr
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.fetch_sub4.stage1_addr
|vpiNetType:36
|vpiRange:
\_range: , line:228
|vpiLeftRange:
\_constant: , line:228
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:228
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (stage2_addr), line:229, parent:fetch_sub4
|vpiName:stage2_addr
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.fetch_sub4.stage2_addr
|vpiNetType:36
|vpiRange:
\_range: , line:229
|vpiLeftRange:
\_constant: , line:229
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:229
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (data_out), line:231, parent:fetch_sub4
|vpiName:data_out
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.fetch_sub4.data_out
|vpiNetType:36
|vpiRange:
\_range: , line:231
|vpiLeftRange:
\_constant: , line:231
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:231
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (data_valid), line:232, parent:fetch_sub4
|vpiName:data_valid
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.fetch_sub4.data_valid
|vpiNetType:36
|vpiNet:
\_logic_net: (ready), line:233, parent:fetch_sub4
|vpiName:ready
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.fetch_sub4.ready
|vpiNetType:36
|vpiNet:
\_logic_net: (new_request), line:234, parent:fetch_sub4
|vpiName:new_request
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.fetch_sub4.new_request
|vpiNetType:36
|vpiNet:
\_logic_net: (flush), line:235, parent:fetch_sub4
|vpiName:flush
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.fetch_sub4.flush
|vpiNetType:36
|vpiInstance:
\_module: work@fetch (fetch_block), file:third_party/cores/taiga/core/taiga.sv, line:160, parent:cpu
|vpiInterface:
\_interface: work@fetch_sub_unit_interface (fetch_sub5), file:third_party/cores/taiga/core/fetch.sv, line:65, parent:fetch_block
|vpiDefName:work@fetch_sub_unit_interface
|vpiName:fetch_sub5
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.fetch_sub5
|vpiModport:
\_modport: (fetch), parent:fetch_sub5
|vpiName:fetch
|vpiIODecl:
\_io_decl: (stage1_addr), parent:fetch
|vpiName:stage1_addr
|vpiDirection:2
|vpiIODecl:
\_io_decl: (stage2_addr), parent:fetch
|vpiName:stage2_addr
|vpiDirection:2
|vpiIODecl:
\_io_decl: (new_request), parent:fetch
|vpiName:new_request
|vpiDirection:2
|vpiIODecl:
\_io_decl: (flush), parent:fetch
|vpiName:flush
|vpiDirection:2
|vpiIODecl:
\_io_decl: (data_out), parent:fetch
|vpiName:data_out
|vpiDirection:1
|vpiIODecl:
\_io_decl: (data_valid), parent:fetch
|vpiName:data_valid
|vpiDirection:1
|vpiIODecl:
\_io_decl: (ready), parent:fetch
|vpiName:ready
|vpiDirection:1
|vpiInterface:
\_interface: work@fetch_sub_unit_interface (fetch_sub5), file:third_party/cores/taiga/core/fetch.sv, line:65, parent:fetch_block
|vpiModport:
\_modport: (sub_unit), parent:fetch_sub5
|vpiName:sub_unit
|vpiIODecl:
\_io_decl: (stage1_addr), parent:sub_unit
|vpiName:stage1_addr
|vpiDirection:1
|vpiIODecl:
\_io_decl: (stage2_addr), parent:sub_unit
|vpiName:stage2_addr
|vpiDirection:1
|vpiIODecl:
\_io_decl: (new_request), parent:sub_unit
|vpiName:new_request
|vpiDirection:1
|vpiIODecl:
\_io_decl: (flush), parent:sub_unit
|vpiName:flush
|vpiDirection:1
|vpiIODecl:
\_io_decl: (data_out), parent:sub_unit
|vpiName:data_out
|vpiDirection:2
|vpiIODecl:
\_io_decl: (data_valid), parent:sub_unit
|vpiName:data_valid
|vpiDirection:2
|vpiIODecl:
\_io_decl: (ready), parent:sub_unit
|vpiName:ready
|vpiDirection:2
|vpiInterface:
\_interface: work@fetch_sub_unit_interface (fetch_sub5), file:third_party/cores/taiga/core/fetch.sv, line:65, parent:fetch_block
|vpiNet:
\_logic_net: (stage1_addr), line:228, parent:fetch_sub5
|vpiName:stage1_addr
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.fetch_sub5.stage1_addr
|vpiNetType:36
|vpiRange:
\_range: , line:228
|vpiLeftRange:
\_constant: , line:228
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:228
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (stage2_addr), line:229, parent:fetch_sub5
|vpiName:stage2_addr
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.fetch_sub5.stage2_addr
|vpiNetType:36
|vpiRange:
\_range: , line:229
|vpiLeftRange:
\_constant: , line:229
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:229
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (data_out), line:231, parent:fetch_sub5
|vpiName:data_out
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.fetch_sub5.data_out
|vpiNetType:36
|vpiRange:
\_range: , line:231
|vpiLeftRange:
\_constant: , line:231
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:231
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (data_valid), line:232, parent:fetch_sub5
|vpiName:data_valid
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.fetch_sub5.data_valid
|vpiNetType:36
|vpiNet:
\_logic_net: (ready), line:233, parent:fetch_sub5
|vpiName:ready
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.fetch_sub5.ready
|vpiNetType:36
|vpiNet:
\_logic_net: (new_request), line:234, parent:fetch_sub5
|vpiName:new_request
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.fetch_sub5.new_request
|vpiNetType:36
|vpiNet:
\_logic_net: (flush), line:235, parent:fetch_sub5
|vpiName:flush
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.fetch_sub5.flush
|vpiNetType:36
|vpiInstance:
\_module: work@fetch (fetch_block), file:third_party/cores/taiga/core/taiga.sv, line:160, parent:cpu
|vpiInterface:
\_interface: work@fetch_sub_unit_interface (fetch_sub6), file:third_party/cores/taiga/core/fetch.sv, line:65, parent:fetch_block
|vpiDefName:work@fetch_sub_unit_interface
|vpiName:fetch_sub6
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.fetch_sub6
|vpiModport:
\_modport: (fetch), parent:fetch_sub6
|vpiName:fetch
|vpiIODecl:
\_io_decl: (stage1_addr), parent:fetch
|vpiName:stage1_addr
|vpiDirection:2
|vpiIODecl:
\_io_decl: (stage2_addr), parent:fetch
|vpiName:stage2_addr
|vpiDirection:2
|vpiIODecl:
\_io_decl: (new_request), parent:fetch
|vpiName:new_request
|vpiDirection:2
|vpiIODecl:
\_io_decl: (flush), parent:fetch
|vpiName:flush
|vpiDirection:2
|vpiIODecl:
\_io_decl: (data_out), parent:fetch
|vpiName:data_out
|vpiDirection:1
|vpiIODecl:
\_io_decl: (data_valid), parent:fetch
|vpiName:data_valid
|vpiDirection:1
|vpiIODecl:
\_io_decl: (ready), parent:fetch
|vpiName:ready
|vpiDirection:1
|vpiInterface:
\_interface: work@fetch_sub_unit_interface (fetch_sub6), file:third_party/cores/taiga/core/fetch.sv, line:65, parent:fetch_block
|vpiModport:
\_modport: (sub_unit), parent:fetch_sub6
|vpiName:sub_unit
|vpiIODecl:
\_io_decl: (stage1_addr), parent:sub_unit
|vpiName:stage1_addr
|vpiDirection:1
|vpiIODecl:
\_io_decl: (stage2_addr), parent:sub_unit
|vpiName:stage2_addr
|vpiDirection:1
|vpiIODecl:
\_io_decl: (new_request), parent:sub_unit
|vpiName:new_request
|vpiDirection:1
|vpiIODecl:
\_io_decl: (flush), parent:sub_unit
|vpiName:flush
|vpiDirection:1
|vpiIODecl:
\_io_decl: (data_out), parent:sub_unit
|vpiName:data_out
|vpiDirection:2
|vpiIODecl:
\_io_decl: (data_valid), parent:sub_unit
|vpiName:data_valid
|vpiDirection:2
|vpiIODecl:
\_io_decl: (ready), parent:sub_unit
|vpiName:ready
|vpiDirection:2
|vpiInterface:
\_interface: work@fetch_sub_unit_interface (fetch_sub6), file:third_party/cores/taiga/core/fetch.sv, line:65, parent:fetch_block
|vpiNet:
\_logic_net: (stage1_addr), line:228, parent:fetch_sub6
|vpiName:stage1_addr
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.fetch_sub6.stage1_addr
|vpiNetType:36
|vpiRange:
\_range: , line:228
|vpiLeftRange:
\_constant: , line:228
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:228
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (stage2_addr), line:229, parent:fetch_sub6
|vpiName:stage2_addr
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.fetch_sub6.stage2_addr
|vpiNetType:36
|vpiRange:
\_range: , line:229
|vpiLeftRange:
\_constant: , line:229
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:229
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (data_out), line:231, parent:fetch_sub6
|vpiName:data_out
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.fetch_sub6.data_out
|vpiNetType:36
|vpiRange:
\_range: , line:231
|vpiLeftRange:
\_constant: , line:231
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:231
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (data_valid), line:232, parent:fetch_sub6
|vpiName:data_valid
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.fetch_sub6.data_valid
|vpiNetType:36
|vpiNet:
\_logic_net: (ready), line:233, parent:fetch_sub6
|vpiName:ready
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.fetch_sub6.ready
|vpiNetType:36
|vpiNet:
\_logic_net: (new_request), line:234, parent:fetch_sub6
|vpiName:new_request
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.fetch_sub6.new_request
|vpiNetType:36
|vpiNet:
\_logic_net: (flush), line:235, parent:fetch_sub6
|vpiName:flush
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.fetch_sub6.flush
|vpiNetType:36
|vpiInstance:
\_module: work@fetch (fetch_block), file:third_party/cores/taiga/core/taiga.sv, line:160, parent:cpu
|vpiInterface:
\_interface: work@fetch_sub_unit_interface (fetch_sub7), file:third_party/cores/taiga/core/fetch.sv, line:65, parent:fetch_block
|vpiDefName:work@fetch_sub_unit_interface
|vpiName:fetch_sub7
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.fetch_sub7
|vpiModport:
\_modport: (fetch), parent:fetch_sub7
|vpiName:fetch
|vpiIODecl:
\_io_decl: (stage1_addr), parent:fetch
|vpiName:stage1_addr
|vpiDirection:2
|vpiIODecl:
\_io_decl: (stage2_addr), parent:fetch
|vpiName:stage2_addr
|vpiDirection:2
|vpiIODecl:
\_io_decl: (new_request), parent:fetch
|vpiName:new_request
|vpiDirection:2
|vpiIODecl:
\_io_decl: (flush), parent:fetch
|vpiName:flush
|vpiDirection:2
|vpiIODecl:
\_io_decl: (data_out), parent:fetch
|vpiName:data_out
|vpiDirection:1
|vpiIODecl:
\_io_decl: (data_valid), parent:fetch
|vpiName:data_valid
|vpiDirection:1
|vpiIODecl:
\_io_decl: (ready), parent:fetch
|vpiName:ready
|vpiDirection:1
|vpiInterface:
\_interface: work@fetch_sub_unit_interface (fetch_sub7), file:third_party/cores/taiga/core/fetch.sv, line:65, parent:fetch_block
|vpiModport:
\_modport: (sub_unit), parent:fetch_sub7
|vpiName:sub_unit
|vpiIODecl:
\_io_decl: (stage1_addr), parent:sub_unit
|vpiName:stage1_addr
|vpiDirection:1
|vpiIODecl:
\_io_decl: (stage2_addr), parent:sub_unit
|vpiName:stage2_addr
|vpiDirection:1
|vpiIODecl:
\_io_decl: (new_request), parent:sub_unit
|vpiName:new_request
|vpiDirection:1
|vpiIODecl:
\_io_decl: (flush), parent:sub_unit
|vpiName:flush
|vpiDirection:1
|vpiIODecl:
\_io_decl: (data_out), parent:sub_unit
|vpiName:data_out
|vpiDirection:2
|vpiIODecl:
\_io_decl: (data_valid), parent:sub_unit
|vpiName:data_valid
|vpiDirection:2
|vpiIODecl:
\_io_decl: (ready), parent:sub_unit
|vpiName:ready
|vpiDirection:2
|vpiInterface:
\_interface: work@fetch_sub_unit_interface (fetch_sub7), file:third_party/cores/taiga/core/fetch.sv, line:65, parent:fetch_block
|vpiNet:
\_logic_net: (stage1_addr), line:228, parent:fetch_sub7
|vpiName:stage1_addr
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.fetch_sub7.stage1_addr
|vpiNetType:36
|vpiRange:
\_range: , line:228
|vpiLeftRange:
\_constant: , line:228
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:228
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (stage2_addr), line:229, parent:fetch_sub7
|vpiName:stage2_addr
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.fetch_sub7.stage2_addr
|vpiNetType:36
|vpiRange:
\_range: , line:229
|vpiLeftRange:
\_constant: , line:229
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:229
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (data_out), line:231, parent:fetch_sub7
|vpiName:data_out
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.fetch_sub7.data_out
|vpiNetType:36
|vpiRange:
\_range: , line:231
|vpiLeftRange:
\_constant: , line:231
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:231
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (data_valid), line:232, parent:fetch_sub7
|vpiName:data_valid
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.fetch_sub7.data_valid
|vpiNetType:36
|vpiNet:
\_logic_net: (ready), line:233, parent:fetch_sub7
|vpiName:ready
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.fetch_sub7.ready
|vpiNetType:36
|vpiNet:
\_logic_net: (new_request), line:234, parent:fetch_sub7
|vpiName:new_request
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.fetch_sub7.new_request
|vpiNetType:36
|vpiNet:
\_logic_net: (flush), line:235, parent:fetch_sub7
|vpiName:flush
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.fetch_sub7.flush
|vpiNetType:36
|vpiInstance:
\_module: work@fetch (fetch_block), file:third_party/cores/taiga/core/taiga.sv, line:160, parent:cpu
|vpiInterface:
\_interface: work@fetch_sub_unit_interface (fetch_sub8), file:third_party/cores/taiga/core/fetch.sv, line:65, parent:fetch_block
|vpiDefName:work@fetch_sub_unit_interface
|vpiName:fetch_sub8
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.fetch_sub8
|vpiModport:
\_modport: (fetch), parent:fetch_sub8
|vpiName:fetch
|vpiIODecl:
\_io_decl: (stage1_addr), parent:fetch
|vpiName:stage1_addr
|vpiDirection:2
|vpiIODecl:
\_io_decl: (stage2_addr), parent:fetch
|vpiName:stage2_addr
|vpiDirection:2
|vpiIODecl:
\_io_decl: (new_request), parent:fetch
|vpiName:new_request
|vpiDirection:2
|vpiIODecl:
\_io_decl: (flush), parent:fetch
|vpiName:flush
|vpiDirection:2
|vpiIODecl:
\_io_decl: (data_out), parent:fetch
|vpiName:data_out
|vpiDirection:1
|vpiIODecl:
\_io_decl: (data_valid), parent:fetch
|vpiName:data_valid
|vpiDirection:1
|vpiIODecl:
\_io_decl: (ready), parent:fetch
|vpiName:ready
|vpiDirection:1
|vpiInterface:
\_interface: work@fetch_sub_unit_interface (fetch_sub8), file:third_party/cores/taiga/core/fetch.sv, line:65, parent:fetch_block
|vpiModport:
\_modport: (sub_unit), parent:fetch_sub8
|vpiName:sub_unit
|vpiIODecl:
\_io_decl: (stage1_addr), parent:sub_unit
|vpiName:stage1_addr
|vpiDirection:1
|vpiIODecl:
\_io_decl: (stage2_addr), parent:sub_unit
|vpiName:stage2_addr
|vpiDirection:1
|vpiIODecl:
\_io_decl: (new_request), parent:sub_unit
|vpiName:new_request
|vpiDirection:1
|vpiIODecl:
\_io_decl: (flush), parent:sub_unit
|vpiName:flush
|vpiDirection:1
|vpiIODecl:
\_io_decl: (data_out), parent:sub_unit
|vpiName:data_out
|vpiDirection:2
|vpiIODecl:
\_io_decl: (data_valid), parent:sub_unit
|vpiName:data_valid
|vpiDirection:2
|vpiIODecl:
\_io_decl: (ready), parent:sub_unit
|vpiName:ready
|vpiDirection:2
|vpiInterface:
\_interface: work@fetch_sub_unit_interface (fetch_sub8), file:third_party/cores/taiga/core/fetch.sv, line:65, parent:fetch_block
|vpiNet:
\_logic_net: (stage1_addr), line:228, parent:fetch_sub8
|vpiName:stage1_addr
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.fetch_sub8.stage1_addr
|vpiNetType:36
|vpiRange:
\_range: , line:228
|vpiLeftRange:
\_constant: , line:228
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:228
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (stage2_addr), line:229, parent:fetch_sub8
|vpiName:stage2_addr
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.fetch_sub8.stage2_addr
|vpiNetType:36
|vpiRange:
\_range: , line:229
|vpiLeftRange:
\_constant: , line:229
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:229
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (data_out), line:231, parent:fetch_sub8
|vpiName:data_out
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.fetch_sub8.data_out
|vpiNetType:36
|vpiRange:
\_range: , line:231
|vpiLeftRange:
\_constant: , line:231
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:231
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (data_valid), line:232, parent:fetch_sub8
|vpiName:data_valid
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.fetch_sub8.data_valid
|vpiNetType:36
|vpiNet:
\_logic_net: (ready), line:233, parent:fetch_sub8
|vpiName:ready
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.fetch_sub8.ready
|vpiNetType:36
|vpiNet:
\_logic_net: (new_request), line:234, parent:fetch_sub8
|vpiName:new_request
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.fetch_sub8.new_request
|vpiNetType:36
|vpiNet:
\_logic_net: (flush), line:235, parent:fetch_sub8
|vpiName:flush
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.fetch_sub8.flush
|vpiNetType:36
|vpiInstance:
\_module: work@fetch (fetch_block), file:third_party/cores/taiga/core/taiga.sv, line:160, parent:cpu
|vpiInterface:
\_interface: work@fifo_interface (next_unit), file:third_party/cores/taiga/core/fetch.sv, line:81, parent:fetch_block
|vpiDefName:work@fifo_interface
|vpiName:next_unit
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.next_unit
|vpiModport:
\_modport: (dequeue), parent:next_unit
|vpiName:dequeue
|vpiIODecl:
\_io_decl: (valid), parent:dequeue
|vpiName:valid
|vpiDirection:1
|vpiIODecl:
\_io_decl: (data_out), parent:dequeue
|vpiName:data_out
|vpiDirection:1
|vpiIODecl:
\_io_decl: (pop), parent:dequeue
|vpiName:pop
|vpiDirection:2
|vpiInterface:
\_interface: work@fifo_interface (next_unit), file:third_party/cores/taiga/core/fetch.sv, line:81, parent:fetch_block
|vpiModport:
\_modport: (enqueue), parent:next_unit
|vpiName:enqueue
|vpiIODecl:
\_io_decl: (full), parent:enqueue
|vpiName:full
|vpiDirection:1
|vpiIODecl:
\_io_decl: (data_in), parent:enqueue
|vpiName:data_in
|vpiDirection:2
|vpiIODecl:
\_io_decl: (push), parent:enqueue
|vpiName:push
|vpiDirection:2
|vpiIODecl:
\_io_decl: (supress_push), parent:enqueue
|vpiName:supress_push
|vpiDirection:2
|vpiInterface:
\_interface: work@fifo_interface (next_unit), file:third_party/cores/taiga/core/fetch.sv, line:81, parent:fetch_block
|vpiModport:
\_modport: (structure), parent:next_unit
|vpiName:structure
|vpiIODecl:
\_io_decl: (push), parent:structure
|vpiName:push
|vpiDirection:1
|vpiIODecl:
\_io_decl: (pop), parent:structure
|vpiName:pop
|vpiDirection:1
|vpiIODecl:
\_io_decl: (data_in), parent:structure
|vpiName:data_in
|vpiDirection:1
|vpiIODecl:
\_io_decl: (supress_push), parent:structure
|vpiName:supress_push
|vpiDirection:1
|vpiIODecl:
\_io_decl: (data_out), parent:structure
|vpiName:data_out
|vpiDirection:2
|vpiIODecl:
\_io_decl: (valid), parent:structure
|vpiName:valid
|vpiDirection:2
|vpiIODecl:
\_io_decl: (full), parent:structure
|vpiName:full
|vpiDirection:2
|vpiInterface:
\_interface: work@fifo_interface (next_unit), file:third_party/cores/taiga/core/fetch.sv, line:81, parent:fetch_block
|vpiNet:
\_logic_net: (push), line:158, parent:next_unit
|vpiName:push
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.next_unit.push
|vpiNetType:36
|vpiNet:
\_logic_net: (pop), line:159, parent:next_unit
|vpiName:pop
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.next_unit.pop
|vpiNetType:36
|vpiNet:
\_logic_net: (data_in), line:160, parent:next_unit
|vpiName:data_in
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.next_unit.data_in
|vpiNetType:36
|vpiRange:
\_range: , line:160
|vpiLeftRange:
\_constant: , line:160
|vpiConstType:7
|vpiDecompile:18446744073709551615
|vpiSize:32
|INT:-1
|vpiRightRange:
\_constant: , line:160
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (data_out), line:161, parent:next_unit
|vpiName:data_out
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.next_unit.data_out
|vpiNetType:36
|vpiRange:
\_range: , line:161
|vpiLeftRange:
\_constant: , line:161
|vpiConstType:7
|vpiDecompile:18446744073709551615
|vpiSize:32
|INT:-1
|vpiRightRange:
\_constant: , line:161
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (valid), line:162, parent:next_unit
|vpiName:valid
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.next_unit.valid
|vpiNetType:36
|vpiNet:
\_logic_net: (full), line:163, parent:next_unit
|vpiName:full
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.next_unit.full
|vpiNetType:36
|vpiNet:
\_logic_net: (supress_push), line:164, parent:next_unit
|vpiName:supress_push
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.next_unit.supress_push
|vpiNetType:36
|vpiNet:
\_logic_net: (push), line:158, parent:next_unit
|vpiName:push
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.next_unit.push
|vpiNetType:36
|vpiNet:
\_logic_net: (pop), line:159, parent:next_unit
|vpiName:pop
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.next_unit.pop
|vpiNetType:36
|vpiNet:
\_logic_net: (data_in), line:160, parent:next_unit
|vpiName:data_in
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.next_unit.data_in
|vpiNetType:36
|vpiRange:
\_range: , line:160
|vpiLeftRange:
\_constant: , line:160
|vpiConstType:7
|vpiDecompile:18446744073709551615
|vpiSize:32
|INT:-1
|vpiRightRange:
\_constant: , line:160
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (data_out), line:161, parent:next_unit
|vpiName:data_out
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.next_unit.data_out
|vpiNetType:36
|vpiRange:
\_range: , line:161
|vpiLeftRange:
\_constant: , line:161
|vpiConstType:7
|vpiDecompile:18446744073709551615
|vpiSize:32
|INT:-1
|vpiRightRange:
\_constant: , line:161
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (valid), line:162, parent:next_unit
|vpiName:valid
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.next_unit.valid
|vpiNetType:36
|vpiNet:
\_logic_net: (full), line:163, parent:next_unit
|vpiName:full
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.next_unit.full
|vpiNetType:36
|vpiNet:
\_logic_net: (supress_push), line:164, parent:next_unit
|vpiName:supress_push
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.next_unit.supress_push
|vpiNetType:36
|vpiInstance:
\_module: work@fetch (fetch_block), file:third_party/cores/taiga/core/taiga.sv, line:160, parent:cpu
|vpiModule:
\_module: work@one_hot_to_integer (hit_way_conv), file:third_party/cores/taiga/core/fetch.sv, line:147, parent:fetch_block
|vpiDefName:work@one_hot_to_integer
|vpiName:hit_way_conv
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.hit_way_conv
|vpiPort:
\_port: (clk), line:31, parent:hit_way_conv
|vpiName:clk
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (clk), line:147
|vpiName:clk
|vpiActual:
\_logic_net: (clk), line:27, parent:fetch_block
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (clk), line:31, parent:hit_way_conv
|vpiName:clk
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.hit_way_conv.clk
|vpiNetType:36
|vpiPort:
\_port: (rst), line:32, parent:hit_way_conv
|vpiName:rst
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (rst), line:147
|vpiName:rst
|vpiActual:
\_logic_net: (rst), line:28, parent:fetch_block
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (rst), line:32, parent:hit_way_conv
|vpiName:rst
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.hit_way_conv.rst
|vpiNetType:36
|vpiPort:
\_port: (one_hot), line:33, parent:hit_way_conv
|vpiName:one_hot
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (one_hot), line:147
|vpiName:one_hot
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (one_hot), line:33, parent:hit_way_conv
|vpiName:one_hot
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.hit_way_conv.one_hot
|vpiNetType:36
|vpiRange:
\_range: , line:33
|vpiLeftRange:
\_constant: , line:33
|vpiConstType:7
|vpiDecompile:8
|vpiSize:32
|INT:8
|vpiRightRange:
\_constant: , line:33
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiPort:
\_port: (int_out), line:34, parent:hit_way_conv
|vpiName:int_out
|vpiDirection:2
|vpiHighConn:
\_ref_obj: (int_out), line:147
|vpiName:int_out
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (int_out), line:34, parent:hit_way_conv
|vpiName:int_out
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.hit_way_conv.int_out
|vpiNetType:36
|vpiRange:
\_range: , line:34
|vpiLeftRange:
\_constant: , line:34
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiRightRange:
\_constant: , line:34
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiGenScopeArray:
\_gen_scope_array: (genblk1), line:40, parent:hit_way_conv
|vpiName:genblk1
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.hit_way_conv.genblk1
|vpiGenScope:
\_gen_scope: , parent:genblk1
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.hit_way_conv.genblk1
|vpiProcess:
\_always: , line:41
|vpiAlwaysType:2
|vpiStmt:
\_begin: , line:41
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.hit_way_conv.genblk1
|vpiStmt:
\_assignment: , line:42
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (int_out), line:42
|vpiName:int_out
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.hit_way_conv.genblk1.int_out
|vpiRhs:
\_constant: , line:42
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiStmt:
\_foreach_stmt: , line:43
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.hit_way_conv.genblk1
|vpiVariables:
\_chandle_var: (one_hot), line:43
|vpiName:one_hot
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.hit_way_conv.genblk1.one_hot
|vpiLoopVars:
\_chandle_var: (i), line:43
|vpiName:i
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.hit_way_conv.genblk1.i
|vpiStmt:
\_if_stmt: , line:44
|vpiCondition:
\_bit_select: (one_hot), line:44
|vpiName:one_hot
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.hit_way_conv.genblk1.one_hot
|vpiIndex:
\_ref_obj: (i), line:44
|vpiName:i
|vpiStmt:
\_assignment: , line:44
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (int_out), line:44
|vpiName:int_out
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.hit_way_conv.genblk1.int_out
|vpiRhs:
\_part_select: , line:44, parent:i
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (i)
|vpiLeftRange:
\_operation: , line:44
|vpiOpType:11
|vpiOperand:
\_sys_func_call: ($clog2), line:44
|vpiName:$clog2
|vpiArgument:
\_ref_obj: (C_WIDTH), line:44
|vpiName:C_WIDTH
|vpiOperand:
\_constant: , line:44
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:44
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (clk), line:31, parent:hit_way_conv
|vpiNet:
\_logic_net: (rst), line:32, parent:hit_way_conv
|vpiNet:
\_logic_net: (one_hot), line:33, parent:hit_way_conv
|vpiNet:
\_logic_net: (int_out), line:34, parent:hit_way_conv
|vpiInstance:
\_module: work@fetch (fetch_block), file:third_party/cores/taiga/core/taiga.sv, line:160, parent:cpu
|vpiParameter:
\_parameter: (C_WIDTH), line:147
|vpiName:C_WIDTH
|INT:9
|vpiModule:
\_module: work@taiga_fifo (attributes_fifo), file:third_party/cores/taiga/core/fetch.sv, line:148, parent:fetch_block
|vpiDefName:work@taiga_fifo
|vpiName:attributes_fifo
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.attributes_fifo
|vpiPort:
\_port: (fifo), line:33, parent:attributes_fifo
|vpiName:fifo
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (next_unit), line:149
|vpiName:next_unit
|vpiActual:
\_interface: work@fifo_interface (next_unit), file:third_party/cores/taiga/core/fetch.sv, line:81
|vpiDefName:work@fifo_interface
|vpiName:next_unit
|vpiModport:
\_modport: (dequeue)
|vpiName:dequeue
|vpiIODecl:
\_io_decl: (valid)
|vpiName:valid
|vpiDirection:1
|vpiIODecl:
\_io_decl: (data_out)
|vpiName:data_out
|vpiDirection:1
|vpiIODecl:
\_io_decl: (pop)
|vpiName:pop
|vpiDirection:2
|vpiInterface:
\_interface: work@fifo_interface (next_unit), file:third_party/cores/taiga/core/fetch.sv, line:81
|vpiModport:
\_modport: (enqueue)
|vpiName:enqueue
|vpiIODecl:
\_io_decl: (full)
|vpiName:full
|vpiDirection:1
|vpiIODecl:
\_io_decl: (data_in)
|vpiName:data_in
|vpiDirection:2
|vpiIODecl:
\_io_decl: (push)
|vpiName:push
|vpiDirection:2
|vpiIODecl:
\_io_decl: (supress_push)
|vpiName:supress_push
|vpiDirection:2
|vpiInterface:
\_interface: work@fifo_interface (next_unit), file:third_party/cores/taiga/core/fetch.sv, line:81
|vpiModport:
\_modport: (structure)
|vpiName:structure
|vpiIODecl:
\_io_decl: (push)
|vpiName:push
|vpiDirection:1
|vpiIODecl:
\_io_decl: (pop)
|vpiName:pop
|vpiDirection:1
|vpiIODecl:
\_io_decl: (data_in)
|vpiName:data_in
|vpiDirection:1
|vpiIODecl:
\_io_decl: (supress_push)
|vpiName:supress_push
|vpiDirection:1
|vpiIODecl:
\_io_decl: (data_out)
|vpiName:data_out
|vpiDirection:2
|vpiIODecl:
\_io_decl: (valid)
|vpiName:valid
|vpiDirection:2
|vpiIODecl:
\_io_decl: (full)
|vpiName:full
|vpiDirection:2
|vpiInterface:
\_interface: work@fifo_interface (next_unit), file:third_party/cores/taiga/core/fetch.sv, line:81
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_interface: work@fifo_interface (fifo), file:third_party/cores/taiga/core/fetch.sv, line:148
|vpiDefName:work@fifo_interface
|vpiName:fifo
|vpiModport:
\_modport: (dequeue)
|vpiName:dequeue
|vpiIODecl:
\_io_decl: (valid)
|vpiName:valid
|vpiDirection:1
|vpiExpr:
\_logic_net: (valid), line:162
|vpiName:valid
|vpiNetType:36
|vpiIODecl:
\_io_decl: (data_out)
|vpiName:data_out
|vpiDirection:1
|vpiExpr:
\_logic_net: (data_out), line:161
|vpiName:data_out
|vpiNetType:36
|vpiRange:
\_range: , line:161
|vpiLeftRange:
\_constant: , line:161
|vpiConstType:7
|vpiDecompile:18446744073709551615
|vpiSize:32
|INT:-1
|vpiRightRange:
\_constant: , line:161
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (pop)
|vpiName:pop
|vpiDirection:2
|vpiExpr:
\_logic_net: (pop), line:159
|vpiName:pop
|vpiNetType:36
|vpiInterface:
\_interface: work@fifo_interface (fifo), file:third_party/cores/taiga/core/fetch.sv, line:148
|vpiModport:
\_modport: (enqueue)
|vpiName:enqueue
|vpiIODecl:
\_io_decl: (full)
|vpiName:full
|vpiDirection:1
|vpiExpr:
\_logic_net: (full), line:163
|vpiName:full
|vpiNetType:36
|vpiIODecl:
\_io_decl: (data_in)
|vpiName:data_in
|vpiDirection:2
|vpiExpr:
\_logic_net: (data_in), line:160
|vpiName:data_in
|vpiNetType:36
|vpiRange:
\_range: , line:160
|vpiLeftRange:
\_constant: , line:160
|vpiConstType:7
|vpiDecompile:18446744073709551615
|vpiSize:32
|INT:-1
|vpiRightRange:
\_constant: , line:160
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (push)
|vpiName:push
|vpiDirection:2
|vpiExpr:
\_logic_net: (push), line:158
|vpiName:push
|vpiNetType:36
|vpiIODecl:
\_io_decl: (supress_push)
|vpiName:supress_push
|vpiDirection:2
|vpiExpr:
\_logic_net: (supress_push), line:164
|vpiName:supress_push
|vpiNetType:36
|vpiInterface:
\_interface: work@fifo_interface (fifo), file:third_party/cores/taiga/core/fetch.sv, line:148
|vpiModport:
\_modport: (structure)
|vpiName:structure
|vpiIODecl:
\_io_decl: (push)
|vpiName:push
|vpiDirection:1
|vpiExpr:
\_logic_net: (push), line:158
|vpiIODecl:
\_io_decl: (pop)
|vpiName:pop
|vpiDirection:1
|vpiExpr:
\_logic_net: (pop), line:159
|vpiIODecl:
\_io_decl: (data_in)
|vpiName:data_in
|vpiDirection:1
|vpiExpr:
\_logic_net: (data_in), line:160
|vpiIODecl:
\_io_decl: (supress_push)
|vpiName:supress_push
|vpiDirection:1
|vpiExpr:
\_logic_net: (supress_push), line:164
|vpiIODecl:
\_io_decl: (data_out)
|vpiName:data_out
|vpiDirection:2
|vpiExpr:
\_logic_net: (data_out), line:161
|vpiIODecl:
\_io_decl: (valid)
|vpiName:valid
|vpiDirection:2
|vpiExpr:
\_logic_net: (valid), line:162
|vpiIODecl:
\_io_decl: (full)
|vpiName:full
|vpiDirection:2
|vpiExpr:
\_logic_net: (full), line:163
|vpiInterface:
\_interface: work@fifo_interface (fifo), file:third_party/cores/taiga/core/fetch.sv, line:148
|vpiPort:
\_port: (rst), line:34, parent:attributes_fifo
|vpiName:rst
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (flush_or_rst), line:149
|vpiName:flush_or_rst
|vpiActual:
\_logic_net: (flush_or_rst), line:79, parent:fetch_block
|vpiName:flush_or_rst
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.flush_or_rst
|vpiNetType:36
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (rst), line:34, parent:attributes_fifo
|vpiName:rst
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.attributes_fifo.rst
|vpiNetType:36
|vpiPort:
\_port: (clk), line:35, parent:attributes_fifo
|vpiName:clk
|vpiDirection:5
|vpiHighConn:
\_ref_obj: (clk), line:149
|vpiName:clk
|vpiActual:
\_logic_net: (clk), line:27, parent:fetch_block
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_modport: (structure)
|vpiName:structure
|vpiIODecl:
\_io_decl: (push)
|vpiName:push
|vpiDirection:1
|vpiExpr:
\_logic_net: (push), line:158
|vpiIODecl:
\_io_decl: (pop)
|vpiName:pop
|vpiDirection:1
|vpiExpr:
\_logic_net: (pop), line:159
|vpiIODecl:
\_io_decl: (data_in)
|vpiName:data_in
|vpiDirection:1
|vpiExpr:
\_logic_net: (data_in), line:160
|vpiIODecl:
\_io_decl: (supress_push)
|vpiName:supress_push
|vpiDirection:1
|vpiExpr:
\_logic_net: (supress_push), line:164
|vpiIODecl:
\_io_decl: (data_out)
|vpiName:data_out
|vpiDirection:2
|vpiExpr:
\_logic_net: (data_out), line:161
|vpiIODecl:
\_io_decl: (valid)
|vpiName:valid
|vpiDirection:2
|vpiExpr:
\_logic_net: (valid), line:162
|vpiIODecl:
\_io_decl: (full)
|vpiName:full
|vpiDirection:2
|vpiExpr:
\_logic_net: (full), line:163
|vpiInterface:
\_interface: work@fifo_interface (fifo), file:third_party/cores/taiga/core/fetch.sv, line:148
|vpiDefName:work@fifo_interface
|vpiName:fifo
|vpiModport:
\_modport: (dequeue)
|vpiName:dequeue
|vpiIODecl:
\_io_decl: (valid)
|vpiName:valid
|vpiDirection:1
|vpiExpr:
\_logic_net: (valid), line:162
|vpiIODecl:
\_io_decl: (data_out)
|vpiName:data_out
|vpiDirection:1
|vpiExpr:
\_logic_net: (data_out), line:161
|vpiIODecl:
\_io_decl: (pop)
|vpiName:pop
|vpiDirection:2
|vpiExpr:
\_logic_net: (pop), line:159
|vpiInterface:
\_interface: work@fifo_interface (fifo), file:third_party/cores/taiga/core/fetch.sv, line:148
|vpiModport:
\_modport: (enqueue)
|vpiName:enqueue
|vpiIODecl:
\_io_decl: (full)
|vpiName:full
|vpiDirection:1
|vpiExpr:
\_logic_net: (full), line:163
|vpiIODecl:
\_io_decl: (data_in)
|vpiName:data_in
|vpiDirection:2
|vpiExpr:
\_logic_net: (data_in), line:160
|vpiIODecl:
\_io_decl: (push)
|vpiName:push
|vpiDirection:2
|vpiExpr:
\_logic_net: (push), line:158
|vpiIODecl:
\_io_decl: (supress_push)
|vpiName:supress_push
|vpiDirection:2
|vpiExpr:
\_logic_net: (supress_push), line:164
|vpiInterface:
\_interface: work@fifo_interface (fifo), file:third_party/cores/taiga/core/fetch.sv, line:148
|vpiModport:
\_modport: (structure)
|vpiPort:
\_port: (rst), parent:attributes_fifo
|vpiName:rst
|vpiHighConn:
\_ref_obj: (rst), line:149
|vpiName:rst
|vpiActual:
\_logic_net: (rst), line:28, parent:fetch_block
|vpiPort:
\_port: (fifo), parent:attributes_fifo
|vpiName:fifo
|vpiHighConn:
\_ref_obj: (fifo), line:149
|vpiName:fifo
|vpiGenScopeArray:
\_gen_scope_array: (genblk1), line:65, parent:attributes_fifo
|vpiName:genblk1
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.attributes_fifo.genblk1
|vpiGenScope:
\_gen_scope: , parent:genblk1
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.attributes_fifo.genblk1
|vpiProcess:
\_always: , line:68
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:68
|vpiCondition:
\_operation: , line:68
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:68
|vpiName:clk
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.attributes_fifo.genblk1.clk
|vpiStmt:
\_begin: , line:68
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.attributes_fifo.genblk1
|vpiStmt:
\_if_else: , line:69
|vpiCondition:
\_ref_obj: (rst), line:69
|vpiName:rst
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.attributes_fifo.genblk1.rst
|vpiStmt:
\_assignment: , line:70
|vpiOpType:82
|vpiLhs:
\_ref_obj: (inflight_count), line:70
|vpiName:inflight_count
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.attributes_fifo.genblk1.inflight_count
|vpiRhs:
\_constant: , line:70
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiElseStmt:
\_assignment: , line:72
|vpiOpType:82
|vpiLhs:
\_ref_obj: (inflight_count), line:72
|vpiName:inflight_count
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.attributes_fifo.genblk1.inflight_count
|vpiRhs:
\_operation: , line:72
|vpiOpType:11
|vpiOperand:
\_operation: , line:72
|vpiOpType:24
|vpiOperand:
\_ref_obj: (inflight_count), line:72
|vpiName:inflight_count
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.attributes_fifo.genblk1.inflight_count
|vpiOperand:
\_operation: , line:72
|vpiOpType:67
|vpiOperand:
\_ref_obj: (fifo.pop), line:72
|vpiName:fifo.pop
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.attributes_fifo.genblk1.fifo.pop
|vpiOperand:
\_operation: , line:72
|vpiOpType:67
|vpiOperand:
\_ref_obj: (supressed_push), line:72
|vpiName:supressed_push
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.attributes_fifo.genblk1.supressed_push
|vpiProcess:
\_always: , line:78
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:78
|vpiCondition:
\_operation: , line:78
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:78
|vpiName:clk
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.attributes_fifo.genblk1.clk
|vpiStmt:
\_begin: , line:78
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.attributes_fifo.genblk1
|vpiStmt:
\_if_else: , line:79
|vpiCondition:
\_ref_obj: (rst), line:79
|vpiName:rst
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.attributes_fifo.genblk1.rst
|vpiStmt:
\_begin: , line:79
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.attributes_fifo.genblk1
|vpiStmt:
\_assignment: , line:80
|vpiOpType:82
|vpiLhs:
\_ref_obj: (read_index), line:80
|vpiName:read_index
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.attributes_fifo.genblk1.read_index
|vpiRhs:
\_constant: , line:80
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiStmt:
\_assignment: , line:81
|vpiOpType:82
|vpiLhs:
\_ref_obj: (write_index), line:81
|vpiName:write_index
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.attributes_fifo.genblk1.write_index
|vpiRhs:
\_constant: , line:81
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiElseStmt:
\_begin: , line:83
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.attributes_fifo.genblk1
|vpiStmt:
\_assignment: , line:84
|vpiOpType:82
|vpiLhs:
\_ref_obj: (read_index), line:84
|vpiName:read_index
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.attributes_fifo.genblk1.read_index
|vpiRhs:
\_operation: , line:84
|vpiOpType:24
|vpiOperand:
\_ref_obj: (read_index), line:84
|vpiName:read_index
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.attributes_fifo.genblk1.read_index
|vpiOperand:
\_operation: , line:84
|vpiOpType:67
|vpiOperand:
\_ref_obj: (fifo.pop), line:84
|vpiName:fifo.pop
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.attributes_fifo.genblk1.fifo.pop
|vpiTypespec:
\_void_typespec: (LOG2_FIFO_DEPTH), line:84
|vpiName:LOG2_FIFO_DEPTH
|vpiStmt:
\_assignment: , line:85
|vpiOpType:82
|vpiLhs:
\_ref_obj: (write_index), line:85
|vpiName:write_index
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.attributes_fifo.genblk1.write_index
|vpiRhs:
\_operation: , line:85
|vpiOpType:24
|vpiOperand:
\_ref_obj: (write_index), line:85
|vpiName:write_index
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.attributes_fifo.genblk1.write_index
|vpiOperand:
\_operation: , line:85
|vpiOpType:67
|vpiOperand:
\_ref_obj: (supressed_push), line:85
|vpiName:supressed_push
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.attributes_fifo.genblk1.supressed_push
|vpiTypespec:
\_void_typespec: (LOG2_FIFO_DEPTH), line:85
|vpiName:LOG2_FIFO_DEPTH
|vpiProcess:
\_always: , line:89
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:89
|vpiCondition:
\_operation: , line:89
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:89
|vpiName:clk
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.attributes_fifo.genblk1.clk
|vpiStmt:
\_begin: , line:89
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.attributes_fifo.genblk1
|vpiStmt:
\_if_stmt: , line:90
|vpiCondition:
\_ref_obj: (fifo.push), line:90
|vpiName:fifo.push
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.attributes_fifo.genblk1.fifo.push
|vpiStmt:
\_assignment: , line:91
|vpiOpType:82
|vpiLhs:
\_bit_select: (lut_ram), line:91
|vpiName:lut_ram
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.attributes_fifo.genblk1.lut_ram
|vpiIndex:
\_ref_obj: (write_index), line:91
|vpiName:write_index
|vpiRhs:
\_ref_obj: (fifo.data_in), line:91
|vpiName:fifo.data_in
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.attributes_fifo.genblk1.fifo.data_in
|vpiContAssign:
\_cont_assign: , line:75
|vpiRhs:
\_bit_select: (inflight_count), line:75
|vpiName:inflight_count
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.attributes_fifo.genblk1.inflight_count
|vpiIndex:
\_ref_obj: (LOG2_FIFO_DEPTH), line:75
|vpiName:LOG2_FIFO_DEPTH
|vpiLhs:
\_ref_obj: (fifo.valid), line:75
|vpiName:fifo.valid
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.attributes_fifo.genblk1.fifo.valid
|vpiContAssign:
\_cont_assign: , line:76
|vpiRhs:
\_operation: , line:76
|vpiOpType:28
|vpiOperand:
\_ref_obj: (fifo.valid), line:76
|vpiName:fifo.valid
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.attributes_fifo.genblk1.fifo.valid
|vpiOperand:
\_operation: , line:76
|vpiOpType:8
|vpiOperand:
\_part_select: , line:76, parent:inflight_count
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (inflight_count)
|vpiLeftRange:
\_operation: , line:76
|vpiOpType:11
|vpiOperand:
\_ref_obj: (LOG2_FIFO_DEPTH), line:76
|vpiName:LOG2_FIFO_DEPTH
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.attributes_fifo.genblk1.LOG2_FIFO_DEPTH
|vpiOperand:
\_constant: , line:76
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:76
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiLhs:
\_ref_obj: (fifo.full), line:76
|vpiName:fifo.full
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.attributes_fifo.genblk1.fifo.full
|vpiContAssign:
\_cont_assign: , line:93
|vpiRhs:
\_bit_select: (lut_ram), line:93
|vpiName:lut_ram
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.attributes_fifo.genblk1.lut_ram
|vpiIndex:
\_ref_obj: (read_index), line:93
|vpiName:read_index
|vpiLhs:
\_ref_obj: (fifo.data_out), line:93
|vpiName:fifo.data_out
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.attributes_fifo.genblk1.fifo.data_out
|vpiParameter:
\_parameter: (ALU_UNIT_WB_ID), line:190
|vpiName:ALU_UNIT_WB_ID
|INT:32
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (BRANCH_PREDICTOR_WAYS), line:159
|vpiName:BRANCH_PREDICTOR_WAYS
|INT:9
|vpiParameter:
\_parameter: (BRANCH_TABLE_ENTRIES), line:160
|vpiName:BRANCH_TABLE_ENTRIES
|INT:4
|vpiParameter:
\_parameter: (BRANCH_UNIT_ID), line:195
|vpiName:BRANCH_UNIT_ID
|INT:8
|vpiParameter:
\_parameter: (BUS_ADDR_H), line:107
|vpiName:BUS_ADDR_H
|INT:1
|vpiParameter:
\_parameter: (BUS_ADDR_L), line:106
|vpiName:BUS_ADDR_L
|INT:0
|vpiParameter:
\_parameter: (BUS_BIT_CHECK), line:108
|vpiName:BUS_BIT_CHECK
|INT:1
|vpiParameter:
\_parameter: (BUS_TYPE), line:89
|vpiName:BUS_TYPE
|INT:5
|vpiParameter:
\_parameter: (COUNTER_W), line:42
|vpiName:COUNTER_W
|INT:33
|vpiParameter:
\_parameter: (CPU_ID), line:38
|vpiName:CPU_ID
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_ADDR_WIDTH), line:113
|vpiName:C_M_AXI_ADDR_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_DATA_WIDTH), line:114
|vpiName:C_M_AXI_DATA_WIDTH
|INT:1
|vpiParameter:
\_parameter: (DCACHE_LINES), line:133
|vpiName:DCACHE_LINES
|INT:-2146435073
|vpiParameter:
\_parameter: (DCACHE_LINE_ADDR_W), line:135
|vpiName:DCACHE_LINE_ADDR_W
|INT:1073741824
|vpiParameter:
\_parameter: (DCACHE_LINE_W), line:136
|vpiName:DCACHE_LINE_W
|INT:1342177279
|vpiParameter:
\_parameter: (DCACHE_SUB_LINE_ADDR_W), line:137
|vpiName:DCACHE_SUB_LINE_ADDR_W
|INT:4
|vpiParameter:
\_parameter: (DCACHE_TAG_W), line:138
|vpiName:DCACHE_TAG_W
|INT:1610612736
|vpiParameter:
\_parameter: (DCACHE_WAYS), line:134
|vpiName:DCACHE_WAYS
|INT:4
|vpiParameter:
\_parameter: (DIV_ALGORITHM), line:67
|vpiName:DIV_ALGORITHM
|INT:0
|vpiParameter:
\_parameter: (DIV_UNIT_WB_ID), line:192
|vpiName:DIV_UNIT_WB_ID
|INT:2
|vpiParameter:
\_parameter: (DTLB_DEPTH), line:152
|vpiName:DTLB_DEPTH
|INT:512
|vpiParameter:
\_parameter: (DTLB_WAYS), line:151
|vpiName:DTLB_WAYS
|INT:32
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (ENABLE_M_MODE), line:34
|vpiName:ENABLE_M_MODE
|INT:1
|vpiParameter:
\_parameter: (ENABLE_S_MODE), line:36
|vpiName:ENABLE_S_MODE
|INT:0
|vpiParameter:
\_parameter: (ENABLE_TRACE_INTERFACE), line:172
|vpiName:ENABLE_TRACE_INTERFACE
|INT:2
|vpiParameter:
\_parameter: (FETCH_BUFFER_DEPTH), line:168
|vpiName:FETCH_BUFFER_DEPTH
|INT:512
|vpiParameter:
\_parameter: (FPGA_VENDOR), line:27
|vpiName:FPGA_VENDOR
|STRING:"xilinx"
|vpiParameter:
\_parameter: (GC_UNIT_ID), line:196
|vpiName:GC_UNIT_ID
|INT:4
|vpiParameter:
\_parameter: (ICACHE_LINES), line:121
|vpiName:ICACHE_LINES
|INT:2
|vpiParameter:
\_parameter: (ICACHE_LINE_ADDR_W), line:123
|vpiName:ICACHE_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_LINE_W), line:124
|vpiName:ICACHE_LINE_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_SUB_LINE_ADDR_W), line:125
|vpiName:ICACHE_SUB_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_TAG_W), line:126
|vpiName:ICACHE_TAG_W
|INT:-2147483648
|vpiParameter:
\_parameter: (ICACHE_WAYS), line:122
|vpiName:ICACHE_WAYS
|INT:1
|vpiParameter:
\_parameter: (ITLB_DEPTH), line:146
|vpiName:ITLB_DEPTH
|INT:32
|vpiParameter:
\_parameter: (ITLB_WAYS), line:145
|vpiName:ITLB_WAYS
|INT:4
|vpiParameter:
\_parameter: (L1_CONNECTIONS), line:177
|vpiName:L1_CONNECTIONS
|INT:9
|vpiParameter:
\_parameter: (L1_DCACHE_ID), line:178
|vpiName:L1_DCACHE_ID
|INT:4
|vpiParameter:
\_parameter: (L1_DMMU_ID), line:179
|vpiName:L1_DMMU_ID
|INT:2
|vpiParameter:
\_parameter: (L1_ICACHE_ID), line:180
|vpiName:L1_ICACHE_ID
|INT:19
|vpiParameter:
\_parameter: (L1_IMMU_ID), line:181
|vpiName:L1_IMMU_ID
|INT:0
|vpiParameter:
\_parameter: (LS_UNIT_WB_ID), line:191
|vpiName:LS_UNIT_WB_ID
|INT:1
|vpiParameter:
\_parameter: (MAX_INFLIGHT_COUNT), line:167
|vpiName:MAX_INFLIGHT_COUNT
|INT:19
|vpiParameter:
\_parameter: (MEMORY_ADDR_H), line:103
|vpiName:MEMORY_ADDR_H
|INT:12
|vpiParameter:
\_parameter: (MEMORY_ADDR_L), line:102
|vpiName:MEMORY_ADDR_L
|INT:11
|vpiParameter:
\_parameter: (MEMORY_BIT_CHECK), line:104
|vpiName:MEMORY_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (MUL_UNIT_WB_ID), line:193
|vpiName:MUL_UNIT_WB_ID
|INT:512
|vpiParameter:
\_parameter: (NUM_UNITS), line:188
|vpiName:NUM_UNITS
|INT:2
|vpiParameter:
\_parameter: (NUM_WB_UNITS), line:186
|vpiName:NUM_WB_UNITS
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (RAS_DEPTH), line:161
|vpiName:RAS_DEPTH
|INT:2
|vpiParameter:
\_parameter: (RESET_VEC), line:39
|vpiName:RESET_VEC
|INT:-2147483648
|vpiParameter:
\_parameter: (SCRATCH_ADDR_H), line:99
|vpiName:SCRATCH_ADDR_H
|INT:9
|vpiParameter:
\_parameter: (SCRATCH_ADDR_L), line:98
|vpiName:SCRATCH_ADDR_L
|INT:8
|vpiParameter:
\_parameter: (SCRATCH_BIT_CHECK), line:100
|vpiName:SCRATCH_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (USE_AMO), line:70
|vpiName:USE_AMO
|INT:1
|vpiParameter:
\_parameter: (USE_BRANCH_PREDICTOR), line:158
|vpiName:USE_BRANCH_PREDICTOR
|INT:2
|vpiParameter:
\_parameter: (USE_BUS), line:88
|vpiName:USE_BUS
|INT:4
|vpiParameter:
\_parameter: (USE_DCACHE), line:92
|vpiName:USE_DCACHE
|INT:6
|vpiParameter:
\_parameter: (USE_DIV), line:49
|vpiName:USE_DIV
|INT:1
|vpiParameter:
\_parameter: (USE_DTAG_INVALIDATIONS), line:140
|vpiName:USE_DTAG_INVALIDATIONS
|INT:1879048191
|vpiParameter:
\_parameter: (USE_D_SCRATCH_MEM), line:79
|vpiName:USE_D_SCRATCH_MEM
|INT:3
|vpiParameter:
\_parameter: (USE_ICACHE), line:93
|vpiName:USE_ICACHE
|INT:7
|vpiParameter:
\_parameter: (USE_I_SCRATCH_MEM), line:78
|vpiName:USE_I_SCRATCH_MEM
|INT:2
|vpiParameter:
\_parameter: (USE_MUL), line:48
|vpiName:USE_MUL
|INT:1
|vpiParameter:
\_parameter: (WB_UNITS_WIDTH), line:187
|vpiName:WB_UNITS_WIDTH
|INT:32
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiNet:
\_logic_net: (clk), line:33, parent:attributes_fifo
|vpiName:clk
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.attributes_fifo.clk
|vpiNetType:36
|vpiNet:
\_logic_net: (rst), line:34, parent:attributes_fifo
|vpiNet:
\_logic_net: (write_index), line:41, parent:attributes_fifo
|vpiName:write_index
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.attributes_fifo.write_index
|vpiNetType:36
|vpiRange:
\_range: , line:41
|vpiLeftRange:
\_constant: , line:41
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:41
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (read_index), line:42, parent:attributes_fifo
|vpiName:read_index
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.attributes_fifo.read_index
|vpiNetType:36
|vpiRange:
\_range: , line:42
|vpiLeftRange:
\_constant: , line:42
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:42
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (inflight_count), line:43, parent:attributes_fifo
|vpiName:inflight_count
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.attributes_fifo.inflight_count
|vpiNetType:36
|vpiRange:
\_range: , line:43
|vpiLeftRange:
\_constant: , line:43
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiRightRange:
\_constant: , line:43
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (supressed_push), line:44, parent:attributes_fifo
|vpiName:supressed_push
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.attributes_fifo.supressed_push
|vpiNetType:36
|vpiNet:
\_logic_net: (fifo), line:35, parent:attributes_fifo
|vpiName:fifo
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.attributes_fifo.fifo
|vpiInstance:
\_module: work@fetch (fetch_block), file:third_party/cores/taiga/core/taiga.sv, line:160, parent:cpu
|vpiArrayNet:
\_array_net: (lut_ram), line:40, parent:attributes_fifo
|vpiName:lut_ram
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.attributes_fifo.lut_ram
|vpiSize:2
|vpiNet:
\_logic_net: , parent:lut_ram
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.attributes_fifo.lut_ram
|vpiNetType:36
|vpiRange:
\_range: , line:40
|vpiLeftRange:
\_constant: , line:40
|vpiConstType:7
|vpiDecompile:18446744073709551615
|vpiSize:32
|INT:-1
|vpiRightRange:
\_constant: , line:40
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiRange:
\_range: , line:40
|vpiLeftRange:
\_constant: , line:40
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:40
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiParameter:
\_parameter: (ALU_UNIT_WB_ID), line:190
|vpiName:ALU_UNIT_WB_ID
|INT:32
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (BRANCH_PREDICTOR_WAYS), line:159
|vpiName:BRANCH_PREDICTOR_WAYS
|INT:9
|vpiParameter:
\_parameter: (BRANCH_TABLE_ENTRIES), line:160
|vpiName:BRANCH_TABLE_ENTRIES
|INT:4
|vpiParameter:
\_parameter: (BRANCH_UNIT_ID), line:195
|vpiName:BRANCH_UNIT_ID
|INT:8
|vpiParameter:
\_parameter: (BUS_ADDR_H), line:107
|vpiName:BUS_ADDR_H
|INT:1
|vpiParameter:
\_parameter: (BUS_ADDR_L), line:106
|vpiName:BUS_ADDR_L
|INT:0
|vpiParameter:
\_parameter: (BUS_BIT_CHECK), line:108
|vpiName:BUS_BIT_CHECK
|INT:1
|vpiParameter:
\_parameter: (BUS_TYPE), line:89
|vpiName:BUS_TYPE
|INT:5
|vpiParameter:
\_parameter: (COUNTER_W), line:42
|vpiName:COUNTER_W
|INT:33
|vpiParameter:
\_parameter: (CPU_ID), line:38
|vpiName:CPU_ID
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_ADDR_WIDTH), line:113
|vpiName:C_M_AXI_ADDR_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_DATA_WIDTH), line:114
|vpiName:C_M_AXI_DATA_WIDTH
|INT:1
|vpiParameter:
\_parameter: (DATA_WIDTH), line:148
|vpiName:DATA_WIDTH
|INT:0
|vpiParameter:
\_parameter: (DCACHE_LINES), line:133
|vpiName:DCACHE_LINES
|INT:-2146435073
|vpiParameter:
\_parameter: (DCACHE_LINE_ADDR_W), line:135
|vpiName:DCACHE_LINE_ADDR_W
|INT:1073741824
|vpiParameter:
\_parameter: (DCACHE_LINE_W), line:136
|vpiName:DCACHE_LINE_W
|INT:1342177279
|vpiParameter:
\_parameter: (DCACHE_SUB_LINE_ADDR_W), line:137
|vpiName:DCACHE_SUB_LINE_ADDR_W
|INT:4
|vpiParameter:
\_parameter: (DCACHE_TAG_W), line:138
|vpiName:DCACHE_TAG_W
|INT:1610612736
|vpiParameter:
\_parameter: (DCACHE_WAYS), line:134
|vpiName:DCACHE_WAYS
|INT:4
|vpiParameter:
\_parameter: (DIV_ALGORITHM), line:67
|vpiName:DIV_ALGORITHM
|INT:0
|vpiParameter:
\_parameter: (DIV_UNIT_WB_ID), line:192
|vpiName:DIV_UNIT_WB_ID
|INT:2
|vpiParameter:
\_parameter: (DTLB_DEPTH), line:152
|vpiName:DTLB_DEPTH
|INT:512
|vpiParameter:
\_parameter: (DTLB_WAYS), line:151
|vpiName:DTLB_WAYS
|INT:32
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (ENABLE_M_MODE), line:34
|vpiName:ENABLE_M_MODE
|INT:1
|vpiParameter:
\_parameter: (ENABLE_S_MODE), line:36
|vpiName:ENABLE_S_MODE
|INT:0
|vpiParameter:
\_parameter: (ENABLE_TRACE_INTERFACE), line:172
|vpiName:ENABLE_TRACE_INTERFACE
|INT:2
|vpiParameter:
\_parameter: (FETCH_BUFFER_DEPTH), line:168
|vpiName:FETCH_BUFFER_DEPTH
|INT:512
|vpiParameter:
\_parameter: (FIFO_DEPTH), line:148
|vpiName:FIFO_DEPTH
|INT:7
|vpiParameter:
\_parameter: (FPGA_VENDOR), line:27
|vpiName:FPGA_VENDOR
|STRING:"xilinx"
|vpiParameter:
\_parameter: (GC_UNIT_ID), line:196
|vpiName:GC_UNIT_ID
|INT:4
|vpiParameter:
\_parameter: (ICACHE_LINES), line:121
|vpiName:ICACHE_LINES
|INT:2
|vpiParameter:
\_parameter: (ICACHE_LINE_ADDR_W), line:123
|vpiName:ICACHE_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_LINE_W), line:124
|vpiName:ICACHE_LINE_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_SUB_LINE_ADDR_W), line:125
|vpiName:ICACHE_SUB_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_TAG_W), line:126
|vpiName:ICACHE_TAG_W
|INT:-2147483648
|vpiParameter:
\_parameter: (ICACHE_WAYS), line:122
|vpiName:ICACHE_WAYS
|INT:1
|vpiParameter:
\_parameter: (ITLB_DEPTH), line:146
|vpiName:ITLB_DEPTH
|INT:32
|vpiParameter:
\_parameter: (ITLB_WAYS), line:145
|vpiName:ITLB_WAYS
|INT:4
|vpiParameter:
\_parameter: (L1_CONNECTIONS), line:177
|vpiName:L1_CONNECTIONS
|INT:9
|vpiParameter:
\_parameter: (L1_DCACHE_ID), line:178
|vpiName:L1_DCACHE_ID
|INT:4
|vpiParameter:
\_parameter: (L1_DMMU_ID), line:179
|vpiName:L1_DMMU_ID
|INT:2
|vpiParameter:
\_parameter: (L1_ICACHE_ID), line:180
|vpiName:L1_ICACHE_ID
|INT:19
|vpiParameter:
\_parameter: (L1_IMMU_ID), line:181
|vpiName:L1_IMMU_ID
|INT:0
|vpiParameter:
\_parameter: (LOG2_FIFO_DEPTH), line:38
|vpiName:LOG2_FIFO_DEPTH
|INT:2
|vpiParameter:
\_parameter: (LS_UNIT_WB_ID), line:191
|vpiName:LS_UNIT_WB_ID
|INT:1
|vpiParameter:
\_parameter: (MAX_INFLIGHT_COUNT), line:167
|vpiName:MAX_INFLIGHT_COUNT
|INT:19
|vpiParameter:
\_parameter: (MEMORY_ADDR_H), line:103
|vpiName:MEMORY_ADDR_H
|INT:12
|vpiParameter:
\_parameter: (MEMORY_ADDR_L), line:102
|vpiName:MEMORY_ADDR_L
|INT:11
|vpiParameter:
\_parameter: (MEMORY_BIT_CHECK), line:104
|vpiName:MEMORY_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (MUL_UNIT_WB_ID), line:193
|vpiName:MUL_UNIT_WB_ID
|INT:512
|vpiParameter:
\_parameter: (NUM_UNITS), line:188
|vpiName:NUM_UNITS
|INT:2
|vpiParameter:
\_parameter: (NUM_WB_UNITS), line:186
|vpiName:NUM_WB_UNITS
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (RAS_DEPTH), line:161
|vpiName:RAS_DEPTH
|INT:2
|vpiParameter:
\_parameter: (RESET_VEC), line:39
|vpiName:RESET_VEC
|INT:-2147483648
|vpiParameter:
\_parameter: (SCRATCH_ADDR_H), line:99
|vpiName:SCRATCH_ADDR_H
|INT:9
|vpiParameter:
\_parameter: (SCRATCH_ADDR_L), line:98
|vpiName:SCRATCH_ADDR_L
|INT:8
|vpiParameter:
\_parameter: (SCRATCH_BIT_CHECK), line:100
|vpiName:SCRATCH_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (USE_AMO), line:70
|vpiName:USE_AMO
|INT:1
|vpiParameter:
\_parameter: (USE_BRANCH_PREDICTOR), line:158
|vpiName:USE_BRANCH_PREDICTOR
|INT:2
|vpiParameter:
\_parameter: (USE_BUS), line:88
|vpiName:USE_BUS
|INT:4
|vpiParameter:
\_parameter: (USE_DCACHE), line:92
|vpiName:USE_DCACHE
|INT:6
|vpiParameter:
\_parameter: (USE_DIV), line:49
|vpiName:USE_DIV
|INT:1
|vpiParameter:
\_parameter: (USE_DTAG_INVALIDATIONS), line:140
|vpiName:USE_DTAG_INVALIDATIONS
|INT:1879048191
|vpiParameter:
\_parameter: (USE_D_SCRATCH_MEM), line:79
|vpiName:USE_D_SCRATCH_MEM
|INT:3
|vpiParameter:
\_parameter: (USE_ICACHE), line:93
|vpiName:USE_ICACHE
|INT:7
|vpiParameter:
\_parameter: (USE_I_SCRATCH_MEM), line:78
|vpiName:USE_I_SCRATCH_MEM
|INT:2
|vpiParameter:
\_parameter: (USE_MUL), line:48
|vpiName:USE_MUL
|INT:1
|vpiParameter:
\_parameter: (WB_UNITS_WIDTH), line:187
|vpiName:WB_UNITS_WIDTH
|INT:32
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiGenScopeArray:
\_gen_scope_array: (genblk1[0]), line:154, parent:fetch_block
|vpiName:genblk1[0]
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk1[0]
|vpiGenScope:
\_gen_scope: , parent:genblk1[0]
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk1[0]
|vpiContAssign:
\_cont_assign: , line:155
|vpiRhs:
\_bit_select: (fetch_sub.ready), line:155
|vpiName:fetch_sub.ready
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk1[0].fetch_sub.ready
|vpiIndex:
\_ref_obj: (i), line:155
|vpiName:i
|vpiLhs:
\_bit_select: (unit_ready), line:155
|vpiName:unit_ready
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk1[0].unit_ready
|vpiIndex:
\_ref_obj: (i), line:155
|vpiName:i
|vpiContAssign:
\_cont_assign: , line:156
|vpiRhs:
\_bit_select: (fetch_sub.data_valid), line:156
|vpiName:fetch_sub.data_valid
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk1[0].fetch_sub.data_valid
|vpiIndex:
\_ref_obj: (i), line:156
|vpiName:i
|vpiLhs:
\_bit_select: (unit_data_valid), line:156
|vpiName:unit_data_valid
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk1[0].unit_data_valid
|vpiIndex:
\_ref_obj: (i), line:156
|vpiName:i
|vpiContAssign:
\_cont_assign: , line:157
|vpiRhs:
\_operation: , line:157
|vpiOpType:28
|vpiOperand:
\_ref_obj: (new_mem_request), line:157
|vpiName:new_mem_request
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk1[0].new_mem_request
|vpiOperand:
\_bit_select: (sub_unit_address_match), line:157
|vpiName:sub_unit_address_match
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk1[0].sub_unit_address_match
|vpiIndex:
\_ref_obj: (i), line:157
|vpiName:i
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk1[0].i
|vpiLhs:
\_ref_obj: (fetch_sub[i].new_request), line:157
|vpiName:fetch_sub[i].new_request
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk1[0].fetch_sub[i].new_request
|vpiContAssign:
\_cont_assign: , line:158
|vpiRhs:
\_ref_obj: (tlb.physical_address), line:158
|vpiName:tlb.physical_address
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk1[0].tlb.physical_address
|vpiLhs:
\_ref_obj: (fetch_sub[i].stage1_addr), line:158
|vpiName:fetch_sub[i].stage1_addr
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk1[0].fetch_sub[i].stage1_addr
|vpiContAssign:
\_cont_assign: , line:159
|vpiRhs:
\_ref_obj: (stage2_phys_address), line:159
|vpiName:stage2_phys_address
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk1[0].stage2_phys_address
|vpiLhs:
\_ref_obj: (fetch_sub[i].stage2_addr), line:159
|vpiName:fetch_sub[i].stage2_addr
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk1[0].fetch_sub[i].stage2_addr
|vpiContAssign:
\_cont_assign: , line:160
|vpiRhs:
\_ref_obj: (gc_fetch_flush), line:160
|vpiName:gc_fetch_flush
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk1[0].gc_fetch_flush
|vpiLhs:
\_ref_obj: (fetch_sub[i].flush), line:160
|vpiName:fetch_sub[i].flush
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk1[0].fetch_sub[i].flush
|vpiContAssign:
\_cont_assign: , line:161
|vpiRhs:
\_bit_select: (fetch_sub.data_out), line:161
|vpiName:fetch_sub.data_out
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk1[0].fetch_sub.data_out
|vpiIndex:
\_ref_obj: (i), line:161
|vpiName:i
|vpiLhs:
\_bit_select: (unit_data_array), line:161
|vpiName:unit_data_array
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk1[0].unit_data_array
|vpiIndex:
\_ref_obj: (i), line:161
|vpiName:i
|vpiParameter:
\_parameter: (ALU_UNIT_WB_ID), line:190
|vpiName:ALU_UNIT_WB_ID
|INT:32
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (BRANCH_PREDICTOR_WAYS), line:159
|vpiName:BRANCH_PREDICTOR_WAYS
|INT:9
|vpiParameter:
\_parameter: (BRANCH_TABLE_ENTRIES), line:160
|vpiName:BRANCH_TABLE_ENTRIES
|INT:4
|vpiParameter:
\_parameter: (BRANCH_UNIT_ID), line:195
|vpiName:BRANCH_UNIT_ID
|INT:8
|vpiParameter:
\_parameter: (BUS_ADDR_H), line:107
|vpiName:BUS_ADDR_H
|INT:1
|vpiParameter:
\_parameter: (BUS_ADDR_L), line:106
|vpiName:BUS_ADDR_L
|INT:0
|vpiParameter:
\_parameter: (BUS_BIT_CHECK), line:108
|vpiName:BUS_BIT_CHECK
|INT:1
|vpiParameter:
\_parameter: (BUS_TYPE), line:89
|vpiName:BUS_TYPE
|INT:5
|vpiParameter:
\_parameter: (COUNTER_W), line:42
|vpiName:COUNTER_W
|INT:33
|vpiParameter:
\_parameter: (CPU_ID), line:38
|vpiName:CPU_ID
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_ADDR_WIDTH), line:113
|vpiName:C_M_AXI_ADDR_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_DATA_WIDTH), line:114
|vpiName:C_M_AXI_DATA_WIDTH
|INT:1
|vpiParameter:
\_parameter: (DCACHE_LINES), line:133
|vpiName:DCACHE_LINES
|INT:-2146435073
|vpiParameter:
\_parameter: (DCACHE_LINE_ADDR_W), line:135
|vpiName:DCACHE_LINE_ADDR_W
|INT:1073741824
|vpiParameter:
\_parameter: (DCACHE_LINE_W), line:136
|vpiName:DCACHE_LINE_W
|INT:1342177279
|vpiParameter:
\_parameter: (DCACHE_SUB_LINE_ADDR_W), line:137
|vpiName:DCACHE_SUB_LINE_ADDR_W
|INT:4
|vpiParameter:
\_parameter: (DCACHE_TAG_W), line:138
|vpiName:DCACHE_TAG_W
|INT:1610612736
|vpiParameter:
\_parameter: (DCACHE_WAYS), line:134
|vpiName:DCACHE_WAYS
|INT:4
|vpiParameter:
\_parameter: (DIV_ALGORITHM), line:67
|vpiName:DIV_ALGORITHM
|INT:0
|vpiParameter:
\_parameter: (DIV_UNIT_WB_ID), line:192
|vpiName:DIV_UNIT_WB_ID
|INT:2
|vpiParameter:
\_parameter: (DTLB_DEPTH), line:152
|vpiName:DTLB_DEPTH
|INT:512
|vpiParameter:
\_parameter: (DTLB_WAYS), line:151
|vpiName:DTLB_WAYS
|INT:32
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (ENABLE_M_MODE), line:34
|vpiName:ENABLE_M_MODE
|INT:1
|vpiParameter:
\_parameter: (ENABLE_S_MODE), line:36
|vpiName:ENABLE_S_MODE
|INT:0
|vpiParameter:
\_parameter: (ENABLE_TRACE_INTERFACE), line:172
|vpiName:ENABLE_TRACE_INTERFACE
|INT:2
|vpiParameter:
\_parameter: (FETCH_BUFFER_DEPTH), line:168
|vpiName:FETCH_BUFFER_DEPTH
|INT:512
|vpiParameter:
\_parameter: (FPGA_VENDOR), line:27
|vpiName:FPGA_VENDOR
|STRING:"xilinx"
|vpiParameter:
\_parameter: (GC_UNIT_ID), line:196
|vpiName:GC_UNIT_ID
|INT:4
|vpiParameter:
\_parameter: (ICACHE_LINES), line:121
|vpiName:ICACHE_LINES
|INT:2
|vpiParameter:
\_parameter: (ICACHE_LINE_ADDR_W), line:123
|vpiName:ICACHE_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_LINE_W), line:124
|vpiName:ICACHE_LINE_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_SUB_LINE_ADDR_W), line:125
|vpiName:ICACHE_SUB_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_TAG_W), line:126
|vpiName:ICACHE_TAG_W
|INT:-2147483648
|vpiParameter:
\_parameter: (ICACHE_WAYS), line:122
|vpiName:ICACHE_WAYS
|INT:1
|vpiParameter:
\_parameter: (ITLB_DEPTH), line:146
|vpiName:ITLB_DEPTH
|INT:32
|vpiParameter:
\_parameter: (ITLB_WAYS), line:145
|vpiName:ITLB_WAYS
|INT:4
|vpiParameter:
\_parameter: (L1_CONNECTIONS), line:177
|vpiName:L1_CONNECTIONS
|INT:9
|vpiParameter:
\_parameter: (L1_DCACHE_ID), line:178
|vpiName:L1_DCACHE_ID
|INT:4
|vpiParameter:
\_parameter: (L1_DMMU_ID), line:179
|vpiName:L1_DMMU_ID
|INT:2
|vpiParameter:
\_parameter: (L1_ICACHE_ID), line:180
|vpiName:L1_ICACHE_ID
|INT:19
|vpiParameter:
\_parameter: (L1_IMMU_ID), line:181
|vpiName:L1_IMMU_ID
|INT:0
|vpiParameter:
\_parameter: (LS_UNIT_WB_ID), line:191
|vpiName:LS_UNIT_WB_ID
|INT:1
|vpiParameter:
\_parameter: (MAX_INFLIGHT_COUNT), line:167
|vpiName:MAX_INFLIGHT_COUNT
|INT:19
|vpiParameter:
\_parameter: (MEMORY_ADDR_H), line:103
|vpiName:MEMORY_ADDR_H
|INT:12
|vpiParameter:
\_parameter: (MEMORY_ADDR_L), line:102
|vpiName:MEMORY_ADDR_L
|INT:11
|vpiParameter:
\_parameter: (MEMORY_BIT_CHECK), line:104
|vpiName:MEMORY_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (MUL_UNIT_WB_ID), line:193
|vpiName:MUL_UNIT_WB_ID
|INT:512
|vpiParameter:
\_parameter: (NUM_UNITS), line:188
|vpiName:NUM_UNITS
|INT:2
|vpiParameter:
\_parameter: (NUM_WB_UNITS), line:186
|vpiName:NUM_WB_UNITS
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (RAS_DEPTH), line:161
|vpiName:RAS_DEPTH
|INT:2
|vpiParameter:
\_parameter: (RESET_VEC), line:39
|vpiName:RESET_VEC
|INT:-2147483648
|vpiParameter:
\_parameter: (SCRATCH_ADDR_H), line:99
|vpiName:SCRATCH_ADDR_H
|INT:9
|vpiParameter:
\_parameter: (SCRATCH_ADDR_L), line:98
|vpiName:SCRATCH_ADDR_L
|INT:8
|vpiParameter:
\_parameter: (SCRATCH_BIT_CHECK), line:100
|vpiName:SCRATCH_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (USE_AMO), line:70
|vpiName:USE_AMO
|INT:1
|vpiParameter:
\_parameter: (USE_BRANCH_PREDICTOR), line:158
|vpiName:USE_BRANCH_PREDICTOR
|INT:2
|vpiParameter:
\_parameter: (USE_BUS), line:88
|vpiName:USE_BUS
|INT:4
|vpiParameter:
\_parameter: (USE_DCACHE), line:92
|vpiName:USE_DCACHE
|INT:6
|vpiParameter:
\_parameter: (USE_DIV), line:49
|vpiName:USE_DIV
|INT:1
|vpiParameter:
\_parameter: (USE_DTAG_INVALIDATIONS), line:140
|vpiName:USE_DTAG_INVALIDATIONS
|INT:1879048191
|vpiParameter:
\_parameter: (USE_D_SCRATCH_MEM), line:79
|vpiName:USE_D_SCRATCH_MEM
|INT:3
|vpiParameter:
\_parameter: (USE_ICACHE), line:93
|vpiName:USE_ICACHE
|INT:7
|vpiParameter:
\_parameter: (USE_I_SCRATCH_MEM), line:78
|vpiName:USE_I_SCRATCH_MEM
|INT:2
|vpiParameter:
\_parameter: (USE_MUL), line:48
|vpiName:USE_MUL
|INT:1
|vpiParameter:
\_parameter: (WB_UNITS_WIDTH), line:187
|vpiName:WB_UNITS_WIDTH
|INT:32
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiParameter:
\_parameter: (i), line:154
|vpiName:i
|INT:0
|vpiGenScopeArray:
\_gen_scope_array: (genblk1[1]), line:154, parent:fetch_block
|vpiName:genblk1[1]
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk1[1]
|vpiGenScope:
\_gen_scope: , parent:genblk1[1]
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk1[1]
|vpiContAssign:
\_cont_assign: , line:155
|vpiRhs:
\_bit_select: (fetch_sub.ready), line:155
|vpiName:fetch_sub.ready
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk1[1].fetch_sub.ready
|vpiIndex:
\_ref_obj: (i), line:155
|vpiName:i
|vpiLhs:
\_bit_select: (unit_ready), line:155
|vpiName:unit_ready
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk1[1].unit_ready
|vpiIndex:
\_ref_obj: (i), line:155
|vpiName:i
|vpiContAssign:
\_cont_assign: , line:156
|vpiRhs:
\_bit_select: (fetch_sub.data_valid), line:156
|vpiName:fetch_sub.data_valid
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk1[1].fetch_sub.data_valid
|vpiIndex:
\_ref_obj: (i), line:156
|vpiName:i
|vpiLhs:
\_bit_select: (unit_data_valid), line:156
|vpiName:unit_data_valid
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk1[1].unit_data_valid
|vpiIndex:
\_ref_obj: (i), line:156
|vpiName:i
|vpiContAssign:
\_cont_assign: , line:157
|vpiRhs:
\_operation: , line:157
|vpiOpType:28
|vpiOperand:
\_ref_obj: (new_mem_request), line:157
|vpiName:new_mem_request
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk1[1].new_mem_request
|vpiOperand:
\_bit_select: (sub_unit_address_match), line:157
|vpiName:sub_unit_address_match
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk1[1].sub_unit_address_match
|vpiIndex:
\_ref_obj: (i), line:157
|vpiName:i
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk1[1].i
|vpiLhs:
\_ref_obj: (fetch_sub[i].new_request), line:157
|vpiName:fetch_sub[i].new_request
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk1[1].fetch_sub[i].new_request
|vpiContAssign:
\_cont_assign: , line:158
|vpiRhs:
\_ref_obj: (tlb.physical_address), line:158
|vpiName:tlb.physical_address
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk1[1].tlb.physical_address
|vpiLhs:
\_ref_obj: (fetch_sub[i].stage1_addr), line:158
|vpiName:fetch_sub[i].stage1_addr
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk1[1].fetch_sub[i].stage1_addr
|vpiContAssign:
\_cont_assign: , line:159
|vpiRhs:
\_ref_obj: (stage2_phys_address), line:159
|vpiName:stage2_phys_address
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk1[1].stage2_phys_address
|vpiLhs:
\_ref_obj: (fetch_sub[i].stage2_addr), line:159
|vpiName:fetch_sub[i].stage2_addr
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk1[1].fetch_sub[i].stage2_addr
|vpiContAssign:
\_cont_assign: , line:160
|vpiRhs:
\_ref_obj: (gc_fetch_flush), line:160
|vpiName:gc_fetch_flush
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk1[1].gc_fetch_flush
|vpiLhs:
\_ref_obj: (fetch_sub[i].flush), line:160
|vpiName:fetch_sub[i].flush
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk1[1].fetch_sub[i].flush
|vpiContAssign:
\_cont_assign: , line:161
|vpiRhs:
\_bit_select: (fetch_sub.data_out), line:161
|vpiName:fetch_sub.data_out
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk1[1].fetch_sub.data_out
|vpiIndex:
\_ref_obj: (i), line:161
|vpiName:i
|vpiLhs:
\_bit_select: (unit_data_array), line:161
|vpiName:unit_data_array
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk1[1].unit_data_array
|vpiIndex:
\_ref_obj: (i), line:161
|vpiName:i
|vpiParameter:
\_parameter: (ALU_UNIT_WB_ID), line:190
|vpiName:ALU_UNIT_WB_ID
|INT:32
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (BRANCH_PREDICTOR_WAYS), line:159
|vpiName:BRANCH_PREDICTOR_WAYS
|INT:9
|vpiParameter:
\_parameter: (BRANCH_TABLE_ENTRIES), line:160
|vpiName:BRANCH_TABLE_ENTRIES
|INT:4
|vpiParameter:
\_parameter: (BRANCH_UNIT_ID), line:195
|vpiName:BRANCH_UNIT_ID
|INT:8
|vpiParameter:
\_parameter: (BUS_ADDR_H), line:107
|vpiName:BUS_ADDR_H
|INT:1
|vpiParameter:
\_parameter: (BUS_ADDR_L), line:106
|vpiName:BUS_ADDR_L
|INT:0
|vpiParameter:
\_parameter: (BUS_BIT_CHECK), line:108
|vpiName:BUS_BIT_CHECK
|INT:1
|vpiParameter:
\_parameter: (BUS_TYPE), line:89
|vpiName:BUS_TYPE
|INT:5
|vpiParameter:
\_parameter: (COUNTER_W), line:42
|vpiName:COUNTER_W
|INT:33
|vpiParameter:
\_parameter: (CPU_ID), line:38
|vpiName:CPU_ID
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_ADDR_WIDTH), line:113
|vpiName:C_M_AXI_ADDR_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_DATA_WIDTH), line:114
|vpiName:C_M_AXI_DATA_WIDTH
|INT:1
|vpiParameter:
\_parameter: (DCACHE_LINES), line:133
|vpiName:DCACHE_LINES
|INT:-2146435073
|vpiParameter:
\_parameter: (DCACHE_LINE_ADDR_W), line:135
|vpiName:DCACHE_LINE_ADDR_W
|INT:1073741824
|vpiParameter:
\_parameter: (DCACHE_LINE_W), line:136
|vpiName:DCACHE_LINE_W
|INT:1342177279
|vpiParameter:
\_parameter: (DCACHE_SUB_LINE_ADDR_W), line:137
|vpiName:DCACHE_SUB_LINE_ADDR_W
|INT:4
|vpiParameter:
\_parameter: (DCACHE_TAG_W), line:138
|vpiName:DCACHE_TAG_W
|INT:1610612736
|vpiParameter:
\_parameter: (DCACHE_WAYS), line:134
|vpiName:DCACHE_WAYS
|INT:4
|vpiParameter:
\_parameter: (DIV_ALGORITHM), line:67
|vpiName:DIV_ALGORITHM
|INT:0
|vpiParameter:
\_parameter: (DIV_UNIT_WB_ID), line:192
|vpiName:DIV_UNIT_WB_ID
|INT:2
|vpiParameter:
\_parameter: (DTLB_DEPTH), line:152
|vpiName:DTLB_DEPTH
|INT:512
|vpiParameter:
\_parameter: (DTLB_WAYS), line:151
|vpiName:DTLB_WAYS
|INT:32
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (ENABLE_M_MODE), line:34
|vpiName:ENABLE_M_MODE
|INT:1
|vpiParameter:
\_parameter: (ENABLE_S_MODE), line:36
|vpiName:ENABLE_S_MODE
|INT:0
|vpiParameter:
\_parameter: (ENABLE_TRACE_INTERFACE), line:172
|vpiName:ENABLE_TRACE_INTERFACE
|INT:2
|vpiParameter:
\_parameter: (FETCH_BUFFER_DEPTH), line:168
|vpiName:FETCH_BUFFER_DEPTH
|INT:512
|vpiParameter:
\_parameter: (FPGA_VENDOR), line:27
|vpiName:FPGA_VENDOR
|STRING:"xilinx"
|vpiParameter:
\_parameter: (GC_UNIT_ID), line:196
|vpiName:GC_UNIT_ID
|INT:4
|vpiParameter:
\_parameter: (ICACHE_LINES), line:121
|vpiName:ICACHE_LINES
|INT:2
|vpiParameter:
\_parameter: (ICACHE_LINE_ADDR_W), line:123
|vpiName:ICACHE_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_LINE_W), line:124
|vpiName:ICACHE_LINE_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_SUB_LINE_ADDR_W), line:125
|vpiName:ICACHE_SUB_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_TAG_W), line:126
|vpiName:ICACHE_TAG_W
|INT:-2147483648
|vpiParameter:
\_parameter: (ICACHE_WAYS), line:122
|vpiName:ICACHE_WAYS
|INT:1
|vpiParameter:
\_parameter: (ITLB_DEPTH), line:146
|vpiName:ITLB_DEPTH
|INT:32
|vpiParameter:
\_parameter: (ITLB_WAYS), line:145
|vpiName:ITLB_WAYS
|INT:4
|vpiParameter:
\_parameter: (L1_CONNECTIONS), line:177
|vpiName:L1_CONNECTIONS
|INT:9
|vpiParameter:
\_parameter: (L1_DCACHE_ID), line:178
|vpiName:L1_DCACHE_ID
|INT:4
|vpiParameter:
\_parameter: (L1_DMMU_ID), line:179
|vpiName:L1_DMMU_ID
|INT:2
|vpiParameter:
\_parameter: (L1_ICACHE_ID), line:180
|vpiName:L1_ICACHE_ID
|INT:19
|vpiParameter:
\_parameter: (L1_IMMU_ID), line:181
|vpiName:L1_IMMU_ID
|INT:0
|vpiParameter:
\_parameter: (LS_UNIT_WB_ID), line:191
|vpiName:LS_UNIT_WB_ID
|INT:1
|vpiParameter:
\_parameter: (MAX_INFLIGHT_COUNT), line:167
|vpiName:MAX_INFLIGHT_COUNT
|INT:19
|vpiParameter:
\_parameter: (MEMORY_ADDR_H), line:103
|vpiName:MEMORY_ADDR_H
|INT:12
|vpiParameter:
\_parameter: (MEMORY_ADDR_L), line:102
|vpiName:MEMORY_ADDR_L
|INT:11
|vpiParameter:
\_parameter: (MEMORY_BIT_CHECK), line:104
|vpiName:MEMORY_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (MUL_UNIT_WB_ID), line:193
|vpiName:MUL_UNIT_WB_ID
|INT:512
|vpiParameter:
\_parameter: (NUM_UNITS), line:188
|vpiName:NUM_UNITS
|INT:2
|vpiParameter:
\_parameter: (NUM_WB_UNITS), line:186
|vpiName:NUM_WB_UNITS
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (RAS_DEPTH), line:161
|vpiName:RAS_DEPTH
|INT:2
|vpiParameter:
\_parameter: (RESET_VEC), line:39
|vpiName:RESET_VEC
|INT:-2147483648
|vpiParameter:
\_parameter: (SCRATCH_ADDR_H), line:99
|vpiName:SCRATCH_ADDR_H
|INT:9
|vpiParameter:
\_parameter: (SCRATCH_ADDR_L), line:98
|vpiName:SCRATCH_ADDR_L
|INT:8
|vpiParameter:
\_parameter: (SCRATCH_BIT_CHECK), line:100
|vpiName:SCRATCH_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (USE_AMO), line:70
|vpiName:USE_AMO
|INT:1
|vpiParameter:
\_parameter: (USE_BRANCH_PREDICTOR), line:158
|vpiName:USE_BRANCH_PREDICTOR
|INT:2
|vpiParameter:
\_parameter: (USE_BUS), line:88
|vpiName:USE_BUS
|INT:4
|vpiParameter:
\_parameter: (USE_DCACHE), line:92
|vpiName:USE_DCACHE
|INT:6
|vpiParameter:
\_parameter: (USE_DIV), line:49
|vpiName:USE_DIV
|INT:1
|vpiParameter:
\_parameter: (USE_DTAG_INVALIDATIONS), line:140
|vpiName:USE_DTAG_INVALIDATIONS
|INT:1879048191
|vpiParameter:
\_parameter: (USE_D_SCRATCH_MEM), line:79
|vpiName:USE_D_SCRATCH_MEM
|INT:3
|vpiParameter:
\_parameter: (USE_ICACHE), line:93
|vpiName:USE_ICACHE
|INT:7
|vpiParameter:
\_parameter: (USE_I_SCRATCH_MEM), line:78
|vpiName:USE_I_SCRATCH_MEM
|INT:2
|vpiParameter:
\_parameter: (USE_MUL), line:48
|vpiName:USE_MUL
|INT:1
|vpiParameter:
\_parameter: (WB_UNITS_WIDTH), line:187
|vpiName:WB_UNITS_WIDTH
|INT:32
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiParameter:
\_parameter: (i), line:154
|vpiName:i
|INT:1
|vpiGenScopeArray:
\_gen_scope_array: (genblk1[2]), line:154, parent:fetch_block
|vpiName:genblk1[2]
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk1[2]
|vpiGenScope:
\_gen_scope: , parent:genblk1[2]
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk1[2]
|vpiContAssign:
\_cont_assign: , line:155
|vpiRhs:
\_bit_select: (fetch_sub.ready), line:155
|vpiName:fetch_sub.ready
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk1[2].fetch_sub.ready
|vpiIndex:
\_ref_obj: (i), line:155
|vpiName:i
|vpiLhs:
\_bit_select: (unit_ready), line:155
|vpiName:unit_ready
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk1[2].unit_ready
|vpiIndex:
\_ref_obj: (i), line:155
|vpiName:i
|vpiContAssign:
\_cont_assign: , line:156
|vpiRhs:
\_bit_select: (fetch_sub.data_valid), line:156
|vpiName:fetch_sub.data_valid
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk1[2].fetch_sub.data_valid
|vpiIndex:
\_ref_obj: (i), line:156
|vpiName:i
|vpiLhs:
\_bit_select: (unit_data_valid), line:156
|vpiName:unit_data_valid
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk1[2].unit_data_valid
|vpiIndex:
\_ref_obj: (i), line:156
|vpiName:i
|vpiContAssign:
\_cont_assign: , line:157
|vpiRhs:
\_operation: , line:157
|vpiOpType:28
|vpiOperand:
\_ref_obj: (new_mem_request), line:157
|vpiName:new_mem_request
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk1[2].new_mem_request
|vpiOperand:
\_bit_select: (sub_unit_address_match), line:157
|vpiName:sub_unit_address_match
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk1[2].sub_unit_address_match
|vpiIndex:
\_ref_obj: (i), line:157
|vpiName:i
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk1[2].i
|vpiLhs:
\_ref_obj: (fetch_sub[i].new_request), line:157
|vpiName:fetch_sub[i].new_request
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk1[2].fetch_sub[i].new_request
|vpiContAssign:
\_cont_assign: , line:158
|vpiRhs:
\_ref_obj: (tlb.physical_address), line:158
|vpiName:tlb.physical_address
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk1[2].tlb.physical_address
|vpiLhs:
\_ref_obj: (fetch_sub[i].stage1_addr), line:158
|vpiName:fetch_sub[i].stage1_addr
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk1[2].fetch_sub[i].stage1_addr
|vpiContAssign:
\_cont_assign: , line:159
|vpiRhs:
\_ref_obj: (stage2_phys_address), line:159
|vpiName:stage2_phys_address
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk1[2].stage2_phys_address
|vpiLhs:
\_ref_obj: (fetch_sub[i].stage2_addr), line:159
|vpiName:fetch_sub[i].stage2_addr
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk1[2].fetch_sub[i].stage2_addr
|vpiContAssign:
\_cont_assign: , line:160
|vpiRhs:
\_ref_obj: (gc_fetch_flush), line:160
|vpiName:gc_fetch_flush
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk1[2].gc_fetch_flush
|vpiLhs:
\_ref_obj: (fetch_sub[i].flush), line:160
|vpiName:fetch_sub[i].flush
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk1[2].fetch_sub[i].flush
|vpiContAssign:
\_cont_assign: , line:161
|vpiRhs:
\_bit_select: (fetch_sub.data_out), line:161
|vpiName:fetch_sub.data_out
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk1[2].fetch_sub.data_out
|vpiIndex:
\_ref_obj: (i), line:161
|vpiName:i
|vpiLhs:
\_bit_select: (unit_data_array), line:161
|vpiName:unit_data_array
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk1[2].unit_data_array
|vpiIndex:
\_ref_obj: (i), line:161
|vpiName:i
|vpiParameter:
\_parameter: (ALU_UNIT_WB_ID), line:190
|vpiName:ALU_UNIT_WB_ID
|INT:32
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (BRANCH_PREDICTOR_WAYS), line:159
|vpiName:BRANCH_PREDICTOR_WAYS
|INT:9
|vpiParameter:
\_parameter: (BRANCH_TABLE_ENTRIES), line:160
|vpiName:BRANCH_TABLE_ENTRIES
|INT:4
|vpiParameter:
\_parameter: (BRANCH_UNIT_ID), line:195
|vpiName:BRANCH_UNIT_ID
|INT:8
|vpiParameter:
\_parameter: (BUS_ADDR_H), line:107
|vpiName:BUS_ADDR_H
|INT:1
|vpiParameter:
\_parameter: (BUS_ADDR_L), line:106
|vpiName:BUS_ADDR_L
|INT:0
|vpiParameter:
\_parameter: (BUS_BIT_CHECK), line:108
|vpiName:BUS_BIT_CHECK
|INT:1
|vpiParameter:
\_parameter: (BUS_TYPE), line:89
|vpiName:BUS_TYPE
|INT:5
|vpiParameter:
\_parameter: (COUNTER_W), line:42
|vpiName:COUNTER_W
|INT:33
|vpiParameter:
\_parameter: (CPU_ID), line:38
|vpiName:CPU_ID
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_ADDR_WIDTH), line:113
|vpiName:C_M_AXI_ADDR_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_DATA_WIDTH), line:114
|vpiName:C_M_AXI_DATA_WIDTH
|INT:1
|vpiParameter:
\_parameter: (DCACHE_LINES), line:133
|vpiName:DCACHE_LINES
|INT:-2146435073
|vpiParameter:
\_parameter: (DCACHE_LINE_ADDR_W), line:135
|vpiName:DCACHE_LINE_ADDR_W
|INT:1073741824
|vpiParameter:
\_parameter: (DCACHE_LINE_W), line:136
|vpiName:DCACHE_LINE_W
|INT:1342177279
|vpiParameter:
\_parameter: (DCACHE_SUB_LINE_ADDR_W), line:137
|vpiName:DCACHE_SUB_LINE_ADDR_W
|INT:4
|vpiParameter:
\_parameter: (DCACHE_TAG_W), line:138
|vpiName:DCACHE_TAG_W
|INT:1610612736
|vpiParameter:
\_parameter: (DCACHE_WAYS), line:134
|vpiName:DCACHE_WAYS
|INT:4
|vpiParameter:
\_parameter: (DIV_ALGORITHM), line:67
|vpiName:DIV_ALGORITHM
|INT:0
|vpiParameter:
\_parameter: (DIV_UNIT_WB_ID), line:192
|vpiName:DIV_UNIT_WB_ID
|INT:2
|vpiParameter:
\_parameter: (DTLB_DEPTH), line:152
|vpiName:DTLB_DEPTH
|INT:512
|vpiParameter:
\_parameter: (DTLB_WAYS), line:151
|vpiName:DTLB_WAYS
|INT:32
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (ENABLE_M_MODE), line:34
|vpiName:ENABLE_M_MODE
|INT:1
|vpiParameter:
\_parameter: (ENABLE_S_MODE), line:36
|vpiName:ENABLE_S_MODE
|INT:0
|vpiParameter:
\_parameter: (ENABLE_TRACE_INTERFACE), line:172
|vpiName:ENABLE_TRACE_INTERFACE
|INT:2
|vpiParameter:
\_parameter: (FETCH_BUFFER_DEPTH), line:168
|vpiName:FETCH_BUFFER_DEPTH
|INT:512
|vpiParameter:
\_parameter: (FPGA_VENDOR), line:27
|vpiName:FPGA_VENDOR
|STRING:"xilinx"
|vpiParameter:
\_parameter: (GC_UNIT_ID), line:196
|vpiName:GC_UNIT_ID
|INT:4
|vpiParameter:
\_parameter: (ICACHE_LINES), line:121
|vpiName:ICACHE_LINES
|INT:2
|vpiParameter:
\_parameter: (ICACHE_LINE_ADDR_W), line:123
|vpiName:ICACHE_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_LINE_W), line:124
|vpiName:ICACHE_LINE_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_SUB_LINE_ADDR_W), line:125
|vpiName:ICACHE_SUB_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_TAG_W), line:126
|vpiName:ICACHE_TAG_W
|INT:-2147483648
|vpiParameter:
\_parameter: (ICACHE_WAYS), line:122
|vpiName:ICACHE_WAYS
|INT:1
|vpiParameter:
\_parameter: (ITLB_DEPTH), line:146
|vpiName:ITLB_DEPTH
|INT:32
|vpiParameter:
\_parameter: (ITLB_WAYS), line:145
|vpiName:ITLB_WAYS
|INT:4
|vpiParameter:
\_parameter: (L1_CONNECTIONS), line:177
|vpiName:L1_CONNECTIONS
|INT:9
|vpiParameter:
\_parameter: (L1_DCACHE_ID), line:178
|vpiName:L1_DCACHE_ID
|INT:4
|vpiParameter:
\_parameter: (L1_DMMU_ID), line:179
|vpiName:L1_DMMU_ID
|INT:2
|vpiParameter:
\_parameter: (L1_ICACHE_ID), line:180
|vpiName:L1_ICACHE_ID
|INT:19
|vpiParameter:
\_parameter: (L1_IMMU_ID), line:181
|vpiName:L1_IMMU_ID
|INT:0
|vpiParameter:
\_parameter: (LS_UNIT_WB_ID), line:191
|vpiName:LS_UNIT_WB_ID
|INT:1
|vpiParameter:
\_parameter: (MAX_INFLIGHT_COUNT), line:167
|vpiName:MAX_INFLIGHT_COUNT
|INT:19
|vpiParameter:
\_parameter: (MEMORY_ADDR_H), line:103
|vpiName:MEMORY_ADDR_H
|INT:12
|vpiParameter:
\_parameter: (MEMORY_ADDR_L), line:102
|vpiName:MEMORY_ADDR_L
|INT:11
|vpiParameter:
\_parameter: (MEMORY_BIT_CHECK), line:104
|vpiName:MEMORY_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (MUL_UNIT_WB_ID), line:193
|vpiName:MUL_UNIT_WB_ID
|INT:512
|vpiParameter:
\_parameter: (NUM_UNITS), line:188
|vpiName:NUM_UNITS
|INT:2
|vpiParameter:
\_parameter: (NUM_WB_UNITS), line:186
|vpiName:NUM_WB_UNITS
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (RAS_DEPTH), line:161
|vpiName:RAS_DEPTH
|INT:2
|vpiParameter:
\_parameter: (RESET_VEC), line:39
|vpiName:RESET_VEC
|INT:-2147483648
|vpiParameter:
\_parameter: (SCRATCH_ADDR_H), line:99
|vpiName:SCRATCH_ADDR_H
|INT:9
|vpiParameter:
\_parameter: (SCRATCH_ADDR_L), line:98
|vpiName:SCRATCH_ADDR_L
|INT:8
|vpiParameter:
\_parameter: (SCRATCH_BIT_CHECK), line:100
|vpiName:SCRATCH_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (USE_AMO), line:70
|vpiName:USE_AMO
|INT:1
|vpiParameter:
\_parameter: (USE_BRANCH_PREDICTOR), line:158
|vpiName:USE_BRANCH_PREDICTOR
|INT:2
|vpiParameter:
\_parameter: (USE_BUS), line:88
|vpiName:USE_BUS
|INT:4
|vpiParameter:
\_parameter: (USE_DCACHE), line:92
|vpiName:USE_DCACHE
|INT:6
|vpiParameter:
\_parameter: (USE_DIV), line:49
|vpiName:USE_DIV
|INT:1
|vpiParameter:
\_parameter: (USE_DTAG_INVALIDATIONS), line:140
|vpiName:USE_DTAG_INVALIDATIONS
|INT:1879048191
|vpiParameter:
\_parameter: (USE_D_SCRATCH_MEM), line:79
|vpiName:USE_D_SCRATCH_MEM
|INT:3
|vpiParameter:
\_parameter: (USE_ICACHE), line:93
|vpiName:USE_ICACHE
|INT:7
|vpiParameter:
\_parameter: (USE_I_SCRATCH_MEM), line:78
|vpiName:USE_I_SCRATCH_MEM
|INT:2
|vpiParameter:
\_parameter: (USE_MUL), line:48
|vpiName:USE_MUL
|INT:1
|vpiParameter:
\_parameter: (WB_UNITS_WIDTH), line:187
|vpiName:WB_UNITS_WIDTH
|INT:32
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiParameter:
\_parameter: (i), line:154
|vpiName:i
|INT:2
|vpiGenScopeArray:
\_gen_scope_array: (genblk1[3]), line:154, parent:fetch_block
|vpiName:genblk1[3]
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk1[3]
|vpiGenScope:
\_gen_scope: , parent:genblk1[3]
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk1[3]
|vpiContAssign:
\_cont_assign: , line:155
|vpiRhs:
\_bit_select: (fetch_sub.ready), line:155
|vpiName:fetch_sub.ready
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk1[3].fetch_sub.ready
|vpiIndex:
\_ref_obj: (i), line:155
|vpiName:i
|vpiLhs:
\_bit_select: (unit_ready), line:155
|vpiName:unit_ready
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk1[3].unit_ready
|vpiIndex:
\_ref_obj: (i), line:155
|vpiName:i
|vpiContAssign:
\_cont_assign: , line:156
|vpiRhs:
\_bit_select: (fetch_sub.data_valid), line:156
|vpiName:fetch_sub.data_valid
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk1[3].fetch_sub.data_valid
|vpiIndex:
\_ref_obj: (i), line:156
|vpiName:i
|vpiLhs:
\_bit_select: (unit_data_valid), line:156
|vpiName:unit_data_valid
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk1[3].unit_data_valid
|vpiIndex:
\_ref_obj: (i), line:156
|vpiName:i
|vpiContAssign:
\_cont_assign: , line:157
|vpiRhs:
\_operation: , line:157
|vpiOpType:28
|vpiOperand:
\_ref_obj: (new_mem_request), line:157
|vpiName:new_mem_request
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk1[3].new_mem_request
|vpiOperand:
\_bit_select: (sub_unit_address_match), line:157
|vpiName:sub_unit_address_match
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk1[3].sub_unit_address_match
|vpiIndex:
\_ref_obj: (i), line:157
|vpiName:i
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk1[3].i
|vpiLhs:
\_ref_obj: (fetch_sub[i].new_request), line:157
|vpiName:fetch_sub[i].new_request
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk1[3].fetch_sub[i].new_request
|vpiContAssign:
\_cont_assign: , line:158
|vpiRhs:
\_ref_obj: (tlb.physical_address), line:158
|vpiName:tlb.physical_address
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk1[3].tlb.physical_address
|vpiLhs:
\_ref_obj: (fetch_sub[i].stage1_addr), line:158
|vpiName:fetch_sub[i].stage1_addr
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk1[3].fetch_sub[i].stage1_addr
|vpiContAssign:
\_cont_assign: , line:159
|vpiRhs:
\_ref_obj: (stage2_phys_address), line:159
|vpiName:stage2_phys_address
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk1[3].stage2_phys_address
|vpiLhs:
\_ref_obj: (fetch_sub[i].stage2_addr), line:159
|vpiName:fetch_sub[i].stage2_addr
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk1[3].fetch_sub[i].stage2_addr
|vpiContAssign:
\_cont_assign: , line:160
|vpiRhs:
\_ref_obj: (gc_fetch_flush), line:160
|vpiName:gc_fetch_flush
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk1[3].gc_fetch_flush
|vpiLhs:
\_ref_obj: (fetch_sub[i].flush), line:160
|vpiName:fetch_sub[i].flush
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk1[3].fetch_sub[i].flush
|vpiContAssign:
\_cont_assign: , line:161
|vpiRhs:
\_bit_select: (fetch_sub.data_out), line:161
|vpiName:fetch_sub.data_out
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk1[3].fetch_sub.data_out
|vpiIndex:
\_ref_obj: (i), line:161
|vpiName:i
|vpiLhs:
\_bit_select: (unit_data_array), line:161
|vpiName:unit_data_array
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk1[3].unit_data_array
|vpiIndex:
\_ref_obj: (i), line:161
|vpiName:i
|vpiParameter:
\_parameter: (ALU_UNIT_WB_ID), line:190
|vpiName:ALU_UNIT_WB_ID
|INT:32
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (BRANCH_PREDICTOR_WAYS), line:159
|vpiName:BRANCH_PREDICTOR_WAYS
|INT:9
|vpiParameter:
\_parameter: (BRANCH_TABLE_ENTRIES), line:160
|vpiName:BRANCH_TABLE_ENTRIES
|INT:4
|vpiParameter:
\_parameter: (BRANCH_UNIT_ID), line:195
|vpiName:BRANCH_UNIT_ID
|INT:8
|vpiParameter:
\_parameter: (BUS_ADDR_H), line:107
|vpiName:BUS_ADDR_H
|INT:1
|vpiParameter:
\_parameter: (BUS_ADDR_L), line:106
|vpiName:BUS_ADDR_L
|INT:0
|vpiParameter:
\_parameter: (BUS_BIT_CHECK), line:108
|vpiName:BUS_BIT_CHECK
|INT:1
|vpiParameter:
\_parameter: (BUS_TYPE), line:89
|vpiName:BUS_TYPE
|INT:5
|vpiParameter:
\_parameter: (COUNTER_W), line:42
|vpiName:COUNTER_W
|INT:33
|vpiParameter:
\_parameter: (CPU_ID), line:38
|vpiName:CPU_ID
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_ADDR_WIDTH), line:113
|vpiName:C_M_AXI_ADDR_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_DATA_WIDTH), line:114
|vpiName:C_M_AXI_DATA_WIDTH
|INT:1
|vpiParameter:
\_parameter: (DCACHE_LINES), line:133
|vpiName:DCACHE_LINES
|INT:-2146435073
|vpiParameter:
\_parameter: (DCACHE_LINE_ADDR_W), line:135
|vpiName:DCACHE_LINE_ADDR_W
|INT:1073741824
|vpiParameter:
\_parameter: (DCACHE_LINE_W), line:136
|vpiName:DCACHE_LINE_W
|INT:1342177279
|vpiParameter:
\_parameter: (DCACHE_SUB_LINE_ADDR_W), line:137
|vpiName:DCACHE_SUB_LINE_ADDR_W
|INT:4
|vpiParameter:
\_parameter: (DCACHE_TAG_W), line:138
|vpiName:DCACHE_TAG_W
|INT:1610612736
|vpiParameter:
\_parameter: (DCACHE_WAYS), line:134
|vpiName:DCACHE_WAYS
|INT:4
|vpiParameter:
\_parameter: (DIV_ALGORITHM), line:67
|vpiName:DIV_ALGORITHM
|INT:0
|vpiParameter:
\_parameter: (DIV_UNIT_WB_ID), line:192
|vpiName:DIV_UNIT_WB_ID
|INT:2
|vpiParameter:
\_parameter: (DTLB_DEPTH), line:152
|vpiName:DTLB_DEPTH
|INT:512
|vpiParameter:
\_parameter: (DTLB_WAYS), line:151
|vpiName:DTLB_WAYS
|INT:32
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (ENABLE_M_MODE), line:34
|vpiName:ENABLE_M_MODE
|INT:1
|vpiParameter:
\_parameter: (ENABLE_S_MODE), line:36
|vpiName:ENABLE_S_MODE
|INT:0
|vpiParameter:
\_parameter: (ENABLE_TRACE_INTERFACE), line:172
|vpiName:ENABLE_TRACE_INTERFACE
|INT:2
|vpiParameter:
\_parameter: (FETCH_BUFFER_DEPTH), line:168
|vpiName:FETCH_BUFFER_DEPTH
|INT:512
|vpiParameter:
\_parameter: (FPGA_VENDOR), line:27
|vpiName:FPGA_VENDOR
|STRING:"xilinx"
|vpiParameter:
\_parameter: (GC_UNIT_ID), line:196
|vpiName:GC_UNIT_ID
|INT:4
|vpiParameter:
\_parameter: (ICACHE_LINES), line:121
|vpiName:ICACHE_LINES
|INT:2
|vpiParameter:
\_parameter: (ICACHE_LINE_ADDR_W), line:123
|vpiName:ICACHE_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_LINE_W), line:124
|vpiName:ICACHE_LINE_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_SUB_LINE_ADDR_W), line:125
|vpiName:ICACHE_SUB_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_TAG_W), line:126
|vpiName:ICACHE_TAG_W
|INT:-2147483648
|vpiParameter:
\_parameter: (ICACHE_WAYS), line:122
|vpiName:ICACHE_WAYS
|INT:1
|vpiParameter:
\_parameter: (ITLB_DEPTH), line:146
|vpiName:ITLB_DEPTH
|INT:32
|vpiParameter:
\_parameter: (ITLB_WAYS), line:145
|vpiName:ITLB_WAYS
|INT:4
|vpiParameter:
\_parameter: (L1_CONNECTIONS), line:177
|vpiName:L1_CONNECTIONS
|INT:9
|vpiParameter:
\_parameter: (L1_DCACHE_ID), line:178
|vpiName:L1_DCACHE_ID
|INT:4
|vpiParameter:
\_parameter: (L1_DMMU_ID), line:179
|vpiName:L1_DMMU_ID
|INT:2
|vpiParameter:
\_parameter: (L1_ICACHE_ID), line:180
|vpiName:L1_ICACHE_ID
|INT:19
|vpiParameter:
\_parameter: (L1_IMMU_ID), line:181
|vpiName:L1_IMMU_ID
|INT:0
|vpiParameter:
\_parameter: (LS_UNIT_WB_ID), line:191
|vpiName:LS_UNIT_WB_ID
|INT:1
|vpiParameter:
\_parameter: (MAX_INFLIGHT_COUNT), line:167
|vpiName:MAX_INFLIGHT_COUNT
|INT:19
|vpiParameter:
\_parameter: (MEMORY_ADDR_H), line:103
|vpiName:MEMORY_ADDR_H
|INT:12
|vpiParameter:
\_parameter: (MEMORY_ADDR_L), line:102
|vpiName:MEMORY_ADDR_L
|INT:11
|vpiParameter:
\_parameter: (MEMORY_BIT_CHECK), line:104
|vpiName:MEMORY_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (MUL_UNIT_WB_ID), line:193
|vpiName:MUL_UNIT_WB_ID
|INT:512
|vpiParameter:
\_parameter: (NUM_UNITS), line:188
|vpiName:NUM_UNITS
|INT:2
|vpiParameter:
\_parameter: (NUM_WB_UNITS), line:186
|vpiName:NUM_WB_UNITS
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (RAS_DEPTH), line:161
|vpiName:RAS_DEPTH
|INT:2
|vpiParameter:
\_parameter: (RESET_VEC), line:39
|vpiName:RESET_VEC
|INT:-2147483648
|vpiParameter:
\_parameter: (SCRATCH_ADDR_H), line:99
|vpiName:SCRATCH_ADDR_H
|INT:9
|vpiParameter:
\_parameter: (SCRATCH_ADDR_L), line:98
|vpiName:SCRATCH_ADDR_L
|INT:8
|vpiParameter:
\_parameter: (SCRATCH_BIT_CHECK), line:100
|vpiName:SCRATCH_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (USE_AMO), line:70
|vpiName:USE_AMO
|INT:1
|vpiParameter:
\_parameter: (USE_BRANCH_PREDICTOR), line:158
|vpiName:USE_BRANCH_PREDICTOR
|INT:2
|vpiParameter:
\_parameter: (USE_BUS), line:88
|vpiName:USE_BUS
|INT:4
|vpiParameter:
\_parameter: (USE_DCACHE), line:92
|vpiName:USE_DCACHE
|INT:6
|vpiParameter:
\_parameter: (USE_DIV), line:49
|vpiName:USE_DIV
|INT:1
|vpiParameter:
\_parameter: (USE_DTAG_INVALIDATIONS), line:140
|vpiName:USE_DTAG_INVALIDATIONS
|INT:1879048191
|vpiParameter:
\_parameter: (USE_D_SCRATCH_MEM), line:79
|vpiName:USE_D_SCRATCH_MEM
|INT:3
|vpiParameter:
\_parameter: (USE_ICACHE), line:93
|vpiName:USE_ICACHE
|INT:7
|vpiParameter:
\_parameter: (USE_I_SCRATCH_MEM), line:78
|vpiName:USE_I_SCRATCH_MEM
|INT:2
|vpiParameter:
\_parameter: (USE_MUL), line:48
|vpiName:USE_MUL
|INT:1
|vpiParameter:
\_parameter: (WB_UNITS_WIDTH), line:187
|vpiName:WB_UNITS_WIDTH
|INT:32
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiParameter:
\_parameter: (i), line:154
|vpiName:i
|INT:3
|vpiGenScopeArray:
\_gen_scope_array: (genblk1[4]), line:154, parent:fetch_block
|vpiName:genblk1[4]
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk1[4]
|vpiGenScope:
\_gen_scope: , parent:genblk1[4]
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk1[4]
|vpiContAssign:
\_cont_assign: , line:155
|vpiRhs:
\_bit_select: (fetch_sub.ready), line:155
|vpiName:fetch_sub.ready
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk1[4].fetch_sub.ready
|vpiIndex:
\_ref_obj: (i), line:155
|vpiName:i
|vpiLhs:
\_bit_select: (unit_ready), line:155
|vpiName:unit_ready
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk1[4].unit_ready
|vpiIndex:
\_ref_obj: (i), line:155
|vpiName:i
|vpiContAssign:
\_cont_assign: , line:156
|vpiRhs:
\_bit_select: (fetch_sub.data_valid), line:156
|vpiName:fetch_sub.data_valid
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk1[4].fetch_sub.data_valid
|vpiIndex:
\_ref_obj: (i), line:156
|vpiName:i
|vpiLhs:
\_bit_select: (unit_data_valid), line:156
|vpiName:unit_data_valid
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk1[4].unit_data_valid
|vpiIndex:
\_ref_obj: (i), line:156
|vpiName:i
|vpiContAssign:
\_cont_assign: , line:157
|vpiRhs:
\_operation: , line:157
|vpiOpType:28
|vpiOperand:
\_ref_obj: (new_mem_request), line:157
|vpiName:new_mem_request
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk1[4].new_mem_request
|vpiOperand:
\_bit_select: (sub_unit_address_match), line:157
|vpiName:sub_unit_address_match
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk1[4].sub_unit_address_match
|vpiIndex:
\_ref_obj: (i), line:157
|vpiName:i
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk1[4].i
|vpiLhs:
\_ref_obj: (fetch_sub[i].new_request), line:157
|vpiName:fetch_sub[i].new_request
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk1[4].fetch_sub[i].new_request
|vpiContAssign:
\_cont_assign: , line:158
|vpiRhs:
\_ref_obj: (tlb.physical_address), line:158
|vpiName:tlb.physical_address
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk1[4].tlb.physical_address
|vpiLhs:
\_ref_obj: (fetch_sub[i].stage1_addr), line:158
|vpiName:fetch_sub[i].stage1_addr
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk1[4].fetch_sub[i].stage1_addr
|vpiContAssign:
\_cont_assign: , line:159
|vpiRhs:
\_ref_obj: (stage2_phys_address), line:159
|vpiName:stage2_phys_address
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk1[4].stage2_phys_address
|vpiLhs:
\_ref_obj: (fetch_sub[i].stage2_addr), line:159
|vpiName:fetch_sub[i].stage2_addr
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk1[4].fetch_sub[i].stage2_addr
|vpiContAssign:
\_cont_assign: , line:160
|vpiRhs:
\_ref_obj: (gc_fetch_flush), line:160
|vpiName:gc_fetch_flush
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk1[4].gc_fetch_flush
|vpiLhs:
\_ref_obj: (fetch_sub[i].flush), line:160
|vpiName:fetch_sub[i].flush
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk1[4].fetch_sub[i].flush
|vpiContAssign:
\_cont_assign: , line:161
|vpiRhs:
\_bit_select: (fetch_sub.data_out), line:161
|vpiName:fetch_sub.data_out
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk1[4].fetch_sub.data_out
|vpiIndex:
\_ref_obj: (i), line:161
|vpiName:i
|vpiLhs:
\_bit_select: (unit_data_array), line:161
|vpiName:unit_data_array
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk1[4].unit_data_array
|vpiIndex:
\_ref_obj: (i), line:161
|vpiName:i
|vpiParameter:
\_parameter: (ALU_UNIT_WB_ID), line:190
|vpiName:ALU_UNIT_WB_ID
|INT:32
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (BRANCH_PREDICTOR_WAYS), line:159
|vpiName:BRANCH_PREDICTOR_WAYS
|INT:9
|vpiParameter:
\_parameter: (BRANCH_TABLE_ENTRIES), line:160
|vpiName:BRANCH_TABLE_ENTRIES
|INT:4
|vpiParameter:
\_parameter: (BRANCH_UNIT_ID), line:195
|vpiName:BRANCH_UNIT_ID
|INT:8
|vpiParameter:
\_parameter: (BUS_ADDR_H), line:107
|vpiName:BUS_ADDR_H
|INT:1
|vpiParameter:
\_parameter: (BUS_ADDR_L), line:106
|vpiName:BUS_ADDR_L
|INT:0
|vpiParameter:
\_parameter: (BUS_BIT_CHECK), line:108
|vpiName:BUS_BIT_CHECK
|INT:1
|vpiParameter:
\_parameter: (BUS_TYPE), line:89
|vpiName:BUS_TYPE
|INT:5
|vpiParameter:
\_parameter: (COUNTER_W), line:42
|vpiName:COUNTER_W
|INT:33
|vpiParameter:
\_parameter: (CPU_ID), line:38
|vpiName:CPU_ID
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_ADDR_WIDTH), line:113
|vpiName:C_M_AXI_ADDR_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_DATA_WIDTH), line:114
|vpiName:C_M_AXI_DATA_WIDTH
|INT:1
|vpiParameter:
\_parameter: (DCACHE_LINES), line:133
|vpiName:DCACHE_LINES
|INT:-2146435073
|vpiParameter:
\_parameter: (DCACHE_LINE_ADDR_W), line:135
|vpiName:DCACHE_LINE_ADDR_W
|INT:1073741824
|vpiParameter:
\_parameter: (DCACHE_LINE_W), line:136
|vpiName:DCACHE_LINE_W
|INT:1342177279
|vpiParameter:
\_parameter: (DCACHE_SUB_LINE_ADDR_W), line:137
|vpiName:DCACHE_SUB_LINE_ADDR_W
|INT:4
|vpiParameter:
\_parameter: (DCACHE_TAG_W), line:138
|vpiName:DCACHE_TAG_W
|INT:1610612736
|vpiParameter:
\_parameter: (DCACHE_WAYS), line:134
|vpiName:DCACHE_WAYS
|INT:4
|vpiParameter:
\_parameter: (DIV_ALGORITHM), line:67
|vpiName:DIV_ALGORITHM
|INT:0
|vpiParameter:
\_parameter: (DIV_UNIT_WB_ID), line:192
|vpiName:DIV_UNIT_WB_ID
|INT:2
|vpiParameter:
\_parameter: (DTLB_DEPTH), line:152
|vpiName:DTLB_DEPTH
|INT:512
|vpiParameter:
\_parameter: (DTLB_WAYS), line:151
|vpiName:DTLB_WAYS
|INT:32
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (ENABLE_M_MODE), line:34
|vpiName:ENABLE_M_MODE
|INT:1
|vpiParameter:
\_parameter: (ENABLE_S_MODE), line:36
|vpiName:ENABLE_S_MODE
|INT:0
|vpiParameter:
\_parameter: (ENABLE_TRACE_INTERFACE), line:172
|vpiName:ENABLE_TRACE_INTERFACE
|INT:2
|vpiParameter:
\_parameter: (FETCH_BUFFER_DEPTH), line:168
|vpiName:FETCH_BUFFER_DEPTH
|INT:512
|vpiParameter:
\_parameter: (FPGA_VENDOR), line:27
|vpiName:FPGA_VENDOR
|STRING:"xilinx"
|vpiParameter:
\_parameter: (GC_UNIT_ID), line:196
|vpiName:GC_UNIT_ID
|INT:4
|vpiParameter:
\_parameter: (ICACHE_LINES), line:121
|vpiName:ICACHE_LINES
|INT:2
|vpiParameter:
\_parameter: (ICACHE_LINE_ADDR_W), line:123
|vpiName:ICACHE_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_LINE_W), line:124
|vpiName:ICACHE_LINE_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_SUB_LINE_ADDR_W), line:125
|vpiName:ICACHE_SUB_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_TAG_W), line:126
|vpiName:ICACHE_TAG_W
|INT:-2147483648
|vpiParameter:
\_parameter: (ICACHE_WAYS), line:122
|vpiName:ICACHE_WAYS
|INT:1
|vpiParameter:
\_parameter: (ITLB_DEPTH), line:146
|vpiName:ITLB_DEPTH
|INT:32
|vpiParameter:
\_parameter: (ITLB_WAYS), line:145
|vpiName:ITLB_WAYS
|INT:4
|vpiParameter:
\_parameter: (L1_CONNECTIONS), line:177
|vpiName:L1_CONNECTIONS
|INT:9
|vpiParameter:
\_parameter: (L1_DCACHE_ID), line:178
|vpiName:L1_DCACHE_ID
|INT:4
|vpiParameter:
\_parameter: (L1_DMMU_ID), line:179
|vpiName:L1_DMMU_ID
|INT:2
|vpiParameter:
\_parameter: (L1_ICACHE_ID), line:180
|vpiName:L1_ICACHE_ID
|INT:19
|vpiParameter:
\_parameter: (L1_IMMU_ID), line:181
|vpiName:L1_IMMU_ID
|INT:0
|vpiParameter:
\_parameter: (LS_UNIT_WB_ID), line:191
|vpiName:LS_UNIT_WB_ID
|INT:1
|vpiParameter:
\_parameter: (MAX_INFLIGHT_COUNT), line:167
|vpiName:MAX_INFLIGHT_COUNT
|INT:19
|vpiParameter:
\_parameter: (MEMORY_ADDR_H), line:103
|vpiName:MEMORY_ADDR_H
|INT:12
|vpiParameter:
\_parameter: (MEMORY_ADDR_L), line:102
|vpiName:MEMORY_ADDR_L
|INT:11
|vpiParameter:
\_parameter: (MEMORY_BIT_CHECK), line:104
|vpiName:MEMORY_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (MUL_UNIT_WB_ID), line:193
|vpiName:MUL_UNIT_WB_ID
|INT:512
|vpiParameter:
\_parameter: (NUM_UNITS), line:188
|vpiName:NUM_UNITS
|INT:2
|vpiParameter:
\_parameter: (NUM_WB_UNITS), line:186
|vpiName:NUM_WB_UNITS
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (RAS_DEPTH), line:161
|vpiName:RAS_DEPTH
|INT:2
|vpiParameter:
\_parameter: (RESET_VEC), line:39
|vpiName:RESET_VEC
|INT:-2147483648
|vpiParameter:
\_parameter: (SCRATCH_ADDR_H), line:99
|vpiName:SCRATCH_ADDR_H
|INT:9
|vpiParameter:
\_parameter: (SCRATCH_ADDR_L), line:98
|vpiName:SCRATCH_ADDR_L
|INT:8
|vpiParameter:
\_parameter: (SCRATCH_BIT_CHECK), line:100
|vpiName:SCRATCH_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (USE_AMO), line:70
|vpiName:USE_AMO
|INT:1
|vpiParameter:
\_parameter: (USE_BRANCH_PREDICTOR), line:158
|vpiName:USE_BRANCH_PREDICTOR
|INT:2
|vpiParameter:
\_parameter: (USE_BUS), line:88
|vpiName:USE_BUS
|INT:4
|vpiParameter:
\_parameter: (USE_DCACHE), line:92
|vpiName:USE_DCACHE
|INT:6
|vpiParameter:
\_parameter: (USE_DIV), line:49
|vpiName:USE_DIV
|INT:1
|vpiParameter:
\_parameter: (USE_DTAG_INVALIDATIONS), line:140
|vpiName:USE_DTAG_INVALIDATIONS
|INT:1879048191
|vpiParameter:
\_parameter: (USE_D_SCRATCH_MEM), line:79
|vpiName:USE_D_SCRATCH_MEM
|INT:3
|vpiParameter:
\_parameter: (USE_ICACHE), line:93
|vpiName:USE_ICACHE
|INT:7
|vpiParameter:
\_parameter: (USE_I_SCRATCH_MEM), line:78
|vpiName:USE_I_SCRATCH_MEM
|INT:2
|vpiParameter:
\_parameter: (USE_MUL), line:48
|vpiName:USE_MUL
|INT:1
|vpiParameter:
\_parameter: (WB_UNITS_WIDTH), line:187
|vpiName:WB_UNITS_WIDTH
|INT:32
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiParameter:
\_parameter: (i), line:154
|vpiName:i
|INT:4
|vpiGenScopeArray:
\_gen_scope_array: (genblk1[5]), line:154, parent:fetch_block
|vpiName:genblk1[5]
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk1[5]
|vpiGenScope:
\_gen_scope: , parent:genblk1[5]
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk1[5]
|vpiContAssign:
\_cont_assign: , line:155
|vpiRhs:
\_bit_select: (fetch_sub.ready), line:155
|vpiName:fetch_sub.ready
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk1[5].fetch_sub.ready
|vpiIndex:
\_ref_obj: (i), line:155
|vpiName:i
|vpiLhs:
\_bit_select: (unit_ready), line:155
|vpiName:unit_ready
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk1[5].unit_ready
|vpiIndex:
\_ref_obj: (i), line:155
|vpiName:i
|vpiContAssign:
\_cont_assign: , line:156
|vpiRhs:
\_bit_select: (fetch_sub.data_valid), line:156
|vpiName:fetch_sub.data_valid
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk1[5].fetch_sub.data_valid
|vpiIndex:
\_ref_obj: (i), line:156
|vpiName:i
|vpiLhs:
\_bit_select: (unit_data_valid), line:156
|vpiName:unit_data_valid
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk1[5].unit_data_valid
|vpiIndex:
\_ref_obj: (i), line:156
|vpiName:i
|vpiContAssign:
\_cont_assign: , line:157
|vpiRhs:
\_operation: , line:157
|vpiOpType:28
|vpiOperand:
\_ref_obj: (new_mem_request), line:157
|vpiName:new_mem_request
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk1[5].new_mem_request
|vpiOperand:
\_bit_select: (sub_unit_address_match), line:157
|vpiName:sub_unit_address_match
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk1[5].sub_unit_address_match
|vpiIndex:
\_ref_obj: (i), line:157
|vpiName:i
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk1[5].i
|vpiLhs:
\_ref_obj: (fetch_sub[i].new_request), line:157
|vpiName:fetch_sub[i].new_request
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk1[5].fetch_sub[i].new_request
|vpiContAssign:
\_cont_assign: , line:158
|vpiRhs:
\_ref_obj: (tlb.physical_address), line:158
|vpiName:tlb.physical_address
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk1[5].tlb.physical_address
|vpiLhs:
\_ref_obj: (fetch_sub[i].stage1_addr), line:158
|vpiName:fetch_sub[i].stage1_addr
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk1[5].fetch_sub[i].stage1_addr
|vpiContAssign:
\_cont_assign: , line:159
|vpiRhs:
\_ref_obj: (stage2_phys_address), line:159
|vpiName:stage2_phys_address
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk1[5].stage2_phys_address
|vpiLhs:
\_ref_obj: (fetch_sub[i].stage2_addr), line:159
|vpiName:fetch_sub[i].stage2_addr
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk1[5].fetch_sub[i].stage2_addr
|vpiContAssign:
\_cont_assign: , line:160
|vpiRhs:
\_ref_obj: (gc_fetch_flush), line:160
|vpiName:gc_fetch_flush
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk1[5].gc_fetch_flush
|vpiLhs:
\_ref_obj: (fetch_sub[i].flush), line:160
|vpiName:fetch_sub[i].flush
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk1[5].fetch_sub[i].flush
|vpiContAssign:
\_cont_assign: , line:161
|vpiRhs:
\_bit_select: (fetch_sub.data_out), line:161
|vpiName:fetch_sub.data_out
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk1[5].fetch_sub.data_out
|vpiIndex:
\_ref_obj: (i), line:161
|vpiName:i
|vpiLhs:
\_bit_select: (unit_data_array), line:161
|vpiName:unit_data_array
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk1[5].unit_data_array
|vpiIndex:
\_ref_obj: (i), line:161
|vpiName:i
|vpiParameter:
\_parameter: (ALU_UNIT_WB_ID), line:190
|vpiName:ALU_UNIT_WB_ID
|INT:32
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (BRANCH_PREDICTOR_WAYS), line:159
|vpiName:BRANCH_PREDICTOR_WAYS
|INT:9
|vpiParameter:
\_parameter: (BRANCH_TABLE_ENTRIES), line:160
|vpiName:BRANCH_TABLE_ENTRIES
|INT:4
|vpiParameter:
\_parameter: (BRANCH_UNIT_ID), line:195
|vpiName:BRANCH_UNIT_ID
|INT:8
|vpiParameter:
\_parameter: (BUS_ADDR_H), line:107
|vpiName:BUS_ADDR_H
|INT:1
|vpiParameter:
\_parameter: (BUS_ADDR_L), line:106
|vpiName:BUS_ADDR_L
|INT:0
|vpiParameter:
\_parameter: (BUS_BIT_CHECK), line:108
|vpiName:BUS_BIT_CHECK
|INT:1
|vpiParameter:
\_parameter: (BUS_TYPE), line:89
|vpiName:BUS_TYPE
|INT:5
|vpiParameter:
\_parameter: (COUNTER_W), line:42
|vpiName:COUNTER_W
|INT:33
|vpiParameter:
\_parameter: (CPU_ID), line:38
|vpiName:CPU_ID
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_ADDR_WIDTH), line:113
|vpiName:C_M_AXI_ADDR_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_DATA_WIDTH), line:114
|vpiName:C_M_AXI_DATA_WIDTH
|INT:1
|vpiParameter:
\_parameter: (DCACHE_LINES), line:133
|vpiName:DCACHE_LINES
|INT:-2146435073
|vpiParameter:
\_parameter: (DCACHE_LINE_ADDR_W), line:135
|vpiName:DCACHE_LINE_ADDR_W
|INT:1073741824
|vpiParameter:
\_parameter: (DCACHE_LINE_W), line:136
|vpiName:DCACHE_LINE_W
|INT:1342177279
|vpiParameter:
\_parameter: (DCACHE_SUB_LINE_ADDR_W), line:137
|vpiName:DCACHE_SUB_LINE_ADDR_W
|INT:4
|vpiParameter:
\_parameter: (DCACHE_TAG_W), line:138
|vpiName:DCACHE_TAG_W
|INT:1610612736
|vpiParameter:
\_parameter: (DCACHE_WAYS), line:134
|vpiName:DCACHE_WAYS
|INT:4
|vpiParameter:
\_parameter: (DIV_ALGORITHM), line:67
|vpiName:DIV_ALGORITHM
|INT:0
|vpiParameter:
\_parameter: (DIV_UNIT_WB_ID), line:192
|vpiName:DIV_UNIT_WB_ID
|INT:2
|vpiParameter:
\_parameter: (DTLB_DEPTH), line:152
|vpiName:DTLB_DEPTH
|INT:512
|vpiParameter:
\_parameter: (DTLB_WAYS), line:151
|vpiName:DTLB_WAYS
|INT:32
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (ENABLE_M_MODE), line:34
|vpiName:ENABLE_M_MODE
|INT:1
|vpiParameter:
\_parameter: (ENABLE_S_MODE), line:36
|vpiName:ENABLE_S_MODE
|INT:0
|vpiParameter:
\_parameter: (ENABLE_TRACE_INTERFACE), line:172
|vpiName:ENABLE_TRACE_INTERFACE
|INT:2
|vpiParameter:
\_parameter: (FETCH_BUFFER_DEPTH), line:168
|vpiName:FETCH_BUFFER_DEPTH
|INT:512
|vpiParameter:
\_parameter: (FPGA_VENDOR), line:27
|vpiName:FPGA_VENDOR
|STRING:"xilinx"
|vpiParameter:
\_parameter: (GC_UNIT_ID), line:196
|vpiName:GC_UNIT_ID
|INT:4
|vpiParameter:
\_parameter: (ICACHE_LINES), line:121
|vpiName:ICACHE_LINES
|INT:2
|vpiParameter:
\_parameter: (ICACHE_LINE_ADDR_W), line:123
|vpiName:ICACHE_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_LINE_W), line:124
|vpiName:ICACHE_LINE_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_SUB_LINE_ADDR_W), line:125
|vpiName:ICACHE_SUB_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_TAG_W), line:126
|vpiName:ICACHE_TAG_W
|INT:-2147483648
|vpiParameter:
\_parameter: (ICACHE_WAYS), line:122
|vpiName:ICACHE_WAYS
|INT:1
|vpiParameter:
\_parameter: (ITLB_DEPTH), line:146
|vpiName:ITLB_DEPTH
|INT:32
|vpiParameter:
\_parameter: (ITLB_WAYS), line:145
|vpiName:ITLB_WAYS
|INT:4
|vpiParameter:
\_parameter: (L1_CONNECTIONS), line:177
|vpiName:L1_CONNECTIONS
|INT:9
|vpiParameter:
\_parameter: (L1_DCACHE_ID), line:178
|vpiName:L1_DCACHE_ID
|INT:4
|vpiParameter:
\_parameter: (L1_DMMU_ID), line:179
|vpiName:L1_DMMU_ID
|INT:2
|vpiParameter:
\_parameter: (L1_ICACHE_ID), line:180
|vpiName:L1_ICACHE_ID
|INT:19
|vpiParameter:
\_parameter: (L1_IMMU_ID), line:181
|vpiName:L1_IMMU_ID
|INT:0
|vpiParameter:
\_parameter: (LS_UNIT_WB_ID), line:191
|vpiName:LS_UNIT_WB_ID
|INT:1
|vpiParameter:
\_parameter: (MAX_INFLIGHT_COUNT), line:167
|vpiName:MAX_INFLIGHT_COUNT
|INT:19
|vpiParameter:
\_parameter: (MEMORY_ADDR_H), line:103
|vpiName:MEMORY_ADDR_H
|INT:12
|vpiParameter:
\_parameter: (MEMORY_ADDR_L), line:102
|vpiName:MEMORY_ADDR_L
|INT:11
|vpiParameter:
\_parameter: (MEMORY_BIT_CHECK), line:104
|vpiName:MEMORY_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (MUL_UNIT_WB_ID), line:193
|vpiName:MUL_UNIT_WB_ID
|INT:512
|vpiParameter:
\_parameter: (NUM_UNITS), line:188
|vpiName:NUM_UNITS
|INT:2
|vpiParameter:
\_parameter: (NUM_WB_UNITS), line:186
|vpiName:NUM_WB_UNITS
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (RAS_DEPTH), line:161
|vpiName:RAS_DEPTH
|INT:2
|vpiParameter:
\_parameter: (RESET_VEC), line:39
|vpiName:RESET_VEC
|INT:-2147483648
|vpiParameter:
\_parameter: (SCRATCH_ADDR_H), line:99
|vpiName:SCRATCH_ADDR_H
|INT:9
|vpiParameter:
\_parameter: (SCRATCH_ADDR_L), line:98
|vpiName:SCRATCH_ADDR_L
|INT:8
|vpiParameter:
\_parameter: (SCRATCH_BIT_CHECK), line:100
|vpiName:SCRATCH_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (USE_AMO), line:70
|vpiName:USE_AMO
|INT:1
|vpiParameter:
\_parameter: (USE_BRANCH_PREDICTOR), line:158
|vpiName:USE_BRANCH_PREDICTOR
|INT:2
|vpiParameter:
\_parameter: (USE_BUS), line:88
|vpiName:USE_BUS
|INT:4
|vpiParameter:
\_parameter: (USE_DCACHE), line:92
|vpiName:USE_DCACHE
|INT:6
|vpiParameter:
\_parameter: (USE_DIV), line:49
|vpiName:USE_DIV
|INT:1
|vpiParameter:
\_parameter: (USE_DTAG_INVALIDATIONS), line:140
|vpiName:USE_DTAG_INVALIDATIONS
|INT:1879048191
|vpiParameter:
\_parameter: (USE_D_SCRATCH_MEM), line:79
|vpiName:USE_D_SCRATCH_MEM
|INT:3
|vpiParameter:
\_parameter: (USE_ICACHE), line:93
|vpiName:USE_ICACHE
|INT:7
|vpiParameter:
\_parameter: (USE_I_SCRATCH_MEM), line:78
|vpiName:USE_I_SCRATCH_MEM
|INT:2
|vpiParameter:
\_parameter: (USE_MUL), line:48
|vpiName:USE_MUL
|INT:1
|vpiParameter:
\_parameter: (WB_UNITS_WIDTH), line:187
|vpiName:WB_UNITS_WIDTH
|INT:32
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiParameter:
\_parameter: (i), line:154
|vpiName:i
|INT:5
|vpiGenScopeArray:
\_gen_scope_array: (genblk1[6]), line:154, parent:fetch_block
|vpiName:genblk1[6]
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk1[6]
|vpiGenScope:
\_gen_scope: , parent:genblk1[6]
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk1[6]
|vpiContAssign:
\_cont_assign: , line:155
|vpiRhs:
\_bit_select: (fetch_sub.ready), line:155
|vpiName:fetch_sub.ready
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk1[6].fetch_sub.ready
|vpiIndex:
\_ref_obj: (i), line:155
|vpiName:i
|vpiLhs:
\_bit_select: (unit_ready), line:155
|vpiName:unit_ready
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk1[6].unit_ready
|vpiIndex:
\_ref_obj: (i), line:155
|vpiName:i
|vpiContAssign:
\_cont_assign: , line:156
|vpiRhs:
\_bit_select: (fetch_sub.data_valid), line:156
|vpiName:fetch_sub.data_valid
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk1[6].fetch_sub.data_valid
|vpiIndex:
\_ref_obj: (i), line:156
|vpiName:i
|vpiLhs:
\_bit_select: (unit_data_valid), line:156
|vpiName:unit_data_valid
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk1[6].unit_data_valid
|vpiIndex:
\_ref_obj: (i), line:156
|vpiName:i
|vpiContAssign:
\_cont_assign: , line:157
|vpiRhs:
\_operation: , line:157
|vpiOpType:28
|vpiOperand:
\_ref_obj: (new_mem_request), line:157
|vpiName:new_mem_request
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk1[6].new_mem_request
|vpiOperand:
\_bit_select: (sub_unit_address_match), line:157
|vpiName:sub_unit_address_match
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk1[6].sub_unit_address_match
|vpiIndex:
\_ref_obj: (i), line:157
|vpiName:i
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk1[6].i
|vpiLhs:
\_ref_obj: (fetch_sub[i].new_request), line:157
|vpiName:fetch_sub[i].new_request
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk1[6].fetch_sub[i].new_request
|vpiContAssign:
\_cont_assign: , line:158
|vpiRhs:
\_ref_obj: (tlb.physical_address), line:158
|vpiName:tlb.physical_address
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk1[6].tlb.physical_address
|vpiLhs:
\_ref_obj: (fetch_sub[i].stage1_addr), line:158
|vpiName:fetch_sub[i].stage1_addr
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk1[6].fetch_sub[i].stage1_addr
|vpiContAssign:
\_cont_assign: , line:159
|vpiRhs:
\_ref_obj: (stage2_phys_address), line:159
|vpiName:stage2_phys_address
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk1[6].stage2_phys_address
|vpiLhs:
\_ref_obj: (fetch_sub[i].stage2_addr), line:159
|vpiName:fetch_sub[i].stage2_addr
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk1[6].fetch_sub[i].stage2_addr
|vpiContAssign:
\_cont_assign: , line:160
|vpiRhs:
\_ref_obj: (gc_fetch_flush), line:160
|vpiName:gc_fetch_flush
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk1[6].gc_fetch_flush
|vpiLhs:
\_ref_obj: (fetch_sub[i].flush), line:160
|vpiName:fetch_sub[i].flush
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk1[6].fetch_sub[i].flush
|vpiContAssign:
\_cont_assign: , line:161
|vpiRhs:
\_bit_select: (fetch_sub.data_out), line:161
|vpiName:fetch_sub.data_out
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk1[6].fetch_sub.data_out
|vpiIndex:
\_ref_obj: (i), line:161
|vpiName:i
|vpiLhs:
\_bit_select: (unit_data_array), line:161
|vpiName:unit_data_array
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk1[6].unit_data_array
|vpiIndex:
\_ref_obj: (i), line:161
|vpiName:i
|vpiParameter:
\_parameter: (ALU_UNIT_WB_ID), line:190
|vpiName:ALU_UNIT_WB_ID
|INT:32
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (BRANCH_PREDICTOR_WAYS), line:159
|vpiName:BRANCH_PREDICTOR_WAYS
|INT:9
|vpiParameter:
\_parameter: (BRANCH_TABLE_ENTRIES), line:160
|vpiName:BRANCH_TABLE_ENTRIES
|INT:4
|vpiParameter:
\_parameter: (BRANCH_UNIT_ID), line:195
|vpiName:BRANCH_UNIT_ID
|INT:8
|vpiParameter:
\_parameter: (BUS_ADDR_H), line:107
|vpiName:BUS_ADDR_H
|INT:1
|vpiParameter:
\_parameter: (BUS_ADDR_L), line:106
|vpiName:BUS_ADDR_L
|INT:0
|vpiParameter:
\_parameter: (BUS_BIT_CHECK), line:108
|vpiName:BUS_BIT_CHECK
|INT:1
|vpiParameter:
\_parameter: (BUS_TYPE), line:89
|vpiName:BUS_TYPE
|INT:5
|vpiParameter:
\_parameter: (COUNTER_W), line:42
|vpiName:COUNTER_W
|INT:33
|vpiParameter:
\_parameter: (CPU_ID), line:38
|vpiName:CPU_ID
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_ADDR_WIDTH), line:113
|vpiName:C_M_AXI_ADDR_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_DATA_WIDTH), line:114
|vpiName:C_M_AXI_DATA_WIDTH
|INT:1
|vpiParameter:
\_parameter: (DCACHE_LINES), line:133
|vpiName:DCACHE_LINES
|INT:-2146435073
|vpiParameter:
\_parameter: (DCACHE_LINE_ADDR_W), line:135
|vpiName:DCACHE_LINE_ADDR_W
|INT:1073741824
|vpiParameter:
\_parameter: (DCACHE_LINE_W), line:136
|vpiName:DCACHE_LINE_W
|INT:1342177279
|vpiParameter:
\_parameter: (DCACHE_SUB_LINE_ADDR_W), line:137
|vpiName:DCACHE_SUB_LINE_ADDR_W
|INT:4
|vpiParameter:
\_parameter: (DCACHE_TAG_W), line:138
|vpiName:DCACHE_TAG_W
|INT:1610612736
|vpiParameter:
\_parameter: (DCACHE_WAYS), line:134
|vpiName:DCACHE_WAYS
|INT:4
|vpiParameter:
\_parameter: (DIV_ALGORITHM), line:67
|vpiName:DIV_ALGORITHM
|INT:0
|vpiParameter:
\_parameter: (DIV_UNIT_WB_ID), line:192
|vpiName:DIV_UNIT_WB_ID
|INT:2
|vpiParameter:
\_parameter: (DTLB_DEPTH), line:152
|vpiName:DTLB_DEPTH
|INT:512
|vpiParameter:
\_parameter: (DTLB_WAYS), line:151
|vpiName:DTLB_WAYS
|INT:32
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (ENABLE_M_MODE), line:34
|vpiName:ENABLE_M_MODE
|INT:1
|vpiParameter:
\_parameter: (ENABLE_S_MODE), line:36
|vpiName:ENABLE_S_MODE
|INT:0
|vpiParameter:
\_parameter: (ENABLE_TRACE_INTERFACE), line:172
|vpiName:ENABLE_TRACE_INTERFACE
|INT:2
|vpiParameter:
\_parameter: (FETCH_BUFFER_DEPTH), line:168
|vpiName:FETCH_BUFFER_DEPTH
|INT:512
|vpiParameter:
\_parameter: (FPGA_VENDOR), line:27
|vpiName:FPGA_VENDOR
|STRING:"xilinx"
|vpiParameter:
\_parameter: (GC_UNIT_ID), line:196
|vpiName:GC_UNIT_ID
|INT:4
|vpiParameter:
\_parameter: (ICACHE_LINES), line:121
|vpiName:ICACHE_LINES
|INT:2
|vpiParameter:
\_parameter: (ICACHE_LINE_ADDR_W), line:123
|vpiName:ICACHE_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_LINE_W), line:124
|vpiName:ICACHE_LINE_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_SUB_LINE_ADDR_W), line:125
|vpiName:ICACHE_SUB_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_TAG_W), line:126
|vpiName:ICACHE_TAG_W
|INT:-2147483648
|vpiParameter:
\_parameter: (ICACHE_WAYS), line:122
|vpiName:ICACHE_WAYS
|INT:1
|vpiParameter:
\_parameter: (ITLB_DEPTH), line:146
|vpiName:ITLB_DEPTH
|INT:32
|vpiParameter:
\_parameter: (ITLB_WAYS), line:145
|vpiName:ITLB_WAYS
|INT:4
|vpiParameter:
\_parameter: (L1_CONNECTIONS), line:177
|vpiName:L1_CONNECTIONS
|INT:9
|vpiParameter:
\_parameter: (L1_DCACHE_ID), line:178
|vpiName:L1_DCACHE_ID
|INT:4
|vpiParameter:
\_parameter: (L1_DMMU_ID), line:179
|vpiName:L1_DMMU_ID
|INT:2
|vpiParameter:
\_parameter: (L1_ICACHE_ID), line:180
|vpiName:L1_ICACHE_ID
|INT:19
|vpiParameter:
\_parameter: (L1_IMMU_ID), line:181
|vpiName:L1_IMMU_ID
|INT:0
|vpiParameter:
\_parameter: (LS_UNIT_WB_ID), line:191
|vpiName:LS_UNIT_WB_ID
|INT:1
|vpiParameter:
\_parameter: (MAX_INFLIGHT_COUNT), line:167
|vpiName:MAX_INFLIGHT_COUNT
|INT:19
|vpiParameter:
\_parameter: (MEMORY_ADDR_H), line:103
|vpiName:MEMORY_ADDR_H
|INT:12
|vpiParameter:
\_parameter: (MEMORY_ADDR_L), line:102
|vpiName:MEMORY_ADDR_L
|INT:11
|vpiParameter:
\_parameter: (MEMORY_BIT_CHECK), line:104
|vpiName:MEMORY_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (MUL_UNIT_WB_ID), line:193
|vpiName:MUL_UNIT_WB_ID
|INT:512
|vpiParameter:
\_parameter: (NUM_UNITS), line:188
|vpiName:NUM_UNITS
|INT:2
|vpiParameter:
\_parameter: (NUM_WB_UNITS), line:186
|vpiName:NUM_WB_UNITS
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (RAS_DEPTH), line:161
|vpiName:RAS_DEPTH
|INT:2
|vpiParameter:
\_parameter: (RESET_VEC), line:39
|vpiName:RESET_VEC
|INT:-2147483648
|vpiParameter:
\_parameter: (SCRATCH_ADDR_H), line:99
|vpiName:SCRATCH_ADDR_H
|INT:9
|vpiParameter:
\_parameter: (SCRATCH_ADDR_L), line:98
|vpiName:SCRATCH_ADDR_L
|INT:8
|vpiParameter:
\_parameter: (SCRATCH_BIT_CHECK), line:100
|vpiName:SCRATCH_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (USE_AMO), line:70
|vpiName:USE_AMO
|INT:1
|vpiParameter:
\_parameter: (USE_BRANCH_PREDICTOR), line:158
|vpiName:USE_BRANCH_PREDICTOR
|INT:2
|vpiParameter:
\_parameter: (USE_BUS), line:88
|vpiName:USE_BUS
|INT:4
|vpiParameter:
\_parameter: (USE_DCACHE), line:92
|vpiName:USE_DCACHE
|INT:6
|vpiParameter:
\_parameter: (USE_DIV), line:49
|vpiName:USE_DIV
|INT:1
|vpiParameter:
\_parameter: (USE_DTAG_INVALIDATIONS), line:140
|vpiName:USE_DTAG_INVALIDATIONS
|INT:1879048191
|vpiParameter:
\_parameter: (USE_D_SCRATCH_MEM), line:79
|vpiName:USE_D_SCRATCH_MEM
|INT:3
|vpiParameter:
\_parameter: (USE_ICACHE), line:93
|vpiName:USE_ICACHE
|INT:7
|vpiParameter:
\_parameter: (USE_I_SCRATCH_MEM), line:78
|vpiName:USE_I_SCRATCH_MEM
|INT:2
|vpiParameter:
\_parameter: (USE_MUL), line:48
|vpiName:USE_MUL
|INT:1
|vpiParameter:
\_parameter: (WB_UNITS_WIDTH), line:187
|vpiName:WB_UNITS_WIDTH
|INT:32
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiParameter:
\_parameter: (i), line:154
|vpiName:i
|INT:6
|vpiGenScopeArray:
\_gen_scope_array: (genblk1[7]), line:154, parent:fetch_block
|vpiName:genblk1[7]
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk1[7]
|vpiGenScope:
\_gen_scope: , parent:genblk1[7]
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk1[7]
|vpiContAssign:
\_cont_assign: , line:155
|vpiRhs:
\_bit_select: (fetch_sub.ready), line:155
|vpiName:fetch_sub.ready
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk1[7].fetch_sub.ready
|vpiIndex:
\_ref_obj: (i), line:155
|vpiName:i
|vpiLhs:
\_bit_select: (unit_ready), line:155
|vpiName:unit_ready
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk1[7].unit_ready
|vpiIndex:
\_ref_obj: (i), line:155
|vpiName:i
|vpiContAssign:
\_cont_assign: , line:156
|vpiRhs:
\_bit_select: (fetch_sub.data_valid), line:156
|vpiName:fetch_sub.data_valid
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk1[7].fetch_sub.data_valid
|vpiIndex:
\_ref_obj: (i), line:156
|vpiName:i
|vpiLhs:
\_bit_select: (unit_data_valid), line:156
|vpiName:unit_data_valid
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk1[7].unit_data_valid
|vpiIndex:
\_ref_obj: (i), line:156
|vpiName:i
|vpiContAssign:
\_cont_assign: , line:157
|vpiRhs:
\_operation: , line:157
|vpiOpType:28
|vpiOperand:
\_ref_obj: (new_mem_request), line:157
|vpiName:new_mem_request
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk1[7].new_mem_request
|vpiOperand:
\_bit_select: (sub_unit_address_match), line:157
|vpiName:sub_unit_address_match
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk1[7].sub_unit_address_match
|vpiIndex:
\_ref_obj: (i), line:157
|vpiName:i
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk1[7].i
|vpiLhs:
\_ref_obj: (fetch_sub[i].new_request), line:157
|vpiName:fetch_sub[i].new_request
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk1[7].fetch_sub[i].new_request
|vpiContAssign:
\_cont_assign: , line:158
|vpiRhs:
\_ref_obj: (tlb.physical_address), line:158
|vpiName:tlb.physical_address
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk1[7].tlb.physical_address
|vpiLhs:
\_ref_obj: (fetch_sub[i].stage1_addr), line:158
|vpiName:fetch_sub[i].stage1_addr
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk1[7].fetch_sub[i].stage1_addr
|vpiContAssign:
\_cont_assign: , line:159
|vpiRhs:
\_ref_obj: (stage2_phys_address), line:159
|vpiName:stage2_phys_address
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk1[7].stage2_phys_address
|vpiLhs:
\_ref_obj: (fetch_sub[i].stage2_addr), line:159
|vpiName:fetch_sub[i].stage2_addr
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk1[7].fetch_sub[i].stage2_addr
|vpiContAssign:
\_cont_assign: , line:160
|vpiRhs:
\_ref_obj: (gc_fetch_flush), line:160
|vpiName:gc_fetch_flush
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk1[7].gc_fetch_flush
|vpiLhs:
\_ref_obj: (fetch_sub[i].flush), line:160
|vpiName:fetch_sub[i].flush
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk1[7].fetch_sub[i].flush
|vpiContAssign:
\_cont_assign: , line:161
|vpiRhs:
\_bit_select: (fetch_sub.data_out), line:161
|vpiName:fetch_sub.data_out
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk1[7].fetch_sub.data_out
|vpiIndex:
\_ref_obj: (i), line:161
|vpiName:i
|vpiLhs:
\_bit_select: (unit_data_array), line:161
|vpiName:unit_data_array
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk1[7].unit_data_array
|vpiIndex:
\_ref_obj: (i), line:161
|vpiName:i
|vpiParameter:
\_parameter: (ALU_UNIT_WB_ID), line:190
|vpiName:ALU_UNIT_WB_ID
|INT:32
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (BRANCH_PREDICTOR_WAYS), line:159
|vpiName:BRANCH_PREDICTOR_WAYS
|INT:9
|vpiParameter:
\_parameter: (BRANCH_TABLE_ENTRIES), line:160
|vpiName:BRANCH_TABLE_ENTRIES
|INT:4
|vpiParameter:
\_parameter: (BRANCH_UNIT_ID), line:195
|vpiName:BRANCH_UNIT_ID
|INT:8
|vpiParameter:
\_parameter: (BUS_ADDR_H), line:107
|vpiName:BUS_ADDR_H
|INT:1
|vpiParameter:
\_parameter: (BUS_ADDR_L), line:106
|vpiName:BUS_ADDR_L
|INT:0
|vpiParameter:
\_parameter: (BUS_BIT_CHECK), line:108
|vpiName:BUS_BIT_CHECK
|INT:1
|vpiParameter:
\_parameter: (BUS_TYPE), line:89
|vpiName:BUS_TYPE
|INT:5
|vpiParameter:
\_parameter: (COUNTER_W), line:42
|vpiName:COUNTER_W
|INT:33
|vpiParameter:
\_parameter: (CPU_ID), line:38
|vpiName:CPU_ID
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_ADDR_WIDTH), line:113
|vpiName:C_M_AXI_ADDR_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_DATA_WIDTH), line:114
|vpiName:C_M_AXI_DATA_WIDTH
|INT:1
|vpiParameter:
\_parameter: (DCACHE_LINES), line:133
|vpiName:DCACHE_LINES
|INT:-2146435073
|vpiParameter:
\_parameter: (DCACHE_LINE_ADDR_W), line:135
|vpiName:DCACHE_LINE_ADDR_W
|INT:1073741824
|vpiParameter:
\_parameter: (DCACHE_LINE_W), line:136
|vpiName:DCACHE_LINE_W
|INT:1342177279
|vpiParameter:
\_parameter: (DCACHE_SUB_LINE_ADDR_W), line:137
|vpiName:DCACHE_SUB_LINE_ADDR_W
|INT:4
|vpiParameter:
\_parameter: (DCACHE_TAG_W), line:138
|vpiName:DCACHE_TAG_W
|INT:1610612736
|vpiParameter:
\_parameter: (DCACHE_WAYS), line:134
|vpiName:DCACHE_WAYS
|INT:4
|vpiParameter:
\_parameter: (DIV_ALGORITHM), line:67
|vpiName:DIV_ALGORITHM
|INT:0
|vpiParameter:
\_parameter: (DIV_UNIT_WB_ID), line:192
|vpiName:DIV_UNIT_WB_ID
|INT:2
|vpiParameter:
\_parameter: (DTLB_DEPTH), line:152
|vpiName:DTLB_DEPTH
|INT:512
|vpiParameter:
\_parameter: (DTLB_WAYS), line:151
|vpiName:DTLB_WAYS
|INT:32
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (ENABLE_M_MODE), line:34
|vpiName:ENABLE_M_MODE
|INT:1
|vpiParameter:
\_parameter: (ENABLE_S_MODE), line:36
|vpiName:ENABLE_S_MODE
|INT:0
|vpiParameter:
\_parameter: (ENABLE_TRACE_INTERFACE), line:172
|vpiName:ENABLE_TRACE_INTERFACE
|INT:2
|vpiParameter:
\_parameter: (FETCH_BUFFER_DEPTH), line:168
|vpiName:FETCH_BUFFER_DEPTH
|INT:512
|vpiParameter:
\_parameter: (FPGA_VENDOR), line:27
|vpiName:FPGA_VENDOR
|STRING:"xilinx"
|vpiParameter:
\_parameter: (GC_UNIT_ID), line:196
|vpiName:GC_UNIT_ID
|INT:4
|vpiParameter:
\_parameter: (ICACHE_LINES), line:121
|vpiName:ICACHE_LINES
|INT:2
|vpiParameter:
\_parameter: (ICACHE_LINE_ADDR_W), line:123
|vpiName:ICACHE_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_LINE_W), line:124
|vpiName:ICACHE_LINE_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_SUB_LINE_ADDR_W), line:125
|vpiName:ICACHE_SUB_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_TAG_W), line:126
|vpiName:ICACHE_TAG_W
|INT:-2147483648
|vpiParameter:
\_parameter: (ICACHE_WAYS), line:122
|vpiName:ICACHE_WAYS
|INT:1
|vpiParameter:
\_parameter: (ITLB_DEPTH), line:146
|vpiName:ITLB_DEPTH
|INT:32
|vpiParameter:
\_parameter: (ITLB_WAYS), line:145
|vpiName:ITLB_WAYS
|INT:4
|vpiParameter:
\_parameter: (L1_CONNECTIONS), line:177
|vpiName:L1_CONNECTIONS
|INT:9
|vpiParameter:
\_parameter: (L1_DCACHE_ID), line:178
|vpiName:L1_DCACHE_ID
|INT:4
|vpiParameter:
\_parameter: (L1_DMMU_ID), line:179
|vpiName:L1_DMMU_ID
|INT:2
|vpiParameter:
\_parameter: (L1_ICACHE_ID), line:180
|vpiName:L1_ICACHE_ID
|INT:19
|vpiParameter:
\_parameter: (L1_IMMU_ID), line:181
|vpiName:L1_IMMU_ID
|INT:0
|vpiParameter:
\_parameter: (LS_UNIT_WB_ID), line:191
|vpiName:LS_UNIT_WB_ID
|INT:1
|vpiParameter:
\_parameter: (MAX_INFLIGHT_COUNT), line:167
|vpiName:MAX_INFLIGHT_COUNT
|INT:19
|vpiParameter:
\_parameter: (MEMORY_ADDR_H), line:103
|vpiName:MEMORY_ADDR_H
|INT:12
|vpiParameter:
\_parameter: (MEMORY_ADDR_L), line:102
|vpiName:MEMORY_ADDR_L
|INT:11
|vpiParameter:
\_parameter: (MEMORY_BIT_CHECK), line:104
|vpiName:MEMORY_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (MUL_UNIT_WB_ID), line:193
|vpiName:MUL_UNIT_WB_ID
|INT:512
|vpiParameter:
\_parameter: (NUM_UNITS), line:188
|vpiName:NUM_UNITS
|INT:2
|vpiParameter:
\_parameter: (NUM_WB_UNITS), line:186
|vpiName:NUM_WB_UNITS
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (RAS_DEPTH), line:161
|vpiName:RAS_DEPTH
|INT:2
|vpiParameter:
\_parameter: (RESET_VEC), line:39
|vpiName:RESET_VEC
|INT:-2147483648
|vpiParameter:
\_parameter: (SCRATCH_ADDR_H), line:99
|vpiName:SCRATCH_ADDR_H
|INT:9
|vpiParameter:
\_parameter: (SCRATCH_ADDR_L), line:98
|vpiName:SCRATCH_ADDR_L
|INT:8
|vpiParameter:
\_parameter: (SCRATCH_BIT_CHECK), line:100
|vpiName:SCRATCH_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (USE_AMO), line:70
|vpiName:USE_AMO
|INT:1
|vpiParameter:
\_parameter: (USE_BRANCH_PREDICTOR), line:158
|vpiName:USE_BRANCH_PREDICTOR
|INT:2
|vpiParameter:
\_parameter: (USE_BUS), line:88
|vpiName:USE_BUS
|INT:4
|vpiParameter:
\_parameter: (USE_DCACHE), line:92
|vpiName:USE_DCACHE
|INT:6
|vpiParameter:
\_parameter: (USE_DIV), line:49
|vpiName:USE_DIV
|INT:1
|vpiParameter:
\_parameter: (USE_DTAG_INVALIDATIONS), line:140
|vpiName:USE_DTAG_INVALIDATIONS
|INT:1879048191
|vpiParameter:
\_parameter: (USE_D_SCRATCH_MEM), line:79
|vpiName:USE_D_SCRATCH_MEM
|INT:3
|vpiParameter:
\_parameter: (USE_ICACHE), line:93
|vpiName:USE_ICACHE
|INT:7
|vpiParameter:
\_parameter: (USE_I_SCRATCH_MEM), line:78
|vpiName:USE_I_SCRATCH_MEM
|INT:2
|vpiParameter:
\_parameter: (USE_MUL), line:48
|vpiName:USE_MUL
|INT:1
|vpiParameter:
\_parameter: (WB_UNITS_WIDTH), line:187
|vpiName:WB_UNITS_WIDTH
|INT:32
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiParameter:
\_parameter: (i), line:154
|vpiName:i
|INT:7
|vpiGenScopeArray:
\_gen_scope_array: (genblk1[8]), line:154, parent:fetch_block
|vpiName:genblk1[8]
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk1[8]
|vpiGenScope:
\_gen_scope: , parent:genblk1[8]
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk1[8]
|vpiContAssign:
\_cont_assign: , line:155
|vpiRhs:
\_bit_select: (fetch_sub.ready), line:155
|vpiName:fetch_sub.ready
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk1[8].fetch_sub.ready
|vpiIndex:
\_ref_obj: (i), line:155
|vpiName:i
|vpiLhs:
\_bit_select: (unit_ready), line:155
|vpiName:unit_ready
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk1[8].unit_ready
|vpiIndex:
\_ref_obj: (i), line:155
|vpiName:i
|vpiContAssign:
\_cont_assign: , line:156
|vpiRhs:
\_bit_select: (fetch_sub.data_valid), line:156
|vpiName:fetch_sub.data_valid
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk1[8].fetch_sub.data_valid
|vpiIndex:
\_ref_obj: (i), line:156
|vpiName:i
|vpiLhs:
\_bit_select: (unit_data_valid), line:156
|vpiName:unit_data_valid
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk1[8].unit_data_valid
|vpiIndex:
\_ref_obj: (i), line:156
|vpiName:i
|vpiContAssign:
\_cont_assign: , line:157
|vpiRhs:
\_operation: , line:157
|vpiOpType:28
|vpiOperand:
\_ref_obj: (new_mem_request), line:157
|vpiName:new_mem_request
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk1[8].new_mem_request
|vpiOperand:
\_bit_select: (sub_unit_address_match), line:157
|vpiName:sub_unit_address_match
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk1[8].sub_unit_address_match
|vpiIndex:
\_ref_obj: (i), line:157
|vpiName:i
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk1[8].i
|vpiLhs:
\_ref_obj: (fetch_sub[i].new_request), line:157
|vpiName:fetch_sub[i].new_request
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk1[8].fetch_sub[i].new_request
|vpiContAssign:
\_cont_assign: , line:158
|vpiRhs:
\_ref_obj: (tlb.physical_address), line:158
|vpiName:tlb.physical_address
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk1[8].tlb.physical_address
|vpiLhs:
\_ref_obj: (fetch_sub[i].stage1_addr), line:158
|vpiName:fetch_sub[i].stage1_addr
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk1[8].fetch_sub[i].stage1_addr
|vpiContAssign:
\_cont_assign: , line:159
|vpiRhs:
\_ref_obj: (stage2_phys_address), line:159
|vpiName:stage2_phys_address
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk1[8].stage2_phys_address
|vpiLhs:
\_ref_obj: (fetch_sub[i].stage2_addr), line:159
|vpiName:fetch_sub[i].stage2_addr
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk1[8].fetch_sub[i].stage2_addr
|vpiContAssign:
\_cont_assign: , line:160
|vpiRhs:
\_ref_obj: (gc_fetch_flush), line:160
|vpiName:gc_fetch_flush
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk1[8].gc_fetch_flush
|vpiLhs:
\_ref_obj: (fetch_sub[i].flush), line:160
|vpiName:fetch_sub[i].flush
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk1[8].fetch_sub[i].flush
|vpiContAssign:
\_cont_assign: , line:161
|vpiRhs:
\_bit_select: (fetch_sub.data_out), line:161
|vpiName:fetch_sub.data_out
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk1[8].fetch_sub.data_out
|vpiIndex:
\_ref_obj: (i), line:161
|vpiName:i
|vpiLhs:
\_bit_select: (unit_data_array), line:161
|vpiName:unit_data_array
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk1[8].unit_data_array
|vpiIndex:
\_ref_obj: (i), line:161
|vpiName:i
|vpiParameter:
\_parameter: (ALU_UNIT_WB_ID), line:190
|vpiName:ALU_UNIT_WB_ID
|INT:32
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (BRANCH_PREDICTOR_WAYS), line:159
|vpiName:BRANCH_PREDICTOR_WAYS
|INT:9
|vpiParameter:
\_parameter: (BRANCH_TABLE_ENTRIES), line:160
|vpiName:BRANCH_TABLE_ENTRIES
|INT:4
|vpiParameter:
\_parameter: (BRANCH_UNIT_ID), line:195
|vpiName:BRANCH_UNIT_ID
|INT:8
|vpiParameter:
\_parameter: (BUS_ADDR_H), line:107
|vpiName:BUS_ADDR_H
|INT:1
|vpiParameter:
\_parameter: (BUS_ADDR_L), line:106
|vpiName:BUS_ADDR_L
|INT:0
|vpiParameter:
\_parameter: (BUS_BIT_CHECK), line:108
|vpiName:BUS_BIT_CHECK
|INT:1
|vpiParameter:
\_parameter: (BUS_TYPE), line:89
|vpiName:BUS_TYPE
|INT:5
|vpiParameter:
\_parameter: (COUNTER_W), line:42
|vpiName:COUNTER_W
|INT:33
|vpiParameter:
\_parameter: (CPU_ID), line:38
|vpiName:CPU_ID
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_ADDR_WIDTH), line:113
|vpiName:C_M_AXI_ADDR_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_DATA_WIDTH), line:114
|vpiName:C_M_AXI_DATA_WIDTH
|INT:1
|vpiParameter:
\_parameter: (DCACHE_LINES), line:133
|vpiName:DCACHE_LINES
|INT:-2146435073
|vpiParameter:
\_parameter: (DCACHE_LINE_ADDR_W), line:135
|vpiName:DCACHE_LINE_ADDR_W
|INT:1073741824
|vpiParameter:
\_parameter: (DCACHE_LINE_W), line:136
|vpiName:DCACHE_LINE_W
|INT:1342177279
|vpiParameter:
\_parameter: (DCACHE_SUB_LINE_ADDR_W), line:137
|vpiName:DCACHE_SUB_LINE_ADDR_W
|INT:4
|vpiParameter:
\_parameter: (DCACHE_TAG_W), line:138
|vpiName:DCACHE_TAG_W
|INT:1610612736
|vpiParameter:
\_parameter: (DCACHE_WAYS), line:134
|vpiName:DCACHE_WAYS
|INT:4
|vpiParameter:
\_parameter: (DIV_ALGORITHM), line:67
|vpiName:DIV_ALGORITHM
|INT:0
|vpiParameter:
\_parameter: (DIV_UNIT_WB_ID), line:192
|vpiName:DIV_UNIT_WB_ID
|INT:2
|vpiParameter:
\_parameter: (DTLB_DEPTH), line:152
|vpiName:DTLB_DEPTH
|INT:512
|vpiParameter:
\_parameter: (DTLB_WAYS), line:151
|vpiName:DTLB_WAYS
|INT:32
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (ENABLE_M_MODE), line:34
|vpiName:ENABLE_M_MODE
|INT:1
|vpiParameter:
\_parameter: (ENABLE_S_MODE), line:36
|vpiName:ENABLE_S_MODE
|INT:0
|vpiParameter:
\_parameter: (ENABLE_TRACE_INTERFACE), line:172
|vpiName:ENABLE_TRACE_INTERFACE
|INT:2
|vpiParameter:
\_parameter: (FETCH_BUFFER_DEPTH), line:168
|vpiName:FETCH_BUFFER_DEPTH
|INT:512
|vpiParameter:
\_parameter: (FPGA_VENDOR), line:27
|vpiName:FPGA_VENDOR
|STRING:"xilinx"
|vpiParameter:
\_parameter: (GC_UNIT_ID), line:196
|vpiName:GC_UNIT_ID
|INT:4
|vpiParameter:
\_parameter: (ICACHE_LINES), line:121
|vpiName:ICACHE_LINES
|INT:2
|vpiParameter:
\_parameter: (ICACHE_LINE_ADDR_W), line:123
|vpiName:ICACHE_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_LINE_W), line:124
|vpiName:ICACHE_LINE_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_SUB_LINE_ADDR_W), line:125
|vpiName:ICACHE_SUB_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_TAG_W), line:126
|vpiName:ICACHE_TAG_W
|INT:-2147483648
|vpiParameter:
\_parameter: (ICACHE_WAYS), line:122
|vpiName:ICACHE_WAYS
|INT:1
|vpiParameter:
\_parameter: (ITLB_DEPTH), line:146
|vpiName:ITLB_DEPTH
|INT:32
|vpiParameter:
\_parameter: (ITLB_WAYS), line:145
|vpiName:ITLB_WAYS
|INT:4
|vpiParameter:
\_parameter: (L1_CONNECTIONS), line:177
|vpiName:L1_CONNECTIONS
|INT:9
|vpiParameter:
\_parameter: (L1_DCACHE_ID), line:178
|vpiName:L1_DCACHE_ID
|INT:4
|vpiParameter:
\_parameter: (L1_DMMU_ID), line:179
|vpiName:L1_DMMU_ID
|INT:2
|vpiParameter:
\_parameter: (L1_ICACHE_ID), line:180
|vpiName:L1_ICACHE_ID
|INT:19
|vpiParameter:
\_parameter: (L1_IMMU_ID), line:181
|vpiName:L1_IMMU_ID
|INT:0
|vpiParameter:
\_parameter: (LS_UNIT_WB_ID), line:191
|vpiName:LS_UNIT_WB_ID
|INT:1
|vpiParameter:
\_parameter: (MAX_INFLIGHT_COUNT), line:167
|vpiName:MAX_INFLIGHT_COUNT
|INT:19
|vpiParameter:
\_parameter: (MEMORY_ADDR_H), line:103
|vpiName:MEMORY_ADDR_H
|INT:12
|vpiParameter:
\_parameter: (MEMORY_ADDR_L), line:102
|vpiName:MEMORY_ADDR_L
|INT:11
|vpiParameter:
\_parameter: (MEMORY_BIT_CHECK), line:104
|vpiName:MEMORY_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (MUL_UNIT_WB_ID), line:193
|vpiName:MUL_UNIT_WB_ID
|INT:512
|vpiParameter:
\_parameter: (NUM_UNITS), line:188
|vpiName:NUM_UNITS
|INT:2
|vpiParameter:
\_parameter: (NUM_WB_UNITS), line:186
|vpiName:NUM_WB_UNITS
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (RAS_DEPTH), line:161
|vpiName:RAS_DEPTH
|INT:2
|vpiParameter:
\_parameter: (RESET_VEC), line:39
|vpiName:RESET_VEC
|INT:-2147483648
|vpiParameter:
\_parameter: (SCRATCH_ADDR_H), line:99
|vpiName:SCRATCH_ADDR_H
|INT:9
|vpiParameter:
\_parameter: (SCRATCH_ADDR_L), line:98
|vpiName:SCRATCH_ADDR_L
|INT:8
|vpiParameter:
\_parameter: (SCRATCH_BIT_CHECK), line:100
|vpiName:SCRATCH_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (USE_AMO), line:70
|vpiName:USE_AMO
|INT:1
|vpiParameter:
\_parameter: (USE_BRANCH_PREDICTOR), line:158
|vpiName:USE_BRANCH_PREDICTOR
|INT:2
|vpiParameter:
\_parameter: (USE_BUS), line:88
|vpiName:USE_BUS
|INT:4
|vpiParameter:
\_parameter: (USE_DCACHE), line:92
|vpiName:USE_DCACHE
|INT:6
|vpiParameter:
\_parameter: (USE_DIV), line:49
|vpiName:USE_DIV
|INT:1
|vpiParameter:
\_parameter: (USE_DTAG_INVALIDATIONS), line:140
|vpiName:USE_DTAG_INVALIDATIONS
|INT:1879048191
|vpiParameter:
\_parameter: (USE_D_SCRATCH_MEM), line:79
|vpiName:USE_D_SCRATCH_MEM
|INT:3
|vpiParameter:
\_parameter: (USE_ICACHE), line:93
|vpiName:USE_ICACHE
|INT:7
|vpiParameter:
\_parameter: (USE_I_SCRATCH_MEM), line:78
|vpiName:USE_I_SCRATCH_MEM
|INT:2
|vpiParameter:
\_parameter: (USE_MUL), line:48
|vpiName:USE_MUL
|INT:1
|vpiParameter:
\_parameter: (WB_UNITS_WIDTH), line:187
|vpiName:WB_UNITS_WIDTH
|INT:32
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiParameter:
\_parameter: (i), line:154
|vpiName:i
|INT:8
|vpiGenScopeArray:
\_gen_scope_array: (genblk2), line:167, parent:fetch_block
|vpiName:genblk2
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk2
|vpiGenScope:
\_gen_scope: , parent:genblk2
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk2
|vpiContAssign:
\_cont_assign: , line:169
|vpiRhs:
\_operation: , line:169
|vpiOpType:32
|vpiOperand:
\_ref_obj: (USE_ICACHE), line:169
|vpiName:USE_ICACHE
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk2.USE_ICACHE
|vpiOperand:
\_operation: , line:169
|vpiOpType:4
|vpiOperand:
\_bit_select: (sub_unit_address_match), line:169
|vpiName:sub_unit_address_match
|vpiIndex:
\_ref_obj: (ICACHE_ID), line:169
|vpiName:ICACHE_ID
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk2.ICACHE_ID
|vpiOperand:
\_constant: , line:169
|vpiConstType:3
|vpiDecompile:'b1
|vpiSize:1
|BIN:1
|vpiLhs:
\_bit_select: (sub_unit_address_match), line:169
|vpiName:sub_unit_address_match
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk2.sub_unit_address_match
|vpiIndex:
\_ref_obj: (BRAM_ID), line:169
|vpiName:BRAM_ID
|vpiModule:
\_module: work@ibram (i_bram), file:third_party/cores/taiga/core/fetch.sv, line:168
|vpiDefName:work@ibram
|vpiName:i_bram
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk2.i_bram
|vpiPort:
\_port: (clk), line:27, parent:i_bram
|vpiName:clk
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (clk), line:168
|vpiName:clk
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (clk), line:27, parent:i_bram
|vpiName:clk
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk2.i_bram.clk
|vpiNetType:36
|vpiPort:
\_port: (rst), line:28, parent:i_bram
|vpiName:rst
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (rst), line:168
|vpiName:rst
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (rst), line:28, parent:i_bram
|vpiName:rst
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk2.i_bram.rst
|vpiNetType:36
|vpiPort:
\_port: (fetch_sub), line:30, parent:i_bram
|vpiName:fetch_sub
|vpiDirection:5
|vpiHighConn:
\_ref_obj: (fetch_sub), line:168
|vpiName:fetch_sub
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_modport: (sub_unit)
|vpiName:sub_unit
|vpiIODecl:
\_io_decl: (stage1_addr)
|vpiName:stage1_addr
|vpiDirection:1
|vpiExpr:
\_logic_net: (stage1_addr), line:228
|vpiName:stage1_addr
|vpiNetType:36
|vpiRange:
\_range: , line:228
|vpiLeftRange:
\_constant: , line:228
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:228
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (stage2_addr)
|vpiName:stage2_addr
|vpiDirection:1
|vpiExpr:
\_logic_net: (stage2_addr), line:229
|vpiName:stage2_addr
|vpiNetType:36
|vpiRange:
\_range: , line:229
|vpiLeftRange:
\_constant: , line:229
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:229
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (new_request)
|vpiName:new_request
|vpiDirection:1
|vpiExpr:
\_logic_net: (new_request), line:234
|vpiName:new_request
|vpiNetType:36
|vpiIODecl:
\_io_decl: (flush)
|vpiName:flush
|vpiDirection:1
|vpiExpr:
\_logic_net: (flush), line:235
|vpiName:flush
|vpiNetType:36
|vpiIODecl:
\_io_decl: (data_out)
|vpiName:data_out
|vpiDirection:2
|vpiExpr:
\_logic_net: (data_out), line:231
|vpiName:data_out
|vpiNetType:36
|vpiRange:
\_range: , line:231
|vpiLeftRange:
\_constant: , line:231
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:231
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (data_valid)
|vpiName:data_valid
|vpiDirection:2
|vpiExpr:
\_logic_net: (data_valid), line:232
|vpiName:data_valid
|vpiNetType:36
|vpiIODecl:
\_io_decl: (ready)
|vpiName:ready
|vpiDirection:2
|vpiExpr:
\_logic_net: (ready), line:233
|vpiName:ready
|vpiNetType:36
|vpiInterface:
\_interface: work@fetch_sub_unit_interface (fetch_sub), file:third_party/cores/taiga/core/fetch.sv, line:168
|vpiDefName:work@fetch_sub_unit_interface
|vpiName:fetch_sub
|vpiModport:
\_modport: (fetch)
|vpiName:fetch
|vpiIODecl:
\_io_decl: (stage1_addr)
|vpiName:stage1_addr
|vpiDirection:2
|vpiExpr:
\_logic_net: (stage1_addr), line:228
|vpiIODecl:
\_io_decl: (stage2_addr)
|vpiName:stage2_addr
|vpiDirection:2
|vpiExpr:
\_logic_net: (stage2_addr), line:229
|vpiIODecl:
\_io_decl: (new_request)
|vpiName:new_request
|vpiDirection:2
|vpiExpr:
\_logic_net: (new_request), line:234
|vpiIODecl:
\_io_decl: (flush)
|vpiName:flush
|vpiDirection:2
|vpiExpr:
\_logic_net: (flush), line:235
|vpiIODecl:
\_io_decl: (data_out)
|vpiName:data_out
|vpiDirection:1
|vpiExpr:
\_logic_net: (data_out), line:231
|vpiIODecl:
\_io_decl: (data_valid)
|vpiName:data_valid
|vpiDirection:1
|vpiExpr:
\_logic_net: (data_valid), line:232
|vpiIODecl:
\_io_decl: (ready)
|vpiName:ready
|vpiDirection:1
|vpiExpr:
\_logic_net: (ready), line:233
|vpiInterface:
\_interface: work@fetch_sub_unit_interface (fetch_sub), file:third_party/cores/taiga/core/fetch.sv, line:168
|vpiModport:
\_modport: (sub_unit)
|vpiPort:
\_port: (instruction_bram), line:31, parent:i_bram
|vpiName:instruction_bram
|vpiDirection:5
|vpiHighConn:
\_ref_obj: (instruction_bram), line:168
|vpiName:instruction_bram
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_modport: (master)
|vpiName:master
|vpiIODecl:
\_io_decl: (addr)
|vpiName:addr
|vpiDirection:2
|vpiExpr:
\_logic_net: (addr), line:25
|vpiName:addr
|vpiNetType:36
|vpiRange:
\_range: , line:25
|vpiLeftRange:
\_constant: , line:25
|vpiConstType:7
|vpiDecompile:29
|vpiSize:32
|INT:29
|vpiRightRange:
\_constant: , line:25
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (en)
|vpiName:en
|vpiDirection:2
|vpiExpr:
\_logic_net: (en), line:26
|vpiName:en
|vpiNetType:36
|vpiIODecl:
\_io_decl: (be)
|vpiName:be
|vpiDirection:2
|vpiExpr:
\_logic_net: (be), line:27
|vpiName:be
|vpiNetType:36
|vpiRange:
\_range: , line:27
|vpiLeftRange:
\_constant: , line:27
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiRightRange:
\_constant: , line:27
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (data_in)
|vpiName:data_in
|vpiDirection:2
|vpiExpr:
\_logic_net: (data_in), line:28
|vpiName:data_in
|vpiNetType:36
|vpiRange:
\_range: , line:28
|vpiLeftRange:
\_constant: , line:28
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:28
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (data_out)
|vpiName:data_out
|vpiDirection:1
|vpiExpr:
\_logic_net: (data_out), line:231
|vpiInterface:
\_interface: work@local_memory_interface (instruction_bram), file:third_party/cores/taiga/core/fetch.sv, line:168
|vpiDefName:work@local_memory_interface
|vpiName:instruction_bram
|vpiModport:
\_modport: (master)
|vpiModport:
\_modport: (slave)
|vpiName:slave
|vpiIODecl:
\_io_decl: (addr)
|vpiName:addr
|vpiDirection:1
|vpiExpr:
\_logic_net: (addr), line:25
|vpiIODecl:
\_io_decl: (en)
|vpiName:en
|vpiDirection:1
|vpiExpr:
\_logic_net: (en), line:26
|vpiIODecl:
\_io_decl: (be)
|vpiName:be
|vpiDirection:1
|vpiExpr:
\_logic_net: (be), line:27
|vpiIODecl:
\_io_decl: (data_in)
|vpiName:data_in
|vpiDirection:1
|vpiExpr:
\_logic_net: (data_in), line:28
|vpiIODecl:
\_io_decl: (data_out)
|vpiName:data_out
|vpiDirection:2
|vpiExpr:
\_logic_net: (data_out), line:231
|vpiInterface:
\_interface: work@local_memory_interface (instruction_bram), file:third_party/cores/taiga/core/fetch.sv, line:168
|vpiNet:
\_logic_net: (clk), line:27, parent:i_bram
|vpiNet:
\_logic_net: (rst), line:28, parent:i_bram
|vpiNet:
\_logic_net: (fetch_sub), line:30, parent:i_bram
|vpiName:fetch_sub
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk2.i_bram.fetch_sub
|vpiNet:
\_logic_net: (instruction_bram), line:31, parent:i_bram
|vpiName:instruction_bram
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk2.i_bram.instruction_bram
|vpiParameter:
\_parameter: (ALU_UNIT_WB_ID), line:190
|vpiName:ALU_UNIT_WB_ID
|INT:32
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (BRANCH_PREDICTOR_WAYS), line:159
|vpiName:BRANCH_PREDICTOR_WAYS
|INT:9
|vpiParameter:
\_parameter: (BRANCH_TABLE_ENTRIES), line:160
|vpiName:BRANCH_TABLE_ENTRIES
|INT:4
|vpiParameter:
\_parameter: (BRANCH_UNIT_ID), line:195
|vpiName:BRANCH_UNIT_ID
|INT:8
|vpiParameter:
\_parameter: (BUS_ADDR_H), line:107
|vpiName:BUS_ADDR_H
|INT:1
|vpiParameter:
\_parameter: (BUS_ADDR_L), line:106
|vpiName:BUS_ADDR_L
|INT:0
|vpiParameter:
\_parameter: (BUS_BIT_CHECK), line:108
|vpiName:BUS_BIT_CHECK
|INT:1
|vpiParameter:
\_parameter: (BUS_TYPE), line:89
|vpiName:BUS_TYPE
|INT:5
|vpiParameter:
\_parameter: (COUNTER_W), line:42
|vpiName:COUNTER_W
|INT:33
|vpiParameter:
\_parameter: (CPU_ID), line:38
|vpiName:CPU_ID
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_ADDR_WIDTH), line:113
|vpiName:C_M_AXI_ADDR_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_DATA_WIDTH), line:114
|vpiName:C_M_AXI_DATA_WIDTH
|INT:1
|vpiParameter:
\_parameter: (DCACHE_LINES), line:133
|vpiName:DCACHE_LINES
|INT:-2146435073
|vpiParameter:
\_parameter: (DCACHE_LINE_ADDR_W), line:135
|vpiName:DCACHE_LINE_ADDR_W
|INT:1073741824
|vpiParameter:
\_parameter: (DCACHE_LINE_W), line:136
|vpiName:DCACHE_LINE_W
|INT:1342177279
|vpiParameter:
\_parameter: (DCACHE_SUB_LINE_ADDR_W), line:137
|vpiName:DCACHE_SUB_LINE_ADDR_W
|INT:4
|vpiParameter:
\_parameter: (DCACHE_TAG_W), line:138
|vpiName:DCACHE_TAG_W
|INT:1610612736
|vpiParameter:
\_parameter: (DCACHE_WAYS), line:134
|vpiName:DCACHE_WAYS
|INT:4
|vpiParameter:
\_parameter: (DIV_ALGORITHM), line:67
|vpiName:DIV_ALGORITHM
|INT:0
|vpiParameter:
\_parameter: (DIV_UNIT_WB_ID), line:192
|vpiName:DIV_UNIT_WB_ID
|INT:2
|vpiParameter:
\_parameter: (DTLB_DEPTH), line:152
|vpiName:DTLB_DEPTH
|INT:512
|vpiParameter:
\_parameter: (DTLB_WAYS), line:151
|vpiName:DTLB_WAYS
|INT:32
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (ENABLE_M_MODE), line:34
|vpiName:ENABLE_M_MODE
|INT:1
|vpiParameter:
\_parameter: (ENABLE_S_MODE), line:36
|vpiName:ENABLE_S_MODE
|INT:0
|vpiParameter:
\_parameter: (ENABLE_TRACE_INTERFACE), line:172
|vpiName:ENABLE_TRACE_INTERFACE
|INT:2
|vpiParameter:
\_parameter: (FETCH_BUFFER_DEPTH), line:168
|vpiName:FETCH_BUFFER_DEPTH
|INT:512
|vpiParameter:
\_parameter: (FPGA_VENDOR), line:27
|vpiName:FPGA_VENDOR
|STRING:"xilinx"
|vpiParameter:
\_parameter: (GC_UNIT_ID), line:196
|vpiName:GC_UNIT_ID
|INT:4
|vpiParameter:
\_parameter: (ICACHE_LINES), line:121
|vpiName:ICACHE_LINES
|INT:2
|vpiParameter:
\_parameter: (ICACHE_LINE_ADDR_W), line:123
|vpiName:ICACHE_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_LINE_W), line:124
|vpiName:ICACHE_LINE_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_SUB_LINE_ADDR_W), line:125
|vpiName:ICACHE_SUB_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_TAG_W), line:126
|vpiName:ICACHE_TAG_W
|INT:-2147483648
|vpiParameter:
\_parameter: (ICACHE_WAYS), line:122
|vpiName:ICACHE_WAYS
|INT:1
|vpiParameter:
\_parameter: (ITLB_DEPTH), line:146
|vpiName:ITLB_DEPTH
|INT:32
|vpiParameter:
\_parameter: (ITLB_WAYS), line:145
|vpiName:ITLB_WAYS
|INT:4
|vpiParameter:
\_parameter: (L1_CONNECTIONS), line:177
|vpiName:L1_CONNECTIONS
|INT:9
|vpiParameter:
\_parameter: (L1_DCACHE_ID), line:178
|vpiName:L1_DCACHE_ID
|INT:4
|vpiParameter:
\_parameter: (L1_DMMU_ID), line:179
|vpiName:L1_DMMU_ID
|INT:2
|vpiParameter:
\_parameter: (L1_ICACHE_ID), line:180
|vpiName:L1_ICACHE_ID
|INT:19
|vpiParameter:
\_parameter: (L1_IMMU_ID), line:181
|vpiName:L1_IMMU_ID
|INT:0
|vpiParameter:
\_parameter: (LS_UNIT_WB_ID), line:191
|vpiName:LS_UNIT_WB_ID
|INT:1
|vpiParameter:
\_parameter: (MAX_INFLIGHT_COUNT), line:167
|vpiName:MAX_INFLIGHT_COUNT
|INT:19
|vpiParameter:
\_parameter: (MEMORY_ADDR_H), line:103
|vpiName:MEMORY_ADDR_H
|INT:12
|vpiParameter:
\_parameter: (MEMORY_ADDR_L), line:102
|vpiName:MEMORY_ADDR_L
|INT:11
|vpiParameter:
\_parameter: (MEMORY_BIT_CHECK), line:104
|vpiName:MEMORY_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (MUL_UNIT_WB_ID), line:193
|vpiName:MUL_UNIT_WB_ID
|INT:512
|vpiParameter:
\_parameter: (NUM_UNITS), line:188
|vpiName:NUM_UNITS
|INT:2
|vpiParameter:
\_parameter: (NUM_WB_UNITS), line:186
|vpiName:NUM_WB_UNITS
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (RAS_DEPTH), line:161
|vpiName:RAS_DEPTH
|INT:2
|vpiParameter:
\_parameter: (RESET_VEC), line:39
|vpiName:RESET_VEC
|INT:-2147483648
|vpiParameter:
\_parameter: (SCRATCH_ADDR_H), line:99
|vpiName:SCRATCH_ADDR_H
|INT:9
|vpiParameter:
\_parameter: (SCRATCH_ADDR_L), line:98
|vpiName:SCRATCH_ADDR_L
|INT:8
|vpiParameter:
\_parameter: (SCRATCH_BIT_CHECK), line:100
|vpiName:SCRATCH_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (USE_AMO), line:70
|vpiName:USE_AMO
|INT:1
|vpiParameter:
\_parameter: (USE_BRANCH_PREDICTOR), line:158
|vpiName:USE_BRANCH_PREDICTOR
|INT:2
|vpiParameter:
\_parameter: (USE_BUS), line:88
|vpiName:USE_BUS
|INT:4
|vpiParameter:
\_parameter: (USE_DCACHE), line:92
|vpiName:USE_DCACHE
|INT:6
|vpiParameter:
\_parameter: (USE_DIV), line:49
|vpiName:USE_DIV
|INT:1
|vpiParameter:
\_parameter: (USE_DTAG_INVALIDATIONS), line:140
|vpiName:USE_DTAG_INVALIDATIONS
|INT:1879048191
|vpiParameter:
\_parameter: (USE_D_SCRATCH_MEM), line:79
|vpiName:USE_D_SCRATCH_MEM
|INT:3
|vpiParameter:
\_parameter: (USE_ICACHE), line:93
|vpiName:USE_ICACHE
|INT:7
|vpiParameter:
\_parameter: (USE_I_SCRATCH_MEM), line:78
|vpiName:USE_I_SCRATCH_MEM
|INT:2
|vpiParameter:
\_parameter: (USE_MUL), line:48
|vpiName:USE_MUL
|INT:1
|vpiParameter:
\_parameter: (WB_UNITS_WIDTH), line:187
|vpiName:WB_UNITS_WIDTH
|INT:32
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiParameter:
\_parameter: (ALU_UNIT_WB_ID), line:190
|vpiName:ALU_UNIT_WB_ID
|INT:32
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (BRANCH_PREDICTOR_WAYS), line:159
|vpiName:BRANCH_PREDICTOR_WAYS
|INT:9
|vpiParameter:
\_parameter: (BRANCH_TABLE_ENTRIES), line:160
|vpiName:BRANCH_TABLE_ENTRIES
|INT:4
|vpiParameter:
\_parameter: (BRANCH_UNIT_ID), line:195
|vpiName:BRANCH_UNIT_ID
|INT:8
|vpiParameter:
\_parameter: (BUS_ADDR_H), line:107
|vpiName:BUS_ADDR_H
|INT:1
|vpiParameter:
\_parameter: (BUS_ADDR_L), line:106
|vpiName:BUS_ADDR_L
|INT:0
|vpiParameter:
\_parameter: (BUS_BIT_CHECK), line:108
|vpiName:BUS_BIT_CHECK
|INT:1
|vpiParameter:
\_parameter: (BUS_TYPE), line:89
|vpiName:BUS_TYPE
|INT:5
|vpiParameter:
\_parameter: (COUNTER_W), line:42
|vpiName:COUNTER_W
|INT:33
|vpiParameter:
\_parameter: (CPU_ID), line:38
|vpiName:CPU_ID
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_ADDR_WIDTH), line:113
|vpiName:C_M_AXI_ADDR_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_DATA_WIDTH), line:114
|vpiName:C_M_AXI_DATA_WIDTH
|INT:1
|vpiParameter:
\_parameter: (DCACHE_LINES), line:133
|vpiName:DCACHE_LINES
|INT:-2146435073
|vpiParameter:
\_parameter: (DCACHE_LINE_ADDR_W), line:135
|vpiName:DCACHE_LINE_ADDR_W
|INT:1073741824
|vpiParameter:
\_parameter: (DCACHE_LINE_W), line:136
|vpiName:DCACHE_LINE_W
|INT:1342177279
|vpiParameter:
\_parameter: (DCACHE_SUB_LINE_ADDR_W), line:137
|vpiName:DCACHE_SUB_LINE_ADDR_W
|INT:4
|vpiParameter:
\_parameter: (DCACHE_TAG_W), line:138
|vpiName:DCACHE_TAG_W
|INT:1610612736
|vpiParameter:
\_parameter: (DCACHE_WAYS), line:134
|vpiName:DCACHE_WAYS
|INT:4
|vpiParameter:
\_parameter: (DIV_ALGORITHM), line:67
|vpiName:DIV_ALGORITHM
|INT:0
|vpiParameter:
\_parameter: (DIV_UNIT_WB_ID), line:192
|vpiName:DIV_UNIT_WB_ID
|INT:2
|vpiParameter:
\_parameter: (DTLB_DEPTH), line:152
|vpiName:DTLB_DEPTH
|INT:512
|vpiParameter:
\_parameter: (DTLB_WAYS), line:151
|vpiName:DTLB_WAYS
|INT:32
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (ENABLE_M_MODE), line:34
|vpiName:ENABLE_M_MODE
|INT:1
|vpiParameter:
\_parameter: (ENABLE_S_MODE), line:36
|vpiName:ENABLE_S_MODE
|INT:0
|vpiParameter:
\_parameter: (ENABLE_TRACE_INTERFACE), line:172
|vpiName:ENABLE_TRACE_INTERFACE
|INT:2
|vpiParameter:
\_parameter: (FETCH_BUFFER_DEPTH), line:168
|vpiName:FETCH_BUFFER_DEPTH
|INT:512
|vpiParameter:
\_parameter: (FPGA_VENDOR), line:27
|vpiName:FPGA_VENDOR
|STRING:"xilinx"
|vpiParameter:
\_parameter: (GC_UNIT_ID), line:196
|vpiName:GC_UNIT_ID
|INT:4
|vpiParameter:
\_parameter: (ICACHE_LINES), line:121
|vpiName:ICACHE_LINES
|INT:2
|vpiParameter:
\_parameter: (ICACHE_LINE_ADDR_W), line:123
|vpiName:ICACHE_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_LINE_W), line:124
|vpiName:ICACHE_LINE_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_SUB_LINE_ADDR_W), line:125
|vpiName:ICACHE_SUB_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_TAG_W), line:126
|vpiName:ICACHE_TAG_W
|INT:-2147483648
|vpiParameter:
\_parameter: (ICACHE_WAYS), line:122
|vpiName:ICACHE_WAYS
|INT:1
|vpiParameter:
\_parameter: (ITLB_DEPTH), line:146
|vpiName:ITLB_DEPTH
|INT:32
|vpiParameter:
\_parameter: (ITLB_WAYS), line:145
|vpiName:ITLB_WAYS
|INT:4
|vpiParameter:
\_parameter: (L1_CONNECTIONS), line:177
|vpiName:L1_CONNECTIONS
|INT:9
|vpiParameter:
\_parameter: (L1_DCACHE_ID), line:178
|vpiName:L1_DCACHE_ID
|INT:4
|vpiParameter:
\_parameter: (L1_DMMU_ID), line:179
|vpiName:L1_DMMU_ID
|INT:2
|vpiParameter:
\_parameter: (L1_ICACHE_ID), line:180
|vpiName:L1_ICACHE_ID
|INT:19
|vpiParameter:
\_parameter: (L1_IMMU_ID), line:181
|vpiName:L1_IMMU_ID
|INT:0
|vpiParameter:
\_parameter: (LS_UNIT_WB_ID), line:191
|vpiName:LS_UNIT_WB_ID
|INT:1
|vpiParameter:
\_parameter: (MAX_INFLIGHT_COUNT), line:167
|vpiName:MAX_INFLIGHT_COUNT
|INT:19
|vpiParameter:
\_parameter: (MEMORY_ADDR_H), line:103
|vpiName:MEMORY_ADDR_H
|INT:12
|vpiParameter:
\_parameter: (MEMORY_ADDR_L), line:102
|vpiName:MEMORY_ADDR_L
|INT:11
|vpiParameter:
\_parameter: (MEMORY_BIT_CHECK), line:104
|vpiName:MEMORY_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (MUL_UNIT_WB_ID), line:193
|vpiName:MUL_UNIT_WB_ID
|INT:512
|vpiParameter:
\_parameter: (NUM_UNITS), line:188
|vpiName:NUM_UNITS
|INT:2
|vpiParameter:
\_parameter: (NUM_WB_UNITS), line:186
|vpiName:NUM_WB_UNITS
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (RAS_DEPTH), line:161
|vpiName:RAS_DEPTH
|INT:2
|vpiParameter:
\_parameter: (RESET_VEC), line:39
|vpiName:RESET_VEC
|INT:-2147483648
|vpiParameter:
\_parameter: (SCRATCH_ADDR_H), line:99
|vpiName:SCRATCH_ADDR_H
|INT:9
|vpiParameter:
\_parameter: (SCRATCH_ADDR_L), line:98
|vpiName:SCRATCH_ADDR_L
|INT:8
|vpiParameter:
\_parameter: (SCRATCH_BIT_CHECK), line:100
|vpiName:SCRATCH_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (USE_AMO), line:70
|vpiName:USE_AMO
|INT:1
|vpiParameter:
\_parameter: (USE_BRANCH_PREDICTOR), line:158
|vpiName:USE_BRANCH_PREDICTOR
|INT:2
|vpiParameter:
\_parameter: (USE_BUS), line:88
|vpiName:USE_BUS
|INT:4
|vpiParameter:
\_parameter: (USE_DCACHE), line:92
|vpiName:USE_DCACHE
|INT:6
|vpiParameter:
\_parameter: (USE_DIV), line:49
|vpiName:USE_DIV
|INT:1
|vpiParameter:
\_parameter: (USE_DTAG_INVALIDATIONS), line:140
|vpiName:USE_DTAG_INVALIDATIONS
|INT:1879048191
|vpiParameter:
\_parameter: (USE_D_SCRATCH_MEM), line:79
|vpiName:USE_D_SCRATCH_MEM
|INT:3
|vpiParameter:
\_parameter: (USE_ICACHE), line:93
|vpiName:USE_ICACHE
|INT:7
|vpiParameter:
\_parameter: (USE_I_SCRATCH_MEM), line:78
|vpiName:USE_I_SCRATCH_MEM
|INT:2
|vpiParameter:
\_parameter: (USE_MUL), line:48
|vpiName:USE_MUL
|INT:1
|vpiParameter:
\_parameter: (WB_UNITS_WIDTH), line:187
|vpiName:WB_UNITS_WIDTH
|INT:32
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiGenScopeArray:
\_gen_scope_array: (genblk3), line:172, parent:fetch_block
|vpiName:genblk3
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk3
|vpiGenScope:
\_gen_scope: , parent:genblk3
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk3
|vpiProcess:
\_always: , line:176
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:176
|vpiCondition:
\_operation: , line:176
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:176
|vpiName:clk
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk3.clk
|vpiStmt:
\_begin: , line:176
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk3
|vpiStmt:
\_if_else: , line:177
|vpiCondition:
\_ref_obj: (flush_or_rst), line:177
|vpiName:flush_or_rst
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk3.flush_or_rst
|vpiStmt:
\_assignment: , line:178
|vpiOpType:82
|vpiLhs:
\_ref_obj: (stage2_valid), line:178
|vpiName:stage2_valid
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk3.stage2_valid
|vpiRhs:
\_constant: , line:178
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiElseStmt:
\_if_else: , line:179
|vpiCondition:
\_ref_obj: (new_mem_request), line:179
|vpiName:new_mem_request
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk3.new_mem_request
|vpiStmt:
\_assignment: , line:180
|vpiOpType:82
|vpiLhs:
\_ref_obj: (stage2_valid), line:180
|vpiName:stage2_valid
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk3.stage2_valid
|vpiRhs:
\_constant: , line:180
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiElseStmt:
\_if_stmt: , line:181
|vpiCondition:
\_ref_obj: (pre_decode_push), line:181
|vpiName:pre_decode_push
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk3.pre_decode_push
|vpiStmt:
\_assignment: , line:182
|vpiOpType:82
|vpiLhs:
\_ref_obj: (stage2_valid), line:182
|vpiName:stage2_valid
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk3.stage2_valid
|vpiRhs:
\_constant: , line:182
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiProcess:
\_always: , line:185
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:185
|vpiCondition:
\_operation: , line:185
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:185
|vpiName:clk
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk3.clk
|vpiStmt:
\_begin: , line:185
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk3
|vpiStmt:
\_if_stmt: , line:186
|vpiCondition:
\_ref_obj: (new_mem_request), line:186
|vpiName:new_mem_request
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk3.new_mem_request
|vpiStmt:
\_assignment: , line:187
|vpiOpType:82
|vpiLhs:
\_ref_obj: (last_sub_unit_id), line:187
|vpiName:last_sub_unit_id
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk3.last_sub_unit_id
|vpiRhs:
\_ref_obj: (sub_unit_address_match), line:187
|vpiName:sub_unit_address_match
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk3.sub_unit_address_match
|vpiProcess:
\_always: , line:191
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:191
|vpiCondition:
\_operation: , line:191
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:191
|vpiName:clk
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk3.clk
|vpiStmt:
\_begin: , line:191
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk3
|vpiStmt:
\_if_else: , line:192
|vpiCondition:
\_ref_obj: (rst), line:192
|vpiName:rst
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk3.rst
|vpiStmt:
\_assignment: , line:193
|vpiOpType:82
|vpiLhs:
\_ref_obj: (delayed_flush), line:193
|vpiName:delayed_flush
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk3.delayed_flush
|vpiRhs:
\_constant: , line:193
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiElseStmt:
\_if_else: , line:194
|vpiCondition:
\_operation: , line:194
|vpiOpType:28
|vpiOperand:
\_operation: , line:194
|vpiOpType:28
|vpiOperand:
\_operation: , line:194
|vpiOpType:28
|vpiOperand:
\_ref_obj: (gc_fetch_flush), line:194
|vpiName:gc_fetch_flush
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk3.gc_fetch_flush
|vpiOperand:
\_ref_obj: (stage2_valid), line:194
|vpiName:stage2_valid
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk3.stage2_valid
|vpiOperand:
\_bit_select: (last_sub_unit_id), line:194
|vpiName:last_sub_unit_id
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk3.last_sub_unit_id
|vpiIndex:
\_ref_obj: (ICACHE_ID), line:194
|vpiName:ICACHE_ID
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk3.ICACHE_ID
|vpiOperand:
\_operation: , line:194
|vpiOpType:4
|vpiOperand:
\_bit_select: (fetch_sub.data_valid), line:194
|vpiName:fetch_sub.data_valid
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk3.fetch_sub.data_valid
|vpiIndex:
\_ref_obj: (ICACHE_ID), line:194
|vpiName:ICACHE_ID
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk3.ICACHE_ID
|vpiStmt:
\_assignment: , line:195
|vpiOpType:82
|vpiLhs:
\_ref_obj: (delayed_flush), line:195
|vpiName:delayed_flush
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk3.delayed_flush
|vpiRhs:
\_constant: , line:195
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiElseStmt:
\_if_stmt: , line:196
|vpiCondition:
\_bit_select: (fetch_sub.data_valid), line:196
|vpiName:fetch_sub.data_valid
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk3.fetch_sub.data_valid
|vpiIndex:
\_ref_obj: (ICACHE_ID), line:196
|vpiName:ICACHE_ID
|vpiStmt:
\_assignment: , line:197
|vpiOpType:82
|vpiLhs:
\_ref_obj: (delayed_flush), line:197
|vpiName:delayed_flush
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk3.delayed_flush
|vpiRhs:
\_constant: , line:197
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiContAssign:
\_cont_assign: , line:174
|vpiRhs:
\_operation: , line:174
|vpiOpType:14
|vpiOperand:
\_ref_obj: (tlb.physical_address), line:174
|vpiName:tlb.physical_address
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk3.tlb.physical_address
|vpiOperand:
\_part_select: , line:174, parent:MEMORY_ADDR_L
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (MEMORY_ADDR_L)
|vpiLeftRange:
\_constant: , line:174
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_operation: , line:174
|vpiOpType:11
|vpiOperand:
\_constant: , line:174
|vpiConstType:7
|vpiDecompile:32
|vpiSize:32
|INT:32
|vpiOperand:
\_ref_obj: (MEMORY_BIT_CHECK), line:174
|vpiName:MEMORY_BIT_CHECK
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk3.MEMORY_BIT_CHECK
|vpiLhs:
\_bit_select: (sub_unit_address_match), line:174
|vpiName:sub_unit_address_match
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk3.sub_unit_address_match
|vpiIndex:
\_ref_obj: (ICACHE_ID), line:174
|vpiName:ICACHE_ID
|vpiContAssign:
\_cont_assign: , line:200
|vpiRhs:
\_constant: , line:200
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiLhs:
\_ref_obj: (delayed_flush), line:200
|vpiName:delayed_flush
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk3.delayed_flush
|vpiModule:
\_module: work@icache (i_cache), file:third_party/cores/taiga/core/fetch.sv, line:173
|vpiDefName:work@icache
|vpiName:i_cache
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk3.i_cache
|vpiPort:
\_port: (clk), line:27, parent:i_cache
|vpiName:clk
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (clk), line:173
|vpiName:clk
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (clk), line:27, parent:i_cache
|vpiName:clk
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk3.i_cache.clk
|vpiNetType:36
|vpiPort:
\_port: (rst), line:28, parent:i_cache
|vpiName:rst
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (rst), line:173
|vpiName:rst
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (rst), line:28, parent:i_cache
|vpiName:rst
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk3.i_cache.rst
|vpiNetType:36
|vpiPort:
\_port: (icache_on), line:29, parent:i_cache
|vpiName:icache_on
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (icache_on), line:173
|vpiName:icache_on
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (icache_on), line:29, parent:i_cache
|vpiName:icache_on
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk3.i_cache.icache_on
|vpiNetType:36
|vpiPort:
\_port: (l1_request), line:30, parent:i_cache
|vpiName:l1_request
|vpiDirection:5
|vpiHighConn:
\_ref_obj: (l1_request), line:173
|vpiName:l1_request
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_modport: (master)
|vpiName:master
|vpiIODecl:
\_io_decl: (addr)
|vpiName:addr
|vpiDirection:2
|vpiExpr:
\_logic_net: (addr), line:123
|vpiName:addr
|vpiNetType:36
|vpiRange:
\_range: , line:123
|vpiLeftRange:
\_constant: , line:123
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:123
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (data)
|vpiName:data
|vpiDirection:2
|vpiExpr:
\_logic_net: (data), line:124
|vpiName:data
|vpiNetType:36
|vpiRange:
\_range: , line:124
|vpiLeftRange:
\_constant: , line:124
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:124
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (rnw)
|vpiName:rnw
|vpiDirection:2
|vpiExpr:
\_logic_net: (rnw), line:125
|vpiName:rnw
|vpiNetType:36
|vpiIODecl:
\_io_decl: (be)
|vpiName:be
|vpiDirection:2
|vpiExpr:
\_logic_net: (be), line:126
|vpiName:be
|vpiNetType:36
|vpiRange:
\_range: , line:126
|vpiLeftRange:
\_constant: , line:126
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiRightRange:
\_constant: , line:126
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (size)
|vpiName:size
|vpiDirection:2
|vpiExpr:
\_logic_net: (size), line:127
|vpiName:size
|vpiNetType:36
|vpiRange:
\_range: , line:127
|vpiLeftRange:
\_constant: , line:127
|vpiConstType:7
|vpiDecompile:4
|vpiSize:32
|INT:4
|vpiRightRange:
\_constant: , line:127
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (is_amo)
|vpiName:is_amo
|vpiDirection:2
|vpiExpr:
\_logic_net: (is_amo), line:128
|vpiName:is_amo
|vpiNetType:36
|vpiIODecl:
\_io_decl: (amo)
|vpiName:amo
|vpiDirection:2
|vpiExpr:
\_logic_net: (amo), line:129
|vpiName:amo
|vpiNetType:36
|vpiRange:
\_range: , line:129
|vpiLeftRange:
\_constant: , line:129
|vpiConstType:7
|vpiDecompile:4
|vpiSize:32
|INT:4
|vpiRightRange:
\_constant: , line:129
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (request)
|vpiName:request
|vpiDirection:2
|vpiExpr:
\_logic_net: (request), line:131
|vpiName:request
|vpiNetType:36
|vpiIODecl:
\_io_decl: (ack)
|vpiName:ack
|vpiDirection:1
|vpiExpr:
\_logic_net: (ack), line:132
|vpiName:ack
|vpiNetType:36
|vpiInterface:
\_interface: work@l1_arbiter_request_interface (l1_request), file:third_party/cores/taiga/core/fetch.sv, line:173
|vpiDefName:work@l1_arbiter_request_interface
|vpiName:l1_request
|vpiModport:
\_modport: (master)
|vpiModport:
\_modport: (slave)
|vpiName:slave
|vpiIODecl:
\_io_decl: (addr)
|vpiName:addr
|vpiDirection:1
|vpiExpr:
\_logic_net: (addr), line:123
|vpiIODecl:
\_io_decl: (data)
|vpiName:data
|vpiDirection:1
|vpiExpr:
\_logic_net: (data), line:124
|vpiIODecl:
\_io_decl: (rnw)
|vpiName:rnw
|vpiDirection:1
|vpiExpr:
\_logic_net: (rnw), line:125
|vpiIODecl:
\_io_decl: (be)
|vpiName:be
|vpiDirection:1
|vpiExpr:
\_logic_net: (be), line:126
|vpiIODecl:
\_io_decl: (size)
|vpiName:size
|vpiDirection:1
|vpiExpr:
\_logic_net: (size), line:127
|vpiIODecl:
\_io_decl: (is_amo)
|vpiName:is_amo
|vpiDirection:1
|vpiExpr:
\_logic_net: (is_amo), line:128
|vpiIODecl:
\_io_decl: (amo)
|vpiName:amo
|vpiDirection:1
|vpiExpr:
\_logic_net: (amo), line:129
|vpiIODecl:
\_io_decl: (request)
|vpiName:request
|vpiDirection:1
|vpiExpr:
\_logic_net: (request), line:131
|vpiIODecl:
\_io_decl: (ack)
|vpiName:ack
|vpiDirection:2
|vpiExpr:
\_logic_net: (ack), line:132
|vpiInterface:
\_interface: work@l1_arbiter_request_interface (l1_request), file:third_party/cores/taiga/core/fetch.sv, line:173
|vpiPort:
\_port: (l1_response), line:31, parent:i_cache
|vpiName:l1_response
|vpiDirection:5
|vpiHighConn:
\_ref_obj: (l1_response), line:173
|vpiName:l1_response
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_modport: (master)
|vpiName:master
|vpiIODecl:
\_io_decl: (inv_addr)
|vpiName:inv_addr
|vpiDirection:1
|vpiExpr:
\_logic_net: (inv_addr), line:149
|vpiName:inv_addr
|vpiNetType:36
|vpiRange:
\_range: , line:149
|vpiLeftRange:
\_constant: , line:149
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:149
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiIODecl:
\_io_decl: (inv_valid)
|vpiName:inv_valid
|vpiDirection:1
|vpiExpr:
\_logic_net: (inv_valid), line:150
|vpiName:inv_valid
|vpiNetType:36
|vpiIODecl:
\_io_decl: (data)
|vpiName:data
|vpiDirection:1
|vpiExpr:
\_logic_net: (data), line:124
|vpiIODecl:
\_io_decl: (data_valid)
|vpiName:data_valid
|vpiDirection:1
|vpiExpr:
\_logic_net: (data_valid), line:153
|vpiName:data_valid
|vpiNetType:36
|vpiIODecl:
\_io_decl: (inv_ack)
|vpiName:inv_ack
|vpiDirection:2
|vpiExpr:
\_logic_net: (inv_ack), line:151
|vpiName:inv_ack
|vpiNetType:36
|vpiInterface:
\_interface: work@l1_arbiter_return_interface (l1_response), file:third_party/cores/taiga/core/fetch.sv, line:173
|vpiDefName:work@l1_arbiter_return_interface
|vpiName:l1_response
|vpiModport:
\_modport: (master)
|vpiModport:
\_modport: (slave)
|vpiName:slave
|vpiIODecl:
\_io_decl: (inv_addr)
|vpiName:inv_addr
|vpiDirection:2
|vpiExpr:
\_logic_net: (inv_addr), line:149
|vpiIODecl:
\_io_decl: (inv_valid)
|vpiName:inv_valid
|vpiDirection:2
|vpiExpr:
\_logic_net: (inv_valid), line:150
|vpiIODecl:
\_io_decl: (data)
|vpiName:data
|vpiDirection:2
|vpiExpr:
\_logic_net: (data), line:124
|vpiIODecl:
\_io_decl: (data_valid)
|vpiName:data_valid
|vpiDirection:2
|vpiExpr:
\_logic_net: (data_valid), line:153
|vpiIODecl:
\_io_decl: (inv_ack)
|vpiName:inv_ack
|vpiDirection:1
|vpiExpr:
\_logic_net: (inv_ack), line:151
|vpiInterface:
\_interface: work@l1_arbiter_return_interface (l1_response), file:third_party/cores/taiga/core/fetch.sv, line:173
|vpiPort:
\_port: (fetch_sub), line:33, parent:i_cache
|vpiName:fetch_sub
|vpiDirection:5
|vpiHighConn:
\_ref_obj: (fetch_sub), line:173
|vpiName:fetch_sub
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_modport: (sub_unit)
|vpiName:sub_unit
|vpiIODecl:
\_io_decl: (stage1_addr)
|vpiName:stage1_addr
|vpiDirection:1
|vpiExpr:
\_logic_net: (stage1_addr), line:228
|vpiName:stage1_addr
|vpiNetType:36
|vpiRange:
\_range: , line:228
|vpiLeftRange:
\_constant: , line:228
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:228
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (stage2_addr)
|vpiName:stage2_addr
|vpiDirection:1
|vpiExpr:
\_logic_net: (stage2_addr), line:229
|vpiName:stage2_addr
|vpiNetType:36
|vpiRange:
\_range: , line:229
|vpiLeftRange:
\_constant: , line:229
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:229
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (new_request)
|vpiName:new_request
|vpiDirection:1
|vpiExpr:
\_logic_net: (new_request), line:234
|vpiName:new_request
|vpiNetType:36
|vpiIODecl:
\_io_decl: (flush)
|vpiName:flush
|vpiDirection:1
|vpiExpr:
\_logic_net: (flush), line:235
|vpiName:flush
|vpiNetType:36
|vpiIODecl:
\_io_decl: (data_out)
|vpiName:data_out
|vpiDirection:2
|vpiExpr:
\_logic_net: (data_out), line:231
|vpiName:data_out
|vpiNetType:36
|vpiRange:
\_range: , line:231
|vpiLeftRange:
\_constant: , line:231
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:231
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (data_valid)
|vpiName:data_valid
|vpiDirection:2
|vpiExpr:
\_logic_net: (data_valid), line:153
|vpiIODecl:
\_io_decl: (ready)
|vpiName:ready
|vpiDirection:2
|vpiExpr:
\_logic_net: (ready), line:233
|vpiName:ready
|vpiNetType:36
|vpiInterface:
\_interface: work@fetch_sub_unit_interface (fetch_sub), file:third_party/cores/taiga/core/fetch.sv, line:173
|vpiDefName:work@fetch_sub_unit_interface
|vpiName:fetch_sub
|vpiModport:
\_modport: (fetch)
|vpiName:fetch
|vpiIODecl:
\_io_decl: (stage1_addr)
|vpiName:stage1_addr
|vpiDirection:2
|vpiExpr:
\_logic_net: (stage1_addr), line:228
|vpiIODecl:
\_io_decl: (stage2_addr)
|vpiName:stage2_addr
|vpiDirection:2
|vpiExpr:
\_logic_net: (stage2_addr), line:229
|vpiIODecl:
\_io_decl: (new_request)
|vpiName:new_request
|vpiDirection:2
|vpiExpr:
\_logic_net: (new_request), line:234
|vpiIODecl:
\_io_decl: (flush)
|vpiName:flush
|vpiDirection:2
|vpiExpr:
\_logic_net: (flush), line:235
|vpiIODecl:
\_io_decl: (data_out)
|vpiName:data_out
|vpiDirection:1
|vpiExpr:
\_logic_net: (data_out), line:231
|vpiIODecl:
\_io_decl: (data_valid)
|vpiName:data_valid
|vpiDirection:1
|vpiExpr:
\_logic_net: (data_valid), line:153
|vpiIODecl:
\_io_decl: (ready)
|vpiName:ready
|vpiDirection:1
|vpiExpr:
\_logic_net: (ready), line:233
|vpiInterface:
\_interface: work@fetch_sub_unit_interface (fetch_sub), file:third_party/cores/taiga/core/fetch.sv, line:173
|vpiModport:
\_modport: (sub_unit)
|vpiModule:
\_module: work@cycler (replacement_policy), file:third_party/cores/taiga/core/icache.sv, line:110, parent:i_cache
|vpiDefName:work@cycler
|vpiName:replacement_policy
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk3.i_cache.replacement_policy
|vpiPort:
\_port: (clk), line:29, parent:replacement_policy
|vpiName:clk
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (clk), line:110
|vpiName:clk
|vpiActual:
\_logic_net: (clk), line:27, parent:i_cache
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (clk), line:29, parent:replacement_policy
|vpiName:clk
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk3.i_cache.replacement_policy.clk
|vpiNetType:36
|vpiPort:
\_port: (rst), line:30, parent:replacement_policy
|vpiName:rst
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (rst), line:110
|vpiName:rst
|vpiActual:
\_logic_net: (rst), line:28, parent:i_cache
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (rst), line:30, parent:replacement_policy
|vpiName:rst
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk3.i_cache.replacement_policy.rst
|vpiNetType:36
|vpiPort:
\_port: (en), line:31, parent:replacement_policy
|vpiName:en
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (en), line:110
|vpiName:en
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (en), line:31, parent:replacement_policy
|vpiName:en
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk3.i_cache.replacement_policy.en
|vpiNetType:36
|vpiPort:
\_port: (one_hot), line:32, parent:replacement_policy
|vpiName:one_hot
|vpiDirection:2
|vpiHighConn:
\_ref_obj: (one_hot), line:110
|vpiName:one_hot
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (one_hot), line:32, parent:replacement_policy
|vpiName:one_hot
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk3.i_cache.replacement_policy.one_hot
|vpiNetType:36
|vpiRange:
\_range: , line:32
|vpiLeftRange:
\_constant: , line:32
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiRightRange:
\_constant: , line:32
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiGenScopeArray:
\_gen_scope_array: (genblk1), line:36, parent:replacement_policy
|vpiName:genblk1
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk3.i_cache.replacement_policy.genblk1
|vpiGenScope:
\_gen_scope: , parent:genblk1
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk3.i_cache.replacement_policy.genblk1
|vpiProcess:
\_always: , line:40
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:40
|vpiCondition:
\_operation: , line:40
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:40
|vpiName:clk
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk3.i_cache.replacement_policy.genblk1.clk
|vpiStmt:
\_begin: , line:40
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk3.i_cache.replacement_policy.genblk1
|vpiStmt:
\_if_else: , line:41
|vpiCondition:
\_ref_obj: (rst), line:41
|vpiName:rst
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk3.i_cache.replacement_policy.genblk1.rst
|vpiStmt:
\_assignment: , line:42
|vpiOpType:82
|vpiLhs:
\_ref_obj: (one_hot), line:42
|vpiName:one_hot
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk3.i_cache.replacement_policy.genblk1.one_hot
|vpiRhs:
\_constant: , line:42
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiElseStmt:
\_if_stmt: , line:43
|vpiCondition:
\_ref_obj: (en), line:43
|vpiName:en
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk3.i_cache.replacement_policy.genblk1.en
|vpiStmt:
\_assignment: , line:44
|vpiOpType:82
|vpiLhs:
\_ref_obj: (one_hot), line:44
|vpiName:one_hot
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk3.i_cache.replacement_policy.genblk1.one_hot
|vpiRhs:
\_operation: , line:44
|vpiOpType:33
|vpiOperand:
\_part_select: , line:44, parent:one_hot
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (one_hot)
|vpiLeftRange:
\_operation: , line:44
|vpiOpType:11
|vpiOperand:
\_ref_obj: (C_WIDTH), line:44
|vpiName:C_WIDTH
|vpiOperand:
\_constant: , line:44
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiRightRange:
\_constant: , line:44
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiOperand:
\_bit_select: (one_hot), line:44
|vpiName:one_hot
|vpiIndex:
\_operation: , line:44
|vpiOpType:11
|vpiOperand:
\_ref_obj: (C_WIDTH), line:44
|vpiName:C_WIDTH
|vpiOperand:
\_constant: , line:44
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiContAssign:
\_cont_assign: , line:37
|vpiRhs:
\_constant: , line:37
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiLhs:
\_ref_obj: (one_hot), line:37
|vpiName:one_hot
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk3.i_cache.replacement_policy.genblk1.one_hot
|vpiNet:
\_logic_net: (clk), line:29, parent:replacement_policy
|vpiNet:
\_logic_net: (rst), line:30, parent:replacement_policy
|vpiNet:
\_logic_net: (en), line:31, parent:replacement_policy
|vpiNet:
\_logic_net: (one_hot), line:32, parent:replacement_policy
|vpiInstance:
\_module: work@icache (i_cache), file:third_party/cores/taiga/core/fetch.sv, line:173
|vpiParameter:
\_parameter: (C_WIDTH), line:110
|vpiName:C_WIDTH
|INT:1
|vpiModule:
\_module: work@itag_banks (icache_tag_banks), file:third_party/cores/taiga/core/icache.sv, line:119, parent:i_cache
|vpiDefName:work@itag_banks
|vpiName:icache_tag_banks
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk3.i_cache.icache_tag_banks
|vpiPort:
\_port: (clk), line:27, parent:icache_tag_banks
|vpiName:clk
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (clk), line:119
|vpiName:clk
|vpiActual:
\_logic_net: (clk), line:27, parent:i_cache
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (clk), line:27, parent:icache_tag_banks
|vpiName:clk
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk3.i_cache.icache_tag_banks.clk
|vpiNetType:36
|vpiPort:
\_port: (rst), line:28, parent:icache_tag_banks
|vpiName:rst
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (rst), line:119
|vpiName:rst
|vpiActual:
\_logic_net: (rst), line:28, parent:i_cache
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (rst), line:28, parent:icache_tag_banks
|vpiName:rst
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk3.i_cache.icache_tag_banks.rst
|vpiNetType:36
|vpiPort:
\_port: (stage1_addr), line:30, parent:icache_tag_banks
|vpiName:stage1_addr
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (stage1_addr), line:119
|vpiName:stage1_addr
|vpiActual:
\_logic_net: (stage1_addr), line:228
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (stage1_addr), line:30, parent:icache_tag_banks
|vpiName:stage1_addr
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk3.i_cache.icache_tag_banks.stage1_addr
|vpiNetType:36
|vpiRange:
\_range: , line:30
|vpiLeftRange:
\_constant: , line:30
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:30
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiPort:
\_port: (stage2_addr), line:31, parent:icache_tag_banks
|vpiName:stage2_addr
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (stage2_addr), line:119
|vpiName:stage2_addr
|vpiActual:
\_logic_net: (stage2_addr), line:229
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (stage2_addr), line:31, parent:icache_tag_banks
|vpiName:stage2_addr
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk3.i_cache.icache_tag_banks.stage2_addr
|vpiNetType:36
|vpiRange:
\_range: , line:31
|vpiLeftRange:
\_constant: , line:31
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:31
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiPort:
\_port: (update_way), line:33, parent:icache_tag_banks
|vpiName:update_way
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (update_way), line:119
|vpiName:update_way
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (update_way), line:33, parent:icache_tag_banks
|vpiName:update_way
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk3.i_cache.icache_tag_banks.update_way
|vpiNetType:36
|vpiRange:
\_range: , line:33
|vpiLeftRange:
\_constant: , line:33
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiRightRange:
\_constant: , line:33
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiPort:
\_port: (update), line:34, parent:icache_tag_banks
|vpiName:update
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (update), line:119
|vpiName:update
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (update), line:34, parent:icache_tag_banks
|vpiName:update
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk3.i_cache.icache_tag_banks.update
|vpiNetType:36
|vpiPort:
\_port: (stage1_adv), line:36, parent:icache_tag_banks
|vpiName:stage1_adv
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (stage1_adv), line:119
|vpiName:stage1_adv
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (stage1_adv), line:36, parent:icache_tag_banks
|vpiName:stage1_adv
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk3.i_cache.icache_tag_banks.stage1_adv
|vpiNetType:36
|vpiPort:
\_port: (tag_hit), line:38, parent:icache_tag_banks
|vpiName:tag_hit
|vpiDirection:2
|vpiHighConn:
\_ref_obj: (tag_hit), line:119
|vpiName:tag_hit
|vpiActual:
\_logic_net: (tag_hit), line:36, parent:i_cache
|vpiName:tag_hit
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk3.i_cache.tag_hit
|vpiNetType:36
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (tag_hit), line:38, parent:icache_tag_banks
|vpiName:tag_hit
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk3.i_cache.icache_tag_banks.tag_hit
|vpiPort:
\_port: (tag_hit_way), line:39, parent:icache_tag_banks
|vpiName:tag_hit_way
|vpiDirection:2
|vpiHighConn:
\_ref_obj: (tag_hit_way), line:119
|vpiName:tag_hit_way
|vpiActual:
\_logic_net: (tag_hit_way), line:37, parent:i_cache
|vpiName:tag_hit_way
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk3.i_cache.tag_hit_way
|vpiNetType:36
|vpiRange:
\_range: , line:37
|vpiLeftRange:
\_constant: , line:37
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiRightRange:
\_constant: , line:37
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (tag_hit_way), line:39, parent:icache_tag_banks
|vpiName:tag_hit_way
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk3.i_cache.icache_tag_banks.tag_hit_way
|vpiNetType:36
|vpiRange:
\_range: , line:39
|vpiLeftRange:
\_constant: , line:39
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiRightRange:
\_constant: , line:39
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiGenScopeArray:
\_gen_scope_array: (tag_bank_gen[0]), line:68, parent:icache_tag_banks
|vpiName:tag_bank_gen[0]
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk3.i_cache.icache_tag_banks.tag_bank_gen[0]
|vpiGenScope:
\_gen_scope: , parent:tag_bank_gen[0]
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk3.i_cache.icache_tag_banks.tag_bank_gen[0]
|vpiContAssign:
\_cont_assign: , line:80
|vpiRhs:
\_operation: , line:80
|vpiOpType:14
|vpiOperand:
\_operation: , line:80
|vpiOpType:33
|vpiOperand:
\_ref_obj: (hit_allowed), line:80
|vpiName:hit_allowed
|vpiOperand:
\_ref_obj: (stage2_tag), line:80
|vpiName:stage2_tag
|vpiOperand:
\_operation: , line:80
|vpiOpType:33
|vpiOperand:
\_constant: , line:80
|vpiConstType:3
|vpiDecompile:'b1
|vpiSize:1
|BIN:1
|vpiOperand:
\_bit_select: (tag_line), line:80
|vpiName:tag_line
|vpiIndex:
\_ref_obj: (i), line:80
|vpiName:i
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk3.i_cache.icache_tag_banks.tag_bank_gen[0].i
|vpiLhs:
\_bit_select: (tag_hit_way), line:80
|vpiName:tag_hit_way
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk3.i_cache.icache_tag_banks.tag_bank_gen[0].tag_hit_way
|vpiIndex:
\_ref_obj: (i), line:80
|vpiName:i
|vpiModule:
\_module: work@tag_bank (itag_bank), file:third_party/cores/taiga/core/itag_banks.sv, line:70
|vpiDefName:work@tag_bank
|vpiName:itag_bank
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk3.i_cache.icache_tag_banks.tag_bank_gen[0].itag_bank
|vpiPort:
\_port: (clk), line:32, parent:itag_bank
|vpiName:clk
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (clk), line:70
|vpiName:clk
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (clk), line:32, parent:itag_bank
|vpiName:clk
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk3.i_cache.icache_tag_banks.tag_bank_gen[0].itag_bank.clk
|vpiNetType:36
|vpiPort:
\_port: (rst), line:33, parent:itag_bank
|vpiName:rst
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (rst), line:70
|vpiName:rst
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (rst), line:33, parent:itag_bank
|vpiName:rst
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk3.i_cache.icache_tag_banks.tag_bank_gen[0].itag_bank.rst
|vpiNetType:36
|vpiPort:
\_port: (addr_a), line:35, parent:itag_bank
|vpiName:addr_a
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (addr_a), line:70
|vpiName:addr_a
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (addr_a), line:35, parent:itag_bank
|vpiName:addr_a
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk3.i_cache.icache_tag_banks.tag_bank_gen[0].itag_bank.addr_a
|vpiNetType:36
|vpiRange:
\_range: , line:35
|vpiLeftRange:
\_constant: , line:35
|vpiConstType:7
|vpiDecompile:8
|vpiSize:32
|INT:8
|vpiRightRange:
\_constant: , line:35
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiPort:
\_port: (addr_b), line:36, parent:itag_bank
|vpiName:addr_b
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (addr_b), line:70
|vpiName:addr_b
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (addr_b), line:36, parent:itag_bank
|vpiName:addr_b
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk3.i_cache.icache_tag_banks.tag_bank_gen[0].itag_bank.addr_b
|vpiNetType:36
|vpiRange:
\_range: , line:36
|vpiLeftRange:
\_constant: , line:36
|vpiConstType:7
|vpiDecompile:8
|vpiSize:32
|INT:8
|vpiRightRange:
\_constant: , line:36
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiPort:
\_port: (en_a), line:37, parent:itag_bank
|vpiName:en_a
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (en_a), line:70
|vpiName:en_a
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (en_a), line:37, parent:itag_bank
|vpiName:en_a
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk3.i_cache.icache_tag_banks.tag_bank_gen[0].itag_bank.en_a
|vpiNetType:36
|vpiPort:
\_port: (en_b), line:38, parent:itag_bank
|vpiName:en_b
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (en_b), line:70
|vpiName:en_b
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (en_b), line:38, parent:itag_bank
|vpiName:en_b
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk3.i_cache.icache_tag_banks.tag_bank_gen[0].itag_bank.en_b
|vpiNetType:36
|vpiPort:
\_port: (wen_a), line:39, parent:itag_bank
|vpiName:wen_a
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (wen_a), line:70
|vpiName:wen_a
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (wen_a), line:39, parent:itag_bank
|vpiName:wen_a
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk3.i_cache.icache_tag_banks.tag_bank_gen[0].itag_bank.wen_a
|vpiNetType:36
|vpiPort:
\_port: (wen_b), line:40, parent:itag_bank
|vpiName:wen_b
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (wen_b), line:70
|vpiName:wen_b
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (wen_b), line:40, parent:itag_bank
|vpiName:wen_b
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk3.i_cache.icache_tag_banks.tag_bank_gen[0].itag_bank.wen_b
|vpiNetType:36
|vpiPort:
\_port: (data_in_a), line:41, parent:itag_bank
|vpiName:data_in_a
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (data_in_a), line:70
|vpiName:data_in_a
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (data_in_a), line:41, parent:itag_bank
|vpiName:data_in_a
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk3.i_cache.icache_tag_banks.tag_bank_gen[0].itag_bank.data_in_a
|vpiNetType:36
|vpiRange:
\_range: , line:41
|vpiLeftRange:
\_constant: , line:41
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:41
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiPort:
\_port: (data_in_b), line:42, parent:itag_bank
|vpiName:data_in_b
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (data_in_b), line:70
|vpiName:data_in_b
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (data_in_b), line:42, parent:itag_bank
|vpiName:data_in_b
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk3.i_cache.icache_tag_banks.tag_bank_gen[0].itag_bank.data_in_b
|vpiNetType:36
|vpiRange:
\_range: , line:42
|vpiLeftRange:
\_constant: , line:42
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:42
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiPort:
\_port: (data_out_a), line:43, parent:itag_bank
|vpiName:data_out_a
|vpiDirection:2
|vpiHighConn:
\_ref_obj: (data_out_a), line:70
|vpiName:data_out_a
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (data_out_a), line:43, parent:itag_bank
|vpiName:data_out_a
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk3.i_cache.icache_tag_banks.tag_bank_gen[0].itag_bank.data_out_a
|vpiNetType:36
|vpiRange:
\_range: , line:43
|vpiLeftRange:
\_constant: , line:43
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:43
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiPort:
\_port: (data_out_b), line:44, parent:itag_bank
|vpiName:data_out_b
|vpiDirection:2
|vpiHighConn:
\_ref_obj: (data_out_b), line:70
|vpiName:data_out_b
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (data_out_b), line:44, parent:itag_bank
|vpiName:data_out_b
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk3.i_cache.icache_tag_banks.tag_bank_gen[0].itag_bank.data_out_b
|vpiNetType:36
|vpiRange:
\_range: , line:44
|vpiLeftRange:
\_constant: , line:44
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:44
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (clk), line:32, parent:itag_bank
|vpiNet:
\_logic_net: (rst), line:33, parent:itag_bank
|vpiNet:
\_logic_net: (addr_a), line:35, parent:itag_bank
|vpiNet:
\_logic_net: (addr_b), line:36, parent:itag_bank
|vpiNet:
\_logic_net: (en_a), line:37, parent:itag_bank
|vpiNet:
\_logic_net: (en_b), line:38, parent:itag_bank
|vpiNet:
\_logic_net: (wen_a), line:39, parent:itag_bank
|vpiNet:
\_logic_net: (wen_b), line:40, parent:itag_bank
|vpiNet:
\_logic_net: (data_in_a), line:41, parent:itag_bank
|vpiNet:
\_logic_net: (data_in_b), line:42, parent:itag_bank
|vpiNet:
\_logic_net: (data_out_a), line:43, parent:itag_bank
|vpiNet:
\_logic_net: (data_out_b), line:44, parent:itag_bank
|vpiNet:
\_logic_net: (i), line:49, parent:itag_bank
|vpiName:i
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk3.i_cache.icache_tag_banks.tag_bank_gen[0].itag_bank.i
|vpiArrayNet:
\_array_net: (tag_entry), line:47, parent:itag_bank
|vpiName:tag_entry
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk3.i_cache.icache_tag_banks.tag_bank_gen[0].itag_bank.tag_entry
|vpiSize:512
|vpiNet:
\_logic_net: , parent:tag_entry
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk3.i_cache.icache_tag_banks.tag_bank_gen[0].itag_bank.tag_entry
|vpiNetType:36
|vpiRange:
\_range: , line:47
|vpiLeftRange:
\_constant: , line:47
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:47
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiRange:
\_range: , line:47
|vpiLeftRange:
\_constant: , line:47
|vpiConstType:7
|vpiDecompile:511
|vpiSize:32
|INT:511
|vpiRightRange:
\_constant: , line:47
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiParameter:
\_parameter: (ALU_UNIT_WB_ID), line:190
|vpiName:ALU_UNIT_WB_ID
|INT:32
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (BRANCH_PREDICTOR_WAYS), line:159
|vpiName:BRANCH_PREDICTOR_WAYS
|INT:9
|vpiParameter:
\_parameter: (BRANCH_TABLE_ENTRIES), line:160
|vpiName:BRANCH_TABLE_ENTRIES
|INT:4
|vpiParameter:
\_parameter: (BRANCH_UNIT_ID), line:195
|vpiName:BRANCH_UNIT_ID
|INT:8
|vpiParameter:
\_parameter: (BUS_ADDR_H), line:107
|vpiName:BUS_ADDR_H
|INT:1
|vpiParameter:
\_parameter: (BUS_ADDR_L), line:106
|vpiName:BUS_ADDR_L
|INT:0
|vpiParameter:
\_parameter: (BUS_BIT_CHECK), line:108
|vpiName:BUS_BIT_CHECK
|INT:1
|vpiParameter:
\_parameter: (BUS_TYPE), line:89
|vpiName:BUS_TYPE
|INT:5
|vpiParameter:
\_parameter: (COUNTER_W), line:42
|vpiName:COUNTER_W
|INT:33
|vpiParameter:
\_parameter: (CPU_ID), line:38
|vpiName:CPU_ID
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_ADDR_WIDTH), line:113
|vpiName:C_M_AXI_ADDR_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_DATA_WIDTH), line:114
|vpiName:C_M_AXI_DATA_WIDTH
|INT:1
|vpiParameter:
\_parameter: (DCACHE_LINES), line:133
|vpiName:DCACHE_LINES
|INT:-2146435073
|vpiParameter:
\_parameter: (DCACHE_LINE_ADDR_W), line:135
|vpiName:DCACHE_LINE_ADDR_W
|INT:1073741824
|vpiParameter:
\_parameter: (DCACHE_LINE_W), line:136
|vpiName:DCACHE_LINE_W
|INT:1342177279
|vpiParameter:
\_parameter: (DCACHE_SUB_LINE_ADDR_W), line:137
|vpiName:DCACHE_SUB_LINE_ADDR_W
|INT:4
|vpiParameter:
\_parameter: (DCACHE_TAG_W), line:138
|vpiName:DCACHE_TAG_W
|INT:1610612736
|vpiParameter:
\_parameter: (DCACHE_WAYS), line:134
|vpiName:DCACHE_WAYS
|INT:4
|vpiParameter:
\_parameter: (DIV_ALGORITHM), line:67
|vpiName:DIV_ALGORITHM
|INT:0
|vpiParameter:
\_parameter: (DIV_UNIT_WB_ID), line:192
|vpiName:DIV_UNIT_WB_ID
|INT:2
|vpiParameter:
\_parameter: (DTLB_DEPTH), line:152
|vpiName:DTLB_DEPTH
|INT:512
|vpiParameter:
\_parameter: (DTLB_WAYS), line:151
|vpiName:DTLB_WAYS
|INT:32
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (ENABLE_M_MODE), line:70
|vpiName:ENABLE_M_MODE
|INT:2
|vpiParameter:
\_parameter: (ENABLE_S_MODE), line:36
|vpiName:ENABLE_S_MODE
|INT:0
|vpiParameter:
\_parameter: (ENABLE_TRACE_INTERFACE), line:172
|vpiName:ENABLE_TRACE_INTERFACE
|INT:2
|vpiParameter:
\_parameter: (FETCH_BUFFER_DEPTH), line:168
|vpiName:FETCH_BUFFER_DEPTH
|INT:512
|vpiParameter:
\_parameter: (FPGA_VENDOR), line:70
|vpiName:FPGA_VENDOR
|INT:-2147483648
|vpiParameter:
\_parameter: (GC_UNIT_ID), line:196
|vpiName:GC_UNIT_ID
|INT:4
|vpiParameter:
\_parameter: (ICACHE_LINES), line:121
|vpiName:ICACHE_LINES
|INT:2
|vpiParameter:
\_parameter: (ICACHE_LINE_ADDR_W), line:123
|vpiName:ICACHE_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_LINE_W), line:124
|vpiName:ICACHE_LINE_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_SUB_LINE_ADDR_W), line:125
|vpiName:ICACHE_SUB_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_TAG_W), line:126
|vpiName:ICACHE_TAG_W
|INT:-2147483648
|vpiParameter:
\_parameter: (ICACHE_WAYS), line:122
|vpiName:ICACHE_WAYS
|INT:1
|vpiParameter:
\_parameter: (ITLB_DEPTH), line:146
|vpiName:ITLB_DEPTH
|INT:32
|vpiParameter:
\_parameter: (ITLB_WAYS), line:145
|vpiName:ITLB_WAYS
|INT:4
|vpiParameter:
\_parameter: (L1_CONNECTIONS), line:177
|vpiName:L1_CONNECTIONS
|INT:9
|vpiParameter:
\_parameter: (L1_DCACHE_ID), line:178
|vpiName:L1_DCACHE_ID
|INT:4
|vpiParameter:
\_parameter: (L1_DMMU_ID), line:179
|vpiName:L1_DMMU_ID
|INT:2
|vpiParameter:
\_parameter: (L1_ICACHE_ID), line:180
|vpiName:L1_ICACHE_ID
|INT:19
|vpiParameter:
\_parameter: (L1_IMMU_ID), line:181
|vpiName:L1_IMMU_ID
|INT:0
|vpiParameter:
\_parameter: (LINES), line:28
|vpiName:LINES
|INT:512
|vpiParameter:
\_parameter: (LS_UNIT_WB_ID), line:191
|vpiName:LS_UNIT_WB_ID
|INT:1
|vpiParameter:
\_parameter: (MAX_INFLIGHT_COUNT), line:167
|vpiName:MAX_INFLIGHT_COUNT
|INT:19
|vpiParameter:
\_parameter: (MEMORY_ADDR_H), line:103
|vpiName:MEMORY_ADDR_H
|INT:12
|vpiParameter:
\_parameter: (MEMORY_ADDR_L), line:102
|vpiName:MEMORY_ADDR_L
|INT:11
|vpiParameter:
\_parameter: (MEMORY_BIT_CHECK), line:104
|vpiName:MEMORY_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (MUL_UNIT_WB_ID), line:193
|vpiName:MUL_UNIT_WB_ID
|INT:512
|vpiParameter:
\_parameter: (NUM_UNITS), line:188
|vpiName:NUM_UNITS
|INT:2
|vpiParameter:
\_parameter: (NUM_WB_UNITS), line:186
|vpiName:NUM_WB_UNITS
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (RAS_DEPTH), line:161
|vpiName:RAS_DEPTH
|INT:2
|vpiParameter:
\_parameter: (RESET_VEC), line:39
|vpiName:RESET_VEC
|INT:-2147483648
|vpiParameter:
\_parameter: (SCRATCH_ADDR_H), line:99
|vpiName:SCRATCH_ADDR_H
|INT:9
|vpiParameter:
\_parameter: (SCRATCH_ADDR_L), line:98
|vpiName:SCRATCH_ADDR_L
|INT:8
|vpiParameter:
\_parameter: (SCRATCH_BIT_CHECK), line:100
|vpiName:SCRATCH_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (USE_AMO), line:70
|vpiName:USE_AMO
|INT:1
|vpiParameter:
\_parameter: (USE_BRANCH_PREDICTOR), line:158
|vpiName:USE_BRANCH_PREDICTOR
|INT:2
|vpiParameter:
\_parameter: (USE_BUS), line:88
|vpiName:USE_BUS
|INT:4
|vpiParameter:
\_parameter: (USE_DCACHE), line:92
|vpiName:USE_DCACHE
|INT:6
|vpiParameter:
\_parameter: (USE_DIV), line:49
|vpiName:USE_DIV
|INT:1
|vpiParameter:
\_parameter: (USE_DTAG_INVALIDATIONS), line:140
|vpiName:USE_DTAG_INVALIDATIONS
|INT:1879048191
|vpiParameter:
\_parameter: (USE_D_SCRATCH_MEM), line:79
|vpiName:USE_D_SCRATCH_MEM
|INT:3
|vpiParameter:
\_parameter: (USE_ICACHE), line:93
|vpiName:USE_ICACHE
|INT:7
|vpiParameter:
\_parameter: (USE_I_SCRATCH_MEM), line:78
|vpiName:USE_I_SCRATCH_MEM
|INT:2
|vpiParameter:
\_parameter: (USE_MUL), line:48
|vpiName:USE_MUL
|INT:1
|vpiParameter:
\_parameter: (WB_UNITS_WIDTH), line:187
|vpiName:WB_UNITS_WIDTH
|INT:32
|vpiParameter:
\_parameter: (WIDTH), line:27
|vpiName:WIDTH
|INT:32
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiParameter:
\_parameter: (ALU_UNIT_WB_ID), line:190
|vpiName:ALU_UNIT_WB_ID
|INT:32
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (BRANCH_PREDICTOR_WAYS), line:159
|vpiName:BRANCH_PREDICTOR_WAYS
|INT:9
|vpiParameter:
\_parameter: (BRANCH_TABLE_ENTRIES), line:160
|vpiName:BRANCH_TABLE_ENTRIES
|INT:4
|vpiParameter:
\_parameter: (BRANCH_UNIT_ID), line:195
|vpiName:BRANCH_UNIT_ID
|INT:8
|vpiParameter:
\_parameter: (BUS_ADDR_H), line:107
|vpiName:BUS_ADDR_H
|INT:1
|vpiParameter:
\_parameter: (BUS_ADDR_L), line:106
|vpiName:BUS_ADDR_L
|INT:0
|vpiParameter:
\_parameter: (BUS_BIT_CHECK), line:108
|vpiName:BUS_BIT_CHECK
|INT:1
|vpiParameter:
\_parameter: (BUS_TYPE), line:89
|vpiName:BUS_TYPE
|INT:5
|vpiParameter:
\_parameter: (COUNTER_W), line:42
|vpiName:COUNTER_W
|INT:33
|vpiParameter:
\_parameter: (CPU_ID), line:38
|vpiName:CPU_ID
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_ADDR_WIDTH), line:113
|vpiName:C_M_AXI_ADDR_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_DATA_WIDTH), line:114
|vpiName:C_M_AXI_DATA_WIDTH
|INT:1
|vpiParameter:
\_parameter: (DCACHE_LINES), line:133
|vpiName:DCACHE_LINES
|INT:-2146435073
|vpiParameter:
\_parameter: (DCACHE_LINE_ADDR_W), line:135
|vpiName:DCACHE_LINE_ADDR_W
|INT:1073741824
|vpiParameter:
\_parameter: (DCACHE_LINE_W), line:136
|vpiName:DCACHE_LINE_W
|INT:1342177279
|vpiParameter:
\_parameter: (DCACHE_SUB_LINE_ADDR_W), line:137
|vpiName:DCACHE_SUB_LINE_ADDR_W
|INT:4
|vpiParameter:
\_parameter: (DCACHE_TAG_W), line:138
|vpiName:DCACHE_TAG_W
|INT:1610612736
|vpiParameter:
\_parameter: (DCACHE_WAYS), line:134
|vpiName:DCACHE_WAYS
|INT:4
|vpiParameter:
\_parameter: (DIV_ALGORITHM), line:67
|vpiName:DIV_ALGORITHM
|INT:0
|vpiParameter:
\_parameter: (DIV_UNIT_WB_ID), line:192
|vpiName:DIV_UNIT_WB_ID
|INT:2
|vpiParameter:
\_parameter: (DTLB_DEPTH), line:152
|vpiName:DTLB_DEPTH
|INT:512
|vpiParameter:
\_parameter: (DTLB_WAYS), line:151
|vpiName:DTLB_WAYS
|INT:32
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (ENABLE_M_MODE), line:34
|vpiName:ENABLE_M_MODE
|INT:1
|vpiParameter:
\_parameter: (ENABLE_S_MODE), line:36
|vpiName:ENABLE_S_MODE
|INT:0
|vpiParameter:
\_parameter: (ENABLE_TRACE_INTERFACE), line:172
|vpiName:ENABLE_TRACE_INTERFACE
|INT:2
|vpiParameter:
\_parameter: (FETCH_BUFFER_DEPTH), line:168
|vpiName:FETCH_BUFFER_DEPTH
|INT:512
|vpiParameter:
\_parameter: (FPGA_VENDOR), line:27
|vpiName:FPGA_VENDOR
|STRING:"xilinx"
|vpiParameter:
\_parameter: (GC_UNIT_ID), line:196
|vpiName:GC_UNIT_ID
|INT:4
|vpiParameter:
\_parameter: (ICACHE_LINES), line:121
|vpiName:ICACHE_LINES
|INT:2
|vpiParameter:
\_parameter: (ICACHE_LINE_ADDR_W), line:123
|vpiName:ICACHE_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_LINE_W), line:124
|vpiName:ICACHE_LINE_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_SUB_LINE_ADDR_W), line:125
|vpiName:ICACHE_SUB_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_TAG_W), line:126
|vpiName:ICACHE_TAG_W
|INT:-2147483648
|vpiParameter:
\_parameter: (ICACHE_WAYS), line:122
|vpiName:ICACHE_WAYS
|INT:1
|vpiParameter:
\_parameter: (ITLB_DEPTH), line:146
|vpiName:ITLB_DEPTH
|INT:32
|vpiParameter:
\_parameter: (ITLB_WAYS), line:145
|vpiName:ITLB_WAYS
|INT:4
|vpiParameter:
\_parameter: (L1_CONNECTIONS), line:177
|vpiName:L1_CONNECTIONS
|INT:9
|vpiParameter:
\_parameter: (L1_DCACHE_ID), line:178
|vpiName:L1_DCACHE_ID
|INT:4
|vpiParameter:
\_parameter: (L1_DMMU_ID), line:179
|vpiName:L1_DMMU_ID
|INT:2
|vpiParameter:
\_parameter: (L1_ICACHE_ID), line:180
|vpiName:L1_ICACHE_ID
|INT:19
|vpiParameter:
\_parameter: (L1_IMMU_ID), line:181
|vpiName:L1_IMMU_ID
|INT:0
|vpiParameter:
\_parameter: (LS_UNIT_WB_ID), line:191
|vpiName:LS_UNIT_WB_ID
|INT:1
|vpiParameter:
\_parameter: (MAX_INFLIGHT_COUNT), line:167
|vpiName:MAX_INFLIGHT_COUNT
|INT:19
|vpiParameter:
\_parameter: (MEMORY_ADDR_H), line:103
|vpiName:MEMORY_ADDR_H
|INT:12
|vpiParameter:
\_parameter: (MEMORY_ADDR_L), line:102
|vpiName:MEMORY_ADDR_L
|INT:11
|vpiParameter:
\_parameter: (MEMORY_BIT_CHECK), line:104
|vpiName:MEMORY_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (MUL_UNIT_WB_ID), line:193
|vpiName:MUL_UNIT_WB_ID
|INT:512
|vpiParameter:
\_parameter: (NUM_UNITS), line:188
|vpiName:NUM_UNITS
|INT:2
|vpiParameter:
\_parameter: (NUM_WB_UNITS), line:186
|vpiName:NUM_WB_UNITS
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (RAS_DEPTH), line:161
|vpiName:RAS_DEPTH
|INT:2
|vpiParameter:
\_parameter: (RESET_VEC), line:39
|vpiName:RESET_VEC
|INT:-2147483648
|vpiParameter:
\_parameter: (SCRATCH_ADDR_H), line:99
|vpiName:SCRATCH_ADDR_H
|INT:9
|vpiParameter:
\_parameter: (SCRATCH_ADDR_L), line:98
|vpiName:SCRATCH_ADDR_L
|INT:8
|vpiParameter:
\_parameter: (SCRATCH_BIT_CHECK), line:100
|vpiName:SCRATCH_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (USE_AMO), line:70
|vpiName:USE_AMO
|INT:1
|vpiParameter:
\_parameter: (USE_BRANCH_PREDICTOR), line:158
|vpiName:USE_BRANCH_PREDICTOR
|INT:2
|vpiParameter:
\_parameter: (USE_BUS), line:88
|vpiName:USE_BUS
|INT:4
|vpiParameter:
\_parameter: (USE_DCACHE), line:92
|vpiName:USE_DCACHE
|INT:6
|vpiParameter:
\_parameter: (USE_DIV), line:49
|vpiName:USE_DIV
|INT:1
|vpiParameter:
\_parameter: (USE_DTAG_INVALIDATIONS), line:140
|vpiName:USE_DTAG_INVALIDATIONS
|INT:1879048191
|vpiParameter:
\_parameter: (USE_D_SCRATCH_MEM), line:79
|vpiName:USE_D_SCRATCH_MEM
|INT:3
|vpiParameter:
\_parameter: (USE_ICACHE), line:93
|vpiName:USE_ICACHE
|INT:7
|vpiParameter:
\_parameter: (USE_I_SCRATCH_MEM), line:78
|vpiName:USE_I_SCRATCH_MEM
|INT:2
|vpiParameter:
\_parameter: (USE_MUL), line:48
|vpiName:USE_MUL
|INT:1
|vpiParameter:
\_parameter: (WB_UNITS_WIDTH), line:187
|vpiName:WB_UNITS_WIDTH
|INT:32
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiParameter:
\_parameter: (i), line:68
|vpiName:i
|INT:0
|vpiNet:
\_logic_net: (clk), line:27, parent:icache_tag_banks
|vpiNet:
\_logic_net: (rst), line:28, parent:icache_tag_banks
|vpiNet:
\_logic_net: (stage1_addr), line:30, parent:icache_tag_banks
|vpiNet:
\_logic_net: (stage2_addr), line:31, parent:icache_tag_banks
|vpiNet:
\_logic_net: (update_way), line:33, parent:icache_tag_banks
|vpiNet:
\_logic_net: (update), line:34, parent:icache_tag_banks
|vpiNet:
\_logic_net: (stage1_adv), line:36, parent:icache_tag_banks
|vpiNet:
\_logic_net: (tag_hit), line:38, parent:icache_tag_banks
|vpiNet:
\_logic_net: (tag_hit_way), line:39, parent:icache_tag_banks
|vpiNet:
\_logic_net: (hit_allowed), line:52, parent:icache_tag_banks
|vpiName:hit_allowed
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk3.i_cache.icache_tag_banks.hit_allowed
|vpiNetType:36
|vpiInstance:
\_module: work@icache (i_cache), file:third_party/cores/taiga/core/fetch.sv, line:173
|vpiVariables:
\_array_var: (tag_line), parent:icache_tag_banks
|vpiArrayType:1
|vpiName:tag_line
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk3.i_cache.icache_tag_banks.tag_line
|vpiRandType:1
|vpiVisibility:1
|vpiSize:1
|vpiReg:
\_logic_var: (tag_line), line:53, parent:tag_line
|vpiName:tag_line
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk3.i_cache.icache_tag_banks.tag_line.tag_line
|vpiRange:
\_range: , line:53
|vpiLeftRange:
\_constant: , line:53
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiRightRange:
\_constant: , line:53
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiVariables:
\_logic_var: (stage2_tag), line:55, parent:icache_tag_banks
|vpiName:stage2_tag
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk3.i_cache.icache_tag_banks.stage2_tag
|vpiParameter:
\_parameter: (ALU_UNIT_WB_ID), line:190
|vpiName:ALU_UNIT_WB_ID
|INT:32
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (BRANCH_PREDICTOR_WAYS), line:159
|vpiName:BRANCH_PREDICTOR_WAYS
|INT:9
|vpiParameter:
\_parameter: (BRANCH_TABLE_ENTRIES), line:160
|vpiName:BRANCH_TABLE_ENTRIES
|INT:4
|vpiParameter:
\_parameter: (BRANCH_UNIT_ID), line:195
|vpiName:BRANCH_UNIT_ID
|INT:8
|vpiParameter:
\_parameter: (BUS_ADDR_H), line:107
|vpiName:BUS_ADDR_H
|INT:1
|vpiParameter:
\_parameter: (BUS_ADDR_L), line:106
|vpiName:BUS_ADDR_L
|INT:0
|vpiParameter:
\_parameter: (BUS_BIT_CHECK), line:108
|vpiName:BUS_BIT_CHECK
|INT:1
|vpiParameter:
\_parameter: (BUS_TYPE), line:89
|vpiName:BUS_TYPE
|INT:5
|vpiParameter:
\_parameter: (COUNTER_W), line:42
|vpiName:COUNTER_W
|INT:33
|vpiParameter:
\_parameter: (CPU_ID), line:38
|vpiName:CPU_ID
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_ADDR_WIDTH), line:113
|vpiName:C_M_AXI_ADDR_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_DATA_WIDTH), line:114
|vpiName:C_M_AXI_DATA_WIDTH
|INT:1
|vpiParameter:
\_parameter: (DCACHE_LINES), line:133
|vpiName:DCACHE_LINES
|INT:-2146435073
|vpiParameter:
\_parameter: (DCACHE_LINE_ADDR_W), line:135
|vpiName:DCACHE_LINE_ADDR_W
|INT:1073741824
|vpiParameter:
\_parameter: (DCACHE_LINE_W), line:136
|vpiName:DCACHE_LINE_W
|INT:1342177279
|vpiParameter:
\_parameter: (DCACHE_SUB_LINE_ADDR_W), line:137
|vpiName:DCACHE_SUB_LINE_ADDR_W
|INT:4
|vpiParameter:
\_parameter: (DCACHE_TAG_W), line:138
|vpiName:DCACHE_TAG_W
|INT:1610612736
|vpiParameter:
\_parameter: (DCACHE_WAYS), line:134
|vpiName:DCACHE_WAYS
|INT:4
|vpiParameter:
\_parameter: (DIV_ALGORITHM), line:67
|vpiName:DIV_ALGORITHM
|INT:0
|vpiParameter:
\_parameter: (DIV_UNIT_WB_ID), line:192
|vpiName:DIV_UNIT_WB_ID
|INT:2
|vpiParameter:
\_parameter: (DTLB_DEPTH), line:152
|vpiName:DTLB_DEPTH
|INT:512
|vpiParameter:
\_parameter: (DTLB_WAYS), line:151
|vpiName:DTLB_WAYS
|INT:32
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (ENABLE_M_MODE), line:34
|vpiName:ENABLE_M_MODE
|INT:1
|vpiParameter:
\_parameter: (ENABLE_S_MODE), line:36
|vpiName:ENABLE_S_MODE
|INT:0
|vpiParameter:
\_parameter: (ENABLE_TRACE_INTERFACE), line:172
|vpiName:ENABLE_TRACE_INTERFACE
|INT:2
|vpiParameter:
\_parameter: (FETCH_BUFFER_DEPTH), line:168
|vpiName:FETCH_BUFFER_DEPTH
|INT:512
|vpiParameter:
\_parameter: (FPGA_VENDOR), line:27
|vpiName:FPGA_VENDOR
|STRING:"xilinx"
|vpiParameter:
\_parameter: (GC_UNIT_ID), line:196
|vpiName:GC_UNIT_ID
|INT:4
|vpiParameter:
\_parameter: (ICACHE_LINES), line:121
|vpiName:ICACHE_LINES
|INT:2
|vpiParameter:
\_parameter: (ICACHE_LINE_ADDR_W), line:123
|vpiName:ICACHE_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_LINE_W), line:124
|vpiName:ICACHE_LINE_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_SUB_LINE_ADDR_W), line:125
|vpiName:ICACHE_SUB_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_TAG_W), line:126
|vpiName:ICACHE_TAG_W
|INT:-2147483648
|vpiParameter:
\_parameter: (ICACHE_WAYS), line:122
|vpiName:ICACHE_WAYS
|INT:1
|vpiParameter:
\_parameter: (ITLB_DEPTH), line:146
|vpiName:ITLB_DEPTH
|INT:32
|vpiParameter:
\_parameter: (ITLB_WAYS), line:145
|vpiName:ITLB_WAYS
|INT:4
|vpiParameter:
\_parameter: (L1_CONNECTIONS), line:177
|vpiName:L1_CONNECTIONS
|INT:9
|vpiParameter:
\_parameter: (L1_DCACHE_ID), line:178
|vpiName:L1_DCACHE_ID
|INT:4
|vpiParameter:
\_parameter: (L1_DMMU_ID), line:179
|vpiName:L1_DMMU_ID
|INT:2
|vpiParameter:
\_parameter: (L1_ICACHE_ID), line:180
|vpiName:L1_ICACHE_ID
|INT:19
|vpiParameter:
\_parameter: (L1_IMMU_ID), line:181
|vpiName:L1_IMMU_ID
|INT:0
|vpiParameter:
\_parameter: (LS_UNIT_WB_ID), line:191
|vpiName:LS_UNIT_WB_ID
|INT:1
|vpiParameter:
\_parameter: (MAX_INFLIGHT_COUNT), line:167
|vpiName:MAX_INFLIGHT_COUNT
|INT:19
|vpiParameter:
\_parameter: (MEMORY_ADDR_H), line:103
|vpiName:MEMORY_ADDR_H
|INT:12
|vpiParameter:
\_parameter: (MEMORY_ADDR_L), line:102
|vpiName:MEMORY_ADDR_L
|INT:11
|vpiParameter:
\_parameter: (MEMORY_BIT_CHECK), line:104
|vpiName:MEMORY_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (MUL_UNIT_WB_ID), line:193
|vpiName:MUL_UNIT_WB_ID
|INT:512
|vpiParameter:
\_parameter: (NUM_UNITS), line:188
|vpiName:NUM_UNITS
|INT:2
|vpiParameter:
\_parameter: (NUM_WB_UNITS), line:186
|vpiName:NUM_WB_UNITS
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (RAS_DEPTH), line:161
|vpiName:RAS_DEPTH
|INT:2
|vpiParameter:
\_parameter: (RESET_VEC), line:39
|vpiName:RESET_VEC
|INT:-2147483648
|vpiParameter:
\_parameter: (SCRATCH_ADDR_H), line:99
|vpiName:SCRATCH_ADDR_H
|INT:9
|vpiParameter:
\_parameter: (SCRATCH_ADDR_L), line:98
|vpiName:SCRATCH_ADDR_L
|INT:8
|vpiParameter:
\_parameter: (SCRATCH_BIT_CHECK), line:100
|vpiName:SCRATCH_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (USE_AMO), line:70
|vpiName:USE_AMO
|INT:1
|vpiParameter:
\_parameter: (USE_BRANCH_PREDICTOR), line:158
|vpiName:USE_BRANCH_PREDICTOR
|INT:2
|vpiParameter:
\_parameter: (USE_BUS), line:88
|vpiName:USE_BUS
|INT:4
|vpiParameter:
\_parameter: (USE_DCACHE), line:92
|vpiName:USE_DCACHE
|INT:6
|vpiParameter:
\_parameter: (USE_DIV), line:49
|vpiName:USE_DIV
|INT:1
|vpiParameter:
\_parameter: (USE_DTAG_INVALIDATIONS), line:140
|vpiName:USE_DTAG_INVALIDATIONS
|INT:1879048191
|vpiParameter:
\_parameter: (USE_D_SCRATCH_MEM), line:79
|vpiName:USE_D_SCRATCH_MEM
|INT:3
|vpiParameter:
\_parameter: (USE_ICACHE), line:93
|vpiName:USE_ICACHE
|INT:7
|vpiParameter:
\_parameter: (USE_I_SCRATCH_MEM), line:78
|vpiName:USE_I_SCRATCH_MEM
|INT:2
|vpiParameter:
\_parameter: (USE_MUL), line:48
|vpiName:USE_MUL
|INT:1
|vpiParameter:
\_parameter: (WB_UNITS_WIDTH), line:187
|vpiName:WB_UNITS_WIDTH
|INT:32
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiGenScopeArray:
\_gen_scope_array: (idata_bank_gen[0]), line:130, parent:i_cache
|vpiName:idata_bank_gen[0]
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk3.i_cache.idata_bank_gen[0]
|vpiGenScope:
\_gen_scope: , parent:idata_bank_gen[0]
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk3.i_cache.idata_bank_gen[0]
|vpiModule:
\_module: work@byte_en_BRAM (idata_bank), file:third_party/cores/taiga/core/icache.sv, line:131
|vpiDefName:work@byte_en_BRAM
|vpiName:idata_bank
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk3.i_cache.idata_bank_gen[0].idata_bank
|vpiPort:
\_port: (clk), line:32, parent:idata_bank
|vpiName:clk
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (clk), line:132
|vpiName:clk
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (clk), line:32, parent:idata_bank
|vpiName:clk
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk3.i_cache.idata_bank_gen[0].idata_bank.clk
|vpiNetType:36
|vpiPort:
\_port: (addr_a), line:33, parent:idata_bank
|vpiName:addr_a
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (fetch_sub.stage1_addr), line:133
|vpiName:fetch_sub.stage1_addr
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (addr_a), line:33, parent:idata_bank
|vpiName:addr_a
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk3.i_cache.idata_bank_gen[0].idata_bank.addr_a
|vpiNetType:36
|vpiRange:
\_range: , line:33
|vpiLeftRange:
\_constant: , line:33
|vpiConstType:7
|vpiDecompile:11
|vpiSize:32
|INT:11
|vpiRightRange:
\_constant: , line:33
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiPort:
\_port: (addr_b), line:34, parent:idata_bank
|vpiName:addr_b
|vpiDirection:1
|vpiHighConn:
\_operation: , line:134
|vpiOpType:33
|vpiOperand:
\_ref_obj: (fetch_sub.stage2_addr), line:134
|vpiName:fetch_sub.stage2_addr
|vpiOperand:
\_ref_obj: (word_count), line:134
|vpiName:word_count
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (en_a), line:34, parent:idata_bank
|vpiName:en_a
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk3.i_cache.idata_bank_gen[0].idata_bank.en_a
|vpiNetType:36
|vpiPort:
\_port: (en_a), line:35, parent:idata_bank
|vpiName:en_a
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (fetch_sub.new_request), line:135
|vpiName:fetch_sub.new_request
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (be_a), line:35, parent:idata_bank
|vpiName:be_a
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk3.i_cache.idata_bank_gen[0].idata_bank.be_a
|vpiNetType:36
|vpiRange:
\_range: , line:35
|vpiLeftRange:
\_constant: , line:35
|vpiConstType:7
|vpiDecompile:18446744073709551615
|vpiSize:32
|INT:-1
|vpiRightRange:
\_constant: , line:35
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiPort:
\_port: (en_b), line:36, parent:idata_bank
|vpiName:en_b
|vpiDirection:1
|vpiHighConn:
\_operation: , line:136
|vpiOpType:28
|vpiOperand:
\_bit_select: (tag_update_way), line:136
|vpiName:tag_update_way
|vpiIndex:
\_constant: , line:136
|vpiDecompile:0
|INT:0
|vpiOperand:
\_ref_obj: (l1_response.data_valid), line:136
|vpiName:l1_response.data_valid
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (data_in_a), line:36, parent:idata_bank
|vpiName:data_in_a
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk3.i_cache.idata_bank_gen[0].idata_bank.data_in_a
|vpiNetType:36
|vpiRange:
\_range: , line:36
|vpiLeftRange:
\_constant: , line:36
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiRightRange:
\_constant: , line:36
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiPort:
\_port: (be_a), line:37, parent:idata_bank
|vpiName:be_a
|vpiDirection:2
|vpiHighConn:
\_constant: , line:137
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (data_out_a), line:37, parent:idata_bank
|vpiName:data_out_a
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk3.i_cache.idata_bank_gen[0].idata_bank.data_out_a
|vpiNetType:36
|vpiRange:
\_range: , line:37
|vpiLeftRange:
\_constant: , line:37
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiRightRange:
\_constant: , line:37
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiPort:
\_port: (be_b), line:39, parent:idata_bank
|vpiName:be_b
|vpiDirection:1
|vpiHighConn:
\_constant: , line:138
|vpiConstType:3
|vpiDecompile:'b1
|vpiSize:1
|BIN:1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (addr_b), line:39, parent:idata_bank
|vpiName:addr_b
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk3.i_cache.idata_bank_gen[0].idata_bank.addr_b
|vpiNetType:36
|vpiRange:
\_range: , line:39
|vpiLeftRange:
\_constant: , line:39
|vpiConstType:7
|vpiDecompile:11
|vpiSize:32
|INT:11
|vpiRightRange:
\_constant: , line:39
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiPort:
\_port: (data_in_a), line:40, parent:idata_bank
|vpiName:data_in_a
|vpiDirection:1
|vpiHighConn:
\_constant: , line:139
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (en_b), line:40, parent:idata_bank
|vpiName:en_b
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk3.i_cache.idata_bank_gen[0].idata_bank.en_b
|vpiNetType:36
|vpiPort:
\_port: (data_in_b), line:41, parent:idata_bank
|vpiName:data_in_b
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (l1_response.data), line:140
|vpiName:l1_response.data
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (be_b), line:41, parent:idata_bank
|vpiName:be_b
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk3.i_cache.idata_bank_gen[0].idata_bank.be_b
|vpiNetType:36
|vpiRange:
\_range: , line:41
|vpiLeftRange:
\_constant: , line:41
|vpiConstType:7
|vpiDecompile:18446744073709551615
|vpiSize:32
|INT:-1
|vpiRightRange:
\_constant: , line:41
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiPort:
\_port: (data_out_a), line:42, parent:idata_bank
|vpiName:data_out_a
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (data_out), line:141
|vpiName:data_out
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (data_in_b), line:42, parent:idata_bank
|vpiName:data_in_b
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk3.i_cache.idata_bank_gen[0].idata_bank.data_in_b
|vpiNetType:36
|vpiRange:
\_range: , line:42
|vpiLeftRange:
\_constant: , line:42
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiRightRange:
\_constant: , line:42
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiPort:
\_port: (data_out_b), line:43, parent:idata_bank
|vpiName:data_out_b
|vpiDirection:2
|vpiHighConn:
\_ref_obj: (data_out_b), line:142
|vpiName:data_out_b
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (data_out_b), line:43, parent:idata_bank
|vpiName:data_out_b
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk3.i_cache.idata_bank_gen[0].idata_bank.data_out_b
|vpiNetType:36
|vpiRange:
\_range: , line:43
|vpiLeftRange:
\_constant: , line:43
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiRightRange:
\_constant: , line:43
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiGenScopeArray:
\_gen_scope_array: (genblk1), line:47, parent:idata_bank
|vpiName:genblk1
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk3.i_cache.idata_bank_gen[0].idata_bank.genblk1
|vpiGenScope:
\_gen_scope: , parent:genblk1
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk3.i_cache.idata_bank_gen[0].idata_bank.genblk1
|vpiModule:
\_module: work@taiga_wrapper.cpu.fetch_block.genblk3.i_cache.idata_bank_gen[0].idata_bank.genblk1::intel_byte_enable_ram (ram_block), file:third_party/cores/taiga/core/byte_en_BRAM.sv, line:50
|vpiDefName:work@taiga_wrapper.cpu.fetch_block.genblk3.i_cache.idata_bank_gen[0].idata_bank.genblk1::intel_byte_enable_ram
|vpiName:ram_block
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk3.i_cache.idata_bank_gen[0].idata_bank.genblk1.ram_block
|vpiParameter:
\_parameter: (ALU_UNIT_WB_ID), line:190
|vpiName:ALU_UNIT_WB_ID
|INT:32
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (BRANCH_PREDICTOR_WAYS), line:159
|vpiName:BRANCH_PREDICTOR_WAYS
|INT:9
|vpiParameter:
\_parameter: (BRANCH_TABLE_ENTRIES), line:160
|vpiName:BRANCH_TABLE_ENTRIES
|INT:4
|vpiParameter:
\_parameter: (BRANCH_UNIT_ID), line:195
|vpiName:BRANCH_UNIT_ID
|INT:8
|vpiParameter:
\_parameter: (BUS_ADDR_H), line:107
|vpiName:BUS_ADDR_H
|INT:1
|vpiParameter:
\_parameter: (BUS_ADDR_L), line:106
|vpiName:BUS_ADDR_L
|INT:0
|vpiParameter:
\_parameter: (BUS_BIT_CHECK), line:108
|vpiName:BUS_BIT_CHECK
|INT:1
|vpiParameter:
\_parameter: (BUS_TYPE), line:89
|vpiName:BUS_TYPE
|INT:5
|vpiParameter:
\_parameter: (COUNTER_W), line:42
|vpiName:COUNTER_W
|INT:33
|vpiParameter:
\_parameter: (CPU_ID), line:38
|vpiName:CPU_ID
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_ADDR_WIDTH), line:113
|vpiName:C_M_AXI_ADDR_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_DATA_WIDTH), line:114
|vpiName:C_M_AXI_DATA_WIDTH
|INT:1
|vpiParameter:
\_parameter: (DCACHE_LINES), line:133
|vpiName:DCACHE_LINES
|INT:-2146435073
|vpiParameter:
\_parameter: (DCACHE_LINE_ADDR_W), line:135
|vpiName:DCACHE_LINE_ADDR_W
|INT:1073741824
|vpiParameter:
\_parameter: (DCACHE_LINE_W), line:136
|vpiName:DCACHE_LINE_W
|INT:1342177279
|vpiParameter:
\_parameter: (DCACHE_SUB_LINE_ADDR_W), line:137
|vpiName:DCACHE_SUB_LINE_ADDR_W
|INT:4
|vpiParameter:
\_parameter: (DCACHE_TAG_W), line:138
|vpiName:DCACHE_TAG_W
|INT:1610612736
|vpiParameter:
\_parameter: (DCACHE_WAYS), line:134
|vpiName:DCACHE_WAYS
|INT:4
|vpiParameter:
\_parameter: (DIV_ALGORITHM), line:67
|vpiName:DIV_ALGORITHM
|INT:0
|vpiParameter:
\_parameter: (DIV_UNIT_WB_ID), line:192
|vpiName:DIV_UNIT_WB_ID
|INT:2
|vpiParameter:
\_parameter: (DTLB_DEPTH), line:152
|vpiName:DTLB_DEPTH
|INT:512
|vpiParameter:
\_parameter: (DTLB_WAYS), line:151
|vpiName:DTLB_WAYS
|INT:32
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (ENABLE_M_MODE), line:34
|vpiName:ENABLE_M_MODE
|INT:1
|vpiParameter:
\_parameter: (ENABLE_S_MODE), line:36
|vpiName:ENABLE_S_MODE
|INT:0
|vpiParameter:
\_parameter: (ENABLE_TRACE_INTERFACE), line:172
|vpiName:ENABLE_TRACE_INTERFACE
|INT:2
|vpiParameter:
\_parameter: (FETCH_BUFFER_DEPTH), line:168
|vpiName:FETCH_BUFFER_DEPTH
|INT:512
|vpiParameter:
\_parameter: (FPGA_VENDOR), line:27
|vpiName:FPGA_VENDOR
|STRING:"xilinx"
|vpiParameter:
\_parameter: (GC_UNIT_ID), line:196
|vpiName:GC_UNIT_ID
|INT:4
|vpiParameter:
\_parameter: (ICACHE_LINES), line:121
|vpiName:ICACHE_LINES
|INT:2
|vpiParameter:
\_parameter: (ICACHE_LINE_ADDR_W), line:123
|vpiName:ICACHE_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_LINE_W), line:124
|vpiName:ICACHE_LINE_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_SUB_LINE_ADDR_W), line:125
|vpiName:ICACHE_SUB_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_TAG_W), line:126
|vpiName:ICACHE_TAG_W
|INT:-2147483648
|vpiParameter:
\_parameter: (ICACHE_WAYS), line:122
|vpiName:ICACHE_WAYS
|INT:1
|vpiParameter:
\_parameter: (ITLB_DEPTH), line:146
|vpiName:ITLB_DEPTH
|INT:32
|vpiParameter:
\_parameter: (ITLB_WAYS), line:145
|vpiName:ITLB_WAYS
|INT:4
|vpiParameter:
\_parameter: (L1_CONNECTIONS), line:177
|vpiName:L1_CONNECTIONS
|INT:9
|vpiParameter:
\_parameter: (L1_DCACHE_ID), line:178
|vpiName:L1_DCACHE_ID
|INT:4
|vpiParameter:
\_parameter: (L1_DMMU_ID), line:179
|vpiName:L1_DMMU_ID
|INT:2
|vpiParameter:
\_parameter: (L1_ICACHE_ID), line:180
|vpiName:L1_ICACHE_ID
|INT:19
|vpiParameter:
\_parameter: (L1_IMMU_ID), line:181
|vpiName:L1_IMMU_ID
|INT:0
|vpiParameter:
\_parameter: (LS_UNIT_WB_ID), line:191
|vpiName:LS_UNIT_WB_ID
|INT:1
|vpiParameter:
\_parameter: (MAX_INFLIGHT_COUNT), line:167
|vpiName:MAX_INFLIGHT_COUNT
|INT:19
|vpiParameter:
\_parameter: (MEMORY_ADDR_H), line:103
|vpiName:MEMORY_ADDR_H
|INT:12
|vpiParameter:
\_parameter: (MEMORY_ADDR_L), line:102
|vpiName:MEMORY_ADDR_L
|INT:11
|vpiParameter:
\_parameter: (MEMORY_BIT_CHECK), line:104
|vpiName:MEMORY_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (MUL_UNIT_WB_ID), line:193
|vpiName:MUL_UNIT_WB_ID
|INT:512
|vpiParameter:
\_parameter: (NUM_UNITS), line:188
|vpiName:NUM_UNITS
|INT:2
|vpiParameter:
\_parameter: (NUM_WB_UNITS), line:186
|vpiName:NUM_WB_UNITS
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (RAS_DEPTH), line:161
|vpiName:RAS_DEPTH
|INT:2
|vpiParameter:
\_parameter: (RESET_VEC), line:39
|vpiName:RESET_VEC
|INT:-2147483648
|vpiParameter:
\_parameter: (SCRATCH_ADDR_H), line:99
|vpiName:SCRATCH_ADDR_H
|INT:9
|vpiParameter:
\_parameter: (SCRATCH_ADDR_L), line:98
|vpiName:SCRATCH_ADDR_L
|INT:8
|vpiParameter:
\_parameter: (SCRATCH_BIT_CHECK), line:100
|vpiName:SCRATCH_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (USE_AMO), line:70
|vpiName:USE_AMO
|INT:1
|vpiParameter:
\_parameter: (USE_BRANCH_PREDICTOR), line:158
|vpiName:USE_BRANCH_PREDICTOR
|INT:2
|vpiParameter:
\_parameter: (USE_BUS), line:88
|vpiName:USE_BUS
|INT:4
|vpiParameter:
\_parameter: (USE_DCACHE), line:92
|vpiName:USE_DCACHE
|INT:6
|vpiParameter:
\_parameter: (USE_DIV), line:49
|vpiName:USE_DIV
|INT:1
|vpiParameter:
\_parameter: (USE_DTAG_INVALIDATIONS), line:140
|vpiName:USE_DTAG_INVALIDATIONS
|INT:1879048191
|vpiParameter:
\_parameter: (USE_D_SCRATCH_MEM), line:79
|vpiName:USE_D_SCRATCH_MEM
|INT:3
|vpiParameter:
\_parameter: (USE_ICACHE), line:93
|vpiName:USE_ICACHE
|INT:7
|vpiParameter:
\_parameter: (USE_I_SCRATCH_MEM), line:78
|vpiName:USE_I_SCRATCH_MEM
|INT:2
|vpiParameter:
\_parameter: (USE_MUL), line:48
|vpiName:USE_MUL
|INT:1
|vpiParameter:
\_parameter: (WB_UNITS_WIDTH), line:187
|vpiName:WB_UNITS_WIDTH
|INT:32
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiNet:
\_logic_net: (clk), line:32, parent:idata_bank
|vpiNet:
\_logic_net: (addr_a), line:33, parent:idata_bank
|vpiNet:
\_logic_net: (en_a), line:34, parent:idata_bank
|vpiNet:
\_logic_net: (be_a), line:35, parent:idata_bank
|vpiNet:
\_logic_net: (data_in_a), line:36, parent:idata_bank
|vpiNet:
\_logic_net: (data_out_a), line:37, parent:idata_bank
|vpiNet:
\_logic_net: (addr_b), line:39, parent:idata_bank
|vpiNet:
\_logic_net: (en_b), line:40, parent:idata_bank
|vpiNet:
\_logic_net: (be_b), line:41, parent:idata_bank
|vpiNet:
\_logic_net: (data_in_b), line:42, parent:idata_bank
|vpiNet:
\_logic_net: (data_out_b), line:43, parent:idata_bank
|vpiParameter:
\_parameter: (ALU_UNIT_WB_ID), line:190
|vpiName:ALU_UNIT_WB_ID
|INT:32
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (BRANCH_PREDICTOR_WAYS), line:159
|vpiName:BRANCH_PREDICTOR_WAYS
|INT:9
|vpiParameter:
\_parameter: (BRANCH_TABLE_ENTRIES), line:160
|vpiName:BRANCH_TABLE_ENTRIES
|INT:4
|vpiParameter:
\_parameter: (BRANCH_UNIT_ID), line:195
|vpiName:BRANCH_UNIT_ID
|INT:8
|vpiParameter:
\_parameter: (BUS_ADDR_H), line:107
|vpiName:BUS_ADDR_H
|INT:1
|vpiParameter:
\_parameter: (BUS_ADDR_L), line:106
|vpiName:BUS_ADDR_L
|INT:0
|vpiParameter:
\_parameter: (BUS_BIT_CHECK), line:108
|vpiName:BUS_BIT_CHECK
|INT:1
|vpiParameter:
\_parameter: (BUS_TYPE), line:89
|vpiName:BUS_TYPE
|INT:5
|vpiParameter:
\_parameter: (COUNTER_W), line:42
|vpiName:COUNTER_W
|INT:33
|vpiParameter:
\_parameter: (CPU_ID), line:38
|vpiName:CPU_ID
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_ADDR_WIDTH), line:113
|vpiName:C_M_AXI_ADDR_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_DATA_WIDTH), line:114
|vpiName:C_M_AXI_DATA_WIDTH
|INT:1
|vpiParameter:
\_parameter: (DCACHE_LINES), line:133
|vpiName:DCACHE_LINES
|INT:-2146435073
|vpiParameter:
\_parameter: (DCACHE_LINE_ADDR_W), line:135
|vpiName:DCACHE_LINE_ADDR_W
|INT:1073741824
|vpiParameter:
\_parameter: (DCACHE_LINE_W), line:136
|vpiName:DCACHE_LINE_W
|INT:1342177279
|vpiParameter:
\_parameter: (DCACHE_SUB_LINE_ADDR_W), line:137
|vpiName:DCACHE_SUB_LINE_ADDR_W
|INT:4
|vpiParameter:
\_parameter: (DCACHE_TAG_W), line:138
|vpiName:DCACHE_TAG_W
|INT:1610612736
|vpiParameter:
\_parameter: (DCACHE_WAYS), line:134
|vpiName:DCACHE_WAYS
|INT:4
|vpiParameter:
\_parameter: (DIV_ALGORITHM), line:67
|vpiName:DIV_ALGORITHM
|INT:0
|vpiParameter:
\_parameter: (DIV_UNIT_WB_ID), line:192
|vpiName:DIV_UNIT_WB_ID
|INT:2
|vpiParameter:
\_parameter: (DTLB_DEPTH), line:152
|vpiName:DTLB_DEPTH
|INT:512
|vpiParameter:
\_parameter: (DTLB_WAYS), line:151
|vpiName:DTLB_WAYS
|INT:32
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (ENABLE_M_MODE), line:34
|vpiName:ENABLE_M_MODE
|INT:1
|vpiParameter:
\_parameter: (ENABLE_S_MODE), line:36
|vpiName:ENABLE_S_MODE
|INT:0
|vpiParameter:
\_parameter: (ENABLE_TRACE_INTERFACE), line:172
|vpiName:ENABLE_TRACE_INTERFACE
|INT:2
|vpiParameter:
\_parameter: (FETCH_BUFFER_DEPTH), line:168
|vpiName:FETCH_BUFFER_DEPTH
|INT:512
|vpiParameter:
\_parameter: (FPGA_VENDOR), line:131
|vpiName:FPGA_VENDOR
|INT:2
|vpiParameter:
\_parameter: (GC_UNIT_ID), line:196
|vpiName:GC_UNIT_ID
|INT:4
|vpiParameter:
\_parameter: (ICACHE_LINES), line:121
|vpiName:ICACHE_LINES
|INT:2
|vpiParameter:
\_parameter: (ICACHE_LINE_ADDR_W), line:123
|vpiName:ICACHE_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_LINE_W), line:124
|vpiName:ICACHE_LINE_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_SUB_LINE_ADDR_W), line:125
|vpiName:ICACHE_SUB_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_TAG_W), line:126
|vpiName:ICACHE_TAG_W
|INT:-2147483648
|vpiParameter:
\_parameter: (ICACHE_WAYS), line:122
|vpiName:ICACHE_WAYS
|INT:1
|vpiParameter:
\_parameter: (ITLB_DEPTH), line:146
|vpiName:ITLB_DEPTH
|INT:32
|vpiParameter:
\_parameter: (ITLB_WAYS), line:145
|vpiName:ITLB_WAYS
|INT:4
|vpiParameter:
\_parameter: (L1_CONNECTIONS), line:177
|vpiName:L1_CONNECTIONS
|INT:9
|vpiParameter:
\_parameter: (L1_DCACHE_ID), line:178
|vpiName:L1_DCACHE_ID
|INT:4
|vpiParameter:
\_parameter: (L1_DMMU_ID), line:179
|vpiName:L1_DMMU_ID
|INT:2
|vpiParameter:
\_parameter: (L1_ICACHE_ID), line:180
|vpiName:L1_ICACHE_ID
|INT:19
|vpiParameter:
\_parameter: (L1_IMMU_ID), line:181
|vpiName:L1_IMMU_ID
|INT:0
|vpiParameter:
\_parameter: (LINES), line:27
|vpiName:LINES
|INT:4096
|vpiParameter:
\_parameter: (LS_UNIT_WB_ID), line:191
|vpiName:LS_UNIT_WB_ID
|INT:1
|vpiParameter:
\_parameter: (MAX_INFLIGHT_COUNT), line:167
|vpiName:MAX_INFLIGHT_COUNT
|INT:19
|vpiParameter:
\_parameter: (MEMORY_ADDR_H), line:103
|vpiName:MEMORY_ADDR_H
|INT:12
|vpiParameter:
\_parameter: (MEMORY_ADDR_L), line:102
|vpiName:MEMORY_ADDR_L
|INT:11
|vpiParameter:
\_parameter: (MEMORY_BIT_CHECK), line:104
|vpiName:MEMORY_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (MUL_UNIT_WB_ID), line:193
|vpiName:MUL_UNIT_WB_ID
|INT:512
|vpiParameter:
\_parameter: (NUM_UNITS), line:188
|vpiName:NUM_UNITS
|INT:2
|vpiParameter:
\_parameter: (NUM_WB_UNITS), line:186
|vpiName:NUM_WB_UNITS
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (RAS_DEPTH), line:161
|vpiName:RAS_DEPTH
|INT:2
|vpiParameter:
\_parameter: (RESET_VEC), line:39
|vpiName:RESET_VEC
|INT:-2147483648
|vpiParameter:
\_parameter: (SCRATCH_ADDR_H), line:99
|vpiName:SCRATCH_ADDR_H
|INT:9
|vpiParameter:
\_parameter: (SCRATCH_ADDR_L), line:98
|vpiName:SCRATCH_ADDR_L
|INT:8
|vpiParameter:
\_parameter: (SCRATCH_BIT_CHECK), line:100
|vpiName:SCRATCH_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (USE_AMO), line:70
|vpiName:USE_AMO
|INT:1
|vpiParameter:
\_parameter: (USE_BRANCH_PREDICTOR), line:158
|vpiName:USE_BRANCH_PREDICTOR
|INT:2
|vpiParameter:
\_parameter: (USE_BUS), line:88
|vpiName:USE_BUS
|INT:4
|vpiParameter:
\_parameter: (USE_DCACHE), line:92
|vpiName:USE_DCACHE
|INT:6
|vpiParameter:
\_parameter: (USE_DIV), line:49
|vpiName:USE_DIV
|INT:1
|vpiParameter:
\_parameter: (USE_DTAG_INVALIDATIONS), line:140
|vpiName:USE_DTAG_INVALIDATIONS
|INT:1879048191
|vpiParameter:
\_parameter: (USE_D_SCRATCH_MEM), line:79
|vpiName:USE_D_SCRATCH_MEM
|INT:3
|vpiParameter:
\_parameter: (USE_ICACHE), line:93
|vpiName:USE_ICACHE
|INT:7
|vpiParameter:
\_parameter: (USE_I_SCRATCH_MEM), line:78
|vpiName:USE_I_SCRATCH_MEM
|INT:2
|vpiParameter:
\_parameter: (USE_MUL), line:48
|vpiName:USE_MUL
|INT:1
|vpiParameter:
\_parameter: (USE_PRELOAD_FILE), line:29
|vpiName:USE_PRELOAD_FILE
|INT:0
|vpiParameter:
\_parameter: (WB_UNITS_WIDTH), line:187
|vpiName:WB_UNITS_WIDTH
|INT:32
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiParameter:
\_parameter: (preload_file), line:28
|vpiName:preload_file
|STRING:""
|vpiParameter:
\_parameter: (ALU_UNIT_WB_ID), line:190
|vpiName:ALU_UNIT_WB_ID
|INT:32
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (BRANCH_PREDICTOR_WAYS), line:159
|vpiName:BRANCH_PREDICTOR_WAYS
|INT:9
|vpiParameter:
\_parameter: (BRANCH_TABLE_ENTRIES), line:160
|vpiName:BRANCH_TABLE_ENTRIES
|INT:4
|vpiParameter:
\_parameter: (BRANCH_UNIT_ID), line:195
|vpiName:BRANCH_UNIT_ID
|INT:8
|vpiParameter:
\_parameter: (BUS_ADDR_H), line:107
|vpiName:BUS_ADDR_H
|INT:1
|vpiParameter:
\_parameter: (BUS_ADDR_L), line:106
|vpiName:BUS_ADDR_L
|INT:0
|vpiParameter:
\_parameter: (BUS_BIT_CHECK), line:108
|vpiName:BUS_BIT_CHECK
|INT:1
|vpiParameter:
\_parameter: (BUS_TYPE), line:89
|vpiName:BUS_TYPE
|INT:5
|vpiParameter:
\_parameter: (COUNTER_W), line:42
|vpiName:COUNTER_W
|INT:33
|vpiParameter:
\_parameter: (CPU_ID), line:38
|vpiName:CPU_ID
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_ADDR_WIDTH), line:113
|vpiName:C_M_AXI_ADDR_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_DATA_WIDTH), line:114
|vpiName:C_M_AXI_DATA_WIDTH
|INT:1
|vpiParameter:
\_parameter: (DCACHE_LINES), line:133
|vpiName:DCACHE_LINES
|INT:-2146435073
|vpiParameter:
\_parameter: (DCACHE_LINE_ADDR_W), line:135
|vpiName:DCACHE_LINE_ADDR_W
|INT:1073741824
|vpiParameter:
\_parameter: (DCACHE_LINE_W), line:136
|vpiName:DCACHE_LINE_W
|INT:1342177279
|vpiParameter:
\_parameter: (DCACHE_SUB_LINE_ADDR_W), line:137
|vpiName:DCACHE_SUB_LINE_ADDR_W
|INT:4
|vpiParameter:
\_parameter: (DCACHE_TAG_W), line:138
|vpiName:DCACHE_TAG_W
|INT:1610612736
|vpiParameter:
\_parameter: (DCACHE_WAYS), line:134
|vpiName:DCACHE_WAYS
|INT:4
|vpiParameter:
\_parameter: (DIV_ALGORITHM), line:67
|vpiName:DIV_ALGORITHM
|INT:0
|vpiParameter:
\_parameter: (DIV_UNIT_WB_ID), line:192
|vpiName:DIV_UNIT_WB_ID
|INT:2
|vpiParameter:
\_parameter: (DTLB_DEPTH), line:152
|vpiName:DTLB_DEPTH
|INT:512
|vpiParameter:
\_parameter: (DTLB_WAYS), line:151
|vpiName:DTLB_WAYS
|INT:32
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (ENABLE_M_MODE), line:34
|vpiName:ENABLE_M_MODE
|INT:1
|vpiParameter:
\_parameter: (ENABLE_S_MODE), line:36
|vpiName:ENABLE_S_MODE
|INT:0
|vpiParameter:
\_parameter: (ENABLE_TRACE_INTERFACE), line:172
|vpiName:ENABLE_TRACE_INTERFACE
|INT:2
|vpiParameter:
\_parameter: (FETCH_BUFFER_DEPTH), line:168
|vpiName:FETCH_BUFFER_DEPTH
|INT:512
|vpiParameter:
\_parameter: (FPGA_VENDOR), line:27
|vpiName:FPGA_VENDOR
|STRING:"xilinx"
|vpiParameter:
\_parameter: (GC_UNIT_ID), line:196
|vpiName:GC_UNIT_ID
|INT:4
|vpiParameter:
\_parameter: (ICACHE_LINES), line:121
|vpiName:ICACHE_LINES
|INT:2
|vpiParameter:
\_parameter: (ICACHE_LINE_ADDR_W), line:123
|vpiName:ICACHE_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_LINE_W), line:124
|vpiName:ICACHE_LINE_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_SUB_LINE_ADDR_W), line:125
|vpiName:ICACHE_SUB_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_TAG_W), line:126
|vpiName:ICACHE_TAG_W
|INT:-2147483648
|vpiParameter:
\_parameter: (ICACHE_WAYS), line:122
|vpiName:ICACHE_WAYS
|INT:1
|vpiParameter:
\_parameter: (ITLB_DEPTH), line:146
|vpiName:ITLB_DEPTH
|INT:32
|vpiParameter:
\_parameter: (ITLB_WAYS), line:145
|vpiName:ITLB_WAYS
|INT:4
|vpiParameter:
\_parameter: (L1_CONNECTIONS), line:177
|vpiName:L1_CONNECTIONS
|INT:9
|vpiParameter:
\_parameter: (L1_DCACHE_ID), line:178
|vpiName:L1_DCACHE_ID
|INT:4
|vpiParameter:
\_parameter: (L1_DMMU_ID), line:179
|vpiName:L1_DMMU_ID
|INT:2
|vpiParameter:
\_parameter: (L1_ICACHE_ID), line:180
|vpiName:L1_ICACHE_ID
|INT:19
|vpiParameter:
\_parameter: (L1_IMMU_ID), line:181
|vpiName:L1_IMMU_ID
|INT:0
|vpiParameter:
\_parameter: (LS_UNIT_WB_ID), line:191
|vpiName:LS_UNIT_WB_ID
|INT:1
|vpiParameter:
\_parameter: (MAX_INFLIGHT_COUNT), line:167
|vpiName:MAX_INFLIGHT_COUNT
|INT:19
|vpiParameter:
\_parameter: (MEMORY_ADDR_H), line:103
|vpiName:MEMORY_ADDR_H
|INT:12
|vpiParameter:
\_parameter: (MEMORY_ADDR_L), line:102
|vpiName:MEMORY_ADDR_L
|INT:11
|vpiParameter:
\_parameter: (MEMORY_BIT_CHECK), line:104
|vpiName:MEMORY_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (MUL_UNIT_WB_ID), line:193
|vpiName:MUL_UNIT_WB_ID
|INT:512
|vpiParameter:
\_parameter: (NUM_UNITS), line:188
|vpiName:NUM_UNITS
|INT:2
|vpiParameter:
\_parameter: (NUM_WB_UNITS), line:186
|vpiName:NUM_WB_UNITS
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (RAS_DEPTH), line:161
|vpiName:RAS_DEPTH
|INT:2
|vpiParameter:
\_parameter: (RESET_VEC), line:39
|vpiName:RESET_VEC
|INT:-2147483648
|vpiParameter:
\_parameter: (SCRATCH_ADDR_H), line:99
|vpiName:SCRATCH_ADDR_H
|INT:9
|vpiParameter:
\_parameter: (SCRATCH_ADDR_L), line:98
|vpiName:SCRATCH_ADDR_L
|INT:8
|vpiParameter:
\_parameter: (SCRATCH_BIT_CHECK), line:100
|vpiName:SCRATCH_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (USE_AMO), line:70
|vpiName:USE_AMO
|INT:1
|vpiParameter:
\_parameter: (USE_BRANCH_PREDICTOR), line:158
|vpiName:USE_BRANCH_PREDICTOR
|INT:2
|vpiParameter:
\_parameter: (USE_BUS), line:88
|vpiName:USE_BUS
|INT:4
|vpiParameter:
\_parameter: (USE_DCACHE), line:92
|vpiName:USE_DCACHE
|INT:6
|vpiParameter:
\_parameter: (USE_DIV), line:49
|vpiName:USE_DIV
|INT:1
|vpiParameter:
\_parameter: (USE_DTAG_INVALIDATIONS), line:140
|vpiName:USE_DTAG_INVALIDATIONS
|INT:1879048191
|vpiParameter:
\_parameter: (USE_D_SCRATCH_MEM), line:79
|vpiName:USE_D_SCRATCH_MEM
|INT:3
|vpiParameter:
\_parameter: (USE_ICACHE), line:93
|vpiName:USE_ICACHE
|INT:7
|vpiParameter:
\_parameter: (USE_I_SCRATCH_MEM), line:78
|vpiName:USE_I_SCRATCH_MEM
|INT:2
|vpiParameter:
\_parameter: (USE_MUL), line:48
|vpiName:USE_MUL
|INT:1
|vpiParameter:
\_parameter: (WB_UNITS_WIDTH), line:187
|vpiName:WB_UNITS_WIDTH
|INT:32
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiParameter:
\_parameter: (i), line:130
|vpiName:i
|INT:0
|vpiNet:
\_logic_net: (clk), line:27, parent:i_cache
|vpiNet:
\_logic_net: (rst), line:28, parent:i_cache
|vpiNet:
\_logic_net: (icache_on), line:29, parent:i_cache
|vpiNet:
\_logic_net: (tag_hit), line:36, parent:i_cache
|vpiNet:
\_logic_net: (tag_hit_way), line:37, parent:i_cache
|vpiNet:
\_logic_net: (tag_update), line:39, parent:i_cache
|vpiName:tag_update
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk3.i_cache.tag_update
|vpiNetType:36
|vpiNet:
\_logic_net: (replacement_way), line:40, parent:i_cache
|vpiName:replacement_way
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk3.i_cache.replacement_way
|vpiNetType:36
|vpiRange:
\_range: , line:40
|vpiLeftRange:
\_constant: , line:40
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiRightRange:
\_constant: , line:40
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (tag_update_way), line:41, parent:i_cache
|vpiName:tag_update_way
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk3.i_cache.tag_update_way
|vpiNetType:36
|vpiRange:
\_range: , line:41
|vpiLeftRange:
\_constant: , line:41
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiRightRange:
\_constant: , line:41
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (word_count), line:43, parent:i_cache
|vpiName:word_count
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk3.i_cache.word_count
|vpiNetType:36
|vpiRange:
\_range: , line:43
|vpiLeftRange:
\_operation: , line:43
|vpiOpType:11
|vpiOperand:
\_sys_func_call: ($clog2), line:43
|vpiName:$clog2
|vpiArgument:
\_ref_obj: (ICACHE_LINE_W), line:43
|vpiName:ICACHE_LINE_W
|vpiOperand:
\_constant: , line:43
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:43
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (is_target_word), line:44, parent:i_cache
|vpiName:is_target_word
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk3.i_cache.is_target_word
|vpiNetType:36
|vpiNet:
\_logic_net: (line_complete), line:45, parent:i_cache
|vpiName:line_complete
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk3.i_cache.line_complete
|vpiNetType:36
|vpiNet:
\_logic_net: (miss_data), line:48, parent:i_cache
|vpiName:miss_data
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk3.i_cache.miss_data
|vpiNetType:36
|vpiRange:
\_range: , line:48
|vpiLeftRange:
\_constant: , line:48
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:48
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (miss_data_ready), line:50, parent:i_cache
|vpiName:miss_data_ready
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk3.i_cache.miss_data_ready
|vpiNetType:36
|vpiNet:
\_logic_net: (second_cycle), line:51, parent:i_cache
|vpiName:second_cycle
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk3.i_cache.second_cycle
|vpiNetType:36
|vpiNet:
\_logic_net: (idle), line:53, parent:i_cache
|vpiName:idle
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk3.i_cache.idle
|vpiNetType:36
|vpiNet:
\_logic_net: (memory_complete), line:54, parent:i_cache
|vpiName:memory_complete
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk3.i_cache.memory_complete
|vpiNetType:36
|vpiNet:
\_logic_net: (hit_allowed), line:55, parent:i_cache
|vpiName:hit_allowed
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk3.i_cache.hit_allowed
|vpiNetType:36
|vpiNet:
\_logic_net: (l1_request), line:30, parent:i_cache
|vpiName:l1_request
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk3.i_cache.l1_request
|vpiNet:
\_logic_net: (l1_response), line:31, parent:i_cache
|vpiName:l1_response
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk3.i_cache.l1_response
|vpiNet:
\_logic_net: (fetch_sub), line:33, parent:i_cache
|vpiName:fetch_sub
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk3.i_cache.fetch_sub
|vpiArrayNet:
\_array_net: (data_out), line:47, parent:i_cache
|vpiName:data_out
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk3.i_cache.data_out
|vpiSize:1
|vpiNet:
\_logic_net: , parent:data_out
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.genblk3.i_cache.data_out
|vpiNetType:36
|vpiRange:
\_range: , line:47
|vpiLeftRange:
\_constant: , line:47
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:47
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiRange:
\_range: , line:47
|vpiLeftRange:
\_constant: , line:47
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiRightRange:
\_constant: , line:47
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiParameter:
\_parameter: (ALU_UNIT_WB_ID), line:190
|vpiName:ALU_UNIT_WB_ID
|INT:32
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (BRANCH_PREDICTOR_WAYS), line:159
|vpiName:BRANCH_PREDICTOR_WAYS
|INT:9
|vpiParameter:
\_parameter: (BRANCH_TABLE_ENTRIES), line:160
|vpiName:BRANCH_TABLE_ENTRIES
|INT:4
|vpiParameter:
\_parameter: (BRANCH_UNIT_ID), line:195
|vpiName:BRANCH_UNIT_ID
|INT:8
|vpiParameter:
\_parameter: (BUS_ADDR_H), line:107
|vpiName:BUS_ADDR_H
|INT:1
|vpiParameter:
\_parameter: (BUS_ADDR_L), line:106
|vpiName:BUS_ADDR_L
|INT:0
|vpiParameter:
\_parameter: (BUS_BIT_CHECK), line:108
|vpiName:BUS_BIT_CHECK
|INT:1
|vpiParameter:
\_parameter: (BUS_TYPE), line:89
|vpiName:BUS_TYPE
|INT:5
|vpiParameter:
\_parameter: (COUNTER_W), line:42
|vpiName:COUNTER_W
|INT:33
|vpiParameter:
\_parameter: (CPU_ID), line:38
|vpiName:CPU_ID
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_ADDR_WIDTH), line:113
|vpiName:C_M_AXI_ADDR_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_DATA_WIDTH), line:114
|vpiName:C_M_AXI_DATA_WIDTH
|INT:1
|vpiParameter:
\_parameter: (DCACHE_LINES), line:133
|vpiName:DCACHE_LINES
|INT:-2146435073
|vpiParameter:
\_parameter: (DCACHE_LINE_ADDR_W), line:135
|vpiName:DCACHE_LINE_ADDR_W
|INT:1073741824
|vpiParameter:
\_parameter: (DCACHE_LINE_W), line:136
|vpiName:DCACHE_LINE_W
|INT:1342177279
|vpiParameter:
\_parameter: (DCACHE_SUB_LINE_ADDR_W), line:137
|vpiName:DCACHE_SUB_LINE_ADDR_W
|INT:4
|vpiParameter:
\_parameter: (DCACHE_TAG_W), line:138
|vpiName:DCACHE_TAG_W
|INT:1610612736
|vpiParameter:
\_parameter: (DCACHE_WAYS), line:134
|vpiName:DCACHE_WAYS
|INT:4
|vpiParameter:
\_parameter: (DIV_ALGORITHM), line:67
|vpiName:DIV_ALGORITHM
|INT:0
|vpiParameter:
\_parameter: (DIV_UNIT_WB_ID), line:192
|vpiName:DIV_UNIT_WB_ID
|INT:2
|vpiParameter:
\_parameter: (DTLB_DEPTH), line:152
|vpiName:DTLB_DEPTH
|INT:512
|vpiParameter:
\_parameter: (DTLB_WAYS), line:151
|vpiName:DTLB_WAYS
|INT:32
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (ENABLE_M_MODE), line:34
|vpiName:ENABLE_M_MODE
|INT:1
|vpiParameter:
\_parameter: (ENABLE_S_MODE), line:36
|vpiName:ENABLE_S_MODE
|INT:0
|vpiParameter:
\_parameter: (ENABLE_TRACE_INTERFACE), line:172
|vpiName:ENABLE_TRACE_INTERFACE
|INT:2
|vpiParameter:
\_parameter: (FETCH_BUFFER_DEPTH), line:168
|vpiName:FETCH_BUFFER_DEPTH
|INT:512
|vpiParameter:
\_parameter: (FPGA_VENDOR), line:27
|vpiName:FPGA_VENDOR
|STRING:"xilinx"
|vpiParameter:
\_parameter: (GC_UNIT_ID), line:196
|vpiName:GC_UNIT_ID
|INT:4
|vpiParameter:
\_parameter: (ICACHE_LINES), line:121
|vpiName:ICACHE_LINES
|INT:2
|vpiParameter:
\_parameter: (ICACHE_LINE_ADDR_W), line:123
|vpiName:ICACHE_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_LINE_W), line:124
|vpiName:ICACHE_LINE_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_SUB_LINE_ADDR_W), line:125
|vpiName:ICACHE_SUB_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_TAG_W), line:126
|vpiName:ICACHE_TAG_W
|INT:-2147483648
|vpiParameter:
\_parameter: (ICACHE_WAYS), line:122
|vpiName:ICACHE_WAYS
|INT:1
|vpiParameter:
\_parameter: (ITLB_DEPTH), line:146
|vpiName:ITLB_DEPTH
|INT:32
|vpiParameter:
\_parameter: (ITLB_WAYS), line:145
|vpiName:ITLB_WAYS
|INT:4
|vpiParameter:
\_parameter: (L1_CONNECTIONS), line:177
|vpiName:L1_CONNECTIONS
|INT:9
|vpiParameter:
\_parameter: (L1_DCACHE_ID), line:178
|vpiName:L1_DCACHE_ID
|INT:4
|vpiParameter:
\_parameter: (L1_DMMU_ID), line:179
|vpiName:L1_DMMU_ID
|INT:2
|vpiParameter:
\_parameter: (L1_ICACHE_ID), line:180
|vpiName:L1_ICACHE_ID
|INT:19
|vpiParameter:
\_parameter: (L1_IMMU_ID), line:181
|vpiName:L1_IMMU_ID
|INT:0
|vpiParameter:
\_parameter: (LS_UNIT_WB_ID), line:191
|vpiName:LS_UNIT_WB_ID
|INT:1
|vpiParameter:
\_parameter: (MAX_INFLIGHT_COUNT), line:167
|vpiName:MAX_INFLIGHT_COUNT
|INT:19
|vpiParameter:
\_parameter: (MEMORY_ADDR_H), line:103
|vpiName:MEMORY_ADDR_H
|INT:12
|vpiParameter:
\_parameter: (MEMORY_ADDR_L), line:102
|vpiName:MEMORY_ADDR_L
|INT:11
|vpiParameter:
\_parameter: (MEMORY_BIT_CHECK), line:104
|vpiName:MEMORY_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (MUL_UNIT_WB_ID), line:193
|vpiName:MUL_UNIT_WB_ID
|INT:512
|vpiParameter:
\_parameter: (NUM_UNITS), line:188
|vpiName:NUM_UNITS
|INT:2
|vpiParameter:
\_parameter: (NUM_WB_UNITS), line:186
|vpiName:NUM_WB_UNITS
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (RAS_DEPTH), line:161
|vpiName:RAS_DEPTH
|INT:2
|vpiParameter:
\_parameter: (RESET_VEC), line:39
|vpiName:RESET_VEC
|INT:-2147483648
|vpiParameter:
\_parameter: (SCRATCH_ADDR_H), line:99
|vpiName:SCRATCH_ADDR_H
|INT:9
|vpiParameter:
\_parameter: (SCRATCH_ADDR_L), line:98
|vpiName:SCRATCH_ADDR_L
|INT:8
|vpiParameter:
\_parameter: (SCRATCH_BIT_CHECK), line:100
|vpiName:SCRATCH_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (USE_AMO), line:70
|vpiName:USE_AMO
|INT:1
|vpiParameter:
\_parameter: (USE_BRANCH_PREDICTOR), line:158
|vpiName:USE_BRANCH_PREDICTOR
|INT:2
|vpiParameter:
\_parameter: (USE_BUS), line:88
|vpiName:USE_BUS
|INT:4
|vpiParameter:
\_parameter: (USE_DCACHE), line:92
|vpiName:USE_DCACHE
|INT:6
|vpiParameter:
\_parameter: (USE_DIV), line:49
|vpiName:USE_DIV
|INT:1
|vpiParameter:
\_parameter: (USE_DTAG_INVALIDATIONS), line:140
|vpiName:USE_DTAG_INVALIDATIONS
|INT:1879048191
|vpiParameter:
\_parameter: (USE_D_SCRATCH_MEM), line:79
|vpiName:USE_D_SCRATCH_MEM
|INT:3
|vpiParameter:
\_parameter: (USE_ICACHE), line:93
|vpiName:USE_ICACHE
|INT:7
|vpiParameter:
\_parameter: (USE_I_SCRATCH_MEM), line:78
|vpiName:USE_I_SCRATCH_MEM
|INT:2
|vpiParameter:
\_parameter: (USE_MUL), line:48
|vpiName:USE_MUL
|INT:1
|vpiParameter:
\_parameter: (WB_UNITS_WIDTH), line:187
|vpiName:WB_UNITS_WIDTH
|INT:32
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiParameter:
\_parameter: (ALU_UNIT_WB_ID), line:190
|vpiName:ALU_UNIT_WB_ID
|INT:32
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (BRANCH_PREDICTOR_WAYS), line:159
|vpiName:BRANCH_PREDICTOR_WAYS
|INT:9
|vpiParameter:
\_parameter: (BRANCH_TABLE_ENTRIES), line:160
|vpiName:BRANCH_TABLE_ENTRIES
|INT:4
|vpiParameter:
\_parameter: (BRANCH_UNIT_ID), line:195
|vpiName:BRANCH_UNIT_ID
|INT:8
|vpiParameter:
\_parameter: (BUS_ADDR_H), line:107
|vpiName:BUS_ADDR_H
|INT:1
|vpiParameter:
\_parameter: (BUS_ADDR_L), line:106
|vpiName:BUS_ADDR_L
|INT:0
|vpiParameter:
\_parameter: (BUS_BIT_CHECK), line:108
|vpiName:BUS_BIT_CHECK
|INT:1
|vpiParameter:
\_parameter: (BUS_TYPE), line:89
|vpiName:BUS_TYPE
|INT:5
|vpiParameter:
\_parameter: (COUNTER_W), line:42
|vpiName:COUNTER_W
|INT:33
|vpiParameter:
\_parameter: (CPU_ID), line:38
|vpiName:CPU_ID
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_ADDR_WIDTH), line:113
|vpiName:C_M_AXI_ADDR_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_DATA_WIDTH), line:114
|vpiName:C_M_AXI_DATA_WIDTH
|INT:1
|vpiParameter:
\_parameter: (DCACHE_LINES), line:133
|vpiName:DCACHE_LINES
|INT:-2146435073
|vpiParameter:
\_parameter: (DCACHE_LINE_ADDR_W), line:135
|vpiName:DCACHE_LINE_ADDR_W
|INT:1073741824
|vpiParameter:
\_parameter: (DCACHE_LINE_W), line:136
|vpiName:DCACHE_LINE_W
|INT:1342177279
|vpiParameter:
\_parameter: (DCACHE_SUB_LINE_ADDR_W), line:137
|vpiName:DCACHE_SUB_LINE_ADDR_W
|INT:4
|vpiParameter:
\_parameter: (DCACHE_TAG_W), line:138
|vpiName:DCACHE_TAG_W
|INT:1610612736
|vpiParameter:
\_parameter: (DCACHE_WAYS), line:134
|vpiName:DCACHE_WAYS
|INT:4
|vpiParameter:
\_parameter: (DIV_ALGORITHM), line:67
|vpiName:DIV_ALGORITHM
|INT:0
|vpiParameter:
\_parameter: (DIV_UNIT_WB_ID), line:192
|vpiName:DIV_UNIT_WB_ID
|INT:2
|vpiParameter:
\_parameter: (DTLB_DEPTH), line:152
|vpiName:DTLB_DEPTH
|INT:512
|vpiParameter:
\_parameter: (DTLB_WAYS), line:151
|vpiName:DTLB_WAYS
|INT:32
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (ENABLE_M_MODE), line:34
|vpiName:ENABLE_M_MODE
|INT:1
|vpiParameter:
\_parameter: (ENABLE_S_MODE), line:36
|vpiName:ENABLE_S_MODE
|INT:0
|vpiParameter:
\_parameter: (ENABLE_TRACE_INTERFACE), line:172
|vpiName:ENABLE_TRACE_INTERFACE
|INT:2
|vpiParameter:
\_parameter: (FETCH_BUFFER_DEPTH), line:168
|vpiName:FETCH_BUFFER_DEPTH
|INT:512
|vpiParameter:
\_parameter: (FPGA_VENDOR), line:27
|vpiName:FPGA_VENDOR
|STRING:"xilinx"
|vpiParameter:
\_parameter: (GC_UNIT_ID), line:196
|vpiName:GC_UNIT_ID
|INT:4
|vpiParameter:
\_parameter: (ICACHE_LINES), line:121
|vpiName:ICACHE_LINES
|INT:2
|vpiParameter:
\_parameter: (ICACHE_LINE_ADDR_W), line:123
|vpiName:ICACHE_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_LINE_W), line:124
|vpiName:ICACHE_LINE_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_SUB_LINE_ADDR_W), line:125
|vpiName:ICACHE_SUB_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_TAG_W), line:126
|vpiName:ICACHE_TAG_W
|INT:-2147483648
|vpiParameter:
\_parameter: (ICACHE_WAYS), line:122
|vpiName:ICACHE_WAYS
|INT:1
|vpiParameter:
\_parameter: (ITLB_DEPTH), line:146
|vpiName:ITLB_DEPTH
|INT:32
|vpiParameter:
\_parameter: (ITLB_WAYS), line:145
|vpiName:ITLB_WAYS
|INT:4
|vpiParameter:
\_parameter: (L1_CONNECTIONS), line:177
|vpiName:L1_CONNECTIONS
|INT:9
|vpiParameter:
\_parameter: (L1_DCACHE_ID), line:178
|vpiName:L1_DCACHE_ID
|INT:4
|vpiParameter:
\_parameter: (L1_DMMU_ID), line:179
|vpiName:L1_DMMU_ID
|INT:2
|vpiParameter:
\_parameter: (L1_ICACHE_ID), line:180
|vpiName:L1_ICACHE_ID
|INT:19
|vpiParameter:
\_parameter: (L1_IMMU_ID), line:181
|vpiName:L1_IMMU_ID
|INT:0
|vpiParameter:
\_parameter: (LS_UNIT_WB_ID), line:191
|vpiName:LS_UNIT_WB_ID
|INT:1
|vpiParameter:
\_parameter: (MAX_INFLIGHT_COUNT), line:167
|vpiName:MAX_INFLIGHT_COUNT
|INT:19
|vpiParameter:
\_parameter: (MEMORY_ADDR_H), line:103
|vpiName:MEMORY_ADDR_H
|INT:12
|vpiParameter:
\_parameter: (MEMORY_ADDR_L), line:102
|vpiName:MEMORY_ADDR_L
|INT:11
|vpiParameter:
\_parameter: (MEMORY_BIT_CHECK), line:104
|vpiName:MEMORY_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (MUL_UNIT_WB_ID), line:193
|vpiName:MUL_UNIT_WB_ID
|INT:512
|vpiParameter:
\_parameter: (NUM_UNITS), line:188
|vpiName:NUM_UNITS
|INT:2
|vpiParameter:
\_parameter: (NUM_WB_UNITS), line:186
|vpiName:NUM_WB_UNITS
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (RAS_DEPTH), line:161
|vpiName:RAS_DEPTH
|INT:2
|vpiParameter:
\_parameter: (RESET_VEC), line:39
|vpiName:RESET_VEC
|INT:-2147483648
|vpiParameter:
\_parameter: (SCRATCH_ADDR_H), line:99
|vpiName:SCRATCH_ADDR_H
|INT:9
|vpiParameter:
\_parameter: (SCRATCH_ADDR_L), line:98
|vpiName:SCRATCH_ADDR_L
|INT:8
|vpiParameter:
\_parameter: (SCRATCH_BIT_CHECK), line:100
|vpiName:SCRATCH_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (USE_AMO), line:70
|vpiName:USE_AMO
|INT:1
|vpiParameter:
\_parameter: (USE_BRANCH_PREDICTOR), line:158
|vpiName:USE_BRANCH_PREDICTOR
|INT:2
|vpiParameter:
\_parameter: (USE_BUS), line:88
|vpiName:USE_BUS
|INT:4
|vpiParameter:
\_parameter: (USE_DCACHE), line:92
|vpiName:USE_DCACHE
|INT:6
|vpiParameter:
\_parameter: (USE_DIV), line:49
|vpiName:USE_DIV
|INT:1
|vpiParameter:
\_parameter: (USE_DTAG_INVALIDATIONS), line:140
|vpiName:USE_DTAG_INVALIDATIONS
|INT:1879048191
|vpiParameter:
\_parameter: (USE_D_SCRATCH_MEM), line:79
|vpiName:USE_D_SCRATCH_MEM
|INT:3
|vpiParameter:
\_parameter: (USE_ICACHE), line:93
|vpiName:USE_ICACHE
|INT:7
|vpiParameter:
\_parameter: (USE_I_SCRATCH_MEM), line:78
|vpiName:USE_I_SCRATCH_MEM
|INT:2
|vpiParameter:
\_parameter: (USE_MUL), line:48
|vpiName:USE_MUL
|INT:1
|vpiParameter:
\_parameter: (WB_UNITS_WIDTH), line:187
|vpiName:WB_UNITS_WIDTH
|INT:32
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiNet:
\_logic_net: (clk), line:27, parent:fetch_block
|vpiNet:
\_logic_net: (rst), line:28, parent:fetch_block
|vpiNet:
\_logic_net: (branch_flush), line:30, parent:fetch_block
|vpiNet:
\_logic_net: (gc_fetch_flush), line:31, parent:fetch_block
|vpiNet:
\_logic_net: (gc_fetch_pc_override), line:32, parent:fetch_block
|vpiNet:
\_logic_net: (exception), line:33, parent:fetch_block
|vpiNet:
\_logic_net: (gc_fetch_pc), line:34, parent:fetch_block
|vpiNet:
\_logic_net: (icache_on), line:41, parent:fetch_block
|vpiNet:
\_logic_net: (pre_decode_pop), line:45, parent:fetch_block
|vpiNet:
\_logic_net: (pre_decode_instruction), line:47, parent:fetch_block
|vpiNet:
\_logic_net: (pre_decode_pc), line:48, parent:fetch_block
|vpiNet:
\_logic_net: (branch_metadata), line:49, parent:fetch_block
|vpiNet:
\_logic_net: (branch_prediction_used), line:50, parent:fetch_block
|vpiNet:
\_logic_net: (bp_update_way), line:51, parent:fetch_block
|vpiNet:
\_logic_net: (pre_decode_push), line:52, parent:fetch_block
|vpiNet:
\_logic_net: (sub_unit_address_match), line:66, parent:fetch_block
|vpiName:sub_unit_address_match
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.sub_unit_address_match
|vpiNetType:36
|vpiRange:
\_range: , line:66
|vpiLeftRange:
\_constant: , line:66
|vpiConstType:7
|vpiDecompile:8
|vpiSize:32
|INT:8
|vpiRightRange:
\_constant: , line:66
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (last_sub_unit_id), line:67, parent:fetch_block
|vpiName:last_sub_unit_id
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.last_sub_unit_id
|vpiNetType:36
|vpiRange:
\_range: , line:67
|vpiLeftRange:
\_constant: , line:67
|vpiConstType:7
|vpiDecompile:8
|vpiSize:32
|INT:8
|vpiRightRange:
\_constant: , line:67
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (unit_ready), line:68, parent:fetch_block
|vpiName:unit_ready
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.unit_ready
|vpiNetType:36
|vpiRange:
\_range: , line:68
|vpiLeftRange:
\_constant: , line:68
|vpiConstType:7
|vpiDecompile:8
|vpiSize:32
|INT:8
|vpiRightRange:
\_constant: , line:68
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (unit_data_valid), line:69, parent:fetch_block
|vpiName:unit_data_valid
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.unit_data_valid
|vpiNetType:36
|vpiRange:
\_range: , line:69
|vpiLeftRange:
\_constant: , line:69
|vpiConstType:7
|vpiDecompile:8
|vpiSize:32
|INT:8
|vpiRightRange:
\_constant: , line:69
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (units_ready), line:73, parent:fetch_block
|vpiName:units_ready
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.units_ready
|vpiNetType:36
|vpiNet:
\_logic_net: (units_data_valid), line:74, parent:fetch_block
|vpiName:units_data_valid
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.units_data_valid
|vpiNetType:36
|vpiNet:
\_logic_net: (next_pc), line:76, parent:fetch_block
|vpiName:next_pc
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.next_pc
|vpiNetType:36
|vpiRange:
\_range: , line:76
|vpiLeftRange:
\_constant: , line:76
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:76
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (pc), line:77, parent:fetch_block
|vpiName:pc
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.pc
|vpiNetType:36
|vpiRange:
\_range: , line:77
|vpiLeftRange:
\_constant: , line:77
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:77
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (flush_or_rst), line:79, parent:fetch_block
|vpiNet:
\_logic_net: (inflight_count), line:80, parent:fetch_block
|vpiName:inflight_count
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.inflight_count
|vpiNetType:36
|vpiRange:
\_range: , line:80
|vpiLeftRange:
\_constant: , line:80
|vpiConstType:7
|vpiDecompile:9
|vpiSize:32
|INT:9
|vpiRightRange:
\_constant: , line:80
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (space_in_inst_buffer), line:82, parent:fetch_block
|vpiName:space_in_inst_buffer
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.space_in_inst_buffer
|vpiNetType:36
|vpiNet:
\_logic_net: (new_mem_request), line:83, parent:fetch_block
|vpiName:new_mem_request
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.new_mem_request
|vpiNetType:36
|vpiNet:
\_logic_net: (delayed_flush), line:86, parent:fetch_block
|vpiName:delayed_flush
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.delayed_flush
|vpiNetType:36
|vpiNet:
\_logic_net: (stage2_phys_address), line:87, parent:fetch_block
|vpiName:stage2_phys_address
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.stage2_phys_address
|vpiNetType:36
|vpiRange:
\_range: , line:87
|vpiLeftRange:
\_constant: , line:87
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:87
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (stage2_valid), line:88, parent:fetch_block
|vpiName:stage2_valid
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.stage2_valid
|vpiNetType:36
|vpiNet:
\_logic_net: (bp), line:36, parent:fetch_block
|vpiName:bp
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.bp
|vpiNet:
\_logic_net: (ras), line:37, parent:fetch_block
|vpiName:ras
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.ras
|vpiNet:
\_logic_net: (tlb), line:39, parent:fetch_block
|vpiName:tlb
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.tlb
|vpiNet:
\_logic_net: (instruction_bram), line:40, parent:fetch_block
|vpiName:instruction_bram
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.instruction_bram
|vpiNet:
\_logic_net: (l1_request), line:42, parent:fetch_block
|vpiName:l1_request
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.l1_request
|vpiNet:
\_logic_net: (l1_response), line:43, parent:fetch_block
|vpiName:l1_response
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.l1_response
|vpiInstance:
\_module: work@taiga (cpu), file:third_party/cores/taiga/examples/zedboard/taiga_wrapper.sv, line:233, parent:work@taiga_wrapper
|vpiArrayNet:
\_array_net: (unit_data_array), line:70, parent:fetch_block
|vpiName:unit_data_array
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.unit_data_array
|vpiSize:9
|vpiNet:
\_logic_net: , parent:unit_data_array
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.unit_data_array
|vpiNetType:36
|vpiRange:
\_range: , line:70
|vpiLeftRange:
\_constant: , line:70
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:70
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiRange:
\_range: , line:70
|vpiLeftRange:
\_constant: , line:70
|vpiConstType:7
|vpiDecompile:8
|vpiSize:32
|INT:8
|vpiRightRange:
\_constant: , line:70
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiArrayNet:
\_array_net: (anded_unit_data_array), line:71, parent:fetch_block
|vpiName:anded_unit_data_array
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.anded_unit_data_array
|vpiSize:9
|vpiNet:
\_logic_net: , parent:anded_unit_data_array
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.anded_unit_data_array
|vpiNetType:36
|vpiRange:
\_range: , line:71
|vpiLeftRange:
\_constant: , line:71
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:71
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiRange:
\_range: , line:71
|vpiLeftRange:
\_constant: , line:71
|vpiConstType:7
|vpiDecompile:8
|vpiSize:32
|INT:8
|vpiRightRange:
\_constant: , line:71
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiVariables:
\_logic_var: (metadata), line:39, parent:fetch_block
|vpiName:metadata
|vpiFullName:work@taiga_wrapper.cpu.fetch_block.metadata
|vpiParameter:
\_parameter: (ALU_UNIT_WB_ID), line:190
|vpiName:ALU_UNIT_WB_ID
|INT:32
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (BRAM_ID), line:58
|vpiName:BRAM_ID
|INT:0
|vpiParameter:
\_parameter: (BRANCH_PREDICTOR_WAYS), line:159
|vpiName:BRANCH_PREDICTOR_WAYS
|INT:9
|vpiParameter:
\_parameter: (BRANCH_TABLE_ENTRIES), line:160
|vpiName:BRANCH_TABLE_ENTRIES
|INT:4
|vpiParameter:
\_parameter: (BRANCH_UNIT_ID), line:195
|vpiName:BRANCH_UNIT_ID
|INT:8
|vpiParameter:
\_parameter: (BUS_ADDR_H), line:107
|vpiName:BUS_ADDR_H
|INT:1
|vpiParameter:
\_parameter: (BUS_ADDR_L), line:106
|vpiName:BUS_ADDR_L
|INT:0
|vpiParameter:
\_parameter: (BUS_BIT_CHECK), line:108
|vpiName:BUS_BIT_CHECK
|INT:1
|vpiParameter:
\_parameter: (BUS_TYPE), line:89
|vpiName:BUS_TYPE
|INT:5
|vpiParameter:
\_parameter: (COUNTER_W), line:42
|vpiName:COUNTER_W
|INT:33
|vpiParameter:
\_parameter: (CPU_ID), line:38
|vpiName:CPU_ID
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_ADDR_WIDTH), line:113
|vpiName:C_M_AXI_ADDR_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_DATA_WIDTH), line:114
|vpiName:C_M_AXI_DATA_WIDTH
|INT:1
|vpiParameter:
\_parameter: (DCACHE_LINES), line:133
|vpiName:DCACHE_LINES
|INT:-2146435073
|vpiParameter:
\_parameter: (DCACHE_LINE_ADDR_W), line:135
|vpiName:DCACHE_LINE_ADDR_W
|INT:1073741824
|vpiParameter:
\_parameter: (DCACHE_LINE_W), line:136
|vpiName:DCACHE_LINE_W
|INT:1342177279
|vpiParameter:
\_parameter: (DCACHE_SUB_LINE_ADDR_W), line:137
|vpiName:DCACHE_SUB_LINE_ADDR_W
|INT:4
|vpiParameter:
\_parameter: (DCACHE_TAG_W), line:138
|vpiName:DCACHE_TAG_W
|INT:1610612736
|vpiParameter:
\_parameter: (DCACHE_WAYS), line:134
|vpiName:DCACHE_WAYS
|INT:4
|vpiParameter:
\_parameter: (DIV_ALGORITHM), line:67
|vpiName:DIV_ALGORITHM
|INT:0
|vpiParameter:
\_parameter: (DIV_UNIT_WB_ID), line:192
|vpiName:DIV_UNIT_WB_ID
|INT:2
|vpiParameter:
\_parameter: (DTLB_DEPTH), line:152
|vpiName:DTLB_DEPTH
|INT:512
|vpiParameter:
\_parameter: (DTLB_WAYS), line:151
|vpiName:DTLB_WAYS
|INT:32
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (ENABLE_M_MODE), line:34
|vpiName:ENABLE_M_MODE
|INT:1
|vpiParameter:
\_parameter: (ENABLE_S_MODE), line:36
|vpiName:ENABLE_S_MODE
|INT:0
|vpiParameter:
\_parameter: (ENABLE_TRACE_INTERFACE), line:172
|vpiName:ENABLE_TRACE_INTERFACE
|INT:2
|vpiParameter:
\_parameter: (FETCH_BUFFER_DEPTH), line:168
|vpiName:FETCH_BUFFER_DEPTH
|INT:512
|vpiParameter:
\_parameter: (FETCH_BUFFER_DEPTH_W), line:61
|vpiName:FETCH_BUFFER_DEPTH_W
|INT:9
|vpiParameter:
\_parameter: (FPGA_VENDOR), line:27
|vpiName:FPGA_VENDOR
|STRING:"xilinx"
|vpiParameter:
\_parameter: (GC_UNIT_ID), line:196
|vpiName:GC_UNIT_ID
|INT:4
|vpiParameter:
\_parameter: (ICACHE_ID), line:59
|vpiName:ICACHE_ID
|INT:2
|vpiParameter:
\_parameter: (ICACHE_LINES), line:121
|vpiName:ICACHE_LINES
|INT:2
|vpiParameter:
\_parameter: (ICACHE_LINE_ADDR_W), line:123
|vpiName:ICACHE_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_LINE_W), line:124
|vpiName:ICACHE_LINE_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_SUB_LINE_ADDR_W), line:125
|vpiName:ICACHE_SUB_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_TAG_W), line:126
|vpiName:ICACHE_TAG_W
|INT:-2147483648
|vpiParameter:
\_parameter: (ICACHE_WAYS), line:122
|vpiName:ICACHE_WAYS
|INT:1
|vpiParameter:
\_parameter: (ITLB_DEPTH), line:146
|vpiName:ITLB_DEPTH
|INT:32
|vpiParameter:
\_parameter: (ITLB_WAYS), line:145
|vpiName:ITLB_WAYS
|INT:4
|vpiParameter:
\_parameter: (L1_CONNECTIONS), line:177
|vpiName:L1_CONNECTIONS
|INT:9
|vpiParameter:
\_parameter: (L1_DCACHE_ID), line:178
|vpiName:L1_DCACHE_ID
|INT:4
|vpiParameter:
\_parameter: (L1_DMMU_ID), line:179
|vpiName:L1_DMMU_ID
|INT:2
|vpiParameter:
\_parameter: (L1_ICACHE_ID), line:180
|vpiName:L1_ICACHE_ID
|INT:19
|vpiParameter:
\_parameter: (L1_IMMU_ID), line:181
|vpiName:L1_IMMU_ID
|INT:0
|vpiParameter:
\_parameter: (LS_UNIT_WB_ID), line:191
|vpiName:LS_UNIT_WB_ID
|INT:1
|vpiParameter:
\_parameter: (MAX_INFLIGHT_COUNT), line:167
|vpiName:MAX_INFLIGHT_COUNT
|INT:19
|vpiParameter:
\_parameter: (MEMORY_ADDR_H), line:103
|vpiName:MEMORY_ADDR_H
|INT:12
|vpiParameter:
\_parameter: (MEMORY_ADDR_L), line:102
|vpiName:MEMORY_ADDR_L
|INT:11
|vpiParameter:
\_parameter: (MEMORY_BIT_CHECK), line:104
|vpiName:MEMORY_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (MUL_UNIT_WB_ID), line:193
|vpiName:MUL_UNIT_WB_ID
|INT:512
|vpiParameter:
\_parameter: (NEXT_ID_DEPTH), line:62
|vpiName:NEXT_ID_DEPTH
|INT:7
|vpiParameter:
\_parameter: (NUM_SUB_UNITS), line:55
|vpiName:NUM_SUB_UNITS
|INT:9
|vpiParameter:
\_parameter: (NUM_SUB_UNITS_W), line:56
|vpiName:NUM_SUB_UNITS_W
|INT:0
|vpiParameter:
\_parameter: (NUM_UNITS), line:188
|vpiName:NUM_UNITS
|INT:2
|vpiParameter:
\_parameter: (NUM_WB_UNITS), line:186
|vpiName:NUM_WB_UNITS
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (RAS_DEPTH), line:161
|vpiName:RAS_DEPTH
|INT:2
|vpiParameter:
\_parameter: (RESET_VEC), line:39
|vpiName:RESET_VEC
|INT:-2147483648
|vpiParameter:
\_parameter: (SCRATCH_ADDR_H), line:99
|vpiName:SCRATCH_ADDR_H
|INT:9
|vpiParameter:
\_parameter: (SCRATCH_ADDR_L), line:98
|vpiName:SCRATCH_ADDR_L
|INT:8
|vpiParameter:
\_parameter: (SCRATCH_BIT_CHECK), line:100
|vpiName:SCRATCH_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (USE_AMO), line:70
|vpiName:USE_AMO
|INT:1
|vpiParameter:
\_parameter: (USE_BRANCH_PREDICTOR), line:158
|vpiName:USE_BRANCH_PREDICTOR
|INT:2
|vpiParameter:
\_parameter: (USE_BUS), line:88
|vpiName:USE_BUS
|INT:4
|vpiParameter:
\_parameter: (USE_DCACHE), line:92
|vpiName:USE_DCACHE
|INT:6
|vpiParameter:
\_parameter: (USE_DIV), line:49
|vpiName:USE_DIV
|INT:1
|vpiParameter:
\_parameter: (USE_DTAG_INVALIDATIONS), line:140
|vpiName:USE_DTAG_INVALIDATIONS
|INT:1879048191
|vpiParameter:
\_parameter: (USE_D_SCRATCH_MEM), line:79
|vpiName:USE_D_SCRATCH_MEM
|INT:3
|vpiParameter:
\_parameter: (USE_ICACHE), line:93
|vpiName:USE_ICACHE
|INT:7
|vpiParameter:
\_parameter: (USE_I_SCRATCH_MEM), line:78
|vpiName:USE_I_SCRATCH_MEM
|INT:2
|vpiParameter:
\_parameter: (USE_MUL), line:48
|vpiName:USE_MUL
|INT:1
|vpiParameter:
\_parameter: (WB_UNITS_WIDTH), line:187
|vpiName:WB_UNITS_WIDTH
|INT:32
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiModule:
\_module: work@branch_predictor (bp_block), file:third_party/cores/taiga/core/taiga.sv, line:161, parent:cpu
|vpiDefName:work@branch_predictor
|vpiName:bp_block
|vpiFullName:work@taiga_wrapper.cpu.bp_block
|vpiPort:
\_port: (clk), line:27, parent:bp_block
|vpiName:clk
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (clk), line:161
|vpiName:clk
|vpiActual:
\_logic_net: (clk), line:27, parent:cpu
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (clk), line:27, parent:bp_block
|vpiName:clk
|vpiFullName:work@taiga_wrapper.cpu.bp_block.clk
|vpiNetType:36
|vpiPort:
\_port: (rst), line:28, parent:bp_block
|vpiName:rst
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (rst), line:161
|vpiName:rst
|vpiActual:
\_logic_net: (rst), line:28, parent:cpu
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (rst), line:28, parent:bp_block
|vpiName:rst
|vpiFullName:work@taiga_wrapper.cpu.bp_block.rst
|vpiNetType:36
|vpiPort:
\_port: (bp), line:29, parent:bp_block
|vpiName:bp
|vpiDirection:5
|vpiHighConn:
\_ref_obj: (bp), line:161
|vpiName:bp
|vpiActual:
\_interface: work@branch_predictor_interface (bp), file:third_party/cores/taiga/core/taiga.sv, line:50
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_modport: (branch_predictor)
|vpiName:branch_predictor
|vpiIODecl:
\_io_decl: (if_pc)
|vpiName:if_pc
|vpiDirection:1
|vpiExpr:
\_logic_net: (if_pc), line:29
|vpiName:if_pc
|vpiNetType:36
|vpiRange:
\_range: , line:29
|vpiLeftRange:
\_constant: , line:29
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:29
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (new_mem_request)
|vpiName:new_mem_request
|vpiDirection:1
|vpiExpr:
\_logic_net: (new_mem_request), line:30
|vpiName:new_mem_request
|vpiNetType:36
|vpiIODecl:
\_io_decl: (next_pc)
|vpiName:next_pc
|vpiDirection:1
|vpiExpr:
\_logic_net: (next_pc), line:31
|vpiName:next_pc
|vpiNetType:36
|vpiRange:
\_range: , line:31
|vpiLeftRange:
\_constant: , line:31
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:31
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (branch_flush_pc)
|vpiName:branch_flush_pc
|vpiDirection:2
|vpiExpr:
\_logic_net: (branch_flush_pc), line:34
|vpiName:branch_flush_pc
|vpiNetType:36
|vpiRange:
\_range: , line:34
|vpiLeftRange:
\_constant: , line:34
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:34
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (predicted_pc)
|vpiName:predicted_pc
|vpiDirection:2
|vpiExpr:
\_logic_net: (predicted_pc), line:35
|vpiName:predicted_pc
|vpiNetType:36
|vpiRange:
\_range: , line:35
|vpiLeftRange:
\_constant: , line:35
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:35
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (use_prediction)
|vpiName:use_prediction
|vpiDirection:2
|vpiExpr:
\_logic_net: (use_prediction), line:36
|vpiName:use_prediction
|vpiNetType:36
|vpiIODecl:
\_io_decl: (update_way)
|vpiName:update_way
|vpiDirection:2
|vpiExpr:
\_logic_net: (update_way), line:37
|vpiName:update_way
|vpiNetType:36
|vpiRange:
\_range: , line:37
|vpiLeftRange:
\_constant: , line:37
|vpiConstType:7
|vpiDecompile:8
|vpiSize:32
|INT:8
|vpiRightRange:
\_constant: , line:37
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (use_ras)
|vpiName:use_ras
|vpiDirection:2
|vpiExpr:
\_logic_net: (use_ras), line:38
|vpiName:use_ras
|vpiNetType:36
|vpiIODecl:
\_io_decl: (metadata)
|vpiName:metadata
|vpiDirection:2
|vpiInterface:
\_interface: work@branch_predictor_interface (bp), file:third_party/cores/taiga/core/taiga.sv, line:161
|vpiDefName:work@branch_predictor_interface
|vpiName:bp
|vpiModport:
\_modport: (branch_predictor)
|vpiModport:
\_modport: (fetch)
|vpiName:fetch
|vpiIODecl:
\_io_decl: (branch_flush_pc)
|vpiName:branch_flush_pc
|vpiDirection:1
|vpiExpr:
\_logic_net: (branch_flush_pc), line:34
|vpiIODecl:
\_io_decl: (predicted_pc)
|vpiName:predicted_pc
|vpiDirection:1
|vpiExpr:
\_logic_net: (predicted_pc), line:35
|vpiIODecl:
\_io_decl: (use_prediction)
|vpiName:use_prediction
|vpiDirection:1
|vpiExpr:
\_logic_net: (use_prediction), line:36
|vpiIODecl:
\_io_decl: (update_way)
|vpiName:update_way
|vpiDirection:1
|vpiExpr:
\_logic_net: (update_way), line:37
|vpiIODecl:
\_io_decl: (use_ras)
|vpiName:use_ras
|vpiDirection:1
|vpiExpr:
\_logic_net: (use_ras), line:38
|vpiIODecl:
\_io_decl: (metadata)
|vpiName:metadata
|vpiDirection:1
|vpiIODecl:
\_io_decl: (if_pc)
|vpiName:if_pc
|vpiDirection:2
|vpiExpr:
\_logic_net: (if_pc), line:29
|vpiIODecl:
\_io_decl: (new_mem_request)
|vpiName:new_mem_request
|vpiDirection:2
|vpiExpr:
\_logic_net: (new_mem_request), line:30
|vpiIODecl:
\_io_decl: (next_pc)
|vpiName:next_pc
|vpiDirection:2
|vpiExpr:
\_logic_net: (next_pc), line:31
|vpiInterface:
\_interface: work@branch_predictor_interface (bp), file:third_party/cores/taiga/core/taiga.sv, line:161
|vpiPort:
\_port: (br_results), line:30, parent:bp_block
|vpiName:br_results
|vpiDirection:1
|vpiTypedef:
\_struct_typespec: (branch_results_t), line:330
|vpiHighConn:
\_ref_obj: (br_results), line:161
|vpiName:br_results
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (br_results), line:30, parent:bp_block
|vpiName:br_results
|vpiFullName:work@taiga_wrapper.cpu.bp_block.br_results
|vpiModule:
\_module: work@cycler (replacement_policy), file:third_party/cores/taiga/core/branch_predictor.sv, line:57, parent:bp_block
|vpiDefName:work@cycler
|vpiName:replacement_policy
|vpiFullName:work@taiga_wrapper.cpu.bp_block.replacement_policy
|vpiPort:
\_port: (clk), line:29, parent:replacement_policy
|vpiName:clk
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (clk), line:57
|vpiName:clk
|vpiActual:
\_logic_net: (clk), line:27, parent:bp_block
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (clk), line:29, parent:replacement_policy
|vpiName:clk
|vpiFullName:work@taiga_wrapper.cpu.bp_block.replacement_policy.clk
|vpiNetType:36
|vpiPort:
\_port: (rst), line:30, parent:replacement_policy
|vpiName:rst
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (rst), line:57
|vpiName:rst
|vpiActual:
\_logic_net: (rst), line:28, parent:bp_block
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (rst), line:30, parent:replacement_policy
|vpiName:rst
|vpiFullName:work@taiga_wrapper.cpu.bp_block.replacement_policy.rst
|vpiNetType:36
|vpiPort:
\_port: (en), line:31, parent:replacement_policy
|vpiName:en
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (en), line:57
|vpiName:en
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (en), line:31, parent:replacement_policy
|vpiName:en
|vpiFullName:work@taiga_wrapper.cpu.bp_block.replacement_policy.en
|vpiNetType:36
|vpiPort:
\_port: (one_hot), line:32, parent:replacement_policy
|vpiName:one_hot
|vpiDirection:2
|vpiHighConn:
\_ref_obj: (one_hot), line:57
|vpiName:one_hot
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (one_hot), line:32, parent:replacement_policy
|vpiName:one_hot
|vpiFullName:work@taiga_wrapper.cpu.bp_block.replacement_policy.one_hot
|vpiNetType:36
|vpiRange:
\_range: , line:32
|vpiLeftRange:
\_constant: , line:32
|vpiConstType:7
|vpiDecompile:8
|vpiSize:32
|INT:8
|vpiRightRange:
\_constant: , line:32
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiGenScopeArray:
\_gen_scope_array: (genblk1), line:39, parent:replacement_policy
|vpiName:genblk1
|vpiFullName:work@taiga_wrapper.cpu.bp_block.replacement_policy.genblk1
|vpiGenScope:
\_gen_scope: , parent:genblk1
|vpiFullName:work@taiga_wrapper.cpu.bp_block.replacement_policy.genblk1
|vpiProcess:
\_always: , line:40
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:40
|vpiCondition:
\_operation: , line:40
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:40
|vpiName:clk
|vpiFullName:work@taiga_wrapper.cpu.bp_block.replacement_policy.genblk1.clk
|vpiStmt:
\_begin: , line:40
|vpiFullName:work@taiga_wrapper.cpu.bp_block.replacement_policy.genblk1
|vpiStmt:
\_if_else: , line:41
|vpiCondition:
\_ref_obj: (rst), line:41
|vpiName:rst
|vpiFullName:work@taiga_wrapper.cpu.bp_block.replacement_policy.genblk1.rst
|vpiStmt:
\_assignment: , line:42
|vpiOpType:82
|vpiLhs:
\_ref_obj: (one_hot), line:42
|vpiName:one_hot
|vpiFullName:work@taiga_wrapper.cpu.bp_block.replacement_policy.genblk1.one_hot
|vpiRhs:
\_constant: , line:42
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiElseStmt:
\_if_stmt: , line:43
|vpiCondition:
\_ref_obj: (en), line:43
|vpiName:en
|vpiFullName:work@taiga_wrapper.cpu.bp_block.replacement_policy.genblk1.en
|vpiStmt:
\_assignment: , line:44
|vpiOpType:82
|vpiLhs:
\_ref_obj: (one_hot), line:44
|vpiName:one_hot
|vpiFullName:work@taiga_wrapper.cpu.bp_block.replacement_policy.genblk1.one_hot
|vpiRhs:
\_operation: , line:44
|vpiOpType:33
|vpiOperand:
\_part_select: , line:44, parent:one_hot
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (one_hot)
|vpiLeftRange:
\_operation: , line:44
|vpiOpType:11
|vpiOperand:
\_ref_obj: (C_WIDTH), line:44
|vpiName:C_WIDTH
|vpiOperand:
\_constant: , line:44
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiRightRange:
\_constant: , line:44
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiOperand:
\_bit_select: (one_hot), line:44
|vpiName:one_hot
|vpiIndex:
\_operation: , line:44
|vpiOpType:11
|vpiOperand:
\_ref_obj: (C_WIDTH), line:44
|vpiName:C_WIDTH
|vpiOperand:
\_constant: , line:44
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiNet:
\_logic_net: (clk), line:29, parent:replacement_policy
|vpiNet:
\_logic_net: (rst), line:30, parent:replacement_policy
|vpiNet:
\_logic_net: (en), line:31, parent:replacement_policy
|vpiNet:
\_logic_net: (one_hot), line:32, parent:replacement_policy
|vpiInstance:
\_module: work@branch_predictor (bp_block), file:third_party/cores/taiga/core/taiga.sv, line:161, parent:cpu
|vpiParameter:
\_parameter: (C_WIDTH), line:57
|vpiName:C_WIDTH
|INT:9
|vpiGenScopeArray:
\_gen_scope_array: (branch_tag_banks), line:60, parent:bp_block
|vpiName:branch_tag_banks
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_tag_banks
|vpiGenScope:
\_gen_scope: , parent:branch_tag_banks
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_tag_banks
|vpiGenScopeArray:
\_gen_scope_array: (branch_tag_banks[0]), line:61
|vpiName:branch_tag_banks[0]
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_tag_banks.branch_tag_banks[0]
|vpiGenScope:
\_gen_scope: , parent:branch_tag_banks[0]
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_tag_banks.branch_tag_banks[0]
|vpiModule:
\_module: work@branch_predictor_ram (tag_bank), file:third_party/cores/taiga/core/branch_predictor.sv, line:62
|vpiDefName:work@branch_predictor_ram
|vpiName:tag_bank
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_tag_banks.branch_tag_banks[0].tag_bank
|vpiPort:
\_port: (clk), line:32, parent:tag_bank
|vpiName:clk
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (clk), line:63
|vpiName:clk
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (clk), line:32, parent:tag_bank
|vpiName:clk
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_tag_banks.branch_tag_banks[0].tag_bank.clk
|vpiNetType:36
|vpiPort:
\_port: (write_addr), line:33, parent:tag_bank
|vpiName:write_addr
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (write_addr), line:63
|vpiName:write_addr
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (write_addr), line:33, parent:tag_bank
|vpiName:write_addr
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_tag_banks.branch_tag_banks[0].tag_bank.write_addr
|vpiNetType:36
|vpiRange:
\_range: , line:33
|vpiLeftRange:
\_constant: , line:33
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:33
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiPort:
\_port: (write_en), line:34, parent:tag_bank
|vpiName:write_en
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (write_en), line:63
|vpiName:write_en
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (write_en), line:34, parent:tag_bank
|vpiName:write_en
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_tag_banks.branch_tag_banks[0].tag_bank.write_en
|vpiNetType:36
|vpiPort:
\_port: (read_addr), line:35, parent:tag_bank
|vpiName:read_addr
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (read_addr), line:63
|vpiName:read_addr
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (read_addr), line:35, parent:tag_bank
|vpiName:read_addr
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_tag_banks.branch_tag_banks[0].tag_bank.read_addr
|vpiNetType:36
|vpiRange:
\_range: , line:35
|vpiLeftRange:
\_constant: , line:35
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:35
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiPort:
\_port: (read_en), line:36, parent:tag_bank
|vpiName:read_en
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (read_en), line:63
|vpiName:read_en
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (read_en), line:36, parent:tag_bank
|vpiName:read_en
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_tag_banks.branch_tag_banks[0].tag_bank.read_en
|vpiNetType:36
|vpiPort:
\_port: (write_data), line:37, parent:tag_bank
|vpiName:write_data
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (write_data), line:63
|vpiName:write_data
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (write_data), line:37, parent:tag_bank
|vpiName:write_data
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_tag_banks.branch_tag_banks[0].tag_bank.write_data
|vpiNetType:36
|vpiRange:
\_range: , line:37
|vpiLeftRange:
\_constant: , line:37
|vpiDecompile:-1
|INT:-1
|vpiRightRange:
\_constant: , line:37
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiPort:
\_port: (read_data), line:38, parent:tag_bank
|vpiName:read_data
|vpiDirection:2
|vpiHighConn:
\_ref_obj: (read_data), line:63
|vpiName:read_data
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (read_data), line:38, parent:tag_bank
|vpiName:read_data
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_tag_banks.branch_tag_banks[0].tag_bank.read_data
|vpiNetType:36
|vpiRange:
\_range: , line:38
|vpiLeftRange:
\_constant: , line:38
|vpiDecompile:-1
|INT:-1
|vpiRightRange:
\_constant: , line:38
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (clk), line:32, parent:tag_bank
|vpiNet:
\_logic_net: (write_addr), line:33, parent:tag_bank
|vpiNet:
\_logic_net: (write_en), line:34, parent:tag_bank
|vpiNet:
\_logic_net: (read_addr), line:35, parent:tag_bank
|vpiNet:
\_logic_net: (read_en), line:36, parent:tag_bank
|vpiNet:
\_logic_net: (write_data), line:37, parent:tag_bank
|vpiNet:
\_logic_net: (read_data), line:38, parent:tag_bank
|vpiArrayNet:
\_array_net: (branch_ram), line:40, parent:tag_bank
|vpiName:branch_ram
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_tag_banks.branch_tag_banks[0].tag_bank.branch_ram
|vpiSize:4
|vpiNet:
\_logic_net: , parent:branch_ram
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_tag_banks.branch_tag_banks[0].tag_bank.branch_ram
|vpiNetType:36
|vpiRange:
\_range: , line:40
|vpiLeftRange:
\_constant: , line:40
|vpiDecompile:-1
|INT:-1
|vpiRightRange:
\_constant: , line:40
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiRange:
\_range: , line:40
|vpiLeftRange:
\_constant: , line:40
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiRightRange:
\_constant: , line:40
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiParameter:
\_parameter: (ALU_UNIT_WB_ID), line:190
|vpiName:ALU_UNIT_WB_ID
|INT:32
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (BRANCH_PREDICTOR_WAYS), line:159
|vpiName:BRANCH_PREDICTOR_WAYS
|INT:9
|vpiParameter:
\_parameter: (BRANCH_TABLE_ENTRIES), line:160
|vpiName:BRANCH_TABLE_ENTRIES
|INT:4
|vpiParameter:
\_parameter: (BRANCH_UNIT_ID), line:195
|vpiName:BRANCH_UNIT_ID
|INT:8
|vpiParameter:
\_parameter: (BUS_ADDR_H), line:107
|vpiName:BUS_ADDR_H
|INT:1
|vpiParameter:
\_parameter: (BUS_ADDR_L), line:106
|vpiName:BUS_ADDR_L
|INT:0
|vpiParameter:
\_parameter: (BUS_BIT_CHECK), line:108
|vpiName:BUS_BIT_CHECK
|INT:1
|vpiParameter:
\_parameter: (BUS_TYPE), line:89
|vpiName:BUS_TYPE
|INT:5
|vpiParameter:
\_parameter: (COUNTER_W), line:42
|vpiName:COUNTER_W
|INT:33
|vpiParameter:
\_parameter: (CPU_ID), line:38
|vpiName:CPU_ID
|INT:0
|vpiParameter:
\_parameter: (C_DATA_WIDTH), line:62
|vpiName:C_DATA_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_DEPTH), line:62
|vpiName:C_DEPTH
|INT:4
|vpiParameter:
\_parameter: (C_M_AXI_ADDR_WIDTH), line:113
|vpiName:C_M_AXI_ADDR_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_DATA_WIDTH), line:114
|vpiName:C_M_AXI_DATA_WIDTH
|INT:1
|vpiParameter:
\_parameter: (DCACHE_LINES), line:133
|vpiName:DCACHE_LINES
|INT:-2146435073
|vpiParameter:
\_parameter: (DCACHE_LINE_ADDR_W), line:135
|vpiName:DCACHE_LINE_ADDR_W
|INT:1073741824
|vpiParameter:
\_parameter: (DCACHE_LINE_W), line:136
|vpiName:DCACHE_LINE_W
|INT:1342177279
|vpiParameter:
\_parameter: (DCACHE_SUB_LINE_ADDR_W), line:137
|vpiName:DCACHE_SUB_LINE_ADDR_W
|INT:4
|vpiParameter:
\_parameter: (DCACHE_TAG_W), line:138
|vpiName:DCACHE_TAG_W
|INT:1610612736
|vpiParameter:
\_parameter: (DCACHE_WAYS), line:134
|vpiName:DCACHE_WAYS
|INT:4
|vpiParameter:
\_parameter: (DIV_ALGORITHM), line:67
|vpiName:DIV_ALGORITHM
|INT:0
|vpiParameter:
\_parameter: (DIV_UNIT_WB_ID), line:192
|vpiName:DIV_UNIT_WB_ID
|INT:2
|vpiParameter:
\_parameter: (DTLB_DEPTH), line:152
|vpiName:DTLB_DEPTH
|INT:512
|vpiParameter:
\_parameter: (DTLB_WAYS), line:151
|vpiName:DTLB_WAYS
|INT:32
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (ENABLE_M_MODE), line:34
|vpiName:ENABLE_M_MODE
|INT:1
|vpiParameter:
\_parameter: (ENABLE_S_MODE), line:36
|vpiName:ENABLE_S_MODE
|INT:0
|vpiParameter:
\_parameter: (ENABLE_TRACE_INTERFACE), line:172
|vpiName:ENABLE_TRACE_INTERFACE
|INT:2
|vpiParameter:
\_parameter: (FETCH_BUFFER_DEPTH), line:168
|vpiName:FETCH_BUFFER_DEPTH
|INT:512
|vpiParameter:
\_parameter: (FPGA_VENDOR), line:27
|vpiName:FPGA_VENDOR
|STRING:"xilinx"
|vpiParameter:
\_parameter: (GC_UNIT_ID), line:196
|vpiName:GC_UNIT_ID
|INT:4
|vpiParameter:
\_parameter: (ICACHE_LINES), line:121
|vpiName:ICACHE_LINES
|INT:2
|vpiParameter:
\_parameter: (ICACHE_LINE_ADDR_W), line:123
|vpiName:ICACHE_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_LINE_W), line:124
|vpiName:ICACHE_LINE_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_SUB_LINE_ADDR_W), line:125
|vpiName:ICACHE_SUB_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_TAG_W), line:126
|vpiName:ICACHE_TAG_W
|INT:-2147483648
|vpiParameter:
\_parameter: (ICACHE_WAYS), line:122
|vpiName:ICACHE_WAYS
|INT:1
|vpiParameter:
\_parameter: (ITLB_DEPTH), line:146
|vpiName:ITLB_DEPTH
|INT:32
|vpiParameter:
\_parameter: (ITLB_WAYS), line:145
|vpiName:ITLB_WAYS
|INT:4
|vpiParameter:
\_parameter: (L1_CONNECTIONS), line:177
|vpiName:L1_CONNECTIONS
|INT:9
|vpiParameter:
\_parameter: (L1_DCACHE_ID), line:178
|vpiName:L1_DCACHE_ID
|INT:4
|vpiParameter:
\_parameter: (L1_DMMU_ID), line:179
|vpiName:L1_DMMU_ID
|INT:2
|vpiParameter:
\_parameter: (L1_ICACHE_ID), line:180
|vpiName:L1_ICACHE_ID
|INT:19
|vpiParameter:
\_parameter: (L1_IMMU_ID), line:181
|vpiName:L1_IMMU_ID
|INT:0
|vpiParameter:
\_parameter: (LS_UNIT_WB_ID), line:191
|vpiName:LS_UNIT_WB_ID
|INT:1
|vpiParameter:
\_parameter: (MAX_INFLIGHT_COUNT), line:167
|vpiName:MAX_INFLIGHT_COUNT
|INT:19
|vpiParameter:
\_parameter: (MEMORY_ADDR_H), line:103
|vpiName:MEMORY_ADDR_H
|INT:12
|vpiParameter:
\_parameter: (MEMORY_ADDR_L), line:102
|vpiName:MEMORY_ADDR_L
|INT:11
|vpiParameter:
\_parameter: (MEMORY_BIT_CHECK), line:104
|vpiName:MEMORY_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (MUL_UNIT_WB_ID), line:193
|vpiName:MUL_UNIT_WB_ID
|INT:512
|vpiParameter:
\_parameter: (NUM_UNITS), line:188
|vpiName:NUM_UNITS
|INT:2
|vpiParameter:
\_parameter: (NUM_WB_UNITS), line:186
|vpiName:NUM_WB_UNITS
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (RAS_DEPTH), line:161
|vpiName:RAS_DEPTH
|INT:2
|vpiParameter:
\_parameter: (RESET_VEC), line:39
|vpiName:RESET_VEC
|INT:-2147483648
|vpiParameter:
\_parameter: (SCRATCH_ADDR_H), line:99
|vpiName:SCRATCH_ADDR_H
|INT:9
|vpiParameter:
\_parameter: (SCRATCH_ADDR_L), line:98
|vpiName:SCRATCH_ADDR_L
|INT:8
|vpiParameter:
\_parameter: (SCRATCH_BIT_CHECK), line:100
|vpiName:SCRATCH_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (USE_AMO), line:70
|vpiName:USE_AMO
|INT:1
|vpiParameter:
\_parameter: (USE_BRANCH_PREDICTOR), line:158
|vpiName:USE_BRANCH_PREDICTOR
|INT:2
|vpiParameter:
\_parameter: (USE_BUS), line:88
|vpiName:USE_BUS
|INT:4
|vpiParameter:
\_parameter: (USE_DCACHE), line:92
|vpiName:USE_DCACHE
|INT:6
|vpiParameter:
\_parameter: (USE_DIV), line:49
|vpiName:USE_DIV
|INT:1
|vpiParameter:
\_parameter: (USE_DTAG_INVALIDATIONS), line:140
|vpiName:USE_DTAG_INVALIDATIONS
|INT:1879048191
|vpiParameter:
\_parameter: (USE_D_SCRATCH_MEM), line:79
|vpiName:USE_D_SCRATCH_MEM
|INT:3
|vpiParameter:
\_parameter: (USE_ICACHE), line:93
|vpiName:USE_ICACHE
|INT:7
|vpiParameter:
\_parameter: (USE_I_SCRATCH_MEM), line:78
|vpiName:USE_I_SCRATCH_MEM
|INT:2
|vpiParameter:
\_parameter: (USE_MUL), line:48
|vpiName:USE_MUL
|INT:1
|vpiParameter:
\_parameter: (WB_UNITS_WIDTH), line:187
|vpiName:WB_UNITS_WIDTH
|INT:32
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiParameter:
\_parameter: (ALU_UNIT_WB_ID), line:190
|vpiName:ALU_UNIT_WB_ID
|INT:32
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (BRANCH_PREDICTOR_WAYS), line:159
|vpiName:BRANCH_PREDICTOR_WAYS
|INT:9
|vpiParameter:
\_parameter: (BRANCH_TABLE_ENTRIES), line:160
|vpiName:BRANCH_TABLE_ENTRIES
|INT:4
|vpiParameter:
\_parameter: (BRANCH_UNIT_ID), line:195
|vpiName:BRANCH_UNIT_ID
|INT:8
|vpiParameter:
\_parameter: (BUS_ADDR_H), line:107
|vpiName:BUS_ADDR_H
|INT:1
|vpiParameter:
\_parameter: (BUS_ADDR_L), line:106
|vpiName:BUS_ADDR_L
|INT:0
|vpiParameter:
\_parameter: (BUS_BIT_CHECK), line:108
|vpiName:BUS_BIT_CHECK
|INT:1
|vpiParameter:
\_parameter: (BUS_TYPE), line:89
|vpiName:BUS_TYPE
|INT:5
|vpiParameter:
\_parameter: (COUNTER_W), line:42
|vpiName:COUNTER_W
|INT:33
|vpiParameter:
\_parameter: (CPU_ID), line:38
|vpiName:CPU_ID
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_ADDR_WIDTH), line:113
|vpiName:C_M_AXI_ADDR_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_DATA_WIDTH), line:114
|vpiName:C_M_AXI_DATA_WIDTH
|INT:1
|vpiParameter:
\_parameter: (DCACHE_LINES), line:133
|vpiName:DCACHE_LINES
|INT:-2146435073
|vpiParameter:
\_parameter: (DCACHE_LINE_ADDR_W), line:135
|vpiName:DCACHE_LINE_ADDR_W
|INT:1073741824
|vpiParameter:
\_parameter: (DCACHE_LINE_W), line:136
|vpiName:DCACHE_LINE_W
|INT:1342177279
|vpiParameter:
\_parameter: (DCACHE_SUB_LINE_ADDR_W), line:137
|vpiName:DCACHE_SUB_LINE_ADDR_W
|INT:4
|vpiParameter:
\_parameter: (DCACHE_TAG_W), line:138
|vpiName:DCACHE_TAG_W
|INT:1610612736
|vpiParameter:
\_parameter: (DCACHE_WAYS), line:134
|vpiName:DCACHE_WAYS
|INT:4
|vpiParameter:
\_parameter: (DIV_ALGORITHM), line:67
|vpiName:DIV_ALGORITHM
|INT:0
|vpiParameter:
\_parameter: (DIV_UNIT_WB_ID), line:192
|vpiName:DIV_UNIT_WB_ID
|INT:2
|vpiParameter:
\_parameter: (DTLB_DEPTH), line:152
|vpiName:DTLB_DEPTH
|INT:512
|vpiParameter:
\_parameter: (DTLB_WAYS), line:151
|vpiName:DTLB_WAYS
|INT:32
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (ENABLE_M_MODE), line:34
|vpiName:ENABLE_M_MODE
|INT:1
|vpiParameter:
\_parameter: (ENABLE_S_MODE), line:36
|vpiName:ENABLE_S_MODE
|INT:0
|vpiParameter:
\_parameter: (ENABLE_TRACE_INTERFACE), line:172
|vpiName:ENABLE_TRACE_INTERFACE
|INT:2
|vpiParameter:
\_parameter: (FETCH_BUFFER_DEPTH), line:168
|vpiName:FETCH_BUFFER_DEPTH
|INT:512
|vpiParameter:
\_parameter: (FPGA_VENDOR), line:27
|vpiName:FPGA_VENDOR
|STRING:"xilinx"
|vpiParameter:
\_parameter: (GC_UNIT_ID), line:196
|vpiName:GC_UNIT_ID
|INT:4
|vpiParameter:
\_parameter: (ICACHE_LINES), line:121
|vpiName:ICACHE_LINES
|INT:2
|vpiParameter:
\_parameter: (ICACHE_LINE_ADDR_W), line:123
|vpiName:ICACHE_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_LINE_W), line:124
|vpiName:ICACHE_LINE_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_SUB_LINE_ADDR_W), line:125
|vpiName:ICACHE_SUB_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_TAG_W), line:126
|vpiName:ICACHE_TAG_W
|INT:-2147483648
|vpiParameter:
\_parameter: (ICACHE_WAYS), line:122
|vpiName:ICACHE_WAYS
|INT:1
|vpiParameter:
\_parameter: (ITLB_DEPTH), line:146
|vpiName:ITLB_DEPTH
|INT:32
|vpiParameter:
\_parameter: (ITLB_WAYS), line:145
|vpiName:ITLB_WAYS
|INT:4
|vpiParameter:
\_parameter: (L1_CONNECTIONS), line:177
|vpiName:L1_CONNECTIONS
|INT:9
|vpiParameter:
\_parameter: (L1_DCACHE_ID), line:178
|vpiName:L1_DCACHE_ID
|INT:4
|vpiParameter:
\_parameter: (L1_DMMU_ID), line:179
|vpiName:L1_DMMU_ID
|INT:2
|vpiParameter:
\_parameter: (L1_ICACHE_ID), line:180
|vpiName:L1_ICACHE_ID
|INT:19
|vpiParameter:
\_parameter: (L1_IMMU_ID), line:181
|vpiName:L1_IMMU_ID
|INT:0
|vpiParameter:
\_parameter: (LS_UNIT_WB_ID), line:191
|vpiName:LS_UNIT_WB_ID
|INT:1
|vpiParameter:
\_parameter: (MAX_INFLIGHT_COUNT), line:167
|vpiName:MAX_INFLIGHT_COUNT
|INT:19
|vpiParameter:
\_parameter: (MEMORY_ADDR_H), line:103
|vpiName:MEMORY_ADDR_H
|INT:12
|vpiParameter:
\_parameter: (MEMORY_ADDR_L), line:102
|vpiName:MEMORY_ADDR_L
|INT:11
|vpiParameter:
\_parameter: (MEMORY_BIT_CHECK), line:104
|vpiName:MEMORY_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (MUL_UNIT_WB_ID), line:193
|vpiName:MUL_UNIT_WB_ID
|INT:512
|vpiParameter:
\_parameter: (NUM_UNITS), line:188
|vpiName:NUM_UNITS
|INT:2
|vpiParameter:
\_parameter: (NUM_WB_UNITS), line:186
|vpiName:NUM_WB_UNITS
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (RAS_DEPTH), line:161
|vpiName:RAS_DEPTH
|INT:2
|vpiParameter:
\_parameter: (RESET_VEC), line:39
|vpiName:RESET_VEC
|INT:-2147483648
|vpiParameter:
\_parameter: (SCRATCH_ADDR_H), line:99
|vpiName:SCRATCH_ADDR_H
|INT:9
|vpiParameter:
\_parameter: (SCRATCH_ADDR_L), line:98
|vpiName:SCRATCH_ADDR_L
|INT:8
|vpiParameter:
\_parameter: (SCRATCH_BIT_CHECK), line:100
|vpiName:SCRATCH_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (USE_AMO), line:70
|vpiName:USE_AMO
|INT:1
|vpiParameter:
\_parameter: (USE_BRANCH_PREDICTOR), line:158
|vpiName:USE_BRANCH_PREDICTOR
|INT:2
|vpiParameter:
\_parameter: (USE_BUS), line:88
|vpiName:USE_BUS
|INT:4
|vpiParameter:
\_parameter: (USE_DCACHE), line:92
|vpiName:USE_DCACHE
|INT:6
|vpiParameter:
\_parameter: (USE_DIV), line:49
|vpiName:USE_DIV
|INT:1
|vpiParameter:
\_parameter: (USE_DTAG_INVALIDATIONS), line:140
|vpiName:USE_DTAG_INVALIDATIONS
|INT:1879048191
|vpiParameter:
\_parameter: (USE_D_SCRATCH_MEM), line:79
|vpiName:USE_D_SCRATCH_MEM
|INT:3
|vpiParameter:
\_parameter: (USE_ICACHE), line:93
|vpiName:USE_ICACHE
|INT:7
|vpiParameter:
\_parameter: (USE_I_SCRATCH_MEM), line:78
|vpiName:USE_I_SCRATCH_MEM
|INT:2
|vpiParameter:
\_parameter: (USE_MUL), line:48
|vpiName:USE_MUL
|INT:1
|vpiParameter:
\_parameter: (WB_UNITS_WIDTH), line:187
|vpiName:WB_UNITS_WIDTH
|INT:32
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiParameter:
\_parameter: (i), line:61
|vpiName:i
|INT:0
|vpiGenScopeArray:
\_gen_scope_array: (branch_tag_banks[1]), line:61
|vpiName:branch_tag_banks[1]
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_tag_banks.branch_tag_banks[1]
|vpiGenScope:
\_gen_scope: , parent:branch_tag_banks[1]
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_tag_banks.branch_tag_banks[1]
|vpiModule:
\_module: work@branch_predictor_ram (tag_bank), file:third_party/cores/taiga/core/branch_predictor.sv, line:62
|vpiDefName:work@branch_predictor_ram
|vpiName:tag_bank
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_tag_banks.branch_tag_banks[1].tag_bank
|vpiPort:
\_port: (clk), line:32, parent:tag_bank
|vpiName:clk
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (clk), line:63
|vpiName:clk
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (clk), line:32, parent:tag_bank
|vpiName:clk
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_tag_banks.branch_tag_banks[1].tag_bank.clk
|vpiNetType:36
|vpiPort:
\_port: (write_addr), line:33, parent:tag_bank
|vpiName:write_addr
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (write_addr), line:63
|vpiName:write_addr
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (write_addr), line:33, parent:tag_bank
|vpiName:write_addr
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_tag_banks.branch_tag_banks[1].tag_bank.write_addr
|vpiNetType:36
|vpiRange:
\_range: , line:33
|vpiLeftRange:
\_constant: , line:33
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:33
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiPort:
\_port: (write_en), line:34, parent:tag_bank
|vpiName:write_en
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (write_en), line:63
|vpiName:write_en
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (write_en), line:34, parent:tag_bank
|vpiName:write_en
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_tag_banks.branch_tag_banks[1].tag_bank.write_en
|vpiNetType:36
|vpiPort:
\_port: (read_addr), line:35, parent:tag_bank
|vpiName:read_addr
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (read_addr), line:63
|vpiName:read_addr
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (read_addr), line:35, parent:tag_bank
|vpiName:read_addr
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_tag_banks.branch_tag_banks[1].tag_bank.read_addr
|vpiNetType:36
|vpiRange:
\_range: , line:35
|vpiLeftRange:
\_constant: , line:35
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:35
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiPort:
\_port: (read_en), line:36, parent:tag_bank
|vpiName:read_en
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (read_en), line:63
|vpiName:read_en
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (read_en), line:36, parent:tag_bank
|vpiName:read_en
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_tag_banks.branch_tag_banks[1].tag_bank.read_en
|vpiNetType:36
|vpiPort:
\_port: (write_data), line:37, parent:tag_bank
|vpiName:write_data
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (write_data), line:63
|vpiName:write_data
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (write_data), line:37, parent:tag_bank
|vpiName:write_data
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_tag_banks.branch_tag_banks[1].tag_bank.write_data
|vpiNetType:36
|vpiRange:
\_range: , line:37
|vpiLeftRange:
\_constant: , line:37
|vpiDecompile:-1
|INT:-1
|vpiRightRange:
\_constant: , line:37
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiPort:
\_port: (read_data), line:38, parent:tag_bank
|vpiName:read_data
|vpiDirection:2
|vpiHighConn:
\_ref_obj: (read_data), line:63
|vpiName:read_data
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (read_data), line:38, parent:tag_bank
|vpiName:read_data
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_tag_banks.branch_tag_banks[1].tag_bank.read_data
|vpiNetType:36
|vpiRange:
\_range: , line:38
|vpiLeftRange:
\_constant: , line:38
|vpiDecompile:-1
|INT:-1
|vpiRightRange:
\_constant: , line:38
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (clk), line:32, parent:tag_bank
|vpiNet:
\_logic_net: (write_addr), line:33, parent:tag_bank
|vpiNet:
\_logic_net: (write_en), line:34, parent:tag_bank
|vpiNet:
\_logic_net: (read_addr), line:35, parent:tag_bank
|vpiNet:
\_logic_net: (read_en), line:36, parent:tag_bank
|vpiNet:
\_logic_net: (write_data), line:37, parent:tag_bank
|vpiNet:
\_logic_net: (read_data), line:38, parent:tag_bank
|vpiArrayNet:
\_array_net: (branch_ram), line:40, parent:tag_bank
|vpiName:branch_ram
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_tag_banks.branch_tag_banks[1].tag_bank.branch_ram
|vpiSize:4
|vpiNet:
\_logic_net: , parent:branch_ram
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_tag_banks.branch_tag_banks[1].tag_bank.branch_ram
|vpiNetType:36
|vpiRange:
\_range: , line:40
|vpiLeftRange:
\_constant: , line:40
|vpiDecompile:-1
|INT:-1
|vpiRightRange:
\_constant: , line:40
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiRange:
\_range: , line:40
|vpiLeftRange:
\_constant: , line:40
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiRightRange:
\_constant: , line:40
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiParameter:
\_parameter: (ALU_UNIT_WB_ID), line:190
|vpiName:ALU_UNIT_WB_ID
|INT:32
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (BRANCH_PREDICTOR_WAYS), line:159
|vpiName:BRANCH_PREDICTOR_WAYS
|INT:9
|vpiParameter:
\_parameter: (BRANCH_TABLE_ENTRIES), line:160
|vpiName:BRANCH_TABLE_ENTRIES
|INT:4
|vpiParameter:
\_parameter: (BRANCH_UNIT_ID), line:195
|vpiName:BRANCH_UNIT_ID
|INT:8
|vpiParameter:
\_parameter: (BUS_ADDR_H), line:107
|vpiName:BUS_ADDR_H
|INT:1
|vpiParameter:
\_parameter: (BUS_ADDR_L), line:106
|vpiName:BUS_ADDR_L
|INT:0
|vpiParameter:
\_parameter: (BUS_BIT_CHECK), line:108
|vpiName:BUS_BIT_CHECK
|INT:1
|vpiParameter:
\_parameter: (BUS_TYPE), line:89
|vpiName:BUS_TYPE
|INT:5
|vpiParameter:
\_parameter: (COUNTER_W), line:42
|vpiName:COUNTER_W
|INT:33
|vpiParameter:
\_parameter: (CPU_ID), line:38
|vpiName:CPU_ID
|INT:0
|vpiParameter:
\_parameter: (C_DATA_WIDTH), line:62
|vpiName:C_DATA_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_DEPTH), line:62
|vpiName:C_DEPTH
|INT:4
|vpiParameter:
\_parameter: (C_M_AXI_ADDR_WIDTH), line:113
|vpiName:C_M_AXI_ADDR_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_DATA_WIDTH), line:114
|vpiName:C_M_AXI_DATA_WIDTH
|INT:1
|vpiParameter:
\_parameter: (DCACHE_LINES), line:133
|vpiName:DCACHE_LINES
|INT:-2146435073
|vpiParameter:
\_parameter: (DCACHE_LINE_ADDR_W), line:135
|vpiName:DCACHE_LINE_ADDR_W
|INT:1073741824
|vpiParameter:
\_parameter: (DCACHE_LINE_W), line:136
|vpiName:DCACHE_LINE_W
|INT:1342177279
|vpiParameter:
\_parameter: (DCACHE_SUB_LINE_ADDR_W), line:137
|vpiName:DCACHE_SUB_LINE_ADDR_W
|INT:4
|vpiParameter:
\_parameter: (DCACHE_TAG_W), line:138
|vpiName:DCACHE_TAG_W
|INT:1610612736
|vpiParameter:
\_parameter: (DCACHE_WAYS), line:134
|vpiName:DCACHE_WAYS
|INT:4
|vpiParameter:
\_parameter: (DIV_ALGORITHM), line:67
|vpiName:DIV_ALGORITHM
|INT:0
|vpiParameter:
\_parameter: (DIV_UNIT_WB_ID), line:192
|vpiName:DIV_UNIT_WB_ID
|INT:2
|vpiParameter:
\_parameter: (DTLB_DEPTH), line:152
|vpiName:DTLB_DEPTH
|INT:512
|vpiParameter:
\_parameter: (DTLB_WAYS), line:151
|vpiName:DTLB_WAYS
|INT:32
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (ENABLE_M_MODE), line:34
|vpiName:ENABLE_M_MODE
|INT:1
|vpiParameter:
\_parameter: (ENABLE_S_MODE), line:36
|vpiName:ENABLE_S_MODE
|INT:0
|vpiParameter:
\_parameter: (ENABLE_TRACE_INTERFACE), line:172
|vpiName:ENABLE_TRACE_INTERFACE
|INT:2
|vpiParameter:
\_parameter: (FETCH_BUFFER_DEPTH), line:168
|vpiName:FETCH_BUFFER_DEPTH
|INT:512
|vpiParameter:
\_parameter: (FPGA_VENDOR), line:27
|vpiName:FPGA_VENDOR
|STRING:"xilinx"
|vpiParameter:
\_parameter: (GC_UNIT_ID), line:196
|vpiName:GC_UNIT_ID
|INT:4
|vpiParameter:
\_parameter: (ICACHE_LINES), line:121
|vpiName:ICACHE_LINES
|INT:2
|vpiParameter:
\_parameter: (ICACHE_LINE_ADDR_W), line:123
|vpiName:ICACHE_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_LINE_W), line:124
|vpiName:ICACHE_LINE_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_SUB_LINE_ADDR_W), line:125
|vpiName:ICACHE_SUB_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_TAG_W), line:126
|vpiName:ICACHE_TAG_W
|INT:-2147483648
|vpiParameter:
\_parameter: (ICACHE_WAYS), line:122
|vpiName:ICACHE_WAYS
|INT:1
|vpiParameter:
\_parameter: (ITLB_DEPTH), line:146
|vpiName:ITLB_DEPTH
|INT:32
|vpiParameter:
\_parameter: (ITLB_WAYS), line:145
|vpiName:ITLB_WAYS
|INT:4
|vpiParameter:
\_parameter: (L1_CONNECTIONS), line:177
|vpiName:L1_CONNECTIONS
|INT:9
|vpiParameter:
\_parameter: (L1_DCACHE_ID), line:178
|vpiName:L1_DCACHE_ID
|INT:4
|vpiParameter:
\_parameter: (L1_DMMU_ID), line:179
|vpiName:L1_DMMU_ID
|INT:2
|vpiParameter:
\_parameter: (L1_ICACHE_ID), line:180
|vpiName:L1_ICACHE_ID
|INT:19
|vpiParameter:
\_parameter: (L1_IMMU_ID), line:181
|vpiName:L1_IMMU_ID
|INT:0
|vpiParameter:
\_parameter: (LS_UNIT_WB_ID), line:191
|vpiName:LS_UNIT_WB_ID
|INT:1
|vpiParameter:
\_parameter: (MAX_INFLIGHT_COUNT), line:167
|vpiName:MAX_INFLIGHT_COUNT
|INT:19
|vpiParameter:
\_parameter: (MEMORY_ADDR_H), line:103
|vpiName:MEMORY_ADDR_H
|INT:12
|vpiParameter:
\_parameter: (MEMORY_ADDR_L), line:102
|vpiName:MEMORY_ADDR_L
|INT:11
|vpiParameter:
\_parameter: (MEMORY_BIT_CHECK), line:104
|vpiName:MEMORY_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (MUL_UNIT_WB_ID), line:193
|vpiName:MUL_UNIT_WB_ID
|INT:512
|vpiParameter:
\_parameter: (NUM_UNITS), line:188
|vpiName:NUM_UNITS
|INT:2
|vpiParameter:
\_parameter: (NUM_WB_UNITS), line:186
|vpiName:NUM_WB_UNITS
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (RAS_DEPTH), line:161
|vpiName:RAS_DEPTH
|INT:2
|vpiParameter:
\_parameter: (RESET_VEC), line:39
|vpiName:RESET_VEC
|INT:-2147483648
|vpiParameter:
\_parameter: (SCRATCH_ADDR_H), line:99
|vpiName:SCRATCH_ADDR_H
|INT:9
|vpiParameter:
\_parameter: (SCRATCH_ADDR_L), line:98
|vpiName:SCRATCH_ADDR_L
|INT:8
|vpiParameter:
\_parameter: (SCRATCH_BIT_CHECK), line:100
|vpiName:SCRATCH_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (USE_AMO), line:70
|vpiName:USE_AMO
|INT:1
|vpiParameter:
\_parameter: (USE_BRANCH_PREDICTOR), line:158
|vpiName:USE_BRANCH_PREDICTOR
|INT:2
|vpiParameter:
\_parameter: (USE_BUS), line:88
|vpiName:USE_BUS
|INT:4
|vpiParameter:
\_parameter: (USE_DCACHE), line:92
|vpiName:USE_DCACHE
|INT:6
|vpiParameter:
\_parameter: (USE_DIV), line:49
|vpiName:USE_DIV
|INT:1
|vpiParameter:
\_parameter: (USE_DTAG_INVALIDATIONS), line:140
|vpiName:USE_DTAG_INVALIDATIONS
|INT:1879048191
|vpiParameter:
\_parameter: (USE_D_SCRATCH_MEM), line:79
|vpiName:USE_D_SCRATCH_MEM
|INT:3
|vpiParameter:
\_parameter: (USE_ICACHE), line:93
|vpiName:USE_ICACHE
|INT:7
|vpiParameter:
\_parameter: (USE_I_SCRATCH_MEM), line:78
|vpiName:USE_I_SCRATCH_MEM
|INT:2
|vpiParameter:
\_parameter: (USE_MUL), line:48
|vpiName:USE_MUL
|INT:1
|vpiParameter:
\_parameter: (WB_UNITS_WIDTH), line:187
|vpiName:WB_UNITS_WIDTH
|INT:32
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiParameter:
\_parameter: (ALU_UNIT_WB_ID), line:190
|vpiName:ALU_UNIT_WB_ID
|INT:32
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (BRANCH_PREDICTOR_WAYS), line:159
|vpiName:BRANCH_PREDICTOR_WAYS
|INT:9
|vpiParameter:
\_parameter: (BRANCH_TABLE_ENTRIES), line:160
|vpiName:BRANCH_TABLE_ENTRIES
|INT:4
|vpiParameter:
\_parameter: (BRANCH_UNIT_ID), line:195
|vpiName:BRANCH_UNIT_ID
|INT:8
|vpiParameter:
\_parameter: (BUS_ADDR_H), line:107
|vpiName:BUS_ADDR_H
|INT:1
|vpiParameter:
\_parameter: (BUS_ADDR_L), line:106
|vpiName:BUS_ADDR_L
|INT:0
|vpiParameter:
\_parameter: (BUS_BIT_CHECK), line:108
|vpiName:BUS_BIT_CHECK
|INT:1
|vpiParameter:
\_parameter: (BUS_TYPE), line:89
|vpiName:BUS_TYPE
|INT:5
|vpiParameter:
\_parameter: (COUNTER_W), line:42
|vpiName:COUNTER_W
|INT:33
|vpiParameter:
\_parameter: (CPU_ID), line:38
|vpiName:CPU_ID
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_ADDR_WIDTH), line:113
|vpiName:C_M_AXI_ADDR_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_DATA_WIDTH), line:114
|vpiName:C_M_AXI_DATA_WIDTH
|INT:1
|vpiParameter:
\_parameter: (DCACHE_LINES), line:133
|vpiName:DCACHE_LINES
|INT:-2146435073
|vpiParameter:
\_parameter: (DCACHE_LINE_ADDR_W), line:135
|vpiName:DCACHE_LINE_ADDR_W
|INT:1073741824
|vpiParameter:
\_parameter: (DCACHE_LINE_W), line:136
|vpiName:DCACHE_LINE_W
|INT:1342177279
|vpiParameter:
\_parameter: (DCACHE_SUB_LINE_ADDR_W), line:137
|vpiName:DCACHE_SUB_LINE_ADDR_W
|INT:4
|vpiParameter:
\_parameter: (DCACHE_TAG_W), line:138
|vpiName:DCACHE_TAG_W
|INT:1610612736
|vpiParameter:
\_parameter: (DCACHE_WAYS), line:134
|vpiName:DCACHE_WAYS
|INT:4
|vpiParameter:
\_parameter: (DIV_ALGORITHM), line:67
|vpiName:DIV_ALGORITHM
|INT:0
|vpiParameter:
\_parameter: (DIV_UNIT_WB_ID), line:192
|vpiName:DIV_UNIT_WB_ID
|INT:2
|vpiParameter:
\_parameter: (DTLB_DEPTH), line:152
|vpiName:DTLB_DEPTH
|INT:512
|vpiParameter:
\_parameter: (DTLB_WAYS), line:151
|vpiName:DTLB_WAYS
|INT:32
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (ENABLE_M_MODE), line:34
|vpiName:ENABLE_M_MODE
|INT:1
|vpiParameter:
\_parameter: (ENABLE_S_MODE), line:36
|vpiName:ENABLE_S_MODE
|INT:0
|vpiParameter:
\_parameter: (ENABLE_TRACE_INTERFACE), line:172
|vpiName:ENABLE_TRACE_INTERFACE
|INT:2
|vpiParameter:
\_parameter: (FETCH_BUFFER_DEPTH), line:168
|vpiName:FETCH_BUFFER_DEPTH
|INT:512
|vpiParameter:
\_parameter: (FPGA_VENDOR), line:27
|vpiName:FPGA_VENDOR
|STRING:"xilinx"
|vpiParameter:
\_parameter: (GC_UNIT_ID), line:196
|vpiName:GC_UNIT_ID
|INT:4
|vpiParameter:
\_parameter: (ICACHE_LINES), line:121
|vpiName:ICACHE_LINES
|INT:2
|vpiParameter:
\_parameter: (ICACHE_LINE_ADDR_W), line:123
|vpiName:ICACHE_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_LINE_W), line:124
|vpiName:ICACHE_LINE_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_SUB_LINE_ADDR_W), line:125
|vpiName:ICACHE_SUB_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_TAG_W), line:126
|vpiName:ICACHE_TAG_W
|INT:-2147483648
|vpiParameter:
\_parameter: (ICACHE_WAYS), line:122
|vpiName:ICACHE_WAYS
|INT:1
|vpiParameter:
\_parameter: (ITLB_DEPTH), line:146
|vpiName:ITLB_DEPTH
|INT:32
|vpiParameter:
\_parameter: (ITLB_WAYS), line:145
|vpiName:ITLB_WAYS
|INT:4
|vpiParameter:
\_parameter: (L1_CONNECTIONS), line:177
|vpiName:L1_CONNECTIONS
|INT:9
|vpiParameter:
\_parameter: (L1_DCACHE_ID), line:178
|vpiName:L1_DCACHE_ID
|INT:4
|vpiParameter:
\_parameter: (L1_DMMU_ID), line:179
|vpiName:L1_DMMU_ID
|INT:2
|vpiParameter:
\_parameter: (L1_ICACHE_ID), line:180
|vpiName:L1_ICACHE_ID
|INT:19
|vpiParameter:
\_parameter: (L1_IMMU_ID), line:181
|vpiName:L1_IMMU_ID
|INT:0
|vpiParameter:
\_parameter: (LS_UNIT_WB_ID), line:191
|vpiName:LS_UNIT_WB_ID
|INT:1
|vpiParameter:
\_parameter: (MAX_INFLIGHT_COUNT), line:167
|vpiName:MAX_INFLIGHT_COUNT
|INT:19
|vpiParameter:
\_parameter: (MEMORY_ADDR_H), line:103
|vpiName:MEMORY_ADDR_H
|INT:12
|vpiParameter:
\_parameter: (MEMORY_ADDR_L), line:102
|vpiName:MEMORY_ADDR_L
|INT:11
|vpiParameter:
\_parameter: (MEMORY_BIT_CHECK), line:104
|vpiName:MEMORY_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (MUL_UNIT_WB_ID), line:193
|vpiName:MUL_UNIT_WB_ID
|INT:512
|vpiParameter:
\_parameter: (NUM_UNITS), line:188
|vpiName:NUM_UNITS
|INT:2
|vpiParameter:
\_parameter: (NUM_WB_UNITS), line:186
|vpiName:NUM_WB_UNITS
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (RAS_DEPTH), line:161
|vpiName:RAS_DEPTH
|INT:2
|vpiParameter:
\_parameter: (RESET_VEC), line:39
|vpiName:RESET_VEC
|INT:-2147483648
|vpiParameter:
\_parameter: (SCRATCH_ADDR_H), line:99
|vpiName:SCRATCH_ADDR_H
|INT:9
|vpiParameter:
\_parameter: (SCRATCH_ADDR_L), line:98
|vpiName:SCRATCH_ADDR_L
|INT:8
|vpiParameter:
\_parameter: (SCRATCH_BIT_CHECK), line:100
|vpiName:SCRATCH_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (USE_AMO), line:70
|vpiName:USE_AMO
|INT:1
|vpiParameter:
\_parameter: (USE_BRANCH_PREDICTOR), line:158
|vpiName:USE_BRANCH_PREDICTOR
|INT:2
|vpiParameter:
\_parameter: (USE_BUS), line:88
|vpiName:USE_BUS
|INT:4
|vpiParameter:
\_parameter: (USE_DCACHE), line:92
|vpiName:USE_DCACHE
|INT:6
|vpiParameter:
\_parameter: (USE_DIV), line:49
|vpiName:USE_DIV
|INT:1
|vpiParameter:
\_parameter: (USE_DTAG_INVALIDATIONS), line:140
|vpiName:USE_DTAG_INVALIDATIONS
|INT:1879048191
|vpiParameter:
\_parameter: (USE_D_SCRATCH_MEM), line:79
|vpiName:USE_D_SCRATCH_MEM
|INT:3
|vpiParameter:
\_parameter: (USE_ICACHE), line:93
|vpiName:USE_ICACHE
|INT:7
|vpiParameter:
\_parameter: (USE_I_SCRATCH_MEM), line:78
|vpiName:USE_I_SCRATCH_MEM
|INT:2
|vpiParameter:
\_parameter: (USE_MUL), line:48
|vpiName:USE_MUL
|INT:1
|vpiParameter:
\_parameter: (WB_UNITS_WIDTH), line:187
|vpiName:WB_UNITS_WIDTH
|INT:32
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiParameter:
\_parameter: (i), line:61
|vpiName:i
|INT:1
|vpiGenScopeArray:
\_gen_scope_array: (branch_tag_banks[2]), line:61
|vpiName:branch_tag_banks[2]
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_tag_banks.branch_tag_banks[2]
|vpiGenScope:
\_gen_scope: , parent:branch_tag_banks[2]
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_tag_banks.branch_tag_banks[2]
|vpiModule:
\_module: work@branch_predictor_ram (tag_bank), file:third_party/cores/taiga/core/branch_predictor.sv, line:62
|vpiDefName:work@branch_predictor_ram
|vpiName:tag_bank
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_tag_banks.branch_tag_banks[2].tag_bank
|vpiPort:
\_port: (clk), line:32, parent:tag_bank
|vpiName:clk
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (clk), line:63
|vpiName:clk
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (clk), line:32, parent:tag_bank
|vpiName:clk
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_tag_banks.branch_tag_banks[2].tag_bank.clk
|vpiNetType:36
|vpiPort:
\_port: (write_addr), line:33, parent:tag_bank
|vpiName:write_addr
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (write_addr), line:63
|vpiName:write_addr
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (write_addr), line:33, parent:tag_bank
|vpiName:write_addr
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_tag_banks.branch_tag_banks[2].tag_bank.write_addr
|vpiNetType:36
|vpiRange:
\_range: , line:33
|vpiLeftRange:
\_constant: , line:33
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:33
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiPort:
\_port: (write_en), line:34, parent:tag_bank
|vpiName:write_en
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (write_en), line:63
|vpiName:write_en
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (write_en), line:34, parent:tag_bank
|vpiName:write_en
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_tag_banks.branch_tag_banks[2].tag_bank.write_en
|vpiNetType:36
|vpiPort:
\_port: (read_addr), line:35, parent:tag_bank
|vpiName:read_addr
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (read_addr), line:63
|vpiName:read_addr
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (read_addr), line:35, parent:tag_bank
|vpiName:read_addr
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_tag_banks.branch_tag_banks[2].tag_bank.read_addr
|vpiNetType:36
|vpiRange:
\_range: , line:35
|vpiLeftRange:
\_constant: , line:35
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:35
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiPort:
\_port: (read_en), line:36, parent:tag_bank
|vpiName:read_en
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (read_en), line:63
|vpiName:read_en
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (read_en), line:36, parent:tag_bank
|vpiName:read_en
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_tag_banks.branch_tag_banks[2].tag_bank.read_en
|vpiNetType:36
|vpiPort:
\_port: (write_data), line:37, parent:tag_bank
|vpiName:write_data
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (write_data), line:63
|vpiName:write_data
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (write_data), line:37, parent:tag_bank
|vpiName:write_data
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_tag_banks.branch_tag_banks[2].tag_bank.write_data
|vpiNetType:36
|vpiRange:
\_range: , line:37
|vpiLeftRange:
\_constant: , line:37
|vpiDecompile:-1
|INT:-1
|vpiRightRange:
\_constant: , line:37
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiPort:
\_port: (read_data), line:38, parent:tag_bank
|vpiName:read_data
|vpiDirection:2
|vpiHighConn:
\_ref_obj: (read_data), line:63
|vpiName:read_data
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (read_data), line:38, parent:tag_bank
|vpiName:read_data
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_tag_banks.branch_tag_banks[2].tag_bank.read_data
|vpiNetType:36
|vpiRange:
\_range: , line:38
|vpiLeftRange:
\_constant: , line:38
|vpiDecompile:-1
|INT:-1
|vpiRightRange:
\_constant: , line:38
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (clk), line:32, parent:tag_bank
|vpiNet:
\_logic_net: (write_addr), line:33, parent:tag_bank
|vpiNet:
\_logic_net: (write_en), line:34, parent:tag_bank
|vpiNet:
\_logic_net: (read_addr), line:35, parent:tag_bank
|vpiNet:
\_logic_net: (read_en), line:36, parent:tag_bank
|vpiNet:
\_logic_net: (write_data), line:37, parent:tag_bank
|vpiNet:
\_logic_net: (read_data), line:38, parent:tag_bank
|vpiArrayNet:
\_array_net: (branch_ram), line:40, parent:tag_bank
|vpiName:branch_ram
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_tag_banks.branch_tag_banks[2].tag_bank.branch_ram
|vpiSize:4
|vpiNet:
\_logic_net: , parent:branch_ram
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_tag_banks.branch_tag_banks[2].tag_bank.branch_ram
|vpiNetType:36
|vpiRange:
\_range: , line:40
|vpiLeftRange:
\_constant: , line:40
|vpiDecompile:-1
|INT:-1
|vpiRightRange:
\_constant: , line:40
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiRange:
\_range: , line:40
|vpiLeftRange:
\_constant: , line:40
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiRightRange:
\_constant: , line:40
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiParameter:
\_parameter: (ALU_UNIT_WB_ID), line:190
|vpiName:ALU_UNIT_WB_ID
|INT:32
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (BRANCH_PREDICTOR_WAYS), line:159
|vpiName:BRANCH_PREDICTOR_WAYS
|INT:9
|vpiParameter:
\_parameter: (BRANCH_TABLE_ENTRIES), line:160
|vpiName:BRANCH_TABLE_ENTRIES
|INT:4
|vpiParameter:
\_parameter: (BRANCH_UNIT_ID), line:195
|vpiName:BRANCH_UNIT_ID
|INT:8
|vpiParameter:
\_parameter: (BUS_ADDR_H), line:107
|vpiName:BUS_ADDR_H
|INT:1
|vpiParameter:
\_parameter: (BUS_ADDR_L), line:106
|vpiName:BUS_ADDR_L
|INT:0
|vpiParameter:
\_parameter: (BUS_BIT_CHECK), line:108
|vpiName:BUS_BIT_CHECK
|INT:1
|vpiParameter:
\_parameter: (BUS_TYPE), line:89
|vpiName:BUS_TYPE
|INT:5
|vpiParameter:
\_parameter: (COUNTER_W), line:42
|vpiName:COUNTER_W
|INT:33
|vpiParameter:
\_parameter: (CPU_ID), line:38
|vpiName:CPU_ID
|INT:0
|vpiParameter:
\_parameter: (C_DATA_WIDTH), line:62
|vpiName:C_DATA_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_DEPTH), line:62
|vpiName:C_DEPTH
|INT:4
|vpiParameter:
\_parameter: (C_M_AXI_ADDR_WIDTH), line:113
|vpiName:C_M_AXI_ADDR_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_DATA_WIDTH), line:114
|vpiName:C_M_AXI_DATA_WIDTH
|INT:1
|vpiParameter:
\_parameter: (DCACHE_LINES), line:133
|vpiName:DCACHE_LINES
|INT:-2146435073
|vpiParameter:
\_parameter: (DCACHE_LINE_ADDR_W), line:135
|vpiName:DCACHE_LINE_ADDR_W
|INT:1073741824
|vpiParameter:
\_parameter: (DCACHE_LINE_W), line:136
|vpiName:DCACHE_LINE_W
|INT:1342177279
|vpiParameter:
\_parameter: (DCACHE_SUB_LINE_ADDR_W), line:137
|vpiName:DCACHE_SUB_LINE_ADDR_W
|INT:4
|vpiParameter:
\_parameter: (DCACHE_TAG_W), line:138
|vpiName:DCACHE_TAG_W
|INT:1610612736
|vpiParameter:
\_parameter: (DCACHE_WAYS), line:134
|vpiName:DCACHE_WAYS
|INT:4
|vpiParameter:
\_parameter: (DIV_ALGORITHM), line:67
|vpiName:DIV_ALGORITHM
|INT:0
|vpiParameter:
\_parameter: (DIV_UNIT_WB_ID), line:192
|vpiName:DIV_UNIT_WB_ID
|INT:2
|vpiParameter:
\_parameter: (DTLB_DEPTH), line:152
|vpiName:DTLB_DEPTH
|INT:512
|vpiParameter:
\_parameter: (DTLB_WAYS), line:151
|vpiName:DTLB_WAYS
|INT:32
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (ENABLE_M_MODE), line:34
|vpiName:ENABLE_M_MODE
|INT:1
|vpiParameter:
\_parameter: (ENABLE_S_MODE), line:36
|vpiName:ENABLE_S_MODE
|INT:0
|vpiParameter:
\_parameter: (ENABLE_TRACE_INTERFACE), line:172
|vpiName:ENABLE_TRACE_INTERFACE
|INT:2
|vpiParameter:
\_parameter: (FETCH_BUFFER_DEPTH), line:168
|vpiName:FETCH_BUFFER_DEPTH
|INT:512
|vpiParameter:
\_parameter: (FPGA_VENDOR), line:27
|vpiName:FPGA_VENDOR
|STRING:"xilinx"
|vpiParameter:
\_parameter: (GC_UNIT_ID), line:196
|vpiName:GC_UNIT_ID
|INT:4
|vpiParameter:
\_parameter: (ICACHE_LINES), line:121
|vpiName:ICACHE_LINES
|INT:2
|vpiParameter:
\_parameter: (ICACHE_LINE_ADDR_W), line:123
|vpiName:ICACHE_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_LINE_W), line:124
|vpiName:ICACHE_LINE_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_SUB_LINE_ADDR_W), line:125
|vpiName:ICACHE_SUB_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_TAG_W), line:126
|vpiName:ICACHE_TAG_W
|INT:-2147483648
|vpiParameter:
\_parameter: (ICACHE_WAYS), line:122
|vpiName:ICACHE_WAYS
|INT:1
|vpiParameter:
\_parameter: (ITLB_DEPTH), line:146
|vpiName:ITLB_DEPTH
|INT:32
|vpiParameter:
\_parameter: (ITLB_WAYS), line:145
|vpiName:ITLB_WAYS
|INT:4
|vpiParameter:
\_parameter: (L1_CONNECTIONS), line:177
|vpiName:L1_CONNECTIONS
|INT:9
|vpiParameter:
\_parameter: (L1_DCACHE_ID), line:178
|vpiName:L1_DCACHE_ID
|INT:4
|vpiParameter:
\_parameter: (L1_DMMU_ID), line:179
|vpiName:L1_DMMU_ID
|INT:2
|vpiParameter:
\_parameter: (L1_ICACHE_ID), line:180
|vpiName:L1_ICACHE_ID
|INT:19
|vpiParameter:
\_parameter: (L1_IMMU_ID), line:181
|vpiName:L1_IMMU_ID
|INT:0
|vpiParameter:
\_parameter: (LS_UNIT_WB_ID), line:191
|vpiName:LS_UNIT_WB_ID
|INT:1
|vpiParameter:
\_parameter: (MAX_INFLIGHT_COUNT), line:167
|vpiName:MAX_INFLIGHT_COUNT
|INT:19
|vpiParameter:
\_parameter: (MEMORY_ADDR_H), line:103
|vpiName:MEMORY_ADDR_H
|INT:12
|vpiParameter:
\_parameter: (MEMORY_ADDR_L), line:102
|vpiName:MEMORY_ADDR_L
|INT:11
|vpiParameter:
\_parameter: (MEMORY_BIT_CHECK), line:104
|vpiName:MEMORY_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (MUL_UNIT_WB_ID), line:193
|vpiName:MUL_UNIT_WB_ID
|INT:512
|vpiParameter:
\_parameter: (NUM_UNITS), line:188
|vpiName:NUM_UNITS
|INT:2
|vpiParameter:
\_parameter: (NUM_WB_UNITS), line:186
|vpiName:NUM_WB_UNITS
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (RAS_DEPTH), line:161
|vpiName:RAS_DEPTH
|INT:2
|vpiParameter:
\_parameter: (RESET_VEC), line:39
|vpiName:RESET_VEC
|INT:-2147483648
|vpiParameter:
\_parameter: (SCRATCH_ADDR_H), line:99
|vpiName:SCRATCH_ADDR_H
|INT:9
|vpiParameter:
\_parameter: (SCRATCH_ADDR_L), line:98
|vpiName:SCRATCH_ADDR_L
|INT:8
|vpiParameter:
\_parameter: (SCRATCH_BIT_CHECK), line:100
|vpiName:SCRATCH_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (USE_AMO), line:70
|vpiName:USE_AMO
|INT:1
|vpiParameter:
\_parameter: (USE_BRANCH_PREDICTOR), line:158
|vpiName:USE_BRANCH_PREDICTOR
|INT:2
|vpiParameter:
\_parameter: (USE_BUS), line:88
|vpiName:USE_BUS
|INT:4
|vpiParameter:
\_parameter: (USE_DCACHE), line:92
|vpiName:USE_DCACHE
|INT:6
|vpiParameter:
\_parameter: (USE_DIV), line:49
|vpiName:USE_DIV
|INT:1
|vpiParameter:
\_parameter: (USE_DTAG_INVALIDATIONS), line:140
|vpiName:USE_DTAG_INVALIDATIONS
|INT:1879048191
|vpiParameter:
\_parameter: (USE_D_SCRATCH_MEM), line:79
|vpiName:USE_D_SCRATCH_MEM
|INT:3
|vpiParameter:
\_parameter: (USE_ICACHE), line:93
|vpiName:USE_ICACHE
|INT:7
|vpiParameter:
\_parameter: (USE_I_SCRATCH_MEM), line:78
|vpiName:USE_I_SCRATCH_MEM
|INT:2
|vpiParameter:
\_parameter: (USE_MUL), line:48
|vpiName:USE_MUL
|INT:1
|vpiParameter:
\_parameter: (WB_UNITS_WIDTH), line:187
|vpiName:WB_UNITS_WIDTH
|INT:32
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiParameter:
\_parameter: (ALU_UNIT_WB_ID), line:190
|vpiName:ALU_UNIT_WB_ID
|INT:32
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (BRANCH_PREDICTOR_WAYS), line:159
|vpiName:BRANCH_PREDICTOR_WAYS
|INT:9
|vpiParameter:
\_parameter: (BRANCH_TABLE_ENTRIES), line:160
|vpiName:BRANCH_TABLE_ENTRIES
|INT:4
|vpiParameter:
\_parameter: (BRANCH_UNIT_ID), line:195
|vpiName:BRANCH_UNIT_ID
|INT:8
|vpiParameter:
\_parameter: (BUS_ADDR_H), line:107
|vpiName:BUS_ADDR_H
|INT:1
|vpiParameter:
\_parameter: (BUS_ADDR_L), line:106
|vpiName:BUS_ADDR_L
|INT:0
|vpiParameter:
\_parameter: (BUS_BIT_CHECK), line:108
|vpiName:BUS_BIT_CHECK
|INT:1
|vpiParameter:
\_parameter: (BUS_TYPE), line:89
|vpiName:BUS_TYPE
|INT:5
|vpiParameter:
\_parameter: (COUNTER_W), line:42
|vpiName:COUNTER_W
|INT:33
|vpiParameter:
\_parameter: (CPU_ID), line:38
|vpiName:CPU_ID
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_ADDR_WIDTH), line:113
|vpiName:C_M_AXI_ADDR_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_DATA_WIDTH), line:114
|vpiName:C_M_AXI_DATA_WIDTH
|INT:1
|vpiParameter:
\_parameter: (DCACHE_LINES), line:133
|vpiName:DCACHE_LINES
|INT:-2146435073
|vpiParameter:
\_parameter: (DCACHE_LINE_ADDR_W), line:135
|vpiName:DCACHE_LINE_ADDR_W
|INT:1073741824
|vpiParameter:
\_parameter: (DCACHE_LINE_W), line:136
|vpiName:DCACHE_LINE_W
|INT:1342177279
|vpiParameter:
\_parameter: (DCACHE_SUB_LINE_ADDR_W), line:137
|vpiName:DCACHE_SUB_LINE_ADDR_W
|INT:4
|vpiParameter:
\_parameter: (DCACHE_TAG_W), line:138
|vpiName:DCACHE_TAG_W
|INT:1610612736
|vpiParameter:
\_parameter: (DCACHE_WAYS), line:134
|vpiName:DCACHE_WAYS
|INT:4
|vpiParameter:
\_parameter: (DIV_ALGORITHM), line:67
|vpiName:DIV_ALGORITHM
|INT:0
|vpiParameter:
\_parameter: (DIV_UNIT_WB_ID), line:192
|vpiName:DIV_UNIT_WB_ID
|INT:2
|vpiParameter:
\_parameter: (DTLB_DEPTH), line:152
|vpiName:DTLB_DEPTH
|INT:512
|vpiParameter:
\_parameter: (DTLB_WAYS), line:151
|vpiName:DTLB_WAYS
|INT:32
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (ENABLE_M_MODE), line:34
|vpiName:ENABLE_M_MODE
|INT:1
|vpiParameter:
\_parameter: (ENABLE_S_MODE), line:36
|vpiName:ENABLE_S_MODE
|INT:0
|vpiParameter:
\_parameter: (ENABLE_TRACE_INTERFACE), line:172
|vpiName:ENABLE_TRACE_INTERFACE
|INT:2
|vpiParameter:
\_parameter: (FETCH_BUFFER_DEPTH), line:168
|vpiName:FETCH_BUFFER_DEPTH
|INT:512
|vpiParameter:
\_parameter: (FPGA_VENDOR), line:27
|vpiName:FPGA_VENDOR
|STRING:"xilinx"
|vpiParameter:
\_parameter: (GC_UNIT_ID), line:196
|vpiName:GC_UNIT_ID
|INT:4
|vpiParameter:
\_parameter: (ICACHE_LINES), line:121
|vpiName:ICACHE_LINES
|INT:2
|vpiParameter:
\_parameter: (ICACHE_LINE_ADDR_W), line:123
|vpiName:ICACHE_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_LINE_W), line:124
|vpiName:ICACHE_LINE_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_SUB_LINE_ADDR_W), line:125
|vpiName:ICACHE_SUB_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_TAG_W), line:126
|vpiName:ICACHE_TAG_W
|INT:-2147483648
|vpiParameter:
\_parameter: (ICACHE_WAYS), line:122
|vpiName:ICACHE_WAYS
|INT:1
|vpiParameter:
\_parameter: (ITLB_DEPTH), line:146
|vpiName:ITLB_DEPTH
|INT:32
|vpiParameter:
\_parameter: (ITLB_WAYS), line:145
|vpiName:ITLB_WAYS
|INT:4
|vpiParameter:
\_parameter: (L1_CONNECTIONS), line:177
|vpiName:L1_CONNECTIONS
|INT:9
|vpiParameter:
\_parameter: (L1_DCACHE_ID), line:178
|vpiName:L1_DCACHE_ID
|INT:4
|vpiParameter:
\_parameter: (L1_DMMU_ID), line:179
|vpiName:L1_DMMU_ID
|INT:2
|vpiParameter:
\_parameter: (L1_ICACHE_ID), line:180
|vpiName:L1_ICACHE_ID
|INT:19
|vpiParameter:
\_parameter: (L1_IMMU_ID), line:181
|vpiName:L1_IMMU_ID
|INT:0
|vpiParameter:
\_parameter: (LS_UNIT_WB_ID), line:191
|vpiName:LS_UNIT_WB_ID
|INT:1
|vpiParameter:
\_parameter: (MAX_INFLIGHT_COUNT), line:167
|vpiName:MAX_INFLIGHT_COUNT
|INT:19
|vpiParameter:
\_parameter: (MEMORY_ADDR_H), line:103
|vpiName:MEMORY_ADDR_H
|INT:12
|vpiParameter:
\_parameter: (MEMORY_ADDR_L), line:102
|vpiName:MEMORY_ADDR_L
|INT:11
|vpiParameter:
\_parameter: (MEMORY_BIT_CHECK), line:104
|vpiName:MEMORY_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (MUL_UNIT_WB_ID), line:193
|vpiName:MUL_UNIT_WB_ID
|INT:512
|vpiParameter:
\_parameter: (NUM_UNITS), line:188
|vpiName:NUM_UNITS
|INT:2
|vpiParameter:
\_parameter: (NUM_WB_UNITS), line:186
|vpiName:NUM_WB_UNITS
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (RAS_DEPTH), line:161
|vpiName:RAS_DEPTH
|INT:2
|vpiParameter:
\_parameter: (RESET_VEC), line:39
|vpiName:RESET_VEC
|INT:-2147483648
|vpiParameter:
\_parameter: (SCRATCH_ADDR_H), line:99
|vpiName:SCRATCH_ADDR_H
|INT:9
|vpiParameter:
\_parameter: (SCRATCH_ADDR_L), line:98
|vpiName:SCRATCH_ADDR_L
|INT:8
|vpiParameter:
\_parameter: (SCRATCH_BIT_CHECK), line:100
|vpiName:SCRATCH_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (USE_AMO), line:70
|vpiName:USE_AMO
|INT:1
|vpiParameter:
\_parameter: (USE_BRANCH_PREDICTOR), line:158
|vpiName:USE_BRANCH_PREDICTOR
|INT:2
|vpiParameter:
\_parameter: (USE_BUS), line:88
|vpiName:USE_BUS
|INT:4
|vpiParameter:
\_parameter: (USE_DCACHE), line:92
|vpiName:USE_DCACHE
|INT:6
|vpiParameter:
\_parameter: (USE_DIV), line:49
|vpiName:USE_DIV
|INT:1
|vpiParameter:
\_parameter: (USE_DTAG_INVALIDATIONS), line:140
|vpiName:USE_DTAG_INVALIDATIONS
|INT:1879048191
|vpiParameter:
\_parameter: (USE_D_SCRATCH_MEM), line:79
|vpiName:USE_D_SCRATCH_MEM
|INT:3
|vpiParameter:
\_parameter: (USE_ICACHE), line:93
|vpiName:USE_ICACHE
|INT:7
|vpiParameter:
\_parameter: (USE_I_SCRATCH_MEM), line:78
|vpiName:USE_I_SCRATCH_MEM
|INT:2
|vpiParameter:
\_parameter: (USE_MUL), line:48
|vpiName:USE_MUL
|INT:1
|vpiParameter:
\_parameter: (WB_UNITS_WIDTH), line:187
|vpiName:WB_UNITS_WIDTH
|INT:32
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiParameter:
\_parameter: (i), line:61
|vpiName:i
|INT:2
|vpiGenScopeArray:
\_gen_scope_array: (branch_tag_banks[3]), line:61
|vpiName:branch_tag_banks[3]
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_tag_banks.branch_tag_banks[3]
|vpiGenScope:
\_gen_scope: , parent:branch_tag_banks[3]
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_tag_banks.branch_tag_banks[3]
|vpiModule:
\_module: work@branch_predictor_ram (tag_bank), file:third_party/cores/taiga/core/branch_predictor.sv, line:62
|vpiDefName:work@branch_predictor_ram
|vpiName:tag_bank
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_tag_banks.branch_tag_banks[3].tag_bank
|vpiPort:
\_port: (clk), line:32, parent:tag_bank
|vpiName:clk
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (clk), line:63
|vpiName:clk
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (clk), line:32, parent:tag_bank
|vpiName:clk
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_tag_banks.branch_tag_banks[3].tag_bank.clk
|vpiNetType:36
|vpiPort:
\_port: (write_addr), line:33, parent:tag_bank
|vpiName:write_addr
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (write_addr), line:63
|vpiName:write_addr
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (write_addr), line:33, parent:tag_bank
|vpiName:write_addr
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_tag_banks.branch_tag_banks[3].tag_bank.write_addr
|vpiNetType:36
|vpiRange:
\_range: , line:33
|vpiLeftRange:
\_constant: , line:33
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:33
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiPort:
\_port: (write_en), line:34, parent:tag_bank
|vpiName:write_en
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (write_en), line:63
|vpiName:write_en
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (write_en), line:34, parent:tag_bank
|vpiName:write_en
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_tag_banks.branch_tag_banks[3].tag_bank.write_en
|vpiNetType:36
|vpiPort:
\_port: (read_addr), line:35, parent:tag_bank
|vpiName:read_addr
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (read_addr), line:63
|vpiName:read_addr
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (read_addr), line:35, parent:tag_bank
|vpiName:read_addr
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_tag_banks.branch_tag_banks[3].tag_bank.read_addr
|vpiNetType:36
|vpiRange:
\_range: , line:35
|vpiLeftRange:
\_constant: , line:35
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:35
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiPort:
\_port: (read_en), line:36, parent:tag_bank
|vpiName:read_en
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (read_en), line:63
|vpiName:read_en
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (read_en), line:36, parent:tag_bank
|vpiName:read_en
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_tag_banks.branch_tag_banks[3].tag_bank.read_en
|vpiNetType:36
|vpiPort:
\_port: (write_data), line:37, parent:tag_bank
|vpiName:write_data
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (write_data), line:63
|vpiName:write_data
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (write_data), line:37, parent:tag_bank
|vpiName:write_data
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_tag_banks.branch_tag_banks[3].tag_bank.write_data
|vpiNetType:36
|vpiRange:
\_range: , line:37
|vpiLeftRange:
\_constant: , line:37
|vpiDecompile:-1
|INT:-1
|vpiRightRange:
\_constant: , line:37
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiPort:
\_port: (read_data), line:38, parent:tag_bank
|vpiName:read_data
|vpiDirection:2
|vpiHighConn:
\_ref_obj: (read_data), line:63
|vpiName:read_data
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (read_data), line:38, parent:tag_bank
|vpiName:read_data
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_tag_banks.branch_tag_banks[3].tag_bank.read_data
|vpiNetType:36
|vpiRange:
\_range: , line:38
|vpiLeftRange:
\_constant: , line:38
|vpiDecompile:-1
|INT:-1
|vpiRightRange:
\_constant: , line:38
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (clk), line:32, parent:tag_bank
|vpiNet:
\_logic_net: (write_addr), line:33, parent:tag_bank
|vpiNet:
\_logic_net: (write_en), line:34, parent:tag_bank
|vpiNet:
\_logic_net: (read_addr), line:35, parent:tag_bank
|vpiNet:
\_logic_net: (read_en), line:36, parent:tag_bank
|vpiNet:
\_logic_net: (write_data), line:37, parent:tag_bank
|vpiNet:
\_logic_net: (read_data), line:38, parent:tag_bank
|vpiArrayNet:
\_array_net: (branch_ram), line:40, parent:tag_bank
|vpiName:branch_ram
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_tag_banks.branch_tag_banks[3].tag_bank.branch_ram
|vpiSize:4
|vpiNet:
\_logic_net: , parent:branch_ram
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_tag_banks.branch_tag_banks[3].tag_bank.branch_ram
|vpiNetType:36
|vpiRange:
\_range: , line:40
|vpiLeftRange:
\_constant: , line:40
|vpiDecompile:-1
|INT:-1
|vpiRightRange:
\_constant: , line:40
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiRange:
\_range: , line:40
|vpiLeftRange:
\_constant: , line:40
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiRightRange:
\_constant: , line:40
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiParameter:
\_parameter: (ALU_UNIT_WB_ID), line:190
|vpiName:ALU_UNIT_WB_ID
|INT:32
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (BRANCH_PREDICTOR_WAYS), line:159
|vpiName:BRANCH_PREDICTOR_WAYS
|INT:9
|vpiParameter:
\_parameter: (BRANCH_TABLE_ENTRIES), line:160
|vpiName:BRANCH_TABLE_ENTRIES
|INT:4
|vpiParameter:
\_parameter: (BRANCH_UNIT_ID), line:195
|vpiName:BRANCH_UNIT_ID
|INT:8
|vpiParameter:
\_parameter: (BUS_ADDR_H), line:107
|vpiName:BUS_ADDR_H
|INT:1
|vpiParameter:
\_parameter: (BUS_ADDR_L), line:106
|vpiName:BUS_ADDR_L
|INT:0
|vpiParameter:
\_parameter: (BUS_BIT_CHECK), line:108
|vpiName:BUS_BIT_CHECK
|INT:1
|vpiParameter:
\_parameter: (BUS_TYPE), line:89
|vpiName:BUS_TYPE
|INT:5
|vpiParameter:
\_parameter: (COUNTER_W), line:42
|vpiName:COUNTER_W
|INT:33
|vpiParameter:
\_parameter: (CPU_ID), line:38
|vpiName:CPU_ID
|INT:0
|vpiParameter:
\_parameter: (C_DATA_WIDTH), line:62
|vpiName:C_DATA_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_DEPTH), line:62
|vpiName:C_DEPTH
|INT:4
|vpiParameter:
\_parameter: (C_M_AXI_ADDR_WIDTH), line:113
|vpiName:C_M_AXI_ADDR_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_DATA_WIDTH), line:114
|vpiName:C_M_AXI_DATA_WIDTH
|INT:1
|vpiParameter:
\_parameter: (DCACHE_LINES), line:133
|vpiName:DCACHE_LINES
|INT:-2146435073
|vpiParameter:
\_parameter: (DCACHE_LINE_ADDR_W), line:135
|vpiName:DCACHE_LINE_ADDR_W
|INT:1073741824
|vpiParameter:
\_parameter: (DCACHE_LINE_W), line:136
|vpiName:DCACHE_LINE_W
|INT:1342177279
|vpiParameter:
\_parameter: (DCACHE_SUB_LINE_ADDR_W), line:137
|vpiName:DCACHE_SUB_LINE_ADDR_W
|INT:4
|vpiParameter:
\_parameter: (DCACHE_TAG_W), line:138
|vpiName:DCACHE_TAG_W
|INT:1610612736
|vpiParameter:
\_parameter: (DCACHE_WAYS), line:134
|vpiName:DCACHE_WAYS
|INT:4
|vpiParameter:
\_parameter: (DIV_ALGORITHM), line:67
|vpiName:DIV_ALGORITHM
|INT:0
|vpiParameter:
\_parameter: (DIV_UNIT_WB_ID), line:192
|vpiName:DIV_UNIT_WB_ID
|INT:2
|vpiParameter:
\_parameter: (DTLB_DEPTH), line:152
|vpiName:DTLB_DEPTH
|INT:512
|vpiParameter:
\_parameter: (DTLB_WAYS), line:151
|vpiName:DTLB_WAYS
|INT:32
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (ENABLE_M_MODE), line:34
|vpiName:ENABLE_M_MODE
|INT:1
|vpiParameter:
\_parameter: (ENABLE_S_MODE), line:36
|vpiName:ENABLE_S_MODE
|INT:0
|vpiParameter:
\_parameter: (ENABLE_TRACE_INTERFACE), line:172
|vpiName:ENABLE_TRACE_INTERFACE
|INT:2
|vpiParameter:
\_parameter: (FETCH_BUFFER_DEPTH), line:168
|vpiName:FETCH_BUFFER_DEPTH
|INT:512
|vpiParameter:
\_parameter: (FPGA_VENDOR), line:27
|vpiName:FPGA_VENDOR
|STRING:"xilinx"
|vpiParameter:
\_parameter: (GC_UNIT_ID), line:196
|vpiName:GC_UNIT_ID
|INT:4
|vpiParameter:
\_parameter: (ICACHE_LINES), line:121
|vpiName:ICACHE_LINES
|INT:2
|vpiParameter:
\_parameter: (ICACHE_LINE_ADDR_W), line:123
|vpiName:ICACHE_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_LINE_W), line:124
|vpiName:ICACHE_LINE_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_SUB_LINE_ADDR_W), line:125
|vpiName:ICACHE_SUB_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_TAG_W), line:126
|vpiName:ICACHE_TAG_W
|INT:-2147483648
|vpiParameter:
\_parameter: (ICACHE_WAYS), line:122
|vpiName:ICACHE_WAYS
|INT:1
|vpiParameter:
\_parameter: (ITLB_DEPTH), line:146
|vpiName:ITLB_DEPTH
|INT:32
|vpiParameter:
\_parameter: (ITLB_WAYS), line:145
|vpiName:ITLB_WAYS
|INT:4
|vpiParameter:
\_parameter: (L1_CONNECTIONS), line:177
|vpiName:L1_CONNECTIONS
|INT:9
|vpiParameter:
\_parameter: (L1_DCACHE_ID), line:178
|vpiName:L1_DCACHE_ID
|INT:4
|vpiParameter:
\_parameter: (L1_DMMU_ID), line:179
|vpiName:L1_DMMU_ID
|INT:2
|vpiParameter:
\_parameter: (L1_ICACHE_ID), line:180
|vpiName:L1_ICACHE_ID
|INT:19
|vpiParameter:
\_parameter: (L1_IMMU_ID), line:181
|vpiName:L1_IMMU_ID
|INT:0
|vpiParameter:
\_parameter: (LS_UNIT_WB_ID), line:191
|vpiName:LS_UNIT_WB_ID
|INT:1
|vpiParameter:
\_parameter: (MAX_INFLIGHT_COUNT), line:167
|vpiName:MAX_INFLIGHT_COUNT
|INT:19
|vpiParameter:
\_parameter: (MEMORY_ADDR_H), line:103
|vpiName:MEMORY_ADDR_H
|INT:12
|vpiParameter:
\_parameter: (MEMORY_ADDR_L), line:102
|vpiName:MEMORY_ADDR_L
|INT:11
|vpiParameter:
\_parameter: (MEMORY_BIT_CHECK), line:104
|vpiName:MEMORY_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (MUL_UNIT_WB_ID), line:193
|vpiName:MUL_UNIT_WB_ID
|INT:512
|vpiParameter:
\_parameter: (NUM_UNITS), line:188
|vpiName:NUM_UNITS
|INT:2
|vpiParameter:
\_parameter: (NUM_WB_UNITS), line:186
|vpiName:NUM_WB_UNITS
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (RAS_DEPTH), line:161
|vpiName:RAS_DEPTH
|INT:2
|vpiParameter:
\_parameter: (RESET_VEC), line:39
|vpiName:RESET_VEC
|INT:-2147483648
|vpiParameter:
\_parameter: (SCRATCH_ADDR_H), line:99
|vpiName:SCRATCH_ADDR_H
|INT:9
|vpiParameter:
\_parameter: (SCRATCH_ADDR_L), line:98
|vpiName:SCRATCH_ADDR_L
|INT:8
|vpiParameter:
\_parameter: (SCRATCH_BIT_CHECK), line:100
|vpiName:SCRATCH_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (USE_AMO), line:70
|vpiName:USE_AMO
|INT:1
|vpiParameter:
\_parameter: (USE_BRANCH_PREDICTOR), line:158
|vpiName:USE_BRANCH_PREDICTOR
|INT:2
|vpiParameter:
\_parameter: (USE_BUS), line:88
|vpiName:USE_BUS
|INT:4
|vpiParameter:
\_parameter: (USE_DCACHE), line:92
|vpiName:USE_DCACHE
|INT:6
|vpiParameter:
\_parameter: (USE_DIV), line:49
|vpiName:USE_DIV
|INT:1
|vpiParameter:
\_parameter: (USE_DTAG_INVALIDATIONS), line:140
|vpiName:USE_DTAG_INVALIDATIONS
|INT:1879048191
|vpiParameter:
\_parameter: (USE_D_SCRATCH_MEM), line:79
|vpiName:USE_D_SCRATCH_MEM
|INT:3
|vpiParameter:
\_parameter: (USE_ICACHE), line:93
|vpiName:USE_ICACHE
|INT:7
|vpiParameter:
\_parameter: (USE_I_SCRATCH_MEM), line:78
|vpiName:USE_I_SCRATCH_MEM
|INT:2
|vpiParameter:
\_parameter: (USE_MUL), line:48
|vpiName:USE_MUL
|INT:1
|vpiParameter:
\_parameter: (WB_UNITS_WIDTH), line:187
|vpiName:WB_UNITS_WIDTH
|INT:32
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiParameter:
\_parameter: (ALU_UNIT_WB_ID), line:190
|vpiName:ALU_UNIT_WB_ID
|INT:32
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (BRANCH_PREDICTOR_WAYS), line:159
|vpiName:BRANCH_PREDICTOR_WAYS
|INT:9
|vpiParameter:
\_parameter: (BRANCH_TABLE_ENTRIES), line:160
|vpiName:BRANCH_TABLE_ENTRIES
|INT:4
|vpiParameter:
\_parameter: (BRANCH_UNIT_ID), line:195
|vpiName:BRANCH_UNIT_ID
|INT:8
|vpiParameter:
\_parameter: (BUS_ADDR_H), line:107
|vpiName:BUS_ADDR_H
|INT:1
|vpiParameter:
\_parameter: (BUS_ADDR_L), line:106
|vpiName:BUS_ADDR_L
|INT:0
|vpiParameter:
\_parameter: (BUS_BIT_CHECK), line:108
|vpiName:BUS_BIT_CHECK
|INT:1
|vpiParameter:
\_parameter: (BUS_TYPE), line:89
|vpiName:BUS_TYPE
|INT:5
|vpiParameter:
\_parameter: (COUNTER_W), line:42
|vpiName:COUNTER_W
|INT:33
|vpiParameter:
\_parameter: (CPU_ID), line:38
|vpiName:CPU_ID
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_ADDR_WIDTH), line:113
|vpiName:C_M_AXI_ADDR_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_DATA_WIDTH), line:114
|vpiName:C_M_AXI_DATA_WIDTH
|INT:1
|vpiParameter:
\_parameter: (DCACHE_LINES), line:133
|vpiName:DCACHE_LINES
|INT:-2146435073
|vpiParameter:
\_parameter: (DCACHE_LINE_ADDR_W), line:135
|vpiName:DCACHE_LINE_ADDR_W
|INT:1073741824
|vpiParameter:
\_parameter: (DCACHE_LINE_W), line:136
|vpiName:DCACHE_LINE_W
|INT:1342177279
|vpiParameter:
\_parameter: (DCACHE_SUB_LINE_ADDR_W), line:137
|vpiName:DCACHE_SUB_LINE_ADDR_W
|INT:4
|vpiParameter:
\_parameter: (DCACHE_TAG_W), line:138
|vpiName:DCACHE_TAG_W
|INT:1610612736
|vpiParameter:
\_parameter: (DCACHE_WAYS), line:134
|vpiName:DCACHE_WAYS
|INT:4
|vpiParameter:
\_parameter: (DIV_ALGORITHM), line:67
|vpiName:DIV_ALGORITHM
|INT:0
|vpiParameter:
\_parameter: (DIV_UNIT_WB_ID), line:192
|vpiName:DIV_UNIT_WB_ID
|INT:2
|vpiParameter:
\_parameter: (DTLB_DEPTH), line:152
|vpiName:DTLB_DEPTH
|INT:512
|vpiParameter:
\_parameter: (DTLB_WAYS), line:151
|vpiName:DTLB_WAYS
|INT:32
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (ENABLE_M_MODE), line:34
|vpiName:ENABLE_M_MODE
|INT:1
|vpiParameter:
\_parameter: (ENABLE_S_MODE), line:36
|vpiName:ENABLE_S_MODE
|INT:0
|vpiParameter:
\_parameter: (ENABLE_TRACE_INTERFACE), line:172
|vpiName:ENABLE_TRACE_INTERFACE
|INT:2
|vpiParameter:
\_parameter: (FETCH_BUFFER_DEPTH), line:168
|vpiName:FETCH_BUFFER_DEPTH
|INT:512
|vpiParameter:
\_parameter: (FPGA_VENDOR), line:27
|vpiName:FPGA_VENDOR
|STRING:"xilinx"
|vpiParameter:
\_parameter: (GC_UNIT_ID), line:196
|vpiName:GC_UNIT_ID
|INT:4
|vpiParameter:
\_parameter: (ICACHE_LINES), line:121
|vpiName:ICACHE_LINES
|INT:2
|vpiParameter:
\_parameter: (ICACHE_LINE_ADDR_W), line:123
|vpiName:ICACHE_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_LINE_W), line:124
|vpiName:ICACHE_LINE_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_SUB_LINE_ADDR_W), line:125
|vpiName:ICACHE_SUB_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_TAG_W), line:126
|vpiName:ICACHE_TAG_W
|INT:-2147483648
|vpiParameter:
\_parameter: (ICACHE_WAYS), line:122
|vpiName:ICACHE_WAYS
|INT:1
|vpiParameter:
\_parameter: (ITLB_DEPTH), line:146
|vpiName:ITLB_DEPTH
|INT:32
|vpiParameter:
\_parameter: (ITLB_WAYS), line:145
|vpiName:ITLB_WAYS
|INT:4
|vpiParameter:
\_parameter: (L1_CONNECTIONS), line:177
|vpiName:L1_CONNECTIONS
|INT:9
|vpiParameter:
\_parameter: (L1_DCACHE_ID), line:178
|vpiName:L1_DCACHE_ID
|INT:4
|vpiParameter:
\_parameter: (L1_DMMU_ID), line:179
|vpiName:L1_DMMU_ID
|INT:2
|vpiParameter:
\_parameter: (L1_ICACHE_ID), line:180
|vpiName:L1_ICACHE_ID
|INT:19
|vpiParameter:
\_parameter: (L1_IMMU_ID), line:181
|vpiName:L1_IMMU_ID
|INT:0
|vpiParameter:
\_parameter: (LS_UNIT_WB_ID), line:191
|vpiName:LS_UNIT_WB_ID
|INT:1
|vpiParameter:
\_parameter: (MAX_INFLIGHT_COUNT), line:167
|vpiName:MAX_INFLIGHT_COUNT
|INT:19
|vpiParameter:
\_parameter: (MEMORY_ADDR_H), line:103
|vpiName:MEMORY_ADDR_H
|INT:12
|vpiParameter:
\_parameter: (MEMORY_ADDR_L), line:102
|vpiName:MEMORY_ADDR_L
|INT:11
|vpiParameter:
\_parameter: (MEMORY_BIT_CHECK), line:104
|vpiName:MEMORY_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (MUL_UNIT_WB_ID), line:193
|vpiName:MUL_UNIT_WB_ID
|INT:512
|vpiParameter:
\_parameter: (NUM_UNITS), line:188
|vpiName:NUM_UNITS
|INT:2
|vpiParameter:
\_parameter: (NUM_WB_UNITS), line:186
|vpiName:NUM_WB_UNITS
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (RAS_DEPTH), line:161
|vpiName:RAS_DEPTH
|INT:2
|vpiParameter:
\_parameter: (RESET_VEC), line:39
|vpiName:RESET_VEC
|INT:-2147483648
|vpiParameter:
\_parameter: (SCRATCH_ADDR_H), line:99
|vpiName:SCRATCH_ADDR_H
|INT:9
|vpiParameter:
\_parameter: (SCRATCH_ADDR_L), line:98
|vpiName:SCRATCH_ADDR_L
|INT:8
|vpiParameter:
\_parameter: (SCRATCH_BIT_CHECK), line:100
|vpiName:SCRATCH_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (USE_AMO), line:70
|vpiName:USE_AMO
|INT:1
|vpiParameter:
\_parameter: (USE_BRANCH_PREDICTOR), line:158
|vpiName:USE_BRANCH_PREDICTOR
|INT:2
|vpiParameter:
\_parameter: (USE_BUS), line:88
|vpiName:USE_BUS
|INT:4
|vpiParameter:
\_parameter: (USE_DCACHE), line:92
|vpiName:USE_DCACHE
|INT:6
|vpiParameter:
\_parameter: (USE_DIV), line:49
|vpiName:USE_DIV
|INT:1
|vpiParameter:
\_parameter: (USE_DTAG_INVALIDATIONS), line:140
|vpiName:USE_DTAG_INVALIDATIONS
|INT:1879048191
|vpiParameter:
\_parameter: (USE_D_SCRATCH_MEM), line:79
|vpiName:USE_D_SCRATCH_MEM
|INT:3
|vpiParameter:
\_parameter: (USE_ICACHE), line:93
|vpiName:USE_ICACHE
|INT:7
|vpiParameter:
\_parameter: (USE_I_SCRATCH_MEM), line:78
|vpiName:USE_I_SCRATCH_MEM
|INT:2
|vpiParameter:
\_parameter: (USE_MUL), line:48
|vpiName:USE_MUL
|INT:1
|vpiParameter:
\_parameter: (WB_UNITS_WIDTH), line:187
|vpiName:WB_UNITS_WIDTH
|INT:32
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiParameter:
\_parameter: (i), line:61
|vpiName:i
|INT:3
|vpiGenScopeArray:
\_gen_scope_array: (branch_tag_banks[4]), line:61
|vpiName:branch_tag_banks[4]
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_tag_banks.branch_tag_banks[4]
|vpiGenScope:
\_gen_scope: , parent:branch_tag_banks[4]
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_tag_banks.branch_tag_banks[4]
|vpiModule:
\_module: work@branch_predictor_ram (tag_bank), file:third_party/cores/taiga/core/branch_predictor.sv, line:62
|vpiDefName:work@branch_predictor_ram
|vpiName:tag_bank
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_tag_banks.branch_tag_banks[4].tag_bank
|vpiPort:
\_port: (clk), line:32, parent:tag_bank
|vpiName:clk
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (clk), line:63
|vpiName:clk
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (clk), line:32, parent:tag_bank
|vpiName:clk
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_tag_banks.branch_tag_banks[4].tag_bank.clk
|vpiNetType:36
|vpiPort:
\_port: (write_addr), line:33, parent:tag_bank
|vpiName:write_addr
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (write_addr), line:63
|vpiName:write_addr
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (write_addr), line:33, parent:tag_bank
|vpiName:write_addr
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_tag_banks.branch_tag_banks[4].tag_bank.write_addr
|vpiNetType:36
|vpiRange:
\_range: , line:33
|vpiLeftRange:
\_constant: , line:33
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:33
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiPort:
\_port: (write_en), line:34, parent:tag_bank
|vpiName:write_en
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (write_en), line:63
|vpiName:write_en
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (write_en), line:34, parent:tag_bank
|vpiName:write_en
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_tag_banks.branch_tag_banks[4].tag_bank.write_en
|vpiNetType:36
|vpiPort:
\_port: (read_addr), line:35, parent:tag_bank
|vpiName:read_addr
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (read_addr), line:63
|vpiName:read_addr
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (read_addr), line:35, parent:tag_bank
|vpiName:read_addr
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_tag_banks.branch_tag_banks[4].tag_bank.read_addr
|vpiNetType:36
|vpiRange:
\_range: , line:35
|vpiLeftRange:
\_constant: , line:35
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:35
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiPort:
\_port: (read_en), line:36, parent:tag_bank
|vpiName:read_en
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (read_en), line:63
|vpiName:read_en
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (read_en), line:36, parent:tag_bank
|vpiName:read_en
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_tag_banks.branch_tag_banks[4].tag_bank.read_en
|vpiNetType:36
|vpiPort:
\_port: (write_data), line:37, parent:tag_bank
|vpiName:write_data
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (write_data), line:63
|vpiName:write_data
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (write_data), line:37, parent:tag_bank
|vpiName:write_data
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_tag_banks.branch_tag_banks[4].tag_bank.write_data
|vpiNetType:36
|vpiRange:
\_range: , line:37
|vpiLeftRange:
\_constant: , line:37
|vpiDecompile:-1
|INT:-1
|vpiRightRange:
\_constant: , line:37
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiPort:
\_port: (read_data), line:38, parent:tag_bank
|vpiName:read_data
|vpiDirection:2
|vpiHighConn:
\_ref_obj: (read_data), line:63
|vpiName:read_data
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (read_data), line:38, parent:tag_bank
|vpiName:read_data
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_tag_banks.branch_tag_banks[4].tag_bank.read_data
|vpiNetType:36
|vpiRange:
\_range: , line:38
|vpiLeftRange:
\_constant: , line:38
|vpiDecompile:-1
|INT:-1
|vpiRightRange:
\_constant: , line:38
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (clk), line:32, parent:tag_bank
|vpiNet:
\_logic_net: (write_addr), line:33, parent:tag_bank
|vpiNet:
\_logic_net: (write_en), line:34, parent:tag_bank
|vpiNet:
\_logic_net: (read_addr), line:35, parent:tag_bank
|vpiNet:
\_logic_net: (read_en), line:36, parent:tag_bank
|vpiNet:
\_logic_net: (write_data), line:37, parent:tag_bank
|vpiNet:
\_logic_net: (read_data), line:38, parent:tag_bank
|vpiArrayNet:
\_array_net: (branch_ram), line:40, parent:tag_bank
|vpiName:branch_ram
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_tag_banks.branch_tag_banks[4].tag_bank.branch_ram
|vpiSize:4
|vpiNet:
\_logic_net: , parent:branch_ram
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_tag_banks.branch_tag_banks[4].tag_bank.branch_ram
|vpiNetType:36
|vpiRange:
\_range: , line:40
|vpiLeftRange:
\_constant: , line:40
|vpiDecompile:-1
|INT:-1
|vpiRightRange:
\_constant: , line:40
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiRange:
\_range: , line:40
|vpiLeftRange:
\_constant: , line:40
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiRightRange:
\_constant: , line:40
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiParameter:
\_parameter: (ALU_UNIT_WB_ID), line:190
|vpiName:ALU_UNIT_WB_ID
|INT:32
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (BRANCH_PREDICTOR_WAYS), line:159
|vpiName:BRANCH_PREDICTOR_WAYS
|INT:9
|vpiParameter:
\_parameter: (BRANCH_TABLE_ENTRIES), line:160
|vpiName:BRANCH_TABLE_ENTRIES
|INT:4
|vpiParameter:
\_parameter: (BRANCH_UNIT_ID), line:195
|vpiName:BRANCH_UNIT_ID
|INT:8
|vpiParameter:
\_parameter: (BUS_ADDR_H), line:107
|vpiName:BUS_ADDR_H
|INT:1
|vpiParameter:
\_parameter: (BUS_ADDR_L), line:106
|vpiName:BUS_ADDR_L
|INT:0
|vpiParameter:
\_parameter: (BUS_BIT_CHECK), line:108
|vpiName:BUS_BIT_CHECK
|INT:1
|vpiParameter:
\_parameter: (BUS_TYPE), line:89
|vpiName:BUS_TYPE
|INT:5
|vpiParameter:
\_parameter: (COUNTER_W), line:42
|vpiName:COUNTER_W
|INT:33
|vpiParameter:
\_parameter: (CPU_ID), line:38
|vpiName:CPU_ID
|INT:0
|vpiParameter:
\_parameter: (C_DATA_WIDTH), line:62
|vpiName:C_DATA_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_DEPTH), line:62
|vpiName:C_DEPTH
|INT:4
|vpiParameter:
\_parameter: (C_M_AXI_ADDR_WIDTH), line:113
|vpiName:C_M_AXI_ADDR_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_DATA_WIDTH), line:114
|vpiName:C_M_AXI_DATA_WIDTH
|INT:1
|vpiParameter:
\_parameter: (DCACHE_LINES), line:133
|vpiName:DCACHE_LINES
|INT:-2146435073
|vpiParameter:
\_parameter: (DCACHE_LINE_ADDR_W), line:135
|vpiName:DCACHE_LINE_ADDR_W
|INT:1073741824
|vpiParameter:
\_parameter: (DCACHE_LINE_W), line:136
|vpiName:DCACHE_LINE_W
|INT:1342177279
|vpiParameter:
\_parameter: (DCACHE_SUB_LINE_ADDR_W), line:137
|vpiName:DCACHE_SUB_LINE_ADDR_W
|INT:4
|vpiParameter:
\_parameter: (DCACHE_TAG_W), line:138
|vpiName:DCACHE_TAG_W
|INT:1610612736
|vpiParameter:
\_parameter: (DCACHE_WAYS), line:134
|vpiName:DCACHE_WAYS
|INT:4
|vpiParameter:
\_parameter: (DIV_ALGORITHM), line:67
|vpiName:DIV_ALGORITHM
|INT:0
|vpiParameter:
\_parameter: (DIV_UNIT_WB_ID), line:192
|vpiName:DIV_UNIT_WB_ID
|INT:2
|vpiParameter:
\_parameter: (DTLB_DEPTH), line:152
|vpiName:DTLB_DEPTH
|INT:512
|vpiParameter:
\_parameter: (DTLB_WAYS), line:151
|vpiName:DTLB_WAYS
|INT:32
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (ENABLE_M_MODE), line:34
|vpiName:ENABLE_M_MODE
|INT:1
|vpiParameter:
\_parameter: (ENABLE_S_MODE), line:36
|vpiName:ENABLE_S_MODE
|INT:0
|vpiParameter:
\_parameter: (ENABLE_TRACE_INTERFACE), line:172
|vpiName:ENABLE_TRACE_INTERFACE
|INT:2
|vpiParameter:
\_parameter: (FETCH_BUFFER_DEPTH), line:168
|vpiName:FETCH_BUFFER_DEPTH
|INT:512
|vpiParameter:
\_parameter: (FPGA_VENDOR), line:27
|vpiName:FPGA_VENDOR
|STRING:"xilinx"
|vpiParameter:
\_parameter: (GC_UNIT_ID), line:196
|vpiName:GC_UNIT_ID
|INT:4
|vpiParameter:
\_parameter: (ICACHE_LINES), line:121
|vpiName:ICACHE_LINES
|INT:2
|vpiParameter:
\_parameter: (ICACHE_LINE_ADDR_W), line:123
|vpiName:ICACHE_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_LINE_W), line:124
|vpiName:ICACHE_LINE_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_SUB_LINE_ADDR_W), line:125
|vpiName:ICACHE_SUB_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_TAG_W), line:126
|vpiName:ICACHE_TAG_W
|INT:-2147483648
|vpiParameter:
\_parameter: (ICACHE_WAYS), line:122
|vpiName:ICACHE_WAYS
|INT:1
|vpiParameter:
\_parameter: (ITLB_DEPTH), line:146
|vpiName:ITLB_DEPTH
|INT:32
|vpiParameter:
\_parameter: (ITLB_WAYS), line:145
|vpiName:ITLB_WAYS
|INT:4
|vpiParameter:
\_parameter: (L1_CONNECTIONS), line:177
|vpiName:L1_CONNECTIONS
|INT:9
|vpiParameter:
\_parameter: (L1_DCACHE_ID), line:178
|vpiName:L1_DCACHE_ID
|INT:4
|vpiParameter:
\_parameter: (L1_DMMU_ID), line:179
|vpiName:L1_DMMU_ID
|INT:2
|vpiParameter:
\_parameter: (L1_ICACHE_ID), line:180
|vpiName:L1_ICACHE_ID
|INT:19
|vpiParameter:
\_parameter: (L1_IMMU_ID), line:181
|vpiName:L1_IMMU_ID
|INT:0
|vpiParameter:
\_parameter: (LS_UNIT_WB_ID), line:191
|vpiName:LS_UNIT_WB_ID
|INT:1
|vpiParameter:
\_parameter: (MAX_INFLIGHT_COUNT), line:167
|vpiName:MAX_INFLIGHT_COUNT
|INT:19
|vpiParameter:
\_parameter: (MEMORY_ADDR_H), line:103
|vpiName:MEMORY_ADDR_H
|INT:12
|vpiParameter:
\_parameter: (MEMORY_ADDR_L), line:102
|vpiName:MEMORY_ADDR_L
|INT:11
|vpiParameter:
\_parameter: (MEMORY_BIT_CHECK), line:104
|vpiName:MEMORY_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (MUL_UNIT_WB_ID), line:193
|vpiName:MUL_UNIT_WB_ID
|INT:512
|vpiParameter:
\_parameter: (NUM_UNITS), line:188
|vpiName:NUM_UNITS
|INT:2
|vpiParameter:
\_parameter: (NUM_WB_UNITS), line:186
|vpiName:NUM_WB_UNITS
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (RAS_DEPTH), line:161
|vpiName:RAS_DEPTH
|INT:2
|vpiParameter:
\_parameter: (RESET_VEC), line:39
|vpiName:RESET_VEC
|INT:-2147483648
|vpiParameter:
\_parameter: (SCRATCH_ADDR_H), line:99
|vpiName:SCRATCH_ADDR_H
|INT:9
|vpiParameter:
\_parameter: (SCRATCH_ADDR_L), line:98
|vpiName:SCRATCH_ADDR_L
|INT:8
|vpiParameter:
\_parameter: (SCRATCH_BIT_CHECK), line:100
|vpiName:SCRATCH_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (USE_AMO), line:70
|vpiName:USE_AMO
|INT:1
|vpiParameter:
\_parameter: (USE_BRANCH_PREDICTOR), line:158
|vpiName:USE_BRANCH_PREDICTOR
|INT:2
|vpiParameter:
\_parameter: (USE_BUS), line:88
|vpiName:USE_BUS
|INT:4
|vpiParameter:
\_parameter: (USE_DCACHE), line:92
|vpiName:USE_DCACHE
|INT:6
|vpiParameter:
\_parameter: (USE_DIV), line:49
|vpiName:USE_DIV
|INT:1
|vpiParameter:
\_parameter: (USE_DTAG_INVALIDATIONS), line:140
|vpiName:USE_DTAG_INVALIDATIONS
|INT:1879048191
|vpiParameter:
\_parameter: (USE_D_SCRATCH_MEM), line:79
|vpiName:USE_D_SCRATCH_MEM
|INT:3
|vpiParameter:
\_parameter: (USE_ICACHE), line:93
|vpiName:USE_ICACHE
|INT:7
|vpiParameter:
\_parameter: (USE_I_SCRATCH_MEM), line:78
|vpiName:USE_I_SCRATCH_MEM
|INT:2
|vpiParameter:
\_parameter: (USE_MUL), line:48
|vpiName:USE_MUL
|INT:1
|vpiParameter:
\_parameter: (WB_UNITS_WIDTH), line:187
|vpiName:WB_UNITS_WIDTH
|INT:32
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiParameter:
\_parameter: (ALU_UNIT_WB_ID), line:190
|vpiName:ALU_UNIT_WB_ID
|INT:32
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (BRANCH_PREDICTOR_WAYS), line:159
|vpiName:BRANCH_PREDICTOR_WAYS
|INT:9
|vpiParameter:
\_parameter: (BRANCH_TABLE_ENTRIES), line:160
|vpiName:BRANCH_TABLE_ENTRIES
|INT:4
|vpiParameter:
\_parameter: (BRANCH_UNIT_ID), line:195
|vpiName:BRANCH_UNIT_ID
|INT:8
|vpiParameter:
\_parameter: (BUS_ADDR_H), line:107
|vpiName:BUS_ADDR_H
|INT:1
|vpiParameter:
\_parameter: (BUS_ADDR_L), line:106
|vpiName:BUS_ADDR_L
|INT:0
|vpiParameter:
\_parameter: (BUS_BIT_CHECK), line:108
|vpiName:BUS_BIT_CHECK
|INT:1
|vpiParameter:
\_parameter: (BUS_TYPE), line:89
|vpiName:BUS_TYPE
|INT:5
|vpiParameter:
\_parameter: (COUNTER_W), line:42
|vpiName:COUNTER_W
|INT:33
|vpiParameter:
\_parameter: (CPU_ID), line:38
|vpiName:CPU_ID
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_ADDR_WIDTH), line:113
|vpiName:C_M_AXI_ADDR_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_DATA_WIDTH), line:114
|vpiName:C_M_AXI_DATA_WIDTH
|INT:1
|vpiParameter:
\_parameter: (DCACHE_LINES), line:133
|vpiName:DCACHE_LINES
|INT:-2146435073
|vpiParameter:
\_parameter: (DCACHE_LINE_ADDR_W), line:135
|vpiName:DCACHE_LINE_ADDR_W
|INT:1073741824
|vpiParameter:
\_parameter: (DCACHE_LINE_W), line:136
|vpiName:DCACHE_LINE_W
|INT:1342177279
|vpiParameter:
\_parameter: (DCACHE_SUB_LINE_ADDR_W), line:137
|vpiName:DCACHE_SUB_LINE_ADDR_W
|INT:4
|vpiParameter:
\_parameter: (DCACHE_TAG_W), line:138
|vpiName:DCACHE_TAG_W
|INT:1610612736
|vpiParameter:
\_parameter: (DCACHE_WAYS), line:134
|vpiName:DCACHE_WAYS
|INT:4
|vpiParameter:
\_parameter: (DIV_ALGORITHM), line:67
|vpiName:DIV_ALGORITHM
|INT:0
|vpiParameter:
\_parameter: (DIV_UNIT_WB_ID), line:192
|vpiName:DIV_UNIT_WB_ID
|INT:2
|vpiParameter:
\_parameter: (DTLB_DEPTH), line:152
|vpiName:DTLB_DEPTH
|INT:512
|vpiParameter:
\_parameter: (DTLB_WAYS), line:151
|vpiName:DTLB_WAYS
|INT:32
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (ENABLE_M_MODE), line:34
|vpiName:ENABLE_M_MODE
|INT:1
|vpiParameter:
\_parameter: (ENABLE_S_MODE), line:36
|vpiName:ENABLE_S_MODE
|INT:0
|vpiParameter:
\_parameter: (ENABLE_TRACE_INTERFACE), line:172
|vpiName:ENABLE_TRACE_INTERFACE
|INT:2
|vpiParameter:
\_parameter: (FETCH_BUFFER_DEPTH), line:168
|vpiName:FETCH_BUFFER_DEPTH
|INT:512
|vpiParameter:
\_parameter: (FPGA_VENDOR), line:27
|vpiName:FPGA_VENDOR
|STRING:"xilinx"
|vpiParameter:
\_parameter: (GC_UNIT_ID), line:196
|vpiName:GC_UNIT_ID
|INT:4
|vpiParameter:
\_parameter: (ICACHE_LINES), line:121
|vpiName:ICACHE_LINES
|INT:2
|vpiParameter:
\_parameter: (ICACHE_LINE_ADDR_W), line:123
|vpiName:ICACHE_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_LINE_W), line:124
|vpiName:ICACHE_LINE_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_SUB_LINE_ADDR_W), line:125
|vpiName:ICACHE_SUB_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_TAG_W), line:126
|vpiName:ICACHE_TAG_W
|INT:-2147483648
|vpiParameter:
\_parameter: (ICACHE_WAYS), line:122
|vpiName:ICACHE_WAYS
|INT:1
|vpiParameter:
\_parameter: (ITLB_DEPTH), line:146
|vpiName:ITLB_DEPTH
|INT:32
|vpiParameter:
\_parameter: (ITLB_WAYS), line:145
|vpiName:ITLB_WAYS
|INT:4
|vpiParameter:
\_parameter: (L1_CONNECTIONS), line:177
|vpiName:L1_CONNECTIONS
|INT:9
|vpiParameter:
\_parameter: (L1_DCACHE_ID), line:178
|vpiName:L1_DCACHE_ID
|INT:4
|vpiParameter:
\_parameter: (L1_DMMU_ID), line:179
|vpiName:L1_DMMU_ID
|INT:2
|vpiParameter:
\_parameter: (L1_ICACHE_ID), line:180
|vpiName:L1_ICACHE_ID
|INT:19
|vpiParameter:
\_parameter: (L1_IMMU_ID), line:181
|vpiName:L1_IMMU_ID
|INT:0
|vpiParameter:
\_parameter: (LS_UNIT_WB_ID), line:191
|vpiName:LS_UNIT_WB_ID
|INT:1
|vpiParameter:
\_parameter: (MAX_INFLIGHT_COUNT), line:167
|vpiName:MAX_INFLIGHT_COUNT
|INT:19
|vpiParameter:
\_parameter: (MEMORY_ADDR_H), line:103
|vpiName:MEMORY_ADDR_H
|INT:12
|vpiParameter:
\_parameter: (MEMORY_ADDR_L), line:102
|vpiName:MEMORY_ADDR_L
|INT:11
|vpiParameter:
\_parameter: (MEMORY_BIT_CHECK), line:104
|vpiName:MEMORY_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (MUL_UNIT_WB_ID), line:193
|vpiName:MUL_UNIT_WB_ID
|INT:512
|vpiParameter:
\_parameter: (NUM_UNITS), line:188
|vpiName:NUM_UNITS
|INT:2
|vpiParameter:
\_parameter: (NUM_WB_UNITS), line:186
|vpiName:NUM_WB_UNITS
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (RAS_DEPTH), line:161
|vpiName:RAS_DEPTH
|INT:2
|vpiParameter:
\_parameter: (RESET_VEC), line:39
|vpiName:RESET_VEC
|INT:-2147483648
|vpiParameter:
\_parameter: (SCRATCH_ADDR_H), line:99
|vpiName:SCRATCH_ADDR_H
|INT:9
|vpiParameter:
\_parameter: (SCRATCH_ADDR_L), line:98
|vpiName:SCRATCH_ADDR_L
|INT:8
|vpiParameter:
\_parameter: (SCRATCH_BIT_CHECK), line:100
|vpiName:SCRATCH_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (USE_AMO), line:70
|vpiName:USE_AMO
|INT:1
|vpiParameter:
\_parameter: (USE_BRANCH_PREDICTOR), line:158
|vpiName:USE_BRANCH_PREDICTOR
|INT:2
|vpiParameter:
\_parameter: (USE_BUS), line:88
|vpiName:USE_BUS
|INT:4
|vpiParameter:
\_parameter: (USE_DCACHE), line:92
|vpiName:USE_DCACHE
|INT:6
|vpiParameter:
\_parameter: (USE_DIV), line:49
|vpiName:USE_DIV
|INT:1
|vpiParameter:
\_parameter: (USE_DTAG_INVALIDATIONS), line:140
|vpiName:USE_DTAG_INVALIDATIONS
|INT:1879048191
|vpiParameter:
\_parameter: (USE_D_SCRATCH_MEM), line:79
|vpiName:USE_D_SCRATCH_MEM
|INT:3
|vpiParameter:
\_parameter: (USE_ICACHE), line:93
|vpiName:USE_ICACHE
|INT:7
|vpiParameter:
\_parameter: (USE_I_SCRATCH_MEM), line:78
|vpiName:USE_I_SCRATCH_MEM
|INT:2
|vpiParameter:
\_parameter: (USE_MUL), line:48
|vpiName:USE_MUL
|INT:1
|vpiParameter:
\_parameter: (WB_UNITS_WIDTH), line:187
|vpiName:WB_UNITS_WIDTH
|INT:32
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiParameter:
\_parameter: (i), line:61
|vpiName:i
|INT:4
|vpiGenScopeArray:
\_gen_scope_array: (branch_tag_banks[5]), line:61
|vpiName:branch_tag_banks[5]
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_tag_banks.branch_tag_banks[5]
|vpiGenScope:
\_gen_scope: , parent:branch_tag_banks[5]
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_tag_banks.branch_tag_banks[5]
|vpiModule:
\_module: work@branch_predictor_ram (tag_bank), file:third_party/cores/taiga/core/branch_predictor.sv, line:62
|vpiDefName:work@branch_predictor_ram
|vpiName:tag_bank
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_tag_banks.branch_tag_banks[5].tag_bank
|vpiPort:
\_port: (clk), line:32, parent:tag_bank
|vpiName:clk
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (clk), line:63
|vpiName:clk
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (clk), line:32, parent:tag_bank
|vpiName:clk
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_tag_banks.branch_tag_banks[5].tag_bank.clk
|vpiNetType:36
|vpiPort:
\_port: (write_addr), line:33, parent:tag_bank
|vpiName:write_addr
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (write_addr), line:63
|vpiName:write_addr
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (write_addr), line:33, parent:tag_bank
|vpiName:write_addr
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_tag_banks.branch_tag_banks[5].tag_bank.write_addr
|vpiNetType:36
|vpiRange:
\_range: , line:33
|vpiLeftRange:
\_constant: , line:33
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:33
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiPort:
\_port: (write_en), line:34, parent:tag_bank
|vpiName:write_en
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (write_en), line:63
|vpiName:write_en
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (write_en), line:34, parent:tag_bank
|vpiName:write_en
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_tag_banks.branch_tag_banks[5].tag_bank.write_en
|vpiNetType:36
|vpiPort:
\_port: (read_addr), line:35, parent:tag_bank
|vpiName:read_addr
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (read_addr), line:63
|vpiName:read_addr
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (read_addr), line:35, parent:tag_bank
|vpiName:read_addr
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_tag_banks.branch_tag_banks[5].tag_bank.read_addr
|vpiNetType:36
|vpiRange:
\_range: , line:35
|vpiLeftRange:
\_constant: , line:35
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:35
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiPort:
\_port: (read_en), line:36, parent:tag_bank
|vpiName:read_en
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (read_en), line:63
|vpiName:read_en
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (read_en), line:36, parent:tag_bank
|vpiName:read_en
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_tag_banks.branch_tag_banks[5].tag_bank.read_en
|vpiNetType:36
|vpiPort:
\_port: (write_data), line:37, parent:tag_bank
|vpiName:write_data
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (write_data), line:63
|vpiName:write_data
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (write_data), line:37, parent:tag_bank
|vpiName:write_data
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_tag_banks.branch_tag_banks[5].tag_bank.write_data
|vpiNetType:36
|vpiRange:
\_range: , line:37
|vpiLeftRange:
\_constant: , line:37
|vpiDecompile:-1
|INT:-1
|vpiRightRange:
\_constant: , line:37
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiPort:
\_port: (read_data), line:38, parent:tag_bank
|vpiName:read_data
|vpiDirection:2
|vpiHighConn:
\_ref_obj: (read_data), line:63
|vpiName:read_data
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (read_data), line:38, parent:tag_bank
|vpiName:read_data
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_tag_banks.branch_tag_banks[5].tag_bank.read_data
|vpiNetType:36
|vpiRange:
\_range: , line:38
|vpiLeftRange:
\_constant: , line:38
|vpiDecompile:-1
|INT:-1
|vpiRightRange:
\_constant: , line:38
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (clk), line:32, parent:tag_bank
|vpiNet:
\_logic_net: (write_addr), line:33, parent:tag_bank
|vpiNet:
\_logic_net: (write_en), line:34, parent:tag_bank
|vpiNet:
\_logic_net: (read_addr), line:35, parent:tag_bank
|vpiNet:
\_logic_net: (read_en), line:36, parent:tag_bank
|vpiNet:
\_logic_net: (write_data), line:37, parent:tag_bank
|vpiNet:
\_logic_net: (read_data), line:38, parent:tag_bank
|vpiArrayNet:
\_array_net: (branch_ram), line:40, parent:tag_bank
|vpiName:branch_ram
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_tag_banks.branch_tag_banks[5].tag_bank.branch_ram
|vpiSize:4
|vpiNet:
\_logic_net: , parent:branch_ram
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_tag_banks.branch_tag_banks[5].tag_bank.branch_ram
|vpiNetType:36
|vpiRange:
\_range: , line:40
|vpiLeftRange:
\_constant: , line:40
|vpiDecompile:-1
|INT:-1
|vpiRightRange:
\_constant: , line:40
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiRange:
\_range: , line:40
|vpiLeftRange:
\_constant: , line:40
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiRightRange:
\_constant: , line:40
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiParameter:
\_parameter: (ALU_UNIT_WB_ID), line:190
|vpiName:ALU_UNIT_WB_ID
|INT:32
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (BRANCH_PREDICTOR_WAYS), line:159
|vpiName:BRANCH_PREDICTOR_WAYS
|INT:9
|vpiParameter:
\_parameter: (BRANCH_TABLE_ENTRIES), line:160
|vpiName:BRANCH_TABLE_ENTRIES
|INT:4
|vpiParameter:
\_parameter: (BRANCH_UNIT_ID), line:195
|vpiName:BRANCH_UNIT_ID
|INT:8
|vpiParameter:
\_parameter: (BUS_ADDR_H), line:107
|vpiName:BUS_ADDR_H
|INT:1
|vpiParameter:
\_parameter: (BUS_ADDR_L), line:106
|vpiName:BUS_ADDR_L
|INT:0
|vpiParameter:
\_parameter: (BUS_BIT_CHECK), line:108
|vpiName:BUS_BIT_CHECK
|INT:1
|vpiParameter:
\_parameter: (BUS_TYPE), line:89
|vpiName:BUS_TYPE
|INT:5
|vpiParameter:
\_parameter: (COUNTER_W), line:42
|vpiName:COUNTER_W
|INT:33
|vpiParameter:
\_parameter: (CPU_ID), line:38
|vpiName:CPU_ID
|INT:0
|vpiParameter:
\_parameter: (C_DATA_WIDTH), line:62
|vpiName:C_DATA_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_DEPTH), line:62
|vpiName:C_DEPTH
|INT:4
|vpiParameter:
\_parameter: (C_M_AXI_ADDR_WIDTH), line:113
|vpiName:C_M_AXI_ADDR_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_DATA_WIDTH), line:114
|vpiName:C_M_AXI_DATA_WIDTH
|INT:1
|vpiParameter:
\_parameter: (DCACHE_LINES), line:133
|vpiName:DCACHE_LINES
|INT:-2146435073
|vpiParameter:
\_parameter: (DCACHE_LINE_ADDR_W), line:135
|vpiName:DCACHE_LINE_ADDR_W
|INT:1073741824
|vpiParameter:
\_parameter: (DCACHE_LINE_W), line:136
|vpiName:DCACHE_LINE_W
|INT:1342177279
|vpiParameter:
\_parameter: (DCACHE_SUB_LINE_ADDR_W), line:137
|vpiName:DCACHE_SUB_LINE_ADDR_W
|INT:4
|vpiParameter:
\_parameter: (DCACHE_TAG_W), line:138
|vpiName:DCACHE_TAG_W
|INT:1610612736
|vpiParameter:
\_parameter: (DCACHE_WAYS), line:134
|vpiName:DCACHE_WAYS
|INT:4
|vpiParameter:
\_parameter: (DIV_ALGORITHM), line:67
|vpiName:DIV_ALGORITHM
|INT:0
|vpiParameter:
\_parameter: (DIV_UNIT_WB_ID), line:192
|vpiName:DIV_UNIT_WB_ID
|INT:2
|vpiParameter:
\_parameter: (DTLB_DEPTH), line:152
|vpiName:DTLB_DEPTH
|INT:512
|vpiParameter:
\_parameter: (DTLB_WAYS), line:151
|vpiName:DTLB_WAYS
|INT:32
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (ENABLE_M_MODE), line:34
|vpiName:ENABLE_M_MODE
|INT:1
|vpiParameter:
\_parameter: (ENABLE_S_MODE), line:36
|vpiName:ENABLE_S_MODE
|INT:0
|vpiParameter:
\_parameter: (ENABLE_TRACE_INTERFACE), line:172
|vpiName:ENABLE_TRACE_INTERFACE
|INT:2
|vpiParameter:
\_parameter: (FETCH_BUFFER_DEPTH), line:168
|vpiName:FETCH_BUFFER_DEPTH
|INT:512
|vpiParameter:
\_parameter: (FPGA_VENDOR), line:27
|vpiName:FPGA_VENDOR
|STRING:"xilinx"
|vpiParameter:
\_parameter: (GC_UNIT_ID), line:196
|vpiName:GC_UNIT_ID
|INT:4
|vpiParameter:
\_parameter: (ICACHE_LINES), line:121
|vpiName:ICACHE_LINES
|INT:2
|vpiParameter:
\_parameter: (ICACHE_LINE_ADDR_W), line:123
|vpiName:ICACHE_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_LINE_W), line:124
|vpiName:ICACHE_LINE_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_SUB_LINE_ADDR_W), line:125
|vpiName:ICACHE_SUB_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_TAG_W), line:126
|vpiName:ICACHE_TAG_W
|INT:-2147483648
|vpiParameter:
\_parameter: (ICACHE_WAYS), line:122
|vpiName:ICACHE_WAYS
|INT:1
|vpiParameter:
\_parameter: (ITLB_DEPTH), line:146
|vpiName:ITLB_DEPTH
|INT:32
|vpiParameter:
\_parameter: (ITLB_WAYS), line:145
|vpiName:ITLB_WAYS
|INT:4
|vpiParameter:
\_parameter: (L1_CONNECTIONS), line:177
|vpiName:L1_CONNECTIONS
|INT:9
|vpiParameter:
\_parameter: (L1_DCACHE_ID), line:178
|vpiName:L1_DCACHE_ID
|INT:4
|vpiParameter:
\_parameter: (L1_DMMU_ID), line:179
|vpiName:L1_DMMU_ID
|INT:2
|vpiParameter:
\_parameter: (L1_ICACHE_ID), line:180
|vpiName:L1_ICACHE_ID
|INT:19
|vpiParameter:
\_parameter: (L1_IMMU_ID), line:181
|vpiName:L1_IMMU_ID
|INT:0
|vpiParameter:
\_parameter: (LS_UNIT_WB_ID), line:191
|vpiName:LS_UNIT_WB_ID
|INT:1
|vpiParameter:
\_parameter: (MAX_INFLIGHT_COUNT), line:167
|vpiName:MAX_INFLIGHT_COUNT
|INT:19
|vpiParameter:
\_parameter: (MEMORY_ADDR_H), line:103
|vpiName:MEMORY_ADDR_H
|INT:12
|vpiParameter:
\_parameter: (MEMORY_ADDR_L), line:102
|vpiName:MEMORY_ADDR_L
|INT:11
|vpiParameter:
\_parameter: (MEMORY_BIT_CHECK), line:104
|vpiName:MEMORY_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (MUL_UNIT_WB_ID), line:193
|vpiName:MUL_UNIT_WB_ID
|INT:512
|vpiParameter:
\_parameter: (NUM_UNITS), line:188
|vpiName:NUM_UNITS
|INT:2
|vpiParameter:
\_parameter: (NUM_WB_UNITS), line:186
|vpiName:NUM_WB_UNITS
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (RAS_DEPTH), line:161
|vpiName:RAS_DEPTH
|INT:2
|vpiParameter:
\_parameter: (RESET_VEC), line:39
|vpiName:RESET_VEC
|INT:-2147483648
|vpiParameter:
\_parameter: (SCRATCH_ADDR_H), line:99
|vpiName:SCRATCH_ADDR_H
|INT:9
|vpiParameter:
\_parameter: (SCRATCH_ADDR_L), line:98
|vpiName:SCRATCH_ADDR_L
|INT:8
|vpiParameter:
\_parameter: (SCRATCH_BIT_CHECK), line:100
|vpiName:SCRATCH_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (USE_AMO), line:70
|vpiName:USE_AMO
|INT:1
|vpiParameter:
\_parameter: (USE_BRANCH_PREDICTOR), line:158
|vpiName:USE_BRANCH_PREDICTOR
|INT:2
|vpiParameter:
\_parameter: (USE_BUS), line:88
|vpiName:USE_BUS
|INT:4
|vpiParameter:
\_parameter: (USE_DCACHE), line:92
|vpiName:USE_DCACHE
|INT:6
|vpiParameter:
\_parameter: (USE_DIV), line:49
|vpiName:USE_DIV
|INT:1
|vpiParameter:
\_parameter: (USE_DTAG_INVALIDATIONS), line:140
|vpiName:USE_DTAG_INVALIDATIONS
|INT:1879048191
|vpiParameter:
\_parameter: (USE_D_SCRATCH_MEM), line:79
|vpiName:USE_D_SCRATCH_MEM
|INT:3
|vpiParameter:
\_parameter: (USE_ICACHE), line:93
|vpiName:USE_ICACHE
|INT:7
|vpiParameter:
\_parameter: (USE_I_SCRATCH_MEM), line:78
|vpiName:USE_I_SCRATCH_MEM
|INT:2
|vpiParameter:
\_parameter: (USE_MUL), line:48
|vpiName:USE_MUL
|INT:1
|vpiParameter:
\_parameter: (WB_UNITS_WIDTH), line:187
|vpiName:WB_UNITS_WIDTH
|INT:32
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiParameter:
\_parameter: (ALU_UNIT_WB_ID), line:190
|vpiName:ALU_UNIT_WB_ID
|INT:32
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (BRANCH_PREDICTOR_WAYS), line:159
|vpiName:BRANCH_PREDICTOR_WAYS
|INT:9
|vpiParameter:
\_parameter: (BRANCH_TABLE_ENTRIES), line:160
|vpiName:BRANCH_TABLE_ENTRIES
|INT:4
|vpiParameter:
\_parameter: (BRANCH_UNIT_ID), line:195
|vpiName:BRANCH_UNIT_ID
|INT:8
|vpiParameter:
\_parameter: (BUS_ADDR_H), line:107
|vpiName:BUS_ADDR_H
|INT:1
|vpiParameter:
\_parameter: (BUS_ADDR_L), line:106
|vpiName:BUS_ADDR_L
|INT:0
|vpiParameter:
\_parameter: (BUS_BIT_CHECK), line:108
|vpiName:BUS_BIT_CHECK
|INT:1
|vpiParameter:
\_parameter: (BUS_TYPE), line:89
|vpiName:BUS_TYPE
|INT:5
|vpiParameter:
\_parameter: (COUNTER_W), line:42
|vpiName:COUNTER_W
|INT:33
|vpiParameter:
\_parameter: (CPU_ID), line:38
|vpiName:CPU_ID
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_ADDR_WIDTH), line:113
|vpiName:C_M_AXI_ADDR_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_DATA_WIDTH), line:114
|vpiName:C_M_AXI_DATA_WIDTH
|INT:1
|vpiParameter:
\_parameter: (DCACHE_LINES), line:133
|vpiName:DCACHE_LINES
|INT:-2146435073
|vpiParameter:
\_parameter: (DCACHE_LINE_ADDR_W), line:135
|vpiName:DCACHE_LINE_ADDR_W
|INT:1073741824
|vpiParameter:
\_parameter: (DCACHE_LINE_W), line:136
|vpiName:DCACHE_LINE_W
|INT:1342177279
|vpiParameter:
\_parameter: (DCACHE_SUB_LINE_ADDR_W), line:137
|vpiName:DCACHE_SUB_LINE_ADDR_W
|INT:4
|vpiParameter:
\_parameter: (DCACHE_TAG_W), line:138
|vpiName:DCACHE_TAG_W
|INT:1610612736
|vpiParameter:
\_parameter: (DCACHE_WAYS), line:134
|vpiName:DCACHE_WAYS
|INT:4
|vpiParameter:
\_parameter: (DIV_ALGORITHM), line:67
|vpiName:DIV_ALGORITHM
|INT:0
|vpiParameter:
\_parameter: (DIV_UNIT_WB_ID), line:192
|vpiName:DIV_UNIT_WB_ID
|INT:2
|vpiParameter:
\_parameter: (DTLB_DEPTH), line:152
|vpiName:DTLB_DEPTH
|INT:512
|vpiParameter:
\_parameter: (DTLB_WAYS), line:151
|vpiName:DTLB_WAYS
|INT:32
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (ENABLE_M_MODE), line:34
|vpiName:ENABLE_M_MODE
|INT:1
|vpiParameter:
\_parameter: (ENABLE_S_MODE), line:36
|vpiName:ENABLE_S_MODE
|INT:0
|vpiParameter:
\_parameter: (ENABLE_TRACE_INTERFACE), line:172
|vpiName:ENABLE_TRACE_INTERFACE
|INT:2
|vpiParameter:
\_parameter: (FETCH_BUFFER_DEPTH), line:168
|vpiName:FETCH_BUFFER_DEPTH
|INT:512
|vpiParameter:
\_parameter: (FPGA_VENDOR), line:27
|vpiName:FPGA_VENDOR
|STRING:"xilinx"
|vpiParameter:
\_parameter: (GC_UNIT_ID), line:196
|vpiName:GC_UNIT_ID
|INT:4
|vpiParameter:
\_parameter: (ICACHE_LINES), line:121
|vpiName:ICACHE_LINES
|INT:2
|vpiParameter:
\_parameter: (ICACHE_LINE_ADDR_W), line:123
|vpiName:ICACHE_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_LINE_W), line:124
|vpiName:ICACHE_LINE_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_SUB_LINE_ADDR_W), line:125
|vpiName:ICACHE_SUB_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_TAG_W), line:126
|vpiName:ICACHE_TAG_W
|INT:-2147483648
|vpiParameter:
\_parameter: (ICACHE_WAYS), line:122
|vpiName:ICACHE_WAYS
|INT:1
|vpiParameter:
\_parameter: (ITLB_DEPTH), line:146
|vpiName:ITLB_DEPTH
|INT:32
|vpiParameter:
\_parameter: (ITLB_WAYS), line:145
|vpiName:ITLB_WAYS
|INT:4
|vpiParameter:
\_parameter: (L1_CONNECTIONS), line:177
|vpiName:L1_CONNECTIONS
|INT:9
|vpiParameter:
\_parameter: (L1_DCACHE_ID), line:178
|vpiName:L1_DCACHE_ID
|INT:4
|vpiParameter:
\_parameter: (L1_DMMU_ID), line:179
|vpiName:L1_DMMU_ID
|INT:2
|vpiParameter:
\_parameter: (L1_ICACHE_ID), line:180
|vpiName:L1_ICACHE_ID
|INT:19
|vpiParameter:
\_parameter: (L1_IMMU_ID), line:181
|vpiName:L1_IMMU_ID
|INT:0
|vpiParameter:
\_parameter: (LS_UNIT_WB_ID), line:191
|vpiName:LS_UNIT_WB_ID
|INT:1
|vpiParameter:
\_parameter: (MAX_INFLIGHT_COUNT), line:167
|vpiName:MAX_INFLIGHT_COUNT
|INT:19
|vpiParameter:
\_parameter: (MEMORY_ADDR_H), line:103
|vpiName:MEMORY_ADDR_H
|INT:12
|vpiParameter:
\_parameter: (MEMORY_ADDR_L), line:102
|vpiName:MEMORY_ADDR_L
|INT:11
|vpiParameter:
\_parameter: (MEMORY_BIT_CHECK), line:104
|vpiName:MEMORY_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (MUL_UNIT_WB_ID), line:193
|vpiName:MUL_UNIT_WB_ID
|INT:512
|vpiParameter:
\_parameter: (NUM_UNITS), line:188
|vpiName:NUM_UNITS
|INT:2
|vpiParameter:
\_parameter: (NUM_WB_UNITS), line:186
|vpiName:NUM_WB_UNITS
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (RAS_DEPTH), line:161
|vpiName:RAS_DEPTH
|INT:2
|vpiParameter:
\_parameter: (RESET_VEC), line:39
|vpiName:RESET_VEC
|INT:-2147483648
|vpiParameter:
\_parameter: (SCRATCH_ADDR_H), line:99
|vpiName:SCRATCH_ADDR_H
|INT:9
|vpiParameter:
\_parameter: (SCRATCH_ADDR_L), line:98
|vpiName:SCRATCH_ADDR_L
|INT:8
|vpiParameter:
\_parameter: (SCRATCH_BIT_CHECK), line:100
|vpiName:SCRATCH_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (USE_AMO), line:70
|vpiName:USE_AMO
|INT:1
|vpiParameter:
\_parameter: (USE_BRANCH_PREDICTOR), line:158
|vpiName:USE_BRANCH_PREDICTOR
|INT:2
|vpiParameter:
\_parameter: (USE_BUS), line:88
|vpiName:USE_BUS
|INT:4
|vpiParameter:
\_parameter: (USE_DCACHE), line:92
|vpiName:USE_DCACHE
|INT:6
|vpiParameter:
\_parameter: (USE_DIV), line:49
|vpiName:USE_DIV
|INT:1
|vpiParameter:
\_parameter: (USE_DTAG_INVALIDATIONS), line:140
|vpiName:USE_DTAG_INVALIDATIONS
|INT:1879048191
|vpiParameter:
\_parameter: (USE_D_SCRATCH_MEM), line:79
|vpiName:USE_D_SCRATCH_MEM
|INT:3
|vpiParameter:
\_parameter: (USE_ICACHE), line:93
|vpiName:USE_ICACHE
|INT:7
|vpiParameter:
\_parameter: (USE_I_SCRATCH_MEM), line:78
|vpiName:USE_I_SCRATCH_MEM
|INT:2
|vpiParameter:
\_parameter: (USE_MUL), line:48
|vpiName:USE_MUL
|INT:1
|vpiParameter:
\_parameter: (WB_UNITS_WIDTH), line:187
|vpiName:WB_UNITS_WIDTH
|INT:32
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiParameter:
\_parameter: (i), line:61
|vpiName:i
|INT:5
|vpiGenScopeArray:
\_gen_scope_array: (branch_tag_banks[6]), line:61
|vpiName:branch_tag_banks[6]
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_tag_banks.branch_tag_banks[6]
|vpiGenScope:
\_gen_scope: , parent:branch_tag_banks[6]
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_tag_banks.branch_tag_banks[6]
|vpiModule:
\_module: work@branch_predictor_ram (tag_bank), file:third_party/cores/taiga/core/branch_predictor.sv, line:62
|vpiDefName:work@branch_predictor_ram
|vpiName:tag_bank
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_tag_banks.branch_tag_banks[6].tag_bank
|vpiPort:
\_port: (clk), line:32, parent:tag_bank
|vpiName:clk
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (clk), line:63
|vpiName:clk
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (clk), line:32, parent:tag_bank
|vpiName:clk
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_tag_banks.branch_tag_banks[6].tag_bank.clk
|vpiNetType:36
|vpiPort:
\_port: (write_addr), line:33, parent:tag_bank
|vpiName:write_addr
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (write_addr), line:63
|vpiName:write_addr
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (write_addr), line:33, parent:tag_bank
|vpiName:write_addr
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_tag_banks.branch_tag_banks[6].tag_bank.write_addr
|vpiNetType:36
|vpiRange:
\_range: , line:33
|vpiLeftRange:
\_constant: , line:33
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:33
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiPort:
\_port: (write_en), line:34, parent:tag_bank
|vpiName:write_en
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (write_en), line:63
|vpiName:write_en
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (write_en), line:34, parent:tag_bank
|vpiName:write_en
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_tag_banks.branch_tag_banks[6].tag_bank.write_en
|vpiNetType:36
|vpiPort:
\_port: (read_addr), line:35, parent:tag_bank
|vpiName:read_addr
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (read_addr), line:63
|vpiName:read_addr
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (read_addr), line:35, parent:tag_bank
|vpiName:read_addr
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_tag_banks.branch_tag_banks[6].tag_bank.read_addr
|vpiNetType:36
|vpiRange:
\_range: , line:35
|vpiLeftRange:
\_constant: , line:35
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:35
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiPort:
\_port: (read_en), line:36, parent:tag_bank
|vpiName:read_en
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (read_en), line:63
|vpiName:read_en
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (read_en), line:36, parent:tag_bank
|vpiName:read_en
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_tag_banks.branch_tag_banks[6].tag_bank.read_en
|vpiNetType:36
|vpiPort:
\_port: (write_data), line:37, parent:tag_bank
|vpiName:write_data
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (write_data), line:63
|vpiName:write_data
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (write_data), line:37, parent:tag_bank
|vpiName:write_data
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_tag_banks.branch_tag_banks[6].tag_bank.write_data
|vpiNetType:36
|vpiRange:
\_range: , line:37
|vpiLeftRange:
\_constant: , line:37
|vpiDecompile:-1
|INT:-1
|vpiRightRange:
\_constant: , line:37
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiPort:
\_port: (read_data), line:38, parent:tag_bank
|vpiName:read_data
|vpiDirection:2
|vpiHighConn:
\_ref_obj: (read_data), line:63
|vpiName:read_data
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (read_data), line:38, parent:tag_bank
|vpiName:read_data
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_tag_banks.branch_tag_banks[6].tag_bank.read_data
|vpiNetType:36
|vpiRange:
\_range: , line:38
|vpiLeftRange:
\_constant: , line:38
|vpiDecompile:-1
|INT:-1
|vpiRightRange:
\_constant: , line:38
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (clk), line:32, parent:tag_bank
|vpiNet:
\_logic_net: (write_addr), line:33, parent:tag_bank
|vpiNet:
\_logic_net: (write_en), line:34, parent:tag_bank
|vpiNet:
\_logic_net: (read_addr), line:35, parent:tag_bank
|vpiNet:
\_logic_net: (read_en), line:36, parent:tag_bank
|vpiNet:
\_logic_net: (write_data), line:37, parent:tag_bank
|vpiNet:
\_logic_net: (read_data), line:38, parent:tag_bank
|vpiArrayNet:
\_array_net: (branch_ram), line:40, parent:tag_bank
|vpiName:branch_ram
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_tag_banks.branch_tag_banks[6].tag_bank.branch_ram
|vpiSize:4
|vpiNet:
\_logic_net: , parent:branch_ram
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_tag_banks.branch_tag_banks[6].tag_bank.branch_ram
|vpiNetType:36
|vpiRange:
\_range: , line:40
|vpiLeftRange:
\_constant: , line:40
|vpiDecompile:-1
|INT:-1
|vpiRightRange:
\_constant: , line:40
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiRange:
\_range: , line:40
|vpiLeftRange:
\_constant: , line:40
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiRightRange:
\_constant: , line:40
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiParameter:
\_parameter: (ALU_UNIT_WB_ID), line:190
|vpiName:ALU_UNIT_WB_ID
|INT:32
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (BRANCH_PREDICTOR_WAYS), line:159
|vpiName:BRANCH_PREDICTOR_WAYS
|INT:9
|vpiParameter:
\_parameter: (BRANCH_TABLE_ENTRIES), line:160
|vpiName:BRANCH_TABLE_ENTRIES
|INT:4
|vpiParameter:
\_parameter: (BRANCH_UNIT_ID), line:195
|vpiName:BRANCH_UNIT_ID
|INT:8
|vpiParameter:
\_parameter: (BUS_ADDR_H), line:107
|vpiName:BUS_ADDR_H
|INT:1
|vpiParameter:
\_parameter: (BUS_ADDR_L), line:106
|vpiName:BUS_ADDR_L
|INT:0
|vpiParameter:
\_parameter: (BUS_BIT_CHECK), line:108
|vpiName:BUS_BIT_CHECK
|INT:1
|vpiParameter:
\_parameter: (BUS_TYPE), line:89
|vpiName:BUS_TYPE
|INT:5
|vpiParameter:
\_parameter: (COUNTER_W), line:42
|vpiName:COUNTER_W
|INT:33
|vpiParameter:
\_parameter: (CPU_ID), line:38
|vpiName:CPU_ID
|INT:0
|vpiParameter:
\_parameter: (C_DATA_WIDTH), line:62
|vpiName:C_DATA_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_DEPTH), line:62
|vpiName:C_DEPTH
|INT:4
|vpiParameter:
\_parameter: (C_M_AXI_ADDR_WIDTH), line:113
|vpiName:C_M_AXI_ADDR_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_DATA_WIDTH), line:114
|vpiName:C_M_AXI_DATA_WIDTH
|INT:1
|vpiParameter:
\_parameter: (DCACHE_LINES), line:133
|vpiName:DCACHE_LINES
|INT:-2146435073
|vpiParameter:
\_parameter: (DCACHE_LINE_ADDR_W), line:135
|vpiName:DCACHE_LINE_ADDR_W
|INT:1073741824
|vpiParameter:
\_parameter: (DCACHE_LINE_W), line:136
|vpiName:DCACHE_LINE_W
|INT:1342177279
|vpiParameter:
\_parameter: (DCACHE_SUB_LINE_ADDR_W), line:137
|vpiName:DCACHE_SUB_LINE_ADDR_W
|INT:4
|vpiParameter:
\_parameter: (DCACHE_TAG_W), line:138
|vpiName:DCACHE_TAG_W
|INT:1610612736
|vpiParameter:
\_parameter: (DCACHE_WAYS), line:134
|vpiName:DCACHE_WAYS
|INT:4
|vpiParameter:
\_parameter: (DIV_ALGORITHM), line:67
|vpiName:DIV_ALGORITHM
|INT:0
|vpiParameter:
\_parameter: (DIV_UNIT_WB_ID), line:192
|vpiName:DIV_UNIT_WB_ID
|INT:2
|vpiParameter:
\_parameter: (DTLB_DEPTH), line:152
|vpiName:DTLB_DEPTH
|INT:512
|vpiParameter:
\_parameter: (DTLB_WAYS), line:151
|vpiName:DTLB_WAYS
|INT:32
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (ENABLE_M_MODE), line:34
|vpiName:ENABLE_M_MODE
|INT:1
|vpiParameter:
\_parameter: (ENABLE_S_MODE), line:36
|vpiName:ENABLE_S_MODE
|INT:0
|vpiParameter:
\_parameter: (ENABLE_TRACE_INTERFACE), line:172
|vpiName:ENABLE_TRACE_INTERFACE
|INT:2
|vpiParameter:
\_parameter: (FETCH_BUFFER_DEPTH), line:168
|vpiName:FETCH_BUFFER_DEPTH
|INT:512
|vpiParameter:
\_parameter: (FPGA_VENDOR), line:27
|vpiName:FPGA_VENDOR
|STRING:"xilinx"
|vpiParameter:
\_parameter: (GC_UNIT_ID), line:196
|vpiName:GC_UNIT_ID
|INT:4
|vpiParameter:
\_parameter: (ICACHE_LINES), line:121
|vpiName:ICACHE_LINES
|INT:2
|vpiParameter:
\_parameter: (ICACHE_LINE_ADDR_W), line:123
|vpiName:ICACHE_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_LINE_W), line:124
|vpiName:ICACHE_LINE_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_SUB_LINE_ADDR_W), line:125
|vpiName:ICACHE_SUB_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_TAG_W), line:126
|vpiName:ICACHE_TAG_W
|INT:-2147483648
|vpiParameter:
\_parameter: (ICACHE_WAYS), line:122
|vpiName:ICACHE_WAYS
|INT:1
|vpiParameter:
\_parameter: (ITLB_DEPTH), line:146
|vpiName:ITLB_DEPTH
|INT:32
|vpiParameter:
\_parameter: (ITLB_WAYS), line:145
|vpiName:ITLB_WAYS
|INT:4
|vpiParameter:
\_parameter: (L1_CONNECTIONS), line:177
|vpiName:L1_CONNECTIONS
|INT:9
|vpiParameter:
\_parameter: (L1_DCACHE_ID), line:178
|vpiName:L1_DCACHE_ID
|INT:4
|vpiParameter:
\_parameter: (L1_DMMU_ID), line:179
|vpiName:L1_DMMU_ID
|INT:2
|vpiParameter:
\_parameter: (L1_ICACHE_ID), line:180
|vpiName:L1_ICACHE_ID
|INT:19
|vpiParameter:
\_parameter: (L1_IMMU_ID), line:181
|vpiName:L1_IMMU_ID
|INT:0
|vpiParameter:
\_parameter: (LS_UNIT_WB_ID), line:191
|vpiName:LS_UNIT_WB_ID
|INT:1
|vpiParameter:
\_parameter: (MAX_INFLIGHT_COUNT), line:167
|vpiName:MAX_INFLIGHT_COUNT
|INT:19
|vpiParameter:
\_parameter: (MEMORY_ADDR_H), line:103
|vpiName:MEMORY_ADDR_H
|INT:12
|vpiParameter:
\_parameter: (MEMORY_ADDR_L), line:102
|vpiName:MEMORY_ADDR_L
|INT:11
|vpiParameter:
\_parameter: (MEMORY_BIT_CHECK), line:104
|vpiName:MEMORY_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (MUL_UNIT_WB_ID), line:193
|vpiName:MUL_UNIT_WB_ID
|INT:512
|vpiParameter:
\_parameter: (NUM_UNITS), line:188
|vpiName:NUM_UNITS
|INT:2
|vpiParameter:
\_parameter: (NUM_WB_UNITS), line:186
|vpiName:NUM_WB_UNITS
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (RAS_DEPTH), line:161
|vpiName:RAS_DEPTH
|INT:2
|vpiParameter:
\_parameter: (RESET_VEC), line:39
|vpiName:RESET_VEC
|INT:-2147483648
|vpiParameter:
\_parameter: (SCRATCH_ADDR_H), line:99
|vpiName:SCRATCH_ADDR_H
|INT:9
|vpiParameter:
\_parameter: (SCRATCH_ADDR_L), line:98
|vpiName:SCRATCH_ADDR_L
|INT:8
|vpiParameter:
\_parameter: (SCRATCH_BIT_CHECK), line:100
|vpiName:SCRATCH_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (USE_AMO), line:70
|vpiName:USE_AMO
|INT:1
|vpiParameter:
\_parameter: (USE_BRANCH_PREDICTOR), line:158
|vpiName:USE_BRANCH_PREDICTOR
|INT:2
|vpiParameter:
\_parameter: (USE_BUS), line:88
|vpiName:USE_BUS
|INT:4
|vpiParameter:
\_parameter: (USE_DCACHE), line:92
|vpiName:USE_DCACHE
|INT:6
|vpiParameter:
\_parameter: (USE_DIV), line:49
|vpiName:USE_DIV
|INT:1
|vpiParameter:
\_parameter: (USE_DTAG_INVALIDATIONS), line:140
|vpiName:USE_DTAG_INVALIDATIONS
|INT:1879048191
|vpiParameter:
\_parameter: (USE_D_SCRATCH_MEM), line:79
|vpiName:USE_D_SCRATCH_MEM
|INT:3
|vpiParameter:
\_parameter: (USE_ICACHE), line:93
|vpiName:USE_ICACHE
|INT:7
|vpiParameter:
\_parameter: (USE_I_SCRATCH_MEM), line:78
|vpiName:USE_I_SCRATCH_MEM
|INT:2
|vpiParameter:
\_parameter: (USE_MUL), line:48
|vpiName:USE_MUL
|INT:1
|vpiParameter:
\_parameter: (WB_UNITS_WIDTH), line:187
|vpiName:WB_UNITS_WIDTH
|INT:32
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiParameter:
\_parameter: (ALU_UNIT_WB_ID), line:190
|vpiName:ALU_UNIT_WB_ID
|INT:32
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (BRANCH_PREDICTOR_WAYS), line:159
|vpiName:BRANCH_PREDICTOR_WAYS
|INT:9
|vpiParameter:
\_parameter: (BRANCH_TABLE_ENTRIES), line:160
|vpiName:BRANCH_TABLE_ENTRIES
|INT:4
|vpiParameter:
\_parameter: (BRANCH_UNIT_ID), line:195
|vpiName:BRANCH_UNIT_ID
|INT:8
|vpiParameter:
\_parameter: (BUS_ADDR_H), line:107
|vpiName:BUS_ADDR_H
|INT:1
|vpiParameter:
\_parameter: (BUS_ADDR_L), line:106
|vpiName:BUS_ADDR_L
|INT:0
|vpiParameter:
\_parameter: (BUS_BIT_CHECK), line:108
|vpiName:BUS_BIT_CHECK
|INT:1
|vpiParameter:
\_parameter: (BUS_TYPE), line:89
|vpiName:BUS_TYPE
|INT:5
|vpiParameter:
\_parameter: (COUNTER_W), line:42
|vpiName:COUNTER_W
|INT:33
|vpiParameter:
\_parameter: (CPU_ID), line:38
|vpiName:CPU_ID
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_ADDR_WIDTH), line:113
|vpiName:C_M_AXI_ADDR_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_DATA_WIDTH), line:114
|vpiName:C_M_AXI_DATA_WIDTH
|INT:1
|vpiParameter:
\_parameter: (DCACHE_LINES), line:133
|vpiName:DCACHE_LINES
|INT:-2146435073
|vpiParameter:
\_parameter: (DCACHE_LINE_ADDR_W), line:135
|vpiName:DCACHE_LINE_ADDR_W
|INT:1073741824
|vpiParameter:
\_parameter: (DCACHE_LINE_W), line:136
|vpiName:DCACHE_LINE_W
|INT:1342177279
|vpiParameter:
\_parameter: (DCACHE_SUB_LINE_ADDR_W), line:137
|vpiName:DCACHE_SUB_LINE_ADDR_W
|INT:4
|vpiParameter:
\_parameter: (DCACHE_TAG_W), line:138
|vpiName:DCACHE_TAG_W
|INT:1610612736
|vpiParameter:
\_parameter: (DCACHE_WAYS), line:134
|vpiName:DCACHE_WAYS
|INT:4
|vpiParameter:
\_parameter: (DIV_ALGORITHM), line:67
|vpiName:DIV_ALGORITHM
|INT:0
|vpiParameter:
\_parameter: (DIV_UNIT_WB_ID), line:192
|vpiName:DIV_UNIT_WB_ID
|INT:2
|vpiParameter:
\_parameter: (DTLB_DEPTH), line:152
|vpiName:DTLB_DEPTH
|INT:512
|vpiParameter:
\_parameter: (DTLB_WAYS), line:151
|vpiName:DTLB_WAYS
|INT:32
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (ENABLE_M_MODE), line:34
|vpiName:ENABLE_M_MODE
|INT:1
|vpiParameter:
\_parameter: (ENABLE_S_MODE), line:36
|vpiName:ENABLE_S_MODE
|INT:0
|vpiParameter:
\_parameter: (ENABLE_TRACE_INTERFACE), line:172
|vpiName:ENABLE_TRACE_INTERFACE
|INT:2
|vpiParameter:
\_parameter: (FETCH_BUFFER_DEPTH), line:168
|vpiName:FETCH_BUFFER_DEPTH
|INT:512
|vpiParameter:
\_parameter: (FPGA_VENDOR), line:27
|vpiName:FPGA_VENDOR
|STRING:"xilinx"
|vpiParameter:
\_parameter: (GC_UNIT_ID), line:196
|vpiName:GC_UNIT_ID
|INT:4
|vpiParameter:
\_parameter: (ICACHE_LINES), line:121
|vpiName:ICACHE_LINES
|INT:2
|vpiParameter:
\_parameter: (ICACHE_LINE_ADDR_W), line:123
|vpiName:ICACHE_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_LINE_W), line:124
|vpiName:ICACHE_LINE_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_SUB_LINE_ADDR_W), line:125
|vpiName:ICACHE_SUB_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_TAG_W), line:126
|vpiName:ICACHE_TAG_W
|INT:-2147483648
|vpiParameter:
\_parameter: (ICACHE_WAYS), line:122
|vpiName:ICACHE_WAYS
|INT:1
|vpiParameter:
\_parameter: (ITLB_DEPTH), line:146
|vpiName:ITLB_DEPTH
|INT:32
|vpiParameter:
\_parameter: (ITLB_WAYS), line:145
|vpiName:ITLB_WAYS
|INT:4
|vpiParameter:
\_parameter: (L1_CONNECTIONS), line:177
|vpiName:L1_CONNECTIONS
|INT:9
|vpiParameter:
\_parameter: (L1_DCACHE_ID), line:178
|vpiName:L1_DCACHE_ID
|INT:4
|vpiParameter:
\_parameter: (L1_DMMU_ID), line:179
|vpiName:L1_DMMU_ID
|INT:2
|vpiParameter:
\_parameter: (L1_ICACHE_ID), line:180
|vpiName:L1_ICACHE_ID
|INT:19
|vpiParameter:
\_parameter: (L1_IMMU_ID), line:181
|vpiName:L1_IMMU_ID
|INT:0
|vpiParameter:
\_parameter: (LS_UNIT_WB_ID), line:191
|vpiName:LS_UNIT_WB_ID
|INT:1
|vpiParameter:
\_parameter: (MAX_INFLIGHT_COUNT), line:167
|vpiName:MAX_INFLIGHT_COUNT
|INT:19
|vpiParameter:
\_parameter: (MEMORY_ADDR_H), line:103
|vpiName:MEMORY_ADDR_H
|INT:12
|vpiParameter:
\_parameter: (MEMORY_ADDR_L), line:102
|vpiName:MEMORY_ADDR_L
|INT:11
|vpiParameter:
\_parameter: (MEMORY_BIT_CHECK), line:104
|vpiName:MEMORY_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (MUL_UNIT_WB_ID), line:193
|vpiName:MUL_UNIT_WB_ID
|INT:512
|vpiParameter:
\_parameter: (NUM_UNITS), line:188
|vpiName:NUM_UNITS
|INT:2
|vpiParameter:
\_parameter: (NUM_WB_UNITS), line:186
|vpiName:NUM_WB_UNITS
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (RAS_DEPTH), line:161
|vpiName:RAS_DEPTH
|INT:2
|vpiParameter:
\_parameter: (RESET_VEC), line:39
|vpiName:RESET_VEC
|INT:-2147483648
|vpiParameter:
\_parameter: (SCRATCH_ADDR_H), line:99
|vpiName:SCRATCH_ADDR_H
|INT:9
|vpiParameter:
\_parameter: (SCRATCH_ADDR_L), line:98
|vpiName:SCRATCH_ADDR_L
|INT:8
|vpiParameter:
\_parameter: (SCRATCH_BIT_CHECK), line:100
|vpiName:SCRATCH_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (USE_AMO), line:70
|vpiName:USE_AMO
|INT:1
|vpiParameter:
\_parameter: (USE_BRANCH_PREDICTOR), line:158
|vpiName:USE_BRANCH_PREDICTOR
|INT:2
|vpiParameter:
\_parameter: (USE_BUS), line:88
|vpiName:USE_BUS
|INT:4
|vpiParameter:
\_parameter: (USE_DCACHE), line:92
|vpiName:USE_DCACHE
|INT:6
|vpiParameter:
\_parameter: (USE_DIV), line:49
|vpiName:USE_DIV
|INT:1
|vpiParameter:
\_parameter: (USE_DTAG_INVALIDATIONS), line:140
|vpiName:USE_DTAG_INVALIDATIONS
|INT:1879048191
|vpiParameter:
\_parameter: (USE_D_SCRATCH_MEM), line:79
|vpiName:USE_D_SCRATCH_MEM
|INT:3
|vpiParameter:
\_parameter: (USE_ICACHE), line:93
|vpiName:USE_ICACHE
|INT:7
|vpiParameter:
\_parameter: (USE_I_SCRATCH_MEM), line:78
|vpiName:USE_I_SCRATCH_MEM
|INT:2
|vpiParameter:
\_parameter: (USE_MUL), line:48
|vpiName:USE_MUL
|INT:1
|vpiParameter:
\_parameter: (WB_UNITS_WIDTH), line:187
|vpiName:WB_UNITS_WIDTH
|INT:32
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiParameter:
\_parameter: (i), line:61
|vpiName:i
|INT:6
|vpiGenScopeArray:
\_gen_scope_array: (branch_tag_banks[7]), line:61
|vpiName:branch_tag_banks[7]
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_tag_banks.branch_tag_banks[7]
|vpiGenScope:
\_gen_scope: , parent:branch_tag_banks[7]
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_tag_banks.branch_tag_banks[7]
|vpiModule:
\_module: work@branch_predictor_ram (tag_bank), file:third_party/cores/taiga/core/branch_predictor.sv, line:62
|vpiDefName:work@branch_predictor_ram
|vpiName:tag_bank
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_tag_banks.branch_tag_banks[7].tag_bank
|vpiPort:
\_port: (clk), line:32, parent:tag_bank
|vpiName:clk
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (clk), line:63
|vpiName:clk
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (clk), line:32, parent:tag_bank
|vpiName:clk
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_tag_banks.branch_tag_banks[7].tag_bank.clk
|vpiNetType:36
|vpiPort:
\_port: (write_addr), line:33, parent:tag_bank
|vpiName:write_addr
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (write_addr), line:63
|vpiName:write_addr
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (write_addr), line:33, parent:tag_bank
|vpiName:write_addr
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_tag_banks.branch_tag_banks[7].tag_bank.write_addr
|vpiNetType:36
|vpiRange:
\_range: , line:33
|vpiLeftRange:
\_constant: , line:33
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:33
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiPort:
\_port: (write_en), line:34, parent:tag_bank
|vpiName:write_en
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (write_en), line:63
|vpiName:write_en
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (write_en), line:34, parent:tag_bank
|vpiName:write_en
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_tag_banks.branch_tag_banks[7].tag_bank.write_en
|vpiNetType:36
|vpiPort:
\_port: (read_addr), line:35, parent:tag_bank
|vpiName:read_addr
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (read_addr), line:63
|vpiName:read_addr
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (read_addr), line:35, parent:tag_bank
|vpiName:read_addr
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_tag_banks.branch_tag_banks[7].tag_bank.read_addr
|vpiNetType:36
|vpiRange:
\_range: , line:35
|vpiLeftRange:
\_constant: , line:35
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:35
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiPort:
\_port: (read_en), line:36, parent:tag_bank
|vpiName:read_en
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (read_en), line:63
|vpiName:read_en
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (read_en), line:36, parent:tag_bank
|vpiName:read_en
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_tag_banks.branch_tag_banks[7].tag_bank.read_en
|vpiNetType:36
|vpiPort:
\_port: (write_data), line:37, parent:tag_bank
|vpiName:write_data
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (write_data), line:63
|vpiName:write_data
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (write_data), line:37, parent:tag_bank
|vpiName:write_data
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_tag_banks.branch_tag_banks[7].tag_bank.write_data
|vpiNetType:36
|vpiRange:
\_range: , line:37
|vpiLeftRange:
\_constant: , line:37
|vpiDecompile:-1
|INT:-1
|vpiRightRange:
\_constant: , line:37
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiPort:
\_port: (read_data), line:38, parent:tag_bank
|vpiName:read_data
|vpiDirection:2
|vpiHighConn:
\_ref_obj: (read_data), line:63
|vpiName:read_data
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (read_data), line:38, parent:tag_bank
|vpiName:read_data
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_tag_banks.branch_tag_banks[7].tag_bank.read_data
|vpiNetType:36
|vpiRange:
\_range: , line:38
|vpiLeftRange:
\_constant: , line:38
|vpiDecompile:-1
|INT:-1
|vpiRightRange:
\_constant: , line:38
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (clk), line:32, parent:tag_bank
|vpiNet:
\_logic_net: (write_addr), line:33, parent:tag_bank
|vpiNet:
\_logic_net: (write_en), line:34, parent:tag_bank
|vpiNet:
\_logic_net: (read_addr), line:35, parent:tag_bank
|vpiNet:
\_logic_net: (read_en), line:36, parent:tag_bank
|vpiNet:
\_logic_net: (write_data), line:37, parent:tag_bank
|vpiNet:
\_logic_net: (read_data), line:38, parent:tag_bank
|vpiArrayNet:
\_array_net: (branch_ram), line:40, parent:tag_bank
|vpiName:branch_ram
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_tag_banks.branch_tag_banks[7].tag_bank.branch_ram
|vpiSize:4
|vpiNet:
\_logic_net: , parent:branch_ram
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_tag_banks.branch_tag_banks[7].tag_bank.branch_ram
|vpiNetType:36
|vpiRange:
\_range: , line:40
|vpiLeftRange:
\_constant: , line:40
|vpiDecompile:-1
|INT:-1
|vpiRightRange:
\_constant: , line:40
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiRange:
\_range: , line:40
|vpiLeftRange:
\_constant: , line:40
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiRightRange:
\_constant: , line:40
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiParameter:
\_parameter: (ALU_UNIT_WB_ID), line:190
|vpiName:ALU_UNIT_WB_ID
|INT:32
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (BRANCH_PREDICTOR_WAYS), line:159
|vpiName:BRANCH_PREDICTOR_WAYS
|INT:9
|vpiParameter:
\_parameter: (BRANCH_TABLE_ENTRIES), line:160
|vpiName:BRANCH_TABLE_ENTRIES
|INT:4
|vpiParameter:
\_parameter: (BRANCH_UNIT_ID), line:195
|vpiName:BRANCH_UNIT_ID
|INT:8
|vpiParameter:
\_parameter: (BUS_ADDR_H), line:107
|vpiName:BUS_ADDR_H
|INT:1
|vpiParameter:
\_parameter: (BUS_ADDR_L), line:106
|vpiName:BUS_ADDR_L
|INT:0
|vpiParameter:
\_parameter: (BUS_BIT_CHECK), line:108
|vpiName:BUS_BIT_CHECK
|INT:1
|vpiParameter:
\_parameter: (BUS_TYPE), line:89
|vpiName:BUS_TYPE
|INT:5
|vpiParameter:
\_parameter: (COUNTER_W), line:42
|vpiName:COUNTER_W
|INT:33
|vpiParameter:
\_parameter: (CPU_ID), line:38
|vpiName:CPU_ID
|INT:0
|vpiParameter:
\_parameter: (C_DATA_WIDTH), line:62
|vpiName:C_DATA_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_DEPTH), line:62
|vpiName:C_DEPTH
|INT:4
|vpiParameter:
\_parameter: (C_M_AXI_ADDR_WIDTH), line:113
|vpiName:C_M_AXI_ADDR_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_DATA_WIDTH), line:114
|vpiName:C_M_AXI_DATA_WIDTH
|INT:1
|vpiParameter:
\_parameter: (DCACHE_LINES), line:133
|vpiName:DCACHE_LINES
|INT:-2146435073
|vpiParameter:
\_parameter: (DCACHE_LINE_ADDR_W), line:135
|vpiName:DCACHE_LINE_ADDR_W
|INT:1073741824
|vpiParameter:
\_parameter: (DCACHE_LINE_W), line:136
|vpiName:DCACHE_LINE_W
|INT:1342177279
|vpiParameter:
\_parameter: (DCACHE_SUB_LINE_ADDR_W), line:137
|vpiName:DCACHE_SUB_LINE_ADDR_W
|INT:4
|vpiParameter:
\_parameter: (DCACHE_TAG_W), line:138
|vpiName:DCACHE_TAG_W
|INT:1610612736
|vpiParameter:
\_parameter: (DCACHE_WAYS), line:134
|vpiName:DCACHE_WAYS
|INT:4
|vpiParameter:
\_parameter: (DIV_ALGORITHM), line:67
|vpiName:DIV_ALGORITHM
|INT:0
|vpiParameter:
\_parameter: (DIV_UNIT_WB_ID), line:192
|vpiName:DIV_UNIT_WB_ID
|INT:2
|vpiParameter:
\_parameter: (DTLB_DEPTH), line:152
|vpiName:DTLB_DEPTH
|INT:512
|vpiParameter:
\_parameter: (DTLB_WAYS), line:151
|vpiName:DTLB_WAYS
|INT:32
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (ENABLE_M_MODE), line:34
|vpiName:ENABLE_M_MODE
|INT:1
|vpiParameter:
\_parameter: (ENABLE_S_MODE), line:36
|vpiName:ENABLE_S_MODE
|INT:0
|vpiParameter:
\_parameter: (ENABLE_TRACE_INTERFACE), line:172
|vpiName:ENABLE_TRACE_INTERFACE
|INT:2
|vpiParameter:
\_parameter: (FETCH_BUFFER_DEPTH), line:168
|vpiName:FETCH_BUFFER_DEPTH
|INT:512
|vpiParameter:
\_parameter: (FPGA_VENDOR), line:27
|vpiName:FPGA_VENDOR
|STRING:"xilinx"
|vpiParameter:
\_parameter: (GC_UNIT_ID), line:196
|vpiName:GC_UNIT_ID
|INT:4
|vpiParameter:
\_parameter: (ICACHE_LINES), line:121
|vpiName:ICACHE_LINES
|INT:2
|vpiParameter:
\_parameter: (ICACHE_LINE_ADDR_W), line:123
|vpiName:ICACHE_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_LINE_W), line:124
|vpiName:ICACHE_LINE_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_SUB_LINE_ADDR_W), line:125
|vpiName:ICACHE_SUB_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_TAG_W), line:126
|vpiName:ICACHE_TAG_W
|INT:-2147483648
|vpiParameter:
\_parameter: (ICACHE_WAYS), line:122
|vpiName:ICACHE_WAYS
|INT:1
|vpiParameter:
\_parameter: (ITLB_DEPTH), line:146
|vpiName:ITLB_DEPTH
|INT:32
|vpiParameter:
\_parameter: (ITLB_WAYS), line:145
|vpiName:ITLB_WAYS
|INT:4
|vpiParameter:
\_parameter: (L1_CONNECTIONS), line:177
|vpiName:L1_CONNECTIONS
|INT:9
|vpiParameter:
\_parameter: (L1_DCACHE_ID), line:178
|vpiName:L1_DCACHE_ID
|INT:4
|vpiParameter:
\_parameter: (L1_DMMU_ID), line:179
|vpiName:L1_DMMU_ID
|INT:2
|vpiParameter:
\_parameter: (L1_ICACHE_ID), line:180
|vpiName:L1_ICACHE_ID
|INT:19
|vpiParameter:
\_parameter: (L1_IMMU_ID), line:181
|vpiName:L1_IMMU_ID
|INT:0
|vpiParameter:
\_parameter: (LS_UNIT_WB_ID), line:191
|vpiName:LS_UNIT_WB_ID
|INT:1
|vpiParameter:
\_parameter: (MAX_INFLIGHT_COUNT), line:167
|vpiName:MAX_INFLIGHT_COUNT
|INT:19
|vpiParameter:
\_parameter: (MEMORY_ADDR_H), line:103
|vpiName:MEMORY_ADDR_H
|INT:12
|vpiParameter:
\_parameter: (MEMORY_ADDR_L), line:102
|vpiName:MEMORY_ADDR_L
|INT:11
|vpiParameter:
\_parameter: (MEMORY_BIT_CHECK), line:104
|vpiName:MEMORY_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (MUL_UNIT_WB_ID), line:193
|vpiName:MUL_UNIT_WB_ID
|INT:512
|vpiParameter:
\_parameter: (NUM_UNITS), line:188
|vpiName:NUM_UNITS
|INT:2
|vpiParameter:
\_parameter: (NUM_WB_UNITS), line:186
|vpiName:NUM_WB_UNITS
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (RAS_DEPTH), line:161
|vpiName:RAS_DEPTH
|INT:2
|vpiParameter:
\_parameter: (RESET_VEC), line:39
|vpiName:RESET_VEC
|INT:-2147483648
|vpiParameter:
\_parameter: (SCRATCH_ADDR_H), line:99
|vpiName:SCRATCH_ADDR_H
|INT:9
|vpiParameter:
\_parameter: (SCRATCH_ADDR_L), line:98
|vpiName:SCRATCH_ADDR_L
|INT:8
|vpiParameter:
\_parameter: (SCRATCH_BIT_CHECK), line:100
|vpiName:SCRATCH_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (USE_AMO), line:70
|vpiName:USE_AMO
|INT:1
|vpiParameter:
\_parameter: (USE_BRANCH_PREDICTOR), line:158
|vpiName:USE_BRANCH_PREDICTOR
|INT:2
|vpiParameter:
\_parameter: (USE_BUS), line:88
|vpiName:USE_BUS
|INT:4
|vpiParameter:
\_parameter: (USE_DCACHE), line:92
|vpiName:USE_DCACHE
|INT:6
|vpiParameter:
\_parameter: (USE_DIV), line:49
|vpiName:USE_DIV
|INT:1
|vpiParameter:
\_parameter: (USE_DTAG_INVALIDATIONS), line:140
|vpiName:USE_DTAG_INVALIDATIONS
|INT:1879048191
|vpiParameter:
\_parameter: (USE_D_SCRATCH_MEM), line:79
|vpiName:USE_D_SCRATCH_MEM
|INT:3
|vpiParameter:
\_parameter: (USE_ICACHE), line:93
|vpiName:USE_ICACHE
|INT:7
|vpiParameter:
\_parameter: (USE_I_SCRATCH_MEM), line:78
|vpiName:USE_I_SCRATCH_MEM
|INT:2
|vpiParameter:
\_parameter: (USE_MUL), line:48
|vpiName:USE_MUL
|INT:1
|vpiParameter:
\_parameter: (WB_UNITS_WIDTH), line:187
|vpiName:WB_UNITS_WIDTH
|INT:32
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiParameter:
\_parameter: (ALU_UNIT_WB_ID), line:190
|vpiName:ALU_UNIT_WB_ID
|INT:32
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (BRANCH_PREDICTOR_WAYS), line:159
|vpiName:BRANCH_PREDICTOR_WAYS
|INT:9
|vpiParameter:
\_parameter: (BRANCH_TABLE_ENTRIES), line:160
|vpiName:BRANCH_TABLE_ENTRIES
|INT:4
|vpiParameter:
\_parameter: (BRANCH_UNIT_ID), line:195
|vpiName:BRANCH_UNIT_ID
|INT:8
|vpiParameter:
\_parameter: (BUS_ADDR_H), line:107
|vpiName:BUS_ADDR_H
|INT:1
|vpiParameter:
\_parameter: (BUS_ADDR_L), line:106
|vpiName:BUS_ADDR_L
|INT:0
|vpiParameter:
\_parameter: (BUS_BIT_CHECK), line:108
|vpiName:BUS_BIT_CHECK
|INT:1
|vpiParameter:
\_parameter: (BUS_TYPE), line:89
|vpiName:BUS_TYPE
|INT:5
|vpiParameter:
\_parameter: (COUNTER_W), line:42
|vpiName:COUNTER_W
|INT:33
|vpiParameter:
\_parameter: (CPU_ID), line:38
|vpiName:CPU_ID
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_ADDR_WIDTH), line:113
|vpiName:C_M_AXI_ADDR_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_DATA_WIDTH), line:114
|vpiName:C_M_AXI_DATA_WIDTH
|INT:1
|vpiParameter:
\_parameter: (DCACHE_LINES), line:133
|vpiName:DCACHE_LINES
|INT:-2146435073
|vpiParameter:
\_parameter: (DCACHE_LINE_ADDR_W), line:135
|vpiName:DCACHE_LINE_ADDR_W
|INT:1073741824
|vpiParameter:
\_parameter: (DCACHE_LINE_W), line:136
|vpiName:DCACHE_LINE_W
|INT:1342177279
|vpiParameter:
\_parameter: (DCACHE_SUB_LINE_ADDR_W), line:137
|vpiName:DCACHE_SUB_LINE_ADDR_W
|INT:4
|vpiParameter:
\_parameter: (DCACHE_TAG_W), line:138
|vpiName:DCACHE_TAG_W
|INT:1610612736
|vpiParameter:
\_parameter: (DCACHE_WAYS), line:134
|vpiName:DCACHE_WAYS
|INT:4
|vpiParameter:
\_parameter: (DIV_ALGORITHM), line:67
|vpiName:DIV_ALGORITHM
|INT:0
|vpiParameter:
\_parameter: (DIV_UNIT_WB_ID), line:192
|vpiName:DIV_UNIT_WB_ID
|INT:2
|vpiParameter:
\_parameter: (DTLB_DEPTH), line:152
|vpiName:DTLB_DEPTH
|INT:512
|vpiParameter:
\_parameter: (DTLB_WAYS), line:151
|vpiName:DTLB_WAYS
|INT:32
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (ENABLE_M_MODE), line:34
|vpiName:ENABLE_M_MODE
|INT:1
|vpiParameter:
\_parameter: (ENABLE_S_MODE), line:36
|vpiName:ENABLE_S_MODE
|INT:0
|vpiParameter:
\_parameter: (ENABLE_TRACE_INTERFACE), line:172
|vpiName:ENABLE_TRACE_INTERFACE
|INT:2
|vpiParameter:
\_parameter: (FETCH_BUFFER_DEPTH), line:168
|vpiName:FETCH_BUFFER_DEPTH
|INT:512
|vpiParameter:
\_parameter: (FPGA_VENDOR), line:27
|vpiName:FPGA_VENDOR
|STRING:"xilinx"
|vpiParameter:
\_parameter: (GC_UNIT_ID), line:196
|vpiName:GC_UNIT_ID
|INT:4
|vpiParameter:
\_parameter: (ICACHE_LINES), line:121
|vpiName:ICACHE_LINES
|INT:2
|vpiParameter:
\_parameter: (ICACHE_LINE_ADDR_W), line:123
|vpiName:ICACHE_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_LINE_W), line:124
|vpiName:ICACHE_LINE_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_SUB_LINE_ADDR_W), line:125
|vpiName:ICACHE_SUB_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_TAG_W), line:126
|vpiName:ICACHE_TAG_W
|INT:-2147483648
|vpiParameter:
\_parameter: (ICACHE_WAYS), line:122
|vpiName:ICACHE_WAYS
|INT:1
|vpiParameter:
\_parameter: (ITLB_DEPTH), line:146
|vpiName:ITLB_DEPTH
|INT:32
|vpiParameter:
\_parameter: (ITLB_WAYS), line:145
|vpiName:ITLB_WAYS
|INT:4
|vpiParameter:
\_parameter: (L1_CONNECTIONS), line:177
|vpiName:L1_CONNECTIONS
|INT:9
|vpiParameter:
\_parameter: (L1_DCACHE_ID), line:178
|vpiName:L1_DCACHE_ID
|INT:4
|vpiParameter:
\_parameter: (L1_DMMU_ID), line:179
|vpiName:L1_DMMU_ID
|INT:2
|vpiParameter:
\_parameter: (L1_ICACHE_ID), line:180
|vpiName:L1_ICACHE_ID
|INT:19
|vpiParameter:
\_parameter: (L1_IMMU_ID), line:181
|vpiName:L1_IMMU_ID
|INT:0
|vpiParameter:
\_parameter: (LS_UNIT_WB_ID), line:191
|vpiName:LS_UNIT_WB_ID
|INT:1
|vpiParameter:
\_parameter: (MAX_INFLIGHT_COUNT), line:167
|vpiName:MAX_INFLIGHT_COUNT
|INT:19
|vpiParameter:
\_parameter: (MEMORY_ADDR_H), line:103
|vpiName:MEMORY_ADDR_H
|INT:12
|vpiParameter:
\_parameter: (MEMORY_ADDR_L), line:102
|vpiName:MEMORY_ADDR_L
|INT:11
|vpiParameter:
\_parameter: (MEMORY_BIT_CHECK), line:104
|vpiName:MEMORY_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (MUL_UNIT_WB_ID), line:193
|vpiName:MUL_UNIT_WB_ID
|INT:512
|vpiParameter:
\_parameter: (NUM_UNITS), line:188
|vpiName:NUM_UNITS
|INT:2
|vpiParameter:
\_parameter: (NUM_WB_UNITS), line:186
|vpiName:NUM_WB_UNITS
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (RAS_DEPTH), line:161
|vpiName:RAS_DEPTH
|INT:2
|vpiParameter:
\_parameter: (RESET_VEC), line:39
|vpiName:RESET_VEC
|INT:-2147483648
|vpiParameter:
\_parameter: (SCRATCH_ADDR_H), line:99
|vpiName:SCRATCH_ADDR_H
|INT:9
|vpiParameter:
\_parameter: (SCRATCH_ADDR_L), line:98
|vpiName:SCRATCH_ADDR_L
|INT:8
|vpiParameter:
\_parameter: (SCRATCH_BIT_CHECK), line:100
|vpiName:SCRATCH_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (USE_AMO), line:70
|vpiName:USE_AMO
|INT:1
|vpiParameter:
\_parameter: (USE_BRANCH_PREDICTOR), line:158
|vpiName:USE_BRANCH_PREDICTOR
|INT:2
|vpiParameter:
\_parameter: (USE_BUS), line:88
|vpiName:USE_BUS
|INT:4
|vpiParameter:
\_parameter: (USE_DCACHE), line:92
|vpiName:USE_DCACHE
|INT:6
|vpiParameter:
\_parameter: (USE_DIV), line:49
|vpiName:USE_DIV
|INT:1
|vpiParameter:
\_parameter: (USE_DTAG_INVALIDATIONS), line:140
|vpiName:USE_DTAG_INVALIDATIONS
|INT:1879048191
|vpiParameter:
\_parameter: (USE_D_SCRATCH_MEM), line:79
|vpiName:USE_D_SCRATCH_MEM
|INT:3
|vpiParameter:
\_parameter: (USE_ICACHE), line:93
|vpiName:USE_ICACHE
|INT:7
|vpiParameter:
\_parameter: (USE_I_SCRATCH_MEM), line:78
|vpiName:USE_I_SCRATCH_MEM
|INT:2
|vpiParameter:
\_parameter: (USE_MUL), line:48
|vpiName:USE_MUL
|INT:1
|vpiParameter:
\_parameter: (WB_UNITS_WIDTH), line:187
|vpiName:WB_UNITS_WIDTH
|INT:32
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiParameter:
\_parameter: (i), line:61
|vpiName:i
|INT:7
|vpiGenScopeArray:
\_gen_scope_array: (branch_tag_banks[8]), line:61
|vpiName:branch_tag_banks[8]
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_tag_banks.branch_tag_banks[8]
|vpiGenScope:
\_gen_scope: , parent:branch_tag_banks[8]
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_tag_banks.branch_tag_banks[8]
|vpiModule:
\_module: work@branch_predictor_ram (tag_bank), file:third_party/cores/taiga/core/branch_predictor.sv, line:62
|vpiDefName:work@branch_predictor_ram
|vpiName:tag_bank
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_tag_banks.branch_tag_banks[8].tag_bank
|vpiPort:
\_port: (clk), line:32, parent:tag_bank
|vpiName:clk
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (clk), line:63
|vpiName:clk
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (clk), line:32, parent:tag_bank
|vpiName:clk
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_tag_banks.branch_tag_banks[8].tag_bank.clk
|vpiNetType:36
|vpiPort:
\_port: (write_addr), line:33, parent:tag_bank
|vpiName:write_addr
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (write_addr), line:63
|vpiName:write_addr
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (write_addr), line:33, parent:tag_bank
|vpiName:write_addr
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_tag_banks.branch_tag_banks[8].tag_bank.write_addr
|vpiNetType:36
|vpiRange:
\_range: , line:33
|vpiLeftRange:
\_constant: , line:33
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:33
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiPort:
\_port: (write_en), line:34, parent:tag_bank
|vpiName:write_en
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (write_en), line:63
|vpiName:write_en
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (write_en), line:34, parent:tag_bank
|vpiName:write_en
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_tag_banks.branch_tag_banks[8].tag_bank.write_en
|vpiNetType:36
|vpiPort:
\_port: (read_addr), line:35, parent:tag_bank
|vpiName:read_addr
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (read_addr), line:63
|vpiName:read_addr
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (read_addr), line:35, parent:tag_bank
|vpiName:read_addr
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_tag_banks.branch_tag_banks[8].tag_bank.read_addr
|vpiNetType:36
|vpiRange:
\_range: , line:35
|vpiLeftRange:
\_constant: , line:35
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:35
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiPort:
\_port: (read_en), line:36, parent:tag_bank
|vpiName:read_en
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (read_en), line:63
|vpiName:read_en
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (read_en), line:36, parent:tag_bank
|vpiName:read_en
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_tag_banks.branch_tag_banks[8].tag_bank.read_en
|vpiNetType:36
|vpiPort:
\_port: (write_data), line:37, parent:tag_bank
|vpiName:write_data
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (write_data), line:63
|vpiName:write_data
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (write_data), line:37, parent:tag_bank
|vpiName:write_data
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_tag_banks.branch_tag_banks[8].tag_bank.write_data
|vpiNetType:36
|vpiRange:
\_range: , line:37
|vpiLeftRange:
\_constant: , line:37
|vpiDecompile:-1
|INT:-1
|vpiRightRange:
\_constant: , line:37
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiPort:
\_port: (read_data), line:38, parent:tag_bank
|vpiName:read_data
|vpiDirection:2
|vpiHighConn:
\_ref_obj: (read_data), line:63
|vpiName:read_data
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (read_data), line:38, parent:tag_bank
|vpiName:read_data
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_tag_banks.branch_tag_banks[8].tag_bank.read_data
|vpiNetType:36
|vpiRange:
\_range: , line:38
|vpiLeftRange:
\_constant: , line:38
|vpiDecompile:-1
|INT:-1
|vpiRightRange:
\_constant: , line:38
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (clk), line:32, parent:tag_bank
|vpiNet:
\_logic_net: (write_addr), line:33, parent:tag_bank
|vpiNet:
\_logic_net: (write_en), line:34, parent:tag_bank
|vpiNet:
\_logic_net: (read_addr), line:35, parent:tag_bank
|vpiNet:
\_logic_net: (read_en), line:36, parent:tag_bank
|vpiNet:
\_logic_net: (write_data), line:37, parent:tag_bank
|vpiNet:
\_logic_net: (read_data), line:38, parent:tag_bank
|vpiArrayNet:
\_array_net: (branch_ram), line:40, parent:tag_bank
|vpiName:branch_ram
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_tag_banks.branch_tag_banks[8].tag_bank.branch_ram
|vpiSize:4
|vpiNet:
\_logic_net: , parent:branch_ram
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_tag_banks.branch_tag_banks[8].tag_bank.branch_ram
|vpiNetType:36
|vpiRange:
\_range: , line:40
|vpiLeftRange:
\_constant: , line:40
|vpiDecompile:-1
|INT:-1
|vpiRightRange:
\_constant: , line:40
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiRange:
\_range: , line:40
|vpiLeftRange:
\_constant: , line:40
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiRightRange:
\_constant: , line:40
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiParameter:
\_parameter: (ALU_UNIT_WB_ID), line:190
|vpiName:ALU_UNIT_WB_ID
|INT:32
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (BRANCH_PREDICTOR_WAYS), line:159
|vpiName:BRANCH_PREDICTOR_WAYS
|INT:9
|vpiParameter:
\_parameter: (BRANCH_TABLE_ENTRIES), line:160
|vpiName:BRANCH_TABLE_ENTRIES
|INT:4
|vpiParameter:
\_parameter: (BRANCH_UNIT_ID), line:195
|vpiName:BRANCH_UNIT_ID
|INT:8
|vpiParameter:
\_parameter: (BUS_ADDR_H), line:107
|vpiName:BUS_ADDR_H
|INT:1
|vpiParameter:
\_parameter: (BUS_ADDR_L), line:106
|vpiName:BUS_ADDR_L
|INT:0
|vpiParameter:
\_parameter: (BUS_BIT_CHECK), line:108
|vpiName:BUS_BIT_CHECK
|INT:1
|vpiParameter:
\_parameter: (BUS_TYPE), line:89
|vpiName:BUS_TYPE
|INT:5
|vpiParameter:
\_parameter: (COUNTER_W), line:42
|vpiName:COUNTER_W
|INT:33
|vpiParameter:
\_parameter: (CPU_ID), line:38
|vpiName:CPU_ID
|INT:0
|vpiParameter:
\_parameter: (C_DATA_WIDTH), line:62
|vpiName:C_DATA_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_DEPTH), line:62
|vpiName:C_DEPTH
|INT:4
|vpiParameter:
\_parameter: (C_M_AXI_ADDR_WIDTH), line:113
|vpiName:C_M_AXI_ADDR_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_DATA_WIDTH), line:114
|vpiName:C_M_AXI_DATA_WIDTH
|INT:1
|vpiParameter:
\_parameter: (DCACHE_LINES), line:133
|vpiName:DCACHE_LINES
|INT:-2146435073
|vpiParameter:
\_parameter: (DCACHE_LINE_ADDR_W), line:135
|vpiName:DCACHE_LINE_ADDR_W
|INT:1073741824
|vpiParameter:
\_parameter: (DCACHE_LINE_W), line:136
|vpiName:DCACHE_LINE_W
|INT:1342177279
|vpiParameter:
\_parameter: (DCACHE_SUB_LINE_ADDR_W), line:137
|vpiName:DCACHE_SUB_LINE_ADDR_W
|INT:4
|vpiParameter:
\_parameter: (DCACHE_TAG_W), line:138
|vpiName:DCACHE_TAG_W
|INT:1610612736
|vpiParameter:
\_parameter: (DCACHE_WAYS), line:134
|vpiName:DCACHE_WAYS
|INT:4
|vpiParameter:
\_parameter: (DIV_ALGORITHM), line:67
|vpiName:DIV_ALGORITHM
|INT:0
|vpiParameter:
\_parameter: (DIV_UNIT_WB_ID), line:192
|vpiName:DIV_UNIT_WB_ID
|INT:2
|vpiParameter:
\_parameter: (DTLB_DEPTH), line:152
|vpiName:DTLB_DEPTH
|INT:512
|vpiParameter:
\_parameter: (DTLB_WAYS), line:151
|vpiName:DTLB_WAYS
|INT:32
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (ENABLE_M_MODE), line:34
|vpiName:ENABLE_M_MODE
|INT:1
|vpiParameter:
\_parameter: (ENABLE_S_MODE), line:36
|vpiName:ENABLE_S_MODE
|INT:0
|vpiParameter:
\_parameter: (ENABLE_TRACE_INTERFACE), line:172
|vpiName:ENABLE_TRACE_INTERFACE
|INT:2
|vpiParameter:
\_parameter: (FETCH_BUFFER_DEPTH), line:168
|vpiName:FETCH_BUFFER_DEPTH
|INT:512
|vpiParameter:
\_parameter: (FPGA_VENDOR), line:27
|vpiName:FPGA_VENDOR
|STRING:"xilinx"
|vpiParameter:
\_parameter: (GC_UNIT_ID), line:196
|vpiName:GC_UNIT_ID
|INT:4
|vpiParameter:
\_parameter: (ICACHE_LINES), line:121
|vpiName:ICACHE_LINES
|INT:2
|vpiParameter:
\_parameter: (ICACHE_LINE_ADDR_W), line:123
|vpiName:ICACHE_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_LINE_W), line:124
|vpiName:ICACHE_LINE_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_SUB_LINE_ADDR_W), line:125
|vpiName:ICACHE_SUB_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_TAG_W), line:126
|vpiName:ICACHE_TAG_W
|INT:-2147483648
|vpiParameter:
\_parameter: (ICACHE_WAYS), line:122
|vpiName:ICACHE_WAYS
|INT:1
|vpiParameter:
\_parameter: (ITLB_DEPTH), line:146
|vpiName:ITLB_DEPTH
|INT:32
|vpiParameter:
\_parameter: (ITLB_WAYS), line:145
|vpiName:ITLB_WAYS
|INT:4
|vpiParameter:
\_parameter: (L1_CONNECTIONS), line:177
|vpiName:L1_CONNECTIONS
|INT:9
|vpiParameter:
\_parameter: (L1_DCACHE_ID), line:178
|vpiName:L1_DCACHE_ID
|INT:4
|vpiParameter:
\_parameter: (L1_DMMU_ID), line:179
|vpiName:L1_DMMU_ID
|INT:2
|vpiParameter:
\_parameter: (L1_ICACHE_ID), line:180
|vpiName:L1_ICACHE_ID
|INT:19
|vpiParameter:
\_parameter: (L1_IMMU_ID), line:181
|vpiName:L1_IMMU_ID
|INT:0
|vpiParameter:
\_parameter: (LS_UNIT_WB_ID), line:191
|vpiName:LS_UNIT_WB_ID
|INT:1
|vpiParameter:
\_parameter: (MAX_INFLIGHT_COUNT), line:167
|vpiName:MAX_INFLIGHT_COUNT
|INT:19
|vpiParameter:
\_parameter: (MEMORY_ADDR_H), line:103
|vpiName:MEMORY_ADDR_H
|INT:12
|vpiParameter:
\_parameter: (MEMORY_ADDR_L), line:102
|vpiName:MEMORY_ADDR_L
|INT:11
|vpiParameter:
\_parameter: (MEMORY_BIT_CHECK), line:104
|vpiName:MEMORY_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (MUL_UNIT_WB_ID), line:193
|vpiName:MUL_UNIT_WB_ID
|INT:512
|vpiParameter:
\_parameter: (NUM_UNITS), line:188
|vpiName:NUM_UNITS
|INT:2
|vpiParameter:
\_parameter: (NUM_WB_UNITS), line:186
|vpiName:NUM_WB_UNITS
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (RAS_DEPTH), line:161
|vpiName:RAS_DEPTH
|INT:2
|vpiParameter:
\_parameter: (RESET_VEC), line:39
|vpiName:RESET_VEC
|INT:-2147483648
|vpiParameter:
\_parameter: (SCRATCH_ADDR_H), line:99
|vpiName:SCRATCH_ADDR_H
|INT:9
|vpiParameter:
\_parameter: (SCRATCH_ADDR_L), line:98
|vpiName:SCRATCH_ADDR_L
|INT:8
|vpiParameter:
\_parameter: (SCRATCH_BIT_CHECK), line:100
|vpiName:SCRATCH_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (USE_AMO), line:70
|vpiName:USE_AMO
|INT:1
|vpiParameter:
\_parameter: (USE_BRANCH_PREDICTOR), line:158
|vpiName:USE_BRANCH_PREDICTOR
|INT:2
|vpiParameter:
\_parameter: (USE_BUS), line:88
|vpiName:USE_BUS
|INT:4
|vpiParameter:
\_parameter: (USE_DCACHE), line:92
|vpiName:USE_DCACHE
|INT:6
|vpiParameter:
\_parameter: (USE_DIV), line:49
|vpiName:USE_DIV
|INT:1
|vpiParameter:
\_parameter: (USE_DTAG_INVALIDATIONS), line:140
|vpiName:USE_DTAG_INVALIDATIONS
|INT:1879048191
|vpiParameter:
\_parameter: (USE_D_SCRATCH_MEM), line:79
|vpiName:USE_D_SCRATCH_MEM
|INT:3
|vpiParameter:
\_parameter: (USE_ICACHE), line:93
|vpiName:USE_ICACHE
|INT:7
|vpiParameter:
\_parameter: (USE_I_SCRATCH_MEM), line:78
|vpiName:USE_I_SCRATCH_MEM
|INT:2
|vpiParameter:
\_parameter: (USE_MUL), line:48
|vpiName:USE_MUL
|INT:1
|vpiParameter:
\_parameter: (WB_UNITS_WIDTH), line:187
|vpiName:WB_UNITS_WIDTH
|INT:32
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiParameter:
\_parameter: (ALU_UNIT_WB_ID), line:190
|vpiName:ALU_UNIT_WB_ID
|INT:32
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (BRANCH_PREDICTOR_WAYS), line:159
|vpiName:BRANCH_PREDICTOR_WAYS
|INT:9
|vpiParameter:
\_parameter: (BRANCH_TABLE_ENTRIES), line:160
|vpiName:BRANCH_TABLE_ENTRIES
|INT:4
|vpiParameter:
\_parameter: (BRANCH_UNIT_ID), line:195
|vpiName:BRANCH_UNIT_ID
|INT:8
|vpiParameter:
\_parameter: (BUS_ADDR_H), line:107
|vpiName:BUS_ADDR_H
|INT:1
|vpiParameter:
\_parameter: (BUS_ADDR_L), line:106
|vpiName:BUS_ADDR_L
|INT:0
|vpiParameter:
\_parameter: (BUS_BIT_CHECK), line:108
|vpiName:BUS_BIT_CHECK
|INT:1
|vpiParameter:
\_parameter: (BUS_TYPE), line:89
|vpiName:BUS_TYPE
|INT:5
|vpiParameter:
\_parameter: (COUNTER_W), line:42
|vpiName:COUNTER_W
|INT:33
|vpiParameter:
\_parameter: (CPU_ID), line:38
|vpiName:CPU_ID
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_ADDR_WIDTH), line:113
|vpiName:C_M_AXI_ADDR_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_DATA_WIDTH), line:114
|vpiName:C_M_AXI_DATA_WIDTH
|INT:1
|vpiParameter:
\_parameter: (DCACHE_LINES), line:133
|vpiName:DCACHE_LINES
|INT:-2146435073
|vpiParameter:
\_parameter: (DCACHE_LINE_ADDR_W), line:135
|vpiName:DCACHE_LINE_ADDR_W
|INT:1073741824
|vpiParameter:
\_parameter: (DCACHE_LINE_W), line:136
|vpiName:DCACHE_LINE_W
|INT:1342177279
|vpiParameter:
\_parameter: (DCACHE_SUB_LINE_ADDR_W), line:137
|vpiName:DCACHE_SUB_LINE_ADDR_W
|INT:4
|vpiParameter:
\_parameter: (DCACHE_TAG_W), line:138
|vpiName:DCACHE_TAG_W
|INT:1610612736
|vpiParameter:
\_parameter: (DCACHE_WAYS), line:134
|vpiName:DCACHE_WAYS
|INT:4
|vpiParameter:
\_parameter: (DIV_ALGORITHM), line:67
|vpiName:DIV_ALGORITHM
|INT:0
|vpiParameter:
\_parameter: (DIV_UNIT_WB_ID), line:192
|vpiName:DIV_UNIT_WB_ID
|INT:2
|vpiParameter:
\_parameter: (DTLB_DEPTH), line:152
|vpiName:DTLB_DEPTH
|INT:512
|vpiParameter:
\_parameter: (DTLB_WAYS), line:151
|vpiName:DTLB_WAYS
|INT:32
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (ENABLE_M_MODE), line:34
|vpiName:ENABLE_M_MODE
|INT:1
|vpiParameter:
\_parameter: (ENABLE_S_MODE), line:36
|vpiName:ENABLE_S_MODE
|INT:0
|vpiParameter:
\_parameter: (ENABLE_TRACE_INTERFACE), line:172
|vpiName:ENABLE_TRACE_INTERFACE
|INT:2
|vpiParameter:
\_parameter: (FETCH_BUFFER_DEPTH), line:168
|vpiName:FETCH_BUFFER_DEPTH
|INT:512
|vpiParameter:
\_parameter: (FPGA_VENDOR), line:27
|vpiName:FPGA_VENDOR
|STRING:"xilinx"
|vpiParameter:
\_parameter: (GC_UNIT_ID), line:196
|vpiName:GC_UNIT_ID
|INT:4
|vpiParameter:
\_parameter: (ICACHE_LINES), line:121
|vpiName:ICACHE_LINES
|INT:2
|vpiParameter:
\_parameter: (ICACHE_LINE_ADDR_W), line:123
|vpiName:ICACHE_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_LINE_W), line:124
|vpiName:ICACHE_LINE_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_SUB_LINE_ADDR_W), line:125
|vpiName:ICACHE_SUB_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_TAG_W), line:126
|vpiName:ICACHE_TAG_W
|INT:-2147483648
|vpiParameter:
\_parameter: (ICACHE_WAYS), line:122
|vpiName:ICACHE_WAYS
|INT:1
|vpiParameter:
\_parameter: (ITLB_DEPTH), line:146
|vpiName:ITLB_DEPTH
|INT:32
|vpiParameter:
\_parameter: (ITLB_WAYS), line:145
|vpiName:ITLB_WAYS
|INT:4
|vpiParameter:
\_parameter: (L1_CONNECTIONS), line:177
|vpiName:L1_CONNECTIONS
|INT:9
|vpiParameter:
\_parameter: (L1_DCACHE_ID), line:178
|vpiName:L1_DCACHE_ID
|INT:4
|vpiParameter:
\_parameter: (L1_DMMU_ID), line:179
|vpiName:L1_DMMU_ID
|INT:2
|vpiParameter:
\_parameter: (L1_ICACHE_ID), line:180
|vpiName:L1_ICACHE_ID
|INT:19
|vpiParameter:
\_parameter: (L1_IMMU_ID), line:181
|vpiName:L1_IMMU_ID
|INT:0
|vpiParameter:
\_parameter: (LS_UNIT_WB_ID), line:191
|vpiName:LS_UNIT_WB_ID
|INT:1
|vpiParameter:
\_parameter: (MAX_INFLIGHT_COUNT), line:167
|vpiName:MAX_INFLIGHT_COUNT
|INT:19
|vpiParameter:
\_parameter: (MEMORY_ADDR_H), line:103
|vpiName:MEMORY_ADDR_H
|INT:12
|vpiParameter:
\_parameter: (MEMORY_ADDR_L), line:102
|vpiName:MEMORY_ADDR_L
|INT:11
|vpiParameter:
\_parameter: (MEMORY_BIT_CHECK), line:104
|vpiName:MEMORY_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (MUL_UNIT_WB_ID), line:193
|vpiName:MUL_UNIT_WB_ID
|INT:512
|vpiParameter:
\_parameter: (NUM_UNITS), line:188
|vpiName:NUM_UNITS
|INT:2
|vpiParameter:
\_parameter: (NUM_WB_UNITS), line:186
|vpiName:NUM_WB_UNITS
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (RAS_DEPTH), line:161
|vpiName:RAS_DEPTH
|INT:2
|vpiParameter:
\_parameter: (RESET_VEC), line:39
|vpiName:RESET_VEC
|INT:-2147483648
|vpiParameter:
\_parameter: (SCRATCH_ADDR_H), line:99
|vpiName:SCRATCH_ADDR_H
|INT:9
|vpiParameter:
\_parameter: (SCRATCH_ADDR_L), line:98
|vpiName:SCRATCH_ADDR_L
|INT:8
|vpiParameter:
\_parameter: (SCRATCH_BIT_CHECK), line:100
|vpiName:SCRATCH_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (USE_AMO), line:70
|vpiName:USE_AMO
|INT:1
|vpiParameter:
\_parameter: (USE_BRANCH_PREDICTOR), line:158
|vpiName:USE_BRANCH_PREDICTOR
|INT:2
|vpiParameter:
\_parameter: (USE_BUS), line:88
|vpiName:USE_BUS
|INT:4
|vpiParameter:
\_parameter: (USE_DCACHE), line:92
|vpiName:USE_DCACHE
|INT:6
|vpiParameter:
\_parameter: (USE_DIV), line:49
|vpiName:USE_DIV
|INT:1
|vpiParameter:
\_parameter: (USE_DTAG_INVALIDATIONS), line:140
|vpiName:USE_DTAG_INVALIDATIONS
|INT:1879048191
|vpiParameter:
\_parameter: (USE_D_SCRATCH_MEM), line:79
|vpiName:USE_D_SCRATCH_MEM
|INT:3
|vpiParameter:
\_parameter: (USE_ICACHE), line:93
|vpiName:USE_ICACHE
|INT:7
|vpiParameter:
\_parameter: (USE_I_SCRATCH_MEM), line:78
|vpiName:USE_I_SCRATCH_MEM
|INT:2
|vpiParameter:
\_parameter: (USE_MUL), line:48
|vpiName:USE_MUL
|INT:1
|vpiParameter:
\_parameter: (WB_UNITS_WIDTH), line:187
|vpiName:WB_UNITS_WIDTH
|INT:32
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiParameter:
\_parameter: (i), line:61
|vpiName:i
|INT:8
|vpiParameter:
\_parameter: (ALU_UNIT_WB_ID), line:190
|vpiName:ALU_UNIT_WB_ID
|INT:32
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (BRANCH_PREDICTOR_WAYS), line:159
|vpiName:BRANCH_PREDICTOR_WAYS
|INT:9
|vpiParameter:
\_parameter: (BRANCH_TABLE_ENTRIES), line:160
|vpiName:BRANCH_TABLE_ENTRIES
|INT:4
|vpiParameter:
\_parameter: (BRANCH_UNIT_ID), line:195
|vpiName:BRANCH_UNIT_ID
|INT:8
|vpiParameter:
\_parameter: (BUS_ADDR_H), line:107
|vpiName:BUS_ADDR_H
|INT:1
|vpiParameter:
\_parameter: (BUS_ADDR_L), line:106
|vpiName:BUS_ADDR_L
|INT:0
|vpiParameter:
\_parameter: (BUS_BIT_CHECK), line:108
|vpiName:BUS_BIT_CHECK
|INT:1
|vpiParameter:
\_parameter: (BUS_TYPE), line:89
|vpiName:BUS_TYPE
|INT:5
|vpiParameter:
\_parameter: (COUNTER_W), line:42
|vpiName:COUNTER_W
|INT:33
|vpiParameter:
\_parameter: (CPU_ID), line:38
|vpiName:CPU_ID
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_ADDR_WIDTH), line:113
|vpiName:C_M_AXI_ADDR_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_DATA_WIDTH), line:114
|vpiName:C_M_AXI_DATA_WIDTH
|INT:1
|vpiParameter:
\_parameter: (DCACHE_LINES), line:133
|vpiName:DCACHE_LINES
|INT:-2146435073
|vpiParameter:
\_parameter: (DCACHE_LINE_ADDR_W), line:135
|vpiName:DCACHE_LINE_ADDR_W
|INT:1073741824
|vpiParameter:
\_parameter: (DCACHE_LINE_W), line:136
|vpiName:DCACHE_LINE_W
|INT:1342177279
|vpiParameter:
\_parameter: (DCACHE_SUB_LINE_ADDR_W), line:137
|vpiName:DCACHE_SUB_LINE_ADDR_W
|INT:4
|vpiParameter:
\_parameter: (DCACHE_TAG_W), line:138
|vpiName:DCACHE_TAG_W
|INT:1610612736
|vpiParameter:
\_parameter: (DCACHE_WAYS), line:134
|vpiName:DCACHE_WAYS
|INT:4
|vpiParameter:
\_parameter: (DIV_ALGORITHM), line:67
|vpiName:DIV_ALGORITHM
|INT:0
|vpiParameter:
\_parameter: (DIV_UNIT_WB_ID), line:192
|vpiName:DIV_UNIT_WB_ID
|INT:2
|vpiParameter:
\_parameter: (DTLB_DEPTH), line:152
|vpiName:DTLB_DEPTH
|INT:512
|vpiParameter:
\_parameter: (DTLB_WAYS), line:151
|vpiName:DTLB_WAYS
|INT:32
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (ENABLE_M_MODE), line:34
|vpiName:ENABLE_M_MODE
|INT:1
|vpiParameter:
\_parameter: (ENABLE_S_MODE), line:36
|vpiName:ENABLE_S_MODE
|INT:0
|vpiParameter:
\_parameter: (ENABLE_TRACE_INTERFACE), line:172
|vpiName:ENABLE_TRACE_INTERFACE
|INT:2
|vpiParameter:
\_parameter: (FETCH_BUFFER_DEPTH), line:168
|vpiName:FETCH_BUFFER_DEPTH
|INT:512
|vpiParameter:
\_parameter: (FPGA_VENDOR), line:27
|vpiName:FPGA_VENDOR
|STRING:"xilinx"
|vpiParameter:
\_parameter: (GC_UNIT_ID), line:196
|vpiName:GC_UNIT_ID
|INT:4
|vpiParameter:
\_parameter: (ICACHE_LINES), line:121
|vpiName:ICACHE_LINES
|INT:2
|vpiParameter:
\_parameter: (ICACHE_LINE_ADDR_W), line:123
|vpiName:ICACHE_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_LINE_W), line:124
|vpiName:ICACHE_LINE_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_SUB_LINE_ADDR_W), line:125
|vpiName:ICACHE_SUB_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_TAG_W), line:126
|vpiName:ICACHE_TAG_W
|INT:-2147483648
|vpiParameter:
\_parameter: (ICACHE_WAYS), line:122
|vpiName:ICACHE_WAYS
|INT:1
|vpiParameter:
\_parameter: (ITLB_DEPTH), line:146
|vpiName:ITLB_DEPTH
|INT:32
|vpiParameter:
\_parameter: (ITLB_WAYS), line:145
|vpiName:ITLB_WAYS
|INT:4
|vpiParameter:
\_parameter: (L1_CONNECTIONS), line:177
|vpiName:L1_CONNECTIONS
|INT:9
|vpiParameter:
\_parameter: (L1_DCACHE_ID), line:178
|vpiName:L1_DCACHE_ID
|INT:4
|vpiParameter:
\_parameter: (L1_DMMU_ID), line:179
|vpiName:L1_DMMU_ID
|INT:2
|vpiParameter:
\_parameter: (L1_ICACHE_ID), line:180
|vpiName:L1_ICACHE_ID
|INT:19
|vpiParameter:
\_parameter: (L1_IMMU_ID), line:181
|vpiName:L1_IMMU_ID
|INT:0
|vpiParameter:
\_parameter: (LS_UNIT_WB_ID), line:191
|vpiName:LS_UNIT_WB_ID
|INT:1
|vpiParameter:
\_parameter: (MAX_INFLIGHT_COUNT), line:167
|vpiName:MAX_INFLIGHT_COUNT
|INT:19
|vpiParameter:
\_parameter: (MEMORY_ADDR_H), line:103
|vpiName:MEMORY_ADDR_H
|INT:12
|vpiParameter:
\_parameter: (MEMORY_ADDR_L), line:102
|vpiName:MEMORY_ADDR_L
|INT:11
|vpiParameter:
\_parameter: (MEMORY_BIT_CHECK), line:104
|vpiName:MEMORY_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (MUL_UNIT_WB_ID), line:193
|vpiName:MUL_UNIT_WB_ID
|INT:512
|vpiParameter:
\_parameter: (NUM_UNITS), line:188
|vpiName:NUM_UNITS
|INT:2
|vpiParameter:
\_parameter: (NUM_WB_UNITS), line:186
|vpiName:NUM_WB_UNITS
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (RAS_DEPTH), line:161
|vpiName:RAS_DEPTH
|INT:2
|vpiParameter:
\_parameter: (RESET_VEC), line:39
|vpiName:RESET_VEC
|INT:-2147483648
|vpiParameter:
\_parameter: (SCRATCH_ADDR_H), line:99
|vpiName:SCRATCH_ADDR_H
|INT:9
|vpiParameter:
\_parameter: (SCRATCH_ADDR_L), line:98
|vpiName:SCRATCH_ADDR_L
|INT:8
|vpiParameter:
\_parameter: (SCRATCH_BIT_CHECK), line:100
|vpiName:SCRATCH_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (USE_AMO), line:70
|vpiName:USE_AMO
|INT:1
|vpiParameter:
\_parameter: (USE_BRANCH_PREDICTOR), line:158
|vpiName:USE_BRANCH_PREDICTOR
|INT:2
|vpiParameter:
\_parameter: (USE_BUS), line:88
|vpiName:USE_BUS
|INT:4
|vpiParameter:
\_parameter: (USE_DCACHE), line:92
|vpiName:USE_DCACHE
|INT:6
|vpiParameter:
\_parameter: (USE_DIV), line:49
|vpiName:USE_DIV
|INT:1
|vpiParameter:
\_parameter: (USE_DTAG_INVALIDATIONS), line:140
|vpiName:USE_DTAG_INVALIDATIONS
|INT:1879048191
|vpiParameter:
\_parameter: (USE_D_SCRATCH_MEM), line:79
|vpiName:USE_D_SCRATCH_MEM
|INT:3
|vpiParameter:
\_parameter: (USE_ICACHE), line:93
|vpiName:USE_ICACHE
|INT:7
|vpiParameter:
\_parameter: (USE_I_SCRATCH_MEM), line:78
|vpiName:USE_I_SCRATCH_MEM
|INT:2
|vpiParameter:
\_parameter: (USE_MUL), line:48
|vpiName:USE_MUL
|INT:1
|vpiParameter:
\_parameter: (WB_UNITS_WIDTH), line:187
|vpiName:WB_UNITS_WIDTH
|INT:32
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiGenScopeArray:
\_gen_scope_array: (branch_table_banks), line:69, parent:bp_block
|vpiName:branch_table_banks
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_table_banks
|vpiGenScope:
\_gen_scope: , parent:branch_table_banks
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_table_banks
|vpiGenScopeArray:
\_gen_scope_array: (branch_table_banks[0]), line:70
|vpiName:branch_table_banks[0]
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_table_banks.branch_table_banks[0]
|vpiGenScope:
\_gen_scope: , parent:branch_table_banks[0]
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_table_banks.branch_table_banks[0]
|vpiModule:
\_module: work@branch_predictor_ram (addr_table), file:third_party/cores/taiga/core/branch_predictor.sv, line:71
|vpiDefName:work@branch_predictor_ram
|vpiName:addr_table
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_table_banks.branch_table_banks[0].addr_table
|vpiPort:
\_port: (clk), line:32, parent:addr_table
|vpiName:clk
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (clk), line:72
|vpiName:clk
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (clk), line:32, parent:addr_table
|vpiName:clk
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_table_banks.branch_table_banks[0].addr_table.clk
|vpiNetType:36
|vpiPort:
\_port: (write_addr), line:33, parent:addr_table
|vpiName:write_addr
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (write_addr), line:72
|vpiName:write_addr
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (write_addr), line:33, parent:addr_table
|vpiName:write_addr
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_table_banks.branch_table_banks[0].addr_table.write_addr
|vpiNetType:36
|vpiRange:
\_range: , line:33
|vpiLeftRange:
\_constant: , line:33
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:33
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiPort:
\_port: (write_en), line:34, parent:addr_table
|vpiName:write_en
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (write_en), line:72
|vpiName:write_en
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (write_en), line:34, parent:addr_table
|vpiName:write_en
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_table_banks.branch_table_banks[0].addr_table.write_en
|vpiNetType:36
|vpiPort:
\_port: (read_addr), line:35, parent:addr_table
|vpiName:read_addr
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (read_addr), line:72
|vpiName:read_addr
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (read_addr), line:35, parent:addr_table
|vpiName:read_addr
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_table_banks.branch_table_banks[0].addr_table.read_addr
|vpiNetType:36
|vpiRange:
\_range: , line:35
|vpiLeftRange:
\_constant: , line:35
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:35
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiPort:
\_port: (read_en), line:36, parent:addr_table
|vpiName:read_en
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (read_en), line:72
|vpiName:read_en
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (read_en), line:36, parent:addr_table
|vpiName:read_en
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_table_banks.branch_table_banks[0].addr_table.read_en
|vpiNetType:36
|vpiPort:
\_port: (write_data), line:37, parent:addr_table
|vpiName:write_data
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (write_data), line:72
|vpiName:write_data
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (write_data), line:37, parent:addr_table
|vpiName:write_data
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_table_banks.branch_table_banks[0].addr_table.write_data
|vpiNetType:36
|vpiRange:
\_range: , line:37
|vpiLeftRange:
\_constant: , line:37
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:37
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiPort:
\_port: (read_data), line:38, parent:addr_table
|vpiName:read_data
|vpiDirection:2
|vpiHighConn:
\_ref_obj: (read_data), line:72
|vpiName:read_data
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (read_data), line:38, parent:addr_table
|vpiName:read_data
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_table_banks.branch_table_banks[0].addr_table.read_data
|vpiNetType:36
|vpiRange:
\_range: , line:38
|vpiLeftRange:
\_constant: , line:38
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:38
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (clk), line:32, parent:addr_table
|vpiNet:
\_logic_net: (write_addr), line:33, parent:addr_table
|vpiNet:
\_logic_net: (write_en), line:34, parent:addr_table
|vpiNet:
\_logic_net: (read_addr), line:35, parent:addr_table
|vpiNet:
\_logic_net: (read_en), line:36, parent:addr_table
|vpiNet:
\_logic_net: (write_data), line:37, parent:addr_table
|vpiNet:
\_logic_net: (read_data), line:38, parent:addr_table
|vpiArrayNet:
\_array_net: (branch_ram), line:40, parent:addr_table
|vpiName:branch_ram
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_table_banks.branch_table_banks[0].addr_table.branch_ram
|vpiSize:4
|vpiNet:
\_logic_net: , parent:branch_ram
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_table_banks.branch_table_banks[0].addr_table.branch_ram
|vpiNetType:36
|vpiRange:
\_range: , line:40
|vpiLeftRange:
\_constant: , line:40
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:40
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiRange:
\_range: , line:40
|vpiLeftRange:
\_constant: , line:40
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiRightRange:
\_constant: , line:40
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiParameter:
\_parameter: (ALU_UNIT_WB_ID), line:190
|vpiName:ALU_UNIT_WB_ID
|INT:32
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (BRANCH_PREDICTOR_WAYS), line:159
|vpiName:BRANCH_PREDICTOR_WAYS
|INT:9
|vpiParameter:
\_parameter: (BRANCH_TABLE_ENTRIES), line:160
|vpiName:BRANCH_TABLE_ENTRIES
|INT:4
|vpiParameter:
\_parameter: (BRANCH_UNIT_ID), line:195
|vpiName:BRANCH_UNIT_ID
|INT:8
|vpiParameter:
\_parameter: (BUS_ADDR_H), line:107
|vpiName:BUS_ADDR_H
|INT:1
|vpiParameter:
\_parameter: (BUS_ADDR_L), line:106
|vpiName:BUS_ADDR_L
|INT:0
|vpiParameter:
\_parameter: (BUS_BIT_CHECK), line:108
|vpiName:BUS_BIT_CHECK
|INT:1
|vpiParameter:
\_parameter: (BUS_TYPE), line:89
|vpiName:BUS_TYPE
|INT:5
|vpiParameter:
\_parameter: (COUNTER_W), line:42
|vpiName:COUNTER_W
|INT:33
|vpiParameter:
\_parameter: (CPU_ID), line:38
|vpiName:CPU_ID
|INT:0
|vpiParameter:
\_parameter: (C_DATA_WIDTH), line:71
|vpiName:C_DATA_WIDTH
|INT:32
|vpiParameter:
\_parameter: (C_DEPTH), line:71
|vpiName:C_DEPTH
|INT:4
|vpiParameter:
\_parameter: (C_M_AXI_ADDR_WIDTH), line:113
|vpiName:C_M_AXI_ADDR_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_DATA_WIDTH), line:114
|vpiName:C_M_AXI_DATA_WIDTH
|INT:1
|vpiParameter:
\_parameter: (DCACHE_LINES), line:133
|vpiName:DCACHE_LINES
|INT:-2146435073
|vpiParameter:
\_parameter: (DCACHE_LINE_ADDR_W), line:135
|vpiName:DCACHE_LINE_ADDR_W
|INT:1073741824
|vpiParameter:
\_parameter: (DCACHE_LINE_W), line:136
|vpiName:DCACHE_LINE_W
|INT:1342177279
|vpiParameter:
\_parameter: (DCACHE_SUB_LINE_ADDR_W), line:137
|vpiName:DCACHE_SUB_LINE_ADDR_W
|INT:4
|vpiParameter:
\_parameter: (DCACHE_TAG_W), line:138
|vpiName:DCACHE_TAG_W
|INT:1610612736
|vpiParameter:
\_parameter: (DCACHE_WAYS), line:134
|vpiName:DCACHE_WAYS
|INT:4
|vpiParameter:
\_parameter: (DIV_ALGORITHM), line:67
|vpiName:DIV_ALGORITHM
|INT:0
|vpiParameter:
\_parameter: (DIV_UNIT_WB_ID), line:192
|vpiName:DIV_UNIT_WB_ID
|INT:2
|vpiParameter:
\_parameter: (DTLB_DEPTH), line:152
|vpiName:DTLB_DEPTH
|INT:512
|vpiParameter:
\_parameter: (DTLB_WAYS), line:151
|vpiName:DTLB_WAYS
|INT:32
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (ENABLE_M_MODE), line:34
|vpiName:ENABLE_M_MODE
|INT:1
|vpiParameter:
\_parameter: (ENABLE_S_MODE), line:36
|vpiName:ENABLE_S_MODE
|INT:0
|vpiParameter:
\_parameter: (ENABLE_TRACE_INTERFACE), line:172
|vpiName:ENABLE_TRACE_INTERFACE
|INT:2
|vpiParameter:
\_parameter: (FETCH_BUFFER_DEPTH), line:168
|vpiName:FETCH_BUFFER_DEPTH
|INT:512
|vpiParameter:
\_parameter: (FPGA_VENDOR), line:27
|vpiName:FPGA_VENDOR
|STRING:"xilinx"
|vpiParameter:
\_parameter: (GC_UNIT_ID), line:196
|vpiName:GC_UNIT_ID
|INT:4
|vpiParameter:
\_parameter: (ICACHE_LINES), line:121
|vpiName:ICACHE_LINES
|INT:2
|vpiParameter:
\_parameter: (ICACHE_LINE_ADDR_W), line:123
|vpiName:ICACHE_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_LINE_W), line:124
|vpiName:ICACHE_LINE_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_SUB_LINE_ADDR_W), line:125
|vpiName:ICACHE_SUB_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_TAG_W), line:126
|vpiName:ICACHE_TAG_W
|INT:-2147483648
|vpiParameter:
\_parameter: (ICACHE_WAYS), line:122
|vpiName:ICACHE_WAYS
|INT:1
|vpiParameter:
\_parameter: (ITLB_DEPTH), line:146
|vpiName:ITLB_DEPTH
|INT:32
|vpiParameter:
\_parameter: (ITLB_WAYS), line:145
|vpiName:ITLB_WAYS
|INT:4
|vpiParameter:
\_parameter: (L1_CONNECTIONS), line:177
|vpiName:L1_CONNECTIONS
|INT:9
|vpiParameter:
\_parameter: (L1_DCACHE_ID), line:178
|vpiName:L1_DCACHE_ID
|INT:4
|vpiParameter:
\_parameter: (L1_DMMU_ID), line:179
|vpiName:L1_DMMU_ID
|INT:2
|vpiParameter:
\_parameter: (L1_ICACHE_ID), line:180
|vpiName:L1_ICACHE_ID
|INT:19
|vpiParameter:
\_parameter: (L1_IMMU_ID), line:181
|vpiName:L1_IMMU_ID
|INT:0
|vpiParameter:
\_parameter: (LS_UNIT_WB_ID), line:191
|vpiName:LS_UNIT_WB_ID
|INT:1
|vpiParameter:
\_parameter: (MAX_INFLIGHT_COUNT), line:167
|vpiName:MAX_INFLIGHT_COUNT
|INT:19
|vpiParameter:
\_parameter: (MEMORY_ADDR_H), line:103
|vpiName:MEMORY_ADDR_H
|INT:12
|vpiParameter:
\_parameter: (MEMORY_ADDR_L), line:102
|vpiName:MEMORY_ADDR_L
|INT:11
|vpiParameter:
\_parameter: (MEMORY_BIT_CHECK), line:104
|vpiName:MEMORY_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (MUL_UNIT_WB_ID), line:193
|vpiName:MUL_UNIT_WB_ID
|INT:512
|vpiParameter:
\_parameter: (NUM_UNITS), line:188
|vpiName:NUM_UNITS
|INT:2
|vpiParameter:
\_parameter: (NUM_WB_UNITS), line:186
|vpiName:NUM_WB_UNITS
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (RAS_DEPTH), line:161
|vpiName:RAS_DEPTH
|INT:2
|vpiParameter:
\_parameter: (RESET_VEC), line:39
|vpiName:RESET_VEC
|INT:-2147483648
|vpiParameter:
\_parameter: (SCRATCH_ADDR_H), line:99
|vpiName:SCRATCH_ADDR_H
|INT:9
|vpiParameter:
\_parameter: (SCRATCH_ADDR_L), line:98
|vpiName:SCRATCH_ADDR_L
|INT:8
|vpiParameter:
\_parameter: (SCRATCH_BIT_CHECK), line:100
|vpiName:SCRATCH_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (USE_AMO), line:70
|vpiName:USE_AMO
|INT:1
|vpiParameter:
\_parameter: (USE_BRANCH_PREDICTOR), line:158
|vpiName:USE_BRANCH_PREDICTOR
|INT:2
|vpiParameter:
\_parameter: (USE_BUS), line:88
|vpiName:USE_BUS
|INT:4
|vpiParameter:
\_parameter: (USE_DCACHE), line:92
|vpiName:USE_DCACHE
|INT:6
|vpiParameter:
\_parameter: (USE_DIV), line:49
|vpiName:USE_DIV
|INT:1
|vpiParameter:
\_parameter: (USE_DTAG_INVALIDATIONS), line:140
|vpiName:USE_DTAG_INVALIDATIONS
|INT:1879048191
|vpiParameter:
\_parameter: (USE_D_SCRATCH_MEM), line:79
|vpiName:USE_D_SCRATCH_MEM
|INT:3
|vpiParameter:
\_parameter: (USE_ICACHE), line:93
|vpiName:USE_ICACHE
|INT:7
|vpiParameter:
\_parameter: (USE_I_SCRATCH_MEM), line:78
|vpiName:USE_I_SCRATCH_MEM
|INT:2
|vpiParameter:
\_parameter: (USE_MUL), line:48
|vpiName:USE_MUL
|INT:1
|vpiParameter:
\_parameter: (WB_UNITS_WIDTH), line:187
|vpiName:WB_UNITS_WIDTH
|INT:32
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiParameter:
\_parameter: (ALU_UNIT_WB_ID), line:190
|vpiName:ALU_UNIT_WB_ID
|INT:32
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (BRANCH_PREDICTOR_WAYS), line:159
|vpiName:BRANCH_PREDICTOR_WAYS
|INT:9
|vpiParameter:
\_parameter: (BRANCH_TABLE_ENTRIES), line:160
|vpiName:BRANCH_TABLE_ENTRIES
|INT:4
|vpiParameter:
\_parameter: (BRANCH_UNIT_ID), line:195
|vpiName:BRANCH_UNIT_ID
|INT:8
|vpiParameter:
\_parameter: (BUS_ADDR_H), line:107
|vpiName:BUS_ADDR_H
|INT:1
|vpiParameter:
\_parameter: (BUS_ADDR_L), line:106
|vpiName:BUS_ADDR_L
|INT:0
|vpiParameter:
\_parameter: (BUS_BIT_CHECK), line:108
|vpiName:BUS_BIT_CHECK
|INT:1
|vpiParameter:
\_parameter: (BUS_TYPE), line:89
|vpiName:BUS_TYPE
|INT:5
|vpiParameter:
\_parameter: (COUNTER_W), line:42
|vpiName:COUNTER_W
|INT:33
|vpiParameter:
\_parameter: (CPU_ID), line:38
|vpiName:CPU_ID
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_ADDR_WIDTH), line:113
|vpiName:C_M_AXI_ADDR_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_DATA_WIDTH), line:114
|vpiName:C_M_AXI_DATA_WIDTH
|INT:1
|vpiParameter:
\_parameter: (DCACHE_LINES), line:133
|vpiName:DCACHE_LINES
|INT:-2146435073
|vpiParameter:
\_parameter: (DCACHE_LINE_ADDR_W), line:135
|vpiName:DCACHE_LINE_ADDR_W
|INT:1073741824
|vpiParameter:
\_parameter: (DCACHE_LINE_W), line:136
|vpiName:DCACHE_LINE_W
|INT:1342177279
|vpiParameter:
\_parameter: (DCACHE_SUB_LINE_ADDR_W), line:137
|vpiName:DCACHE_SUB_LINE_ADDR_W
|INT:4
|vpiParameter:
\_parameter: (DCACHE_TAG_W), line:138
|vpiName:DCACHE_TAG_W
|INT:1610612736
|vpiParameter:
\_parameter: (DCACHE_WAYS), line:134
|vpiName:DCACHE_WAYS
|INT:4
|vpiParameter:
\_parameter: (DIV_ALGORITHM), line:67
|vpiName:DIV_ALGORITHM
|INT:0
|vpiParameter:
\_parameter: (DIV_UNIT_WB_ID), line:192
|vpiName:DIV_UNIT_WB_ID
|INT:2
|vpiParameter:
\_parameter: (DTLB_DEPTH), line:152
|vpiName:DTLB_DEPTH
|INT:512
|vpiParameter:
\_parameter: (DTLB_WAYS), line:151
|vpiName:DTLB_WAYS
|INT:32
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (ENABLE_M_MODE), line:34
|vpiName:ENABLE_M_MODE
|INT:1
|vpiParameter:
\_parameter: (ENABLE_S_MODE), line:36
|vpiName:ENABLE_S_MODE
|INT:0
|vpiParameter:
\_parameter: (ENABLE_TRACE_INTERFACE), line:172
|vpiName:ENABLE_TRACE_INTERFACE
|INT:2
|vpiParameter:
\_parameter: (FETCH_BUFFER_DEPTH), line:168
|vpiName:FETCH_BUFFER_DEPTH
|INT:512
|vpiParameter:
\_parameter: (FPGA_VENDOR), line:27
|vpiName:FPGA_VENDOR
|STRING:"xilinx"
|vpiParameter:
\_parameter: (GC_UNIT_ID), line:196
|vpiName:GC_UNIT_ID
|INT:4
|vpiParameter:
\_parameter: (ICACHE_LINES), line:121
|vpiName:ICACHE_LINES
|INT:2
|vpiParameter:
\_parameter: (ICACHE_LINE_ADDR_W), line:123
|vpiName:ICACHE_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_LINE_W), line:124
|vpiName:ICACHE_LINE_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_SUB_LINE_ADDR_W), line:125
|vpiName:ICACHE_SUB_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_TAG_W), line:126
|vpiName:ICACHE_TAG_W
|INT:-2147483648
|vpiParameter:
\_parameter: (ICACHE_WAYS), line:122
|vpiName:ICACHE_WAYS
|INT:1
|vpiParameter:
\_parameter: (ITLB_DEPTH), line:146
|vpiName:ITLB_DEPTH
|INT:32
|vpiParameter:
\_parameter: (ITLB_WAYS), line:145
|vpiName:ITLB_WAYS
|INT:4
|vpiParameter:
\_parameter: (L1_CONNECTIONS), line:177
|vpiName:L1_CONNECTIONS
|INT:9
|vpiParameter:
\_parameter: (L1_DCACHE_ID), line:178
|vpiName:L1_DCACHE_ID
|INT:4
|vpiParameter:
\_parameter: (L1_DMMU_ID), line:179
|vpiName:L1_DMMU_ID
|INT:2
|vpiParameter:
\_parameter: (L1_ICACHE_ID), line:180
|vpiName:L1_ICACHE_ID
|INT:19
|vpiParameter:
\_parameter: (L1_IMMU_ID), line:181
|vpiName:L1_IMMU_ID
|INT:0
|vpiParameter:
\_parameter: (LS_UNIT_WB_ID), line:191
|vpiName:LS_UNIT_WB_ID
|INT:1
|vpiParameter:
\_parameter: (MAX_INFLIGHT_COUNT), line:167
|vpiName:MAX_INFLIGHT_COUNT
|INT:19
|vpiParameter:
\_parameter: (MEMORY_ADDR_H), line:103
|vpiName:MEMORY_ADDR_H
|INT:12
|vpiParameter:
\_parameter: (MEMORY_ADDR_L), line:102
|vpiName:MEMORY_ADDR_L
|INT:11
|vpiParameter:
\_parameter: (MEMORY_BIT_CHECK), line:104
|vpiName:MEMORY_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (MUL_UNIT_WB_ID), line:193
|vpiName:MUL_UNIT_WB_ID
|INT:512
|vpiParameter:
\_parameter: (NUM_UNITS), line:188
|vpiName:NUM_UNITS
|INT:2
|vpiParameter:
\_parameter: (NUM_WB_UNITS), line:186
|vpiName:NUM_WB_UNITS
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (RAS_DEPTH), line:161
|vpiName:RAS_DEPTH
|INT:2
|vpiParameter:
\_parameter: (RESET_VEC), line:39
|vpiName:RESET_VEC
|INT:-2147483648
|vpiParameter:
\_parameter: (SCRATCH_ADDR_H), line:99
|vpiName:SCRATCH_ADDR_H
|INT:9
|vpiParameter:
\_parameter: (SCRATCH_ADDR_L), line:98
|vpiName:SCRATCH_ADDR_L
|INT:8
|vpiParameter:
\_parameter: (SCRATCH_BIT_CHECK), line:100
|vpiName:SCRATCH_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (USE_AMO), line:70
|vpiName:USE_AMO
|INT:1
|vpiParameter:
\_parameter: (USE_BRANCH_PREDICTOR), line:158
|vpiName:USE_BRANCH_PREDICTOR
|INT:2
|vpiParameter:
\_parameter: (USE_BUS), line:88
|vpiName:USE_BUS
|INT:4
|vpiParameter:
\_parameter: (USE_DCACHE), line:92
|vpiName:USE_DCACHE
|INT:6
|vpiParameter:
\_parameter: (USE_DIV), line:49
|vpiName:USE_DIV
|INT:1
|vpiParameter:
\_parameter: (USE_DTAG_INVALIDATIONS), line:140
|vpiName:USE_DTAG_INVALIDATIONS
|INT:1879048191
|vpiParameter:
\_parameter: (USE_D_SCRATCH_MEM), line:79
|vpiName:USE_D_SCRATCH_MEM
|INT:3
|vpiParameter:
\_parameter: (USE_ICACHE), line:93
|vpiName:USE_ICACHE
|INT:7
|vpiParameter:
\_parameter: (USE_I_SCRATCH_MEM), line:78
|vpiName:USE_I_SCRATCH_MEM
|INT:2
|vpiParameter:
\_parameter: (USE_MUL), line:48
|vpiName:USE_MUL
|INT:1
|vpiParameter:
\_parameter: (WB_UNITS_WIDTH), line:187
|vpiName:WB_UNITS_WIDTH
|INT:32
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiParameter:
\_parameter: (i), line:70
|vpiName:i
|INT:0
|vpiGenScopeArray:
\_gen_scope_array: (branch_table_banks[1]), line:70
|vpiName:branch_table_banks[1]
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_table_banks.branch_table_banks[1]
|vpiGenScope:
\_gen_scope: , parent:branch_table_banks[1]
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_table_banks.branch_table_banks[1]
|vpiModule:
\_module: work@branch_predictor_ram (addr_table), file:third_party/cores/taiga/core/branch_predictor.sv, line:71
|vpiDefName:work@branch_predictor_ram
|vpiName:addr_table
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_table_banks.branch_table_banks[1].addr_table
|vpiPort:
\_port: (clk), line:32, parent:addr_table
|vpiName:clk
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (clk), line:72
|vpiName:clk
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (clk), line:32, parent:addr_table
|vpiName:clk
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_table_banks.branch_table_banks[1].addr_table.clk
|vpiNetType:36
|vpiPort:
\_port: (write_addr), line:33, parent:addr_table
|vpiName:write_addr
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (write_addr), line:72
|vpiName:write_addr
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (write_addr), line:33, parent:addr_table
|vpiName:write_addr
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_table_banks.branch_table_banks[1].addr_table.write_addr
|vpiNetType:36
|vpiRange:
\_range: , line:33
|vpiLeftRange:
\_constant: , line:33
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:33
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiPort:
\_port: (write_en), line:34, parent:addr_table
|vpiName:write_en
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (write_en), line:72
|vpiName:write_en
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (write_en), line:34, parent:addr_table
|vpiName:write_en
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_table_banks.branch_table_banks[1].addr_table.write_en
|vpiNetType:36
|vpiPort:
\_port: (read_addr), line:35, parent:addr_table
|vpiName:read_addr
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (read_addr), line:72
|vpiName:read_addr
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (read_addr), line:35, parent:addr_table
|vpiName:read_addr
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_table_banks.branch_table_banks[1].addr_table.read_addr
|vpiNetType:36
|vpiRange:
\_range: , line:35
|vpiLeftRange:
\_constant: , line:35
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:35
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiPort:
\_port: (read_en), line:36, parent:addr_table
|vpiName:read_en
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (read_en), line:72
|vpiName:read_en
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (read_en), line:36, parent:addr_table
|vpiName:read_en
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_table_banks.branch_table_banks[1].addr_table.read_en
|vpiNetType:36
|vpiPort:
\_port: (write_data), line:37, parent:addr_table
|vpiName:write_data
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (write_data), line:72
|vpiName:write_data
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (write_data), line:37, parent:addr_table
|vpiName:write_data
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_table_banks.branch_table_banks[1].addr_table.write_data
|vpiNetType:36
|vpiRange:
\_range: , line:37
|vpiLeftRange:
\_constant: , line:37
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:37
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiPort:
\_port: (read_data), line:38, parent:addr_table
|vpiName:read_data
|vpiDirection:2
|vpiHighConn:
\_ref_obj: (read_data), line:72
|vpiName:read_data
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (read_data), line:38, parent:addr_table
|vpiName:read_data
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_table_banks.branch_table_banks[1].addr_table.read_data
|vpiNetType:36
|vpiRange:
\_range: , line:38
|vpiLeftRange:
\_constant: , line:38
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:38
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (clk), line:32, parent:addr_table
|vpiNet:
\_logic_net: (write_addr), line:33, parent:addr_table
|vpiNet:
\_logic_net: (write_en), line:34, parent:addr_table
|vpiNet:
\_logic_net: (read_addr), line:35, parent:addr_table
|vpiNet:
\_logic_net: (read_en), line:36, parent:addr_table
|vpiNet:
\_logic_net: (write_data), line:37, parent:addr_table
|vpiNet:
\_logic_net: (read_data), line:38, parent:addr_table
|vpiArrayNet:
\_array_net: (branch_ram), line:40, parent:addr_table
|vpiName:branch_ram
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_table_banks.branch_table_banks[1].addr_table.branch_ram
|vpiSize:4
|vpiNet:
\_logic_net: , parent:branch_ram
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_table_banks.branch_table_banks[1].addr_table.branch_ram
|vpiNetType:36
|vpiRange:
\_range: , line:40
|vpiLeftRange:
\_constant: , line:40
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:40
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiRange:
\_range: , line:40
|vpiLeftRange:
\_constant: , line:40
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiRightRange:
\_constant: , line:40
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiParameter:
\_parameter: (ALU_UNIT_WB_ID), line:190
|vpiName:ALU_UNIT_WB_ID
|INT:32
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (BRANCH_PREDICTOR_WAYS), line:159
|vpiName:BRANCH_PREDICTOR_WAYS
|INT:9
|vpiParameter:
\_parameter: (BRANCH_TABLE_ENTRIES), line:160
|vpiName:BRANCH_TABLE_ENTRIES
|INT:4
|vpiParameter:
\_parameter: (BRANCH_UNIT_ID), line:195
|vpiName:BRANCH_UNIT_ID
|INT:8
|vpiParameter:
\_parameter: (BUS_ADDR_H), line:107
|vpiName:BUS_ADDR_H
|INT:1
|vpiParameter:
\_parameter: (BUS_ADDR_L), line:106
|vpiName:BUS_ADDR_L
|INT:0
|vpiParameter:
\_parameter: (BUS_BIT_CHECK), line:108
|vpiName:BUS_BIT_CHECK
|INT:1
|vpiParameter:
\_parameter: (BUS_TYPE), line:89
|vpiName:BUS_TYPE
|INT:5
|vpiParameter:
\_parameter: (COUNTER_W), line:42
|vpiName:COUNTER_W
|INT:33
|vpiParameter:
\_parameter: (CPU_ID), line:38
|vpiName:CPU_ID
|INT:0
|vpiParameter:
\_parameter: (C_DATA_WIDTH), line:71
|vpiName:C_DATA_WIDTH
|INT:32
|vpiParameter:
\_parameter: (C_DEPTH), line:71
|vpiName:C_DEPTH
|INT:4
|vpiParameter:
\_parameter: (C_M_AXI_ADDR_WIDTH), line:113
|vpiName:C_M_AXI_ADDR_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_DATA_WIDTH), line:114
|vpiName:C_M_AXI_DATA_WIDTH
|INT:1
|vpiParameter:
\_parameter: (DCACHE_LINES), line:133
|vpiName:DCACHE_LINES
|INT:-2146435073
|vpiParameter:
\_parameter: (DCACHE_LINE_ADDR_W), line:135
|vpiName:DCACHE_LINE_ADDR_W
|INT:1073741824
|vpiParameter:
\_parameter: (DCACHE_LINE_W), line:136
|vpiName:DCACHE_LINE_W
|INT:1342177279
|vpiParameter:
\_parameter: (DCACHE_SUB_LINE_ADDR_W), line:137
|vpiName:DCACHE_SUB_LINE_ADDR_W
|INT:4
|vpiParameter:
\_parameter: (DCACHE_TAG_W), line:138
|vpiName:DCACHE_TAG_W
|INT:1610612736
|vpiParameter:
\_parameter: (DCACHE_WAYS), line:134
|vpiName:DCACHE_WAYS
|INT:4
|vpiParameter:
\_parameter: (DIV_ALGORITHM), line:67
|vpiName:DIV_ALGORITHM
|INT:0
|vpiParameter:
\_parameter: (DIV_UNIT_WB_ID), line:192
|vpiName:DIV_UNIT_WB_ID
|INT:2
|vpiParameter:
\_parameter: (DTLB_DEPTH), line:152
|vpiName:DTLB_DEPTH
|INT:512
|vpiParameter:
\_parameter: (DTLB_WAYS), line:151
|vpiName:DTLB_WAYS
|INT:32
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (ENABLE_M_MODE), line:34
|vpiName:ENABLE_M_MODE
|INT:1
|vpiParameter:
\_parameter: (ENABLE_S_MODE), line:36
|vpiName:ENABLE_S_MODE
|INT:0
|vpiParameter:
\_parameter: (ENABLE_TRACE_INTERFACE), line:172
|vpiName:ENABLE_TRACE_INTERFACE
|INT:2
|vpiParameter:
\_parameter: (FETCH_BUFFER_DEPTH), line:168
|vpiName:FETCH_BUFFER_DEPTH
|INT:512
|vpiParameter:
\_parameter: (FPGA_VENDOR), line:27
|vpiName:FPGA_VENDOR
|STRING:"xilinx"
|vpiParameter:
\_parameter: (GC_UNIT_ID), line:196
|vpiName:GC_UNIT_ID
|INT:4
|vpiParameter:
\_parameter: (ICACHE_LINES), line:121
|vpiName:ICACHE_LINES
|INT:2
|vpiParameter:
\_parameter: (ICACHE_LINE_ADDR_W), line:123
|vpiName:ICACHE_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_LINE_W), line:124
|vpiName:ICACHE_LINE_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_SUB_LINE_ADDR_W), line:125
|vpiName:ICACHE_SUB_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_TAG_W), line:126
|vpiName:ICACHE_TAG_W
|INT:-2147483648
|vpiParameter:
\_parameter: (ICACHE_WAYS), line:122
|vpiName:ICACHE_WAYS
|INT:1
|vpiParameter:
\_parameter: (ITLB_DEPTH), line:146
|vpiName:ITLB_DEPTH
|INT:32
|vpiParameter:
\_parameter: (ITLB_WAYS), line:145
|vpiName:ITLB_WAYS
|INT:4
|vpiParameter:
\_parameter: (L1_CONNECTIONS), line:177
|vpiName:L1_CONNECTIONS
|INT:9
|vpiParameter:
\_parameter: (L1_DCACHE_ID), line:178
|vpiName:L1_DCACHE_ID
|INT:4
|vpiParameter:
\_parameter: (L1_DMMU_ID), line:179
|vpiName:L1_DMMU_ID
|INT:2
|vpiParameter:
\_parameter: (L1_ICACHE_ID), line:180
|vpiName:L1_ICACHE_ID
|INT:19
|vpiParameter:
\_parameter: (L1_IMMU_ID), line:181
|vpiName:L1_IMMU_ID
|INT:0
|vpiParameter:
\_parameter: (LS_UNIT_WB_ID), line:191
|vpiName:LS_UNIT_WB_ID
|INT:1
|vpiParameter:
\_parameter: (MAX_INFLIGHT_COUNT), line:167
|vpiName:MAX_INFLIGHT_COUNT
|INT:19
|vpiParameter:
\_parameter: (MEMORY_ADDR_H), line:103
|vpiName:MEMORY_ADDR_H
|INT:12
|vpiParameter:
\_parameter: (MEMORY_ADDR_L), line:102
|vpiName:MEMORY_ADDR_L
|INT:11
|vpiParameter:
\_parameter: (MEMORY_BIT_CHECK), line:104
|vpiName:MEMORY_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (MUL_UNIT_WB_ID), line:193
|vpiName:MUL_UNIT_WB_ID
|INT:512
|vpiParameter:
\_parameter: (NUM_UNITS), line:188
|vpiName:NUM_UNITS
|INT:2
|vpiParameter:
\_parameter: (NUM_WB_UNITS), line:186
|vpiName:NUM_WB_UNITS
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (RAS_DEPTH), line:161
|vpiName:RAS_DEPTH
|INT:2
|vpiParameter:
\_parameter: (RESET_VEC), line:39
|vpiName:RESET_VEC
|INT:-2147483648
|vpiParameter:
\_parameter: (SCRATCH_ADDR_H), line:99
|vpiName:SCRATCH_ADDR_H
|INT:9
|vpiParameter:
\_parameter: (SCRATCH_ADDR_L), line:98
|vpiName:SCRATCH_ADDR_L
|INT:8
|vpiParameter:
\_parameter: (SCRATCH_BIT_CHECK), line:100
|vpiName:SCRATCH_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (USE_AMO), line:70
|vpiName:USE_AMO
|INT:1
|vpiParameter:
\_parameter: (USE_BRANCH_PREDICTOR), line:158
|vpiName:USE_BRANCH_PREDICTOR
|INT:2
|vpiParameter:
\_parameter: (USE_BUS), line:88
|vpiName:USE_BUS
|INT:4
|vpiParameter:
\_parameter: (USE_DCACHE), line:92
|vpiName:USE_DCACHE
|INT:6
|vpiParameter:
\_parameter: (USE_DIV), line:49
|vpiName:USE_DIV
|INT:1
|vpiParameter:
\_parameter: (USE_DTAG_INVALIDATIONS), line:140
|vpiName:USE_DTAG_INVALIDATIONS
|INT:1879048191
|vpiParameter:
\_parameter: (USE_D_SCRATCH_MEM), line:79
|vpiName:USE_D_SCRATCH_MEM
|INT:3
|vpiParameter:
\_parameter: (USE_ICACHE), line:93
|vpiName:USE_ICACHE
|INT:7
|vpiParameter:
\_parameter: (USE_I_SCRATCH_MEM), line:78
|vpiName:USE_I_SCRATCH_MEM
|INT:2
|vpiParameter:
\_parameter: (USE_MUL), line:48
|vpiName:USE_MUL
|INT:1
|vpiParameter:
\_parameter: (WB_UNITS_WIDTH), line:187
|vpiName:WB_UNITS_WIDTH
|INT:32
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiParameter:
\_parameter: (ALU_UNIT_WB_ID), line:190
|vpiName:ALU_UNIT_WB_ID
|INT:32
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (BRANCH_PREDICTOR_WAYS), line:159
|vpiName:BRANCH_PREDICTOR_WAYS
|INT:9
|vpiParameter:
\_parameter: (BRANCH_TABLE_ENTRIES), line:160
|vpiName:BRANCH_TABLE_ENTRIES
|INT:4
|vpiParameter:
\_parameter: (BRANCH_UNIT_ID), line:195
|vpiName:BRANCH_UNIT_ID
|INT:8
|vpiParameter:
\_parameter: (BUS_ADDR_H), line:107
|vpiName:BUS_ADDR_H
|INT:1
|vpiParameter:
\_parameter: (BUS_ADDR_L), line:106
|vpiName:BUS_ADDR_L
|INT:0
|vpiParameter:
\_parameter: (BUS_BIT_CHECK), line:108
|vpiName:BUS_BIT_CHECK
|INT:1
|vpiParameter:
\_parameter: (BUS_TYPE), line:89
|vpiName:BUS_TYPE
|INT:5
|vpiParameter:
\_parameter: (COUNTER_W), line:42
|vpiName:COUNTER_W
|INT:33
|vpiParameter:
\_parameter: (CPU_ID), line:38
|vpiName:CPU_ID
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_ADDR_WIDTH), line:113
|vpiName:C_M_AXI_ADDR_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_DATA_WIDTH), line:114
|vpiName:C_M_AXI_DATA_WIDTH
|INT:1
|vpiParameter:
\_parameter: (DCACHE_LINES), line:133
|vpiName:DCACHE_LINES
|INT:-2146435073
|vpiParameter:
\_parameter: (DCACHE_LINE_ADDR_W), line:135
|vpiName:DCACHE_LINE_ADDR_W
|INT:1073741824
|vpiParameter:
\_parameter: (DCACHE_LINE_W), line:136
|vpiName:DCACHE_LINE_W
|INT:1342177279
|vpiParameter:
\_parameter: (DCACHE_SUB_LINE_ADDR_W), line:137
|vpiName:DCACHE_SUB_LINE_ADDR_W
|INT:4
|vpiParameter:
\_parameter: (DCACHE_TAG_W), line:138
|vpiName:DCACHE_TAG_W
|INT:1610612736
|vpiParameter:
\_parameter: (DCACHE_WAYS), line:134
|vpiName:DCACHE_WAYS
|INT:4
|vpiParameter:
\_parameter: (DIV_ALGORITHM), line:67
|vpiName:DIV_ALGORITHM
|INT:0
|vpiParameter:
\_parameter: (DIV_UNIT_WB_ID), line:192
|vpiName:DIV_UNIT_WB_ID
|INT:2
|vpiParameter:
\_parameter: (DTLB_DEPTH), line:152
|vpiName:DTLB_DEPTH
|INT:512
|vpiParameter:
\_parameter: (DTLB_WAYS), line:151
|vpiName:DTLB_WAYS
|INT:32
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (ENABLE_M_MODE), line:34
|vpiName:ENABLE_M_MODE
|INT:1
|vpiParameter:
\_parameter: (ENABLE_S_MODE), line:36
|vpiName:ENABLE_S_MODE
|INT:0
|vpiParameter:
\_parameter: (ENABLE_TRACE_INTERFACE), line:172
|vpiName:ENABLE_TRACE_INTERFACE
|INT:2
|vpiParameter:
\_parameter: (FETCH_BUFFER_DEPTH), line:168
|vpiName:FETCH_BUFFER_DEPTH
|INT:512
|vpiParameter:
\_parameter: (FPGA_VENDOR), line:27
|vpiName:FPGA_VENDOR
|STRING:"xilinx"
|vpiParameter:
\_parameter: (GC_UNIT_ID), line:196
|vpiName:GC_UNIT_ID
|INT:4
|vpiParameter:
\_parameter: (ICACHE_LINES), line:121
|vpiName:ICACHE_LINES
|INT:2
|vpiParameter:
\_parameter: (ICACHE_LINE_ADDR_W), line:123
|vpiName:ICACHE_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_LINE_W), line:124
|vpiName:ICACHE_LINE_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_SUB_LINE_ADDR_W), line:125
|vpiName:ICACHE_SUB_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_TAG_W), line:126
|vpiName:ICACHE_TAG_W
|INT:-2147483648
|vpiParameter:
\_parameter: (ICACHE_WAYS), line:122
|vpiName:ICACHE_WAYS
|INT:1
|vpiParameter:
\_parameter: (ITLB_DEPTH), line:146
|vpiName:ITLB_DEPTH
|INT:32
|vpiParameter:
\_parameter: (ITLB_WAYS), line:145
|vpiName:ITLB_WAYS
|INT:4
|vpiParameter:
\_parameter: (L1_CONNECTIONS), line:177
|vpiName:L1_CONNECTIONS
|INT:9
|vpiParameter:
\_parameter: (L1_DCACHE_ID), line:178
|vpiName:L1_DCACHE_ID
|INT:4
|vpiParameter:
\_parameter: (L1_DMMU_ID), line:179
|vpiName:L1_DMMU_ID
|INT:2
|vpiParameter:
\_parameter: (L1_ICACHE_ID), line:180
|vpiName:L1_ICACHE_ID
|INT:19
|vpiParameter:
\_parameter: (L1_IMMU_ID), line:181
|vpiName:L1_IMMU_ID
|INT:0
|vpiParameter:
\_parameter: (LS_UNIT_WB_ID), line:191
|vpiName:LS_UNIT_WB_ID
|INT:1
|vpiParameter:
\_parameter: (MAX_INFLIGHT_COUNT), line:167
|vpiName:MAX_INFLIGHT_COUNT
|INT:19
|vpiParameter:
\_parameter: (MEMORY_ADDR_H), line:103
|vpiName:MEMORY_ADDR_H
|INT:12
|vpiParameter:
\_parameter: (MEMORY_ADDR_L), line:102
|vpiName:MEMORY_ADDR_L
|INT:11
|vpiParameter:
\_parameter: (MEMORY_BIT_CHECK), line:104
|vpiName:MEMORY_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (MUL_UNIT_WB_ID), line:193
|vpiName:MUL_UNIT_WB_ID
|INT:512
|vpiParameter:
\_parameter: (NUM_UNITS), line:188
|vpiName:NUM_UNITS
|INT:2
|vpiParameter:
\_parameter: (NUM_WB_UNITS), line:186
|vpiName:NUM_WB_UNITS
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (RAS_DEPTH), line:161
|vpiName:RAS_DEPTH
|INT:2
|vpiParameter:
\_parameter: (RESET_VEC), line:39
|vpiName:RESET_VEC
|INT:-2147483648
|vpiParameter:
\_parameter: (SCRATCH_ADDR_H), line:99
|vpiName:SCRATCH_ADDR_H
|INT:9
|vpiParameter:
\_parameter: (SCRATCH_ADDR_L), line:98
|vpiName:SCRATCH_ADDR_L
|INT:8
|vpiParameter:
\_parameter: (SCRATCH_BIT_CHECK), line:100
|vpiName:SCRATCH_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (USE_AMO), line:70
|vpiName:USE_AMO
|INT:1
|vpiParameter:
\_parameter: (USE_BRANCH_PREDICTOR), line:158
|vpiName:USE_BRANCH_PREDICTOR
|INT:2
|vpiParameter:
\_parameter: (USE_BUS), line:88
|vpiName:USE_BUS
|INT:4
|vpiParameter:
\_parameter: (USE_DCACHE), line:92
|vpiName:USE_DCACHE
|INT:6
|vpiParameter:
\_parameter: (USE_DIV), line:49
|vpiName:USE_DIV
|INT:1
|vpiParameter:
\_parameter: (USE_DTAG_INVALIDATIONS), line:140
|vpiName:USE_DTAG_INVALIDATIONS
|INT:1879048191
|vpiParameter:
\_parameter: (USE_D_SCRATCH_MEM), line:79
|vpiName:USE_D_SCRATCH_MEM
|INT:3
|vpiParameter:
\_parameter: (USE_ICACHE), line:93
|vpiName:USE_ICACHE
|INT:7
|vpiParameter:
\_parameter: (USE_I_SCRATCH_MEM), line:78
|vpiName:USE_I_SCRATCH_MEM
|INT:2
|vpiParameter:
\_parameter: (USE_MUL), line:48
|vpiName:USE_MUL
|INT:1
|vpiParameter:
\_parameter: (WB_UNITS_WIDTH), line:187
|vpiName:WB_UNITS_WIDTH
|INT:32
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiParameter:
\_parameter: (i), line:70
|vpiName:i
|INT:1
|vpiGenScopeArray:
\_gen_scope_array: (branch_table_banks[2]), line:70
|vpiName:branch_table_banks[2]
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_table_banks.branch_table_banks[2]
|vpiGenScope:
\_gen_scope: , parent:branch_table_banks[2]
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_table_banks.branch_table_banks[2]
|vpiModule:
\_module: work@branch_predictor_ram (addr_table), file:third_party/cores/taiga/core/branch_predictor.sv, line:71
|vpiDefName:work@branch_predictor_ram
|vpiName:addr_table
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_table_banks.branch_table_banks[2].addr_table
|vpiPort:
\_port: (clk), line:32, parent:addr_table
|vpiName:clk
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (clk), line:72
|vpiName:clk
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (clk), line:32, parent:addr_table
|vpiName:clk
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_table_banks.branch_table_banks[2].addr_table.clk
|vpiNetType:36
|vpiPort:
\_port: (write_addr), line:33, parent:addr_table
|vpiName:write_addr
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (write_addr), line:72
|vpiName:write_addr
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (write_addr), line:33, parent:addr_table
|vpiName:write_addr
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_table_banks.branch_table_banks[2].addr_table.write_addr
|vpiNetType:36
|vpiRange:
\_range: , line:33
|vpiLeftRange:
\_constant: , line:33
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:33
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiPort:
\_port: (write_en), line:34, parent:addr_table
|vpiName:write_en
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (write_en), line:72
|vpiName:write_en
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (write_en), line:34, parent:addr_table
|vpiName:write_en
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_table_banks.branch_table_banks[2].addr_table.write_en
|vpiNetType:36
|vpiPort:
\_port: (read_addr), line:35, parent:addr_table
|vpiName:read_addr
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (read_addr), line:72
|vpiName:read_addr
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (read_addr), line:35, parent:addr_table
|vpiName:read_addr
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_table_banks.branch_table_banks[2].addr_table.read_addr
|vpiNetType:36
|vpiRange:
\_range: , line:35
|vpiLeftRange:
\_constant: , line:35
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:35
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiPort:
\_port: (read_en), line:36, parent:addr_table
|vpiName:read_en
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (read_en), line:72
|vpiName:read_en
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (read_en), line:36, parent:addr_table
|vpiName:read_en
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_table_banks.branch_table_banks[2].addr_table.read_en
|vpiNetType:36
|vpiPort:
\_port: (write_data), line:37, parent:addr_table
|vpiName:write_data
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (write_data), line:72
|vpiName:write_data
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (write_data), line:37, parent:addr_table
|vpiName:write_data
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_table_banks.branch_table_banks[2].addr_table.write_data
|vpiNetType:36
|vpiRange:
\_range: , line:37
|vpiLeftRange:
\_constant: , line:37
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:37
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiPort:
\_port: (read_data), line:38, parent:addr_table
|vpiName:read_data
|vpiDirection:2
|vpiHighConn:
\_ref_obj: (read_data), line:72
|vpiName:read_data
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (read_data), line:38, parent:addr_table
|vpiName:read_data
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_table_banks.branch_table_banks[2].addr_table.read_data
|vpiNetType:36
|vpiRange:
\_range: , line:38
|vpiLeftRange:
\_constant: , line:38
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:38
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (clk), line:32, parent:addr_table
|vpiNet:
\_logic_net: (write_addr), line:33, parent:addr_table
|vpiNet:
\_logic_net: (write_en), line:34, parent:addr_table
|vpiNet:
\_logic_net: (read_addr), line:35, parent:addr_table
|vpiNet:
\_logic_net: (read_en), line:36, parent:addr_table
|vpiNet:
\_logic_net: (write_data), line:37, parent:addr_table
|vpiNet:
\_logic_net: (read_data), line:38, parent:addr_table
|vpiArrayNet:
\_array_net: (branch_ram), line:40, parent:addr_table
|vpiName:branch_ram
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_table_banks.branch_table_banks[2].addr_table.branch_ram
|vpiSize:4
|vpiNet:
\_logic_net: , parent:branch_ram
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_table_banks.branch_table_banks[2].addr_table.branch_ram
|vpiNetType:36
|vpiRange:
\_range: , line:40
|vpiLeftRange:
\_constant: , line:40
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:40
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiRange:
\_range: , line:40
|vpiLeftRange:
\_constant: , line:40
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiRightRange:
\_constant: , line:40
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiParameter:
\_parameter: (ALU_UNIT_WB_ID), line:190
|vpiName:ALU_UNIT_WB_ID
|INT:32
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (BRANCH_PREDICTOR_WAYS), line:159
|vpiName:BRANCH_PREDICTOR_WAYS
|INT:9
|vpiParameter:
\_parameter: (BRANCH_TABLE_ENTRIES), line:160
|vpiName:BRANCH_TABLE_ENTRIES
|INT:4
|vpiParameter:
\_parameter: (BRANCH_UNIT_ID), line:195
|vpiName:BRANCH_UNIT_ID
|INT:8
|vpiParameter:
\_parameter: (BUS_ADDR_H), line:107
|vpiName:BUS_ADDR_H
|INT:1
|vpiParameter:
\_parameter: (BUS_ADDR_L), line:106
|vpiName:BUS_ADDR_L
|INT:0
|vpiParameter:
\_parameter: (BUS_BIT_CHECK), line:108
|vpiName:BUS_BIT_CHECK
|INT:1
|vpiParameter:
\_parameter: (BUS_TYPE), line:89
|vpiName:BUS_TYPE
|INT:5
|vpiParameter:
\_parameter: (COUNTER_W), line:42
|vpiName:COUNTER_W
|INT:33
|vpiParameter:
\_parameter: (CPU_ID), line:38
|vpiName:CPU_ID
|INT:0
|vpiParameter:
\_parameter: (C_DATA_WIDTH), line:71
|vpiName:C_DATA_WIDTH
|INT:32
|vpiParameter:
\_parameter: (C_DEPTH), line:71
|vpiName:C_DEPTH
|INT:4
|vpiParameter:
\_parameter: (C_M_AXI_ADDR_WIDTH), line:113
|vpiName:C_M_AXI_ADDR_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_DATA_WIDTH), line:114
|vpiName:C_M_AXI_DATA_WIDTH
|INT:1
|vpiParameter:
\_parameter: (DCACHE_LINES), line:133
|vpiName:DCACHE_LINES
|INT:-2146435073
|vpiParameter:
\_parameter: (DCACHE_LINE_ADDR_W), line:135
|vpiName:DCACHE_LINE_ADDR_W
|INT:1073741824
|vpiParameter:
\_parameter: (DCACHE_LINE_W), line:136
|vpiName:DCACHE_LINE_W
|INT:1342177279
|vpiParameter:
\_parameter: (DCACHE_SUB_LINE_ADDR_W), line:137
|vpiName:DCACHE_SUB_LINE_ADDR_W
|INT:4
|vpiParameter:
\_parameter: (DCACHE_TAG_W), line:138
|vpiName:DCACHE_TAG_W
|INT:1610612736
|vpiParameter:
\_parameter: (DCACHE_WAYS), line:134
|vpiName:DCACHE_WAYS
|INT:4
|vpiParameter:
\_parameter: (DIV_ALGORITHM), line:67
|vpiName:DIV_ALGORITHM
|INT:0
|vpiParameter:
\_parameter: (DIV_UNIT_WB_ID), line:192
|vpiName:DIV_UNIT_WB_ID
|INT:2
|vpiParameter:
\_parameter: (DTLB_DEPTH), line:152
|vpiName:DTLB_DEPTH
|INT:512
|vpiParameter:
\_parameter: (DTLB_WAYS), line:151
|vpiName:DTLB_WAYS
|INT:32
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (ENABLE_M_MODE), line:34
|vpiName:ENABLE_M_MODE
|INT:1
|vpiParameter:
\_parameter: (ENABLE_S_MODE), line:36
|vpiName:ENABLE_S_MODE
|INT:0
|vpiParameter:
\_parameter: (ENABLE_TRACE_INTERFACE), line:172
|vpiName:ENABLE_TRACE_INTERFACE
|INT:2
|vpiParameter:
\_parameter: (FETCH_BUFFER_DEPTH), line:168
|vpiName:FETCH_BUFFER_DEPTH
|INT:512
|vpiParameter:
\_parameter: (FPGA_VENDOR), line:27
|vpiName:FPGA_VENDOR
|STRING:"xilinx"
|vpiParameter:
\_parameter: (GC_UNIT_ID), line:196
|vpiName:GC_UNIT_ID
|INT:4
|vpiParameter:
\_parameter: (ICACHE_LINES), line:121
|vpiName:ICACHE_LINES
|INT:2
|vpiParameter:
\_parameter: (ICACHE_LINE_ADDR_W), line:123
|vpiName:ICACHE_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_LINE_W), line:124
|vpiName:ICACHE_LINE_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_SUB_LINE_ADDR_W), line:125
|vpiName:ICACHE_SUB_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_TAG_W), line:126
|vpiName:ICACHE_TAG_W
|INT:-2147483648
|vpiParameter:
\_parameter: (ICACHE_WAYS), line:122
|vpiName:ICACHE_WAYS
|INT:1
|vpiParameter:
\_parameter: (ITLB_DEPTH), line:146
|vpiName:ITLB_DEPTH
|INT:32
|vpiParameter:
\_parameter: (ITLB_WAYS), line:145
|vpiName:ITLB_WAYS
|INT:4
|vpiParameter:
\_parameter: (L1_CONNECTIONS), line:177
|vpiName:L1_CONNECTIONS
|INT:9
|vpiParameter:
\_parameter: (L1_DCACHE_ID), line:178
|vpiName:L1_DCACHE_ID
|INT:4
|vpiParameter:
\_parameter: (L1_DMMU_ID), line:179
|vpiName:L1_DMMU_ID
|INT:2
|vpiParameter:
\_parameter: (L1_ICACHE_ID), line:180
|vpiName:L1_ICACHE_ID
|INT:19
|vpiParameter:
\_parameter: (L1_IMMU_ID), line:181
|vpiName:L1_IMMU_ID
|INT:0
|vpiParameter:
\_parameter: (LS_UNIT_WB_ID), line:191
|vpiName:LS_UNIT_WB_ID
|INT:1
|vpiParameter:
\_parameter: (MAX_INFLIGHT_COUNT), line:167
|vpiName:MAX_INFLIGHT_COUNT
|INT:19
|vpiParameter:
\_parameter: (MEMORY_ADDR_H), line:103
|vpiName:MEMORY_ADDR_H
|INT:12
|vpiParameter:
\_parameter: (MEMORY_ADDR_L), line:102
|vpiName:MEMORY_ADDR_L
|INT:11
|vpiParameter:
\_parameter: (MEMORY_BIT_CHECK), line:104
|vpiName:MEMORY_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (MUL_UNIT_WB_ID), line:193
|vpiName:MUL_UNIT_WB_ID
|INT:512
|vpiParameter:
\_parameter: (NUM_UNITS), line:188
|vpiName:NUM_UNITS
|INT:2
|vpiParameter:
\_parameter: (NUM_WB_UNITS), line:186
|vpiName:NUM_WB_UNITS
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (RAS_DEPTH), line:161
|vpiName:RAS_DEPTH
|INT:2
|vpiParameter:
\_parameter: (RESET_VEC), line:39
|vpiName:RESET_VEC
|INT:-2147483648
|vpiParameter:
\_parameter: (SCRATCH_ADDR_H), line:99
|vpiName:SCRATCH_ADDR_H
|INT:9
|vpiParameter:
\_parameter: (SCRATCH_ADDR_L), line:98
|vpiName:SCRATCH_ADDR_L
|INT:8
|vpiParameter:
\_parameter: (SCRATCH_BIT_CHECK), line:100
|vpiName:SCRATCH_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (USE_AMO), line:70
|vpiName:USE_AMO
|INT:1
|vpiParameter:
\_parameter: (USE_BRANCH_PREDICTOR), line:158
|vpiName:USE_BRANCH_PREDICTOR
|INT:2
|vpiParameter:
\_parameter: (USE_BUS), line:88
|vpiName:USE_BUS
|INT:4
|vpiParameter:
\_parameter: (USE_DCACHE), line:92
|vpiName:USE_DCACHE
|INT:6
|vpiParameter:
\_parameter: (USE_DIV), line:49
|vpiName:USE_DIV
|INT:1
|vpiParameter:
\_parameter: (USE_DTAG_INVALIDATIONS), line:140
|vpiName:USE_DTAG_INVALIDATIONS
|INT:1879048191
|vpiParameter:
\_parameter: (USE_D_SCRATCH_MEM), line:79
|vpiName:USE_D_SCRATCH_MEM
|INT:3
|vpiParameter:
\_parameter: (USE_ICACHE), line:93
|vpiName:USE_ICACHE
|INT:7
|vpiParameter:
\_parameter: (USE_I_SCRATCH_MEM), line:78
|vpiName:USE_I_SCRATCH_MEM
|INT:2
|vpiParameter:
\_parameter: (USE_MUL), line:48
|vpiName:USE_MUL
|INT:1
|vpiParameter:
\_parameter: (WB_UNITS_WIDTH), line:187
|vpiName:WB_UNITS_WIDTH
|INT:32
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiParameter:
\_parameter: (ALU_UNIT_WB_ID), line:190
|vpiName:ALU_UNIT_WB_ID
|INT:32
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (BRANCH_PREDICTOR_WAYS), line:159
|vpiName:BRANCH_PREDICTOR_WAYS
|INT:9
|vpiParameter:
\_parameter: (BRANCH_TABLE_ENTRIES), line:160
|vpiName:BRANCH_TABLE_ENTRIES
|INT:4
|vpiParameter:
\_parameter: (BRANCH_UNIT_ID), line:195
|vpiName:BRANCH_UNIT_ID
|INT:8
|vpiParameter:
\_parameter: (BUS_ADDR_H), line:107
|vpiName:BUS_ADDR_H
|INT:1
|vpiParameter:
\_parameter: (BUS_ADDR_L), line:106
|vpiName:BUS_ADDR_L
|INT:0
|vpiParameter:
\_parameter: (BUS_BIT_CHECK), line:108
|vpiName:BUS_BIT_CHECK
|INT:1
|vpiParameter:
\_parameter: (BUS_TYPE), line:89
|vpiName:BUS_TYPE
|INT:5
|vpiParameter:
\_parameter: (COUNTER_W), line:42
|vpiName:COUNTER_W
|INT:33
|vpiParameter:
\_parameter: (CPU_ID), line:38
|vpiName:CPU_ID
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_ADDR_WIDTH), line:113
|vpiName:C_M_AXI_ADDR_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_DATA_WIDTH), line:114
|vpiName:C_M_AXI_DATA_WIDTH
|INT:1
|vpiParameter:
\_parameter: (DCACHE_LINES), line:133
|vpiName:DCACHE_LINES
|INT:-2146435073
|vpiParameter:
\_parameter: (DCACHE_LINE_ADDR_W), line:135
|vpiName:DCACHE_LINE_ADDR_W
|INT:1073741824
|vpiParameter:
\_parameter: (DCACHE_LINE_W), line:136
|vpiName:DCACHE_LINE_W
|INT:1342177279
|vpiParameter:
\_parameter: (DCACHE_SUB_LINE_ADDR_W), line:137
|vpiName:DCACHE_SUB_LINE_ADDR_W
|INT:4
|vpiParameter:
\_parameter: (DCACHE_TAG_W), line:138
|vpiName:DCACHE_TAG_W
|INT:1610612736
|vpiParameter:
\_parameter: (DCACHE_WAYS), line:134
|vpiName:DCACHE_WAYS
|INT:4
|vpiParameter:
\_parameter: (DIV_ALGORITHM), line:67
|vpiName:DIV_ALGORITHM
|INT:0
|vpiParameter:
\_parameter: (DIV_UNIT_WB_ID), line:192
|vpiName:DIV_UNIT_WB_ID
|INT:2
|vpiParameter:
\_parameter: (DTLB_DEPTH), line:152
|vpiName:DTLB_DEPTH
|INT:512
|vpiParameter:
\_parameter: (DTLB_WAYS), line:151
|vpiName:DTLB_WAYS
|INT:32
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (ENABLE_M_MODE), line:34
|vpiName:ENABLE_M_MODE
|INT:1
|vpiParameter:
\_parameter: (ENABLE_S_MODE), line:36
|vpiName:ENABLE_S_MODE
|INT:0
|vpiParameter:
\_parameter: (ENABLE_TRACE_INTERFACE), line:172
|vpiName:ENABLE_TRACE_INTERFACE
|INT:2
|vpiParameter:
\_parameter: (FETCH_BUFFER_DEPTH), line:168
|vpiName:FETCH_BUFFER_DEPTH
|INT:512
|vpiParameter:
\_parameter: (FPGA_VENDOR), line:27
|vpiName:FPGA_VENDOR
|STRING:"xilinx"
|vpiParameter:
\_parameter: (GC_UNIT_ID), line:196
|vpiName:GC_UNIT_ID
|INT:4
|vpiParameter:
\_parameter: (ICACHE_LINES), line:121
|vpiName:ICACHE_LINES
|INT:2
|vpiParameter:
\_parameter: (ICACHE_LINE_ADDR_W), line:123
|vpiName:ICACHE_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_LINE_W), line:124
|vpiName:ICACHE_LINE_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_SUB_LINE_ADDR_W), line:125
|vpiName:ICACHE_SUB_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_TAG_W), line:126
|vpiName:ICACHE_TAG_W
|INT:-2147483648
|vpiParameter:
\_parameter: (ICACHE_WAYS), line:122
|vpiName:ICACHE_WAYS
|INT:1
|vpiParameter:
\_parameter: (ITLB_DEPTH), line:146
|vpiName:ITLB_DEPTH
|INT:32
|vpiParameter:
\_parameter: (ITLB_WAYS), line:145
|vpiName:ITLB_WAYS
|INT:4
|vpiParameter:
\_parameter: (L1_CONNECTIONS), line:177
|vpiName:L1_CONNECTIONS
|INT:9
|vpiParameter:
\_parameter: (L1_DCACHE_ID), line:178
|vpiName:L1_DCACHE_ID
|INT:4
|vpiParameter:
\_parameter: (L1_DMMU_ID), line:179
|vpiName:L1_DMMU_ID
|INT:2
|vpiParameter:
\_parameter: (L1_ICACHE_ID), line:180
|vpiName:L1_ICACHE_ID
|INT:19
|vpiParameter:
\_parameter: (L1_IMMU_ID), line:181
|vpiName:L1_IMMU_ID
|INT:0
|vpiParameter:
\_parameter: (LS_UNIT_WB_ID), line:191
|vpiName:LS_UNIT_WB_ID
|INT:1
|vpiParameter:
\_parameter: (MAX_INFLIGHT_COUNT), line:167
|vpiName:MAX_INFLIGHT_COUNT
|INT:19
|vpiParameter:
\_parameter: (MEMORY_ADDR_H), line:103
|vpiName:MEMORY_ADDR_H
|INT:12
|vpiParameter:
\_parameter: (MEMORY_ADDR_L), line:102
|vpiName:MEMORY_ADDR_L
|INT:11
|vpiParameter:
\_parameter: (MEMORY_BIT_CHECK), line:104
|vpiName:MEMORY_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (MUL_UNIT_WB_ID), line:193
|vpiName:MUL_UNIT_WB_ID
|INT:512
|vpiParameter:
\_parameter: (NUM_UNITS), line:188
|vpiName:NUM_UNITS
|INT:2
|vpiParameter:
\_parameter: (NUM_WB_UNITS), line:186
|vpiName:NUM_WB_UNITS
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (RAS_DEPTH), line:161
|vpiName:RAS_DEPTH
|INT:2
|vpiParameter:
\_parameter: (RESET_VEC), line:39
|vpiName:RESET_VEC
|INT:-2147483648
|vpiParameter:
\_parameter: (SCRATCH_ADDR_H), line:99
|vpiName:SCRATCH_ADDR_H
|INT:9
|vpiParameter:
\_parameter: (SCRATCH_ADDR_L), line:98
|vpiName:SCRATCH_ADDR_L
|INT:8
|vpiParameter:
\_parameter: (SCRATCH_BIT_CHECK), line:100
|vpiName:SCRATCH_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (USE_AMO), line:70
|vpiName:USE_AMO
|INT:1
|vpiParameter:
\_parameter: (USE_BRANCH_PREDICTOR), line:158
|vpiName:USE_BRANCH_PREDICTOR
|INT:2
|vpiParameter:
\_parameter: (USE_BUS), line:88
|vpiName:USE_BUS
|INT:4
|vpiParameter:
\_parameter: (USE_DCACHE), line:92
|vpiName:USE_DCACHE
|INT:6
|vpiParameter:
\_parameter: (USE_DIV), line:49
|vpiName:USE_DIV
|INT:1
|vpiParameter:
\_parameter: (USE_DTAG_INVALIDATIONS), line:140
|vpiName:USE_DTAG_INVALIDATIONS
|INT:1879048191
|vpiParameter:
\_parameter: (USE_D_SCRATCH_MEM), line:79
|vpiName:USE_D_SCRATCH_MEM
|INT:3
|vpiParameter:
\_parameter: (USE_ICACHE), line:93
|vpiName:USE_ICACHE
|INT:7
|vpiParameter:
\_parameter: (USE_I_SCRATCH_MEM), line:78
|vpiName:USE_I_SCRATCH_MEM
|INT:2
|vpiParameter:
\_parameter: (USE_MUL), line:48
|vpiName:USE_MUL
|INT:1
|vpiParameter:
\_parameter: (WB_UNITS_WIDTH), line:187
|vpiName:WB_UNITS_WIDTH
|INT:32
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiParameter:
\_parameter: (i), line:70
|vpiName:i
|INT:2
|vpiGenScopeArray:
\_gen_scope_array: (branch_table_banks[3]), line:70
|vpiName:branch_table_banks[3]
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_table_banks.branch_table_banks[3]
|vpiGenScope:
\_gen_scope: , parent:branch_table_banks[3]
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_table_banks.branch_table_banks[3]
|vpiModule:
\_module: work@branch_predictor_ram (addr_table), file:third_party/cores/taiga/core/branch_predictor.sv, line:71
|vpiDefName:work@branch_predictor_ram
|vpiName:addr_table
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_table_banks.branch_table_banks[3].addr_table
|vpiPort:
\_port: (clk), line:32, parent:addr_table
|vpiName:clk
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (clk), line:72
|vpiName:clk
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (clk), line:32, parent:addr_table
|vpiName:clk
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_table_banks.branch_table_banks[3].addr_table.clk
|vpiNetType:36
|vpiPort:
\_port: (write_addr), line:33, parent:addr_table
|vpiName:write_addr
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (write_addr), line:72
|vpiName:write_addr
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (write_addr), line:33, parent:addr_table
|vpiName:write_addr
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_table_banks.branch_table_banks[3].addr_table.write_addr
|vpiNetType:36
|vpiRange:
\_range: , line:33
|vpiLeftRange:
\_constant: , line:33
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:33
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiPort:
\_port: (write_en), line:34, parent:addr_table
|vpiName:write_en
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (write_en), line:72
|vpiName:write_en
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (write_en), line:34, parent:addr_table
|vpiName:write_en
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_table_banks.branch_table_banks[3].addr_table.write_en
|vpiNetType:36
|vpiPort:
\_port: (read_addr), line:35, parent:addr_table
|vpiName:read_addr
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (read_addr), line:72
|vpiName:read_addr
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (read_addr), line:35, parent:addr_table
|vpiName:read_addr
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_table_banks.branch_table_banks[3].addr_table.read_addr
|vpiNetType:36
|vpiRange:
\_range: , line:35
|vpiLeftRange:
\_constant: , line:35
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:35
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiPort:
\_port: (read_en), line:36, parent:addr_table
|vpiName:read_en
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (read_en), line:72
|vpiName:read_en
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (read_en), line:36, parent:addr_table
|vpiName:read_en
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_table_banks.branch_table_banks[3].addr_table.read_en
|vpiNetType:36
|vpiPort:
\_port: (write_data), line:37, parent:addr_table
|vpiName:write_data
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (write_data), line:72
|vpiName:write_data
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (write_data), line:37, parent:addr_table
|vpiName:write_data
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_table_banks.branch_table_banks[3].addr_table.write_data
|vpiNetType:36
|vpiRange:
\_range: , line:37
|vpiLeftRange:
\_constant: , line:37
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:37
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiPort:
\_port: (read_data), line:38, parent:addr_table
|vpiName:read_data
|vpiDirection:2
|vpiHighConn:
\_ref_obj: (read_data), line:72
|vpiName:read_data
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (read_data), line:38, parent:addr_table
|vpiName:read_data
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_table_banks.branch_table_banks[3].addr_table.read_data
|vpiNetType:36
|vpiRange:
\_range: , line:38
|vpiLeftRange:
\_constant: , line:38
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:38
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (clk), line:32, parent:addr_table
|vpiNet:
\_logic_net: (write_addr), line:33, parent:addr_table
|vpiNet:
\_logic_net: (write_en), line:34, parent:addr_table
|vpiNet:
\_logic_net: (read_addr), line:35, parent:addr_table
|vpiNet:
\_logic_net: (read_en), line:36, parent:addr_table
|vpiNet:
\_logic_net: (write_data), line:37, parent:addr_table
|vpiNet:
\_logic_net: (read_data), line:38, parent:addr_table
|vpiArrayNet:
\_array_net: (branch_ram), line:40, parent:addr_table
|vpiName:branch_ram
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_table_banks.branch_table_banks[3].addr_table.branch_ram
|vpiSize:4
|vpiNet:
\_logic_net: , parent:branch_ram
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_table_banks.branch_table_banks[3].addr_table.branch_ram
|vpiNetType:36
|vpiRange:
\_range: , line:40
|vpiLeftRange:
\_constant: , line:40
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:40
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiRange:
\_range: , line:40
|vpiLeftRange:
\_constant: , line:40
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiRightRange:
\_constant: , line:40
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiParameter:
\_parameter: (ALU_UNIT_WB_ID), line:190
|vpiName:ALU_UNIT_WB_ID
|INT:32
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (BRANCH_PREDICTOR_WAYS), line:159
|vpiName:BRANCH_PREDICTOR_WAYS
|INT:9
|vpiParameter:
\_parameter: (BRANCH_TABLE_ENTRIES), line:160
|vpiName:BRANCH_TABLE_ENTRIES
|INT:4
|vpiParameter:
\_parameter: (BRANCH_UNIT_ID), line:195
|vpiName:BRANCH_UNIT_ID
|INT:8
|vpiParameter:
\_parameter: (BUS_ADDR_H), line:107
|vpiName:BUS_ADDR_H
|INT:1
|vpiParameter:
\_parameter: (BUS_ADDR_L), line:106
|vpiName:BUS_ADDR_L
|INT:0
|vpiParameter:
\_parameter: (BUS_BIT_CHECK), line:108
|vpiName:BUS_BIT_CHECK
|INT:1
|vpiParameter:
\_parameter: (BUS_TYPE), line:89
|vpiName:BUS_TYPE
|INT:5
|vpiParameter:
\_parameter: (COUNTER_W), line:42
|vpiName:COUNTER_W
|INT:33
|vpiParameter:
\_parameter: (CPU_ID), line:38
|vpiName:CPU_ID
|INT:0
|vpiParameter:
\_parameter: (C_DATA_WIDTH), line:71
|vpiName:C_DATA_WIDTH
|INT:32
|vpiParameter:
\_parameter: (C_DEPTH), line:71
|vpiName:C_DEPTH
|INT:4
|vpiParameter:
\_parameter: (C_M_AXI_ADDR_WIDTH), line:113
|vpiName:C_M_AXI_ADDR_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_DATA_WIDTH), line:114
|vpiName:C_M_AXI_DATA_WIDTH
|INT:1
|vpiParameter:
\_parameter: (DCACHE_LINES), line:133
|vpiName:DCACHE_LINES
|INT:-2146435073
|vpiParameter:
\_parameter: (DCACHE_LINE_ADDR_W), line:135
|vpiName:DCACHE_LINE_ADDR_W
|INT:1073741824
|vpiParameter:
\_parameter: (DCACHE_LINE_W), line:136
|vpiName:DCACHE_LINE_W
|INT:1342177279
|vpiParameter:
\_parameter: (DCACHE_SUB_LINE_ADDR_W), line:137
|vpiName:DCACHE_SUB_LINE_ADDR_W
|INT:4
|vpiParameter:
\_parameter: (DCACHE_TAG_W), line:138
|vpiName:DCACHE_TAG_W
|INT:1610612736
|vpiParameter:
\_parameter: (DCACHE_WAYS), line:134
|vpiName:DCACHE_WAYS
|INT:4
|vpiParameter:
\_parameter: (DIV_ALGORITHM), line:67
|vpiName:DIV_ALGORITHM
|INT:0
|vpiParameter:
\_parameter: (DIV_UNIT_WB_ID), line:192
|vpiName:DIV_UNIT_WB_ID
|INT:2
|vpiParameter:
\_parameter: (DTLB_DEPTH), line:152
|vpiName:DTLB_DEPTH
|INT:512
|vpiParameter:
\_parameter: (DTLB_WAYS), line:151
|vpiName:DTLB_WAYS
|INT:32
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (ENABLE_M_MODE), line:34
|vpiName:ENABLE_M_MODE
|INT:1
|vpiParameter:
\_parameter: (ENABLE_S_MODE), line:36
|vpiName:ENABLE_S_MODE
|INT:0
|vpiParameter:
\_parameter: (ENABLE_TRACE_INTERFACE), line:172
|vpiName:ENABLE_TRACE_INTERFACE
|INT:2
|vpiParameter:
\_parameter: (FETCH_BUFFER_DEPTH), line:168
|vpiName:FETCH_BUFFER_DEPTH
|INT:512
|vpiParameter:
\_parameter: (FPGA_VENDOR), line:27
|vpiName:FPGA_VENDOR
|STRING:"xilinx"
|vpiParameter:
\_parameter: (GC_UNIT_ID), line:196
|vpiName:GC_UNIT_ID
|INT:4
|vpiParameter:
\_parameter: (ICACHE_LINES), line:121
|vpiName:ICACHE_LINES
|INT:2
|vpiParameter:
\_parameter: (ICACHE_LINE_ADDR_W), line:123
|vpiName:ICACHE_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_LINE_W), line:124
|vpiName:ICACHE_LINE_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_SUB_LINE_ADDR_W), line:125
|vpiName:ICACHE_SUB_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_TAG_W), line:126
|vpiName:ICACHE_TAG_W
|INT:-2147483648
|vpiParameter:
\_parameter: (ICACHE_WAYS), line:122
|vpiName:ICACHE_WAYS
|INT:1
|vpiParameter:
\_parameter: (ITLB_DEPTH), line:146
|vpiName:ITLB_DEPTH
|INT:32
|vpiParameter:
\_parameter: (ITLB_WAYS), line:145
|vpiName:ITLB_WAYS
|INT:4
|vpiParameter:
\_parameter: (L1_CONNECTIONS), line:177
|vpiName:L1_CONNECTIONS
|INT:9
|vpiParameter:
\_parameter: (L1_DCACHE_ID), line:178
|vpiName:L1_DCACHE_ID
|INT:4
|vpiParameter:
\_parameter: (L1_DMMU_ID), line:179
|vpiName:L1_DMMU_ID
|INT:2
|vpiParameter:
\_parameter: (L1_ICACHE_ID), line:180
|vpiName:L1_ICACHE_ID
|INT:19
|vpiParameter:
\_parameter: (L1_IMMU_ID), line:181
|vpiName:L1_IMMU_ID
|INT:0
|vpiParameter:
\_parameter: (LS_UNIT_WB_ID), line:191
|vpiName:LS_UNIT_WB_ID
|INT:1
|vpiParameter:
\_parameter: (MAX_INFLIGHT_COUNT), line:167
|vpiName:MAX_INFLIGHT_COUNT
|INT:19
|vpiParameter:
\_parameter: (MEMORY_ADDR_H), line:103
|vpiName:MEMORY_ADDR_H
|INT:12
|vpiParameter:
\_parameter: (MEMORY_ADDR_L), line:102
|vpiName:MEMORY_ADDR_L
|INT:11
|vpiParameter:
\_parameter: (MEMORY_BIT_CHECK), line:104
|vpiName:MEMORY_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (MUL_UNIT_WB_ID), line:193
|vpiName:MUL_UNIT_WB_ID
|INT:512
|vpiParameter:
\_parameter: (NUM_UNITS), line:188
|vpiName:NUM_UNITS
|INT:2
|vpiParameter:
\_parameter: (NUM_WB_UNITS), line:186
|vpiName:NUM_WB_UNITS
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (RAS_DEPTH), line:161
|vpiName:RAS_DEPTH
|INT:2
|vpiParameter:
\_parameter: (RESET_VEC), line:39
|vpiName:RESET_VEC
|INT:-2147483648
|vpiParameter:
\_parameter: (SCRATCH_ADDR_H), line:99
|vpiName:SCRATCH_ADDR_H
|INT:9
|vpiParameter:
\_parameter: (SCRATCH_ADDR_L), line:98
|vpiName:SCRATCH_ADDR_L
|INT:8
|vpiParameter:
\_parameter: (SCRATCH_BIT_CHECK), line:100
|vpiName:SCRATCH_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (USE_AMO), line:70
|vpiName:USE_AMO
|INT:1
|vpiParameter:
\_parameter: (USE_BRANCH_PREDICTOR), line:158
|vpiName:USE_BRANCH_PREDICTOR
|INT:2
|vpiParameter:
\_parameter: (USE_BUS), line:88
|vpiName:USE_BUS
|INT:4
|vpiParameter:
\_parameter: (USE_DCACHE), line:92
|vpiName:USE_DCACHE
|INT:6
|vpiParameter:
\_parameter: (USE_DIV), line:49
|vpiName:USE_DIV
|INT:1
|vpiParameter:
\_parameter: (USE_DTAG_INVALIDATIONS), line:140
|vpiName:USE_DTAG_INVALIDATIONS
|INT:1879048191
|vpiParameter:
\_parameter: (USE_D_SCRATCH_MEM), line:79
|vpiName:USE_D_SCRATCH_MEM
|INT:3
|vpiParameter:
\_parameter: (USE_ICACHE), line:93
|vpiName:USE_ICACHE
|INT:7
|vpiParameter:
\_parameter: (USE_I_SCRATCH_MEM), line:78
|vpiName:USE_I_SCRATCH_MEM
|INT:2
|vpiParameter:
\_parameter: (USE_MUL), line:48
|vpiName:USE_MUL
|INT:1
|vpiParameter:
\_parameter: (WB_UNITS_WIDTH), line:187
|vpiName:WB_UNITS_WIDTH
|INT:32
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiParameter:
\_parameter: (ALU_UNIT_WB_ID), line:190
|vpiName:ALU_UNIT_WB_ID
|INT:32
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (BRANCH_PREDICTOR_WAYS), line:159
|vpiName:BRANCH_PREDICTOR_WAYS
|INT:9
|vpiParameter:
\_parameter: (BRANCH_TABLE_ENTRIES), line:160
|vpiName:BRANCH_TABLE_ENTRIES
|INT:4
|vpiParameter:
\_parameter: (BRANCH_UNIT_ID), line:195
|vpiName:BRANCH_UNIT_ID
|INT:8
|vpiParameter:
\_parameter: (BUS_ADDR_H), line:107
|vpiName:BUS_ADDR_H
|INT:1
|vpiParameter:
\_parameter: (BUS_ADDR_L), line:106
|vpiName:BUS_ADDR_L
|INT:0
|vpiParameter:
\_parameter: (BUS_BIT_CHECK), line:108
|vpiName:BUS_BIT_CHECK
|INT:1
|vpiParameter:
\_parameter: (BUS_TYPE), line:89
|vpiName:BUS_TYPE
|INT:5
|vpiParameter:
\_parameter: (COUNTER_W), line:42
|vpiName:COUNTER_W
|INT:33
|vpiParameter:
\_parameter: (CPU_ID), line:38
|vpiName:CPU_ID
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_ADDR_WIDTH), line:113
|vpiName:C_M_AXI_ADDR_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_DATA_WIDTH), line:114
|vpiName:C_M_AXI_DATA_WIDTH
|INT:1
|vpiParameter:
\_parameter: (DCACHE_LINES), line:133
|vpiName:DCACHE_LINES
|INT:-2146435073
|vpiParameter:
\_parameter: (DCACHE_LINE_ADDR_W), line:135
|vpiName:DCACHE_LINE_ADDR_W
|INT:1073741824
|vpiParameter:
\_parameter: (DCACHE_LINE_W), line:136
|vpiName:DCACHE_LINE_W
|INT:1342177279
|vpiParameter:
\_parameter: (DCACHE_SUB_LINE_ADDR_W), line:137
|vpiName:DCACHE_SUB_LINE_ADDR_W
|INT:4
|vpiParameter:
\_parameter: (DCACHE_TAG_W), line:138
|vpiName:DCACHE_TAG_W
|INT:1610612736
|vpiParameter:
\_parameter: (DCACHE_WAYS), line:134
|vpiName:DCACHE_WAYS
|INT:4
|vpiParameter:
\_parameter: (DIV_ALGORITHM), line:67
|vpiName:DIV_ALGORITHM
|INT:0
|vpiParameter:
\_parameter: (DIV_UNIT_WB_ID), line:192
|vpiName:DIV_UNIT_WB_ID
|INT:2
|vpiParameter:
\_parameter: (DTLB_DEPTH), line:152
|vpiName:DTLB_DEPTH
|INT:512
|vpiParameter:
\_parameter: (DTLB_WAYS), line:151
|vpiName:DTLB_WAYS
|INT:32
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (ENABLE_M_MODE), line:34
|vpiName:ENABLE_M_MODE
|INT:1
|vpiParameter:
\_parameter: (ENABLE_S_MODE), line:36
|vpiName:ENABLE_S_MODE
|INT:0
|vpiParameter:
\_parameter: (ENABLE_TRACE_INTERFACE), line:172
|vpiName:ENABLE_TRACE_INTERFACE
|INT:2
|vpiParameter:
\_parameter: (FETCH_BUFFER_DEPTH), line:168
|vpiName:FETCH_BUFFER_DEPTH
|INT:512
|vpiParameter:
\_parameter: (FPGA_VENDOR), line:27
|vpiName:FPGA_VENDOR
|STRING:"xilinx"
|vpiParameter:
\_parameter: (GC_UNIT_ID), line:196
|vpiName:GC_UNIT_ID
|INT:4
|vpiParameter:
\_parameter: (ICACHE_LINES), line:121
|vpiName:ICACHE_LINES
|INT:2
|vpiParameter:
\_parameter: (ICACHE_LINE_ADDR_W), line:123
|vpiName:ICACHE_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_LINE_W), line:124
|vpiName:ICACHE_LINE_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_SUB_LINE_ADDR_W), line:125
|vpiName:ICACHE_SUB_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_TAG_W), line:126
|vpiName:ICACHE_TAG_W
|INT:-2147483648
|vpiParameter:
\_parameter: (ICACHE_WAYS), line:122
|vpiName:ICACHE_WAYS
|INT:1
|vpiParameter:
\_parameter: (ITLB_DEPTH), line:146
|vpiName:ITLB_DEPTH
|INT:32
|vpiParameter:
\_parameter: (ITLB_WAYS), line:145
|vpiName:ITLB_WAYS
|INT:4
|vpiParameter:
\_parameter: (L1_CONNECTIONS), line:177
|vpiName:L1_CONNECTIONS
|INT:9
|vpiParameter:
\_parameter: (L1_DCACHE_ID), line:178
|vpiName:L1_DCACHE_ID
|INT:4
|vpiParameter:
\_parameter: (L1_DMMU_ID), line:179
|vpiName:L1_DMMU_ID
|INT:2
|vpiParameter:
\_parameter: (L1_ICACHE_ID), line:180
|vpiName:L1_ICACHE_ID
|INT:19
|vpiParameter:
\_parameter: (L1_IMMU_ID), line:181
|vpiName:L1_IMMU_ID
|INT:0
|vpiParameter:
\_parameter: (LS_UNIT_WB_ID), line:191
|vpiName:LS_UNIT_WB_ID
|INT:1
|vpiParameter:
\_parameter: (MAX_INFLIGHT_COUNT), line:167
|vpiName:MAX_INFLIGHT_COUNT
|INT:19
|vpiParameter:
\_parameter: (MEMORY_ADDR_H), line:103
|vpiName:MEMORY_ADDR_H
|INT:12
|vpiParameter:
\_parameter: (MEMORY_ADDR_L), line:102
|vpiName:MEMORY_ADDR_L
|INT:11
|vpiParameter:
\_parameter: (MEMORY_BIT_CHECK), line:104
|vpiName:MEMORY_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (MUL_UNIT_WB_ID), line:193
|vpiName:MUL_UNIT_WB_ID
|INT:512
|vpiParameter:
\_parameter: (NUM_UNITS), line:188
|vpiName:NUM_UNITS
|INT:2
|vpiParameter:
\_parameter: (NUM_WB_UNITS), line:186
|vpiName:NUM_WB_UNITS
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (RAS_DEPTH), line:161
|vpiName:RAS_DEPTH
|INT:2
|vpiParameter:
\_parameter: (RESET_VEC), line:39
|vpiName:RESET_VEC
|INT:-2147483648
|vpiParameter:
\_parameter: (SCRATCH_ADDR_H), line:99
|vpiName:SCRATCH_ADDR_H
|INT:9
|vpiParameter:
\_parameter: (SCRATCH_ADDR_L), line:98
|vpiName:SCRATCH_ADDR_L
|INT:8
|vpiParameter:
\_parameter: (SCRATCH_BIT_CHECK), line:100
|vpiName:SCRATCH_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (USE_AMO), line:70
|vpiName:USE_AMO
|INT:1
|vpiParameter:
\_parameter: (USE_BRANCH_PREDICTOR), line:158
|vpiName:USE_BRANCH_PREDICTOR
|INT:2
|vpiParameter:
\_parameter: (USE_BUS), line:88
|vpiName:USE_BUS
|INT:4
|vpiParameter:
\_parameter: (USE_DCACHE), line:92
|vpiName:USE_DCACHE
|INT:6
|vpiParameter:
\_parameter: (USE_DIV), line:49
|vpiName:USE_DIV
|INT:1
|vpiParameter:
\_parameter: (USE_DTAG_INVALIDATIONS), line:140
|vpiName:USE_DTAG_INVALIDATIONS
|INT:1879048191
|vpiParameter:
\_parameter: (USE_D_SCRATCH_MEM), line:79
|vpiName:USE_D_SCRATCH_MEM
|INT:3
|vpiParameter:
\_parameter: (USE_ICACHE), line:93
|vpiName:USE_ICACHE
|INT:7
|vpiParameter:
\_parameter: (USE_I_SCRATCH_MEM), line:78
|vpiName:USE_I_SCRATCH_MEM
|INT:2
|vpiParameter:
\_parameter: (USE_MUL), line:48
|vpiName:USE_MUL
|INT:1
|vpiParameter:
\_parameter: (WB_UNITS_WIDTH), line:187
|vpiName:WB_UNITS_WIDTH
|INT:32
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiParameter:
\_parameter: (i), line:70
|vpiName:i
|INT:3
|vpiGenScopeArray:
\_gen_scope_array: (branch_table_banks[4]), line:70
|vpiName:branch_table_banks[4]
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_table_banks.branch_table_banks[4]
|vpiGenScope:
\_gen_scope: , parent:branch_table_banks[4]
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_table_banks.branch_table_banks[4]
|vpiModule:
\_module: work@branch_predictor_ram (addr_table), file:third_party/cores/taiga/core/branch_predictor.sv, line:71
|vpiDefName:work@branch_predictor_ram
|vpiName:addr_table
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_table_banks.branch_table_banks[4].addr_table
|vpiPort:
\_port: (clk), line:32, parent:addr_table
|vpiName:clk
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (clk), line:72
|vpiName:clk
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (clk), line:32, parent:addr_table
|vpiName:clk
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_table_banks.branch_table_banks[4].addr_table.clk
|vpiNetType:36
|vpiPort:
\_port: (write_addr), line:33, parent:addr_table
|vpiName:write_addr
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (write_addr), line:72
|vpiName:write_addr
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (write_addr), line:33, parent:addr_table
|vpiName:write_addr
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_table_banks.branch_table_banks[4].addr_table.write_addr
|vpiNetType:36
|vpiRange:
\_range: , line:33
|vpiLeftRange:
\_constant: , line:33
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:33
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiPort:
\_port: (write_en), line:34, parent:addr_table
|vpiName:write_en
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (write_en), line:72
|vpiName:write_en
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (write_en), line:34, parent:addr_table
|vpiName:write_en
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_table_banks.branch_table_banks[4].addr_table.write_en
|vpiNetType:36
|vpiPort:
\_port: (read_addr), line:35, parent:addr_table
|vpiName:read_addr
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (read_addr), line:72
|vpiName:read_addr
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (read_addr), line:35, parent:addr_table
|vpiName:read_addr
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_table_banks.branch_table_banks[4].addr_table.read_addr
|vpiNetType:36
|vpiRange:
\_range: , line:35
|vpiLeftRange:
\_constant: , line:35
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:35
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiPort:
\_port: (read_en), line:36, parent:addr_table
|vpiName:read_en
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (read_en), line:72
|vpiName:read_en
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (read_en), line:36, parent:addr_table
|vpiName:read_en
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_table_banks.branch_table_banks[4].addr_table.read_en
|vpiNetType:36
|vpiPort:
\_port: (write_data), line:37, parent:addr_table
|vpiName:write_data
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (write_data), line:72
|vpiName:write_data
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (write_data), line:37, parent:addr_table
|vpiName:write_data
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_table_banks.branch_table_banks[4].addr_table.write_data
|vpiNetType:36
|vpiRange:
\_range: , line:37
|vpiLeftRange:
\_constant: , line:37
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:37
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiPort:
\_port: (read_data), line:38, parent:addr_table
|vpiName:read_data
|vpiDirection:2
|vpiHighConn:
\_ref_obj: (read_data), line:72
|vpiName:read_data
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (read_data), line:38, parent:addr_table
|vpiName:read_data
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_table_banks.branch_table_banks[4].addr_table.read_data
|vpiNetType:36
|vpiRange:
\_range: , line:38
|vpiLeftRange:
\_constant: , line:38
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:38
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (clk), line:32, parent:addr_table
|vpiNet:
\_logic_net: (write_addr), line:33, parent:addr_table
|vpiNet:
\_logic_net: (write_en), line:34, parent:addr_table
|vpiNet:
\_logic_net: (read_addr), line:35, parent:addr_table
|vpiNet:
\_logic_net: (read_en), line:36, parent:addr_table
|vpiNet:
\_logic_net: (write_data), line:37, parent:addr_table
|vpiNet:
\_logic_net: (read_data), line:38, parent:addr_table
|vpiArrayNet:
\_array_net: (branch_ram), line:40, parent:addr_table
|vpiName:branch_ram
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_table_banks.branch_table_banks[4].addr_table.branch_ram
|vpiSize:4
|vpiNet:
\_logic_net: , parent:branch_ram
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_table_banks.branch_table_banks[4].addr_table.branch_ram
|vpiNetType:36
|vpiRange:
\_range: , line:40
|vpiLeftRange:
\_constant: , line:40
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:40
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiRange:
\_range: , line:40
|vpiLeftRange:
\_constant: , line:40
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiRightRange:
\_constant: , line:40
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiParameter:
\_parameter: (ALU_UNIT_WB_ID), line:190
|vpiName:ALU_UNIT_WB_ID
|INT:32
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (BRANCH_PREDICTOR_WAYS), line:159
|vpiName:BRANCH_PREDICTOR_WAYS
|INT:9
|vpiParameter:
\_parameter: (BRANCH_TABLE_ENTRIES), line:160
|vpiName:BRANCH_TABLE_ENTRIES
|INT:4
|vpiParameter:
\_parameter: (BRANCH_UNIT_ID), line:195
|vpiName:BRANCH_UNIT_ID
|INT:8
|vpiParameter:
\_parameter: (BUS_ADDR_H), line:107
|vpiName:BUS_ADDR_H
|INT:1
|vpiParameter:
\_parameter: (BUS_ADDR_L), line:106
|vpiName:BUS_ADDR_L
|INT:0
|vpiParameter:
\_parameter: (BUS_BIT_CHECK), line:108
|vpiName:BUS_BIT_CHECK
|INT:1
|vpiParameter:
\_parameter: (BUS_TYPE), line:89
|vpiName:BUS_TYPE
|INT:5
|vpiParameter:
\_parameter: (COUNTER_W), line:42
|vpiName:COUNTER_W
|INT:33
|vpiParameter:
\_parameter: (CPU_ID), line:38
|vpiName:CPU_ID
|INT:0
|vpiParameter:
\_parameter: (C_DATA_WIDTH), line:71
|vpiName:C_DATA_WIDTH
|INT:32
|vpiParameter:
\_parameter: (C_DEPTH), line:71
|vpiName:C_DEPTH
|INT:4
|vpiParameter:
\_parameter: (C_M_AXI_ADDR_WIDTH), line:113
|vpiName:C_M_AXI_ADDR_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_DATA_WIDTH), line:114
|vpiName:C_M_AXI_DATA_WIDTH
|INT:1
|vpiParameter:
\_parameter: (DCACHE_LINES), line:133
|vpiName:DCACHE_LINES
|INT:-2146435073
|vpiParameter:
\_parameter: (DCACHE_LINE_ADDR_W), line:135
|vpiName:DCACHE_LINE_ADDR_W
|INT:1073741824
|vpiParameter:
\_parameter: (DCACHE_LINE_W), line:136
|vpiName:DCACHE_LINE_W
|INT:1342177279
|vpiParameter:
\_parameter: (DCACHE_SUB_LINE_ADDR_W), line:137
|vpiName:DCACHE_SUB_LINE_ADDR_W
|INT:4
|vpiParameter:
\_parameter: (DCACHE_TAG_W), line:138
|vpiName:DCACHE_TAG_W
|INT:1610612736
|vpiParameter:
\_parameter: (DCACHE_WAYS), line:134
|vpiName:DCACHE_WAYS
|INT:4
|vpiParameter:
\_parameter: (DIV_ALGORITHM), line:67
|vpiName:DIV_ALGORITHM
|INT:0
|vpiParameter:
\_parameter: (DIV_UNIT_WB_ID), line:192
|vpiName:DIV_UNIT_WB_ID
|INT:2
|vpiParameter:
\_parameter: (DTLB_DEPTH), line:152
|vpiName:DTLB_DEPTH
|INT:512
|vpiParameter:
\_parameter: (DTLB_WAYS), line:151
|vpiName:DTLB_WAYS
|INT:32
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (ENABLE_M_MODE), line:34
|vpiName:ENABLE_M_MODE
|INT:1
|vpiParameter:
\_parameter: (ENABLE_S_MODE), line:36
|vpiName:ENABLE_S_MODE
|INT:0
|vpiParameter:
\_parameter: (ENABLE_TRACE_INTERFACE), line:172
|vpiName:ENABLE_TRACE_INTERFACE
|INT:2
|vpiParameter:
\_parameter: (FETCH_BUFFER_DEPTH), line:168
|vpiName:FETCH_BUFFER_DEPTH
|INT:512
|vpiParameter:
\_parameter: (FPGA_VENDOR), line:27
|vpiName:FPGA_VENDOR
|STRING:"xilinx"
|vpiParameter:
\_parameter: (GC_UNIT_ID), line:196
|vpiName:GC_UNIT_ID
|INT:4
|vpiParameter:
\_parameter: (ICACHE_LINES), line:121
|vpiName:ICACHE_LINES
|INT:2
|vpiParameter:
\_parameter: (ICACHE_LINE_ADDR_W), line:123
|vpiName:ICACHE_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_LINE_W), line:124
|vpiName:ICACHE_LINE_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_SUB_LINE_ADDR_W), line:125
|vpiName:ICACHE_SUB_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_TAG_W), line:126
|vpiName:ICACHE_TAG_W
|INT:-2147483648
|vpiParameter:
\_parameter: (ICACHE_WAYS), line:122
|vpiName:ICACHE_WAYS
|INT:1
|vpiParameter:
\_parameter: (ITLB_DEPTH), line:146
|vpiName:ITLB_DEPTH
|INT:32
|vpiParameter:
\_parameter: (ITLB_WAYS), line:145
|vpiName:ITLB_WAYS
|INT:4
|vpiParameter:
\_parameter: (L1_CONNECTIONS), line:177
|vpiName:L1_CONNECTIONS
|INT:9
|vpiParameter:
\_parameter: (L1_DCACHE_ID), line:178
|vpiName:L1_DCACHE_ID
|INT:4
|vpiParameter:
\_parameter: (L1_DMMU_ID), line:179
|vpiName:L1_DMMU_ID
|INT:2
|vpiParameter:
\_parameter: (L1_ICACHE_ID), line:180
|vpiName:L1_ICACHE_ID
|INT:19
|vpiParameter:
\_parameter: (L1_IMMU_ID), line:181
|vpiName:L1_IMMU_ID
|INT:0
|vpiParameter:
\_parameter: (LS_UNIT_WB_ID), line:191
|vpiName:LS_UNIT_WB_ID
|INT:1
|vpiParameter:
\_parameter: (MAX_INFLIGHT_COUNT), line:167
|vpiName:MAX_INFLIGHT_COUNT
|INT:19
|vpiParameter:
\_parameter: (MEMORY_ADDR_H), line:103
|vpiName:MEMORY_ADDR_H
|INT:12
|vpiParameter:
\_parameter: (MEMORY_ADDR_L), line:102
|vpiName:MEMORY_ADDR_L
|INT:11
|vpiParameter:
\_parameter: (MEMORY_BIT_CHECK), line:104
|vpiName:MEMORY_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (MUL_UNIT_WB_ID), line:193
|vpiName:MUL_UNIT_WB_ID
|INT:512
|vpiParameter:
\_parameter: (NUM_UNITS), line:188
|vpiName:NUM_UNITS
|INT:2
|vpiParameter:
\_parameter: (NUM_WB_UNITS), line:186
|vpiName:NUM_WB_UNITS
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (RAS_DEPTH), line:161
|vpiName:RAS_DEPTH
|INT:2
|vpiParameter:
\_parameter: (RESET_VEC), line:39
|vpiName:RESET_VEC
|INT:-2147483648
|vpiParameter:
\_parameter: (SCRATCH_ADDR_H), line:99
|vpiName:SCRATCH_ADDR_H
|INT:9
|vpiParameter:
\_parameter: (SCRATCH_ADDR_L), line:98
|vpiName:SCRATCH_ADDR_L
|INT:8
|vpiParameter:
\_parameter: (SCRATCH_BIT_CHECK), line:100
|vpiName:SCRATCH_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (USE_AMO), line:70
|vpiName:USE_AMO
|INT:1
|vpiParameter:
\_parameter: (USE_BRANCH_PREDICTOR), line:158
|vpiName:USE_BRANCH_PREDICTOR
|INT:2
|vpiParameter:
\_parameter: (USE_BUS), line:88
|vpiName:USE_BUS
|INT:4
|vpiParameter:
\_parameter: (USE_DCACHE), line:92
|vpiName:USE_DCACHE
|INT:6
|vpiParameter:
\_parameter: (USE_DIV), line:49
|vpiName:USE_DIV
|INT:1
|vpiParameter:
\_parameter: (USE_DTAG_INVALIDATIONS), line:140
|vpiName:USE_DTAG_INVALIDATIONS
|INT:1879048191
|vpiParameter:
\_parameter: (USE_D_SCRATCH_MEM), line:79
|vpiName:USE_D_SCRATCH_MEM
|INT:3
|vpiParameter:
\_parameter: (USE_ICACHE), line:93
|vpiName:USE_ICACHE
|INT:7
|vpiParameter:
\_parameter: (USE_I_SCRATCH_MEM), line:78
|vpiName:USE_I_SCRATCH_MEM
|INT:2
|vpiParameter:
\_parameter: (USE_MUL), line:48
|vpiName:USE_MUL
|INT:1
|vpiParameter:
\_parameter: (WB_UNITS_WIDTH), line:187
|vpiName:WB_UNITS_WIDTH
|INT:32
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiParameter:
\_parameter: (ALU_UNIT_WB_ID), line:190
|vpiName:ALU_UNIT_WB_ID
|INT:32
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (BRANCH_PREDICTOR_WAYS), line:159
|vpiName:BRANCH_PREDICTOR_WAYS
|INT:9
|vpiParameter:
\_parameter: (BRANCH_TABLE_ENTRIES), line:160
|vpiName:BRANCH_TABLE_ENTRIES
|INT:4
|vpiParameter:
\_parameter: (BRANCH_UNIT_ID), line:195
|vpiName:BRANCH_UNIT_ID
|INT:8
|vpiParameter:
\_parameter: (BUS_ADDR_H), line:107
|vpiName:BUS_ADDR_H
|INT:1
|vpiParameter:
\_parameter: (BUS_ADDR_L), line:106
|vpiName:BUS_ADDR_L
|INT:0
|vpiParameter:
\_parameter: (BUS_BIT_CHECK), line:108
|vpiName:BUS_BIT_CHECK
|INT:1
|vpiParameter:
\_parameter: (BUS_TYPE), line:89
|vpiName:BUS_TYPE
|INT:5
|vpiParameter:
\_parameter: (COUNTER_W), line:42
|vpiName:COUNTER_W
|INT:33
|vpiParameter:
\_parameter: (CPU_ID), line:38
|vpiName:CPU_ID
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_ADDR_WIDTH), line:113
|vpiName:C_M_AXI_ADDR_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_DATA_WIDTH), line:114
|vpiName:C_M_AXI_DATA_WIDTH
|INT:1
|vpiParameter:
\_parameter: (DCACHE_LINES), line:133
|vpiName:DCACHE_LINES
|INT:-2146435073
|vpiParameter:
\_parameter: (DCACHE_LINE_ADDR_W), line:135
|vpiName:DCACHE_LINE_ADDR_W
|INT:1073741824
|vpiParameter:
\_parameter: (DCACHE_LINE_W), line:136
|vpiName:DCACHE_LINE_W
|INT:1342177279
|vpiParameter:
\_parameter: (DCACHE_SUB_LINE_ADDR_W), line:137
|vpiName:DCACHE_SUB_LINE_ADDR_W
|INT:4
|vpiParameter:
\_parameter: (DCACHE_TAG_W), line:138
|vpiName:DCACHE_TAG_W
|INT:1610612736
|vpiParameter:
\_parameter: (DCACHE_WAYS), line:134
|vpiName:DCACHE_WAYS
|INT:4
|vpiParameter:
\_parameter: (DIV_ALGORITHM), line:67
|vpiName:DIV_ALGORITHM
|INT:0
|vpiParameter:
\_parameter: (DIV_UNIT_WB_ID), line:192
|vpiName:DIV_UNIT_WB_ID
|INT:2
|vpiParameter:
\_parameter: (DTLB_DEPTH), line:152
|vpiName:DTLB_DEPTH
|INT:512
|vpiParameter:
\_parameter: (DTLB_WAYS), line:151
|vpiName:DTLB_WAYS
|INT:32
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (ENABLE_M_MODE), line:34
|vpiName:ENABLE_M_MODE
|INT:1
|vpiParameter:
\_parameter: (ENABLE_S_MODE), line:36
|vpiName:ENABLE_S_MODE
|INT:0
|vpiParameter:
\_parameter: (ENABLE_TRACE_INTERFACE), line:172
|vpiName:ENABLE_TRACE_INTERFACE
|INT:2
|vpiParameter:
\_parameter: (FETCH_BUFFER_DEPTH), line:168
|vpiName:FETCH_BUFFER_DEPTH
|INT:512
|vpiParameter:
\_parameter: (FPGA_VENDOR), line:27
|vpiName:FPGA_VENDOR
|STRING:"xilinx"
|vpiParameter:
\_parameter: (GC_UNIT_ID), line:196
|vpiName:GC_UNIT_ID
|INT:4
|vpiParameter:
\_parameter: (ICACHE_LINES), line:121
|vpiName:ICACHE_LINES
|INT:2
|vpiParameter:
\_parameter: (ICACHE_LINE_ADDR_W), line:123
|vpiName:ICACHE_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_LINE_W), line:124
|vpiName:ICACHE_LINE_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_SUB_LINE_ADDR_W), line:125
|vpiName:ICACHE_SUB_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_TAG_W), line:126
|vpiName:ICACHE_TAG_W
|INT:-2147483648
|vpiParameter:
\_parameter: (ICACHE_WAYS), line:122
|vpiName:ICACHE_WAYS
|INT:1
|vpiParameter:
\_parameter: (ITLB_DEPTH), line:146
|vpiName:ITLB_DEPTH
|INT:32
|vpiParameter:
\_parameter: (ITLB_WAYS), line:145
|vpiName:ITLB_WAYS
|INT:4
|vpiParameter:
\_parameter: (L1_CONNECTIONS), line:177
|vpiName:L1_CONNECTIONS
|INT:9
|vpiParameter:
\_parameter: (L1_DCACHE_ID), line:178
|vpiName:L1_DCACHE_ID
|INT:4
|vpiParameter:
\_parameter: (L1_DMMU_ID), line:179
|vpiName:L1_DMMU_ID
|INT:2
|vpiParameter:
\_parameter: (L1_ICACHE_ID), line:180
|vpiName:L1_ICACHE_ID
|INT:19
|vpiParameter:
\_parameter: (L1_IMMU_ID), line:181
|vpiName:L1_IMMU_ID
|INT:0
|vpiParameter:
\_parameter: (LS_UNIT_WB_ID), line:191
|vpiName:LS_UNIT_WB_ID
|INT:1
|vpiParameter:
\_parameter: (MAX_INFLIGHT_COUNT), line:167
|vpiName:MAX_INFLIGHT_COUNT
|INT:19
|vpiParameter:
\_parameter: (MEMORY_ADDR_H), line:103
|vpiName:MEMORY_ADDR_H
|INT:12
|vpiParameter:
\_parameter: (MEMORY_ADDR_L), line:102
|vpiName:MEMORY_ADDR_L
|INT:11
|vpiParameter:
\_parameter: (MEMORY_BIT_CHECK), line:104
|vpiName:MEMORY_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (MUL_UNIT_WB_ID), line:193
|vpiName:MUL_UNIT_WB_ID
|INT:512
|vpiParameter:
\_parameter: (NUM_UNITS), line:188
|vpiName:NUM_UNITS
|INT:2
|vpiParameter:
\_parameter: (NUM_WB_UNITS), line:186
|vpiName:NUM_WB_UNITS
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (RAS_DEPTH), line:161
|vpiName:RAS_DEPTH
|INT:2
|vpiParameter:
\_parameter: (RESET_VEC), line:39
|vpiName:RESET_VEC
|INT:-2147483648
|vpiParameter:
\_parameter: (SCRATCH_ADDR_H), line:99
|vpiName:SCRATCH_ADDR_H
|INT:9
|vpiParameter:
\_parameter: (SCRATCH_ADDR_L), line:98
|vpiName:SCRATCH_ADDR_L
|INT:8
|vpiParameter:
\_parameter: (SCRATCH_BIT_CHECK), line:100
|vpiName:SCRATCH_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (USE_AMO), line:70
|vpiName:USE_AMO
|INT:1
|vpiParameter:
\_parameter: (USE_BRANCH_PREDICTOR), line:158
|vpiName:USE_BRANCH_PREDICTOR
|INT:2
|vpiParameter:
\_parameter: (USE_BUS), line:88
|vpiName:USE_BUS
|INT:4
|vpiParameter:
\_parameter: (USE_DCACHE), line:92
|vpiName:USE_DCACHE
|INT:6
|vpiParameter:
\_parameter: (USE_DIV), line:49
|vpiName:USE_DIV
|INT:1
|vpiParameter:
\_parameter: (USE_DTAG_INVALIDATIONS), line:140
|vpiName:USE_DTAG_INVALIDATIONS
|INT:1879048191
|vpiParameter:
\_parameter: (USE_D_SCRATCH_MEM), line:79
|vpiName:USE_D_SCRATCH_MEM
|INT:3
|vpiParameter:
\_parameter: (USE_ICACHE), line:93
|vpiName:USE_ICACHE
|INT:7
|vpiParameter:
\_parameter: (USE_I_SCRATCH_MEM), line:78
|vpiName:USE_I_SCRATCH_MEM
|INT:2
|vpiParameter:
\_parameter: (USE_MUL), line:48
|vpiName:USE_MUL
|INT:1
|vpiParameter:
\_parameter: (WB_UNITS_WIDTH), line:187
|vpiName:WB_UNITS_WIDTH
|INT:32
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiParameter:
\_parameter: (i), line:70
|vpiName:i
|INT:4
|vpiGenScopeArray:
\_gen_scope_array: (branch_table_banks[5]), line:70
|vpiName:branch_table_banks[5]
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_table_banks.branch_table_banks[5]
|vpiGenScope:
\_gen_scope: , parent:branch_table_banks[5]
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_table_banks.branch_table_banks[5]
|vpiModule:
\_module: work@branch_predictor_ram (addr_table), file:third_party/cores/taiga/core/branch_predictor.sv, line:71
|vpiDefName:work@branch_predictor_ram
|vpiName:addr_table
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_table_banks.branch_table_banks[5].addr_table
|vpiPort:
\_port: (clk), line:32, parent:addr_table
|vpiName:clk
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (clk), line:72
|vpiName:clk
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (clk), line:32, parent:addr_table
|vpiName:clk
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_table_banks.branch_table_banks[5].addr_table.clk
|vpiNetType:36
|vpiPort:
\_port: (write_addr), line:33, parent:addr_table
|vpiName:write_addr
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (write_addr), line:72
|vpiName:write_addr
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (write_addr), line:33, parent:addr_table
|vpiName:write_addr
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_table_banks.branch_table_banks[5].addr_table.write_addr
|vpiNetType:36
|vpiRange:
\_range: , line:33
|vpiLeftRange:
\_constant: , line:33
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:33
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiPort:
\_port: (write_en), line:34, parent:addr_table
|vpiName:write_en
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (write_en), line:72
|vpiName:write_en
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (write_en), line:34, parent:addr_table
|vpiName:write_en
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_table_banks.branch_table_banks[5].addr_table.write_en
|vpiNetType:36
|vpiPort:
\_port: (read_addr), line:35, parent:addr_table
|vpiName:read_addr
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (read_addr), line:72
|vpiName:read_addr
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (read_addr), line:35, parent:addr_table
|vpiName:read_addr
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_table_banks.branch_table_banks[5].addr_table.read_addr
|vpiNetType:36
|vpiRange:
\_range: , line:35
|vpiLeftRange:
\_constant: , line:35
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:35
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiPort:
\_port: (read_en), line:36, parent:addr_table
|vpiName:read_en
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (read_en), line:72
|vpiName:read_en
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (read_en), line:36, parent:addr_table
|vpiName:read_en
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_table_banks.branch_table_banks[5].addr_table.read_en
|vpiNetType:36
|vpiPort:
\_port: (write_data), line:37, parent:addr_table
|vpiName:write_data
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (write_data), line:72
|vpiName:write_data
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (write_data), line:37, parent:addr_table
|vpiName:write_data
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_table_banks.branch_table_banks[5].addr_table.write_data
|vpiNetType:36
|vpiRange:
\_range: , line:37
|vpiLeftRange:
\_constant: , line:37
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:37
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiPort:
\_port: (read_data), line:38, parent:addr_table
|vpiName:read_data
|vpiDirection:2
|vpiHighConn:
\_ref_obj: (read_data), line:72
|vpiName:read_data
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (read_data), line:38, parent:addr_table
|vpiName:read_data
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_table_banks.branch_table_banks[5].addr_table.read_data
|vpiNetType:36
|vpiRange:
\_range: , line:38
|vpiLeftRange:
\_constant: , line:38
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:38
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (clk), line:32, parent:addr_table
|vpiNet:
\_logic_net: (write_addr), line:33, parent:addr_table
|vpiNet:
\_logic_net: (write_en), line:34, parent:addr_table
|vpiNet:
\_logic_net: (read_addr), line:35, parent:addr_table
|vpiNet:
\_logic_net: (read_en), line:36, parent:addr_table
|vpiNet:
\_logic_net: (write_data), line:37, parent:addr_table
|vpiNet:
\_logic_net: (read_data), line:38, parent:addr_table
|vpiArrayNet:
\_array_net: (branch_ram), line:40, parent:addr_table
|vpiName:branch_ram
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_table_banks.branch_table_banks[5].addr_table.branch_ram
|vpiSize:4
|vpiNet:
\_logic_net: , parent:branch_ram
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_table_banks.branch_table_banks[5].addr_table.branch_ram
|vpiNetType:36
|vpiRange:
\_range: , line:40
|vpiLeftRange:
\_constant: , line:40
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:40
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiRange:
\_range: , line:40
|vpiLeftRange:
\_constant: , line:40
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiRightRange:
\_constant: , line:40
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiParameter:
\_parameter: (ALU_UNIT_WB_ID), line:190
|vpiName:ALU_UNIT_WB_ID
|INT:32
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (BRANCH_PREDICTOR_WAYS), line:159
|vpiName:BRANCH_PREDICTOR_WAYS
|INT:9
|vpiParameter:
\_parameter: (BRANCH_TABLE_ENTRIES), line:160
|vpiName:BRANCH_TABLE_ENTRIES
|INT:4
|vpiParameter:
\_parameter: (BRANCH_UNIT_ID), line:195
|vpiName:BRANCH_UNIT_ID
|INT:8
|vpiParameter:
\_parameter: (BUS_ADDR_H), line:107
|vpiName:BUS_ADDR_H
|INT:1
|vpiParameter:
\_parameter: (BUS_ADDR_L), line:106
|vpiName:BUS_ADDR_L
|INT:0
|vpiParameter:
\_parameter: (BUS_BIT_CHECK), line:108
|vpiName:BUS_BIT_CHECK
|INT:1
|vpiParameter:
\_parameter: (BUS_TYPE), line:89
|vpiName:BUS_TYPE
|INT:5
|vpiParameter:
\_parameter: (COUNTER_W), line:42
|vpiName:COUNTER_W
|INT:33
|vpiParameter:
\_parameter: (CPU_ID), line:38
|vpiName:CPU_ID
|INT:0
|vpiParameter:
\_parameter: (C_DATA_WIDTH), line:71
|vpiName:C_DATA_WIDTH
|INT:32
|vpiParameter:
\_parameter: (C_DEPTH), line:71
|vpiName:C_DEPTH
|INT:4
|vpiParameter:
\_parameter: (C_M_AXI_ADDR_WIDTH), line:113
|vpiName:C_M_AXI_ADDR_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_DATA_WIDTH), line:114
|vpiName:C_M_AXI_DATA_WIDTH
|INT:1
|vpiParameter:
\_parameter: (DCACHE_LINES), line:133
|vpiName:DCACHE_LINES
|INT:-2146435073
|vpiParameter:
\_parameter: (DCACHE_LINE_ADDR_W), line:135
|vpiName:DCACHE_LINE_ADDR_W
|INT:1073741824
|vpiParameter:
\_parameter: (DCACHE_LINE_W), line:136
|vpiName:DCACHE_LINE_W
|INT:1342177279
|vpiParameter:
\_parameter: (DCACHE_SUB_LINE_ADDR_W), line:137
|vpiName:DCACHE_SUB_LINE_ADDR_W
|INT:4
|vpiParameter:
\_parameter: (DCACHE_TAG_W), line:138
|vpiName:DCACHE_TAG_W
|INT:1610612736
|vpiParameter:
\_parameter: (DCACHE_WAYS), line:134
|vpiName:DCACHE_WAYS
|INT:4
|vpiParameter:
\_parameter: (DIV_ALGORITHM), line:67
|vpiName:DIV_ALGORITHM
|INT:0
|vpiParameter:
\_parameter: (DIV_UNIT_WB_ID), line:192
|vpiName:DIV_UNIT_WB_ID
|INT:2
|vpiParameter:
\_parameter: (DTLB_DEPTH), line:152
|vpiName:DTLB_DEPTH
|INT:512
|vpiParameter:
\_parameter: (DTLB_WAYS), line:151
|vpiName:DTLB_WAYS
|INT:32
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (ENABLE_M_MODE), line:34
|vpiName:ENABLE_M_MODE
|INT:1
|vpiParameter:
\_parameter: (ENABLE_S_MODE), line:36
|vpiName:ENABLE_S_MODE
|INT:0
|vpiParameter:
\_parameter: (ENABLE_TRACE_INTERFACE), line:172
|vpiName:ENABLE_TRACE_INTERFACE
|INT:2
|vpiParameter:
\_parameter: (FETCH_BUFFER_DEPTH), line:168
|vpiName:FETCH_BUFFER_DEPTH
|INT:512
|vpiParameter:
\_parameter: (FPGA_VENDOR), line:27
|vpiName:FPGA_VENDOR
|STRING:"xilinx"
|vpiParameter:
\_parameter: (GC_UNIT_ID), line:196
|vpiName:GC_UNIT_ID
|INT:4
|vpiParameter:
\_parameter: (ICACHE_LINES), line:121
|vpiName:ICACHE_LINES
|INT:2
|vpiParameter:
\_parameter: (ICACHE_LINE_ADDR_W), line:123
|vpiName:ICACHE_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_LINE_W), line:124
|vpiName:ICACHE_LINE_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_SUB_LINE_ADDR_W), line:125
|vpiName:ICACHE_SUB_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_TAG_W), line:126
|vpiName:ICACHE_TAG_W
|INT:-2147483648
|vpiParameter:
\_parameter: (ICACHE_WAYS), line:122
|vpiName:ICACHE_WAYS
|INT:1
|vpiParameter:
\_parameter: (ITLB_DEPTH), line:146
|vpiName:ITLB_DEPTH
|INT:32
|vpiParameter:
\_parameter: (ITLB_WAYS), line:145
|vpiName:ITLB_WAYS
|INT:4
|vpiParameter:
\_parameter: (L1_CONNECTIONS), line:177
|vpiName:L1_CONNECTIONS
|INT:9
|vpiParameter:
\_parameter: (L1_DCACHE_ID), line:178
|vpiName:L1_DCACHE_ID
|INT:4
|vpiParameter:
\_parameter: (L1_DMMU_ID), line:179
|vpiName:L1_DMMU_ID
|INT:2
|vpiParameter:
\_parameter: (L1_ICACHE_ID), line:180
|vpiName:L1_ICACHE_ID
|INT:19
|vpiParameter:
\_parameter: (L1_IMMU_ID), line:181
|vpiName:L1_IMMU_ID
|INT:0
|vpiParameter:
\_parameter: (LS_UNIT_WB_ID), line:191
|vpiName:LS_UNIT_WB_ID
|INT:1
|vpiParameter:
\_parameter: (MAX_INFLIGHT_COUNT), line:167
|vpiName:MAX_INFLIGHT_COUNT
|INT:19
|vpiParameter:
\_parameter: (MEMORY_ADDR_H), line:103
|vpiName:MEMORY_ADDR_H
|INT:12
|vpiParameter:
\_parameter: (MEMORY_ADDR_L), line:102
|vpiName:MEMORY_ADDR_L
|INT:11
|vpiParameter:
\_parameter: (MEMORY_BIT_CHECK), line:104
|vpiName:MEMORY_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (MUL_UNIT_WB_ID), line:193
|vpiName:MUL_UNIT_WB_ID
|INT:512
|vpiParameter:
\_parameter: (NUM_UNITS), line:188
|vpiName:NUM_UNITS
|INT:2
|vpiParameter:
\_parameter: (NUM_WB_UNITS), line:186
|vpiName:NUM_WB_UNITS
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (RAS_DEPTH), line:161
|vpiName:RAS_DEPTH
|INT:2
|vpiParameter:
\_parameter: (RESET_VEC), line:39
|vpiName:RESET_VEC
|INT:-2147483648
|vpiParameter:
\_parameter: (SCRATCH_ADDR_H), line:99
|vpiName:SCRATCH_ADDR_H
|INT:9
|vpiParameter:
\_parameter: (SCRATCH_ADDR_L), line:98
|vpiName:SCRATCH_ADDR_L
|INT:8
|vpiParameter:
\_parameter: (SCRATCH_BIT_CHECK), line:100
|vpiName:SCRATCH_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (USE_AMO), line:70
|vpiName:USE_AMO
|INT:1
|vpiParameter:
\_parameter: (USE_BRANCH_PREDICTOR), line:158
|vpiName:USE_BRANCH_PREDICTOR
|INT:2
|vpiParameter:
\_parameter: (USE_BUS), line:88
|vpiName:USE_BUS
|INT:4
|vpiParameter:
\_parameter: (USE_DCACHE), line:92
|vpiName:USE_DCACHE
|INT:6
|vpiParameter:
\_parameter: (USE_DIV), line:49
|vpiName:USE_DIV
|INT:1
|vpiParameter:
\_parameter: (USE_DTAG_INVALIDATIONS), line:140
|vpiName:USE_DTAG_INVALIDATIONS
|INT:1879048191
|vpiParameter:
\_parameter: (USE_D_SCRATCH_MEM), line:79
|vpiName:USE_D_SCRATCH_MEM
|INT:3
|vpiParameter:
\_parameter: (USE_ICACHE), line:93
|vpiName:USE_ICACHE
|INT:7
|vpiParameter:
\_parameter: (USE_I_SCRATCH_MEM), line:78
|vpiName:USE_I_SCRATCH_MEM
|INT:2
|vpiParameter:
\_parameter: (USE_MUL), line:48
|vpiName:USE_MUL
|INT:1
|vpiParameter:
\_parameter: (WB_UNITS_WIDTH), line:187
|vpiName:WB_UNITS_WIDTH
|INT:32
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiParameter:
\_parameter: (ALU_UNIT_WB_ID), line:190
|vpiName:ALU_UNIT_WB_ID
|INT:32
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (BRANCH_PREDICTOR_WAYS), line:159
|vpiName:BRANCH_PREDICTOR_WAYS
|INT:9
|vpiParameter:
\_parameter: (BRANCH_TABLE_ENTRIES), line:160
|vpiName:BRANCH_TABLE_ENTRIES
|INT:4
|vpiParameter:
\_parameter: (BRANCH_UNIT_ID), line:195
|vpiName:BRANCH_UNIT_ID
|INT:8
|vpiParameter:
\_parameter: (BUS_ADDR_H), line:107
|vpiName:BUS_ADDR_H
|INT:1
|vpiParameter:
\_parameter: (BUS_ADDR_L), line:106
|vpiName:BUS_ADDR_L
|INT:0
|vpiParameter:
\_parameter: (BUS_BIT_CHECK), line:108
|vpiName:BUS_BIT_CHECK
|INT:1
|vpiParameter:
\_parameter: (BUS_TYPE), line:89
|vpiName:BUS_TYPE
|INT:5
|vpiParameter:
\_parameter: (COUNTER_W), line:42
|vpiName:COUNTER_W
|INT:33
|vpiParameter:
\_parameter: (CPU_ID), line:38
|vpiName:CPU_ID
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_ADDR_WIDTH), line:113
|vpiName:C_M_AXI_ADDR_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_DATA_WIDTH), line:114
|vpiName:C_M_AXI_DATA_WIDTH
|INT:1
|vpiParameter:
\_parameter: (DCACHE_LINES), line:133
|vpiName:DCACHE_LINES
|INT:-2146435073
|vpiParameter:
\_parameter: (DCACHE_LINE_ADDR_W), line:135
|vpiName:DCACHE_LINE_ADDR_W
|INT:1073741824
|vpiParameter:
\_parameter: (DCACHE_LINE_W), line:136
|vpiName:DCACHE_LINE_W
|INT:1342177279
|vpiParameter:
\_parameter: (DCACHE_SUB_LINE_ADDR_W), line:137
|vpiName:DCACHE_SUB_LINE_ADDR_W
|INT:4
|vpiParameter:
\_parameter: (DCACHE_TAG_W), line:138
|vpiName:DCACHE_TAG_W
|INT:1610612736
|vpiParameter:
\_parameter: (DCACHE_WAYS), line:134
|vpiName:DCACHE_WAYS
|INT:4
|vpiParameter:
\_parameter: (DIV_ALGORITHM), line:67
|vpiName:DIV_ALGORITHM
|INT:0
|vpiParameter:
\_parameter: (DIV_UNIT_WB_ID), line:192
|vpiName:DIV_UNIT_WB_ID
|INT:2
|vpiParameter:
\_parameter: (DTLB_DEPTH), line:152
|vpiName:DTLB_DEPTH
|INT:512
|vpiParameter:
\_parameter: (DTLB_WAYS), line:151
|vpiName:DTLB_WAYS
|INT:32
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (ENABLE_M_MODE), line:34
|vpiName:ENABLE_M_MODE
|INT:1
|vpiParameter:
\_parameter: (ENABLE_S_MODE), line:36
|vpiName:ENABLE_S_MODE
|INT:0
|vpiParameter:
\_parameter: (ENABLE_TRACE_INTERFACE), line:172
|vpiName:ENABLE_TRACE_INTERFACE
|INT:2
|vpiParameter:
\_parameter: (FETCH_BUFFER_DEPTH), line:168
|vpiName:FETCH_BUFFER_DEPTH
|INT:512
|vpiParameter:
\_parameter: (FPGA_VENDOR), line:27
|vpiName:FPGA_VENDOR
|STRING:"xilinx"
|vpiParameter:
\_parameter: (GC_UNIT_ID), line:196
|vpiName:GC_UNIT_ID
|INT:4
|vpiParameter:
\_parameter: (ICACHE_LINES), line:121
|vpiName:ICACHE_LINES
|INT:2
|vpiParameter:
\_parameter: (ICACHE_LINE_ADDR_W), line:123
|vpiName:ICACHE_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_LINE_W), line:124
|vpiName:ICACHE_LINE_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_SUB_LINE_ADDR_W), line:125
|vpiName:ICACHE_SUB_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_TAG_W), line:126
|vpiName:ICACHE_TAG_W
|INT:-2147483648
|vpiParameter:
\_parameter: (ICACHE_WAYS), line:122
|vpiName:ICACHE_WAYS
|INT:1
|vpiParameter:
\_parameter: (ITLB_DEPTH), line:146
|vpiName:ITLB_DEPTH
|INT:32
|vpiParameter:
\_parameter: (ITLB_WAYS), line:145
|vpiName:ITLB_WAYS
|INT:4
|vpiParameter:
\_parameter: (L1_CONNECTIONS), line:177
|vpiName:L1_CONNECTIONS
|INT:9
|vpiParameter:
\_parameter: (L1_DCACHE_ID), line:178
|vpiName:L1_DCACHE_ID
|INT:4
|vpiParameter:
\_parameter: (L1_DMMU_ID), line:179
|vpiName:L1_DMMU_ID
|INT:2
|vpiParameter:
\_parameter: (L1_ICACHE_ID), line:180
|vpiName:L1_ICACHE_ID
|INT:19
|vpiParameter:
\_parameter: (L1_IMMU_ID), line:181
|vpiName:L1_IMMU_ID
|INT:0
|vpiParameter:
\_parameter: (LS_UNIT_WB_ID), line:191
|vpiName:LS_UNIT_WB_ID
|INT:1
|vpiParameter:
\_parameter: (MAX_INFLIGHT_COUNT), line:167
|vpiName:MAX_INFLIGHT_COUNT
|INT:19
|vpiParameter:
\_parameter: (MEMORY_ADDR_H), line:103
|vpiName:MEMORY_ADDR_H
|INT:12
|vpiParameter:
\_parameter: (MEMORY_ADDR_L), line:102
|vpiName:MEMORY_ADDR_L
|INT:11
|vpiParameter:
\_parameter: (MEMORY_BIT_CHECK), line:104
|vpiName:MEMORY_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (MUL_UNIT_WB_ID), line:193
|vpiName:MUL_UNIT_WB_ID
|INT:512
|vpiParameter:
\_parameter: (NUM_UNITS), line:188
|vpiName:NUM_UNITS
|INT:2
|vpiParameter:
\_parameter: (NUM_WB_UNITS), line:186
|vpiName:NUM_WB_UNITS
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (RAS_DEPTH), line:161
|vpiName:RAS_DEPTH
|INT:2
|vpiParameter:
\_parameter: (RESET_VEC), line:39
|vpiName:RESET_VEC
|INT:-2147483648
|vpiParameter:
\_parameter: (SCRATCH_ADDR_H), line:99
|vpiName:SCRATCH_ADDR_H
|INT:9
|vpiParameter:
\_parameter: (SCRATCH_ADDR_L), line:98
|vpiName:SCRATCH_ADDR_L
|INT:8
|vpiParameter:
\_parameter: (SCRATCH_BIT_CHECK), line:100
|vpiName:SCRATCH_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (USE_AMO), line:70
|vpiName:USE_AMO
|INT:1
|vpiParameter:
\_parameter: (USE_BRANCH_PREDICTOR), line:158
|vpiName:USE_BRANCH_PREDICTOR
|INT:2
|vpiParameter:
\_parameter: (USE_BUS), line:88
|vpiName:USE_BUS
|INT:4
|vpiParameter:
\_parameter: (USE_DCACHE), line:92
|vpiName:USE_DCACHE
|INT:6
|vpiParameter:
\_parameter: (USE_DIV), line:49
|vpiName:USE_DIV
|INT:1
|vpiParameter:
\_parameter: (USE_DTAG_INVALIDATIONS), line:140
|vpiName:USE_DTAG_INVALIDATIONS
|INT:1879048191
|vpiParameter:
\_parameter: (USE_D_SCRATCH_MEM), line:79
|vpiName:USE_D_SCRATCH_MEM
|INT:3
|vpiParameter:
\_parameter: (USE_ICACHE), line:93
|vpiName:USE_ICACHE
|INT:7
|vpiParameter:
\_parameter: (USE_I_SCRATCH_MEM), line:78
|vpiName:USE_I_SCRATCH_MEM
|INT:2
|vpiParameter:
\_parameter: (USE_MUL), line:48
|vpiName:USE_MUL
|INT:1
|vpiParameter:
\_parameter: (WB_UNITS_WIDTH), line:187
|vpiName:WB_UNITS_WIDTH
|INT:32
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiParameter:
\_parameter: (i), line:70
|vpiName:i
|INT:5
|vpiGenScopeArray:
\_gen_scope_array: (branch_table_banks[6]), line:70
|vpiName:branch_table_banks[6]
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_table_banks.branch_table_banks[6]
|vpiGenScope:
\_gen_scope: , parent:branch_table_banks[6]
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_table_banks.branch_table_banks[6]
|vpiModule:
\_module: work@branch_predictor_ram (addr_table), file:third_party/cores/taiga/core/branch_predictor.sv, line:71
|vpiDefName:work@branch_predictor_ram
|vpiName:addr_table
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_table_banks.branch_table_banks[6].addr_table
|vpiPort:
\_port: (clk), line:32, parent:addr_table
|vpiName:clk
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (clk), line:72
|vpiName:clk
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (clk), line:32, parent:addr_table
|vpiName:clk
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_table_banks.branch_table_banks[6].addr_table.clk
|vpiNetType:36
|vpiPort:
\_port: (write_addr), line:33, parent:addr_table
|vpiName:write_addr
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (write_addr), line:72
|vpiName:write_addr
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (write_addr), line:33, parent:addr_table
|vpiName:write_addr
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_table_banks.branch_table_banks[6].addr_table.write_addr
|vpiNetType:36
|vpiRange:
\_range: , line:33
|vpiLeftRange:
\_constant: , line:33
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:33
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiPort:
\_port: (write_en), line:34, parent:addr_table
|vpiName:write_en
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (write_en), line:72
|vpiName:write_en
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (write_en), line:34, parent:addr_table
|vpiName:write_en
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_table_banks.branch_table_banks[6].addr_table.write_en
|vpiNetType:36
|vpiPort:
\_port: (read_addr), line:35, parent:addr_table
|vpiName:read_addr
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (read_addr), line:72
|vpiName:read_addr
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (read_addr), line:35, parent:addr_table
|vpiName:read_addr
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_table_banks.branch_table_banks[6].addr_table.read_addr
|vpiNetType:36
|vpiRange:
\_range: , line:35
|vpiLeftRange:
\_constant: , line:35
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:35
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiPort:
\_port: (read_en), line:36, parent:addr_table
|vpiName:read_en
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (read_en), line:72
|vpiName:read_en
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (read_en), line:36, parent:addr_table
|vpiName:read_en
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_table_banks.branch_table_banks[6].addr_table.read_en
|vpiNetType:36
|vpiPort:
\_port: (write_data), line:37, parent:addr_table
|vpiName:write_data
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (write_data), line:72
|vpiName:write_data
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (write_data), line:37, parent:addr_table
|vpiName:write_data
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_table_banks.branch_table_banks[6].addr_table.write_data
|vpiNetType:36
|vpiRange:
\_range: , line:37
|vpiLeftRange:
\_constant: , line:37
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:37
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiPort:
\_port: (read_data), line:38, parent:addr_table
|vpiName:read_data
|vpiDirection:2
|vpiHighConn:
\_ref_obj: (read_data), line:72
|vpiName:read_data
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (read_data), line:38, parent:addr_table
|vpiName:read_data
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_table_banks.branch_table_banks[6].addr_table.read_data
|vpiNetType:36
|vpiRange:
\_range: , line:38
|vpiLeftRange:
\_constant: , line:38
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:38
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (clk), line:32, parent:addr_table
|vpiNet:
\_logic_net: (write_addr), line:33, parent:addr_table
|vpiNet:
\_logic_net: (write_en), line:34, parent:addr_table
|vpiNet:
\_logic_net: (read_addr), line:35, parent:addr_table
|vpiNet:
\_logic_net: (read_en), line:36, parent:addr_table
|vpiNet:
\_logic_net: (write_data), line:37, parent:addr_table
|vpiNet:
\_logic_net: (read_data), line:38, parent:addr_table
|vpiArrayNet:
\_array_net: (branch_ram), line:40, parent:addr_table
|vpiName:branch_ram
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_table_banks.branch_table_banks[6].addr_table.branch_ram
|vpiSize:4
|vpiNet:
\_logic_net: , parent:branch_ram
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_table_banks.branch_table_banks[6].addr_table.branch_ram
|vpiNetType:36
|vpiRange:
\_range: , line:40
|vpiLeftRange:
\_constant: , line:40
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:40
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiRange:
\_range: , line:40
|vpiLeftRange:
\_constant: , line:40
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiRightRange:
\_constant: , line:40
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiParameter:
\_parameter: (ALU_UNIT_WB_ID), line:190
|vpiName:ALU_UNIT_WB_ID
|INT:32
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (BRANCH_PREDICTOR_WAYS), line:159
|vpiName:BRANCH_PREDICTOR_WAYS
|INT:9
|vpiParameter:
\_parameter: (BRANCH_TABLE_ENTRIES), line:160
|vpiName:BRANCH_TABLE_ENTRIES
|INT:4
|vpiParameter:
\_parameter: (BRANCH_UNIT_ID), line:195
|vpiName:BRANCH_UNIT_ID
|INT:8
|vpiParameter:
\_parameter: (BUS_ADDR_H), line:107
|vpiName:BUS_ADDR_H
|INT:1
|vpiParameter:
\_parameter: (BUS_ADDR_L), line:106
|vpiName:BUS_ADDR_L
|INT:0
|vpiParameter:
\_parameter: (BUS_BIT_CHECK), line:108
|vpiName:BUS_BIT_CHECK
|INT:1
|vpiParameter:
\_parameter: (BUS_TYPE), line:89
|vpiName:BUS_TYPE
|INT:5
|vpiParameter:
\_parameter: (COUNTER_W), line:42
|vpiName:COUNTER_W
|INT:33
|vpiParameter:
\_parameter: (CPU_ID), line:38
|vpiName:CPU_ID
|INT:0
|vpiParameter:
\_parameter: (C_DATA_WIDTH), line:71
|vpiName:C_DATA_WIDTH
|INT:32
|vpiParameter:
\_parameter: (C_DEPTH), line:71
|vpiName:C_DEPTH
|INT:4
|vpiParameter:
\_parameter: (C_M_AXI_ADDR_WIDTH), line:113
|vpiName:C_M_AXI_ADDR_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_DATA_WIDTH), line:114
|vpiName:C_M_AXI_DATA_WIDTH
|INT:1
|vpiParameter:
\_parameter: (DCACHE_LINES), line:133
|vpiName:DCACHE_LINES
|INT:-2146435073
|vpiParameter:
\_parameter: (DCACHE_LINE_ADDR_W), line:135
|vpiName:DCACHE_LINE_ADDR_W
|INT:1073741824
|vpiParameter:
\_parameter: (DCACHE_LINE_W), line:136
|vpiName:DCACHE_LINE_W
|INT:1342177279
|vpiParameter:
\_parameter: (DCACHE_SUB_LINE_ADDR_W), line:137
|vpiName:DCACHE_SUB_LINE_ADDR_W
|INT:4
|vpiParameter:
\_parameter: (DCACHE_TAG_W), line:138
|vpiName:DCACHE_TAG_W
|INT:1610612736
|vpiParameter:
\_parameter: (DCACHE_WAYS), line:134
|vpiName:DCACHE_WAYS
|INT:4
|vpiParameter:
\_parameter: (DIV_ALGORITHM), line:67
|vpiName:DIV_ALGORITHM
|INT:0
|vpiParameter:
\_parameter: (DIV_UNIT_WB_ID), line:192
|vpiName:DIV_UNIT_WB_ID
|INT:2
|vpiParameter:
\_parameter: (DTLB_DEPTH), line:152
|vpiName:DTLB_DEPTH
|INT:512
|vpiParameter:
\_parameter: (DTLB_WAYS), line:151
|vpiName:DTLB_WAYS
|INT:32
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (ENABLE_M_MODE), line:34
|vpiName:ENABLE_M_MODE
|INT:1
|vpiParameter:
\_parameter: (ENABLE_S_MODE), line:36
|vpiName:ENABLE_S_MODE
|INT:0
|vpiParameter:
\_parameter: (ENABLE_TRACE_INTERFACE), line:172
|vpiName:ENABLE_TRACE_INTERFACE
|INT:2
|vpiParameter:
\_parameter: (FETCH_BUFFER_DEPTH), line:168
|vpiName:FETCH_BUFFER_DEPTH
|INT:512
|vpiParameter:
\_parameter: (FPGA_VENDOR), line:27
|vpiName:FPGA_VENDOR
|STRING:"xilinx"
|vpiParameter:
\_parameter: (GC_UNIT_ID), line:196
|vpiName:GC_UNIT_ID
|INT:4
|vpiParameter:
\_parameter: (ICACHE_LINES), line:121
|vpiName:ICACHE_LINES
|INT:2
|vpiParameter:
\_parameter: (ICACHE_LINE_ADDR_W), line:123
|vpiName:ICACHE_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_LINE_W), line:124
|vpiName:ICACHE_LINE_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_SUB_LINE_ADDR_W), line:125
|vpiName:ICACHE_SUB_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_TAG_W), line:126
|vpiName:ICACHE_TAG_W
|INT:-2147483648
|vpiParameter:
\_parameter: (ICACHE_WAYS), line:122
|vpiName:ICACHE_WAYS
|INT:1
|vpiParameter:
\_parameter: (ITLB_DEPTH), line:146
|vpiName:ITLB_DEPTH
|INT:32
|vpiParameter:
\_parameter: (ITLB_WAYS), line:145
|vpiName:ITLB_WAYS
|INT:4
|vpiParameter:
\_parameter: (L1_CONNECTIONS), line:177
|vpiName:L1_CONNECTIONS
|INT:9
|vpiParameter:
\_parameter: (L1_DCACHE_ID), line:178
|vpiName:L1_DCACHE_ID
|INT:4
|vpiParameter:
\_parameter: (L1_DMMU_ID), line:179
|vpiName:L1_DMMU_ID
|INT:2
|vpiParameter:
\_parameter: (L1_ICACHE_ID), line:180
|vpiName:L1_ICACHE_ID
|INT:19
|vpiParameter:
\_parameter: (L1_IMMU_ID), line:181
|vpiName:L1_IMMU_ID
|INT:0
|vpiParameter:
\_parameter: (LS_UNIT_WB_ID), line:191
|vpiName:LS_UNIT_WB_ID
|INT:1
|vpiParameter:
\_parameter: (MAX_INFLIGHT_COUNT), line:167
|vpiName:MAX_INFLIGHT_COUNT
|INT:19
|vpiParameter:
\_parameter: (MEMORY_ADDR_H), line:103
|vpiName:MEMORY_ADDR_H
|INT:12
|vpiParameter:
\_parameter: (MEMORY_ADDR_L), line:102
|vpiName:MEMORY_ADDR_L
|INT:11
|vpiParameter:
\_parameter: (MEMORY_BIT_CHECK), line:104
|vpiName:MEMORY_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (MUL_UNIT_WB_ID), line:193
|vpiName:MUL_UNIT_WB_ID
|INT:512
|vpiParameter:
\_parameter: (NUM_UNITS), line:188
|vpiName:NUM_UNITS
|INT:2
|vpiParameter:
\_parameter: (NUM_WB_UNITS), line:186
|vpiName:NUM_WB_UNITS
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (RAS_DEPTH), line:161
|vpiName:RAS_DEPTH
|INT:2
|vpiParameter:
\_parameter: (RESET_VEC), line:39
|vpiName:RESET_VEC
|INT:-2147483648
|vpiParameter:
\_parameter: (SCRATCH_ADDR_H), line:99
|vpiName:SCRATCH_ADDR_H
|INT:9
|vpiParameter:
\_parameter: (SCRATCH_ADDR_L), line:98
|vpiName:SCRATCH_ADDR_L
|INT:8
|vpiParameter:
\_parameter: (SCRATCH_BIT_CHECK), line:100
|vpiName:SCRATCH_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (USE_AMO), line:70
|vpiName:USE_AMO
|INT:1
|vpiParameter:
\_parameter: (USE_BRANCH_PREDICTOR), line:158
|vpiName:USE_BRANCH_PREDICTOR
|INT:2
|vpiParameter:
\_parameter: (USE_BUS), line:88
|vpiName:USE_BUS
|INT:4
|vpiParameter:
\_parameter: (USE_DCACHE), line:92
|vpiName:USE_DCACHE
|INT:6
|vpiParameter:
\_parameter: (USE_DIV), line:49
|vpiName:USE_DIV
|INT:1
|vpiParameter:
\_parameter: (USE_DTAG_INVALIDATIONS), line:140
|vpiName:USE_DTAG_INVALIDATIONS
|INT:1879048191
|vpiParameter:
\_parameter: (USE_D_SCRATCH_MEM), line:79
|vpiName:USE_D_SCRATCH_MEM
|INT:3
|vpiParameter:
\_parameter: (USE_ICACHE), line:93
|vpiName:USE_ICACHE
|INT:7
|vpiParameter:
\_parameter: (USE_I_SCRATCH_MEM), line:78
|vpiName:USE_I_SCRATCH_MEM
|INT:2
|vpiParameter:
\_parameter: (USE_MUL), line:48
|vpiName:USE_MUL
|INT:1
|vpiParameter:
\_parameter: (WB_UNITS_WIDTH), line:187
|vpiName:WB_UNITS_WIDTH
|INT:32
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiParameter:
\_parameter: (ALU_UNIT_WB_ID), line:190
|vpiName:ALU_UNIT_WB_ID
|INT:32
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (BRANCH_PREDICTOR_WAYS), line:159
|vpiName:BRANCH_PREDICTOR_WAYS
|INT:9
|vpiParameter:
\_parameter: (BRANCH_TABLE_ENTRIES), line:160
|vpiName:BRANCH_TABLE_ENTRIES
|INT:4
|vpiParameter:
\_parameter: (BRANCH_UNIT_ID), line:195
|vpiName:BRANCH_UNIT_ID
|INT:8
|vpiParameter:
\_parameter: (BUS_ADDR_H), line:107
|vpiName:BUS_ADDR_H
|INT:1
|vpiParameter:
\_parameter: (BUS_ADDR_L), line:106
|vpiName:BUS_ADDR_L
|INT:0
|vpiParameter:
\_parameter: (BUS_BIT_CHECK), line:108
|vpiName:BUS_BIT_CHECK
|INT:1
|vpiParameter:
\_parameter: (BUS_TYPE), line:89
|vpiName:BUS_TYPE
|INT:5
|vpiParameter:
\_parameter: (COUNTER_W), line:42
|vpiName:COUNTER_W
|INT:33
|vpiParameter:
\_parameter: (CPU_ID), line:38
|vpiName:CPU_ID
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_ADDR_WIDTH), line:113
|vpiName:C_M_AXI_ADDR_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_DATA_WIDTH), line:114
|vpiName:C_M_AXI_DATA_WIDTH
|INT:1
|vpiParameter:
\_parameter: (DCACHE_LINES), line:133
|vpiName:DCACHE_LINES
|INT:-2146435073
|vpiParameter:
\_parameter: (DCACHE_LINE_ADDR_W), line:135
|vpiName:DCACHE_LINE_ADDR_W
|INT:1073741824
|vpiParameter:
\_parameter: (DCACHE_LINE_W), line:136
|vpiName:DCACHE_LINE_W
|INT:1342177279
|vpiParameter:
\_parameter: (DCACHE_SUB_LINE_ADDR_W), line:137
|vpiName:DCACHE_SUB_LINE_ADDR_W
|INT:4
|vpiParameter:
\_parameter: (DCACHE_TAG_W), line:138
|vpiName:DCACHE_TAG_W
|INT:1610612736
|vpiParameter:
\_parameter: (DCACHE_WAYS), line:134
|vpiName:DCACHE_WAYS
|INT:4
|vpiParameter:
\_parameter: (DIV_ALGORITHM), line:67
|vpiName:DIV_ALGORITHM
|INT:0
|vpiParameter:
\_parameter: (DIV_UNIT_WB_ID), line:192
|vpiName:DIV_UNIT_WB_ID
|INT:2
|vpiParameter:
\_parameter: (DTLB_DEPTH), line:152
|vpiName:DTLB_DEPTH
|INT:512
|vpiParameter:
\_parameter: (DTLB_WAYS), line:151
|vpiName:DTLB_WAYS
|INT:32
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (ENABLE_M_MODE), line:34
|vpiName:ENABLE_M_MODE
|INT:1
|vpiParameter:
\_parameter: (ENABLE_S_MODE), line:36
|vpiName:ENABLE_S_MODE
|INT:0
|vpiParameter:
\_parameter: (ENABLE_TRACE_INTERFACE), line:172
|vpiName:ENABLE_TRACE_INTERFACE
|INT:2
|vpiParameter:
\_parameter: (FETCH_BUFFER_DEPTH), line:168
|vpiName:FETCH_BUFFER_DEPTH
|INT:512
|vpiParameter:
\_parameter: (FPGA_VENDOR), line:27
|vpiName:FPGA_VENDOR
|STRING:"xilinx"
|vpiParameter:
\_parameter: (GC_UNIT_ID), line:196
|vpiName:GC_UNIT_ID
|INT:4
|vpiParameter:
\_parameter: (ICACHE_LINES), line:121
|vpiName:ICACHE_LINES
|INT:2
|vpiParameter:
\_parameter: (ICACHE_LINE_ADDR_W), line:123
|vpiName:ICACHE_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_LINE_W), line:124
|vpiName:ICACHE_LINE_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_SUB_LINE_ADDR_W), line:125
|vpiName:ICACHE_SUB_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_TAG_W), line:126
|vpiName:ICACHE_TAG_W
|INT:-2147483648
|vpiParameter:
\_parameter: (ICACHE_WAYS), line:122
|vpiName:ICACHE_WAYS
|INT:1
|vpiParameter:
\_parameter: (ITLB_DEPTH), line:146
|vpiName:ITLB_DEPTH
|INT:32
|vpiParameter:
\_parameter: (ITLB_WAYS), line:145
|vpiName:ITLB_WAYS
|INT:4
|vpiParameter:
\_parameter: (L1_CONNECTIONS), line:177
|vpiName:L1_CONNECTIONS
|INT:9
|vpiParameter:
\_parameter: (L1_DCACHE_ID), line:178
|vpiName:L1_DCACHE_ID
|INT:4
|vpiParameter:
\_parameter: (L1_DMMU_ID), line:179
|vpiName:L1_DMMU_ID
|INT:2
|vpiParameter:
\_parameter: (L1_ICACHE_ID), line:180
|vpiName:L1_ICACHE_ID
|INT:19
|vpiParameter:
\_parameter: (L1_IMMU_ID), line:181
|vpiName:L1_IMMU_ID
|INT:0
|vpiParameter:
\_parameter: (LS_UNIT_WB_ID), line:191
|vpiName:LS_UNIT_WB_ID
|INT:1
|vpiParameter:
\_parameter: (MAX_INFLIGHT_COUNT), line:167
|vpiName:MAX_INFLIGHT_COUNT
|INT:19
|vpiParameter:
\_parameter: (MEMORY_ADDR_H), line:103
|vpiName:MEMORY_ADDR_H
|INT:12
|vpiParameter:
\_parameter: (MEMORY_ADDR_L), line:102
|vpiName:MEMORY_ADDR_L
|INT:11
|vpiParameter:
\_parameter: (MEMORY_BIT_CHECK), line:104
|vpiName:MEMORY_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (MUL_UNIT_WB_ID), line:193
|vpiName:MUL_UNIT_WB_ID
|INT:512
|vpiParameter:
\_parameter: (NUM_UNITS), line:188
|vpiName:NUM_UNITS
|INT:2
|vpiParameter:
\_parameter: (NUM_WB_UNITS), line:186
|vpiName:NUM_WB_UNITS
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (RAS_DEPTH), line:161
|vpiName:RAS_DEPTH
|INT:2
|vpiParameter:
\_parameter: (RESET_VEC), line:39
|vpiName:RESET_VEC
|INT:-2147483648
|vpiParameter:
\_parameter: (SCRATCH_ADDR_H), line:99
|vpiName:SCRATCH_ADDR_H
|INT:9
|vpiParameter:
\_parameter: (SCRATCH_ADDR_L), line:98
|vpiName:SCRATCH_ADDR_L
|INT:8
|vpiParameter:
\_parameter: (SCRATCH_BIT_CHECK), line:100
|vpiName:SCRATCH_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (USE_AMO), line:70
|vpiName:USE_AMO
|INT:1
|vpiParameter:
\_parameter: (USE_BRANCH_PREDICTOR), line:158
|vpiName:USE_BRANCH_PREDICTOR
|INT:2
|vpiParameter:
\_parameter: (USE_BUS), line:88
|vpiName:USE_BUS
|INT:4
|vpiParameter:
\_parameter: (USE_DCACHE), line:92
|vpiName:USE_DCACHE
|INT:6
|vpiParameter:
\_parameter: (USE_DIV), line:49
|vpiName:USE_DIV
|INT:1
|vpiParameter:
\_parameter: (USE_DTAG_INVALIDATIONS), line:140
|vpiName:USE_DTAG_INVALIDATIONS
|INT:1879048191
|vpiParameter:
\_parameter: (USE_D_SCRATCH_MEM), line:79
|vpiName:USE_D_SCRATCH_MEM
|INT:3
|vpiParameter:
\_parameter: (USE_ICACHE), line:93
|vpiName:USE_ICACHE
|INT:7
|vpiParameter:
\_parameter: (USE_I_SCRATCH_MEM), line:78
|vpiName:USE_I_SCRATCH_MEM
|INT:2
|vpiParameter:
\_parameter: (USE_MUL), line:48
|vpiName:USE_MUL
|INT:1
|vpiParameter:
\_parameter: (WB_UNITS_WIDTH), line:187
|vpiName:WB_UNITS_WIDTH
|INT:32
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiParameter:
\_parameter: (i), line:70
|vpiName:i
|INT:6
|vpiGenScopeArray:
\_gen_scope_array: (branch_table_banks[7]), line:70
|vpiName:branch_table_banks[7]
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_table_banks.branch_table_banks[7]
|vpiGenScope:
\_gen_scope: , parent:branch_table_banks[7]
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_table_banks.branch_table_banks[7]
|vpiModule:
\_module: work@branch_predictor_ram (addr_table), file:third_party/cores/taiga/core/branch_predictor.sv, line:71
|vpiDefName:work@branch_predictor_ram
|vpiName:addr_table
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_table_banks.branch_table_banks[7].addr_table
|vpiPort:
\_port: (clk), line:32, parent:addr_table
|vpiName:clk
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (clk), line:72
|vpiName:clk
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (clk), line:32, parent:addr_table
|vpiName:clk
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_table_banks.branch_table_banks[7].addr_table.clk
|vpiNetType:36
|vpiPort:
\_port: (write_addr), line:33, parent:addr_table
|vpiName:write_addr
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (write_addr), line:72
|vpiName:write_addr
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (write_addr), line:33, parent:addr_table
|vpiName:write_addr
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_table_banks.branch_table_banks[7].addr_table.write_addr
|vpiNetType:36
|vpiRange:
\_range: , line:33
|vpiLeftRange:
\_constant: , line:33
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:33
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiPort:
\_port: (write_en), line:34, parent:addr_table
|vpiName:write_en
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (write_en), line:72
|vpiName:write_en
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (write_en), line:34, parent:addr_table
|vpiName:write_en
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_table_banks.branch_table_banks[7].addr_table.write_en
|vpiNetType:36
|vpiPort:
\_port: (read_addr), line:35, parent:addr_table
|vpiName:read_addr
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (read_addr), line:72
|vpiName:read_addr
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (read_addr), line:35, parent:addr_table
|vpiName:read_addr
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_table_banks.branch_table_banks[7].addr_table.read_addr
|vpiNetType:36
|vpiRange:
\_range: , line:35
|vpiLeftRange:
\_constant: , line:35
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:35
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiPort:
\_port: (read_en), line:36, parent:addr_table
|vpiName:read_en
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (read_en), line:72
|vpiName:read_en
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (read_en), line:36, parent:addr_table
|vpiName:read_en
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_table_banks.branch_table_banks[7].addr_table.read_en
|vpiNetType:36
|vpiPort:
\_port: (write_data), line:37, parent:addr_table
|vpiName:write_data
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (write_data), line:72
|vpiName:write_data
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (write_data), line:37, parent:addr_table
|vpiName:write_data
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_table_banks.branch_table_banks[7].addr_table.write_data
|vpiNetType:36
|vpiRange:
\_range: , line:37
|vpiLeftRange:
\_constant: , line:37
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:37
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiPort:
\_port: (read_data), line:38, parent:addr_table
|vpiName:read_data
|vpiDirection:2
|vpiHighConn:
\_ref_obj: (read_data), line:72
|vpiName:read_data
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (read_data), line:38, parent:addr_table
|vpiName:read_data
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_table_banks.branch_table_banks[7].addr_table.read_data
|vpiNetType:36
|vpiRange:
\_range: , line:38
|vpiLeftRange:
\_constant: , line:38
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:38
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (clk), line:32, parent:addr_table
|vpiNet:
\_logic_net: (write_addr), line:33, parent:addr_table
|vpiNet:
\_logic_net: (write_en), line:34, parent:addr_table
|vpiNet:
\_logic_net: (read_addr), line:35, parent:addr_table
|vpiNet:
\_logic_net: (read_en), line:36, parent:addr_table
|vpiNet:
\_logic_net: (write_data), line:37, parent:addr_table
|vpiNet:
\_logic_net: (read_data), line:38, parent:addr_table
|vpiArrayNet:
\_array_net: (branch_ram), line:40, parent:addr_table
|vpiName:branch_ram
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_table_banks.branch_table_banks[7].addr_table.branch_ram
|vpiSize:4
|vpiNet:
\_logic_net: , parent:branch_ram
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_table_banks.branch_table_banks[7].addr_table.branch_ram
|vpiNetType:36
|vpiRange:
\_range: , line:40
|vpiLeftRange:
\_constant: , line:40
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:40
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiRange:
\_range: , line:40
|vpiLeftRange:
\_constant: , line:40
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiRightRange:
\_constant: , line:40
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiParameter:
\_parameter: (ALU_UNIT_WB_ID), line:190
|vpiName:ALU_UNIT_WB_ID
|INT:32
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (BRANCH_PREDICTOR_WAYS), line:159
|vpiName:BRANCH_PREDICTOR_WAYS
|INT:9
|vpiParameter:
\_parameter: (BRANCH_TABLE_ENTRIES), line:160
|vpiName:BRANCH_TABLE_ENTRIES
|INT:4
|vpiParameter:
\_parameter: (BRANCH_UNIT_ID), line:195
|vpiName:BRANCH_UNIT_ID
|INT:8
|vpiParameter:
\_parameter: (BUS_ADDR_H), line:107
|vpiName:BUS_ADDR_H
|INT:1
|vpiParameter:
\_parameter: (BUS_ADDR_L), line:106
|vpiName:BUS_ADDR_L
|INT:0
|vpiParameter:
\_parameter: (BUS_BIT_CHECK), line:108
|vpiName:BUS_BIT_CHECK
|INT:1
|vpiParameter:
\_parameter: (BUS_TYPE), line:89
|vpiName:BUS_TYPE
|INT:5
|vpiParameter:
\_parameter: (COUNTER_W), line:42
|vpiName:COUNTER_W
|INT:33
|vpiParameter:
\_parameter: (CPU_ID), line:38
|vpiName:CPU_ID
|INT:0
|vpiParameter:
\_parameter: (C_DATA_WIDTH), line:71
|vpiName:C_DATA_WIDTH
|INT:32
|vpiParameter:
\_parameter: (C_DEPTH), line:71
|vpiName:C_DEPTH
|INT:4
|vpiParameter:
\_parameter: (C_M_AXI_ADDR_WIDTH), line:113
|vpiName:C_M_AXI_ADDR_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_DATA_WIDTH), line:114
|vpiName:C_M_AXI_DATA_WIDTH
|INT:1
|vpiParameter:
\_parameter: (DCACHE_LINES), line:133
|vpiName:DCACHE_LINES
|INT:-2146435073
|vpiParameter:
\_parameter: (DCACHE_LINE_ADDR_W), line:135
|vpiName:DCACHE_LINE_ADDR_W
|INT:1073741824
|vpiParameter:
\_parameter: (DCACHE_LINE_W), line:136
|vpiName:DCACHE_LINE_W
|INT:1342177279
|vpiParameter:
\_parameter: (DCACHE_SUB_LINE_ADDR_W), line:137
|vpiName:DCACHE_SUB_LINE_ADDR_W
|INT:4
|vpiParameter:
\_parameter: (DCACHE_TAG_W), line:138
|vpiName:DCACHE_TAG_W
|INT:1610612736
|vpiParameter:
\_parameter: (DCACHE_WAYS), line:134
|vpiName:DCACHE_WAYS
|INT:4
|vpiParameter:
\_parameter: (DIV_ALGORITHM), line:67
|vpiName:DIV_ALGORITHM
|INT:0
|vpiParameter:
\_parameter: (DIV_UNIT_WB_ID), line:192
|vpiName:DIV_UNIT_WB_ID
|INT:2
|vpiParameter:
\_parameter: (DTLB_DEPTH), line:152
|vpiName:DTLB_DEPTH
|INT:512
|vpiParameter:
\_parameter: (DTLB_WAYS), line:151
|vpiName:DTLB_WAYS
|INT:32
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (ENABLE_M_MODE), line:34
|vpiName:ENABLE_M_MODE
|INT:1
|vpiParameter:
\_parameter: (ENABLE_S_MODE), line:36
|vpiName:ENABLE_S_MODE
|INT:0
|vpiParameter:
\_parameter: (ENABLE_TRACE_INTERFACE), line:172
|vpiName:ENABLE_TRACE_INTERFACE
|INT:2
|vpiParameter:
\_parameter: (FETCH_BUFFER_DEPTH), line:168
|vpiName:FETCH_BUFFER_DEPTH
|INT:512
|vpiParameter:
\_parameter: (FPGA_VENDOR), line:27
|vpiName:FPGA_VENDOR
|STRING:"xilinx"
|vpiParameter:
\_parameter: (GC_UNIT_ID), line:196
|vpiName:GC_UNIT_ID
|INT:4
|vpiParameter:
\_parameter: (ICACHE_LINES), line:121
|vpiName:ICACHE_LINES
|INT:2
|vpiParameter:
\_parameter: (ICACHE_LINE_ADDR_W), line:123
|vpiName:ICACHE_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_LINE_W), line:124
|vpiName:ICACHE_LINE_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_SUB_LINE_ADDR_W), line:125
|vpiName:ICACHE_SUB_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_TAG_W), line:126
|vpiName:ICACHE_TAG_W
|INT:-2147483648
|vpiParameter:
\_parameter: (ICACHE_WAYS), line:122
|vpiName:ICACHE_WAYS
|INT:1
|vpiParameter:
\_parameter: (ITLB_DEPTH), line:146
|vpiName:ITLB_DEPTH
|INT:32
|vpiParameter:
\_parameter: (ITLB_WAYS), line:145
|vpiName:ITLB_WAYS
|INT:4
|vpiParameter:
\_parameter: (L1_CONNECTIONS), line:177
|vpiName:L1_CONNECTIONS
|INT:9
|vpiParameter:
\_parameter: (L1_DCACHE_ID), line:178
|vpiName:L1_DCACHE_ID
|INT:4
|vpiParameter:
\_parameter: (L1_DMMU_ID), line:179
|vpiName:L1_DMMU_ID
|INT:2
|vpiParameter:
\_parameter: (L1_ICACHE_ID), line:180
|vpiName:L1_ICACHE_ID
|INT:19
|vpiParameter:
\_parameter: (L1_IMMU_ID), line:181
|vpiName:L1_IMMU_ID
|INT:0
|vpiParameter:
\_parameter: (LS_UNIT_WB_ID), line:191
|vpiName:LS_UNIT_WB_ID
|INT:1
|vpiParameter:
\_parameter: (MAX_INFLIGHT_COUNT), line:167
|vpiName:MAX_INFLIGHT_COUNT
|INT:19
|vpiParameter:
\_parameter: (MEMORY_ADDR_H), line:103
|vpiName:MEMORY_ADDR_H
|INT:12
|vpiParameter:
\_parameter: (MEMORY_ADDR_L), line:102
|vpiName:MEMORY_ADDR_L
|INT:11
|vpiParameter:
\_parameter: (MEMORY_BIT_CHECK), line:104
|vpiName:MEMORY_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (MUL_UNIT_WB_ID), line:193
|vpiName:MUL_UNIT_WB_ID
|INT:512
|vpiParameter:
\_parameter: (NUM_UNITS), line:188
|vpiName:NUM_UNITS
|INT:2
|vpiParameter:
\_parameter: (NUM_WB_UNITS), line:186
|vpiName:NUM_WB_UNITS
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (RAS_DEPTH), line:161
|vpiName:RAS_DEPTH
|INT:2
|vpiParameter:
\_parameter: (RESET_VEC), line:39
|vpiName:RESET_VEC
|INT:-2147483648
|vpiParameter:
\_parameter: (SCRATCH_ADDR_H), line:99
|vpiName:SCRATCH_ADDR_H
|INT:9
|vpiParameter:
\_parameter: (SCRATCH_ADDR_L), line:98
|vpiName:SCRATCH_ADDR_L
|INT:8
|vpiParameter:
\_parameter: (SCRATCH_BIT_CHECK), line:100
|vpiName:SCRATCH_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (USE_AMO), line:70
|vpiName:USE_AMO
|INT:1
|vpiParameter:
\_parameter: (USE_BRANCH_PREDICTOR), line:158
|vpiName:USE_BRANCH_PREDICTOR
|INT:2
|vpiParameter:
\_parameter: (USE_BUS), line:88
|vpiName:USE_BUS
|INT:4
|vpiParameter:
\_parameter: (USE_DCACHE), line:92
|vpiName:USE_DCACHE
|INT:6
|vpiParameter:
\_parameter: (USE_DIV), line:49
|vpiName:USE_DIV
|INT:1
|vpiParameter:
\_parameter: (USE_DTAG_INVALIDATIONS), line:140
|vpiName:USE_DTAG_INVALIDATIONS
|INT:1879048191
|vpiParameter:
\_parameter: (USE_D_SCRATCH_MEM), line:79
|vpiName:USE_D_SCRATCH_MEM
|INT:3
|vpiParameter:
\_parameter: (USE_ICACHE), line:93
|vpiName:USE_ICACHE
|INT:7
|vpiParameter:
\_parameter: (USE_I_SCRATCH_MEM), line:78
|vpiName:USE_I_SCRATCH_MEM
|INT:2
|vpiParameter:
\_parameter: (USE_MUL), line:48
|vpiName:USE_MUL
|INT:1
|vpiParameter:
\_parameter: (WB_UNITS_WIDTH), line:187
|vpiName:WB_UNITS_WIDTH
|INT:32
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiParameter:
\_parameter: (ALU_UNIT_WB_ID), line:190
|vpiName:ALU_UNIT_WB_ID
|INT:32
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (BRANCH_PREDICTOR_WAYS), line:159
|vpiName:BRANCH_PREDICTOR_WAYS
|INT:9
|vpiParameter:
\_parameter: (BRANCH_TABLE_ENTRIES), line:160
|vpiName:BRANCH_TABLE_ENTRIES
|INT:4
|vpiParameter:
\_parameter: (BRANCH_UNIT_ID), line:195
|vpiName:BRANCH_UNIT_ID
|INT:8
|vpiParameter:
\_parameter: (BUS_ADDR_H), line:107
|vpiName:BUS_ADDR_H
|INT:1
|vpiParameter:
\_parameter: (BUS_ADDR_L), line:106
|vpiName:BUS_ADDR_L
|INT:0
|vpiParameter:
\_parameter: (BUS_BIT_CHECK), line:108
|vpiName:BUS_BIT_CHECK
|INT:1
|vpiParameter:
\_parameter: (BUS_TYPE), line:89
|vpiName:BUS_TYPE
|INT:5
|vpiParameter:
\_parameter: (COUNTER_W), line:42
|vpiName:COUNTER_W
|INT:33
|vpiParameter:
\_parameter: (CPU_ID), line:38
|vpiName:CPU_ID
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_ADDR_WIDTH), line:113
|vpiName:C_M_AXI_ADDR_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_DATA_WIDTH), line:114
|vpiName:C_M_AXI_DATA_WIDTH
|INT:1
|vpiParameter:
\_parameter: (DCACHE_LINES), line:133
|vpiName:DCACHE_LINES
|INT:-2146435073
|vpiParameter:
\_parameter: (DCACHE_LINE_ADDR_W), line:135
|vpiName:DCACHE_LINE_ADDR_W
|INT:1073741824
|vpiParameter:
\_parameter: (DCACHE_LINE_W), line:136
|vpiName:DCACHE_LINE_W
|INT:1342177279
|vpiParameter:
\_parameter: (DCACHE_SUB_LINE_ADDR_W), line:137
|vpiName:DCACHE_SUB_LINE_ADDR_W
|INT:4
|vpiParameter:
\_parameter: (DCACHE_TAG_W), line:138
|vpiName:DCACHE_TAG_W
|INT:1610612736
|vpiParameter:
\_parameter: (DCACHE_WAYS), line:134
|vpiName:DCACHE_WAYS
|INT:4
|vpiParameter:
\_parameter: (DIV_ALGORITHM), line:67
|vpiName:DIV_ALGORITHM
|INT:0
|vpiParameter:
\_parameter: (DIV_UNIT_WB_ID), line:192
|vpiName:DIV_UNIT_WB_ID
|INT:2
|vpiParameter:
\_parameter: (DTLB_DEPTH), line:152
|vpiName:DTLB_DEPTH
|INT:512
|vpiParameter:
\_parameter: (DTLB_WAYS), line:151
|vpiName:DTLB_WAYS
|INT:32
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (ENABLE_M_MODE), line:34
|vpiName:ENABLE_M_MODE
|INT:1
|vpiParameter:
\_parameter: (ENABLE_S_MODE), line:36
|vpiName:ENABLE_S_MODE
|INT:0
|vpiParameter:
\_parameter: (ENABLE_TRACE_INTERFACE), line:172
|vpiName:ENABLE_TRACE_INTERFACE
|INT:2
|vpiParameter:
\_parameter: (FETCH_BUFFER_DEPTH), line:168
|vpiName:FETCH_BUFFER_DEPTH
|INT:512
|vpiParameter:
\_parameter: (FPGA_VENDOR), line:27
|vpiName:FPGA_VENDOR
|STRING:"xilinx"
|vpiParameter:
\_parameter: (GC_UNIT_ID), line:196
|vpiName:GC_UNIT_ID
|INT:4
|vpiParameter:
\_parameter: (ICACHE_LINES), line:121
|vpiName:ICACHE_LINES
|INT:2
|vpiParameter:
\_parameter: (ICACHE_LINE_ADDR_W), line:123
|vpiName:ICACHE_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_LINE_W), line:124
|vpiName:ICACHE_LINE_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_SUB_LINE_ADDR_W), line:125
|vpiName:ICACHE_SUB_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_TAG_W), line:126
|vpiName:ICACHE_TAG_W
|INT:-2147483648
|vpiParameter:
\_parameter: (ICACHE_WAYS), line:122
|vpiName:ICACHE_WAYS
|INT:1
|vpiParameter:
\_parameter: (ITLB_DEPTH), line:146
|vpiName:ITLB_DEPTH
|INT:32
|vpiParameter:
\_parameter: (ITLB_WAYS), line:145
|vpiName:ITLB_WAYS
|INT:4
|vpiParameter:
\_parameter: (L1_CONNECTIONS), line:177
|vpiName:L1_CONNECTIONS
|INT:9
|vpiParameter:
\_parameter: (L1_DCACHE_ID), line:178
|vpiName:L1_DCACHE_ID
|INT:4
|vpiParameter:
\_parameter: (L1_DMMU_ID), line:179
|vpiName:L1_DMMU_ID
|INT:2
|vpiParameter:
\_parameter: (L1_ICACHE_ID), line:180
|vpiName:L1_ICACHE_ID
|INT:19
|vpiParameter:
\_parameter: (L1_IMMU_ID), line:181
|vpiName:L1_IMMU_ID
|INT:0
|vpiParameter:
\_parameter: (LS_UNIT_WB_ID), line:191
|vpiName:LS_UNIT_WB_ID
|INT:1
|vpiParameter:
\_parameter: (MAX_INFLIGHT_COUNT), line:167
|vpiName:MAX_INFLIGHT_COUNT
|INT:19
|vpiParameter:
\_parameter: (MEMORY_ADDR_H), line:103
|vpiName:MEMORY_ADDR_H
|INT:12
|vpiParameter:
\_parameter: (MEMORY_ADDR_L), line:102
|vpiName:MEMORY_ADDR_L
|INT:11
|vpiParameter:
\_parameter: (MEMORY_BIT_CHECK), line:104
|vpiName:MEMORY_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (MUL_UNIT_WB_ID), line:193
|vpiName:MUL_UNIT_WB_ID
|INT:512
|vpiParameter:
\_parameter: (NUM_UNITS), line:188
|vpiName:NUM_UNITS
|INT:2
|vpiParameter:
\_parameter: (NUM_WB_UNITS), line:186
|vpiName:NUM_WB_UNITS
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (RAS_DEPTH), line:161
|vpiName:RAS_DEPTH
|INT:2
|vpiParameter:
\_parameter: (RESET_VEC), line:39
|vpiName:RESET_VEC
|INT:-2147483648
|vpiParameter:
\_parameter: (SCRATCH_ADDR_H), line:99
|vpiName:SCRATCH_ADDR_H
|INT:9
|vpiParameter:
\_parameter: (SCRATCH_ADDR_L), line:98
|vpiName:SCRATCH_ADDR_L
|INT:8
|vpiParameter:
\_parameter: (SCRATCH_BIT_CHECK), line:100
|vpiName:SCRATCH_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (USE_AMO), line:70
|vpiName:USE_AMO
|INT:1
|vpiParameter:
\_parameter: (USE_BRANCH_PREDICTOR), line:158
|vpiName:USE_BRANCH_PREDICTOR
|INT:2
|vpiParameter:
\_parameter: (USE_BUS), line:88
|vpiName:USE_BUS
|INT:4
|vpiParameter:
\_parameter: (USE_DCACHE), line:92
|vpiName:USE_DCACHE
|INT:6
|vpiParameter:
\_parameter: (USE_DIV), line:49
|vpiName:USE_DIV
|INT:1
|vpiParameter:
\_parameter: (USE_DTAG_INVALIDATIONS), line:140
|vpiName:USE_DTAG_INVALIDATIONS
|INT:1879048191
|vpiParameter:
\_parameter: (USE_D_SCRATCH_MEM), line:79
|vpiName:USE_D_SCRATCH_MEM
|INT:3
|vpiParameter:
\_parameter: (USE_ICACHE), line:93
|vpiName:USE_ICACHE
|INT:7
|vpiParameter:
\_parameter: (USE_I_SCRATCH_MEM), line:78
|vpiName:USE_I_SCRATCH_MEM
|INT:2
|vpiParameter:
\_parameter: (USE_MUL), line:48
|vpiName:USE_MUL
|INT:1
|vpiParameter:
\_parameter: (WB_UNITS_WIDTH), line:187
|vpiName:WB_UNITS_WIDTH
|INT:32
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiParameter:
\_parameter: (i), line:70
|vpiName:i
|INT:7
|vpiGenScopeArray:
\_gen_scope_array: (branch_table_banks[8]), line:70
|vpiName:branch_table_banks[8]
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_table_banks.branch_table_banks[8]
|vpiGenScope:
\_gen_scope: , parent:branch_table_banks[8]
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_table_banks.branch_table_banks[8]
|vpiModule:
\_module: work@branch_predictor_ram (addr_table), file:third_party/cores/taiga/core/branch_predictor.sv, line:71
|vpiDefName:work@branch_predictor_ram
|vpiName:addr_table
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_table_banks.branch_table_banks[8].addr_table
|vpiPort:
\_port: (clk), line:32, parent:addr_table
|vpiName:clk
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (clk), line:72
|vpiName:clk
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (clk), line:32, parent:addr_table
|vpiName:clk
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_table_banks.branch_table_banks[8].addr_table.clk
|vpiNetType:36
|vpiPort:
\_port: (write_addr), line:33, parent:addr_table
|vpiName:write_addr
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (write_addr), line:72
|vpiName:write_addr
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (write_addr), line:33, parent:addr_table
|vpiName:write_addr
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_table_banks.branch_table_banks[8].addr_table.write_addr
|vpiNetType:36
|vpiRange:
\_range: , line:33
|vpiLeftRange:
\_constant: , line:33
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:33
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiPort:
\_port: (write_en), line:34, parent:addr_table
|vpiName:write_en
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (write_en), line:72
|vpiName:write_en
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (write_en), line:34, parent:addr_table
|vpiName:write_en
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_table_banks.branch_table_banks[8].addr_table.write_en
|vpiNetType:36
|vpiPort:
\_port: (read_addr), line:35, parent:addr_table
|vpiName:read_addr
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (read_addr), line:72
|vpiName:read_addr
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (read_addr), line:35, parent:addr_table
|vpiName:read_addr
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_table_banks.branch_table_banks[8].addr_table.read_addr
|vpiNetType:36
|vpiRange:
\_range: , line:35
|vpiLeftRange:
\_constant: , line:35
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:35
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiPort:
\_port: (read_en), line:36, parent:addr_table
|vpiName:read_en
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (read_en), line:72
|vpiName:read_en
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (read_en), line:36, parent:addr_table
|vpiName:read_en
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_table_banks.branch_table_banks[8].addr_table.read_en
|vpiNetType:36
|vpiPort:
\_port: (write_data), line:37, parent:addr_table
|vpiName:write_data
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (write_data), line:72
|vpiName:write_data
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (write_data), line:37, parent:addr_table
|vpiName:write_data
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_table_banks.branch_table_banks[8].addr_table.write_data
|vpiNetType:36
|vpiRange:
\_range: , line:37
|vpiLeftRange:
\_constant: , line:37
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:37
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiPort:
\_port: (read_data), line:38, parent:addr_table
|vpiName:read_data
|vpiDirection:2
|vpiHighConn:
\_ref_obj: (read_data), line:72
|vpiName:read_data
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (read_data), line:38, parent:addr_table
|vpiName:read_data
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_table_banks.branch_table_banks[8].addr_table.read_data
|vpiNetType:36
|vpiRange:
\_range: , line:38
|vpiLeftRange:
\_constant: , line:38
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:38
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (clk), line:32, parent:addr_table
|vpiNet:
\_logic_net: (write_addr), line:33, parent:addr_table
|vpiNet:
\_logic_net: (write_en), line:34, parent:addr_table
|vpiNet:
\_logic_net: (read_addr), line:35, parent:addr_table
|vpiNet:
\_logic_net: (read_en), line:36, parent:addr_table
|vpiNet:
\_logic_net: (write_data), line:37, parent:addr_table
|vpiNet:
\_logic_net: (read_data), line:38, parent:addr_table
|vpiArrayNet:
\_array_net: (branch_ram), line:40, parent:addr_table
|vpiName:branch_ram
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_table_banks.branch_table_banks[8].addr_table.branch_ram
|vpiSize:4
|vpiNet:
\_logic_net: , parent:branch_ram
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_table_banks.branch_table_banks[8].addr_table.branch_ram
|vpiNetType:36
|vpiRange:
\_range: , line:40
|vpiLeftRange:
\_constant: , line:40
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:40
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiRange:
\_range: , line:40
|vpiLeftRange:
\_constant: , line:40
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiRightRange:
\_constant: , line:40
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiParameter:
\_parameter: (ALU_UNIT_WB_ID), line:190
|vpiName:ALU_UNIT_WB_ID
|INT:32
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (BRANCH_PREDICTOR_WAYS), line:159
|vpiName:BRANCH_PREDICTOR_WAYS
|INT:9
|vpiParameter:
\_parameter: (BRANCH_TABLE_ENTRIES), line:160
|vpiName:BRANCH_TABLE_ENTRIES
|INT:4
|vpiParameter:
\_parameter: (BRANCH_UNIT_ID), line:195
|vpiName:BRANCH_UNIT_ID
|INT:8
|vpiParameter:
\_parameter: (BUS_ADDR_H), line:107
|vpiName:BUS_ADDR_H
|INT:1
|vpiParameter:
\_parameter: (BUS_ADDR_L), line:106
|vpiName:BUS_ADDR_L
|INT:0
|vpiParameter:
\_parameter: (BUS_BIT_CHECK), line:108
|vpiName:BUS_BIT_CHECK
|INT:1
|vpiParameter:
\_parameter: (BUS_TYPE), line:89
|vpiName:BUS_TYPE
|INT:5
|vpiParameter:
\_parameter: (COUNTER_W), line:42
|vpiName:COUNTER_W
|INT:33
|vpiParameter:
\_parameter: (CPU_ID), line:38
|vpiName:CPU_ID
|INT:0
|vpiParameter:
\_parameter: (C_DATA_WIDTH), line:71
|vpiName:C_DATA_WIDTH
|INT:32
|vpiParameter:
\_parameter: (C_DEPTH), line:71
|vpiName:C_DEPTH
|INT:4
|vpiParameter:
\_parameter: (C_M_AXI_ADDR_WIDTH), line:113
|vpiName:C_M_AXI_ADDR_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_DATA_WIDTH), line:114
|vpiName:C_M_AXI_DATA_WIDTH
|INT:1
|vpiParameter:
\_parameter: (DCACHE_LINES), line:133
|vpiName:DCACHE_LINES
|INT:-2146435073
|vpiParameter:
\_parameter: (DCACHE_LINE_ADDR_W), line:135
|vpiName:DCACHE_LINE_ADDR_W
|INT:1073741824
|vpiParameter:
\_parameter: (DCACHE_LINE_W), line:136
|vpiName:DCACHE_LINE_W
|INT:1342177279
|vpiParameter:
\_parameter: (DCACHE_SUB_LINE_ADDR_W), line:137
|vpiName:DCACHE_SUB_LINE_ADDR_W
|INT:4
|vpiParameter:
\_parameter: (DCACHE_TAG_W), line:138
|vpiName:DCACHE_TAG_W
|INT:1610612736
|vpiParameter:
\_parameter: (DCACHE_WAYS), line:134
|vpiName:DCACHE_WAYS
|INT:4
|vpiParameter:
\_parameter: (DIV_ALGORITHM), line:67
|vpiName:DIV_ALGORITHM
|INT:0
|vpiParameter:
\_parameter: (DIV_UNIT_WB_ID), line:192
|vpiName:DIV_UNIT_WB_ID
|INT:2
|vpiParameter:
\_parameter: (DTLB_DEPTH), line:152
|vpiName:DTLB_DEPTH
|INT:512
|vpiParameter:
\_parameter: (DTLB_WAYS), line:151
|vpiName:DTLB_WAYS
|INT:32
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (ENABLE_M_MODE), line:34
|vpiName:ENABLE_M_MODE
|INT:1
|vpiParameter:
\_parameter: (ENABLE_S_MODE), line:36
|vpiName:ENABLE_S_MODE
|INT:0
|vpiParameter:
\_parameter: (ENABLE_TRACE_INTERFACE), line:172
|vpiName:ENABLE_TRACE_INTERFACE
|INT:2
|vpiParameter:
\_parameter: (FETCH_BUFFER_DEPTH), line:168
|vpiName:FETCH_BUFFER_DEPTH
|INT:512
|vpiParameter:
\_parameter: (FPGA_VENDOR), line:27
|vpiName:FPGA_VENDOR
|STRING:"xilinx"
|vpiParameter:
\_parameter: (GC_UNIT_ID), line:196
|vpiName:GC_UNIT_ID
|INT:4
|vpiParameter:
\_parameter: (ICACHE_LINES), line:121
|vpiName:ICACHE_LINES
|INT:2
|vpiParameter:
\_parameter: (ICACHE_LINE_ADDR_W), line:123
|vpiName:ICACHE_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_LINE_W), line:124
|vpiName:ICACHE_LINE_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_SUB_LINE_ADDR_W), line:125
|vpiName:ICACHE_SUB_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_TAG_W), line:126
|vpiName:ICACHE_TAG_W
|INT:-2147483648
|vpiParameter:
\_parameter: (ICACHE_WAYS), line:122
|vpiName:ICACHE_WAYS
|INT:1
|vpiParameter:
\_parameter: (ITLB_DEPTH), line:146
|vpiName:ITLB_DEPTH
|INT:32
|vpiParameter:
\_parameter: (ITLB_WAYS), line:145
|vpiName:ITLB_WAYS
|INT:4
|vpiParameter:
\_parameter: (L1_CONNECTIONS), line:177
|vpiName:L1_CONNECTIONS
|INT:9
|vpiParameter:
\_parameter: (L1_DCACHE_ID), line:178
|vpiName:L1_DCACHE_ID
|INT:4
|vpiParameter:
\_parameter: (L1_DMMU_ID), line:179
|vpiName:L1_DMMU_ID
|INT:2
|vpiParameter:
\_parameter: (L1_ICACHE_ID), line:180
|vpiName:L1_ICACHE_ID
|INT:19
|vpiParameter:
\_parameter: (L1_IMMU_ID), line:181
|vpiName:L1_IMMU_ID
|INT:0
|vpiParameter:
\_parameter: (LS_UNIT_WB_ID), line:191
|vpiName:LS_UNIT_WB_ID
|INT:1
|vpiParameter:
\_parameter: (MAX_INFLIGHT_COUNT), line:167
|vpiName:MAX_INFLIGHT_COUNT
|INT:19
|vpiParameter:
\_parameter: (MEMORY_ADDR_H), line:103
|vpiName:MEMORY_ADDR_H
|INT:12
|vpiParameter:
\_parameter: (MEMORY_ADDR_L), line:102
|vpiName:MEMORY_ADDR_L
|INT:11
|vpiParameter:
\_parameter: (MEMORY_BIT_CHECK), line:104
|vpiName:MEMORY_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (MUL_UNIT_WB_ID), line:193
|vpiName:MUL_UNIT_WB_ID
|INT:512
|vpiParameter:
\_parameter: (NUM_UNITS), line:188
|vpiName:NUM_UNITS
|INT:2
|vpiParameter:
\_parameter: (NUM_WB_UNITS), line:186
|vpiName:NUM_WB_UNITS
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (RAS_DEPTH), line:161
|vpiName:RAS_DEPTH
|INT:2
|vpiParameter:
\_parameter: (RESET_VEC), line:39
|vpiName:RESET_VEC
|INT:-2147483648
|vpiParameter:
\_parameter: (SCRATCH_ADDR_H), line:99
|vpiName:SCRATCH_ADDR_H
|INT:9
|vpiParameter:
\_parameter: (SCRATCH_ADDR_L), line:98
|vpiName:SCRATCH_ADDR_L
|INT:8
|vpiParameter:
\_parameter: (SCRATCH_BIT_CHECK), line:100
|vpiName:SCRATCH_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (USE_AMO), line:70
|vpiName:USE_AMO
|INT:1
|vpiParameter:
\_parameter: (USE_BRANCH_PREDICTOR), line:158
|vpiName:USE_BRANCH_PREDICTOR
|INT:2
|vpiParameter:
\_parameter: (USE_BUS), line:88
|vpiName:USE_BUS
|INT:4
|vpiParameter:
\_parameter: (USE_DCACHE), line:92
|vpiName:USE_DCACHE
|INT:6
|vpiParameter:
\_parameter: (USE_DIV), line:49
|vpiName:USE_DIV
|INT:1
|vpiParameter:
\_parameter: (USE_DTAG_INVALIDATIONS), line:140
|vpiName:USE_DTAG_INVALIDATIONS
|INT:1879048191
|vpiParameter:
\_parameter: (USE_D_SCRATCH_MEM), line:79
|vpiName:USE_D_SCRATCH_MEM
|INT:3
|vpiParameter:
\_parameter: (USE_ICACHE), line:93
|vpiName:USE_ICACHE
|INT:7
|vpiParameter:
\_parameter: (USE_I_SCRATCH_MEM), line:78
|vpiName:USE_I_SCRATCH_MEM
|INT:2
|vpiParameter:
\_parameter: (USE_MUL), line:48
|vpiName:USE_MUL
|INT:1
|vpiParameter:
\_parameter: (WB_UNITS_WIDTH), line:187
|vpiName:WB_UNITS_WIDTH
|INT:32
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiParameter:
\_parameter: (ALU_UNIT_WB_ID), line:190
|vpiName:ALU_UNIT_WB_ID
|INT:32
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (BRANCH_PREDICTOR_WAYS), line:159
|vpiName:BRANCH_PREDICTOR_WAYS
|INT:9
|vpiParameter:
\_parameter: (BRANCH_TABLE_ENTRIES), line:160
|vpiName:BRANCH_TABLE_ENTRIES
|INT:4
|vpiParameter:
\_parameter: (BRANCH_UNIT_ID), line:195
|vpiName:BRANCH_UNIT_ID
|INT:8
|vpiParameter:
\_parameter: (BUS_ADDR_H), line:107
|vpiName:BUS_ADDR_H
|INT:1
|vpiParameter:
\_parameter: (BUS_ADDR_L), line:106
|vpiName:BUS_ADDR_L
|INT:0
|vpiParameter:
\_parameter: (BUS_BIT_CHECK), line:108
|vpiName:BUS_BIT_CHECK
|INT:1
|vpiParameter:
\_parameter: (BUS_TYPE), line:89
|vpiName:BUS_TYPE
|INT:5
|vpiParameter:
\_parameter: (COUNTER_W), line:42
|vpiName:COUNTER_W
|INT:33
|vpiParameter:
\_parameter: (CPU_ID), line:38
|vpiName:CPU_ID
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_ADDR_WIDTH), line:113
|vpiName:C_M_AXI_ADDR_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_DATA_WIDTH), line:114
|vpiName:C_M_AXI_DATA_WIDTH
|INT:1
|vpiParameter:
\_parameter: (DCACHE_LINES), line:133
|vpiName:DCACHE_LINES
|INT:-2146435073
|vpiParameter:
\_parameter: (DCACHE_LINE_ADDR_W), line:135
|vpiName:DCACHE_LINE_ADDR_W
|INT:1073741824
|vpiParameter:
\_parameter: (DCACHE_LINE_W), line:136
|vpiName:DCACHE_LINE_W
|INT:1342177279
|vpiParameter:
\_parameter: (DCACHE_SUB_LINE_ADDR_W), line:137
|vpiName:DCACHE_SUB_LINE_ADDR_W
|INT:4
|vpiParameter:
\_parameter: (DCACHE_TAG_W), line:138
|vpiName:DCACHE_TAG_W
|INT:1610612736
|vpiParameter:
\_parameter: (DCACHE_WAYS), line:134
|vpiName:DCACHE_WAYS
|INT:4
|vpiParameter:
\_parameter: (DIV_ALGORITHM), line:67
|vpiName:DIV_ALGORITHM
|INT:0
|vpiParameter:
\_parameter: (DIV_UNIT_WB_ID), line:192
|vpiName:DIV_UNIT_WB_ID
|INT:2
|vpiParameter:
\_parameter: (DTLB_DEPTH), line:152
|vpiName:DTLB_DEPTH
|INT:512
|vpiParameter:
\_parameter: (DTLB_WAYS), line:151
|vpiName:DTLB_WAYS
|INT:32
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (ENABLE_M_MODE), line:34
|vpiName:ENABLE_M_MODE
|INT:1
|vpiParameter:
\_parameter: (ENABLE_S_MODE), line:36
|vpiName:ENABLE_S_MODE
|INT:0
|vpiParameter:
\_parameter: (ENABLE_TRACE_INTERFACE), line:172
|vpiName:ENABLE_TRACE_INTERFACE
|INT:2
|vpiParameter:
\_parameter: (FETCH_BUFFER_DEPTH), line:168
|vpiName:FETCH_BUFFER_DEPTH
|INT:512
|vpiParameter:
\_parameter: (FPGA_VENDOR), line:27
|vpiName:FPGA_VENDOR
|STRING:"xilinx"
|vpiParameter:
\_parameter: (GC_UNIT_ID), line:196
|vpiName:GC_UNIT_ID
|INT:4
|vpiParameter:
\_parameter: (ICACHE_LINES), line:121
|vpiName:ICACHE_LINES
|INT:2
|vpiParameter:
\_parameter: (ICACHE_LINE_ADDR_W), line:123
|vpiName:ICACHE_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_LINE_W), line:124
|vpiName:ICACHE_LINE_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_SUB_LINE_ADDR_W), line:125
|vpiName:ICACHE_SUB_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_TAG_W), line:126
|vpiName:ICACHE_TAG_W
|INT:-2147483648
|vpiParameter:
\_parameter: (ICACHE_WAYS), line:122
|vpiName:ICACHE_WAYS
|INT:1
|vpiParameter:
\_parameter: (ITLB_DEPTH), line:146
|vpiName:ITLB_DEPTH
|INT:32
|vpiParameter:
\_parameter: (ITLB_WAYS), line:145
|vpiName:ITLB_WAYS
|INT:4
|vpiParameter:
\_parameter: (L1_CONNECTIONS), line:177
|vpiName:L1_CONNECTIONS
|INT:9
|vpiParameter:
\_parameter: (L1_DCACHE_ID), line:178
|vpiName:L1_DCACHE_ID
|INT:4
|vpiParameter:
\_parameter: (L1_DMMU_ID), line:179
|vpiName:L1_DMMU_ID
|INT:2
|vpiParameter:
\_parameter: (L1_ICACHE_ID), line:180
|vpiName:L1_ICACHE_ID
|INT:19
|vpiParameter:
\_parameter: (L1_IMMU_ID), line:181
|vpiName:L1_IMMU_ID
|INT:0
|vpiParameter:
\_parameter: (LS_UNIT_WB_ID), line:191
|vpiName:LS_UNIT_WB_ID
|INT:1
|vpiParameter:
\_parameter: (MAX_INFLIGHT_COUNT), line:167
|vpiName:MAX_INFLIGHT_COUNT
|INT:19
|vpiParameter:
\_parameter: (MEMORY_ADDR_H), line:103
|vpiName:MEMORY_ADDR_H
|INT:12
|vpiParameter:
\_parameter: (MEMORY_ADDR_L), line:102
|vpiName:MEMORY_ADDR_L
|INT:11
|vpiParameter:
\_parameter: (MEMORY_BIT_CHECK), line:104
|vpiName:MEMORY_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (MUL_UNIT_WB_ID), line:193
|vpiName:MUL_UNIT_WB_ID
|INT:512
|vpiParameter:
\_parameter: (NUM_UNITS), line:188
|vpiName:NUM_UNITS
|INT:2
|vpiParameter:
\_parameter: (NUM_WB_UNITS), line:186
|vpiName:NUM_WB_UNITS
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (RAS_DEPTH), line:161
|vpiName:RAS_DEPTH
|INT:2
|vpiParameter:
\_parameter: (RESET_VEC), line:39
|vpiName:RESET_VEC
|INT:-2147483648
|vpiParameter:
\_parameter: (SCRATCH_ADDR_H), line:99
|vpiName:SCRATCH_ADDR_H
|INT:9
|vpiParameter:
\_parameter: (SCRATCH_ADDR_L), line:98
|vpiName:SCRATCH_ADDR_L
|INT:8
|vpiParameter:
\_parameter: (SCRATCH_BIT_CHECK), line:100
|vpiName:SCRATCH_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (USE_AMO), line:70
|vpiName:USE_AMO
|INT:1
|vpiParameter:
\_parameter: (USE_BRANCH_PREDICTOR), line:158
|vpiName:USE_BRANCH_PREDICTOR
|INT:2
|vpiParameter:
\_parameter: (USE_BUS), line:88
|vpiName:USE_BUS
|INT:4
|vpiParameter:
\_parameter: (USE_DCACHE), line:92
|vpiName:USE_DCACHE
|INT:6
|vpiParameter:
\_parameter: (USE_DIV), line:49
|vpiName:USE_DIV
|INT:1
|vpiParameter:
\_parameter: (USE_DTAG_INVALIDATIONS), line:140
|vpiName:USE_DTAG_INVALIDATIONS
|INT:1879048191
|vpiParameter:
\_parameter: (USE_D_SCRATCH_MEM), line:79
|vpiName:USE_D_SCRATCH_MEM
|INT:3
|vpiParameter:
\_parameter: (USE_ICACHE), line:93
|vpiName:USE_ICACHE
|INT:7
|vpiParameter:
\_parameter: (USE_I_SCRATCH_MEM), line:78
|vpiName:USE_I_SCRATCH_MEM
|INT:2
|vpiParameter:
\_parameter: (USE_MUL), line:48
|vpiName:USE_MUL
|INT:1
|vpiParameter:
\_parameter: (WB_UNITS_WIDTH), line:187
|vpiName:WB_UNITS_WIDTH
|INT:32
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiParameter:
\_parameter: (i), line:70
|vpiName:i
|INT:8
|vpiParameter:
\_parameter: (ALU_UNIT_WB_ID), line:190
|vpiName:ALU_UNIT_WB_ID
|INT:32
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (BRANCH_PREDICTOR_WAYS), line:159
|vpiName:BRANCH_PREDICTOR_WAYS
|INT:9
|vpiParameter:
\_parameter: (BRANCH_TABLE_ENTRIES), line:160
|vpiName:BRANCH_TABLE_ENTRIES
|INT:4
|vpiParameter:
\_parameter: (BRANCH_UNIT_ID), line:195
|vpiName:BRANCH_UNIT_ID
|INT:8
|vpiParameter:
\_parameter: (BUS_ADDR_H), line:107
|vpiName:BUS_ADDR_H
|INT:1
|vpiParameter:
\_parameter: (BUS_ADDR_L), line:106
|vpiName:BUS_ADDR_L
|INT:0
|vpiParameter:
\_parameter: (BUS_BIT_CHECK), line:108
|vpiName:BUS_BIT_CHECK
|INT:1
|vpiParameter:
\_parameter: (BUS_TYPE), line:89
|vpiName:BUS_TYPE
|INT:5
|vpiParameter:
\_parameter: (COUNTER_W), line:42
|vpiName:COUNTER_W
|INT:33
|vpiParameter:
\_parameter: (CPU_ID), line:38
|vpiName:CPU_ID
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_ADDR_WIDTH), line:113
|vpiName:C_M_AXI_ADDR_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_DATA_WIDTH), line:114
|vpiName:C_M_AXI_DATA_WIDTH
|INT:1
|vpiParameter:
\_parameter: (DCACHE_LINES), line:133
|vpiName:DCACHE_LINES
|INT:-2146435073
|vpiParameter:
\_parameter: (DCACHE_LINE_ADDR_W), line:135
|vpiName:DCACHE_LINE_ADDR_W
|INT:1073741824
|vpiParameter:
\_parameter: (DCACHE_LINE_W), line:136
|vpiName:DCACHE_LINE_W
|INT:1342177279
|vpiParameter:
\_parameter: (DCACHE_SUB_LINE_ADDR_W), line:137
|vpiName:DCACHE_SUB_LINE_ADDR_W
|INT:4
|vpiParameter:
\_parameter: (DCACHE_TAG_W), line:138
|vpiName:DCACHE_TAG_W
|INT:1610612736
|vpiParameter:
\_parameter: (DCACHE_WAYS), line:134
|vpiName:DCACHE_WAYS
|INT:4
|vpiParameter:
\_parameter: (DIV_ALGORITHM), line:67
|vpiName:DIV_ALGORITHM
|INT:0
|vpiParameter:
\_parameter: (DIV_UNIT_WB_ID), line:192
|vpiName:DIV_UNIT_WB_ID
|INT:2
|vpiParameter:
\_parameter: (DTLB_DEPTH), line:152
|vpiName:DTLB_DEPTH
|INT:512
|vpiParameter:
\_parameter: (DTLB_WAYS), line:151
|vpiName:DTLB_WAYS
|INT:32
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (ENABLE_M_MODE), line:34
|vpiName:ENABLE_M_MODE
|INT:1
|vpiParameter:
\_parameter: (ENABLE_S_MODE), line:36
|vpiName:ENABLE_S_MODE
|INT:0
|vpiParameter:
\_parameter: (ENABLE_TRACE_INTERFACE), line:172
|vpiName:ENABLE_TRACE_INTERFACE
|INT:2
|vpiParameter:
\_parameter: (FETCH_BUFFER_DEPTH), line:168
|vpiName:FETCH_BUFFER_DEPTH
|INT:512
|vpiParameter:
\_parameter: (FPGA_VENDOR), line:27
|vpiName:FPGA_VENDOR
|STRING:"xilinx"
|vpiParameter:
\_parameter: (GC_UNIT_ID), line:196
|vpiName:GC_UNIT_ID
|INT:4
|vpiParameter:
\_parameter: (ICACHE_LINES), line:121
|vpiName:ICACHE_LINES
|INT:2
|vpiParameter:
\_parameter: (ICACHE_LINE_ADDR_W), line:123
|vpiName:ICACHE_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_LINE_W), line:124
|vpiName:ICACHE_LINE_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_SUB_LINE_ADDR_W), line:125
|vpiName:ICACHE_SUB_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_TAG_W), line:126
|vpiName:ICACHE_TAG_W
|INT:-2147483648
|vpiParameter:
\_parameter: (ICACHE_WAYS), line:122
|vpiName:ICACHE_WAYS
|INT:1
|vpiParameter:
\_parameter: (ITLB_DEPTH), line:146
|vpiName:ITLB_DEPTH
|INT:32
|vpiParameter:
\_parameter: (ITLB_WAYS), line:145
|vpiName:ITLB_WAYS
|INT:4
|vpiParameter:
\_parameter: (L1_CONNECTIONS), line:177
|vpiName:L1_CONNECTIONS
|INT:9
|vpiParameter:
\_parameter: (L1_DCACHE_ID), line:178
|vpiName:L1_DCACHE_ID
|INT:4
|vpiParameter:
\_parameter: (L1_DMMU_ID), line:179
|vpiName:L1_DMMU_ID
|INT:2
|vpiParameter:
\_parameter: (L1_ICACHE_ID), line:180
|vpiName:L1_ICACHE_ID
|INT:19
|vpiParameter:
\_parameter: (L1_IMMU_ID), line:181
|vpiName:L1_IMMU_ID
|INT:0
|vpiParameter:
\_parameter: (LS_UNIT_WB_ID), line:191
|vpiName:LS_UNIT_WB_ID
|INT:1
|vpiParameter:
\_parameter: (MAX_INFLIGHT_COUNT), line:167
|vpiName:MAX_INFLIGHT_COUNT
|INT:19
|vpiParameter:
\_parameter: (MEMORY_ADDR_H), line:103
|vpiName:MEMORY_ADDR_H
|INT:12
|vpiParameter:
\_parameter: (MEMORY_ADDR_L), line:102
|vpiName:MEMORY_ADDR_L
|INT:11
|vpiParameter:
\_parameter: (MEMORY_BIT_CHECK), line:104
|vpiName:MEMORY_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (MUL_UNIT_WB_ID), line:193
|vpiName:MUL_UNIT_WB_ID
|INT:512
|vpiParameter:
\_parameter: (NUM_UNITS), line:188
|vpiName:NUM_UNITS
|INT:2
|vpiParameter:
\_parameter: (NUM_WB_UNITS), line:186
|vpiName:NUM_WB_UNITS
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (RAS_DEPTH), line:161
|vpiName:RAS_DEPTH
|INT:2
|vpiParameter:
\_parameter: (RESET_VEC), line:39
|vpiName:RESET_VEC
|INT:-2147483648
|vpiParameter:
\_parameter: (SCRATCH_ADDR_H), line:99
|vpiName:SCRATCH_ADDR_H
|INT:9
|vpiParameter:
\_parameter: (SCRATCH_ADDR_L), line:98
|vpiName:SCRATCH_ADDR_L
|INT:8
|vpiParameter:
\_parameter: (SCRATCH_BIT_CHECK), line:100
|vpiName:SCRATCH_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (USE_AMO), line:70
|vpiName:USE_AMO
|INT:1
|vpiParameter:
\_parameter: (USE_BRANCH_PREDICTOR), line:158
|vpiName:USE_BRANCH_PREDICTOR
|INT:2
|vpiParameter:
\_parameter: (USE_BUS), line:88
|vpiName:USE_BUS
|INT:4
|vpiParameter:
\_parameter: (USE_DCACHE), line:92
|vpiName:USE_DCACHE
|INT:6
|vpiParameter:
\_parameter: (USE_DIV), line:49
|vpiName:USE_DIV
|INT:1
|vpiParameter:
\_parameter: (USE_DTAG_INVALIDATIONS), line:140
|vpiName:USE_DTAG_INVALIDATIONS
|INT:1879048191
|vpiParameter:
\_parameter: (USE_D_SCRATCH_MEM), line:79
|vpiName:USE_D_SCRATCH_MEM
|INT:3
|vpiParameter:
\_parameter: (USE_ICACHE), line:93
|vpiName:USE_ICACHE
|INT:7
|vpiParameter:
\_parameter: (USE_I_SCRATCH_MEM), line:78
|vpiName:USE_I_SCRATCH_MEM
|INT:2
|vpiParameter:
\_parameter: (USE_MUL), line:48
|vpiName:USE_MUL
|INT:1
|vpiParameter:
\_parameter: (WB_UNITS_WIDTH), line:187
|vpiName:WB_UNITS_WIDTH
|INT:32
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiGenScopeArray:
\_gen_scope_array: (branch_hit_detection), line:78, parent:bp_block
|vpiName:branch_hit_detection
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_hit_detection
|vpiGenScope:
\_gen_scope: , parent:branch_hit_detection
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_hit_detection
|vpiGenScopeArray:
\_gen_scope_array: (branch_hit_detection[0]), line:79
|vpiName:branch_hit_detection[0]
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_hit_detection.branch_hit_detection[0]
|vpiGenScope:
\_gen_scope: , parent:branch_hit_detection[0]
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_hit_detection.branch_hit_detection[0]
|vpiContAssign:
\_cont_assign: , line:80
|vpiRhs:
\_operation: , line:80
|vpiOpType:14
|vpiOperand:
\_operation: , line:80
|vpiOpType:33
|vpiOperand:
\_bit_select: (if_entry.valid), line:80
|vpiName:if_entry.valid
|vpiIndex:
\_ref_obj: (i), line:80
|vpiName:i
|vpiOperand:
\_bit_select: (if_entry.tag), line:80
|vpiName:if_entry.tag
|vpiIndex:
\_ref_obj: (i), line:80
|vpiName:i
|vpiOperand:
\_operation: , line:80
|vpiOpType:33
|vpiOperand:
\_constant: , line:80
|vpiConstType:3
|vpiDecompile:'b1
|vpiSize:1
|BIN:1
|vpiOperand:
\_ref_obj: (bp.if_pc), line:80
|vpiName:bp.if_pc
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_hit_detection.branch_hit_detection[0].bp.if_pc
|vpiLhs:
\_bit_select: (tag_matches), line:80
|vpiName:tag_matches
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_hit_detection.branch_hit_detection[0].tag_matches
|vpiIndex:
\_ref_obj: (i), line:80
|vpiName:i
|vpiParameter:
\_parameter: (ALU_UNIT_WB_ID), line:190
|vpiName:ALU_UNIT_WB_ID
|INT:32
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (BRANCH_PREDICTOR_WAYS), line:159
|vpiName:BRANCH_PREDICTOR_WAYS
|INT:9
|vpiParameter:
\_parameter: (BRANCH_TABLE_ENTRIES), line:160
|vpiName:BRANCH_TABLE_ENTRIES
|INT:4
|vpiParameter:
\_parameter: (BRANCH_UNIT_ID), line:195
|vpiName:BRANCH_UNIT_ID
|INT:8
|vpiParameter:
\_parameter: (BUS_ADDR_H), line:107
|vpiName:BUS_ADDR_H
|INT:1
|vpiParameter:
\_parameter: (BUS_ADDR_L), line:106
|vpiName:BUS_ADDR_L
|INT:0
|vpiParameter:
\_parameter: (BUS_BIT_CHECK), line:108
|vpiName:BUS_BIT_CHECK
|INT:1
|vpiParameter:
\_parameter: (BUS_TYPE), line:89
|vpiName:BUS_TYPE
|INT:5
|vpiParameter:
\_parameter: (COUNTER_W), line:42
|vpiName:COUNTER_W
|INT:33
|vpiParameter:
\_parameter: (CPU_ID), line:38
|vpiName:CPU_ID
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_ADDR_WIDTH), line:113
|vpiName:C_M_AXI_ADDR_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_DATA_WIDTH), line:114
|vpiName:C_M_AXI_DATA_WIDTH
|INT:1
|vpiParameter:
\_parameter: (DCACHE_LINES), line:133
|vpiName:DCACHE_LINES
|INT:-2146435073
|vpiParameter:
\_parameter: (DCACHE_LINE_ADDR_W), line:135
|vpiName:DCACHE_LINE_ADDR_W
|INT:1073741824
|vpiParameter:
\_parameter: (DCACHE_LINE_W), line:136
|vpiName:DCACHE_LINE_W
|INT:1342177279
|vpiParameter:
\_parameter: (DCACHE_SUB_LINE_ADDR_W), line:137
|vpiName:DCACHE_SUB_LINE_ADDR_W
|INT:4
|vpiParameter:
\_parameter: (DCACHE_TAG_W), line:138
|vpiName:DCACHE_TAG_W
|INT:1610612736
|vpiParameter:
\_parameter: (DCACHE_WAYS), line:134
|vpiName:DCACHE_WAYS
|INT:4
|vpiParameter:
\_parameter: (DIV_ALGORITHM), line:67
|vpiName:DIV_ALGORITHM
|INT:0
|vpiParameter:
\_parameter: (DIV_UNIT_WB_ID), line:192
|vpiName:DIV_UNIT_WB_ID
|INT:2
|vpiParameter:
\_parameter: (DTLB_DEPTH), line:152
|vpiName:DTLB_DEPTH
|INT:512
|vpiParameter:
\_parameter: (DTLB_WAYS), line:151
|vpiName:DTLB_WAYS
|INT:32
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (ENABLE_M_MODE), line:34
|vpiName:ENABLE_M_MODE
|INT:1
|vpiParameter:
\_parameter: (ENABLE_S_MODE), line:36
|vpiName:ENABLE_S_MODE
|INT:0
|vpiParameter:
\_parameter: (ENABLE_TRACE_INTERFACE), line:172
|vpiName:ENABLE_TRACE_INTERFACE
|INT:2
|vpiParameter:
\_parameter: (FETCH_BUFFER_DEPTH), line:168
|vpiName:FETCH_BUFFER_DEPTH
|INT:512
|vpiParameter:
\_parameter: (FPGA_VENDOR), line:27
|vpiName:FPGA_VENDOR
|STRING:"xilinx"
|vpiParameter:
\_parameter: (GC_UNIT_ID), line:196
|vpiName:GC_UNIT_ID
|INT:4
|vpiParameter:
\_parameter: (ICACHE_LINES), line:121
|vpiName:ICACHE_LINES
|INT:2
|vpiParameter:
\_parameter: (ICACHE_LINE_ADDR_W), line:123
|vpiName:ICACHE_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_LINE_W), line:124
|vpiName:ICACHE_LINE_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_SUB_LINE_ADDR_W), line:125
|vpiName:ICACHE_SUB_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_TAG_W), line:126
|vpiName:ICACHE_TAG_W
|INT:-2147483648
|vpiParameter:
\_parameter: (ICACHE_WAYS), line:122
|vpiName:ICACHE_WAYS
|INT:1
|vpiParameter:
\_parameter: (ITLB_DEPTH), line:146
|vpiName:ITLB_DEPTH
|INT:32
|vpiParameter:
\_parameter: (ITLB_WAYS), line:145
|vpiName:ITLB_WAYS
|INT:4
|vpiParameter:
\_parameter: (L1_CONNECTIONS), line:177
|vpiName:L1_CONNECTIONS
|INT:9
|vpiParameter:
\_parameter: (L1_DCACHE_ID), line:178
|vpiName:L1_DCACHE_ID
|INT:4
|vpiParameter:
\_parameter: (L1_DMMU_ID), line:179
|vpiName:L1_DMMU_ID
|INT:2
|vpiParameter:
\_parameter: (L1_ICACHE_ID), line:180
|vpiName:L1_ICACHE_ID
|INT:19
|vpiParameter:
\_parameter: (L1_IMMU_ID), line:181
|vpiName:L1_IMMU_ID
|INT:0
|vpiParameter:
\_parameter: (LS_UNIT_WB_ID), line:191
|vpiName:LS_UNIT_WB_ID
|INT:1
|vpiParameter:
\_parameter: (MAX_INFLIGHT_COUNT), line:167
|vpiName:MAX_INFLIGHT_COUNT
|INT:19
|vpiParameter:
\_parameter: (MEMORY_ADDR_H), line:103
|vpiName:MEMORY_ADDR_H
|INT:12
|vpiParameter:
\_parameter: (MEMORY_ADDR_L), line:102
|vpiName:MEMORY_ADDR_L
|INT:11
|vpiParameter:
\_parameter: (MEMORY_BIT_CHECK), line:104
|vpiName:MEMORY_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (MUL_UNIT_WB_ID), line:193
|vpiName:MUL_UNIT_WB_ID
|INT:512
|vpiParameter:
\_parameter: (NUM_UNITS), line:188
|vpiName:NUM_UNITS
|INT:2
|vpiParameter:
\_parameter: (NUM_WB_UNITS), line:186
|vpiName:NUM_WB_UNITS
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (RAS_DEPTH), line:161
|vpiName:RAS_DEPTH
|INT:2
|vpiParameter:
\_parameter: (RESET_VEC), line:39
|vpiName:RESET_VEC
|INT:-2147483648
|vpiParameter:
\_parameter: (SCRATCH_ADDR_H), line:99
|vpiName:SCRATCH_ADDR_H
|INT:9
|vpiParameter:
\_parameter: (SCRATCH_ADDR_L), line:98
|vpiName:SCRATCH_ADDR_L
|INT:8
|vpiParameter:
\_parameter: (SCRATCH_BIT_CHECK), line:100
|vpiName:SCRATCH_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (USE_AMO), line:70
|vpiName:USE_AMO
|INT:1
|vpiParameter:
\_parameter: (USE_BRANCH_PREDICTOR), line:158
|vpiName:USE_BRANCH_PREDICTOR
|INT:2
|vpiParameter:
\_parameter: (USE_BUS), line:88
|vpiName:USE_BUS
|INT:4
|vpiParameter:
\_parameter: (USE_DCACHE), line:92
|vpiName:USE_DCACHE
|INT:6
|vpiParameter:
\_parameter: (USE_DIV), line:49
|vpiName:USE_DIV
|INT:1
|vpiParameter:
\_parameter: (USE_DTAG_INVALIDATIONS), line:140
|vpiName:USE_DTAG_INVALIDATIONS
|INT:1879048191
|vpiParameter:
\_parameter: (USE_D_SCRATCH_MEM), line:79
|vpiName:USE_D_SCRATCH_MEM
|INT:3
|vpiParameter:
\_parameter: (USE_ICACHE), line:93
|vpiName:USE_ICACHE
|INT:7
|vpiParameter:
\_parameter: (USE_I_SCRATCH_MEM), line:78
|vpiName:USE_I_SCRATCH_MEM
|INT:2
|vpiParameter:
\_parameter: (USE_MUL), line:48
|vpiName:USE_MUL
|INT:1
|vpiParameter:
\_parameter: (WB_UNITS_WIDTH), line:187
|vpiName:WB_UNITS_WIDTH
|INT:32
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiParameter:
\_parameter: (i), line:79
|vpiName:i
|INT:0
|vpiGenScopeArray:
\_gen_scope_array: (branch_hit_detection[1]), line:79
|vpiName:branch_hit_detection[1]
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_hit_detection.branch_hit_detection[1]
|vpiGenScope:
\_gen_scope: , parent:branch_hit_detection[1]
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_hit_detection.branch_hit_detection[1]
|vpiContAssign:
\_cont_assign: , line:80
|vpiRhs:
\_operation: , line:80
|vpiOpType:14
|vpiOperand:
\_operation: , line:80
|vpiOpType:33
|vpiOperand:
\_bit_select: (if_entry.valid), line:80
|vpiName:if_entry.valid
|vpiIndex:
\_ref_obj: (i), line:80
|vpiName:i
|vpiOperand:
\_bit_select: (if_entry.tag), line:80
|vpiName:if_entry.tag
|vpiIndex:
\_ref_obj: (i), line:80
|vpiName:i
|vpiOperand:
\_operation: , line:80
|vpiOpType:33
|vpiOperand:
\_constant: , line:80
|vpiConstType:3
|vpiDecompile:'b1
|vpiSize:1
|BIN:1
|vpiOperand:
\_ref_obj: (bp.if_pc), line:80
|vpiName:bp.if_pc
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_hit_detection.branch_hit_detection[1].bp.if_pc
|vpiLhs:
\_bit_select: (tag_matches), line:80
|vpiName:tag_matches
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_hit_detection.branch_hit_detection[1].tag_matches
|vpiIndex:
\_ref_obj: (i), line:80
|vpiName:i
|vpiParameter:
\_parameter: (ALU_UNIT_WB_ID), line:190
|vpiName:ALU_UNIT_WB_ID
|INT:32
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (BRANCH_PREDICTOR_WAYS), line:159
|vpiName:BRANCH_PREDICTOR_WAYS
|INT:9
|vpiParameter:
\_parameter: (BRANCH_TABLE_ENTRIES), line:160
|vpiName:BRANCH_TABLE_ENTRIES
|INT:4
|vpiParameter:
\_parameter: (BRANCH_UNIT_ID), line:195
|vpiName:BRANCH_UNIT_ID
|INT:8
|vpiParameter:
\_parameter: (BUS_ADDR_H), line:107
|vpiName:BUS_ADDR_H
|INT:1
|vpiParameter:
\_parameter: (BUS_ADDR_L), line:106
|vpiName:BUS_ADDR_L
|INT:0
|vpiParameter:
\_parameter: (BUS_BIT_CHECK), line:108
|vpiName:BUS_BIT_CHECK
|INT:1
|vpiParameter:
\_parameter: (BUS_TYPE), line:89
|vpiName:BUS_TYPE
|INT:5
|vpiParameter:
\_parameter: (COUNTER_W), line:42
|vpiName:COUNTER_W
|INT:33
|vpiParameter:
\_parameter: (CPU_ID), line:38
|vpiName:CPU_ID
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_ADDR_WIDTH), line:113
|vpiName:C_M_AXI_ADDR_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_DATA_WIDTH), line:114
|vpiName:C_M_AXI_DATA_WIDTH
|INT:1
|vpiParameter:
\_parameter: (DCACHE_LINES), line:133
|vpiName:DCACHE_LINES
|INT:-2146435073
|vpiParameter:
\_parameter: (DCACHE_LINE_ADDR_W), line:135
|vpiName:DCACHE_LINE_ADDR_W
|INT:1073741824
|vpiParameter:
\_parameter: (DCACHE_LINE_W), line:136
|vpiName:DCACHE_LINE_W
|INT:1342177279
|vpiParameter:
\_parameter: (DCACHE_SUB_LINE_ADDR_W), line:137
|vpiName:DCACHE_SUB_LINE_ADDR_W
|INT:4
|vpiParameter:
\_parameter: (DCACHE_TAG_W), line:138
|vpiName:DCACHE_TAG_W
|INT:1610612736
|vpiParameter:
\_parameter: (DCACHE_WAYS), line:134
|vpiName:DCACHE_WAYS
|INT:4
|vpiParameter:
\_parameter: (DIV_ALGORITHM), line:67
|vpiName:DIV_ALGORITHM
|INT:0
|vpiParameter:
\_parameter: (DIV_UNIT_WB_ID), line:192
|vpiName:DIV_UNIT_WB_ID
|INT:2
|vpiParameter:
\_parameter: (DTLB_DEPTH), line:152
|vpiName:DTLB_DEPTH
|INT:512
|vpiParameter:
\_parameter: (DTLB_WAYS), line:151
|vpiName:DTLB_WAYS
|INT:32
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (ENABLE_M_MODE), line:34
|vpiName:ENABLE_M_MODE
|INT:1
|vpiParameter:
\_parameter: (ENABLE_S_MODE), line:36
|vpiName:ENABLE_S_MODE
|INT:0
|vpiParameter:
\_parameter: (ENABLE_TRACE_INTERFACE), line:172
|vpiName:ENABLE_TRACE_INTERFACE
|INT:2
|vpiParameter:
\_parameter: (FETCH_BUFFER_DEPTH), line:168
|vpiName:FETCH_BUFFER_DEPTH
|INT:512
|vpiParameter:
\_parameter: (FPGA_VENDOR), line:27
|vpiName:FPGA_VENDOR
|STRING:"xilinx"
|vpiParameter:
\_parameter: (GC_UNIT_ID), line:196
|vpiName:GC_UNIT_ID
|INT:4
|vpiParameter:
\_parameter: (ICACHE_LINES), line:121
|vpiName:ICACHE_LINES
|INT:2
|vpiParameter:
\_parameter: (ICACHE_LINE_ADDR_W), line:123
|vpiName:ICACHE_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_LINE_W), line:124
|vpiName:ICACHE_LINE_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_SUB_LINE_ADDR_W), line:125
|vpiName:ICACHE_SUB_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_TAG_W), line:126
|vpiName:ICACHE_TAG_W
|INT:-2147483648
|vpiParameter:
\_parameter: (ICACHE_WAYS), line:122
|vpiName:ICACHE_WAYS
|INT:1
|vpiParameter:
\_parameter: (ITLB_DEPTH), line:146
|vpiName:ITLB_DEPTH
|INT:32
|vpiParameter:
\_parameter: (ITLB_WAYS), line:145
|vpiName:ITLB_WAYS
|INT:4
|vpiParameter:
\_parameter: (L1_CONNECTIONS), line:177
|vpiName:L1_CONNECTIONS
|INT:9
|vpiParameter:
\_parameter: (L1_DCACHE_ID), line:178
|vpiName:L1_DCACHE_ID
|INT:4
|vpiParameter:
\_parameter: (L1_DMMU_ID), line:179
|vpiName:L1_DMMU_ID
|INT:2
|vpiParameter:
\_parameter: (L1_ICACHE_ID), line:180
|vpiName:L1_ICACHE_ID
|INT:19
|vpiParameter:
\_parameter: (L1_IMMU_ID), line:181
|vpiName:L1_IMMU_ID
|INT:0
|vpiParameter:
\_parameter: (LS_UNIT_WB_ID), line:191
|vpiName:LS_UNIT_WB_ID
|INT:1
|vpiParameter:
\_parameter: (MAX_INFLIGHT_COUNT), line:167
|vpiName:MAX_INFLIGHT_COUNT
|INT:19
|vpiParameter:
\_parameter: (MEMORY_ADDR_H), line:103
|vpiName:MEMORY_ADDR_H
|INT:12
|vpiParameter:
\_parameter: (MEMORY_ADDR_L), line:102
|vpiName:MEMORY_ADDR_L
|INT:11
|vpiParameter:
\_parameter: (MEMORY_BIT_CHECK), line:104
|vpiName:MEMORY_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (MUL_UNIT_WB_ID), line:193
|vpiName:MUL_UNIT_WB_ID
|INT:512
|vpiParameter:
\_parameter: (NUM_UNITS), line:188
|vpiName:NUM_UNITS
|INT:2
|vpiParameter:
\_parameter: (NUM_WB_UNITS), line:186
|vpiName:NUM_WB_UNITS
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (RAS_DEPTH), line:161
|vpiName:RAS_DEPTH
|INT:2
|vpiParameter:
\_parameter: (RESET_VEC), line:39
|vpiName:RESET_VEC
|INT:-2147483648
|vpiParameter:
\_parameter: (SCRATCH_ADDR_H), line:99
|vpiName:SCRATCH_ADDR_H
|INT:9
|vpiParameter:
\_parameter: (SCRATCH_ADDR_L), line:98
|vpiName:SCRATCH_ADDR_L
|INT:8
|vpiParameter:
\_parameter: (SCRATCH_BIT_CHECK), line:100
|vpiName:SCRATCH_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (USE_AMO), line:70
|vpiName:USE_AMO
|INT:1
|vpiParameter:
\_parameter: (USE_BRANCH_PREDICTOR), line:158
|vpiName:USE_BRANCH_PREDICTOR
|INT:2
|vpiParameter:
\_parameter: (USE_BUS), line:88
|vpiName:USE_BUS
|INT:4
|vpiParameter:
\_parameter: (USE_DCACHE), line:92
|vpiName:USE_DCACHE
|INT:6
|vpiParameter:
\_parameter: (USE_DIV), line:49
|vpiName:USE_DIV
|INT:1
|vpiParameter:
\_parameter: (USE_DTAG_INVALIDATIONS), line:140
|vpiName:USE_DTAG_INVALIDATIONS
|INT:1879048191
|vpiParameter:
\_parameter: (USE_D_SCRATCH_MEM), line:79
|vpiName:USE_D_SCRATCH_MEM
|INT:3
|vpiParameter:
\_parameter: (USE_ICACHE), line:93
|vpiName:USE_ICACHE
|INT:7
|vpiParameter:
\_parameter: (USE_I_SCRATCH_MEM), line:78
|vpiName:USE_I_SCRATCH_MEM
|INT:2
|vpiParameter:
\_parameter: (USE_MUL), line:48
|vpiName:USE_MUL
|INT:1
|vpiParameter:
\_parameter: (WB_UNITS_WIDTH), line:187
|vpiName:WB_UNITS_WIDTH
|INT:32
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiParameter:
\_parameter: (i), line:79
|vpiName:i
|INT:1
|vpiGenScopeArray:
\_gen_scope_array: (branch_hit_detection[2]), line:79
|vpiName:branch_hit_detection[2]
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_hit_detection.branch_hit_detection[2]
|vpiGenScope:
\_gen_scope: , parent:branch_hit_detection[2]
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_hit_detection.branch_hit_detection[2]
|vpiContAssign:
\_cont_assign: , line:80
|vpiRhs:
\_operation: , line:80
|vpiOpType:14
|vpiOperand:
\_operation: , line:80
|vpiOpType:33
|vpiOperand:
\_bit_select: (if_entry.valid), line:80
|vpiName:if_entry.valid
|vpiIndex:
\_ref_obj: (i), line:80
|vpiName:i
|vpiOperand:
\_bit_select: (if_entry.tag), line:80
|vpiName:if_entry.tag
|vpiIndex:
\_ref_obj: (i), line:80
|vpiName:i
|vpiOperand:
\_operation: , line:80
|vpiOpType:33
|vpiOperand:
\_constant: , line:80
|vpiConstType:3
|vpiDecompile:'b1
|vpiSize:1
|BIN:1
|vpiOperand:
\_ref_obj: (bp.if_pc), line:80
|vpiName:bp.if_pc
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_hit_detection.branch_hit_detection[2].bp.if_pc
|vpiLhs:
\_bit_select: (tag_matches), line:80
|vpiName:tag_matches
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_hit_detection.branch_hit_detection[2].tag_matches
|vpiIndex:
\_ref_obj: (i), line:80
|vpiName:i
|vpiParameter:
\_parameter: (ALU_UNIT_WB_ID), line:190
|vpiName:ALU_UNIT_WB_ID
|INT:32
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (BRANCH_PREDICTOR_WAYS), line:159
|vpiName:BRANCH_PREDICTOR_WAYS
|INT:9
|vpiParameter:
\_parameter: (BRANCH_TABLE_ENTRIES), line:160
|vpiName:BRANCH_TABLE_ENTRIES
|INT:4
|vpiParameter:
\_parameter: (BRANCH_UNIT_ID), line:195
|vpiName:BRANCH_UNIT_ID
|INT:8
|vpiParameter:
\_parameter: (BUS_ADDR_H), line:107
|vpiName:BUS_ADDR_H
|INT:1
|vpiParameter:
\_parameter: (BUS_ADDR_L), line:106
|vpiName:BUS_ADDR_L
|INT:0
|vpiParameter:
\_parameter: (BUS_BIT_CHECK), line:108
|vpiName:BUS_BIT_CHECK
|INT:1
|vpiParameter:
\_parameter: (BUS_TYPE), line:89
|vpiName:BUS_TYPE
|INT:5
|vpiParameter:
\_parameter: (COUNTER_W), line:42
|vpiName:COUNTER_W
|INT:33
|vpiParameter:
\_parameter: (CPU_ID), line:38
|vpiName:CPU_ID
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_ADDR_WIDTH), line:113
|vpiName:C_M_AXI_ADDR_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_DATA_WIDTH), line:114
|vpiName:C_M_AXI_DATA_WIDTH
|INT:1
|vpiParameter:
\_parameter: (DCACHE_LINES), line:133
|vpiName:DCACHE_LINES
|INT:-2146435073
|vpiParameter:
\_parameter: (DCACHE_LINE_ADDR_W), line:135
|vpiName:DCACHE_LINE_ADDR_W
|INT:1073741824
|vpiParameter:
\_parameter: (DCACHE_LINE_W), line:136
|vpiName:DCACHE_LINE_W
|INT:1342177279
|vpiParameter:
\_parameter: (DCACHE_SUB_LINE_ADDR_W), line:137
|vpiName:DCACHE_SUB_LINE_ADDR_W
|INT:4
|vpiParameter:
\_parameter: (DCACHE_TAG_W), line:138
|vpiName:DCACHE_TAG_W
|INT:1610612736
|vpiParameter:
\_parameter: (DCACHE_WAYS), line:134
|vpiName:DCACHE_WAYS
|INT:4
|vpiParameter:
\_parameter: (DIV_ALGORITHM), line:67
|vpiName:DIV_ALGORITHM
|INT:0
|vpiParameter:
\_parameter: (DIV_UNIT_WB_ID), line:192
|vpiName:DIV_UNIT_WB_ID
|INT:2
|vpiParameter:
\_parameter: (DTLB_DEPTH), line:152
|vpiName:DTLB_DEPTH
|INT:512
|vpiParameter:
\_parameter: (DTLB_WAYS), line:151
|vpiName:DTLB_WAYS
|INT:32
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (ENABLE_M_MODE), line:34
|vpiName:ENABLE_M_MODE
|INT:1
|vpiParameter:
\_parameter: (ENABLE_S_MODE), line:36
|vpiName:ENABLE_S_MODE
|INT:0
|vpiParameter:
\_parameter: (ENABLE_TRACE_INTERFACE), line:172
|vpiName:ENABLE_TRACE_INTERFACE
|INT:2
|vpiParameter:
\_parameter: (FETCH_BUFFER_DEPTH), line:168
|vpiName:FETCH_BUFFER_DEPTH
|INT:512
|vpiParameter:
\_parameter: (FPGA_VENDOR), line:27
|vpiName:FPGA_VENDOR
|STRING:"xilinx"
|vpiParameter:
\_parameter: (GC_UNIT_ID), line:196
|vpiName:GC_UNIT_ID
|INT:4
|vpiParameter:
\_parameter: (ICACHE_LINES), line:121
|vpiName:ICACHE_LINES
|INT:2
|vpiParameter:
\_parameter: (ICACHE_LINE_ADDR_W), line:123
|vpiName:ICACHE_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_LINE_W), line:124
|vpiName:ICACHE_LINE_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_SUB_LINE_ADDR_W), line:125
|vpiName:ICACHE_SUB_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_TAG_W), line:126
|vpiName:ICACHE_TAG_W
|INT:-2147483648
|vpiParameter:
\_parameter: (ICACHE_WAYS), line:122
|vpiName:ICACHE_WAYS
|INT:1
|vpiParameter:
\_parameter: (ITLB_DEPTH), line:146
|vpiName:ITLB_DEPTH
|INT:32
|vpiParameter:
\_parameter: (ITLB_WAYS), line:145
|vpiName:ITLB_WAYS
|INT:4
|vpiParameter:
\_parameter: (L1_CONNECTIONS), line:177
|vpiName:L1_CONNECTIONS
|INT:9
|vpiParameter:
\_parameter: (L1_DCACHE_ID), line:178
|vpiName:L1_DCACHE_ID
|INT:4
|vpiParameter:
\_parameter: (L1_DMMU_ID), line:179
|vpiName:L1_DMMU_ID
|INT:2
|vpiParameter:
\_parameter: (L1_ICACHE_ID), line:180
|vpiName:L1_ICACHE_ID
|INT:19
|vpiParameter:
\_parameter: (L1_IMMU_ID), line:181
|vpiName:L1_IMMU_ID
|INT:0
|vpiParameter:
\_parameter: (LS_UNIT_WB_ID), line:191
|vpiName:LS_UNIT_WB_ID
|INT:1
|vpiParameter:
\_parameter: (MAX_INFLIGHT_COUNT), line:167
|vpiName:MAX_INFLIGHT_COUNT
|INT:19
|vpiParameter:
\_parameter: (MEMORY_ADDR_H), line:103
|vpiName:MEMORY_ADDR_H
|INT:12
|vpiParameter:
\_parameter: (MEMORY_ADDR_L), line:102
|vpiName:MEMORY_ADDR_L
|INT:11
|vpiParameter:
\_parameter: (MEMORY_BIT_CHECK), line:104
|vpiName:MEMORY_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (MUL_UNIT_WB_ID), line:193
|vpiName:MUL_UNIT_WB_ID
|INT:512
|vpiParameter:
\_parameter: (NUM_UNITS), line:188
|vpiName:NUM_UNITS
|INT:2
|vpiParameter:
\_parameter: (NUM_WB_UNITS), line:186
|vpiName:NUM_WB_UNITS
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (RAS_DEPTH), line:161
|vpiName:RAS_DEPTH
|INT:2
|vpiParameter:
\_parameter: (RESET_VEC), line:39
|vpiName:RESET_VEC
|INT:-2147483648
|vpiParameter:
\_parameter: (SCRATCH_ADDR_H), line:99
|vpiName:SCRATCH_ADDR_H
|INT:9
|vpiParameter:
\_parameter: (SCRATCH_ADDR_L), line:98
|vpiName:SCRATCH_ADDR_L
|INT:8
|vpiParameter:
\_parameter: (SCRATCH_BIT_CHECK), line:100
|vpiName:SCRATCH_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (USE_AMO), line:70
|vpiName:USE_AMO
|INT:1
|vpiParameter:
\_parameter: (USE_BRANCH_PREDICTOR), line:158
|vpiName:USE_BRANCH_PREDICTOR
|INT:2
|vpiParameter:
\_parameter: (USE_BUS), line:88
|vpiName:USE_BUS
|INT:4
|vpiParameter:
\_parameter: (USE_DCACHE), line:92
|vpiName:USE_DCACHE
|INT:6
|vpiParameter:
\_parameter: (USE_DIV), line:49
|vpiName:USE_DIV
|INT:1
|vpiParameter:
\_parameter: (USE_DTAG_INVALIDATIONS), line:140
|vpiName:USE_DTAG_INVALIDATIONS
|INT:1879048191
|vpiParameter:
\_parameter: (USE_D_SCRATCH_MEM), line:79
|vpiName:USE_D_SCRATCH_MEM
|INT:3
|vpiParameter:
\_parameter: (USE_ICACHE), line:93
|vpiName:USE_ICACHE
|INT:7
|vpiParameter:
\_parameter: (USE_I_SCRATCH_MEM), line:78
|vpiName:USE_I_SCRATCH_MEM
|INT:2
|vpiParameter:
\_parameter: (USE_MUL), line:48
|vpiName:USE_MUL
|INT:1
|vpiParameter:
\_parameter: (WB_UNITS_WIDTH), line:187
|vpiName:WB_UNITS_WIDTH
|INT:32
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiParameter:
\_parameter: (i), line:79
|vpiName:i
|INT:2
|vpiGenScopeArray:
\_gen_scope_array: (branch_hit_detection[3]), line:79
|vpiName:branch_hit_detection[3]
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_hit_detection.branch_hit_detection[3]
|vpiGenScope:
\_gen_scope: , parent:branch_hit_detection[3]
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_hit_detection.branch_hit_detection[3]
|vpiContAssign:
\_cont_assign: , line:80
|vpiRhs:
\_operation: , line:80
|vpiOpType:14
|vpiOperand:
\_operation: , line:80
|vpiOpType:33
|vpiOperand:
\_bit_select: (if_entry.valid), line:80
|vpiName:if_entry.valid
|vpiIndex:
\_ref_obj: (i), line:80
|vpiName:i
|vpiOperand:
\_bit_select: (if_entry.tag), line:80
|vpiName:if_entry.tag
|vpiIndex:
\_ref_obj: (i), line:80
|vpiName:i
|vpiOperand:
\_operation: , line:80
|vpiOpType:33
|vpiOperand:
\_constant: , line:80
|vpiConstType:3
|vpiDecompile:'b1
|vpiSize:1
|BIN:1
|vpiOperand:
\_ref_obj: (bp.if_pc), line:80
|vpiName:bp.if_pc
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_hit_detection.branch_hit_detection[3].bp.if_pc
|vpiLhs:
\_bit_select: (tag_matches), line:80
|vpiName:tag_matches
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_hit_detection.branch_hit_detection[3].tag_matches
|vpiIndex:
\_ref_obj: (i), line:80
|vpiName:i
|vpiParameter:
\_parameter: (ALU_UNIT_WB_ID), line:190
|vpiName:ALU_UNIT_WB_ID
|INT:32
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (BRANCH_PREDICTOR_WAYS), line:159
|vpiName:BRANCH_PREDICTOR_WAYS
|INT:9
|vpiParameter:
\_parameter: (BRANCH_TABLE_ENTRIES), line:160
|vpiName:BRANCH_TABLE_ENTRIES
|INT:4
|vpiParameter:
\_parameter: (BRANCH_UNIT_ID), line:195
|vpiName:BRANCH_UNIT_ID
|INT:8
|vpiParameter:
\_parameter: (BUS_ADDR_H), line:107
|vpiName:BUS_ADDR_H
|INT:1
|vpiParameter:
\_parameter: (BUS_ADDR_L), line:106
|vpiName:BUS_ADDR_L
|INT:0
|vpiParameter:
\_parameter: (BUS_BIT_CHECK), line:108
|vpiName:BUS_BIT_CHECK
|INT:1
|vpiParameter:
\_parameter: (BUS_TYPE), line:89
|vpiName:BUS_TYPE
|INT:5
|vpiParameter:
\_parameter: (COUNTER_W), line:42
|vpiName:COUNTER_W
|INT:33
|vpiParameter:
\_parameter: (CPU_ID), line:38
|vpiName:CPU_ID
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_ADDR_WIDTH), line:113
|vpiName:C_M_AXI_ADDR_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_DATA_WIDTH), line:114
|vpiName:C_M_AXI_DATA_WIDTH
|INT:1
|vpiParameter:
\_parameter: (DCACHE_LINES), line:133
|vpiName:DCACHE_LINES
|INT:-2146435073
|vpiParameter:
\_parameter: (DCACHE_LINE_ADDR_W), line:135
|vpiName:DCACHE_LINE_ADDR_W
|INT:1073741824
|vpiParameter:
\_parameter: (DCACHE_LINE_W), line:136
|vpiName:DCACHE_LINE_W
|INT:1342177279
|vpiParameter:
\_parameter: (DCACHE_SUB_LINE_ADDR_W), line:137
|vpiName:DCACHE_SUB_LINE_ADDR_W
|INT:4
|vpiParameter:
\_parameter: (DCACHE_TAG_W), line:138
|vpiName:DCACHE_TAG_W
|INT:1610612736
|vpiParameter:
\_parameter: (DCACHE_WAYS), line:134
|vpiName:DCACHE_WAYS
|INT:4
|vpiParameter:
\_parameter: (DIV_ALGORITHM), line:67
|vpiName:DIV_ALGORITHM
|INT:0
|vpiParameter:
\_parameter: (DIV_UNIT_WB_ID), line:192
|vpiName:DIV_UNIT_WB_ID
|INT:2
|vpiParameter:
\_parameter: (DTLB_DEPTH), line:152
|vpiName:DTLB_DEPTH
|INT:512
|vpiParameter:
\_parameter: (DTLB_WAYS), line:151
|vpiName:DTLB_WAYS
|INT:32
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (ENABLE_M_MODE), line:34
|vpiName:ENABLE_M_MODE
|INT:1
|vpiParameter:
\_parameter: (ENABLE_S_MODE), line:36
|vpiName:ENABLE_S_MODE
|INT:0
|vpiParameter:
\_parameter: (ENABLE_TRACE_INTERFACE), line:172
|vpiName:ENABLE_TRACE_INTERFACE
|INT:2
|vpiParameter:
\_parameter: (FETCH_BUFFER_DEPTH), line:168
|vpiName:FETCH_BUFFER_DEPTH
|INT:512
|vpiParameter:
\_parameter: (FPGA_VENDOR), line:27
|vpiName:FPGA_VENDOR
|STRING:"xilinx"
|vpiParameter:
\_parameter: (GC_UNIT_ID), line:196
|vpiName:GC_UNIT_ID
|INT:4
|vpiParameter:
\_parameter: (ICACHE_LINES), line:121
|vpiName:ICACHE_LINES
|INT:2
|vpiParameter:
\_parameter: (ICACHE_LINE_ADDR_W), line:123
|vpiName:ICACHE_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_LINE_W), line:124
|vpiName:ICACHE_LINE_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_SUB_LINE_ADDR_W), line:125
|vpiName:ICACHE_SUB_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_TAG_W), line:126
|vpiName:ICACHE_TAG_W
|INT:-2147483648
|vpiParameter:
\_parameter: (ICACHE_WAYS), line:122
|vpiName:ICACHE_WAYS
|INT:1
|vpiParameter:
\_parameter: (ITLB_DEPTH), line:146
|vpiName:ITLB_DEPTH
|INT:32
|vpiParameter:
\_parameter: (ITLB_WAYS), line:145
|vpiName:ITLB_WAYS
|INT:4
|vpiParameter:
\_parameter: (L1_CONNECTIONS), line:177
|vpiName:L1_CONNECTIONS
|INT:9
|vpiParameter:
\_parameter: (L1_DCACHE_ID), line:178
|vpiName:L1_DCACHE_ID
|INT:4
|vpiParameter:
\_parameter: (L1_DMMU_ID), line:179
|vpiName:L1_DMMU_ID
|INT:2
|vpiParameter:
\_parameter: (L1_ICACHE_ID), line:180
|vpiName:L1_ICACHE_ID
|INT:19
|vpiParameter:
\_parameter: (L1_IMMU_ID), line:181
|vpiName:L1_IMMU_ID
|INT:0
|vpiParameter:
\_parameter: (LS_UNIT_WB_ID), line:191
|vpiName:LS_UNIT_WB_ID
|INT:1
|vpiParameter:
\_parameter: (MAX_INFLIGHT_COUNT), line:167
|vpiName:MAX_INFLIGHT_COUNT
|INT:19
|vpiParameter:
\_parameter: (MEMORY_ADDR_H), line:103
|vpiName:MEMORY_ADDR_H
|INT:12
|vpiParameter:
\_parameter: (MEMORY_ADDR_L), line:102
|vpiName:MEMORY_ADDR_L
|INT:11
|vpiParameter:
\_parameter: (MEMORY_BIT_CHECK), line:104
|vpiName:MEMORY_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (MUL_UNIT_WB_ID), line:193
|vpiName:MUL_UNIT_WB_ID
|INT:512
|vpiParameter:
\_parameter: (NUM_UNITS), line:188
|vpiName:NUM_UNITS
|INT:2
|vpiParameter:
\_parameter: (NUM_WB_UNITS), line:186
|vpiName:NUM_WB_UNITS
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (RAS_DEPTH), line:161
|vpiName:RAS_DEPTH
|INT:2
|vpiParameter:
\_parameter: (RESET_VEC), line:39
|vpiName:RESET_VEC
|INT:-2147483648
|vpiParameter:
\_parameter: (SCRATCH_ADDR_H), line:99
|vpiName:SCRATCH_ADDR_H
|INT:9
|vpiParameter:
\_parameter: (SCRATCH_ADDR_L), line:98
|vpiName:SCRATCH_ADDR_L
|INT:8
|vpiParameter:
\_parameter: (SCRATCH_BIT_CHECK), line:100
|vpiName:SCRATCH_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (USE_AMO), line:70
|vpiName:USE_AMO
|INT:1
|vpiParameter:
\_parameter: (USE_BRANCH_PREDICTOR), line:158
|vpiName:USE_BRANCH_PREDICTOR
|INT:2
|vpiParameter:
\_parameter: (USE_BUS), line:88
|vpiName:USE_BUS
|INT:4
|vpiParameter:
\_parameter: (USE_DCACHE), line:92
|vpiName:USE_DCACHE
|INT:6
|vpiParameter:
\_parameter: (USE_DIV), line:49
|vpiName:USE_DIV
|INT:1
|vpiParameter:
\_parameter: (USE_DTAG_INVALIDATIONS), line:140
|vpiName:USE_DTAG_INVALIDATIONS
|INT:1879048191
|vpiParameter:
\_parameter: (USE_D_SCRATCH_MEM), line:79
|vpiName:USE_D_SCRATCH_MEM
|INT:3
|vpiParameter:
\_parameter: (USE_ICACHE), line:93
|vpiName:USE_ICACHE
|INT:7
|vpiParameter:
\_parameter: (USE_I_SCRATCH_MEM), line:78
|vpiName:USE_I_SCRATCH_MEM
|INT:2
|vpiParameter:
\_parameter: (USE_MUL), line:48
|vpiName:USE_MUL
|INT:1
|vpiParameter:
\_parameter: (WB_UNITS_WIDTH), line:187
|vpiName:WB_UNITS_WIDTH
|INT:32
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiParameter:
\_parameter: (i), line:79
|vpiName:i
|INT:3
|vpiGenScopeArray:
\_gen_scope_array: (branch_hit_detection[4]), line:79
|vpiName:branch_hit_detection[4]
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_hit_detection.branch_hit_detection[4]
|vpiGenScope:
\_gen_scope: , parent:branch_hit_detection[4]
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_hit_detection.branch_hit_detection[4]
|vpiContAssign:
\_cont_assign: , line:80
|vpiRhs:
\_operation: , line:80
|vpiOpType:14
|vpiOperand:
\_operation: , line:80
|vpiOpType:33
|vpiOperand:
\_bit_select: (if_entry.valid), line:80
|vpiName:if_entry.valid
|vpiIndex:
\_ref_obj: (i), line:80
|vpiName:i
|vpiOperand:
\_bit_select: (if_entry.tag), line:80
|vpiName:if_entry.tag
|vpiIndex:
\_ref_obj: (i), line:80
|vpiName:i
|vpiOperand:
\_operation: , line:80
|vpiOpType:33
|vpiOperand:
\_constant: , line:80
|vpiConstType:3
|vpiDecompile:'b1
|vpiSize:1
|BIN:1
|vpiOperand:
\_ref_obj: (bp.if_pc), line:80
|vpiName:bp.if_pc
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_hit_detection.branch_hit_detection[4].bp.if_pc
|vpiLhs:
\_bit_select: (tag_matches), line:80
|vpiName:tag_matches
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_hit_detection.branch_hit_detection[4].tag_matches
|vpiIndex:
\_ref_obj: (i), line:80
|vpiName:i
|vpiParameter:
\_parameter: (ALU_UNIT_WB_ID), line:190
|vpiName:ALU_UNIT_WB_ID
|INT:32
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (BRANCH_PREDICTOR_WAYS), line:159
|vpiName:BRANCH_PREDICTOR_WAYS
|INT:9
|vpiParameter:
\_parameter: (BRANCH_TABLE_ENTRIES), line:160
|vpiName:BRANCH_TABLE_ENTRIES
|INT:4
|vpiParameter:
\_parameter: (BRANCH_UNIT_ID), line:195
|vpiName:BRANCH_UNIT_ID
|INT:8
|vpiParameter:
\_parameter: (BUS_ADDR_H), line:107
|vpiName:BUS_ADDR_H
|INT:1
|vpiParameter:
\_parameter: (BUS_ADDR_L), line:106
|vpiName:BUS_ADDR_L
|INT:0
|vpiParameter:
\_parameter: (BUS_BIT_CHECK), line:108
|vpiName:BUS_BIT_CHECK
|INT:1
|vpiParameter:
\_parameter: (BUS_TYPE), line:89
|vpiName:BUS_TYPE
|INT:5
|vpiParameter:
\_parameter: (COUNTER_W), line:42
|vpiName:COUNTER_W
|INT:33
|vpiParameter:
\_parameter: (CPU_ID), line:38
|vpiName:CPU_ID
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_ADDR_WIDTH), line:113
|vpiName:C_M_AXI_ADDR_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_DATA_WIDTH), line:114
|vpiName:C_M_AXI_DATA_WIDTH
|INT:1
|vpiParameter:
\_parameter: (DCACHE_LINES), line:133
|vpiName:DCACHE_LINES
|INT:-2146435073
|vpiParameter:
\_parameter: (DCACHE_LINE_ADDR_W), line:135
|vpiName:DCACHE_LINE_ADDR_W
|INT:1073741824
|vpiParameter:
\_parameter: (DCACHE_LINE_W), line:136
|vpiName:DCACHE_LINE_W
|INT:1342177279
|vpiParameter:
\_parameter: (DCACHE_SUB_LINE_ADDR_W), line:137
|vpiName:DCACHE_SUB_LINE_ADDR_W
|INT:4
|vpiParameter:
\_parameter: (DCACHE_TAG_W), line:138
|vpiName:DCACHE_TAG_W
|INT:1610612736
|vpiParameter:
\_parameter: (DCACHE_WAYS), line:134
|vpiName:DCACHE_WAYS
|INT:4
|vpiParameter:
\_parameter: (DIV_ALGORITHM), line:67
|vpiName:DIV_ALGORITHM
|INT:0
|vpiParameter:
\_parameter: (DIV_UNIT_WB_ID), line:192
|vpiName:DIV_UNIT_WB_ID
|INT:2
|vpiParameter:
\_parameter: (DTLB_DEPTH), line:152
|vpiName:DTLB_DEPTH
|INT:512
|vpiParameter:
\_parameter: (DTLB_WAYS), line:151
|vpiName:DTLB_WAYS
|INT:32
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (ENABLE_M_MODE), line:34
|vpiName:ENABLE_M_MODE
|INT:1
|vpiParameter:
\_parameter: (ENABLE_S_MODE), line:36
|vpiName:ENABLE_S_MODE
|INT:0
|vpiParameter:
\_parameter: (ENABLE_TRACE_INTERFACE), line:172
|vpiName:ENABLE_TRACE_INTERFACE
|INT:2
|vpiParameter:
\_parameter: (FETCH_BUFFER_DEPTH), line:168
|vpiName:FETCH_BUFFER_DEPTH
|INT:512
|vpiParameter:
\_parameter: (FPGA_VENDOR), line:27
|vpiName:FPGA_VENDOR
|STRING:"xilinx"
|vpiParameter:
\_parameter: (GC_UNIT_ID), line:196
|vpiName:GC_UNIT_ID
|INT:4
|vpiParameter:
\_parameter: (ICACHE_LINES), line:121
|vpiName:ICACHE_LINES
|INT:2
|vpiParameter:
\_parameter: (ICACHE_LINE_ADDR_W), line:123
|vpiName:ICACHE_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_LINE_W), line:124
|vpiName:ICACHE_LINE_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_SUB_LINE_ADDR_W), line:125
|vpiName:ICACHE_SUB_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_TAG_W), line:126
|vpiName:ICACHE_TAG_W
|INT:-2147483648
|vpiParameter:
\_parameter: (ICACHE_WAYS), line:122
|vpiName:ICACHE_WAYS
|INT:1
|vpiParameter:
\_parameter: (ITLB_DEPTH), line:146
|vpiName:ITLB_DEPTH
|INT:32
|vpiParameter:
\_parameter: (ITLB_WAYS), line:145
|vpiName:ITLB_WAYS
|INT:4
|vpiParameter:
\_parameter: (L1_CONNECTIONS), line:177
|vpiName:L1_CONNECTIONS
|INT:9
|vpiParameter:
\_parameter: (L1_DCACHE_ID), line:178
|vpiName:L1_DCACHE_ID
|INT:4
|vpiParameter:
\_parameter: (L1_DMMU_ID), line:179
|vpiName:L1_DMMU_ID
|INT:2
|vpiParameter:
\_parameter: (L1_ICACHE_ID), line:180
|vpiName:L1_ICACHE_ID
|INT:19
|vpiParameter:
\_parameter: (L1_IMMU_ID), line:181
|vpiName:L1_IMMU_ID
|INT:0
|vpiParameter:
\_parameter: (LS_UNIT_WB_ID), line:191
|vpiName:LS_UNIT_WB_ID
|INT:1
|vpiParameter:
\_parameter: (MAX_INFLIGHT_COUNT), line:167
|vpiName:MAX_INFLIGHT_COUNT
|INT:19
|vpiParameter:
\_parameter: (MEMORY_ADDR_H), line:103
|vpiName:MEMORY_ADDR_H
|INT:12
|vpiParameter:
\_parameter: (MEMORY_ADDR_L), line:102
|vpiName:MEMORY_ADDR_L
|INT:11
|vpiParameter:
\_parameter: (MEMORY_BIT_CHECK), line:104
|vpiName:MEMORY_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (MUL_UNIT_WB_ID), line:193
|vpiName:MUL_UNIT_WB_ID
|INT:512
|vpiParameter:
\_parameter: (NUM_UNITS), line:188
|vpiName:NUM_UNITS
|INT:2
|vpiParameter:
\_parameter: (NUM_WB_UNITS), line:186
|vpiName:NUM_WB_UNITS
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (RAS_DEPTH), line:161
|vpiName:RAS_DEPTH
|INT:2
|vpiParameter:
\_parameter: (RESET_VEC), line:39
|vpiName:RESET_VEC
|INT:-2147483648
|vpiParameter:
\_parameter: (SCRATCH_ADDR_H), line:99
|vpiName:SCRATCH_ADDR_H
|INT:9
|vpiParameter:
\_parameter: (SCRATCH_ADDR_L), line:98
|vpiName:SCRATCH_ADDR_L
|INT:8
|vpiParameter:
\_parameter: (SCRATCH_BIT_CHECK), line:100
|vpiName:SCRATCH_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (USE_AMO), line:70
|vpiName:USE_AMO
|INT:1
|vpiParameter:
\_parameter: (USE_BRANCH_PREDICTOR), line:158
|vpiName:USE_BRANCH_PREDICTOR
|INT:2
|vpiParameter:
\_parameter: (USE_BUS), line:88
|vpiName:USE_BUS
|INT:4
|vpiParameter:
\_parameter: (USE_DCACHE), line:92
|vpiName:USE_DCACHE
|INT:6
|vpiParameter:
\_parameter: (USE_DIV), line:49
|vpiName:USE_DIV
|INT:1
|vpiParameter:
\_parameter: (USE_DTAG_INVALIDATIONS), line:140
|vpiName:USE_DTAG_INVALIDATIONS
|INT:1879048191
|vpiParameter:
\_parameter: (USE_D_SCRATCH_MEM), line:79
|vpiName:USE_D_SCRATCH_MEM
|INT:3
|vpiParameter:
\_parameter: (USE_ICACHE), line:93
|vpiName:USE_ICACHE
|INT:7
|vpiParameter:
\_parameter: (USE_I_SCRATCH_MEM), line:78
|vpiName:USE_I_SCRATCH_MEM
|INT:2
|vpiParameter:
\_parameter: (USE_MUL), line:48
|vpiName:USE_MUL
|INT:1
|vpiParameter:
\_parameter: (WB_UNITS_WIDTH), line:187
|vpiName:WB_UNITS_WIDTH
|INT:32
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiParameter:
\_parameter: (i), line:79
|vpiName:i
|INT:4
|vpiGenScopeArray:
\_gen_scope_array: (branch_hit_detection[5]), line:79
|vpiName:branch_hit_detection[5]
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_hit_detection.branch_hit_detection[5]
|vpiGenScope:
\_gen_scope: , parent:branch_hit_detection[5]
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_hit_detection.branch_hit_detection[5]
|vpiContAssign:
\_cont_assign: , line:80
|vpiRhs:
\_operation: , line:80
|vpiOpType:14
|vpiOperand:
\_operation: , line:80
|vpiOpType:33
|vpiOperand:
\_bit_select: (if_entry.valid), line:80
|vpiName:if_entry.valid
|vpiIndex:
\_ref_obj: (i), line:80
|vpiName:i
|vpiOperand:
\_bit_select: (if_entry.tag), line:80
|vpiName:if_entry.tag
|vpiIndex:
\_ref_obj: (i), line:80
|vpiName:i
|vpiOperand:
\_operation: , line:80
|vpiOpType:33
|vpiOperand:
\_constant: , line:80
|vpiConstType:3
|vpiDecompile:'b1
|vpiSize:1
|BIN:1
|vpiOperand:
\_ref_obj: (bp.if_pc), line:80
|vpiName:bp.if_pc
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_hit_detection.branch_hit_detection[5].bp.if_pc
|vpiLhs:
\_bit_select: (tag_matches), line:80
|vpiName:tag_matches
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_hit_detection.branch_hit_detection[5].tag_matches
|vpiIndex:
\_ref_obj: (i), line:80
|vpiName:i
|vpiParameter:
\_parameter: (ALU_UNIT_WB_ID), line:190
|vpiName:ALU_UNIT_WB_ID
|INT:32
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (BRANCH_PREDICTOR_WAYS), line:159
|vpiName:BRANCH_PREDICTOR_WAYS
|INT:9
|vpiParameter:
\_parameter: (BRANCH_TABLE_ENTRIES), line:160
|vpiName:BRANCH_TABLE_ENTRIES
|INT:4
|vpiParameter:
\_parameter: (BRANCH_UNIT_ID), line:195
|vpiName:BRANCH_UNIT_ID
|INT:8
|vpiParameter:
\_parameter: (BUS_ADDR_H), line:107
|vpiName:BUS_ADDR_H
|INT:1
|vpiParameter:
\_parameter: (BUS_ADDR_L), line:106
|vpiName:BUS_ADDR_L
|INT:0
|vpiParameter:
\_parameter: (BUS_BIT_CHECK), line:108
|vpiName:BUS_BIT_CHECK
|INT:1
|vpiParameter:
\_parameter: (BUS_TYPE), line:89
|vpiName:BUS_TYPE
|INT:5
|vpiParameter:
\_parameter: (COUNTER_W), line:42
|vpiName:COUNTER_W
|INT:33
|vpiParameter:
\_parameter: (CPU_ID), line:38
|vpiName:CPU_ID
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_ADDR_WIDTH), line:113
|vpiName:C_M_AXI_ADDR_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_DATA_WIDTH), line:114
|vpiName:C_M_AXI_DATA_WIDTH
|INT:1
|vpiParameter:
\_parameter: (DCACHE_LINES), line:133
|vpiName:DCACHE_LINES
|INT:-2146435073
|vpiParameter:
\_parameter: (DCACHE_LINE_ADDR_W), line:135
|vpiName:DCACHE_LINE_ADDR_W
|INT:1073741824
|vpiParameter:
\_parameter: (DCACHE_LINE_W), line:136
|vpiName:DCACHE_LINE_W
|INT:1342177279
|vpiParameter:
\_parameter: (DCACHE_SUB_LINE_ADDR_W), line:137
|vpiName:DCACHE_SUB_LINE_ADDR_W
|INT:4
|vpiParameter:
\_parameter: (DCACHE_TAG_W), line:138
|vpiName:DCACHE_TAG_W
|INT:1610612736
|vpiParameter:
\_parameter: (DCACHE_WAYS), line:134
|vpiName:DCACHE_WAYS
|INT:4
|vpiParameter:
\_parameter: (DIV_ALGORITHM), line:67
|vpiName:DIV_ALGORITHM
|INT:0
|vpiParameter:
\_parameter: (DIV_UNIT_WB_ID), line:192
|vpiName:DIV_UNIT_WB_ID
|INT:2
|vpiParameter:
\_parameter: (DTLB_DEPTH), line:152
|vpiName:DTLB_DEPTH
|INT:512
|vpiParameter:
\_parameter: (DTLB_WAYS), line:151
|vpiName:DTLB_WAYS
|INT:32
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (ENABLE_M_MODE), line:34
|vpiName:ENABLE_M_MODE
|INT:1
|vpiParameter:
\_parameter: (ENABLE_S_MODE), line:36
|vpiName:ENABLE_S_MODE
|INT:0
|vpiParameter:
\_parameter: (ENABLE_TRACE_INTERFACE), line:172
|vpiName:ENABLE_TRACE_INTERFACE
|INT:2
|vpiParameter:
\_parameter: (FETCH_BUFFER_DEPTH), line:168
|vpiName:FETCH_BUFFER_DEPTH
|INT:512
|vpiParameter:
\_parameter: (FPGA_VENDOR), line:27
|vpiName:FPGA_VENDOR
|STRING:"xilinx"
|vpiParameter:
\_parameter: (GC_UNIT_ID), line:196
|vpiName:GC_UNIT_ID
|INT:4
|vpiParameter:
\_parameter: (ICACHE_LINES), line:121
|vpiName:ICACHE_LINES
|INT:2
|vpiParameter:
\_parameter: (ICACHE_LINE_ADDR_W), line:123
|vpiName:ICACHE_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_LINE_W), line:124
|vpiName:ICACHE_LINE_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_SUB_LINE_ADDR_W), line:125
|vpiName:ICACHE_SUB_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_TAG_W), line:126
|vpiName:ICACHE_TAG_W
|INT:-2147483648
|vpiParameter:
\_parameter: (ICACHE_WAYS), line:122
|vpiName:ICACHE_WAYS
|INT:1
|vpiParameter:
\_parameter: (ITLB_DEPTH), line:146
|vpiName:ITLB_DEPTH
|INT:32
|vpiParameter:
\_parameter: (ITLB_WAYS), line:145
|vpiName:ITLB_WAYS
|INT:4
|vpiParameter:
\_parameter: (L1_CONNECTIONS), line:177
|vpiName:L1_CONNECTIONS
|INT:9
|vpiParameter:
\_parameter: (L1_DCACHE_ID), line:178
|vpiName:L1_DCACHE_ID
|INT:4
|vpiParameter:
\_parameter: (L1_DMMU_ID), line:179
|vpiName:L1_DMMU_ID
|INT:2
|vpiParameter:
\_parameter: (L1_ICACHE_ID), line:180
|vpiName:L1_ICACHE_ID
|INT:19
|vpiParameter:
\_parameter: (L1_IMMU_ID), line:181
|vpiName:L1_IMMU_ID
|INT:0
|vpiParameter:
\_parameter: (LS_UNIT_WB_ID), line:191
|vpiName:LS_UNIT_WB_ID
|INT:1
|vpiParameter:
\_parameter: (MAX_INFLIGHT_COUNT), line:167
|vpiName:MAX_INFLIGHT_COUNT
|INT:19
|vpiParameter:
\_parameter: (MEMORY_ADDR_H), line:103
|vpiName:MEMORY_ADDR_H
|INT:12
|vpiParameter:
\_parameter: (MEMORY_ADDR_L), line:102
|vpiName:MEMORY_ADDR_L
|INT:11
|vpiParameter:
\_parameter: (MEMORY_BIT_CHECK), line:104
|vpiName:MEMORY_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (MUL_UNIT_WB_ID), line:193
|vpiName:MUL_UNIT_WB_ID
|INT:512
|vpiParameter:
\_parameter: (NUM_UNITS), line:188
|vpiName:NUM_UNITS
|INT:2
|vpiParameter:
\_parameter: (NUM_WB_UNITS), line:186
|vpiName:NUM_WB_UNITS
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (RAS_DEPTH), line:161
|vpiName:RAS_DEPTH
|INT:2
|vpiParameter:
\_parameter: (RESET_VEC), line:39
|vpiName:RESET_VEC
|INT:-2147483648
|vpiParameter:
\_parameter: (SCRATCH_ADDR_H), line:99
|vpiName:SCRATCH_ADDR_H
|INT:9
|vpiParameter:
\_parameter: (SCRATCH_ADDR_L), line:98
|vpiName:SCRATCH_ADDR_L
|INT:8
|vpiParameter:
\_parameter: (SCRATCH_BIT_CHECK), line:100
|vpiName:SCRATCH_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (USE_AMO), line:70
|vpiName:USE_AMO
|INT:1
|vpiParameter:
\_parameter: (USE_BRANCH_PREDICTOR), line:158
|vpiName:USE_BRANCH_PREDICTOR
|INT:2
|vpiParameter:
\_parameter: (USE_BUS), line:88
|vpiName:USE_BUS
|INT:4
|vpiParameter:
\_parameter: (USE_DCACHE), line:92
|vpiName:USE_DCACHE
|INT:6
|vpiParameter:
\_parameter: (USE_DIV), line:49
|vpiName:USE_DIV
|INT:1
|vpiParameter:
\_parameter: (USE_DTAG_INVALIDATIONS), line:140
|vpiName:USE_DTAG_INVALIDATIONS
|INT:1879048191
|vpiParameter:
\_parameter: (USE_D_SCRATCH_MEM), line:79
|vpiName:USE_D_SCRATCH_MEM
|INT:3
|vpiParameter:
\_parameter: (USE_ICACHE), line:93
|vpiName:USE_ICACHE
|INT:7
|vpiParameter:
\_parameter: (USE_I_SCRATCH_MEM), line:78
|vpiName:USE_I_SCRATCH_MEM
|INT:2
|vpiParameter:
\_parameter: (USE_MUL), line:48
|vpiName:USE_MUL
|INT:1
|vpiParameter:
\_parameter: (WB_UNITS_WIDTH), line:187
|vpiName:WB_UNITS_WIDTH
|INT:32
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiParameter:
\_parameter: (i), line:79
|vpiName:i
|INT:5
|vpiGenScopeArray:
\_gen_scope_array: (branch_hit_detection[6]), line:79
|vpiName:branch_hit_detection[6]
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_hit_detection.branch_hit_detection[6]
|vpiGenScope:
\_gen_scope: , parent:branch_hit_detection[6]
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_hit_detection.branch_hit_detection[6]
|vpiContAssign:
\_cont_assign: , line:80
|vpiRhs:
\_operation: , line:80
|vpiOpType:14
|vpiOperand:
\_operation: , line:80
|vpiOpType:33
|vpiOperand:
\_bit_select: (if_entry.valid), line:80
|vpiName:if_entry.valid
|vpiIndex:
\_ref_obj: (i), line:80
|vpiName:i
|vpiOperand:
\_bit_select: (if_entry.tag), line:80
|vpiName:if_entry.tag
|vpiIndex:
\_ref_obj: (i), line:80
|vpiName:i
|vpiOperand:
\_operation: , line:80
|vpiOpType:33
|vpiOperand:
\_constant: , line:80
|vpiConstType:3
|vpiDecompile:'b1
|vpiSize:1
|BIN:1
|vpiOperand:
\_ref_obj: (bp.if_pc), line:80
|vpiName:bp.if_pc
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_hit_detection.branch_hit_detection[6].bp.if_pc
|vpiLhs:
\_bit_select: (tag_matches), line:80
|vpiName:tag_matches
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_hit_detection.branch_hit_detection[6].tag_matches
|vpiIndex:
\_ref_obj: (i), line:80
|vpiName:i
|vpiParameter:
\_parameter: (ALU_UNIT_WB_ID), line:190
|vpiName:ALU_UNIT_WB_ID
|INT:32
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (BRANCH_PREDICTOR_WAYS), line:159
|vpiName:BRANCH_PREDICTOR_WAYS
|INT:9
|vpiParameter:
\_parameter: (BRANCH_TABLE_ENTRIES), line:160
|vpiName:BRANCH_TABLE_ENTRIES
|INT:4
|vpiParameter:
\_parameter: (BRANCH_UNIT_ID), line:195
|vpiName:BRANCH_UNIT_ID
|INT:8
|vpiParameter:
\_parameter: (BUS_ADDR_H), line:107
|vpiName:BUS_ADDR_H
|INT:1
|vpiParameter:
\_parameter: (BUS_ADDR_L), line:106
|vpiName:BUS_ADDR_L
|INT:0
|vpiParameter:
\_parameter: (BUS_BIT_CHECK), line:108
|vpiName:BUS_BIT_CHECK
|INT:1
|vpiParameter:
\_parameter: (BUS_TYPE), line:89
|vpiName:BUS_TYPE
|INT:5
|vpiParameter:
\_parameter: (COUNTER_W), line:42
|vpiName:COUNTER_W
|INT:33
|vpiParameter:
\_parameter: (CPU_ID), line:38
|vpiName:CPU_ID
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_ADDR_WIDTH), line:113
|vpiName:C_M_AXI_ADDR_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_DATA_WIDTH), line:114
|vpiName:C_M_AXI_DATA_WIDTH
|INT:1
|vpiParameter:
\_parameter: (DCACHE_LINES), line:133
|vpiName:DCACHE_LINES
|INT:-2146435073
|vpiParameter:
\_parameter: (DCACHE_LINE_ADDR_W), line:135
|vpiName:DCACHE_LINE_ADDR_W
|INT:1073741824
|vpiParameter:
\_parameter: (DCACHE_LINE_W), line:136
|vpiName:DCACHE_LINE_W
|INT:1342177279
|vpiParameter:
\_parameter: (DCACHE_SUB_LINE_ADDR_W), line:137
|vpiName:DCACHE_SUB_LINE_ADDR_W
|INT:4
|vpiParameter:
\_parameter: (DCACHE_TAG_W), line:138
|vpiName:DCACHE_TAG_W
|INT:1610612736
|vpiParameter:
\_parameter: (DCACHE_WAYS), line:134
|vpiName:DCACHE_WAYS
|INT:4
|vpiParameter:
\_parameter: (DIV_ALGORITHM), line:67
|vpiName:DIV_ALGORITHM
|INT:0
|vpiParameter:
\_parameter: (DIV_UNIT_WB_ID), line:192
|vpiName:DIV_UNIT_WB_ID
|INT:2
|vpiParameter:
\_parameter: (DTLB_DEPTH), line:152
|vpiName:DTLB_DEPTH
|INT:512
|vpiParameter:
\_parameter: (DTLB_WAYS), line:151
|vpiName:DTLB_WAYS
|INT:32
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (ENABLE_M_MODE), line:34
|vpiName:ENABLE_M_MODE
|INT:1
|vpiParameter:
\_parameter: (ENABLE_S_MODE), line:36
|vpiName:ENABLE_S_MODE
|INT:0
|vpiParameter:
\_parameter: (ENABLE_TRACE_INTERFACE), line:172
|vpiName:ENABLE_TRACE_INTERFACE
|INT:2
|vpiParameter:
\_parameter: (FETCH_BUFFER_DEPTH), line:168
|vpiName:FETCH_BUFFER_DEPTH
|INT:512
|vpiParameter:
\_parameter: (FPGA_VENDOR), line:27
|vpiName:FPGA_VENDOR
|STRING:"xilinx"
|vpiParameter:
\_parameter: (GC_UNIT_ID), line:196
|vpiName:GC_UNIT_ID
|INT:4
|vpiParameter:
\_parameter: (ICACHE_LINES), line:121
|vpiName:ICACHE_LINES
|INT:2
|vpiParameter:
\_parameter: (ICACHE_LINE_ADDR_W), line:123
|vpiName:ICACHE_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_LINE_W), line:124
|vpiName:ICACHE_LINE_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_SUB_LINE_ADDR_W), line:125
|vpiName:ICACHE_SUB_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_TAG_W), line:126
|vpiName:ICACHE_TAG_W
|INT:-2147483648
|vpiParameter:
\_parameter: (ICACHE_WAYS), line:122
|vpiName:ICACHE_WAYS
|INT:1
|vpiParameter:
\_parameter: (ITLB_DEPTH), line:146
|vpiName:ITLB_DEPTH
|INT:32
|vpiParameter:
\_parameter: (ITLB_WAYS), line:145
|vpiName:ITLB_WAYS
|INT:4
|vpiParameter:
\_parameter: (L1_CONNECTIONS), line:177
|vpiName:L1_CONNECTIONS
|INT:9
|vpiParameter:
\_parameter: (L1_DCACHE_ID), line:178
|vpiName:L1_DCACHE_ID
|INT:4
|vpiParameter:
\_parameter: (L1_DMMU_ID), line:179
|vpiName:L1_DMMU_ID
|INT:2
|vpiParameter:
\_parameter: (L1_ICACHE_ID), line:180
|vpiName:L1_ICACHE_ID
|INT:19
|vpiParameter:
\_parameter: (L1_IMMU_ID), line:181
|vpiName:L1_IMMU_ID
|INT:0
|vpiParameter:
\_parameter: (LS_UNIT_WB_ID), line:191
|vpiName:LS_UNIT_WB_ID
|INT:1
|vpiParameter:
\_parameter: (MAX_INFLIGHT_COUNT), line:167
|vpiName:MAX_INFLIGHT_COUNT
|INT:19
|vpiParameter:
\_parameter: (MEMORY_ADDR_H), line:103
|vpiName:MEMORY_ADDR_H
|INT:12
|vpiParameter:
\_parameter: (MEMORY_ADDR_L), line:102
|vpiName:MEMORY_ADDR_L
|INT:11
|vpiParameter:
\_parameter: (MEMORY_BIT_CHECK), line:104
|vpiName:MEMORY_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (MUL_UNIT_WB_ID), line:193
|vpiName:MUL_UNIT_WB_ID
|INT:512
|vpiParameter:
\_parameter: (NUM_UNITS), line:188
|vpiName:NUM_UNITS
|INT:2
|vpiParameter:
\_parameter: (NUM_WB_UNITS), line:186
|vpiName:NUM_WB_UNITS
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (RAS_DEPTH), line:161
|vpiName:RAS_DEPTH
|INT:2
|vpiParameter:
\_parameter: (RESET_VEC), line:39
|vpiName:RESET_VEC
|INT:-2147483648
|vpiParameter:
\_parameter: (SCRATCH_ADDR_H), line:99
|vpiName:SCRATCH_ADDR_H
|INT:9
|vpiParameter:
\_parameter: (SCRATCH_ADDR_L), line:98
|vpiName:SCRATCH_ADDR_L
|INT:8
|vpiParameter:
\_parameter: (SCRATCH_BIT_CHECK), line:100
|vpiName:SCRATCH_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (USE_AMO), line:70
|vpiName:USE_AMO
|INT:1
|vpiParameter:
\_parameter: (USE_BRANCH_PREDICTOR), line:158
|vpiName:USE_BRANCH_PREDICTOR
|INT:2
|vpiParameter:
\_parameter: (USE_BUS), line:88
|vpiName:USE_BUS
|INT:4
|vpiParameter:
\_parameter: (USE_DCACHE), line:92
|vpiName:USE_DCACHE
|INT:6
|vpiParameter:
\_parameter: (USE_DIV), line:49
|vpiName:USE_DIV
|INT:1
|vpiParameter:
\_parameter: (USE_DTAG_INVALIDATIONS), line:140
|vpiName:USE_DTAG_INVALIDATIONS
|INT:1879048191
|vpiParameter:
\_parameter: (USE_D_SCRATCH_MEM), line:79
|vpiName:USE_D_SCRATCH_MEM
|INT:3
|vpiParameter:
\_parameter: (USE_ICACHE), line:93
|vpiName:USE_ICACHE
|INT:7
|vpiParameter:
\_parameter: (USE_I_SCRATCH_MEM), line:78
|vpiName:USE_I_SCRATCH_MEM
|INT:2
|vpiParameter:
\_parameter: (USE_MUL), line:48
|vpiName:USE_MUL
|INT:1
|vpiParameter:
\_parameter: (WB_UNITS_WIDTH), line:187
|vpiName:WB_UNITS_WIDTH
|INT:32
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiParameter:
\_parameter: (i), line:79
|vpiName:i
|INT:6
|vpiGenScopeArray:
\_gen_scope_array: (branch_hit_detection[7]), line:79
|vpiName:branch_hit_detection[7]
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_hit_detection.branch_hit_detection[7]
|vpiGenScope:
\_gen_scope: , parent:branch_hit_detection[7]
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_hit_detection.branch_hit_detection[7]
|vpiContAssign:
\_cont_assign: , line:80
|vpiRhs:
\_operation: , line:80
|vpiOpType:14
|vpiOperand:
\_operation: , line:80
|vpiOpType:33
|vpiOperand:
\_bit_select: (if_entry.valid), line:80
|vpiName:if_entry.valid
|vpiIndex:
\_ref_obj: (i), line:80
|vpiName:i
|vpiOperand:
\_bit_select: (if_entry.tag), line:80
|vpiName:if_entry.tag
|vpiIndex:
\_ref_obj: (i), line:80
|vpiName:i
|vpiOperand:
\_operation: , line:80
|vpiOpType:33
|vpiOperand:
\_constant: , line:80
|vpiConstType:3
|vpiDecompile:'b1
|vpiSize:1
|BIN:1
|vpiOperand:
\_ref_obj: (bp.if_pc), line:80
|vpiName:bp.if_pc
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_hit_detection.branch_hit_detection[7].bp.if_pc
|vpiLhs:
\_bit_select: (tag_matches), line:80
|vpiName:tag_matches
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_hit_detection.branch_hit_detection[7].tag_matches
|vpiIndex:
\_ref_obj: (i), line:80
|vpiName:i
|vpiParameter:
\_parameter: (ALU_UNIT_WB_ID), line:190
|vpiName:ALU_UNIT_WB_ID
|INT:32
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (BRANCH_PREDICTOR_WAYS), line:159
|vpiName:BRANCH_PREDICTOR_WAYS
|INT:9
|vpiParameter:
\_parameter: (BRANCH_TABLE_ENTRIES), line:160
|vpiName:BRANCH_TABLE_ENTRIES
|INT:4
|vpiParameter:
\_parameter: (BRANCH_UNIT_ID), line:195
|vpiName:BRANCH_UNIT_ID
|INT:8
|vpiParameter:
\_parameter: (BUS_ADDR_H), line:107
|vpiName:BUS_ADDR_H
|INT:1
|vpiParameter:
\_parameter: (BUS_ADDR_L), line:106
|vpiName:BUS_ADDR_L
|INT:0
|vpiParameter:
\_parameter: (BUS_BIT_CHECK), line:108
|vpiName:BUS_BIT_CHECK
|INT:1
|vpiParameter:
\_parameter: (BUS_TYPE), line:89
|vpiName:BUS_TYPE
|INT:5
|vpiParameter:
\_parameter: (COUNTER_W), line:42
|vpiName:COUNTER_W
|INT:33
|vpiParameter:
\_parameter: (CPU_ID), line:38
|vpiName:CPU_ID
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_ADDR_WIDTH), line:113
|vpiName:C_M_AXI_ADDR_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_DATA_WIDTH), line:114
|vpiName:C_M_AXI_DATA_WIDTH
|INT:1
|vpiParameter:
\_parameter: (DCACHE_LINES), line:133
|vpiName:DCACHE_LINES
|INT:-2146435073
|vpiParameter:
\_parameter: (DCACHE_LINE_ADDR_W), line:135
|vpiName:DCACHE_LINE_ADDR_W
|INT:1073741824
|vpiParameter:
\_parameter: (DCACHE_LINE_W), line:136
|vpiName:DCACHE_LINE_W
|INT:1342177279
|vpiParameter:
\_parameter: (DCACHE_SUB_LINE_ADDR_W), line:137
|vpiName:DCACHE_SUB_LINE_ADDR_W
|INT:4
|vpiParameter:
\_parameter: (DCACHE_TAG_W), line:138
|vpiName:DCACHE_TAG_W
|INT:1610612736
|vpiParameter:
\_parameter: (DCACHE_WAYS), line:134
|vpiName:DCACHE_WAYS
|INT:4
|vpiParameter:
\_parameter: (DIV_ALGORITHM), line:67
|vpiName:DIV_ALGORITHM
|INT:0
|vpiParameter:
\_parameter: (DIV_UNIT_WB_ID), line:192
|vpiName:DIV_UNIT_WB_ID
|INT:2
|vpiParameter:
\_parameter: (DTLB_DEPTH), line:152
|vpiName:DTLB_DEPTH
|INT:512
|vpiParameter:
\_parameter: (DTLB_WAYS), line:151
|vpiName:DTLB_WAYS
|INT:32
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (ENABLE_M_MODE), line:34
|vpiName:ENABLE_M_MODE
|INT:1
|vpiParameter:
\_parameter: (ENABLE_S_MODE), line:36
|vpiName:ENABLE_S_MODE
|INT:0
|vpiParameter:
\_parameter: (ENABLE_TRACE_INTERFACE), line:172
|vpiName:ENABLE_TRACE_INTERFACE
|INT:2
|vpiParameter:
\_parameter: (FETCH_BUFFER_DEPTH), line:168
|vpiName:FETCH_BUFFER_DEPTH
|INT:512
|vpiParameter:
\_parameter: (FPGA_VENDOR), line:27
|vpiName:FPGA_VENDOR
|STRING:"xilinx"
|vpiParameter:
\_parameter: (GC_UNIT_ID), line:196
|vpiName:GC_UNIT_ID
|INT:4
|vpiParameter:
\_parameter: (ICACHE_LINES), line:121
|vpiName:ICACHE_LINES
|INT:2
|vpiParameter:
\_parameter: (ICACHE_LINE_ADDR_W), line:123
|vpiName:ICACHE_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_LINE_W), line:124
|vpiName:ICACHE_LINE_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_SUB_LINE_ADDR_W), line:125
|vpiName:ICACHE_SUB_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_TAG_W), line:126
|vpiName:ICACHE_TAG_W
|INT:-2147483648
|vpiParameter:
\_parameter: (ICACHE_WAYS), line:122
|vpiName:ICACHE_WAYS
|INT:1
|vpiParameter:
\_parameter: (ITLB_DEPTH), line:146
|vpiName:ITLB_DEPTH
|INT:32
|vpiParameter:
\_parameter: (ITLB_WAYS), line:145
|vpiName:ITLB_WAYS
|INT:4
|vpiParameter:
\_parameter: (L1_CONNECTIONS), line:177
|vpiName:L1_CONNECTIONS
|INT:9
|vpiParameter:
\_parameter: (L1_DCACHE_ID), line:178
|vpiName:L1_DCACHE_ID
|INT:4
|vpiParameter:
\_parameter: (L1_DMMU_ID), line:179
|vpiName:L1_DMMU_ID
|INT:2
|vpiParameter:
\_parameter: (L1_ICACHE_ID), line:180
|vpiName:L1_ICACHE_ID
|INT:19
|vpiParameter:
\_parameter: (L1_IMMU_ID), line:181
|vpiName:L1_IMMU_ID
|INT:0
|vpiParameter:
\_parameter: (LS_UNIT_WB_ID), line:191
|vpiName:LS_UNIT_WB_ID
|INT:1
|vpiParameter:
\_parameter: (MAX_INFLIGHT_COUNT), line:167
|vpiName:MAX_INFLIGHT_COUNT
|INT:19
|vpiParameter:
\_parameter: (MEMORY_ADDR_H), line:103
|vpiName:MEMORY_ADDR_H
|INT:12
|vpiParameter:
\_parameter: (MEMORY_ADDR_L), line:102
|vpiName:MEMORY_ADDR_L
|INT:11
|vpiParameter:
\_parameter: (MEMORY_BIT_CHECK), line:104
|vpiName:MEMORY_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (MUL_UNIT_WB_ID), line:193
|vpiName:MUL_UNIT_WB_ID
|INT:512
|vpiParameter:
\_parameter: (NUM_UNITS), line:188
|vpiName:NUM_UNITS
|INT:2
|vpiParameter:
\_parameter: (NUM_WB_UNITS), line:186
|vpiName:NUM_WB_UNITS
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (RAS_DEPTH), line:161
|vpiName:RAS_DEPTH
|INT:2
|vpiParameter:
\_parameter: (RESET_VEC), line:39
|vpiName:RESET_VEC
|INT:-2147483648
|vpiParameter:
\_parameter: (SCRATCH_ADDR_H), line:99
|vpiName:SCRATCH_ADDR_H
|INT:9
|vpiParameter:
\_parameter: (SCRATCH_ADDR_L), line:98
|vpiName:SCRATCH_ADDR_L
|INT:8
|vpiParameter:
\_parameter: (SCRATCH_BIT_CHECK), line:100
|vpiName:SCRATCH_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (USE_AMO), line:70
|vpiName:USE_AMO
|INT:1
|vpiParameter:
\_parameter: (USE_BRANCH_PREDICTOR), line:158
|vpiName:USE_BRANCH_PREDICTOR
|INT:2
|vpiParameter:
\_parameter: (USE_BUS), line:88
|vpiName:USE_BUS
|INT:4
|vpiParameter:
\_parameter: (USE_DCACHE), line:92
|vpiName:USE_DCACHE
|INT:6
|vpiParameter:
\_parameter: (USE_DIV), line:49
|vpiName:USE_DIV
|INT:1
|vpiParameter:
\_parameter: (USE_DTAG_INVALIDATIONS), line:140
|vpiName:USE_DTAG_INVALIDATIONS
|INT:1879048191
|vpiParameter:
\_parameter: (USE_D_SCRATCH_MEM), line:79
|vpiName:USE_D_SCRATCH_MEM
|INT:3
|vpiParameter:
\_parameter: (USE_ICACHE), line:93
|vpiName:USE_ICACHE
|INT:7
|vpiParameter:
\_parameter: (USE_I_SCRATCH_MEM), line:78
|vpiName:USE_I_SCRATCH_MEM
|INT:2
|vpiParameter:
\_parameter: (USE_MUL), line:48
|vpiName:USE_MUL
|INT:1
|vpiParameter:
\_parameter: (WB_UNITS_WIDTH), line:187
|vpiName:WB_UNITS_WIDTH
|INT:32
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiParameter:
\_parameter: (i), line:79
|vpiName:i
|INT:7
|vpiGenScopeArray:
\_gen_scope_array: (branch_hit_detection[8]), line:79
|vpiName:branch_hit_detection[8]
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_hit_detection.branch_hit_detection[8]
|vpiGenScope:
\_gen_scope: , parent:branch_hit_detection[8]
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_hit_detection.branch_hit_detection[8]
|vpiContAssign:
\_cont_assign: , line:80
|vpiRhs:
\_operation: , line:80
|vpiOpType:14
|vpiOperand:
\_operation: , line:80
|vpiOpType:33
|vpiOperand:
\_bit_select: (if_entry.valid), line:80
|vpiName:if_entry.valid
|vpiIndex:
\_ref_obj: (i), line:80
|vpiName:i
|vpiOperand:
\_bit_select: (if_entry.tag), line:80
|vpiName:if_entry.tag
|vpiIndex:
\_ref_obj: (i), line:80
|vpiName:i
|vpiOperand:
\_operation: , line:80
|vpiOpType:33
|vpiOperand:
\_constant: , line:80
|vpiConstType:3
|vpiDecompile:'b1
|vpiSize:1
|BIN:1
|vpiOperand:
\_ref_obj: (bp.if_pc), line:80
|vpiName:bp.if_pc
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_hit_detection.branch_hit_detection[8].bp.if_pc
|vpiLhs:
\_bit_select: (tag_matches), line:80
|vpiName:tag_matches
|vpiFullName:work@taiga_wrapper.cpu.bp_block.branch_hit_detection.branch_hit_detection[8].tag_matches
|vpiIndex:
\_ref_obj: (i), line:80
|vpiName:i
|vpiParameter:
\_parameter: (ALU_UNIT_WB_ID), line:190
|vpiName:ALU_UNIT_WB_ID
|INT:32
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (BRANCH_PREDICTOR_WAYS), line:159
|vpiName:BRANCH_PREDICTOR_WAYS
|INT:9
|vpiParameter:
\_parameter: (BRANCH_TABLE_ENTRIES), line:160
|vpiName:BRANCH_TABLE_ENTRIES
|INT:4
|vpiParameter:
\_parameter: (BRANCH_UNIT_ID), line:195
|vpiName:BRANCH_UNIT_ID
|INT:8
|vpiParameter:
\_parameter: (BUS_ADDR_H), line:107
|vpiName:BUS_ADDR_H
|INT:1
|vpiParameter:
\_parameter: (BUS_ADDR_L), line:106
|vpiName:BUS_ADDR_L
|INT:0
|vpiParameter:
\_parameter: (BUS_BIT_CHECK), line:108
|vpiName:BUS_BIT_CHECK
|INT:1
|vpiParameter:
\_parameter: (BUS_TYPE), line:89
|vpiName:BUS_TYPE
|INT:5
|vpiParameter:
\_parameter: (COUNTER_W), line:42
|vpiName:COUNTER_W
|INT:33
|vpiParameter:
\_parameter: (CPU_ID), line:38
|vpiName:CPU_ID
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_ADDR_WIDTH), line:113
|vpiName:C_M_AXI_ADDR_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_DATA_WIDTH), line:114
|vpiName:C_M_AXI_DATA_WIDTH
|INT:1
|vpiParameter:
\_parameter: (DCACHE_LINES), line:133
|vpiName:DCACHE_LINES
|INT:-2146435073
|vpiParameter:
\_parameter: (DCACHE_LINE_ADDR_W), line:135
|vpiName:DCACHE_LINE_ADDR_W
|INT:1073741824
|vpiParameter:
\_parameter: (DCACHE_LINE_W), line:136
|vpiName:DCACHE_LINE_W
|INT:1342177279
|vpiParameter:
\_parameter: (DCACHE_SUB_LINE_ADDR_W), line:137
|vpiName:DCACHE_SUB_LINE_ADDR_W
|INT:4
|vpiParameter:
\_parameter: (DCACHE_TAG_W), line:138
|vpiName:DCACHE_TAG_W
|INT:1610612736
|vpiParameter:
\_parameter: (DCACHE_WAYS), line:134
|vpiName:DCACHE_WAYS
|INT:4
|vpiParameter:
\_parameter: (DIV_ALGORITHM), line:67
|vpiName:DIV_ALGORITHM
|INT:0
|vpiParameter:
\_parameter: (DIV_UNIT_WB_ID), line:192
|vpiName:DIV_UNIT_WB_ID
|INT:2
|vpiParameter:
\_parameter: (DTLB_DEPTH), line:152
|vpiName:DTLB_DEPTH
|INT:512
|vpiParameter:
\_parameter: (DTLB_WAYS), line:151
|vpiName:DTLB_WAYS
|INT:32
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (ENABLE_M_MODE), line:34
|vpiName:ENABLE_M_MODE
|INT:1
|vpiParameter:
\_parameter: (ENABLE_S_MODE), line:36
|vpiName:ENABLE_S_MODE
|INT:0
|vpiParameter:
\_parameter: (ENABLE_TRACE_INTERFACE), line:172
|vpiName:ENABLE_TRACE_INTERFACE
|INT:2
|vpiParameter:
\_parameter: (FETCH_BUFFER_DEPTH), line:168
|vpiName:FETCH_BUFFER_DEPTH
|INT:512
|vpiParameter:
\_parameter: (FPGA_VENDOR), line:27
|vpiName:FPGA_VENDOR
|STRING:"xilinx"
|vpiParameter:
\_parameter: (GC_UNIT_ID), line:196
|vpiName:GC_UNIT_ID
|INT:4
|vpiParameter:
\_parameter: (ICACHE_LINES), line:121
|vpiName:ICACHE_LINES
|INT:2
|vpiParameter:
\_parameter: (ICACHE_LINE_ADDR_W), line:123
|vpiName:ICACHE_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_LINE_W), line:124
|vpiName:ICACHE_LINE_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_SUB_LINE_ADDR_W), line:125
|vpiName:ICACHE_SUB_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_TAG_W), line:126
|vpiName:ICACHE_TAG_W
|INT:-2147483648
|vpiParameter:
\_parameter: (ICACHE_WAYS), line:122
|vpiName:ICACHE_WAYS
|INT:1
|vpiParameter:
\_parameter: (ITLB_DEPTH), line:146
|vpiName:ITLB_DEPTH
|INT:32
|vpiParameter:
\_parameter: (ITLB_WAYS), line:145
|vpiName:ITLB_WAYS
|INT:4
|vpiParameter:
\_parameter: (L1_CONNECTIONS), line:177
|vpiName:L1_CONNECTIONS
|INT:9
|vpiParameter:
\_parameter: (L1_DCACHE_ID), line:178
|vpiName:L1_DCACHE_ID
|INT:4
|vpiParameter:
\_parameter: (L1_DMMU_ID), line:179
|vpiName:L1_DMMU_ID
|INT:2
|vpiParameter:
\_parameter: (L1_ICACHE_ID), line:180
|vpiName:L1_ICACHE_ID
|INT:19
|vpiParameter:
\_parameter: (L1_IMMU_ID), line:181
|vpiName:L1_IMMU_ID
|INT:0
|vpiParameter:
\_parameter: (LS_UNIT_WB_ID), line:191
|vpiName:LS_UNIT_WB_ID
|INT:1
|vpiParameter:
\_parameter: (MAX_INFLIGHT_COUNT), line:167
|vpiName:MAX_INFLIGHT_COUNT
|INT:19
|vpiParameter:
\_parameter: (MEMORY_ADDR_H), line:103
|vpiName:MEMORY_ADDR_H
|INT:12
|vpiParameter:
\_parameter: (MEMORY_ADDR_L), line:102
|vpiName:MEMORY_ADDR_L
|INT:11
|vpiParameter:
\_parameter: (MEMORY_BIT_CHECK), line:104
|vpiName:MEMORY_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (MUL_UNIT_WB_ID), line:193
|vpiName:MUL_UNIT_WB_ID
|INT:512
|vpiParameter:
\_parameter: (NUM_UNITS), line:188
|vpiName:NUM_UNITS
|INT:2
|vpiParameter:
\_parameter: (NUM_WB_UNITS), line:186
|vpiName:NUM_WB_UNITS
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (RAS_DEPTH), line:161
|vpiName:RAS_DEPTH
|INT:2
|vpiParameter:
\_parameter: (RESET_VEC), line:39
|vpiName:RESET_VEC
|INT:-2147483648
|vpiParameter:
\_parameter: (SCRATCH_ADDR_H), line:99
|vpiName:SCRATCH_ADDR_H
|INT:9
|vpiParameter:
\_parameter: (SCRATCH_ADDR_L), line:98
|vpiName:SCRATCH_ADDR_L
|INT:8
|vpiParameter:
\_parameter: (SCRATCH_BIT_CHECK), line:100
|vpiName:SCRATCH_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (USE_AMO), line:70
|vpiName:USE_AMO
|INT:1
|vpiParameter:
\_parameter: (USE_BRANCH_PREDICTOR), line:158
|vpiName:USE_BRANCH_PREDICTOR
|INT:2
|vpiParameter:
\_parameter: (USE_BUS), line:88
|vpiName:USE_BUS
|INT:4
|vpiParameter:
\_parameter: (USE_DCACHE), line:92
|vpiName:USE_DCACHE
|INT:6
|vpiParameter:
\_parameter: (USE_DIV), line:49
|vpiName:USE_DIV
|INT:1
|vpiParameter:
\_parameter: (USE_DTAG_INVALIDATIONS), line:140
|vpiName:USE_DTAG_INVALIDATIONS
|INT:1879048191
|vpiParameter:
\_parameter: (USE_D_SCRATCH_MEM), line:79
|vpiName:USE_D_SCRATCH_MEM
|INT:3
|vpiParameter:
\_parameter: (USE_ICACHE), line:93
|vpiName:USE_ICACHE
|INT:7
|vpiParameter:
\_parameter: (USE_I_SCRATCH_MEM), line:78
|vpiName:USE_I_SCRATCH_MEM
|INT:2
|vpiParameter:
\_parameter: (USE_MUL), line:48
|vpiName:USE_MUL
|INT:1
|vpiParameter:
\_parameter: (WB_UNITS_WIDTH), line:187
|vpiName:WB_UNITS_WIDTH
|INT:32
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiParameter:
\_parameter: (i), line:79
|vpiName:i
|INT:8
|vpiParameter:
\_parameter: (ALU_UNIT_WB_ID), line:190
|vpiName:ALU_UNIT_WB_ID
|INT:32
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (BRANCH_PREDICTOR_WAYS), line:159
|vpiName:BRANCH_PREDICTOR_WAYS
|INT:9
|vpiParameter:
\_parameter: (BRANCH_TABLE_ENTRIES), line:160
|vpiName:BRANCH_TABLE_ENTRIES
|INT:4
|vpiParameter:
\_parameter: (BRANCH_UNIT_ID), line:195
|vpiName:BRANCH_UNIT_ID
|INT:8
|vpiParameter:
\_parameter: (BUS_ADDR_H), line:107
|vpiName:BUS_ADDR_H
|INT:1
|vpiParameter:
\_parameter: (BUS_ADDR_L), line:106
|vpiName:BUS_ADDR_L
|INT:0
|vpiParameter:
\_parameter: (BUS_BIT_CHECK), line:108
|vpiName:BUS_BIT_CHECK
|INT:1
|vpiParameter:
\_parameter: (BUS_TYPE), line:89
|vpiName:BUS_TYPE
|INT:5
|vpiParameter:
\_parameter: (COUNTER_W), line:42
|vpiName:COUNTER_W
|INT:33
|vpiParameter:
\_parameter: (CPU_ID), line:38
|vpiName:CPU_ID
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_ADDR_WIDTH), line:113
|vpiName:C_M_AXI_ADDR_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_DATA_WIDTH), line:114
|vpiName:C_M_AXI_DATA_WIDTH
|INT:1
|vpiParameter:
\_parameter: (DCACHE_LINES), line:133
|vpiName:DCACHE_LINES
|INT:-2146435073
|vpiParameter:
\_parameter: (DCACHE_LINE_ADDR_W), line:135
|vpiName:DCACHE_LINE_ADDR_W
|INT:1073741824
|vpiParameter:
\_parameter: (DCACHE_LINE_W), line:136
|vpiName:DCACHE_LINE_W
|INT:1342177279
|vpiParameter:
\_parameter: (DCACHE_SUB_LINE_ADDR_W), line:137
|vpiName:DCACHE_SUB_LINE_ADDR_W
|INT:4
|vpiParameter:
\_parameter: (DCACHE_TAG_W), line:138
|vpiName:DCACHE_TAG_W
|INT:1610612736
|vpiParameter:
\_parameter: (DCACHE_WAYS), line:134
|vpiName:DCACHE_WAYS
|INT:4
|vpiParameter:
\_parameter: (DIV_ALGORITHM), line:67
|vpiName:DIV_ALGORITHM
|INT:0
|vpiParameter:
\_parameter: (DIV_UNIT_WB_ID), line:192
|vpiName:DIV_UNIT_WB_ID
|INT:2
|vpiParameter:
\_parameter: (DTLB_DEPTH), line:152
|vpiName:DTLB_DEPTH
|INT:512
|vpiParameter:
\_parameter: (DTLB_WAYS), line:151
|vpiName:DTLB_WAYS
|INT:32
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (ENABLE_M_MODE), line:34
|vpiName:ENABLE_M_MODE
|INT:1
|vpiParameter:
\_parameter: (ENABLE_S_MODE), line:36
|vpiName:ENABLE_S_MODE
|INT:0
|vpiParameter:
\_parameter: (ENABLE_TRACE_INTERFACE), line:172
|vpiName:ENABLE_TRACE_INTERFACE
|INT:2
|vpiParameter:
\_parameter: (FETCH_BUFFER_DEPTH), line:168
|vpiName:FETCH_BUFFER_DEPTH
|INT:512
|vpiParameter:
\_parameter: (FPGA_VENDOR), line:27
|vpiName:FPGA_VENDOR
|STRING:"xilinx"
|vpiParameter:
\_parameter: (GC_UNIT_ID), line:196
|vpiName:GC_UNIT_ID
|INT:4
|vpiParameter:
\_parameter: (ICACHE_LINES), line:121
|vpiName:ICACHE_LINES
|INT:2
|vpiParameter:
\_parameter: (ICACHE_LINE_ADDR_W), line:123
|vpiName:ICACHE_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_LINE_W), line:124
|vpiName:ICACHE_LINE_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_SUB_LINE_ADDR_W), line:125
|vpiName:ICACHE_SUB_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_TAG_W), line:126
|vpiName:ICACHE_TAG_W
|INT:-2147483648
|vpiParameter:
\_parameter: (ICACHE_WAYS), line:122
|vpiName:ICACHE_WAYS
|INT:1
|vpiParameter:
\_parameter: (ITLB_DEPTH), line:146
|vpiName:ITLB_DEPTH
|INT:32
|vpiParameter:
\_parameter: (ITLB_WAYS), line:145
|vpiName:ITLB_WAYS
|INT:4
|vpiParameter:
\_parameter: (L1_CONNECTIONS), line:177
|vpiName:L1_CONNECTIONS
|INT:9
|vpiParameter:
\_parameter: (L1_DCACHE_ID), line:178
|vpiName:L1_DCACHE_ID
|INT:4
|vpiParameter:
\_parameter: (L1_DMMU_ID), line:179
|vpiName:L1_DMMU_ID
|INT:2
|vpiParameter:
\_parameter: (L1_ICACHE_ID), line:180
|vpiName:L1_ICACHE_ID
|INT:19
|vpiParameter:
\_parameter: (L1_IMMU_ID), line:181
|vpiName:L1_IMMU_ID
|INT:0
|vpiParameter:
\_parameter: (LS_UNIT_WB_ID), line:191
|vpiName:LS_UNIT_WB_ID
|INT:1
|vpiParameter:
\_parameter: (MAX_INFLIGHT_COUNT), line:167
|vpiName:MAX_INFLIGHT_COUNT
|INT:19
|vpiParameter:
\_parameter: (MEMORY_ADDR_H), line:103
|vpiName:MEMORY_ADDR_H
|INT:12
|vpiParameter:
\_parameter: (MEMORY_ADDR_L), line:102
|vpiName:MEMORY_ADDR_L
|INT:11
|vpiParameter:
\_parameter: (MEMORY_BIT_CHECK), line:104
|vpiName:MEMORY_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (MUL_UNIT_WB_ID), line:193
|vpiName:MUL_UNIT_WB_ID
|INT:512
|vpiParameter:
\_parameter: (NUM_UNITS), line:188
|vpiName:NUM_UNITS
|INT:2
|vpiParameter:
\_parameter: (NUM_WB_UNITS), line:186
|vpiName:NUM_WB_UNITS
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (RAS_DEPTH), line:161
|vpiName:RAS_DEPTH
|INT:2
|vpiParameter:
\_parameter: (RESET_VEC), line:39
|vpiName:RESET_VEC
|INT:-2147483648
|vpiParameter:
\_parameter: (SCRATCH_ADDR_H), line:99
|vpiName:SCRATCH_ADDR_H
|INT:9
|vpiParameter:
\_parameter: (SCRATCH_ADDR_L), line:98
|vpiName:SCRATCH_ADDR_L
|INT:8
|vpiParameter:
\_parameter: (SCRATCH_BIT_CHECK), line:100
|vpiName:SCRATCH_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (USE_AMO), line:70
|vpiName:USE_AMO
|INT:1
|vpiParameter:
\_parameter: (USE_BRANCH_PREDICTOR), line:158
|vpiName:USE_BRANCH_PREDICTOR
|INT:2
|vpiParameter:
\_parameter: (USE_BUS), line:88
|vpiName:USE_BUS
|INT:4
|vpiParameter:
\_parameter: (USE_DCACHE), line:92
|vpiName:USE_DCACHE
|INT:6
|vpiParameter:
\_parameter: (USE_DIV), line:49
|vpiName:USE_DIV
|INT:1
|vpiParameter:
\_parameter: (USE_DTAG_INVALIDATIONS), line:140
|vpiName:USE_DTAG_INVALIDATIONS
|INT:1879048191
|vpiParameter:
\_parameter: (USE_D_SCRATCH_MEM), line:79
|vpiName:USE_D_SCRATCH_MEM
|INT:3
|vpiParameter:
\_parameter: (USE_ICACHE), line:93
|vpiName:USE_ICACHE
|INT:7
|vpiParameter:
\_parameter: (USE_I_SCRATCH_MEM), line:78
|vpiName:USE_I_SCRATCH_MEM
|INT:2
|vpiParameter:
\_parameter: (USE_MUL), line:48
|vpiName:USE_MUL
|INT:1
|vpiParameter:
\_parameter: (WB_UNITS_WIDTH), line:187
|vpiName:WB_UNITS_WIDTH
|INT:32
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiGenScopeArray:
\_gen_scope_array: (genblk1), line:84, parent:bp_block
|vpiName:genblk1
|vpiFullName:work@taiga_wrapper.cpu.bp_block.genblk1
|vpiGenScope:
\_gen_scope: , parent:genblk1
|vpiFullName:work@taiga_wrapper.cpu.bp_block.genblk1
|vpiContAssign:
\_cont_assign: , line:87
|vpiRhs:
\_constant: , line:87
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiLhs:
\_ref_obj: (hit_way), line:87
|vpiName:hit_way
|vpiFullName:work@taiga_wrapper.cpu.bp_block.genblk1.hit_way
|vpiModule:
\_module: work@one_hot_to_integer (hit_way_conv), file:third_party/cores/taiga/core/branch_predictor.sv, line:85
|vpiDefName:work@one_hot_to_integer
|vpiName:hit_way_conv
|vpiFullName:work@taiga_wrapper.cpu.bp_block.genblk1.hit_way_conv
|vpiPort:
\_port: (clk), line:31, parent:hit_way_conv
|vpiName:clk
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (clk), line:85
|vpiName:clk
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (clk), line:31, parent:hit_way_conv
|vpiName:clk
|vpiFullName:work@taiga_wrapper.cpu.bp_block.genblk1.hit_way_conv.clk
|vpiNetType:36
|vpiPort:
\_port: (rst), line:32, parent:hit_way_conv
|vpiName:rst
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (rst), line:85
|vpiName:rst
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (rst), line:32, parent:hit_way_conv
|vpiName:rst
|vpiFullName:work@taiga_wrapper.cpu.bp_block.genblk1.hit_way_conv.rst
|vpiNetType:36
|vpiPort:
\_port: (one_hot), line:33, parent:hit_way_conv
|vpiName:one_hot
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (one_hot), line:85
|vpiName:one_hot
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (one_hot), line:33, parent:hit_way_conv
|vpiName:one_hot
|vpiFullName:work@taiga_wrapper.cpu.bp_block.genblk1.hit_way_conv.one_hot
|vpiNetType:36
|vpiRange:
\_range: , line:33
|vpiLeftRange:
\_constant: , line:33
|vpiConstType:7
|vpiDecompile:8
|vpiSize:32
|INT:8
|vpiRightRange:
\_constant: , line:33
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiPort:
\_port: (int_out), line:34, parent:hit_way_conv
|vpiName:int_out
|vpiDirection:2
|vpiHighConn:
\_ref_obj: (int_out), line:85
|vpiName:int_out
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (int_out), line:34, parent:hit_way_conv
|vpiName:int_out
|vpiFullName:work@taiga_wrapper.cpu.bp_block.genblk1.hit_way_conv.int_out
|vpiNetType:36
|vpiRange:
\_range: , line:34
|vpiLeftRange:
\_constant: , line:34
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiRightRange:
\_constant: , line:34
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiGenScopeArray:
\_gen_scope_array: (genblk1), line:40, parent:hit_way_conv
|vpiName:genblk1
|vpiFullName:work@taiga_wrapper.cpu.bp_block.genblk1.hit_way_conv.genblk1
|vpiGenScope:
\_gen_scope: , parent:genblk1
|vpiFullName:work@taiga_wrapper.cpu.bp_block.genblk1.hit_way_conv.genblk1
|vpiProcess:
\_always: , line:41
|vpiAlwaysType:2
|vpiStmt:
\_begin: , line:41
|vpiFullName:work@taiga_wrapper.cpu.bp_block.genblk1.hit_way_conv.genblk1
|vpiStmt:
\_assignment: , line:42
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (int_out), line:42
|vpiName:int_out
|vpiFullName:work@taiga_wrapper.cpu.bp_block.genblk1.hit_way_conv.genblk1.int_out
|vpiRhs:
\_constant: , line:42
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiStmt:
\_foreach_stmt: , line:43
|vpiFullName:work@taiga_wrapper.cpu.bp_block.genblk1.hit_way_conv.genblk1
|vpiVariables:
\_chandle_var: (one_hot), line:43
|vpiName:one_hot
|vpiFullName:work@taiga_wrapper.cpu.bp_block.genblk1.hit_way_conv.genblk1.one_hot
|vpiLoopVars:
\_chandle_var: (i), line:43
|vpiName:i
|vpiFullName:work@taiga_wrapper.cpu.bp_block.genblk1.hit_way_conv.genblk1.i
|vpiStmt:
\_if_stmt: , line:44
|vpiCondition:
\_bit_select: (one_hot), line:44
|vpiName:one_hot
|vpiFullName:work@taiga_wrapper.cpu.bp_block.genblk1.hit_way_conv.genblk1.one_hot
|vpiIndex:
\_ref_obj: (i), line:44
|vpiName:i
|vpiStmt:
\_assignment: , line:44
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (int_out), line:44
|vpiName:int_out
|vpiFullName:work@taiga_wrapper.cpu.bp_block.genblk1.hit_way_conv.genblk1.int_out
|vpiRhs:
\_part_select: , line:44, parent:i
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (i)
|vpiLeftRange:
\_operation: , line:44
|vpiOpType:11
|vpiOperand:
\_sys_func_call: ($clog2), line:44
|vpiName:$clog2
|vpiArgument:
\_ref_obj: (C_WIDTH), line:44
|vpiName:C_WIDTH
|vpiOperand:
\_constant: , line:44
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:44
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (clk), line:31, parent:hit_way_conv
|vpiNet:
\_logic_net: (rst), line:32, parent:hit_way_conv
|vpiNet:
\_logic_net: (one_hot), line:33, parent:hit_way_conv
|vpiNet:
\_logic_net: (int_out), line:34, parent:hit_way_conv
|vpiParameter:
\_parameter: (C_WIDTH), line:85
|vpiName:C_WIDTH
|INT:9
|vpiParameter:
\_parameter: (ALU_UNIT_WB_ID), line:190
|vpiName:ALU_UNIT_WB_ID
|INT:32
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (BRANCH_PREDICTOR_WAYS), line:159
|vpiName:BRANCH_PREDICTOR_WAYS
|INT:9
|vpiParameter:
\_parameter: (BRANCH_TABLE_ENTRIES), line:160
|vpiName:BRANCH_TABLE_ENTRIES
|INT:4
|vpiParameter:
\_parameter: (BRANCH_UNIT_ID), line:195
|vpiName:BRANCH_UNIT_ID
|INT:8
|vpiParameter:
\_parameter: (BUS_ADDR_H), line:107
|vpiName:BUS_ADDR_H
|INT:1
|vpiParameter:
\_parameter: (BUS_ADDR_L), line:106
|vpiName:BUS_ADDR_L
|INT:0
|vpiParameter:
\_parameter: (BUS_BIT_CHECK), line:108
|vpiName:BUS_BIT_CHECK
|INT:1
|vpiParameter:
\_parameter: (BUS_TYPE), line:89
|vpiName:BUS_TYPE
|INT:5
|vpiParameter:
\_parameter: (COUNTER_W), line:42
|vpiName:COUNTER_W
|INT:33
|vpiParameter:
\_parameter: (CPU_ID), line:38
|vpiName:CPU_ID
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_ADDR_WIDTH), line:113
|vpiName:C_M_AXI_ADDR_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_DATA_WIDTH), line:114
|vpiName:C_M_AXI_DATA_WIDTH
|INT:1
|vpiParameter:
\_parameter: (DCACHE_LINES), line:133
|vpiName:DCACHE_LINES
|INT:-2146435073
|vpiParameter:
\_parameter: (DCACHE_LINE_ADDR_W), line:135
|vpiName:DCACHE_LINE_ADDR_W
|INT:1073741824
|vpiParameter:
\_parameter: (DCACHE_LINE_W), line:136
|vpiName:DCACHE_LINE_W
|INT:1342177279
|vpiParameter:
\_parameter: (DCACHE_SUB_LINE_ADDR_W), line:137
|vpiName:DCACHE_SUB_LINE_ADDR_W
|INT:4
|vpiParameter:
\_parameter: (DCACHE_TAG_W), line:138
|vpiName:DCACHE_TAG_W
|INT:1610612736
|vpiParameter:
\_parameter: (DCACHE_WAYS), line:134
|vpiName:DCACHE_WAYS
|INT:4
|vpiParameter:
\_parameter: (DIV_ALGORITHM), line:67
|vpiName:DIV_ALGORITHM
|INT:0
|vpiParameter:
\_parameter: (DIV_UNIT_WB_ID), line:192
|vpiName:DIV_UNIT_WB_ID
|INT:2
|vpiParameter:
\_parameter: (DTLB_DEPTH), line:152
|vpiName:DTLB_DEPTH
|INT:512
|vpiParameter:
\_parameter: (DTLB_WAYS), line:151
|vpiName:DTLB_WAYS
|INT:32
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (ENABLE_M_MODE), line:34
|vpiName:ENABLE_M_MODE
|INT:1
|vpiParameter:
\_parameter: (ENABLE_S_MODE), line:36
|vpiName:ENABLE_S_MODE
|INT:0
|vpiParameter:
\_parameter: (ENABLE_TRACE_INTERFACE), line:172
|vpiName:ENABLE_TRACE_INTERFACE
|INT:2
|vpiParameter:
\_parameter: (FETCH_BUFFER_DEPTH), line:168
|vpiName:FETCH_BUFFER_DEPTH
|INT:512
|vpiParameter:
\_parameter: (FPGA_VENDOR), line:27
|vpiName:FPGA_VENDOR
|STRING:"xilinx"
|vpiParameter:
\_parameter: (GC_UNIT_ID), line:196
|vpiName:GC_UNIT_ID
|INT:4
|vpiParameter:
\_parameter: (ICACHE_LINES), line:121
|vpiName:ICACHE_LINES
|INT:2
|vpiParameter:
\_parameter: (ICACHE_LINE_ADDR_W), line:123
|vpiName:ICACHE_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_LINE_W), line:124
|vpiName:ICACHE_LINE_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_SUB_LINE_ADDR_W), line:125
|vpiName:ICACHE_SUB_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_TAG_W), line:126
|vpiName:ICACHE_TAG_W
|INT:-2147483648
|vpiParameter:
\_parameter: (ICACHE_WAYS), line:122
|vpiName:ICACHE_WAYS
|INT:1
|vpiParameter:
\_parameter: (ITLB_DEPTH), line:146
|vpiName:ITLB_DEPTH
|INT:32
|vpiParameter:
\_parameter: (ITLB_WAYS), line:145
|vpiName:ITLB_WAYS
|INT:4
|vpiParameter:
\_parameter: (L1_CONNECTIONS), line:177
|vpiName:L1_CONNECTIONS
|INT:9
|vpiParameter:
\_parameter: (L1_DCACHE_ID), line:178
|vpiName:L1_DCACHE_ID
|INT:4
|vpiParameter:
\_parameter: (L1_DMMU_ID), line:179
|vpiName:L1_DMMU_ID
|INT:2
|vpiParameter:
\_parameter: (L1_ICACHE_ID), line:180
|vpiName:L1_ICACHE_ID
|INT:19
|vpiParameter:
\_parameter: (L1_IMMU_ID), line:181
|vpiName:L1_IMMU_ID
|INT:0
|vpiParameter:
\_parameter: (LS_UNIT_WB_ID), line:191
|vpiName:LS_UNIT_WB_ID
|INT:1
|vpiParameter:
\_parameter: (MAX_INFLIGHT_COUNT), line:167
|vpiName:MAX_INFLIGHT_COUNT
|INT:19
|vpiParameter:
\_parameter: (MEMORY_ADDR_H), line:103
|vpiName:MEMORY_ADDR_H
|INT:12
|vpiParameter:
\_parameter: (MEMORY_ADDR_L), line:102
|vpiName:MEMORY_ADDR_L
|INT:11
|vpiParameter:
\_parameter: (MEMORY_BIT_CHECK), line:104
|vpiName:MEMORY_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (MUL_UNIT_WB_ID), line:193
|vpiName:MUL_UNIT_WB_ID
|INT:512
|vpiParameter:
\_parameter: (NUM_UNITS), line:188
|vpiName:NUM_UNITS
|INT:2
|vpiParameter:
\_parameter: (NUM_WB_UNITS), line:186
|vpiName:NUM_WB_UNITS
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (RAS_DEPTH), line:161
|vpiName:RAS_DEPTH
|INT:2
|vpiParameter:
\_parameter: (RESET_VEC), line:39
|vpiName:RESET_VEC
|INT:-2147483648
|vpiParameter:
\_parameter: (SCRATCH_ADDR_H), line:99
|vpiName:SCRATCH_ADDR_H
|INT:9
|vpiParameter:
\_parameter: (SCRATCH_ADDR_L), line:98
|vpiName:SCRATCH_ADDR_L
|INT:8
|vpiParameter:
\_parameter: (SCRATCH_BIT_CHECK), line:100
|vpiName:SCRATCH_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (USE_AMO), line:70
|vpiName:USE_AMO
|INT:1
|vpiParameter:
\_parameter: (USE_BRANCH_PREDICTOR), line:158
|vpiName:USE_BRANCH_PREDICTOR
|INT:2
|vpiParameter:
\_parameter: (USE_BUS), line:88
|vpiName:USE_BUS
|INT:4
|vpiParameter:
\_parameter: (USE_DCACHE), line:92
|vpiName:USE_DCACHE
|INT:6
|vpiParameter:
\_parameter: (USE_DIV), line:49
|vpiName:USE_DIV
|INT:1
|vpiParameter:
\_parameter: (USE_DTAG_INVALIDATIONS), line:140
|vpiName:USE_DTAG_INVALIDATIONS
|INT:1879048191
|vpiParameter:
\_parameter: (USE_D_SCRATCH_MEM), line:79
|vpiName:USE_D_SCRATCH_MEM
|INT:3
|vpiParameter:
\_parameter: (USE_ICACHE), line:93
|vpiName:USE_ICACHE
|INT:7
|vpiParameter:
\_parameter: (USE_I_SCRATCH_MEM), line:78
|vpiName:USE_I_SCRATCH_MEM
|INT:2
|vpiParameter:
\_parameter: (USE_MUL), line:48
|vpiName:USE_MUL
|INT:1
|vpiParameter:
\_parameter: (WB_UNITS_WIDTH), line:187
|vpiName:WB_UNITS_WIDTH
|INT:32
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiGenScopeArray:
\_gen_scope_array: (genblk2), line:119, parent:bp_block
|vpiName:genblk2
|vpiFullName:work@taiga_wrapper.cpu.bp_block.genblk2
|vpiGenScope:
\_gen_scope: , parent:genblk2
|vpiFullName:work@taiga_wrapper.cpu.bp_block.genblk2
|vpiContAssign:
\_cont_assign: , line:120
|vpiRhs:
\_ref_obj: (tag_match), line:120
|vpiName:tag_match
|vpiFullName:work@taiga_wrapper.cpu.bp_block.genblk2.tag_match
|vpiLhs:
\_ref_obj: (bp.use_prediction), line:120
|vpiName:bp.use_prediction
|vpiFullName:work@taiga_wrapper.cpu.bp_block.genblk2.bp.use_prediction
|vpiContAssign:
\_cont_assign: , line:122
|vpiRhs:
\_constant: , line:122
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiLhs:
\_ref_obj: (bp.use_prediction), line:122
|vpiName:bp.use_prediction
|vpiFullName:work@taiga_wrapper.cpu.bp_block.genblk2.bp.use_prediction
|vpiParameter:
\_parameter: (ALU_UNIT_WB_ID), line:190
|vpiName:ALU_UNIT_WB_ID
|INT:32
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (BRANCH_PREDICTOR_WAYS), line:159
|vpiName:BRANCH_PREDICTOR_WAYS
|INT:9
|vpiParameter:
\_parameter: (BRANCH_TABLE_ENTRIES), line:160
|vpiName:BRANCH_TABLE_ENTRIES
|INT:4
|vpiParameter:
\_parameter: (BRANCH_UNIT_ID), line:195
|vpiName:BRANCH_UNIT_ID
|INT:8
|vpiParameter:
\_parameter: (BUS_ADDR_H), line:107
|vpiName:BUS_ADDR_H
|INT:1
|vpiParameter:
\_parameter: (BUS_ADDR_L), line:106
|vpiName:BUS_ADDR_L
|INT:0
|vpiParameter:
\_parameter: (BUS_BIT_CHECK), line:108
|vpiName:BUS_BIT_CHECK
|INT:1
|vpiParameter:
\_parameter: (BUS_TYPE), line:89
|vpiName:BUS_TYPE
|INT:5
|vpiParameter:
\_parameter: (COUNTER_W), line:42
|vpiName:COUNTER_W
|INT:33
|vpiParameter:
\_parameter: (CPU_ID), line:38
|vpiName:CPU_ID
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_ADDR_WIDTH), line:113
|vpiName:C_M_AXI_ADDR_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_DATA_WIDTH), line:114
|vpiName:C_M_AXI_DATA_WIDTH
|INT:1
|vpiParameter:
\_parameter: (DCACHE_LINES), line:133
|vpiName:DCACHE_LINES
|INT:-2146435073
|vpiParameter:
\_parameter: (DCACHE_LINE_ADDR_W), line:135
|vpiName:DCACHE_LINE_ADDR_W
|INT:1073741824
|vpiParameter:
\_parameter: (DCACHE_LINE_W), line:136
|vpiName:DCACHE_LINE_W
|INT:1342177279
|vpiParameter:
\_parameter: (DCACHE_SUB_LINE_ADDR_W), line:137
|vpiName:DCACHE_SUB_LINE_ADDR_W
|INT:4
|vpiParameter:
\_parameter: (DCACHE_TAG_W), line:138
|vpiName:DCACHE_TAG_W
|INT:1610612736
|vpiParameter:
\_parameter: (DCACHE_WAYS), line:134
|vpiName:DCACHE_WAYS
|INT:4
|vpiParameter:
\_parameter: (DIV_ALGORITHM), line:67
|vpiName:DIV_ALGORITHM
|INT:0
|vpiParameter:
\_parameter: (DIV_UNIT_WB_ID), line:192
|vpiName:DIV_UNIT_WB_ID
|INT:2
|vpiParameter:
\_parameter: (DTLB_DEPTH), line:152
|vpiName:DTLB_DEPTH
|INT:512
|vpiParameter:
\_parameter: (DTLB_WAYS), line:151
|vpiName:DTLB_WAYS
|INT:32
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (ENABLE_M_MODE), line:34
|vpiName:ENABLE_M_MODE
|INT:1
|vpiParameter:
\_parameter: (ENABLE_S_MODE), line:36
|vpiName:ENABLE_S_MODE
|INT:0
|vpiParameter:
\_parameter: (ENABLE_TRACE_INTERFACE), line:172
|vpiName:ENABLE_TRACE_INTERFACE
|INT:2
|vpiParameter:
\_parameter: (FETCH_BUFFER_DEPTH), line:168
|vpiName:FETCH_BUFFER_DEPTH
|INT:512
|vpiParameter:
\_parameter: (FPGA_VENDOR), line:27
|vpiName:FPGA_VENDOR
|STRING:"xilinx"
|vpiParameter:
\_parameter: (GC_UNIT_ID), line:196
|vpiName:GC_UNIT_ID
|INT:4
|vpiParameter:
\_parameter: (ICACHE_LINES), line:121
|vpiName:ICACHE_LINES
|INT:2
|vpiParameter:
\_parameter: (ICACHE_LINE_ADDR_W), line:123
|vpiName:ICACHE_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_LINE_W), line:124
|vpiName:ICACHE_LINE_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_SUB_LINE_ADDR_W), line:125
|vpiName:ICACHE_SUB_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_TAG_W), line:126
|vpiName:ICACHE_TAG_W
|INT:-2147483648
|vpiParameter:
\_parameter: (ICACHE_WAYS), line:122
|vpiName:ICACHE_WAYS
|INT:1
|vpiParameter:
\_parameter: (ITLB_DEPTH), line:146
|vpiName:ITLB_DEPTH
|INT:32
|vpiParameter:
\_parameter: (ITLB_WAYS), line:145
|vpiName:ITLB_WAYS
|INT:4
|vpiParameter:
\_parameter: (L1_CONNECTIONS), line:177
|vpiName:L1_CONNECTIONS
|INT:9
|vpiParameter:
\_parameter: (L1_DCACHE_ID), line:178
|vpiName:L1_DCACHE_ID
|INT:4
|vpiParameter:
\_parameter: (L1_DMMU_ID), line:179
|vpiName:L1_DMMU_ID
|INT:2
|vpiParameter:
\_parameter: (L1_ICACHE_ID), line:180
|vpiName:L1_ICACHE_ID
|INT:19
|vpiParameter:
\_parameter: (L1_IMMU_ID), line:181
|vpiName:L1_IMMU_ID
|INT:0
|vpiParameter:
\_parameter: (LS_UNIT_WB_ID), line:191
|vpiName:LS_UNIT_WB_ID
|INT:1
|vpiParameter:
\_parameter: (MAX_INFLIGHT_COUNT), line:167
|vpiName:MAX_INFLIGHT_COUNT
|INT:19
|vpiParameter:
\_parameter: (MEMORY_ADDR_H), line:103
|vpiName:MEMORY_ADDR_H
|INT:12
|vpiParameter:
\_parameter: (MEMORY_ADDR_L), line:102
|vpiName:MEMORY_ADDR_L
|INT:11
|vpiParameter:
\_parameter: (MEMORY_BIT_CHECK), line:104
|vpiName:MEMORY_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (MUL_UNIT_WB_ID), line:193
|vpiName:MUL_UNIT_WB_ID
|INT:512
|vpiParameter:
\_parameter: (NUM_UNITS), line:188
|vpiName:NUM_UNITS
|INT:2
|vpiParameter:
\_parameter: (NUM_WB_UNITS), line:186
|vpiName:NUM_WB_UNITS
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (RAS_DEPTH), line:161
|vpiName:RAS_DEPTH
|INT:2
|vpiParameter:
\_parameter: (RESET_VEC), line:39
|vpiName:RESET_VEC
|INT:-2147483648
|vpiParameter:
\_parameter: (SCRATCH_ADDR_H), line:99
|vpiName:SCRATCH_ADDR_H
|INT:9
|vpiParameter:
\_parameter: (SCRATCH_ADDR_L), line:98
|vpiName:SCRATCH_ADDR_L
|INT:8
|vpiParameter:
\_parameter: (SCRATCH_BIT_CHECK), line:100
|vpiName:SCRATCH_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (USE_AMO), line:70
|vpiName:USE_AMO
|INT:1
|vpiParameter:
\_parameter: (USE_BRANCH_PREDICTOR), line:158
|vpiName:USE_BRANCH_PREDICTOR
|INT:2
|vpiParameter:
\_parameter: (USE_BUS), line:88
|vpiName:USE_BUS
|INT:4
|vpiParameter:
\_parameter: (USE_DCACHE), line:92
|vpiName:USE_DCACHE
|INT:6
|vpiParameter:
\_parameter: (USE_DIV), line:49
|vpiName:USE_DIV
|INT:1
|vpiParameter:
\_parameter: (USE_DTAG_INVALIDATIONS), line:140
|vpiName:USE_DTAG_INVALIDATIONS
|INT:1879048191
|vpiParameter:
\_parameter: (USE_D_SCRATCH_MEM), line:79
|vpiName:USE_D_SCRATCH_MEM
|INT:3
|vpiParameter:
\_parameter: (USE_ICACHE), line:93
|vpiName:USE_ICACHE
|INT:7
|vpiParameter:
\_parameter: (USE_I_SCRATCH_MEM), line:78
|vpiName:USE_I_SCRATCH_MEM
|INT:2
|vpiParameter:
\_parameter: (USE_MUL), line:48
|vpiName:USE_MUL
|INT:1
|vpiParameter:
\_parameter: (WB_UNITS_WIDTH), line:187
|vpiName:WB_UNITS_WIDTH
|INT:32
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiNet:
\_logic_net: (clk), line:27, parent:bp_block
|vpiNet:
\_logic_net: (rst), line:28, parent:bp_block
|vpiNet:
\_logic_net: (br_results), line:30, parent:bp_block
|vpiNet:
\_logic_net: (if_entry), line:44, parent:bp_block
|vpiName:if_entry
|vpiFullName:work@taiga_wrapper.cpu.bp_block.if_entry
|vpiRange:
\_range: , line:44
|vpiLeftRange:
\_constant: , line:44
|vpiConstType:7
|vpiDecompile:8
|vpiSize:32
|INT:8
|vpiRightRange:
\_constant: , line:44
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (new_jump_addr), line:47, parent:bp_block
|vpiName:new_jump_addr
|vpiFullName:work@taiga_wrapper.cpu.bp_block.new_jump_addr
|vpiNetType:36
|vpiRange:
\_range: , line:47
|vpiLeftRange:
\_constant: , line:47
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:47
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (tag_matches), line:50, parent:bp_block
|vpiName:tag_matches
|vpiFullName:work@taiga_wrapper.cpu.bp_block.tag_matches
|vpiNetType:36
|vpiRange:
\_range: , line:50
|vpiLeftRange:
\_constant: , line:50
|vpiConstType:7
|vpiDecompile:8
|vpiSize:32
|INT:8
|vpiRightRange:
\_constant: , line:50
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (replacement_way), line:51, parent:bp_block
|vpiName:replacement_way
|vpiFullName:work@taiga_wrapper.cpu.bp_block.replacement_way
|vpiNetType:36
|vpiRange:
\_range: , line:51
|vpiLeftRange:
\_constant: , line:51
|vpiConstType:7
|vpiDecompile:8
|vpiSize:32
|INT:8
|vpiRightRange:
\_constant: , line:51
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (update_way), line:52, parent:bp_block
|vpiName:update_way
|vpiFullName:work@taiga_wrapper.cpu.bp_block.update_way
|vpiNetType:36
|vpiRange:
\_range: , line:52
|vpiLeftRange:
\_constant: , line:52
|vpiConstType:7
|vpiDecompile:8
|vpiSize:32
|INT:8
|vpiRightRange:
\_constant: , line:52
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (hit_way), line:53, parent:bp_block
|vpiName:hit_way
|vpiFullName:work@taiga_wrapper.cpu.bp_block.hit_way
|vpiNetType:36
|vpiRange:
\_range: , line:53
|vpiLeftRange:
\_constant: , line:53
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiRightRange:
\_constant: , line:53
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (tag_match), line:54, parent:bp_block
|vpiName:tag_match
|vpiFullName:work@taiga_wrapper.cpu.bp_block.tag_match
|vpiNetType:36
|vpiNet:
\_logic_net: (bp), line:29, parent:bp_block
|vpiName:bp
|vpiFullName:work@taiga_wrapper.cpu.bp_block.bp
|vpiInstance:
\_module: work@taiga (cpu), file:third_party/cores/taiga/examples/zedboard/taiga_wrapper.sv, line:233, parent:work@taiga_wrapper
|vpiArrayNet:
\_array_net: (predicted_pc), line:48, parent:bp_block
|vpiName:predicted_pc
|vpiFullName:work@taiga_wrapper.cpu.bp_block.predicted_pc
|vpiSize:9
|vpiNet:
\_logic_net: , parent:predicted_pc
|vpiFullName:work@taiga_wrapper.cpu.bp_block.predicted_pc
|vpiNetType:36
|vpiRange:
\_range: , line:48
|vpiLeftRange:
\_constant: , line:48
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:48
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiRange:
\_range: , line:48
|vpiLeftRange:
\_constant: , line:48
|vpiConstType:7
|vpiDecompile:8
|vpiSize:32
|INT:8
|vpiRightRange:
\_constant: , line:48
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiVariables:
\_struct_var: (ex_entry), line:45, parent:bp_block
|vpiName:ex_entry
|vpiFullName:work@taiga_wrapper.cpu.bp_block.ex_entry
|vpiTypespec:
\_struct_typespec: (branch_table_entry_t), line:36
|vpiParameter:
\_parameter: (ALU_UNIT_WB_ID), line:190
|vpiName:ALU_UNIT_WB_ID
|INT:32
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (BRANCH_ADDR_W), line:33
|vpiName:BRANCH_ADDR_W
|INT:2
|vpiParameter:
\_parameter: (BRANCH_PREDICTOR_WAYS), line:159
|vpiName:BRANCH_PREDICTOR_WAYS
|INT:9
|vpiParameter:
\_parameter: (BRANCH_TABLE_ENTRIES), line:160
|vpiName:BRANCH_TABLE_ENTRIES
|INT:4
|vpiParameter:
\_parameter: (BRANCH_UNIT_ID), line:195
|vpiName:BRANCH_UNIT_ID
|INT:8
|vpiParameter:
\_parameter: (BTAG_W), line:34
|vpiName:BTAG_W
|INT:28
|vpiParameter:
\_parameter: (BUS_ADDR_H), line:107
|vpiName:BUS_ADDR_H
|INT:1
|vpiParameter:
\_parameter: (BUS_ADDR_L), line:106
|vpiName:BUS_ADDR_L
|INT:0
|vpiParameter:
\_parameter: (BUS_BIT_CHECK), line:108
|vpiName:BUS_BIT_CHECK
|INT:1
|vpiParameter:
\_parameter: (BUS_TYPE), line:89
|vpiName:BUS_TYPE
|INT:5
|vpiParameter:
\_parameter: (COUNTER_W), line:42
|vpiName:COUNTER_W
|INT:33
|vpiParameter:
\_parameter: (CPU_ID), line:38
|vpiName:CPU_ID
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_ADDR_WIDTH), line:113
|vpiName:C_M_AXI_ADDR_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_DATA_WIDTH), line:114
|vpiName:C_M_AXI_DATA_WIDTH
|INT:1
|vpiParameter:
\_parameter: (DCACHE_LINES), line:133
|vpiName:DCACHE_LINES
|INT:-2146435073
|vpiParameter:
\_parameter: (DCACHE_LINE_ADDR_W), line:135
|vpiName:DCACHE_LINE_ADDR_W
|INT:1073741824
|vpiParameter:
\_parameter: (DCACHE_LINE_W), line:136
|vpiName:DCACHE_LINE_W
|INT:1342177279
|vpiParameter:
\_parameter: (DCACHE_SUB_LINE_ADDR_W), line:137
|vpiName:DCACHE_SUB_LINE_ADDR_W
|INT:4
|vpiParameter:
\_parameter: (DCACHE_TAG_W), line:138
|vpiName:DCACHE_TAG_W
|INT:1610612736
|vpiParameter:
\_parameter: (DCACHE_WAYS), line:134
|vpiName:DCACHE_WAYS
|INT:4
|vpiParameter:
\_parameter: (DIV_ALGORITHM), line:67
|vpiName:DIV_ALGORITHM
|INT:0
|vpiParameter:
\_parameter: (DIV_UNIT_WB_ID), line:192
|vpiName:DIV_UNIT_WB_ID
|INT:2
|vpiParameter:
\_parameter: (DTLB_DEPTH), line:152
|vpiName:DTLB_DEPTH
|INT:512
|vpiParameter:
\_parameter: (DTLB_WAYS), line:151
|vpiName:DTLB_WAYS
|INT:32
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (ENABLE_M_MODE), line:34
|vpiName:ENABLE_M_MODE
|INT:1
|vpiParameter:
\_parameter: (ENABLE_S_MODE), line:36
|vpiName:ENABLE_S_MODE
|INT:0
|vpiParameter:
\_parameter: (ENABLE_TRACE_INTERFACE), line:172
|vpiName:ENABLE_TRACE_INTERFACE
|INT:2
|vpiParameter:
\_parameter: (FETCH_BUFFER_DEPTH), line:168
|vpiName:FETCH_BUFFER_DEPTH
|INT:512
|vpiParameter:
\_parameter: (FPGA_VENDOR), line:27
|vpiName:FPGA_VENDOR
|STRING:"xilinx"
|vpiParameter:
\_parameter: (GC_UNIT_ID), line:196
|vpiName:GC_UNIT_ID
|INT:4
|vpiParameter:
\_parameter: (ICACHE_LINES), line:121
|vpiName:ICACHE_LINES
|INT:2
|vpiParameter:
\_parameter: (ICACHE_LINE_ADDR_W), line:123
|vpiName:ICACHE_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_LINE_W), line:124
|vpiName:ICACHE_LINE_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_SUB_LINE_ADDR_W), line:125
|vpiName:ICACHE_SUB_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_TAG_W), line:126
|vpiName:ICACHE_TAG_W
|INT:-2147483648
|vpiParameter:
\_parameter: (ICACHE_WAYS), line:122
|vpiName:ICACHE_WAYS
|INT:1
|vpiParameter:
\_parameter: (ITLB_DEPTH), line:146
|vpiName:ITLB_DEPTH
|INT:32
|vpiParameter:
\_parameter: (ITLB_WAYS), line:145
|vpiName:ITLB_WAYS
|INT:4
|vpiParameter:
\_parameter: (L1_CONNECTIONS), line:177
|vpiName:L1_CONNECTIONS
|INT:9
|vpiParameter:
\_parameter: (L1_DCACHE_ID), line:178
|vpiName:L1_DCACHE_ID
|INT:4
|vpiParameter:
\_parameter: (L1_DMMU_ID), line:179
|vpiName:L1_DMMU_ID
|INT:2
|vpiParameter:
\_parameter: (L1_ICACHE_ID), line:180
|vpiName:L1_ICACHE_ID
|INT:19
|vpiParameter:
\_parameter: (L1_IMMU_ID), line:181
|vpiName:L1_IMMU_ID
|INT:0
|vpiParameter:
\_parameter: (LS_UNIT_WB_ID), line:191
|vpiName:LS_UNIT_WB_ID
|INT:1
|vpiParameter:
\_parameter: (MAX_INFLIGHT_COUNT), line:167
|vpiName:MAX_INFLIGHT_COUNT
|INT:19
|vpiParameter:
\_parameter: (MEMORY_ADDR_H), line:103
|vpiName:MEMORY_ADDR_H
|INT:12
|vpiParameter:
\_parameter: (MEMORY_ADDR_L), line:102
|vpiName:MEMORY_ADDR_L
|INT:11
|vpiParameter:
\_parameter: (MEMORY_BIT_CHECK), line:104
|vpiName:MEMORY_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (MUL_UNIT_WB_ID), line:193
|vpiName:MUL_UNIT_WB_ID
|INT:512
|vpiParameter:
\_parameter: (NUM_UNITS), line:188
|vpiName:NUM_UNITS
|INT:2
|vpiParameter:
\_parameter: (NUM_WB_UNITS), line:186
|vpiName:NUM_WB_UNITS
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (RAS_DEPTH), line:161
|vpiName:RAS_DEPTH
|INT:2
|vpiParameter:
\_parameter: (RESET_VEC), line:39
|vpiName:RESET_VEC
|INT:-2147483648
|vpiParameter:
\_parameter: (SCRATCH_ADDR_H), line:99
|vpiName:SCRATCH_ADDR_H
|INT:9
|vpiParameter:
\_parameter: (SCRATCH_ADDR_L), line:98
|vpiName:SCRATCH_ADDR_L
|INT:8
|vpiParameter:
\_parameter: (SCRATCH_BIT_CHECK), line:100
|vpiName:SCRATCH_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (USE_AMO), line:70
|vpiName:USE_AMO
|INT:1
|vpiParameter:
\_parameter: (USE_BRANCH_PREDICTOR), line:158
|vpiName:USE_BRANCH_PREDICTOR
|INT:2
|vpiParameter:
\_parameter: (USE_BUS), line:88
|vpiName:USE_BUS
|INT:4
|vpiParameter:
\_parameter: (USE_DCACHE), line:92
|vpiName:USE_DCACHE
|INT:6
|vpiParameter:
\_parameter: (USE_DIV), line:49
|vpiName:USE_DIV
|INT:1
|vpiParameter:
\_parameter: (USE_DTAG_INVALIDATIONS), line:140
|vpiName:USE_DTAG_INVALIDATIONS
|INT:1879048191
|vpiParameter:
\_parameter: (USE_D_SCRATCH_MEM), line:79
|vpiName:USE_D_SCRATCH_MEM
|INT:3
|vpiParameter:
\_parameter: (USE_ICACHE), line:93
|vpiName:USE_ICACHE
|INT:7
|vpiParameter:
\_parameter: (USE_I_SCRATCH_MEM), line:78
|vpiName:USE_I_SCRATCH_MEM
|INT:2
|vpiParameter:
\_parameter: (USE_MUL), line:48
|vpiName:USE_MUL
|INT:1
|vpiParameter:
\_parameter: (WB_UNITS_WIDTH), line:187
|vpiName:WB_UNITS_WIDTH
|INT:32
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiModule:
\_module: work@ras (ras_block), file:third_party/cores/taiga/core/taiga.sv, line:162, parent:cpu
|vpiDefName:work@ras
|vpiName:ras_block
|vpiFullName:work@taiga_wrapper.cpu.ras_block
|vpiPort:
\_port: (clk), line:27, parent:ras_block
|vpiName:clk
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (clk), line:162
|vpiName:clk
|vpiActual:
\_logic_net: (clk), line:27, parent:cpu
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (clk), line:27, parent:ras_block
|vpiName:clk
|vpiFullName:work@taiga_wrapper.cpu.ras_block.clk
|vpiNetType:36
|vpiPort:
\_port: (rst), line:28, parent:ras_block
|vpiName:rst
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (rst), line:162
|vpiName:rst
|vpiActual:
\_logic_net: (rst), line:28, parent:cpu
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (rst), line:28, parent:ras_block
|vpiName:rst
|vpiFullName:work@taiga_wrapper.cpu.ras_block.rst
|vpiNetType:36
|vpiPort:
\_port: (ras), line:29, parent:ras_block
|vpiName:ras
|vpiDirection:5
|vpiHighConn:
\_ref_obj: (ras), line:162
|vpiName:ras
|vpiActual:
\_interface: work@ras_interface (ras), file:third_party/cores/taiga/core/taiga.sv, line:54
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_modport: (self)
|vpiName:self
|vpiIODecl:
\_io_decl: (push)
|vpiName:push
|vpiDirection:1
|vpiExpr:
\_logic_net: (push), line:65
|vpiName:push
|vpiNetType:36
|vpiIODecl:
\_io_decl: (pop)
|vpiName:pop
|vpiDirection:1
|vpiExpr:
\_logic_net: (pop), line:66
|vpiName:pop
|vpiNetType:36
|vpiIODecl:
\_io_decl: (new_addr)
|vpiName:new_addr
|vpiDirection:1
|vpiExpr:
\_logic_net: (new_addr), line:67
|vpiName:new_addr
|vpiNetType:36
|vpiRange:
\_range: , line:67
|vpiLeftRange:
\_constant: , line:67
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:67
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (addr)
|vpiName:addr
|vpiDirection:2
|vpiExpr:
\_logic_net: (addr), line:68
|vpiName:addr
|vpiNetType:36
|vpiRange:
\_range: , line:68
|vpiLeftRange:
\_constant: , line:68
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:68
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (valid)
|vpiName:valid
|vpiDirection:2
|vpiExpr:
\_logic_net: (valid), line:69
|vpiName:valid
|vpiNetType:36
|vpiInterface:
\_interface: work@ras_interface (ras), file:third_party/cores/taiga/core/taiga.sv, line:162
|vpiDefName:work@ras_interface
|vpiName:ras
|vpiModport:
\_modport: (branch_unit)
|vpiName:branch_unit
|vpiIODecl:
\_io_decl: (push)
|vpiName:push
|vpiDirection:2
|vpiExpr:
\_logic_net: (push), line:65
|vpiIODecl:
\_io_decl: (pop)
|vpiName:pop
|vpiDirection:2
|vpiExpr:
\_logic_net: (pop), line:66
|vpiIODecl:
\_io_decl: (new_addr)
|vpiName:new_addr
|vpiDirection:2
|vpiExpr:
\_logic_net: (new_addr), line:67
|vpiInterface:
\_interface: work@ras_interface (ras), file:third_party/cores/taiga/core/taiga.sv, line:162
|vpiModport:
\_modport: (fetch)
|vpiName:fetch
|vpiIODecl:
\_io_decl: (addr)
|vpiName:addr
|vpiDirection:1
|vpiExpr:
\_logic_net: (addr), line:68
|vpiIODecl:
\_io_decl: (valid)
|vpiName:valid
|vpiDirection:1
|vpiExpr:
\_logic_net: (valid), line:69
|vpiInterface:
\_interface: work@ras_interface (ras), file:third_party/cores/taiga/core/taiga.sv, line:162
|vpiModport:
\_modport: (self)
|vpiNet:
\_logic_net: (clk), line:27, parent:ras_block
|vpiNet:
\_logic_net: (rst), line:28, parent:ras_block
|vpiNet:
\_logic_net: (read_index), line:35, parent:ras_block
|vpiName:read_index
|vpiFullName:work@taiga_wrapper.cpu.ras_block.read_index
|vpiNetType:36
|vpiRange:
\_range: , line:35
|vpiLeftRange:
\_constant: , line:35
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiRightRange:
\_constant: , line:35
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (write_index), line:36, parent:ras_block
|vpiName:write_index
|vpiFullName:work@taiga_wrapper.cpu.ras_block.write_index
|vpiNetType:36
|vpiRange:
\_range: , line:36
|vpiLeftRange:
\_constant: , line:36
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiRightRange:
\_constant: , line:36
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (valid_chain_update), line:38, parent:ras_block
|vpiName:valid_chain_update
|vpiFullName:work@taiga_wrapper.cpu.ras_block.valid_chain_update
|vpiNetType:36
|vpiNet:
\_logic_net: (ras), line:29, parent:ras_block
|vpiName:ras
|vpiFullName:work@taiga_wrapper.cpu.ras_block.ras
|vpiInstance:
\_module: work@taiga (cpu), file:third_party/cores/taiga/examples/zedboard/taiga_wrapper.sv, line:233, parent:work@taiga_wrapper
|vpiArrayNet:
\_array_net: (lut_ram), line:32, parent:ras_block
|vpiName:lut_ram
|vpiFullName:work@taiga_wrapper.cpu.ras_block.lut_ram
|vpiSize:2
|vpiNet:
\_logic_net: , parent:lut_ram
|vpiFullName:work@taiga_wrapper.cpu.ras_block.lut_ram
|vpiNetType:36
|vpiRange:
\_range: , line:32
|vpiLeftRange:
\_constant: , line:32
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:32
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiRange:
\_range: , line:32
|vpiLeftRange:
\_constant: , line:32
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:32
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiArrayNet:
\_array_net: (valid_chain), line:37, parent:ras_block
|vpiName:valid_chain
|vpiFullName:work@taiga_wrapper.cpu.ras_block.valid_chain
|vpiSize:2
|vpiNet:
\_logic_net: , parent:valid_chain
|vpiFullName:work@taiga_wrapper.cpu.ras_block.valid_chain
|vpiNetType:36
|vpiRange:
\_range: , line:37
|vpiLeftRange:
\_constant: , line:37
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:37
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiParameter:
\_parameter: (ALU_UNIT_WB_ID), line:190
|vpiName:ALU_UNIT_WB_ID
|INT:32
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (BRANCH_PREDICTOR_WAYS), line:159
|vpiName:BRANCH_PREDICTOR_WAYS
|INT:9
|vpiParameter:
\_parameter: (BRANCH_TABLE_ENTRIES), line:160
|vpiName:BRANCH_TABLE_ENTRIES
|INT:4
|vpiParameter:
\_parameter: (BRANCH_UNIT_ID), line:195
|vpiName:BRANCH_UNIT_ID
|INT:8
|vpiParameter:
\_parameter: (BUS_ADDR_H), line:107
|vpiName:BUS_ADDR_H
|INT:1
|vpiParameter:
\_parameter: (BUS_ADDR_L), line:106
|vpiName:BUS_ADDR_L
|INT:0
|vpiParameter:
\_parameter: (BUS_BIT_CHECK), line:108
|vpiName:BUS_BIT_CHECK
|INT:1
|vpiParameter:
\_parameter: (BUS_TYPE), line:89
|vpiName:BUS_TYPE
|INT:5
|vpiParameter:
\_parameter: (COUNTER_W), line:42
|vpiName:COUNTER_W
|INT:33
|vpiParameter:
\_parameter: (CPU_ID), line:38
|vpiName:CPU_ID
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_ADDR_WIDTH), line:113
|vpiName:C_M_AXI_ADDR_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_DATA_WIDTH), line:114
|vpiName:C_M_AXI_DATA_WIDTH
|INT:1
|vpiParameter:
\_parameter: (DCACHE_LINES), line:133
|vpiName:DCACHE_LINES
|INT:-2146435073
|vpiParameter:
\_parameter: (DCACHE_LINE_ADDR_W), line:135
|vpiName:DCACHE_LINE_ADDR_W
|INT:1073741824
|vpiParameter:
\_parameter: (DCACHE_LINE_W), line:136
|vpiName:DCACHE_LINE_W
|INT:1342177279
|vpiParameter:
\_parameter: (DCACHE_SUB_LINE_ADDR_W), line:137
|vpiName:DCACHE_SUB_LINE_ADDR_W
|INT:4
|vpiParameter:
\_parameter: (DCACHE_TAG_W), line:138
|vpiName:DCACHE_TAG_W
|INT:1610612736
|vpiParameter:
\_parameter: (DCACHE_WAYS), line:134
|vpiName:DCACHE_WAYS
|INT:4
|vpiParameter:
\_parameter: (DIV_ALGORITHM), line:67
|vpiName:DIV_ALGORITHM
|INT:0
|vpiParameter:
\_parameter: (DIV_UNIT_WB_ID), line:192
|vpiName:DIV_UNIT_WB_ID
|INT:2
|vpiParameter:
\_parameter: (DTLB_DEPTH), line:152
|vpiName:DTLB_DEPTH
|INT:512
|vpiParameter:
\_parameter: (DTLB_WAYS), line:151
|vpiName:DTLB_WAYS
|INT:32
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (ENABLE_M_MODE), line:34
|vpiName:ENABLE_M_MODE
|INT:1
|vpiParameter:
\_parameter: (ENABLE_S_MODE), line:36
|vpiName:ENABLE_S_MODE
|INT:0
|vpiParameter:
\_parameter: (ENABLE_TRACE_INTERFACE), line:172
|vpiName:ENABLE_TRACE_INTERFACE
|INT:2
|vpiParameter:
\_parameter: (FETCH_BUFFER_DEPTH), line:168
|vpiName:FETCH_BUFFER_DEPTH
|INT:512
|vpiParameter:
\_parameter: (FPGA_VENDOR), line:27
|vpiName:FPGA_VENDOR
|STRING:"xilinx"
|vpiParameter:
\_parameter: (GC_UNIT_ID), line:196
|vpiName:GC_UNIT_ID
|INT:4
|vpiParameter:
\_parameter: (ICACHE_LINES), line:121
|vpiName:ICACHE_LINES
|INT:2
|vpiParameter:
\_parameter: (ICACHE_LINE_ADDR_W), line:123
|vpiName:ICACHE_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_LINE_W), line:124
|vpiName:ICACHE_LINE_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_SUB_LINE_ADDR_W), line:125
|vpiName:ICACHE_SUB_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_TAG_W), line:126
|vpiName:ICACHE_TAG_W
|INT:-2147483648
|vpiParameter:
\_parameter: (ICACHE_WAYS), line:122
|vpiName:ICACHE_WAYS
|INT:1
|vpiParameter:
\_parameter: (ITLB_DEPTH), line:146
|vpiName:ITLB_DEPTH
|INT:32
|vpiParameter:
\_parameter: (ITLB_WAYS), line:145
|vpiName:ITLB_WAYS
|INT:4
|vpiParameter:
\_parameter: (L1_CONNECTIONS), line:177
|vpiName:L1_CONNECTIONS
|INT:9
|vpiParameter:
\_parameter: (L1_DCACHE_ID), line:178
|vpiName:L1_DCACHE_ID
|INT:4
|vpiParameter:
\_parameter: (L1_DMMU_ID), line:179
|vpiName:L1_DMMU_ID
|INT:2
|vpiParameter:
\_parameter: (L1_ICACHE_ID), line:180
|vpiName:L1_ICACHE_ID
|INT:19
|vpiParameter:
\_parameter: (L1_IMMU_ID), line:181
|vpiName:L1_IMMU_ID
|INT:0
|vpiParameter:
\_parameter: (LS_UNIT_WB_ID), line:191
|vpiName:LS_UNIT_WB_ID
|INT:1
|vpiParameter:
\_parameter: (MAX_INFLIGHT_COUNT), line:167
|vpiName:MAX_INFLIGHT_COUNT
|INT:19
|vpiParameter:
\_parameter: (MEMORY_ADDR_H), line:103
|vpiName:MEMORY_ADDR_H
|INT:12
|vpiParameter:
\_parameter: (MEMORY_ADDR_L), line:102
|vpiName:MEMORY_ADDR_L
|INT:11
|vpiParameter:
\_parameter: (MEMORY_BIT_CHECK), line:104
|vpiName:MEMORY_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (MUL_UNIT_WB_ID), line:193
|vpiName:MUL_UNIT_WB_ID
|INT:512
|vpiParameter:
\_parameter: (NUM_UNITS), line:188
|vpiName:NUM_UNITS
|INT:2
|vpiParameter:
\_parameter: (NUM_WB_UNITS), line:186
|vpiName:NUM_WB_UNITS
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (RAS_DEPTH), line:161
|vpiName:RAS_DEPTH
|INT:2
|vpiParameter:
\_parameter: (RAS_DEPTH_W), line:34
|vpiName:RAS_DEPTH_W
|INT:1
|vpiParameter:
\_parameter: (RESET_VEC), line:39
|vpiName:RESET_VEC
|INT:-2147483648
|vpiParameter:
\_parameter: (SCRATCH_ADDR_H), line:99
|vpiName:SCRATCH_ADDR_H
|INT:9
|vpiParameter:
\_parameter: (SCRATCH_ADDR_L), line:98
|vpiName:SCRATCH_ADDR_L
|INT:8
|vpiParameter:
\_parameter: (SCRATCH_BIT_CHECK), line:100
|vpiName:SCRATCH_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (USE_AMO), line:70
|vpiName:USE_AMO
|INT:1
|vpiParameter:
\_parameter: (USE_BRANCH_PREDICTOR), line:158
|vpiName:USE_BRANCH_PREDICTOR
|INT:2
|vpiParameter:
\_parameter: (USE_BUS), line:88
|vpiName:USE_BUS
|INT:4
|vpiParameter:
\_parameter: (USE_DCACHE), line:92
|vpiName:USE_DCACHE
|INT:6
|vpiParameter:
\_parameter: (USE_DIV), line:49
|vpiName:USE_DIV
|INT:1
|vpiParameter:
\_parameter: (USE_DTAG_INVALIDATIONS), line:140
|vpiName:USE_DTAG_INVALIDATIONS
|INT:1879048191
|vpiParameter:
\_parameter: (USE_D_SCRATCH_MEM), line:79
|vpiName:USE_D_SCRATCH_MEM
|INT:3
|vpiParameter:
\_parameter: (USE_ICACHE), line:93
|vpiName:USE_ICACHE
|INT:7
|vpiParameter:
\_parameter: (USE_I_SCRATCH_MEM), line:78
|vpiName:USE_I_SCRATCH_MEM
|INT:2
|vpiParameter:
\_parameter: (USE_MUL), line:48
|vpiName:USE_MUL
|INT:1
|vpiParameter:
\_parameter: (WB_UNITS_WIDTH), line:187
|vpiName:WB_UNITS_WIDTH
|INT:32
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiModule:
\_module: work@pre_decode (pre_decode_block), file:third_party/cores/taiga/core/taiga.sv, line:172, parent:cpu
|vpiDefName:work@pre_decode
|vpiName:pre_decode_block
|vpiFullName:work@taiga_wrapper.cpu.pre_decode_block
|vpiPort:
\_port: (clk), line:28, parent:pre_decode_block
|vpiName:clk
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (clk), line:172
|vpiName:clk
|vpiActual:
\_logic_net: (clk), line:27, parent:cpu
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (clk), line:28, parent:pre_decode_block
|vpiName:clk
|vpiFullName:work@taiga_wrapper.cpu.pre_decode_block.clk
|vpiNetType:36
|vpiPort:
\_port: (rst), line:29, parent:pre_decode_block
|vpiName:rst
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (rst), line:172
|vpiName:rst
|vpiActual:
\_logic_net: (rst), line:28, parent:cpu
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (rst), line:29, parent:pre_decode_block
|vpiName:rst
|vpiFullName:work@taiga_wrapper.cpu.pre_decode_block.rst
|vpiNetType:36
|vpiPort:
\_port: (pre_decode_instruction), line:32, parent:pre_decode_block
|vpiName:pre_decode_instruction
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (pre_decode_instruction), line:172
|vpiName:pre_decode_instruction
|vpiActual:
\_logic_net: (pre_decode_instruction), line:84, parent:cpu
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (pre_decode_instruction), line:32, parent:pre_decode_block
|vpiName:pre_decode_instruction
|vpiFullName:work@taiga_wrapper.cpu.pre_decode_block.pre_decode_instruction
|vpiNetType:36
|vpiRange:
\_range: , line:32
|vpiLeftRange:
\_constant: , line:32
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:32
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiPort:
\_port: (pre_decode_pc), line:33, parent:pre_decode_block
|vpiName:pre_decode_pc
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (pre_decode_pc), line:172
|vpiName:pre_decode_pc
|vpiActual:
\_logic_net: (pre_decode_pc), line:85, parent:cpu
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (pre_decode_pc), line:33, parent:pre_decode_block
|vpiName:pre_decode_pc
|vpiFullName:work@taiga_wrapper.cpu.pre_decode_block.pre_decode_pc
|vpiNetType:36
|vpiRange:
\_range: , line:33
|vpiLeftRange:
\_constant: , line:33
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:33
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiPort:
\_port: (branch_metadata), line:34, parent:pre_decode_block
|vpiName:branch_metadata
|vpiDirection:1
|vpiTypedef:
\_logic_typespec: (branch_predictor_metadata_t), line:32
|vpiHighConn:
\_ref_obj: (branch_metadata), line:172
|vpiName:branch_metadata
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (branch_metadata), line:34, parent:pre_decode_block
|vpiName:branch_metadata
|vpiFullName:work@taiga_wrapper.cpu.pre_decode_block.branch_metadata
|vpiPort:
\_port: (branch_prediction_used), line:35, parent:pre_decode_block
|vpiName:branch_prediction_used
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (branch_prediction_used), line:172
|vpiName:branch_prediction_used
|vpiActual:
\_logic_net: (branch_prediction_used), line:87, parent:cpu
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (branch_prediction_used), line:35, parent:pre_decode_block
|vpiName:branch_prediction_used
|vpiFullName:work@taiga_wrapper.cpu.pre_decode_block.branch_prediction_used
|vpiNetType:36
|vpiPort:
\_port: (bp_update_way), line:36, parent:pre_decode_block
|vpiName:bp_update_way
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (bp_update_way), line:172
|vpiName:bp_update_way
|vpiActual:
\_logic_net: (bp_update_way), line:88, parent:cpu
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (bp_update_way), line:36, parent:pre_decode_block
|vpiName:bp_update_way
|vpiFullName:work@taiga_wrapper.cpu.pre_decode_block.bp_update_way
|vpiNetType:36
|vpiRange:
\_range: , line:36
|vpiLeftRange:
\_constant: , line:36
|vpiConstType:7
|vpiDecompile:8
|vpiSize:32
|INT:8
|vpiRightRange:
\_constant: , line:36
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiPort:
\_port: (pre_decode_push), line:37, parent:pre_decode_block
|vpiName:pre_decode_push
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (pre_decode_push), line:172
|vpiName:pre_decode_push
|vpiActual:
\_logic_net: (pre_decode_push), line:82, parent:cpu
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (pre_decode_push), line:37, parent:pre_decode_block
|vpiName:pre_decode_push
|vpiFullName:work@taiga_wrapper.cpu.pre_decode_block.pre_decode_push
|vpiNetType:36
|vpiPort:
\_port: (gc_fetch_flush), line:40, parent:pre_decode_block
|vpiName:gc_fetch_flush
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (gc_fetch_flush), line:172
|vpiName:gc_fetch_flush
|vpiActual:
\_logic_net: (gc_fetch_flush), line:95, parent:cpu
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (gc_fetch_flush), line:40, parent:pre_decode_block
|vpiName:gc_fetch_flush
|vpiFullName:work@taiga_wrapper.cpu.pre_decode_block.gc_fetch_flush
|vpiNetType:36
|vpiPort:
\_port: (pre_decode_pop), line:43, parent:pre_decode_block
|vpiName:pre_decode_pop
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (pre_decode_pop), line:172
|vpiName:pre_decode_pop
|vpiActual:
\_logic_net: (pre_decode_pop), line:83, parent:cpu
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (pre_decode_pop), line:43, parent:pre_decode_block
|vpiName:pre_decode_pop
|vpiFullName:work@taiga_wrapper.cpu.pre_decode_block.pre_decode_pop
|vpiNetType:36
|vpiPort:
\_port: (fb_valid), line:44, parent:pre_decode_block
|vpiName:fb_valid
|vpiDirection:2
|vpiHighConn:
\_ref_obj: (fb_valid), line:172
|vpiName:fb_valid
|vpiActual:
\_logic_net: (fb_valid), line:89, parent:cpu
|vpiName:fb_valid
|vpiFullName:work@taiga_wrapper.cpu.fb_valid
|vpiNetType:36
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (fb_valid), line:44, parent:pre_decode_block
|vpiName:fb_valid
|vpiFullName:work@taiga_wrapper.cpu.pre_decode_block.fb_valid
|vpiNetType:36
|vpiPort:
\_port: (fb), line:45, parent:pre_decode_block
|vpiName:fb
|vpiDirection:2
|vpiTypedef:
\_struct_typespec: (fetch_buffer_packet_t), line:276
|vpiHighConn:
\_ref_obj: (fb), line:172
|vpiName:fb
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (fb), line:45, parent:pre_decode_block
|vpiName:fb
|vpiFullName:work@taiga_wrapper.cpu.pre_decode_block.fb
|vpiInterface:
\_interface: work@fifo_interface (fb_fifo), file:third_party/cores/taiga/core/pre_decode.sv, line:66, parent:pre_decode_block
|vpiDefName:work@fifo_interface
|vpiName:fb_fifo
|vpiFullName:work@taiga_wrapper.cpu.pre_decode_block.fb_fifo
|vpiModport:
\_modport: (dequeue), parent:fb_fifo
|vpiName:dequeue
|vpiIODecl:
\_io_decl: (valid), parent:dequeue
|vpiName:valid
|vpiDirection:1
|vpiIODecl:
\_io_decl: (data_out), parent:dequeue
|vpiName:data_out
|vpiDirection:1
|vpiIODecl:
\_io_decl: (pop), parent:dequeue
|vpiName:pop
|vpiDirection:2
|vpiInterface:
\_interface: work@fifo_interface (fb_fifo), file:third_party/cores/taiga/core/pre_decode.sv, line:66, parent:pre_decode_block
|vpiModport:
\_modport: (enqueue), parent:fb_fifo
|vpiName:enqueue
|vpiIODecl:
\_io_decl: (full), parent:enqueue
|vpiName:full
|vpiDirection:1
|vpiIODecl:
\_io_decl: (data_in), parent:enqueue
|vpiName:data_in
|vpiDirection:2
|vpiIODecl:
\_io_decl: (push), parent:enqueue
|vpiName:push
|vpiDirection:2
|vpiIODecl:
\_io_decl: (supress_push), parent:enqueue
|vpiName:supress_push
|vpiDirection:2
|vpiInterface:
\_interface: work@fifo_interface (fb_fifo), file:third_party/cores/taiga/core/pre_decode.sv, line:66, parent:pre_decode_block
|vpiModport:
\_modport: (structure), parent:fb_fifo
|vpiName:structure
|vpiIODecl:
\_io_decl: (push), parent:structure
|vpiName:push
|vpiDirection:1
|vpiIODecl:
\_io_decl: (pop), parent:structure
|vpiName:pop
|vpiDirection:1
|vpiIODecl:
\_io_decl: (data_in), parent:structure
|vpiName:data_in
|vpiDirection:1
|vpiIODecl:
\_io_decl: (supress_push), parent:structure
|vpiName:supress_push
|vpiDirection:1
|vpiIODecl:
\_io_decl: (data_out), parent:structure
|vpiName:data_out
|vpiDirection:2
|vpiIODecl:
\_io_decl: (valid), parent:structure
|vpiName:valid
|vpiDirection:2
|vpiIODecl:
\_io_decl: (full), parent:structure
|vpiName:full
|vpiDirection:2
|vpiInterface:
\_interface: work@fifo_interface (fb_fifo), file:third_party/cores/taiga/core/pre_decode.sv, line:66, parent:pre_decode_block
|vpiNet:
\_logic_net: (push), line:158, parent:fb_fifo
|vpiName:push
|vpiFullName:work@taiga_wrapper.cpu.pre_decode_block.fb_fifo.push
|vpiNetType:36
|vpiNet:
\_logic_net: (pop), line:159, parent:fb_fifo
|vpiName:pop
|vpiFullName:work@taiga_wrapper.cpu.pre_decode_block.fb_fifo.pop
|vpiNetType:36
|vpiNet:
\_logic_net: (data_in), line:160, parent:fb_fifo
|vpiName:data_in
|vpiFullName:work@taiga_wrapper.cpu.pre_decode_block.fb_fifo.data_in
|vpiNetType:36
|vpiRange:
\_range: , line:160
|vpiLeftRange:
\_constant: , line:160
|vpiDecompile:-1
|INT:-1
|vpiRightRange:
\_constant: , line:160
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (data_out), line:161, parent:fb_fifo
|vpiName:data_out
|vpiFullName:work@taiga_wrapper.cpu.pre_decode_block.fb_fifo.data_out
|vpiNetType:36
|vpiRange:
\_range: , line:161
|vpiLeftRange:
\_constant: , line:161
|vpiDecompile:-1
|INT:-1
|vpiRightRange:
\_constant: , line:161
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (valid), line:162, parent:fb_fifo
|vpiName:valid
|vpiFullName:work@taiga_wrapper.cpu.pre_decode_block.fb_fifo.valid
|vpiNetType:36
|vpiNet:
\_logic_net: (full), line:163, parent:fb_fifo
|vpiName:full
|vpiFullName:work@taiga_wrapper.cpu.pre_decode_block.fb_fifo.full
|vpiNetType:36
|vpiNet:
\_logic_net: (supress_push), line:164, parent:fb_fifo
|vpiName:supress_push
|vpiFullName:work@taiga_wrapper.cpu.pre_decode_block.fb_fifo.supress_push
|vpiNetType:36
|vpiNet:
\_logic_net: (push), line:158, parent:fb_fifo
|vpiName:push
|vpiFullName:work@taiga_wrapper.cpu.pre_decode_block.fb_fifo.push
|vpiNetType:36
|vpiNet:
\_logic_net: (pop), line:159, parent:fb_fifo
|vpiName:pop
|vpiFullName:work@taiga_wrapper.cpu.pre_decode_block.fb_fifo.pop
|vpiNetType:36
|vpiNet:
\_logic_net: (data_in), line:160, parent:fb_fifo
|vpiName:data_in
|vpiFullName:work@taiga_wrapper.cpu.pre_decode_block.fb_fifo.data_in
|vpiNetType:36
|vpiRange:
\_range: , line:160
|vpiLeftRange:
\_constant: , line:160
|vpiDecompile:-1
|INT:-1
|vpiRightRange:
\_constant: , line:160
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (data_out), line:161, parent:fb_fifo
|vpiName:data_out
|vpiFullName:work@taiga_wrapper.cpu.pre_decode_block.fb_fifo.data_out
|vpiNetType:36
|vpiRange:
\_range: , line:161
|vpiLeftRange:
\_constant: , line:161
|vpiDecompile:-1
|INT:-1
|vpiRightRange:
\_constant: , line:161
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (valid), line:162, parent:fb_fifo
|vpiName:valid
|vpiFullName:work@taiga_wrapper.cpu.pre_decode_block.fb_fifo.valid
|vpiNetType:36
|vpiNet:
\_logic_net: (full), line:163, parent:fb_fifo
|vpiName:full
|vpiFullName:work@taiga_wrapper.cpu.pre_decode_block.fb_fifo.full
|vpiNetType:36
|vpiNet:
\_logic_net: (supress_push), line:164, parent:fb_fifo
|vpiName:supress_push
|vpiFullName:work@taiga_wrapper.cpu.pre_decode_block.fb_fifo.supress_push
|vpiNetType:36
|vpiInstance:
\_module: work@pre_decode (pre_decode_block), file:third_party/cores/taiga/core/taiga.sv, line:172, parent:cpu
|vpiModule:
\_module: work@taiga_fifo (fb_fifo_block), file:third_party/cores/taiga/core/pre_decode.sv, line:100, parent:pre_decode_block
|vpiDefName:work@taiga_fifo
|vpiName:fb_fifo_block
|vpiFullName:work@taiga_wrapper.cpu.pre_decode_block.fb_fifo_block
|vpiPort:
\_port: (fifo), line:33, parent:fb_fifo_block
|vpiName:fifo
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (fb_fifo), line:103
|vpiName:fb_fifo
|vpiActual:
\_interface: work@fifo_interface (fb_fifo), file:third_party/cores/taiga/core/pre_decode.sv, line:66
|vpiDefName:work@fifo_interface
|vpiName:fb_fifo
|vpiModport:
\_modport: (dequeue)
|vpiName:dequeue
|vpiIODecl:
\_io_decl: (valid)
|vpiName:valid
|vpiDirection:1
|vpiIODecl:
\_io_decl: (data_out)
|vpiName:data_out
|vpiDirection:1
|vpiIODecl:
\_io_decl: (pop)
|vpiName:pop
|vpiDirection:2
|vpiInterface:
\_interface: work@fifo_interface (fb_fifo), file:third_party/cores/taiga/core/pre_decode.sv, line:66
|vpiModport:
\_modport: (enqueue)
|vpiName:enqueue
|vpiIODecl:
\_io_decl: (full)
|vpiName:full
|vpiDirection:1
|vpiIODecl:
\_io_decl: (data_in)
|vpiName:data_in
|vpiDirection:2
|vpiIODecl:
\_io_decl: (push)
|vpiName:push
|vpiDirection:2
|vpiIODecl:
\_io_decl: (supress_push)
|vpiName:supress_push
|vpiDirection:2
|vpiInterface:
\_interface: work@fifo_interface (fb_fifo), file:third_party/cores/taiga/core/pre_decode.sv, line:66
|vpiModport:
\_modport: (structure)
|vpiName:structure
|vpiIODecl:
\_io_decl: (push)
|vpiName:push
|vpiDirection:1
|vpiIODecl:
\_io_decl: (pop)
|vpiName:pop
|vpiDirection:1
|vpiIODecl:
\_io_decl: (data_in)
|vpiName:data_in
|vpiDirection:1
|vpiIODecl:
\_io_decl: (supress_push)
|vpiName:supress_push
|vpiDirection:1
|vpiIODecl:
\_io_decl: (data_out)
|vpiName:data_out
|vpiDirection:2
|vpiIODecl:
\_io_decl: (valid)
|vpiName:valid
|vpiDirection:2
|vpiIODecl:
\_io_decl: (full)
|vpiName:full
|vpiDirection:2
|vpiInterface:
\_interface: work@fifo_interface (fb_fifo), file:third_party/cores/taiga/core/pre_decode.sv, line:66
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_interface: work@fifo_interface (fifo), file:third_party/cores/taiga/core/pre_decode.sv, line:100
|vpiDefName:work@fifo_interface
|vpiName:fifo
|vpiModport:
\_modport: (dequeue)
|vpiName:dequeue
|vpiIODecl:
\_io_decl: (valid)
|vpiName:valid
|vpiDirection:1
|vpiExpr:
\_logic_net: (valid), line:162
|vpiName:valid
|vpiNetType:36
|vpiIODecl:
\_io_decl: (data_out)
|vpiName:data_out
|vpiDirection:1
|vpiExpr:
\_logic_net: (data_out), line:161
|vpiName:data_out
|vpiNetType:36
|vpiRange:
\_range: , line:161
|vpiLeftRange:
\_constant: , line:161
|vpiDecompile:-1
|INT:-1
|vpiRightRange:
\_constant: , line:161
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (pop)
|vpiName:pop
|vpiDirection:2
|vpiExpr:
\_logic_net: (pop), line:159
|vpiName:pop
|vpiNetType:36
|vpiInterface:
\_interface: work@fifo_interface (fifo), file:third_party/cores/taiga/core/pre_decode.sv, line:100
|vpiModport:
\_modport: (enqueue)
|vpiName:enqueue
|vpiIODecl:
\_io_decl: (full)
|vpiName:full
|vpiDirection:1
|vpiExpr:
\_logic_net: (full), line:163
|vpiName:full
|vpiNetType:36
|vpiIODecl:
\_io_decl: (data_in)
|vpiName:data_in
|vpiDirection:2
|vpiExpr:
\_logic_net: (data_in), line:160
|vpiName:data_in
|vpiNetType:36
|vpiRange:
\_range: , line:160
|vpiLeftRange:
\_constant: , line:160
|vpiDecompile:-1
|INT:-1
|vpiRightRange:
\_constant: , line:160
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (push)
|vpiName:push
|vpiDirection:2
|vpiExpr:
\_logic_net: (push), line:158
|vpiName:push
|vpiNetType:36
|vpiIODecl:
\_io_decl: (supress_push)
|vpiName:supress_push
|vpiDirection:2
|vpiExpr:
\_logic_net: (supress_push), line:164
|vpiName:supress_push
|vpiNetType:36
|vpiInterface:
\_interface: work@fifo_interface (fifo), file:third_party/cores/taiga/core/pre_decode.sv, line:100
|vpiModport:
\_modport: (structure)
|vpiName:structure
|vpiIODecl:
\_io_decl: (push)
|vpiName:push
|vpiDirection:1
|vpiExpr:
\_logic_net: (push), line:158
|vpiIODecl:
\_io_decl: (pop)
|vpiName:pop
|vpiDirection:1
|vpiExpr:
\_logic_net: (pop), line:159
|vpiIODecl:
\_io_decl: (data_in)
|vpiName:data_in
|vpiDirection:1
|vpiExpr:
\_logic_net: (data_in), line:160
|vpiIODecl:
\_io_decl: (supress_push)
|vpiName:supress_push
|vpiDirection:1
|vpiExpr:
\_logic_net: (supress_push), line:164
|vpiIODecl:
\_io_decl: (data_out)
|vpiName:data_out
|vpiDirection:2
|vpiExpr:
\_logic_net: (data_out), line:161
|vpiIODecl:
\_io_decl: (valid)
|vpiName:valid
|vpiDirection:2
|vpiExpr:
\_logic_net: (valid), line:162
|vpiIODecl:
\_io_decl: (full)
|vpiName:full
|vpiDirection:2
|vpiExpr:
\_logic_net: (full), line:163
|vpiInterface:
\_interface: work@fifo_interface (fifo), file:third_party/cores/taiga/core/pre_decode.sv, line:100
|vpiPort:
\_port: (rst), line:34, parent:fb_fifo_block
|vpiName:rst
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (buffer_reset), line:103
|vpiName:buffer_reset
|vpiActual:
\_logic_net: (buffer_reset), line:48, parent:pre_decode_block
|vpiName:buffer_reset
|vpiFullName:work@taiga_wrapper.cpu.pre_decode_block.buffer_reset
|vpiNetType:36
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (rst), line:34, parent:fb_fifo_block
|vpiName:rst
|vpiFullName:work@taiga_wrapper.cpu.pre_decode_block.fb_fifo_block.rst
|vpiNetType:36
|vpiPort:
\_port: (clk), line:35, parent:fb_fifo_block
|vpiName:clk
|vpiDirection:5
|vpiHighConn:
\_ref_obj: (clk), line:103
|vpiName:clk
|vpiActual:
\_logic_net: (clk), line:28, parent:pre_decode_block
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_modport: (structure)
|vpiName:structure
|vpiIODecl:
\_io_decl: (push)
|vpiName:push
|vpiDirection:1
|vpiExpr:
\_logic_net: (push), line:158
|vpiIODecl:
\_io_decl: (pop)
|vpiName:pop
|vpiDirection:1
|vpiExpr:
\_logic_net: (pop), line:159
|vpiIODecl:
\_io_decl: (data_in)
|vpiName:data_in
|vpiDirection:1
|vpiExpr:
\_logic_net: (data_in), line:160
|vpiIODecl:
\_io_decl: (supress_push)
|vpiName:supress_push
|vpiDirection:1
|vpiExpr:
\_logic_net: (supress_push), line:164
|vpiIODecl:
\_io_decl: (data_out)
|vpiName:data_out
|vpiDirection:2
|vpiExpr:
\_logic_net: (data_out), line:161
|vpiIODecl:
\_io_decl: (valid)
|vpiName:valid
|vpiDirection:2
|vpiExpr:
\_logic_net: (valid), line:162
|vpiIODecl:
\_io_decl: (full)
|vpiName:full
|vpiDirection:2
|vpiExpr:
\_logic_net: (full), line:163
|vpiInterface:
\_interface: work@fifo_interface (fifo), file:third_party/cores/taiga/core/pre_decode.sv, line:100
|vpiDefName:work@fifo_interface
|vpiName:fifo
|vpiModport:
\_modport: (dequeue)
|vpiName:dequeue
|vpiIODecl:
\_io_decl: (valid)
|vpiName:valid
|vpiDirection:1
|vpiExpr:
\_logic_net: (valid), line:162
|vpiIODecl:
\_io_decl: (data_out)
|vpiName:data_out
|vpiDirection:1
|vpiExpr:
\_logic_net: (data_out), line:161
|vpiIODecl:
\_io_decl: (pop)
|vpiName:pop
|vpiDirection:2
|vpiExpr:
\_logic_net: (pop), line:159
|vpiInterface:
\_interface: work@fifo_interface (fifo), file:third_party/cores/taiga/core/pre_decode.sv, line:100
|vpiModport:
\_modport: (enqueue)
|vpiName:enqueue
|vpiIODecl:
\_io_decl: (full)
|vpiName:full
|vpiDirection:1
|vpiExpr:
\_logic_net: (full), line:163
|vpiIODecl:
\_io_decl: (data_in)
|vpiName:data_in
|vpiDirection:2
|vpiExpr:
\_logic_net: (data_in), line:160
|vpiIODecl:
\_io_decl: (push)
|vpiName:push
|vpiDirection:2
|vpiExpr:
\_logic_net: (push), line:158
|vpiIODecl:
\_io_decl: (supress_push)
|vpiName:supress_push
|vpiDirection:2
|vpiExpr:
\_logic_net: (supress_push), line:164
|vpiInterface:
\_interface: work@fifo_interface (fifo), file:third_party/cores/taiga/core/pre_decode.sv, line:100
|vpiModport:
\_modport: (structure)
|vpiPort:
\_port: (rst), parent:fb_fifo_block
|vpiName:rst
|vpiHighConn:
\_ref_obj: (rst), line:103
|vpiName:rst
|vpiActual:
\_logic_net: (rst), line:29, parent:pre_decode_block
|vpiPort:
\_port: (fifo), parent:fb_fifo_block
|vpiName:fifo
|vpiHighConn:
\_ref_obj: (fifo), line:103
|vpiName:fifo
|vpiGenScopeArray:
\_gen_scope_array: (genblk1), line:65, parent:fb_fifo_block
|vpiName:genblk1
|vpiFullName:work@taiga_wrapper.cpu.pre_decode_block.fb_fifo_block.genblk1
|vpiGenScope:
\_gen_scope: , parent:genblk1
|vpiFullName:work@taiga_wrapper.cpu.pre_decode_block.fb_fifo_block.genblk1
|vpiProcess:
\_always: , line:68
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:68
|vpiCondition:
\_operation: , line:68
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:68
|vpiName:clk
|vpiFullName:work@taiga_wrapper.cpu.pre_decode_block.fb_fifo_block.genblk1.clk
|vpiStmt:
\_begin: , line:68
|vpiFullName:work@taiga_wrapper.cpu.pre_decode_block.fb_fifo_block.genblk1
|vpiStmt:
\_if_else: , line:69
|vpiCondition:
\_ref_obj: (rst), line:69
|vpiName:rst
|vpiFullName:work@taiga_wrapper.cpu.pre_decode_block.fb_fifo_block.genblk1.rst
|vpiStmt:
\_assignment: , line:70
|vpiOpType:82
|vpiLhs:
\_ref_obj: (inflight_count), line:70
|vpiName:inflight_count
|vpiFullName:work@taiga_wrapper.cpu.pre_decode_block.fb_fifo_block.genblk1.inflight_count
|vpiRhs:
\_constant: , line:70
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiElseStmt:
\_assignment: , line:72
|vpiOpType:82
|vpiLhs:
\_ref_obj: (inflight_count), line:72
|vpiName:inflight_count
|vpiFullName:work@taiga_wrapper.cpu.pre_decode_block.fb_fifo_block.genblk1.inflight_count
|vpiRhs:
\_operation: , line:72
|vpiOpType:11
|vpiOperand:
\_operation: , line:72
|vpiOpType:24
|vpiOperand:
\_ref_obj: (inflight_count), line:72
|vpiName:inflight_count
|vpiFullName:work@taiga_wrapper.cpu.pre_decode_block.fb_fifo_block.genblk1.inflight_count
|vpiOperand:
\_operation: , line:72
|vpiOpType:67
|vpiOperand:
\_ref_obj: (fifo.pop), line:72
|vpiName:fifo.pop
|vpiFullName:work@taiga_wrapper.cpu.pre_decode_block.fb_fifo_block.genblk1.fifo.pop
|vpiOperand:
\_operation: , line:72
|vpiOpType:67
|vpiOperand:
\_ref_obj: (supressed_push), line:72
|vpiName:supressed_push
|vpiFullName:work@taiga_wrapper.cpu.pre_decode_block.fb_fifo_block.genblk1.supressed_push
|vpiProcess:
\_always: , line:78
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:78
|vpiCondition:
\_operation: , line:78
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:78
|vpiName:clk
|vpiFullName:work@taiga_wrapper.cpu.pre_decode_block.fb_fifo_block.genblk1.clk
|vpiStmt:
\_begin: , line:78
|vpiFullName:work@taiga_wrapper.cpu.pre_decode_block.fb_fifo_block.genblk1
|vpiStmt:
\_if_else: , line:79
|vpiCondition:
\_ref_obj: (rst), line:79
|vpiName:rst
|vpiFullName:work@taiga_wrapper.cpu.pre_decode_block.fb_fifo_block.genblk1.rst
|vpiStmt:
\_begin: , line:79
|vpiFullName:work@taiga_wrapper.cpu.pre_decode_block.fb_fifo_block.genblk1
|vpiStmt:
\_assignment: , line:80
|vpiOpType:82
|vpiLhs:
\_ref_obj: (read_index), line:80
|vpiName:read_index
|vpiFullName:work@taiga_wrapper.cpu.pre_decode_block.fb_fifo_block.genblk1.read_index
|vpiRhs:
\_constant: , line:80
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiStmt:
\_assignment: , line:81
|vpiOpType:82
|vpiLhs:
\_ref_obj: (write_index), line:81
|vpiName:write_index
|vpiFullName:work@taiga_wrapper.cpu.pre_decode_block.fb_fifo_block.genblk1.write_index
|vpiRhs:
\_constant: , line:81
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiElseStmt:
\_begin: , line:83
|vpiFullName:work@taiga_wrapper.cpu.pre_decode_block.fb_fifo_block.genblk1
|vpiStmt:
\_assignment: , line:84
|vpiOpType:82
|vpiLhs:
\_ref_obj: (read_index), line:84
|vpiName:read_index
|vpiFullName:work@taiga_wrapper.cpu.pre_decode_block.fb_fifo_block.genblk1.read_index
|vpiRhs:
\_operation: , line:84
|vpiOpType:24
|vpiOperand:
\_ref_obj: (read_index), line:84
|vpiName:read_index
|vpiFullName:work@taiga_wrapper.cpu.pre_decode_block.fb_fifo_block.genblk1.read_index
|vpiOperand:
\_operation: , line:84
|vpiOpType:67
|vpiOperand:
\_ref_obj: (fifo.pop), line:84
|vpiName:fifo.pop
|vpiFullName:work@taiga_wrapper.cpu.pre_decode_block.fb_fifo_block.genblk1.fifo.pop
|vpiTypespec:
\_void_typespec: (LOG2_FIFO_DEPTH), line:84
|vpiName:LOG2_FIFO_DEPTH
|vpiStmt:
\_assignment: , line:85
|vpiOpType:82
|vpiLhs:
\_ref_obj: (write_index), line:85
|vpiName:write_index
|vpiFullName:work@taiga_wrapper.cpu.pre_decode_block.fb_fifo_block.genblk1.write_index
|vpiRhs:
\_operation: , line:85
|vpiOpType:24
|vpiOperand:
\_ref_obj: (write_index), line:85
|vpiName:write_index
|vpiFullName:work@taiga_wrapper.cpu.pre_decode_block.fb_fifo_block.genblk1.write_index
|vpiOperand:
\_operation: , line:85
|vpiOpType:67
|vpiOperand:
\_ref_obj: (supressed_push), line:85
|vpiName:supressed_push
|vpiFullName:work@taiga_wrapper.cpu.pre_decode_block.fb_fifo_block.genblk1.supressed_push
|vpiTypespec:
\_void_typespec: (LOG2_FIFO_DEPTH), line:85
|vpiName:LOG2_FIFO_DEPTH
|vpiProcess:
\_always: , line:89
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:89
|vpiCondition:
\_operation: , line:89
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:89
|vpiName:clk
|vpiFullName:work@taiga_wrapper.cpu.pre_decode_block.fb_fifo_block.genblk1.clk
|vpiStmt:
\_begin: , line:89
|vpiFullName:work@taiga_wrapper.cpu.pre_decode_block.fb_fifo_block.genblk1
|vpiStmt:
\_if_stmt: , line:90
|vpiCondition:
\_ref_obj: (fifo.push), line:90
|vpiName:fifo.push
|vpiFullName:work@taiga_wrapper.cpu.pre_decode_block.fb_fifo_block.genblk1.fifo.push
|vpiStmt:
\_assignment: , line:91
|vpiOpType:82
|vpiLhs:
\_bit_select: (lut_ram), line:91
|vpiName:lut_ram
|vpiFullName:work@taiga_wrapper.cpu.pre_decode_block.fb_fifo_block.genblk1.lut_ram
|vpiIndex:
\_ref_obj: (write_index), line:91
|vpiName:write_index
|vpiRhs:
\_ref_obj: (fifo.data_in), line:91
|vpiName:fifo.data_in
|vpiFullName:work@taiga_wrapper.cpu.pre_decode_block.fb_fifo_block.genblk1.fifo.data_in
|vpiContAssign:
\_cont_assign: , line:75
|vpiRhs:
\_bit_select: (inflight_count), line:75
|vpiName:inflight_count
|vpiFullName:work@taiga_wrapper.cpu.pre_decode_block.fb_fifo_block.genblk1.inflight_count
|vpiIndex:
\_ref_obj: (LOG2_FIFO_DEPTH), line:75
|vpiName:LOG2_FIFO_DEPTH
|vpiLhs:
\_ref_obj: (fifo.valid), line:75
|vpiName:fifo.valid
|vpiFullName:work@taiga_wrapper.cpu.pre_decode_block.fb_fifo_block.genblk1.fifo.valid
|vpiContAssign:
\_cont_assign: , line:76
|vpiRhs:
\_operation: , line:76
|vpiOpType:28
|vpiOperand:
\_ref_obj: (fifo.valid), line:76
|vpiName:fifo.valid
|vpiFullName:work@taiga_wrapper.cpu.pre_decode_block.fb_fifo_block.genblk1.fifo.valid
|vpiOperand:
\_operation: , line:76
|vpiOpType:8
|vpiOperand:
\_part_select: , line:76, parent:inflight_count
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (inflight_count)
|vpiLeftRange:
\_operation: , line:76
|vpiOpType:11
|vpiOperand:
\_ref_obj: (LOG2_FIFO_DEPTH), line:76
|vpiName:LOG2_FIFO_DEPTH
|vpiFullName:work@taiga_wrapper.cpu.pre_decode_block.fb_fifo_block.genblk1.LOG2_FIFO_DEPTH
|vpiOperand:
\_constant: , line:76
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:76
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiLhs:
\_ref_obj: (fifo.full), line:76
|vpiName:fifo.full
|vpiFullName:work@taiga_wrapper.cpu.pre_decode_block.fb_fifo_block.genblk1.fifo.full
|vpiContAssign:
\_cont_assign: , line:93
|vpiRhs:
\_bit_select: (lut_ram), line:93
|vpiName:lut_ram
|vpiFullName:work@taiga_wrapper.cpu.pre_decode_block.fb_fifo_block.genblk1.lut_ram
|vpiIndex:
\_ref_obj: (read_index), line:93
|vpiName:read_index
|vpiLhs:
\_ref_obj: (fifo.data_out), line:93
|vpiName:fifo.data_out
|vpiFullName:work@taiga_wrapper.cpu.pre_decode_block.fb_fifo_block.genblk1.fifo.data_out
|vpiParameter:
\_parameter: (ALU_UNIT_WB_ID), line:190
|vpiName:ALU_UNIT_WB_ID
|INT:32
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (BRANCH_PREDICTOR_WAYS), line:159
|vpiName:BRANCH_PREDICTOR_WAYS
|INT:9
|vpiParameter:
\_parameter: (BRANCH_TABLE_ENTRIES), line:160
|vpiName:BRANCH_TABLE_ENTRIES
|INT:4
|vpiParameter:
\_parameter: (BRANCH_UNIT_ID), line:195
|vpiName:BRANCH_UNIT_ID
|INT:8
|vpiParameter:
\_parameter: (BUS_ADDR_H), line:107
|vpiName:BUS_ADDR_H
|INT:1
|vpiParameter:
\_parameter: (BUS_ADDR_L), line:106
|vpiName:BUS_ADDR_L
|INT:0
|vpiParameter:
\_parameter: (BUS_BIT_CHECK), line:108
|vpiName:BUS_BIT_CHECK
|INT:1
|vpiParameter:
\_parameter: (BUS_TYPE), line:89
|vpiName:BUS_TYPE
|INT:5
|vpiParameter:
\_parameter: (COUNTER_W), line:42
|vpiName:COUNTER_W
|INT:33
|vpiParameter:
\_parameter: (CPU_ID), line:38
|vpiName:CPU_ID
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_ADDR_WIDTH), line:113
|vpiName:C_M_AXI_ADDR_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_DATA_WIDTH), line:114
|vpiName:C_M_AXI_DATA_WIDTH
|INT:1
|vpiParameter:
\_parameter: (DCACHE_LINES), line:133
|vpiName:DCACHE_LINES
|INT:-2146435073
|vpiParameter:
\_parameter: (DCACHE_LINE_ADDR_W), line:135
|vpiName:DCACHE_LINE_ADDR_W
|INT:1073741824
|vpiParameter:
\_parameter: (DCACHE_LINE_W), line:136
|vpiName:DCACHE_LINE_W
|INT:1342177279
|vpiParameter:
\_parameter: (DCACHE_SUB_LINE_ADDR_W), line:137
|vpiName:DCACHE_SUB_LINE_ADDR_W
|INT:4
|vpiParameter:
\_parameter: (DCACHE_TAG_W), line:138
|vpiName:DCACHE_TAG_W
|INT:1610612736
|vpiParameter:
\_parameter: (DCACHE_WAYS), line:134
|vpiName:DCACHE_WAYS
|INT:4
|vpiParameter:
\_parameter: (DIV_ALGORITHM), line:67
|vpiName:DIV_ALGORITHM
|INT:0
|vpiParameter:
\_parameter: (DIV_UNIT_WB_ID), line:192
|vpiName:DIV_UNIT_WB_ID
|INT:2
|vpiParameter:
\_parameter: (DTLB_DEPTH), line:152
|vpiName:DTLB_DEPTH
|INT:512
|vpiParameter:
\_parameter: (DTLB_WAYS), line:151
|vpiName:DTLB_WAYS
|INT:32
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (ENABLE_M_MODE), line:34
|vpiName:ENABLE_M_MODE
|INT:1
|vpiParameter:
\_parameter: (ENABLE_S_MODE), line:36
|vpiName:ENABLE_S_MODE
|INT:0
|vpiParameter:
\_parameter: (ENABLE_TRACE_INTERFACE), line:172
|vpiName:ENABLE_TRACE_INTERFACE
|INT:2
|vpiParameter:
\_parameter: (FETCH_BUFFER_DEPTH), line:168
|vpiName:FETCH_BUFFER_DEPTH
|INT:512
|vpiParameter:
\_parameter: (FPGA_VENDOR), line:27
|vpiName:FPGA_VENDOR
|STRING:"xilinx"
|vpiParameter:
\_parameter: (GC_UNIT_ID), line:196
|vpiName:GC_UNIT_ID
|INT:4
|vpiParameter:
\_parameter: (ICACHE_LINES), line:121
|vpiName:ICACHE_LINES
|INT:2
|vpiParameter:
\_parameter: (ICACHE_LINE_ADDR_W), line:123
|vpiName:ICACHE_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_LINE_W), line:124
|vpiName:ICACHE_LINE_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_SUB_LINE_ADDR_W), line:125
|vpiName:ICACHE_SUB_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_TAG_W), line:126
|vpiName:ICACHE_TAG_W
|INT:-2147483648
|vpiParameter:
\_parameter: (ICACHE_WAYS), line:122
|vpiName:ICACHE_WAYS
|INT:1
|vpiParameter:
\_parameter: (ITLB_DEPTH), line:146
|vpiName:ITLB_DEPTH
|INT:32
|vpiParameter:
\_parameter: (ITLB_WAYS), line:145
|vpiName:ITLB_WAYS
|INT:4
|vpiParameter:
\_parameter: (L1_CONNECTIONS), line:177
|vpiName:L1_CONNECTIONS
|INT:9
|vpiParameter:
\_parameter: (L1_DCACHE_ID), line:178
|vpiName:L1_DCACHE_ID
|INT:4
|vpiParameter:
\_parameter: (L1_DMMU_ID), line:179
|vpiName:L1_DMMU_ID
|INT:2
|vpiParameter:
\_parameter: (L1_ICACHE_ID), line:180
|vpiName:L1_ICACHE_ID
|INT:19
|vpiParameter:
\_parameter: (L1_IMMU_ID), line:181
|vpiName:L1_IMMU_ID
|INT:0
|vpiParameter:
\_parameter: (LS_UNIT_WB_ID), line:191
|vpiName:LS_UNIT_WB_ID
|INT:1
|vpiParameter:
\_parameter: (MAX_INFLIGHT_COUNT), line:167
|vpiName:MAX_INFLIGHT_COUNT
|INT:19
|vpiParameter:
\_parameter: (MEMORY_ADDR_H), line:103
|vpiName:MEMORY_ADDR_H
|INT:12
|vpiParameter:
\_parameter: (MEMORY_ADDR_L), line:102
|vpiName:MEMORY_ADDR_L
|INT:11
|vpiParameter:
\_parameter: (MEMORY_BIT_CHECK), line:104
|vpiName:MEMORY_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (MUL_UNIT_WB_ID), line:193
|vpiName:MUL_UNIT_WB_ID
|INT:512
|vpiParameter:
\_parameter: (NUM_UNITS), line:188
|vpiName:NUM_UNITS
|INT:2
|vpiParameter:
\_parameter: (NUM_WB_UNITS), line:186
|vpiName:NUM_WB_UNITS
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (RAS_DEPTH), line:161
|vpiName:RAS_DEPTH
|INT:2
|vpiParameter:
\_parameter: (RESET_VEC), line:39
|vpiName:RESET_VEC
|INT:-2147483648
|vpiParameter:
\_parameter: (SCRATCH_ADDR_H), line:99
|vpiName:SCRATCH_ADDR_H
|INT:9
|vpiParameter:
\_parameter: (SCRATCH_ADDR_L), line:98
|vpiName:SCRATCH_ADDR_L
|INT:8
|vpiParameter:
\_parameter: (SCRATCH_BIT_CHECK), line:100
|vpiName:SCRATCH_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (USE_AMO), line:70
|vpiName:USE_AMO
|INT:1
|vpiParameter:
\_parameter: (USE_BRANCH_PREDICTOR), line:158
|vpiName:USE_BRANCH_PREDICTOR
|INT:2
|vpiParameter:
\_parameter: (USE_BUS), line:88
|vpiName:USE_BUS
|INT:4
|vpiParameter:
\_parameter: (USE_DCACHE), line:92
|vpiName:USE_DCACHE
|INT:6
|vpiParameter:
\_parameter: (USE_DIV), line:49
|vpiName:USE_DIV
|INT:1
|vpiParameter:
\_parameter: (USE_DTAG_INVALIDATIONS), line:140
|vpiName:USE_DTAG_INVALIDATIONS
|INT:1879048191
|vpiParameter:
\_parameter: (USE_D_SCRATCH_MEM), line:79
|vpiName:USE_D_SCRATCH_MEM
|INT:3
|vpiParameter:
\_parameter: (USE_ICACHE), line:93
|vpiName:USE_ICACHE
|INT:7
|vpiParameter:
\_parameter: (USE_I_SCRATCH_MEM), line:78
|vpiName:USE_I_SCRATCH_MEM
|INT:2
|vpiParameter:
\_parameter: (USE_MUL), line:48
|vpiName:USE_MUL
|INT:1
|vpiParameter:
\_parameter: (WB_UNITS_WIDTH), line:187
|vpiName:WB_UNITS_WIDTH
|INT:32
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiNet:
\_logic_net: (clk), line:33, parent:fb_fifo_block
|vpiName:clk
|vpiFullName:work@taiga_wrapper.cpu.pre_decode_block.fb_fifo_block.clk
|vpiNetType:36
|vpiNet:
\_logic_net: (rst), line:34, parent:fb_fifo_block
|vpiNet:
\_logic_net: (write_index), line:41, parent:fb_fifo_block
|vpiName:write_index
|vpiFullName:work@taiga_wrapper.cpu.pre_decode_block.fb_fifo_block.write_index
|vpiNetType:36
|vpiRange:
\_range: , line:41
|vpiLeftRange:
\_constant: , line:41
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:41
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (read_index), line:42, parent:fb_fifo_block
|vpiName:read_index
|vpiFullName:work@taiga_wrapper.cpu.pre_decode_block.fb_fifo_block.read_index
|vpiNetType:36
|vpiRange:
\_range: , line:42
|vpiLeftRange:
\_constant: , line:42
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:42
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (inflight_count), line:43, parent:fb_fifo_block
|vpiName:inflight_count
|vpiFullName:work@taiga_wrapper.cpu.pre_decode_block.fb_fifo_block.inflight_count
|vpiNetType:36
|vpiRange:
\_range: , line:43
|vpiLeftRange:
\_constant: , line:43
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiRightRange:
\_constant: , line:43
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (supressed_push), line:44, parent:fb_fifo_block
|vpiName:supressed_push
|vpiFullName:work@taiga_wrapper.cpu.pre_decode_block.fb_fifo_block.supressed_push
|vpiNetType:36
|vpiNet:
\_logic_net: (fifo), line:35, parent:fb_fifo_block
|vpiName:fifo
|vpiFullName:work@taiga_wrapper.cpu.pre_decode_block.fb_fifo_block.fifo
|vpiInstance:
\_module: work@pre_decode (pre_decode_block), file:third_party/cores/taiga/core/taiga.sv, line:172, parent:cpu
|vpiArrayNet:
\_array_net: (lut_ram), line:40, parent:fb_fifo_block
|vpiName:lut_ram
|vpiFullName:work@taiga_wrapper.cpu.pre_decode_block.fb_fifo_block.lut_ram
|vpiSize:2
|vpiNet:
\_logic_net: , parent:lut_ram
|vpiFullName:work@taiga_wrapper.cpu.pre_decode_block.fb_fifo_block.lut_ram
|vpiNetType:36
|vpiRange:
\_range: , line:40
|vpiLeftRange:
\_constant: , line:40
|vpiDecompile:-1
|INT:-1
|vpiRightRange:
\_constant: , line:40
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiRange:
\_range: , line:40
|vpiLeftRange:
\_constant: , line:40
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:40
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiParameter:
\_parameter: (ALU_UNIT_WB_ID), line:190
|vpiName:ALU_UNIT_WB_ID
|INT:32
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (BRANCH_PREDICTOR_WAYS), line:159
|vpiName:BRANCH_PREDICTOR_WAYS
|INT:9
|vpiParameter:
\_parameter: (BRANCH_TABLE_ENTRIES), line:160
|vpiName:BRANCH_TABLE_ENTRIES
|INT:4
|vpiParameter:
\_parameter: (BRANCH_UNIT_ID), line:195
|vpiName:BRANCH_UNIT_ID
|INT:8
|vpiParameter:
\_parameter: (BUS_ADDR_H), line:107
|vpiName:BUS_ADDR_H
|INT:1
|vpiParameter:
\_parameter: (BUS_ADDR_L), line:106
|vpiName:BUS_ADDR_L
|INT:0
|vpiParameter:
\_parameter: (BUS_BIT_CHECK), line:108
|vpiName:BUS_BIT_CHECK
|INT:1
|vpiParameter:
\_parameter: (BUS_TYPE), line:89
|vpiName:BUS_TYPE
|INT:5
|vpiParameter:
\_parameter: (COUNTER_W), line:42
|vpiName:COUNTER_W
|INT:33
|vpiParameter:
\_parameter: (CPU_ID), line:38
|vpiName:CPU_ID
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_ADDR_WIDTH), line:113
|vpiName:C_M_AXI_ADDR_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_DATA_WIDTH), line:114
|vpiName:C_M_AXI_DATA_WIDTH
|INT:1
|vpiParameter:
\_parameter: (DATA_WIDTH), line:101
|vpiName:DATA_WIDTH
|INT:0
|vpiParameter:
\_parameter: (DCACHE_LINES), line:133
|vpiName:DCACHE_LINES
|INT:-2146435073
|vpiParameter:
\_parameter: (DCACHE_LINE_ADDR_W), line:135
|vpiName:DCACHE_LINE_ADDR_W
|INT:1073741824
|vpiParameter:
\_parameter: (DCACHE_LINE_W), line:136
|vpiName:DCACHE_LINE_W
|INT:1342177279
|vpiParameter:
\_parameter: (DCACHE_SUB_LINE_ADDR_W), line:137
|vpiName:DCACHE_SUB_LINE_ADDR_W
|INT:4
|vpiParameter:
\_parameter: (DCACHE_TAG_W), line:138
|vpiName:DCACHE_TAG_W
|INT:1610612736
|vpiParameter:
\_parameter: (DCACHE_WAYS), line:134
|vpiName:DCACHE_WAYS
|INT:4
|vpiParameter:
\_parameter: (DIV_ALGORITHM), line:67
|vpiName:DIV_ALGORITHM
|INT:0
|vpiParameter:
\_parameter: (DIV_UNIT_WB_ID), line:192
|vpiName:DIV_UNIT_WB_ID
|INT:2
|vpiParameter:
\_parameter: (DTLB_DEPTH), line:152
|vpiName:DTLB_DEPTH
|INT:512
|vpiParameter:
\_parameter: (DTLB_WAYS), line:151
|vpiName:DTLB_WAYS
|INT:32
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (ENABLE_M_MODE), line:34
|vpiName:ENABLE_M_MODE
|INT:1
|vpiParameter:
\_parameter: (ENABLE_S_MODE), line:36
|vpiName:ENABLE_S_MODE
|INT:0
|vpiParameter:
\_parameter: (ENABLE_TRACE_INTERFACE), line:172
|vpiName:ENABLE_TRACE_INTERFACE
|INT:2
|vpiParameter:
\_parameter: (FETCH_BUFFER_DEPTH), line:168
|vpiName:FETCH_BUFFER_DEPTH
|INT:512
|vpiParameter:
\_parameter: (FIFO_DEPTH), line:102
|vpiName:FIFO_DEPTH
|INT:512
|vpiParameter:
\_parameter: (FPGA_VENDOR), line:27
|vpiName:FPGA_VENDOR
|STRING:"xilinx"
|vpiParameter:
\_parameter: (GC_UNIT_ID), line:196
|vpiName:GC_UNIT_ID
|INT:4
|vpiParameter:
\_parameter: (ICACHE_LINES), line:121
|vpiName:ICACHE_LINES
|INT:2
|vpiParameter:
\_parameter: (ICACHE_LINE_ADDR_W), line:123
|vpiName:ICACHE_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_LINE_W), line:124
|vpiName:ICACHE_LINE_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_SUB_LINE_ADDR_W), line:125
|vpiName:ICACHE_SUB_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_TAG_W), line:126
|vpiName:ICACHE_TAG_W
|INT:-2147483648
|vpiParameter:
\_parameter: (ICACHE_WAYS), line:122
|vpiName:ICACHE_WAYS
|INT:1
|vpiParameter:
\_parameter: (ITLB_DEPTH), line:146
|vpiName:ITLB_DEPTH
|INT:32
|vpiParameter:
\_parameter: (ITLB_WAYS), line:145
|vpiName:ITLB_WAYS
|INT:4
|vpiParameter:
\_parameter: (L1_CONNECTIONS), line:177
|vpiName:L1_CONNECTIONS
|INT:9
|vpiParameter:
\_parameter: (L1_DCACHE_ID), line:178
|vpiName:L1_DCACHE_ID
|INT:4
|vpiParameter:
\_parameter: (L1_DMMU_ID), line:179
|vpiName:L1_DMMU_ID
|INT:2
|vpiParameter:
\_parameter: (L1_ICACHE_ID), line:180
|vpiName:L1_ICACHE_ID
|INT:19
|vpiParameter:
\_parameter: (L1_IMMU_ID), line:181
|vpiName:L1_IMMU_ID
|INT:0
|vpiParameter:
\_parameter: (LOG2_FIFO_DEPTH), line:38
|vpiName:LOG2_FIFO_DEPTH
|INT:2
|vpiParameter:
\_parameter: (LS_UNIT_WB_ID), line:191
|vpiName:LS_UNIT_WB_ID
|INT:1
|vpiParameter:
\_parameter: (MAX_INFLIGHT_COUNT), line:167
|vpiName:MAX_INFLIGHT_COUNT
|INT:19
|vpiParameter:
\_parameter: (MEMORY_ADDR_H), line:103
|vpiName:MEMORY_ADDR_H
|INT:12
|vpiParameter:
\_parameter: (MEMORY_ADDR_L), line:102
|vpiName:MEMORY_ADDR_L
|INT:11
|vpiParameter:
\_parameter: (MEMORY_BIT_CHECK), line:104
|vpiName:MEMORY_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (MUL_UNIT_WB_ID), line:193
|vpiName:MUL_UNIT_WB_ID
|INT:512
|vpiParameter:
\_parameter: (NUM_UNITS), line:188
|vpiName:NUM_UNITS
|INT:2
|vpiParameter:
\_parameter: (NUM_WB_UNITS), line:186
|vpiName:NUM_WB_UNITS
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (RAS_DEPTH), line:161
|vpiName:RAS_DEPTH
|INT:2
|vpiParameter:
\_parameter: (RESET_VEC), line:39
|vpiName:RESET_VEC
|INT:-2147483648
|vpiParameter:
\_parameter: (SCRATCH_ADDR_H), line:99
|vpiName:SCRATCH_ADDR_H
|INT:9
|vpiParameter:
\_parameter: (SCRATCH_ADDR_L), line:98
|vpiName:SCRATCH_ADDR_L
|INT:8
|vpiParameter:
\_parameter: (SCRATCH_BIT_CHECK), line:100
|vpiName:SCRATCH_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (USE_AMO), line:70
|vpiName:USE_AMO
|INT:1
|vpiParameter:
\_parameter: (USE_BRANCH_PREDICTOR), line:158
|vpiName:USE_BRANCH_PREDICTOR
|INT:2
|vpiParameter:
\_parameter: (USE_BUS), line:88
|vpiName:USE_BUS
|INT:4
|vpiParameter:
\_parameter: (USE_DCACHE), line:92
|vpiName:USE_DCACHE
|INT:6
|vpiParameter:
\_parameter: (USE_DIV), line:49
|vpiName:USE_DIV
|INT:1
|vpiParameter:
\_parameter: (USE_DTAG_INVALIDATIONS), line:140
|vpiName:USE_DTAG_INVALIDATIONS
|INT:1879048191
|vpiParameter:
\_parameter: (USE_D_SCRATCH_MEM), line:79
|vpiName:USE_D_SCRATCH_MEM
|INT:3
|vpiParameter:
\_parameter: (USE_ICACHE), line:93
|vpiName:USE_ICACHE
|INT:7
|vpiParameter:
\_parameter: (USE_I_SCRATCH_MEM), line:78
|vpiName:USE_I_SCRATCH_MEM
|INT:2
|vpiParameter:
\_parameter: (USE_MUL), line:48
|vpiName:USE_MUL
|INT:1
|vpiParameter:
\_parameter: (WB_UNITS_WIDTH), line:187
|vpiName:WB_UNITS_WIDTH
|INT:32
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiNet:
\_logic_net: (clk), line:28, parent:pre_decode_block
|vpiNet:
\_logic_net: (rst), line:29, parent:pre_decode_block
|vpiNet:
\_logic_net: (pre_decode_instruction), line:32, parent:pre_decode_block
|vpiNet:
\_logic_net: (pre_decode_pc), line:33, parent:pre_decode_block
|vpiNet:
\_logic_net: (branch_metadata), line:34, parent:pre_decode_block
|vpiNet:
\_logic_net: (branch_prediction_used), line:35, parent:pre_decode_block
|vpiNet:
\_logic_net: (bp_update_way), line:36, parent:pre_decode_block
|vpiNet:
\_logic_net: (pre_decode_push), line:37, parent:pre_decode_block
|vpiNet:
\_logic_net: (gc_fetch_flush), line:40, parent:pre_decode_block
|vpiNet:
\_logic_net: (pre_decode_pop), line:43, parent:pre_decode_block
|vpiNet:
\_logic_net: (fb_valid), line:44, parent:pre_decode_block
|vpiNet:
\_logic_net: (fb), line:45, parent:pre_decode_block
|vpiNet:
\_logic_net: (buffer_reset), line:48, parent:pre_decode_block
|vpiNet:
\_logic_net: (opcode), line:50, parent:pre_decode_block
|vpiName:opcode
|vpiFullName:work@taiga_wrapper.cpu.pre_decode_block.opcode
|vpiNetType:36
|vpiRange:
\_range: , line:50
|vpiLeftRange:
\_constant: , line:50
|vpiConstType:7
|vpiDecompile:6
|vpiSize:32
|INT:6
|vpiRightRange:
\_constant: , line:50
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (opcode_trimmed), line:51, parent:pre_decode_block
|vpiName:opcode_trimmed
|vpiFullName:work@taiga_wrapper.cpu.pre_decode_block.opcode_trimmed
|vpiNetType:36
|vpiRange:
\_range: , line:51
|vpiLeftRange:
\_constant: , line:51
|vpiConstType:7
|vpiDecompile:4
|vpiSize:32
|INT:4
|vpiRightRange:
\_constant: , line:51
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (rs1_addr), line:52, parent:pre_decode_block
|vpiName:rs1_addr
|vpiFullName:work@taiga_wrapper.cpu.pre_decode_block.rs1_addr
|vpiNetType:36
|vpiRange:
\_range: , line:52
|vpiLeftRange:
\_constant: , line:52
|vpiConstType:7
|vpiDecompile:4
|vpiSize:32
|INT:4
|vpiRightRange:
\_constant: , line:52
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (rs2_addr), line:53, parent:pre_decode_block
|vpiName:rs2_addr
|vpiFullName:work@taiga_wrapper.cpu.pre_decode_block.rs2_addr
|vpiNetType:36
|vpiRange:
\_range: , line:53
|vpiLeftRange:
\_constant: , line:53
|vpiConstType:7
|vpiDecompile:4
|vpiSize:32
|INT:4
|vpiRightRange:
\_constant: , line:53
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (rd_addr), line:54, parent:pre_decode_block
|vpiName:rd_addr
|vpiFullName:work@taiga_wrapper.cpu.pre_decode_block.rd_addr
|vpiNetType:36
|vpiRange:
\_range: , line:54
|vpiLeftRange:
\_constant: , line:54
|vpiConstType:7
|vpiDecompile:4
|vpiSize:32
|INT:4
|vpiRightRange:
\_constant: , line:54
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (fn3), line:55, parent:pre_decode_block
|vpiName:fn3
|vpiFullName:work@taiga_wrapper.cpu.pre_decode_block.fn3
|vpiNetType:36
|vpiRange:
\_range: , line:55
|vpiLeftRange:
\_constant: , line:55
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiRightRange:
\_constant: , line:55
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (csr_imm_op), line:57, parent:pre_decode_block
|vpiName:csr_imm_op
|vpiFullName:work@taiga_wrapper.cpu.pre_decode_block.csr_imm_op
|vpiNetType:36
|vpiNet:
\_logic_net: (sys_op), line:58, parent:pre_decode_block
|vpiName:sys_op
|vpiFullName:work@taiga_wrapper.cpu.pre_decode_block.sys_op
|vpiNetType:36
|vpiNet:
\_logic_net: (rs1_link), line:60, parent:pre_decode_block
|vpiName:rs1_link
|vpiFullName:work@taiga_wrapper.cpu.pre_decode_block.rs1_link
|vpiNetType:36
|vpiNet:
\_logic_net: (rd_link), line:60, parent:pre_decode_block
|vpiName:rd_link
|vpiFullName:work@taiga_wrapper.cpu.pre_decode_block.rd_link
|vpiNetType:36
|vpiNet:
\_logic_net: (rs1_eq_rd), line:60, parent:pre_decode_block
|vpiName:rs1_eq_rd
|vpiFullName:work@taiga_wrapper.cpu.pre_decode_block.rs1_eq_rd
|vpiNetType:36
|vpiNet:
\_logic_net: (use_ras), line:60, parent:pre_decode_block
|vpiName:use_ras
|vpiFullName:work@taiga_wrapper.cpu.pre_decode_block.use_ras
|vpiNetType:36
|vpiNet:
\_logic_net: (push_to_reg), line:62, parent:pre_decode_block
|vpiName:push_to_reg
|vpiFullName:work@taiga_wrapper.cpu.pre_decode_block.push_to_reg
|vpiNetType:36
|vpiNet:
\_logic_net: (sub_instruction), line:148, parent:pre_decode_block
|vpiName:sub_instruction
|vpiFullName:work@taiga_wrapper.cpu.pre_decode_block.sub_instruction
|vpiNetType:36
|vpiNet:
\_logic_net: (non_mul_div_arith_op), line:182, parent:pre_decode_block
|vpiName:non_mul_div_arith_op
|vpiFullName:work@taiga_wrapper.cpu.pre_decode_block.non_mul_div_arith_op
|vpiNetType:36
|vpiInstance:
\_module: work@taiga (cpu), file:third_party/cores/taiga/examples/zedboard/taiga_wrapper.sv, line:233, parent:work@taiga_wrapper
|vpiVariables:
\_struct_var: (data_in), line:64, parent:pre_decode_block
|vpiName:data_in
|vpiFullName:work@taiga_wrapper.cpu.pre_decode_block.data_in
|vpiTypespec:
\_struct_typespec: (fetch_buffer_packet_t), line:276
|vpiVariables:
\_struct_var: (data_out), line:65, parent:pre_decode_block
|vpiName:data_out
|vpiFullName:work@taiga_wrapper.cpu.pre_decode_block.data_out
|vpiTypespec:
\_struct_typespec: (fetch_buffer_packet_t), line:276
|vpiParameter:
\_parameter: (ALU_UNIT_WB_ID), line:190
|vpiName:ALU_UNIT_WB_ID
|INT:32
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (BRANCH_PREDICTOR_WAYS), line:159
|vpiName:BRANCH_PREDICTOR_WAYS
|INT:9
|vpiParameter:
\_parameter: (BRANCH_TABLE_ENTRIES), line:160
|vpiName:BRANCH_TABLE_ENTRIES
|INT:4
|vpiParameter:
\_parameter: (BRANCH_UNIT_ID), line:195
|vpiName:BRANCH_UNIT_ID
|INT:8
|vpiParameter:
\_parameter: (BUS_ADDR_H), line:107
|vpiName:BUS_ADDR_H
|INT:1
|vpiParameter:
\_parameter: (BUS_ADDR_L), line:106
|vpiName:BUS_ADDR_L
|INT:0
|vpiParameter:
\_parameter: (BUS_BIT_CHECK), line:108
|vpiName:BUS_BIT_CHECK
|INT:1
|vpiParameter:
\_parameter: (BUS_TYPE), line:89
|vpiName:BUS_TYPE
|INT:5
|vpiParameter:
\_parameter: (COUNTER_W), line:42
|vpiName:COUNTER_W
|INT:33
|vpiParameter:
\_parameter: (CPU_ID), line:38
|vpiName:CPU_ID
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_ADDR_WIDTH), line:113
|vpiName:C_M_AXI_ADDR_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_DATA_WIDTH), line:114
|vpiName:C_M_AXI_DATA_WIDTH
|INT:1
|vpiParameter:
\_parameter: (DCACHE_LINES), line:133
|vpiName:DCACHE_LINES
|INT:-2146435073
|vpiParameter:
\_parameter: (DCACHE_LINE_ADDR_W), line:135
|vpiName:DCACHE_LINE_ADDR_W
|INT:1073741824
|vpiParameter:
\_parameter: (DCACHE_LINE_W), line:136
|vpiName:DCACHE_LINE_W
|INT:1342177279
|vpiParameter:
\_parameter: (DCACHE_SUB_LINE_ADDR_W), line:137
|vpiName:DCACHE_SUB_LINE_ADDR_W
|INT:4
|vpiParameter:
\_parameter: (DCACHE_TAG_W), line:138
|vpiName:DCACHE_TAG_W
|INT:1610612736
|vpiParameter:
\_parameter: (DCACHE_WAYS), line:134
|vpiName:DCACHE_WAYS
|INT:4
|vpiParameter:
\_parameter: (DIV_ALGORITHM), line:67
|vpiName:DIV_ALGORITHM
|INT:0
|vpiParameter:
\_parameter: (DIV_UNIT_WB_ID), line:192
|vpiName:DIV_UNIT_WB_ID
|INT:2
|vpiParameter:
\_parameter: (DTLB_DEPTH), line:152
|vpiName:DTLB_DEPTH
|INT:512
|vpiParameter:
\_parameter: (DTLB_WAYS), line:151
|vpiName:DTLB_WAYS
|INT:32
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (ENABLE_M_MODE), line:34
|vpiName:ENABLE_M_MODE
|INT:1
|vpiParameter:
\_parameter: (ENABLE_S_MODE), line:36
|vpiName:ENABLE_S_MODE
|INT:0
|vpiParameter:
\_parameter: (ENABLE_TRACE_INTERFACE), line:172
|vpiName:ENABLE_TRACE_INTERFACE
|INT:2
|vpiParameter:
\_parameter: (FETCH_BUFFER_DEPTH), line:168
|vpiName:FETCH_BUFFER_DEPTH
|INT:512
|vpiParameter:
\_parameter: (FPGA_VENDOR), line:27
|vpiName:FPGA_VENDOR
|STRING:"xilinx"
|vpiParameter:
\_parameter: (GC_UNIT_ID), line:196
|vpiName:GC_UNIT_ID
|INT:4
|vpiParameter:
\_parameter: (ICACHE_LINES), line:121
|vpiName:ICACHE_LINES
|INT:2
|vpiParameter:
\_parameter: (ICACHE_LINE_ADDR_W), line:123
|vpiName:ICACHE_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_LINE_W), line:124
|vpiName:ICACHE_LINE_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_SUB_LINE_ADDR_W), line:125
|vpiName:ICACHE_SUB_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_TAG_W), line:126
|vpiName:ICACHE_TAG_W
|INT:-2147483648
|vpiParameter:
\_parameter: (ICACHE_WAYS), line:122
|vpiName:ICACHE_WAYS
|INT:1
|vpiParameter:
\_parameter: (ITLB_DEPTH), line:146
|vpiName:ITLB_DEPTH
|INT:32
|vpiParameter:
\_parameter: (ITLB_WAYS), line:145
|vpiName:ITLB_WAYS
|INT:4
|vpiParameter:
\_parameter: (L1_CONNECTIONS), line:177
|vpiName:L1_CONNECTIONS
|INT:9
|vpiParameter:
\_parameter: (L1_DCACHE_ID), line:178
|vpiName:L1_DCACHE_ID
|INT:4
|vpiParameter:
\_parameter: (L1_DMMU_ID), line:179
|vpiName:L1_DMMU_ID
|INT:2
|vpiParameter:
\_parameter: (L1_ICACHE_ID), line:180
|vpiName:L1_ICACHE_ID
|INT:19
|vpiParameter:
\_parameter: (L1_IMMU_ID), line:181
|vpiName:L1_IMMU_ID
|INT:0
|vpiParameter:
\_parameter: (LS_UNIT_WB_ID), line:191
|vpiName:LS_UNIT_WB_ID
|INT:1
|vpiParameter:
\_parameter: (MAX_INFLIGHT_COUNT), line:167
|vpiName:MAX_INFLIGHT_COUNT
|INT:19
|vpiParameter:
\_parameter: (MEMORY_ADDR_H), line:103
|vpiName:MEMORY_ADDR_H
|INT:12
|vpiParameter:
\_parameter: (MEMORY_ADDR_L), line:102
|vpiName:MEMORY_ADDR_L
|INT:11
|vpiParameter:
\_parameter: (MEMORY_BIT_CHECK), line:104
|vpiName:MEMORY_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (MUL_UNIT_WB_ID), line:193
|vpiName:MUL_UNIT_WB_ID
|INT:512
|vpiParameter:
\_parameter: (NUM_UNITS), line:188
|vpiName:NUM_UNITS
|INT:2
|vpiParameter:
\_parameter: (NUM_WB_UNITS), line:186
|vpiName:NUM_WB_UNITS
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (RAS_DEPTH), line:161
|vpiName:RAS_DEPTH
|INT:2
|vpiParameter:
\_parameter: (RESET_VEC), line:39
|vpiName:RESET_VEC
|INT:-2147483648
|vpiParameter:
\_parameter: (SCRATCH_ADDR_H), line:99
|vpiName:SCRATCH_ADDR_H
|INT:9
|vpiParameter:
\_parameter: (SCRATCH_ADDR_L), line:98
|vpiName:SCRATCH_ADDR_L
|INT:8
|vpiParameter:
\_parameter: (SCRATCH_BIT_CHECK), line:100
|vpiName:SCRATCH_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (USE_AMO), line:70
|vpiName:USE_AMO
|INT:1
|vpiParameter:
\_parameter: (USE_BRANCH_PREDICTOR), line:158
|vpiName:USE_BRANCH_PREDICTOR
|INT:2
|vpiParameter:
\_parameter: (USE_BUS), line:88
|vpiName:USE_BUS
|INT:4
|vpiParameter:
\_parameter: (USE_DCACHE), line:92
|vpiName:USE_DCACHE
|INT:6
|vpiParameter:
\_parameter: (USE_DIV), line:49
|vpiName:USE_DIV
|INT:1
|vpiParameter:
\_parameter: (USE_DTAG_INVALIDATIONS), line:140
|vpiName:USE_DTAG_INVALIDATIONS
|INT:1879048191
|vpiParameter:
\_parameter: (USE_D_SCRATCH_MEM), line:79
|vpiName:USE_D_SCRATCH_MEM
|INT:3
|vpiParameter:
\_parameter: (USE_ICACHE), line:93
|vpiName:USE_ICACHE
|INT:7
|vpiParameter:
\_parameter: (USE_I_SCRATCH_MEM), line:78
|vpiName:USE_I_SCRATCH_MEM
|INT:2
|vpiParameter:
\_parameter: (USE_MUL), line:48
|vpiName:USE_MUL
|INT:1
|vpiParameter:
\_parameter: (WB_UNITS_WIDTH), line:187
|vpiName:WB_UNITS_WIDTH
|INT:32
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiModule:
\_module: work@decode (decode_block), file:third_party/cores/taiga/core/taiga.sv, line:176, parent:cpu
|vpiDefName:work@decode
|vpiName:decode_block
|vpiFullName:work@taiga_wrapper.cpu.decode_block
|vpiPort:
\_port: (clk), line:27, parent:decode_block
|vpiName:clk
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (clk), line:176
|vpiName:clk
|vpiActual:
\_logic_net: (clk), line:27, parent:cpu
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (clk), line:27, parent:decode_block
|vpiName:clk
|vpiFullName:work@taiga_wrapper.cpu.decode_block.clk
|vpiNetType:36
|vpiPort:
\_port: (rst), line:28, parent:decode_block
|vpiName:rst
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (rst), line:176
|vpiName:rst
|vpiActual:
\_logic_net: (rst), line:28, parent:cpu
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (rst), line:28, parent:decode_block
|vpiName:rst
|vpiFullName:work@taiga_wrapper.cpu.decode_block.rst
|vpiNetType:36
|vpiPort:
\_port: (pre_decode_pop), line:30, parent:decode_block
|vpiName:pre_decode_pop
|vpiDirection:2
|vpiHighConn:
\_ref_obj: (pre_decode_pop), line:176
|vpiName:pre_decode_pop
|vpiActual:
\_logic_net: (pre_decode_pop), line:83, parent:cpu
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (pre_decode_pop), line:30, parent:decode_block
|vpiName:pre_decode_pop
|vpiFullName:work@taiga_wrapper.cpu.decode_block.pre_decode_pop
|vpiNetType:36
|vpiPort:
\_port: (fb_valid), line:31, parent:decode_block
|vpiName:fb_valid
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (fb_valid), line:176
|vpiName:fb_valid
|vpiActual:
\_logic_net: (fb_valid), line:89, parent:cpu
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (fb_valid), line:31, parent:decode_block
|vpiName:fb_valid
|vpiFullName:work@taiga_wrapper.cpu.decode_block.fb_valid
|vpiNetType:36
|vpiPort:
\_port: (fb), line:32, parent:decode_block
|vpiName:fb
|vpiDirection:1
|vpiTypedef:
\_struct_typespec: (fetch_buffer_packet_t), line:276
|vpiHighConn:
\_ref_obj: (fb), line:176
|vpiName:fb
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (fb), line:32, parent:decode_block
|vpiName:fb
|vpiFullName:work@taiga_wrapper.cpu.decode_block.fb
|vpiPort:
\_port: (ti), line:34, parent:decode_block
|vpiName:ti
|vpiDirection:5
|vpiHighConn:
\_ref_obj: (ti), line:176
|vpiName:ti
|vpiActual:
\_interface: work@tracking_interface (ti), file:third_party/cores/taiga/core/taiga.sv, line:69
|vpiDefName:work@tracking_interface
|vpiName:ti
|vpiModport:
\_modport: (decode)
|vpiName:decode
|vpiIODecl:
\_io_decl: (issue_id)
|vpiName:issue_id
|vpiDirection:1
|vpiIODecl:
\_io_decl: (id_available)
|vpiName:id_available
|vpiDirection:1
|vpiIODecl:
\_io_decl: (inflight_packet)
|vpiName:inflight_packet
|vpiDirection:2
|vpiIODecl:
\_io_decl: (issued)
|vpiName:issued
|vpiDirection:2
|vpiIODecl:
\_io_decl: (issue_unit_id)
|vpiName:issue_unit_id
|vpiDirection:2
|vpiInterface:
\_interface: work@tracking_interface (ti), file:third_party/cores/taiga/core/taiga.sv, line:69
|vpiModport:
\_modport: (wb)
|vpiName:wb
|vpiIODecl:
\_io_decl: (issue_id)
|vpiName:issue_id
|vpiDirection:2
|vpiIODecl:
\_io_decl: (id_available)
|vpiName:id_available
|vpiDirection:2
|vpiIODecl:
\_io_decl: (inflight_packet)
|vpiName:inflight_packet
|vpiDirection:1
|vpiIODecl:
\_io_decl: (issued)
|vpiName:issued
|vpiDirection:1
|vpiIODecl:
\_io_decl: (issue_unit_id)
|vpiName:issue_unit_id
|vpiDirection:1
|vpiInterface:
\_interface: work@tracking_interface (ti), file:third_party/cores/taiga/core/taiga.sv, line:69
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_modport: (decode)
|vpiName:decode
|vpiIODecl:
\_io_decl: (issue_id)
|vpiName:issue_id
|vpiDirection:1
|vpiIODecl:
\_io_decl: (id_available)
|vpiName:id_available
|vpiDirection:1
|vpiExpr:
\_logic_net: (id_available), line:147
|vpiName:id_available
|vpiNetType:36
|vpiIODecl:
\_io_decl: (inflight_packet)
|vpiName:inflight_packet
|vpiDirection:2
|vpiIODecl:
\_io_decl: (issued)
|vpiName:issued
|vpiDirection:2
|vpiExpr:
\_logic_net: (issued), line:150
|vpiName:issued
|vpiNetType:36
|vpiIODecl:
\_io_decl: (issue_unit_id)
|vpiName:issue_unit_id
|vpiDirection:2
|vpiExpr:
\_logic_net: (issue_unit_id), line:151
|vpiName:issue_unit_id
|vpiNetType:36
|vpiRange:
\_range: , line:151
|vpiLeftRange:
\_constant: , line:151
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:151
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiInterface:
\_interface: work@tracking_interface (ti), file:third_party/cores/taiga/core/taiga.sv, line:176
|vpiDefName:work@tracking_interface
|vpiName:ti
|vpiModport:
\_modport: (decode)
|vpiModport:
\_modport: (wb)
|vpiName:wb
|vpiIODecl:
\_io_decl: (issue_id)
|vpiName:issue_id
|vpiDirection:2
|vpiIODecl:
\_io_decl: (id_available)
|vpiName:id_available
|vpiDirection:2
|vpiExpr:
\_logic_net: (id_available), line:147
|vpiIODecl:
\_io_decl: (inflight_packet)
|vpiName:inflight_packet
|vpiDirection:1
|vpiIODecl:
\_io_decl: (issued)
|vpiName:issued
|vpiDirection:1
|vpiExpr:
\_logic_net: (issued), line:150
|vpiIODecl:
\_io_decl: (issue_unit_id)
|vpiName:issue_unit_id
|vpiDirection:1
|vpiExpr:
\_logic_net: (issue_unit_id), line:151
|vpiInterface:
\_interface: work@tracking_interface (ti), file:third_party/cores/taiga/core/taiga.sv, line:176
|vpiPort:
\_port: (rf_decode), line:35, parent:decode_block
|vpiName:rf_decode
|vpiDirection:5
|vpiHighConn:
\_ref_obj: (rf_decode), line:176
|vpiName:rf_decode
|vpiActual:
\_interface: work@register_file_decode_interface (rf_decode), file:third_party/cores/taiga/core/taiga.sv, line:56
|vpiDefName:work@register_file_decode_interface
|vpiName:rf_decode
|vpiModport:
\_modport: (decode)
|vpiName:decode
|vpiIODecl:
\_io_decl: (future_rd_addr)
|vpiName:future_rd_addr
|vpiDirection:2
|vpiIODecl:
\_io_decl: (rs1_addr)
|vpiName:rs1_addr
|vpiDirection:2
|vpiIODecl:
\_io_decl: (rs2_addr)
|vpiName:rs2_addr
|vpiDirection:2
|vpiIODecl:
\_io_decl: (instruction_issued)
|vpiName:instruction_issued
|vpiDirection:2
|vpiIODecl:
\_io_decl: (id)
|vpiName:id
|vpiDirection:2
|vpiIODecl:
\_io_decl: (uses_rs1)
|vpiName:uses_rs1
|vpiDirection:2
|vpiIODecl:
\_io_decl: (uses_rs2)
|vpiName:uses_rs2
|vpiDirection:2
|vpiIODecl:
\_io_decl: (rs1_conflict)
|vpiName:rs1_conflict
|vpiDirection:1
|vpiIODecl:
\_io_decl: (rs2_conflict)
|vpiName:rs2_conflict
|vpiDirection:1
|vpiIODecl:
\_io_decl: (rs1_data)
|vpiName:rs1_data
|vpiDirection:1
|vpiIODecl:
\_io_decl: (rs2_data)
|vpiName:rs2_data
|vpiDirection:1
|vpiIODecl:
\_io_decl: (rs2_id)
|vpiName:rs2_id
|vpiDirection:1
|vpiInterface:
\_interface: work@register_file_decode_interface (rf_decode), file:third_party/cores/taiga/core/taiga.sv, line:56
|vpiModport:
\_modport: (unit)
|vpiName:unit
|vpiIODecl:
\_io_decl: (future_rd_addr)
|vpiName:future_rd_addr
|vpiDirection:1
|vpiIODecl:
\_io_decl: (rs1_addr)
|vpiName:rs1_addr
|vpiDirection:1
|vpiIODecl:
\_io_decl: (rs2_addr)
|vpiName:rs2_addr
|vpiDirection:1
|vpiIODecl:
\_io_decl: (instruction_issued)
|vpiName:instruction_issued
|vpiDirection:1
|vpiIODecl:
\_io_decl: (id)
|vpiName:id
|vpiDirection:1
|vpiIODecl:
\_io_decl: (uses_rs1)
|vpiName:uses_rs1
|vpiDirection:1
|vpiIODecl:
\_io_decl: (uses_rs2)
|vpiName:uses_rs2
|vpiDirection:1
|vpiIODecl:
\_io_decl: (rs1_conflict)
|vpiName:rs1_conflict
|vpiDirection:2
|vpiIODecl:
\_io_decl: (rs2_conflict)
|vpiName:rs2_conflict
|vpiDirection:2
|vpiIODecl:
\_io_decl: (rs1_data)
|vpiName:rs1_data
|vpiDirection:2
|vpiIODecl:
\_io_decl: (rs2_data)
|vpiName:rs2_data
|vpiDirection:2
|vpiIODecl:
\_io_decl: (rs2_id)
|vpiName:rs2_id
|vpiDirection:2
|vpiInterface:
\_interface: work@register_file_decode_interface (rf_decode), file:third_party/cores/taiga/core/taiga.sv, line:56
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_modport: (decode)
|vpiName:decode
|vpiIODecl:
\_io_decl: (future_rd_addr)
|vpiName:future_rd_addr
|vpiDirection:2
|vpiExpr:
\_logic_net: (future_rd_addr), line:104
|vpiName:future_rd_addr
|vpiNetType:36
|vpiRange:
\_range: , line:104
|vpiLeftRange:
\_constant: , line:104
|vpiConstType:7
|vpiDecompile:4
|vpiSize:32
|INT:4
|vpiRightRange:
\_constant: , line:104
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (rs1_addr)
|vpiName:rs1_addr
|vpiDirection:2
|vpiExpr:
\_logic_net: (rs1_addr), line:105
|vpiName:rs1_addr
|vpiNetType:36
|vpiRange:
\_range: , line:105
|vpiLeftRange:
\_constant: , line:105
|vpiConstType:7
|vpiDecompile:4
|vpiSize:32
|INT:4
|vpiRightRange:
\_constant: , line:105
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (rs2_addr)
|vpiName:rs2_addr
|vpiDirection:2
|vpiExpr:
\_logic_net: (rs2_addr), line:107
|vpiName:rs2_addr
|vpiNetType:36
|vpiRange:
\_range: , line:107
|vpiLeftRange:
\_constant: , line:107
|vpiConstType:7
|vpiDecompile:4
|vpiSize:32
|INT:4
|vpiRightRange:
\_constant: , line:107
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (instruction_issued)
|vpiName:instruction_issued
|vpiDirection:2
|vpiExpr:
\_logic_net: (instruction_issued), line:116
|vpiName:instruction_issued
|vpiNetType:36
|vpiIODecl:
\_io_decl: (id)
|vpiName:id
|vpiDirection:2
|vpiIODecl:
\_io_decl: (uses_rs1)
|vpiName:uses_rs1
|vpiDirection:2
|vpiExpr:
\_logic_net: (uses_rs1), line:111
|vpiName:uses_rs1
|vpiNetType:36
|vpiIODecl:
\_io_decl: (uses_rs2)
|vpiName:uses_rs2
|vpiDirection:2
|vpiExpr:
\_logic_net: (uses_rs2), line:112
|vpiName:uses_rs2
|vpiNetType:36
|vpiIODecl:
\_io_decl: (rs1_conflict)
|vpiName:rs1_conflict
|vpiDirection:1
|vpiExpr:
\_logic_net: (rs1_conflict), line:113
|vpiName:rs1_conflict
|vpiNetType:36
|vpiIODecl:
\_io_decl: (rs2_conflict)
|vpiName:rs2_conflict
|vpiDirection:1
|vpiExpr:
\_logic_net: (rs2_conflict), line:114
|vpiName:rs2_conflict
|vpiNetType:36
|vpiIODecl:
\_io_decl: (rs1_data)
|vpiName:rs1_data
|vpiDirection:1
|vpiExpr:
\_logic_net: (rs1_data), line:106
|vpiName:rs1_data
|vpiNetType:36
|vpiRange:
\_range: , line:106
|vpiLeftRange:
\_constant: , line:106
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiRightRange:
\_constant: , line:106
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (rs2_data)
|vpiName:rs2_data
|vpiDirection:1
|vpiExpr:
\_logic_net: (rs2_data), line:108
|vpiName:rs2_data
|vpiNetType:36
|vpiRange:
\_range: , line:108
|vpiLeftRange:
\_constant: , line:108
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiRightRange:
\_constant: , line:108
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (rs2_id)
|vpiName:rs2_id
|vpiDirection:1
|vpiInterface:
\_interface: work@register_file_decode_interface (rf_decode), file:third_party/cores/taiga/core/taiga.sv, line:176
|vpiDefName:work@register_file_decode_interface
|vpiName:rf_decode
|vpiModport:
\_modport: (decode)
|vpiModport:
\_modport: (unit)
|vpiName:unit
|vpiIODecl:
\_io_decl: (future_rd_addr)
|vpiName:future_rd_addr
|vpiDirection:1
|vpiExpr:
\_logic_net: (future_rd_addr), line:104
|vpiIODecl:
\_io_decl: (rs1_addr)
|vpiName:rs1_addr
|vpiDirection:1
|vpiExpr:
\_logic_net: (rs1_addr), line:105
|vpiIODecl:
\_io_decl: (rs2_addr)
|vpiName:rs2_addr
|vpiDirection:1
|vpiExpr:
\_logic_net: (rs2_addr), line:107
|vpiIODecl:
\_io_decl: (instruction_issued)
|vpiName:instruction_issued
|vpiDirection:1
|vpiExpr:
\_logic_net: (instruction_issued), line:116
|vpiIODecl:
\_io_decl: (id)
|vpiName:id
|vpiDirection:1
|vpiIODecl:
\_io_decl: (uses_rs1)
|vpiName:uses_rs1
|vpiDirection:1
|vpiExpr:
\_logic_net: (uses_rs1), line:111
|vpiIODecl:
\_io_decl: (uses_rs2)
|vpiName:uses_rs2
|vpiDirection:1
|vpiExpr:
\_logic_net: (uses_rs2), line:112
|vpiIODecl:
\_io_decl: (rs1_conflict)
|vpiName:rs1_conflict
|vpiDirection:2
|vpiExpr:
\_logic_net: (rs1_conflict), line:113
|vpiIODecl:
\_io_decl: (rs2_conflict)
|vpiName:rs2_conflict
|vpiDirection:2
|vpiExpr:
\_logic_net: (rs2_conflict), line:114
|vpiIODecl:
\_io_decl: (rs1_data)
|vpiName:rs1_data
|vpiDirection:2
|vpiExpr:
\_logic_net: (rs1_data), line:106
|vpiIODecl:
\_io_decl: (rs2_data)
|vpiName:rs2_data
|vpiDirection:2
|vpiExpr:
\_logic_net: (rs2_data), line:108
|vpiIODecl:
\_io_decl: (rs2_id)
|vpiName:rs2_id
|vpiDirection:2
|vpiInterface:
\_interface: work@register_file_decode_interface (rf_decode), file:third_party/cores/taiga/core/taiga.sv, line:176
|vpiPort:
\_port: (alu_inputs), line:37, parent:decode_block
|vpiName:alu_inputs
|vpiDirection:2
|vpiTypedef:
\_struct_typespec: (alu_inputs_t), line:301
|vpiHighConn:
\_ref_obj: (alu_inputs), line:176
|vpiName:alu_inputs
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (alu_inputs), line:37, parent:decode_block
|vpiName:alu_inputs
|vpiFullName:work@taiga_wrapper.cpu.decode_block.alu_inputs
|vpiPort:
\_port: (ls_inputs), line:38, parent:decode_block
|vpiName:ls_inputs
|vpiDirection:2
|vpiTypedef:
\_struct_typespec: (load_store_inputs_t), line:369
|vpiHighConn:
\_ref_obj: (ls_inputs), line:176
|vpiName:ls_inputs
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (ls_inputs), line:38, parent:decode_block
|vpiName:ls_inputs
|vpiFullName:work@taiga_wrapper.cpu.decode_block.ls_inputs
|vpiPort:
\_port: (branch_inputs), line:39, parent:decode_block
|vpiName:branch_inputs
|vpiDirection:2
|vpiTypedef:
\_struct_typespec: (branch_inputs_t), line:313
|vpiHighConn:
\_ref_obj: (branch_inputs), line:176
|vpiName:branch_inputs
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (branch_inputs), line:39, parent:decode_block
|vpiName:branch_inputs
|vpiFullName:work@taiga_wrapper.cpu.decode_block.branch_inputs
|vpiPort:
\_port: (gc_inputs), line:40, parent:decode_block
|vpiName:gc_inputs
|vpiDirection:2
|vpiTypedef:
\_struct_typespec: (gc_inputs_t), line:404
|vpiHighConn:
\_ref_obj: (gc_inputs), line:176
|vpiName:gc_inputs
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (gc_inputs), line:40, parent:decode_block
|vpiName:gc_inputs
|vpiFullName:work@taiga_wrapper.cpu.decode_block.gc_inputs
|vpiPort:
\_port: (mul_inputs), line:41, parent:decode_block
|vpiName:mul_inputs
|vpiDirection:2
|vpiTypedef:
\_struct_typespec: (mul_inputs_t), line:383
|vpiHighConn:
\_ref_obj: (mul_inputs), line:176
|vpiName:mul_inputs
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (mul_inputs), line:41, parent:decode_block
|vpiName:mul_inputs
|vpiFullName:work@taiga_wrapper.cpu.decode_block.mul_inputs
|vpiPort:
\_port: (div_inputs), line:42, parent:decode_block
|vpiName:div_inputs
|vpiDirection:2
|vpiTypedef:
\_struct_typespec: (div_inputs_t), line:389
|vpiHighConn:
\_ref_obj: (div_inputs), line:176
|vpiName:div_inputs
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (div_inputs), line:42, parent:decode_block
|vpiName:div_inputs
|vpiFullName:work@taiga_wrapper.cpu.decode_block.div_inputs
|vpiPort:
\_port: (unit_issue), line:44, parent:decode_block
|vpiName:unit_issue
|vpiDirection:5
|vpiHighConn:
\_ref_obj: (unit_issue), line:176
|vpiName:unit_issue
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_modport: (decode)
|vpiName:decode
|vpiIODecl:
\_io_decl: (ready)
|vpiName:ready
|vpiDirection:1
|vpiExpr:
\_logic_net: (ready), line:58
|vpiName:ready
|vpiNetType:36
|vpiIODecl:
\_io_decl: (possible_issue)
|vpiName:possible_issue
|vpiDirection:2
|vpiExpr:
\_logic_net: (possible_issue), line:53
|vpiName:possible_issue
|vpiNetType:36
|vpiIODecl:
\_io_decl: (new_request)
|vpiName:new_request
|vpiDirection:2
|vpiExpr:
\_logic_net: (new_request), line:54
|vpiName:new_request
|vpiNetType:36
|vpiIODecl:
\_io_decl: (new_request_r)
|vpiName:new_request_r
|vpiDirection:2
|vpiExpr:
\_logic_net: (new_request_r), line:55
|vpiName:new_request_r
|vpiNetType:36
|vpiIODecl:
\_io_decl: (instruction_id)
|vpiName:instruction_id
|vpiDirection:2
|vpiInterface:
\_interface: work@unit_issue_interface (unit_issue), file:third_party/cores/taiga/core/taiga.sv, line:176
|vpiDefName:work@unit_issue_interface
|vpiName:unit_issue
|vpiModport:
\_modport: (decode)
|vpiModport:
\_modport: (unit)
|vpiName:unit
|vpiIODecl:
\_io_decl: (ready)
|vpiName:ready
|vpiDirection:2
|vpiExpr:
\_logic_net: (ready), line:58
|vpiIODecl:
\_io_decl: (possible_issue)
|vpiName:possible_issue
|vpiDirection:1
|vpiExpr:
\_logic_net: (possible_issue), line:53
|vpiIODecl:
\_io_decl: (new_request)
|vpiName:new_request
|vpiDirection:1
|vpiExpr:
\_logic_net: (new_request), line:54
|vpiIODecl:
\_io_decl: (new_request_r)
|vpiName:new_request_r
|vpiDirection:1
|vpiExpr:
\_logic_net: (new_request_r), line:55
|vpiIODecl:
\_io_decl: (instruction_id)
|vpiName:instruction_id
|vpiDirection:1
|vpiInterface:
\_interface: work@unit_issue_interface (unit_issue), file:third_party/cores/taiga/core/taiga.sv, line:176
|vpiPort:
\_port: (gc_issue_hold), line:46, parent:decode_block
|vpiName:gc_issue_hold
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (gc_issue_hold), line:176
|vpiName:gc_issue_hold
|vpiActual:
\_logic_net: (gc_issue_hold), line:93, parent:cpu
|vpiName:gc_issue_hold
|vpiFullName:work@taiga_wrapper.cpu.gc_issue_hold
|vpiNetType:36
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (gc_issue_hold), line:46, parent:decode_block
|vpiName:gc_issue_hold
|vpiFullName:work@taiga_wrapper.cpu.decode_block.gc_issue_hold
|vpiNetType:36
|vpiPort:
\_port: (gc_fetch_flush), line:47, parent:decode_block
|vpiName:gc_fetch_flush
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (gc_fetch_flush), line:176
|vpiName:gc_fetch_flush
|vpiActual:
\_logic_net: (gc_fetch_flush), line:95, parent:cpu
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (gc_fetch_flush), line:47, parent:decode_block
|vpiName:gc_fetch_flush
|vpiFullName:work@taiga_wrapper.cpu.decode_block.gc_fetch_flush
|vpiNetType:36
|vpiPort:
\_port: (gc_issue_flush), line:48, parent:decode_block
|vpiName:gc_issue_flush
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (gc_issue_flush), line:176
|vpiName:gc_issue_flush
|vpiActual:
\_logic_net: (gc_issue_flush), line:94, parent:cpu
|vpiName:gc_issue_flush
|vpiFullName:work@taiga_wrapper.cpu.gc_issue_flush
|vpiNetType:36
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (gc_issue_flush), line:48, parent:decode_block
|vpiName:gc_issue_flush
|vpiFullName:work@taiga_wrapper.cpu.decode_block.gc_issue_flush
|vpiNetType:36
|vpiPort:
\_port: (gc_flush_required), line:49, parent:decode_block
|vpiName:gc_flush_required
|vpiDirection:2
|vpiHighConn:
\_ref_obj: (gc_flush_required), line:176
|vpiName:gc_flush_required
|vpiActual:
\_logic_net: (gc_flush_required), line:115, parent:cpu
|vpiName:gc_flush_required
|vpiFullName:work@taiga_wrapper.cpu.gc_flush_required
|vpiNetType:36
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (gc_flush_required), line:49, parent:decode_block
|vpiName:gc_flush_required
|vpiFullName:work@taiga_wrapper.cpu.decode_block.gc_flush_required
|vpiNetType:36
|vpiPort:
\_port: (load_store_issue), line:51, parent:decode_block
|vpiName:load_store_issue
|vpiDirection:2
|vpiHighConn:
\_ref_obj: (load_store_issue), line:176
|vpiName:load_store_issue
|vpiActual:
\_logic_net: (load_store_issue), line:99, parent:cpu
|vpiName:load_store_issue
|vpiFullName:work@taiga_wrapper.cpu.load_store_issue
|vpiNetType:36
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (load_store_issue), line:51, parent:decode_block
|vpiName:load_store_issue
|vpiFullName:work@taiga_wrapper.cpu.decode_block.load_store_issue
|vpiNetType:36
|vpiPort:
\_port: (store_issued_with_data), line:52, parent:decode_block
|vpiName:store_issued_with_data
|vpiDirection:2
|vpiHighConn:
\_ref_obj: (store_issued_with_data), line:176
|vpiName:store_issued_with_data
|vpiActual:
\_logic_net: (store_issued_with_data), line:122, parent:cpu
|vpiName:store_issued_with_data
|vpiFullName:work@taiga_wrapper.cpu.store_issued_with_data
|vpiNetType:36
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (store_issued_with_data), line:52, parent:decode_block
|vpiName:store_issued_with_data
|vpiFullName:work@taiga_wrapper.cpu.decode_block.store_issued_with_data
|vpiNetType:36
|vpiPort:
\_port: (store_data), line:53, parent:decode_block
|vpiName:store_data
|vpiDirection:2
|vpiHighConn:
\_ref_obj: (store_data), line:176
|vpiName:store_data
|vpiActual:
\_logic_net: (store_data), line:123, parent:cpu
|vpiName:store_data
|vpiFullName:work@taiga_wrapper.cpu.store_data
|vpiNetType:36
|vpiRange:
\_range: , line:123
|vpiLeftRange:
\_constant: , line:123
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:123
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (store_data), line:53, parent:decode_block
|vpiName:store_data
|vpiFullName:work@taiga_wrapper.cpu.decode_block.store_data
|vpiNetType:36
|vpiRange:
\_range: , line:53
|vpiLeftRange:
\_constant: , line:53
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:53
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiPort:
\_port: (instruction_issued), line:55, parent:decode_block
|vpiName:instruction_issued
|vpiDirection:2
|vpiHighConn:
\_ref_obj: (instruction_issued), line:176
|vpiName:instruction_issued
|vpiActual:
\_logic_net: (instruction_issued), line:111, parent:cpu
|vpiName:instruction_issued
|vpiFullName:work@taiga_wrapper.cpu.instruction_issued
|vpiNetType:36
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (instruction_issued), line:116
|vpiPort:
\_port: (instruction_issued_no_rd), line:56, parent:decode_block
|vpiName:instruction_issued_no_rd
|vpiDirection:2
|vpiHighConn:
\_ref_obj: (instruction_issued_no_rd), line:176
|vpiName:instruction_issued_no_rd
|vpiActual:
\_logic_net: (instruction_issued_no_rd), line:112, parent:cpu
|vpiName:instruction_issued_no_rd
|vpiFullName:work@taiga_wrapper.cpu.instruction_issued_no_rd
|vpiNetType:36
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (instruction_issued_no_rd), line:56, parent:decode_block
|vpiName:instruction_issued_no_rd
|vpiFullName:work@taiga_wrapper.cpu.decode_block.instruction_issued_no_rd
|vpiNetType:36
|vpiPort:
\_port: (instruction_issued_with_rd), line:57, parent:decode_block
|vpiName:instruction_issued_with_rd
|vpiDirection:2
|vpiHighConn:
\_ref_obj: (instruction_issued_with_rd), line:176
|vpiName:instruction_issued_with_rd
|vpiActual:
\_logic_net: (instruction_issued_with_rd), line:113, parent:cpu
|vpiName:instruction_issued_with_rd
|vpiFullName:work@taiga_wrapper.cpu.instruction_issued_with_rd
|vpiNetType:36
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (instruction_issued_with_rd), line:57, parent:decode_block
|vpiName:instruction_issued_with_rd
|vpiFullName:work@taiga_wrapper.cpu.decode_block.instruction_issued_with_rd
|vpiNetType:36
|vpiPort:
\_port: (illegal_instruction), line:58, parent:decode_block
|vpiName:illegal_instruction
|vpiDirection:2
|vpiHighConn:
\_ref_obj: (illegal_instruction), line:176
|vpiName:illegal_instruction
|vpiActual:
\_logic_net: (illegal_instruction), line:108, parent:cpu
|vpiName:illegal_instruction
|vpiFullName:work@taiga_wrapper.cpu.illegal_instruction
|vpiNetType:36
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (illegal_instruction), line:58, parent:decode_block
|vpiName:illegal_instruction
|vpiFullName:work@taiga_wrapper.cpu.decode_block.illegal_instruction
|vpiNetType:36
|vpiPort:
\_port: (tr_operand_stall), line:61, parent:decode_block
|vpiName:tr_operand_stall
|vpiDirection:2
|vpiHighConn:
\_ref_obj: (tr_operand_stall), line:176
|vpiName:tr_operand_stall
|vpiActual:
\_logic_net: (tr_operand_stall), line:126, parent:cpu
|vpiName:tr_operand_stall
|vpiFullName:work@taiga_wrapper.cpu.tr_operand_stall
|vpiNetType:36
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (tr_operand_stall), line:61, parent:decode_block
|vpiName:tr_operand_stall
|vpiFullName:work@taiga_wrapper.cpu.decode_block.tr_operand_stall
|vpiNetType:36
|vpiPort:
\_port: (tr_unit_stall), line:62, parent:decode_block
|vpiName:tr_unit_stall
|vpiDirection:2
|vpiHighConn:
\_ref_obj: (tr_unit_stall), line:176
|vpiName:tr_unit_stall
|vpiActual:
\_logic_net: (tr_unit_stall), line:127, parent:cpu
|vpiName:tr_unit_stall
|vpiFullName:work@taiga_wrapper.cpu.tr_unit_stall
|vpiNetType:36
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (tr_unit_stall), line:62, parent:decode_block
|vpiName:tr_unit_stall
|vpiFullName:work@taiga_wrapper.cpu.decode_block.tr_unit_stall
|vpiNetType:36
|vpiPort:
\_port: (tr_no_id_stall), line:63, parent:decode_block
|vpiName:tr_no_id_stall
|vpiDirection:2
|vpiHighConn:
\_ref_obj: (tr_no_id_stall), line:176
|vpiName:tr_no_id_stall
|vpiActual:
\_logic_net: (tr_no_id_stall), line:128, parent:cpu
|vpiName:tr_no_id_stall
|vpiFullName:work@taiga_wrapper.cpu.tr_no_id_stall
|vpiNetType:36
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (tr_no_id_stall), line:63, parent:decode_block
|vpiName:tr_no_id_stall
|vpiFullName:work@taiga_wrapper.cpu.decode_block.tr_no_id_stall
|vpiNetType:36
|vpiPort:
\_port: (tr_no_instruction_stall), line:64, parent:decode_block
|vpiName:tr_no_instruction_stall
|vpiDirection:2
|vpiHighConn:
\_ref_obj: (tr_no_instruction_stall), line:176
|vpiName:tr_no_instruction_stall
|vpiActual:
\_logic_net: (tr_no_instruction_stall), line:129, parent:cpu
|vpiName:tr_no_instruction_stall
|vpiFullName:work@taiga_wrapper.cpu.tr_no_instruction_stall
|vpiNetType:36
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (tr_no_instruction_stall), line:64, parent:decode_block
|vpiName:tr_no_instruction_stall
|vpiFullName:work@taiga_wrapper.cpu.decode_block.tr_no_instruction_stall
|vpiNetType:36
|vpiPort:
\_port: (tr_other_stall), line:65, parent:decode_block
|vpiName:tr_other_stall
|vpiDirection:2
|vpiHighConn:
\_ref_obj: (tr_other_stall), line:176
|vpiName:tr_other_stall
|vpiActual:
\_logic_net: (tr_other_stall), line:130, parent:cpu
|vpiName:tr_other_stall
|vpiFullName:work@taiga_wrapper.cpu.tr_other_stall
|vpiNetType:36
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (tr_other_stall), line:65, parent:decode_block
|vpiName:tr_other_stall
|vpiFullName:work@taiga_wrapper.cpu.decode_block.tr_other_stall
|vpiNetType:36
|vpiPort:
\_port: (tr_branch_operand_stall), line:66, parent:decode_block
|vpiName:tr_branch_operand_stall
|vpiDirection:2
|vpiHighConn:
\_ref_obj: (tr_branch_operand_stall), line:176
|vpiName:tr_branch_operand_stall
|vpiActual:
\_logic_net: (tr_branch_operand_stall), line:131, parent:cpu
|vpiName:tr_branch_operand_stall
|vpiFullName:work@taiga_wrapper.cpu.tr_branch_operand_stall
|vpiNetType:36
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (tr_branch_operand_stall), line:66, parent:decode_block
|vpiName:tr_branch_operand_stall
|vpiFullName:work@taiga_wrapper.cpu.decode_block.tr_branch_operand_stall
|vpiNetType:36
|vpiPort:
\_port: (tr_alu_operand_stall), line:67, parent:decode_block
|vpiName:tr_alu_operand_stall
|vpiDirection:2
|vpiHighConn:
\_ref_obj: (tr_alu_operand_stall), line:176
|vpiName:tr_alu_operand_stall
|vpiActual:
\_logic_net: (tr_alu_operand_stall), line:132, parent:cpu
|vpiName:tr_alu_operand_stall
|vpiFullName:work@taiga_wrapper.cpu.tr_alu_operand_stall
|vpiNetType:36
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (tr_alu_operand_stall), line:67, parent:decode_block
|vpiName:tr_alu_operand_stall
|vpiFullName:work@taiga_wrapper.cpu.decode_block.tr_alu_operand_stall
|vpiNetType:36
|vpiPort:
\_port: (tr_ls_operand_stall), line:68, parent:decode_block
|vpiName:tr_ls_operand_stall
|vpiDirection:2
|vpiHighConn:
\_ref_obj: (tr_ls_operand_stall), line:176
|vpiName:tr_ls_operand_stall
|vpiActual:
\_logic_net: (tr_ls_operand_stall), line:133, parent:cpu
|vpiName:tr_ls_operand_stall
|vpiFullName:work@taiga_wrapper.cpu.tr_ls_operand_stall
|vpiNetType:36
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (tr_ls_operand_stall), line:68, parent:decode_block
|vpiName:tr_ls_operand_stall
|vpiFullName:work@taiga_wrapper.cpu.decode_block.tr_ls_operand_stall
|vpiNetType:36
|vpiPort:
\_port: (tr_div_operand_stall), line:69, parent:decode_block
|vpiName:tr_div_operand_stall
|vpiDirection:2
|vpiHighConn:
\_ref_obj: (tr_div_operand_stall), line:176
|vpiName:tr_div_operand_stall
|vpiActual:
\_logic_net: (tr_div_operand_stall), line:134, parent:cpu
|vpiName:tr_div_operand_stall
|vpiFullName:work@taiga_wrapper.cpu.tr_div_operand_stall
|vpiNetType:36
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (tr_div_operand_stall), line:69, parent:decode_block
|vpiName:tr_div_operand_stall
|vpiFullName:work@taiga_wrapper.cpu.decode_block.tr_div_operand_stall
|vpiNetType:36
|vpiPort:
\_port: (tr_instruction_issued_dec), line:71, parent:decode_block
|vpiName:tr_instruction_issued_dec
|vpiDirection:2
|vpiHighConn:
\_ref_obj: (tr_instruction_issued_dec), line:176
|vpiName:tr_instruction_issued_dec
|vpiActual:
\_logic_net: (tr_instruction_issued_dec), line:136, parent:cpu
|vpiName:tr_instruction_issued_dec
|vpiFullName:work@taiga_wrapper.cpu.tr_instruction_issued_dec
|vpiNetType:36
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (tr_instruction_issued_dec), line:71, parent:decode_block
|vpiName:tr_instruction_issued_dec
|vpiFullName:work@taiga_wrapper.cpu.decode_block.tr_instruction_issued_dec
|vpiNetType:36
|vpiPort:
\_port: (tr_instruction_pc_dec), line:72, parent:decode_block
|vpiName:tr_instruction_pc_dec
|vpiDirection:2
|vpiHighConn:
\_ref_obj: (tr_instruction_pc_dec), line:176
|vpiName:tr_instruction_pc_dec
|vpiActual:
\_logic_net: (tr_instruction_pc_dec), line:137, parent:cpu
|vpiName:tr_instruction_pc_dec
|vpiFullName:work@taiga_wrapper.cpu.tr_instruction_pc_dec
|vpiNetType:36
|vpiRange:
\_range: , line:137
|vpiLeftRange:
\_constant: , line:137
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:137
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (tr_instruction_pc_dec), line:72, parent:decode_block
|vpiName:tr_instruction_pc_dec
|vpiFullName:work@taiga_wrapper.cpu.decode_block.tr_instruction_pc_dec
|vpiNetType:36
|vpiRange:
\_range: , line:72
|vpiLeftRange:
\_constant: , line:72
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:72
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiPort:
\_port: (tr_instruction_data_dec), line:73, parent:decode_block
|vpiName:tr_instruction_data_dec
|vpiDirection:2
|vpiHighConn:
\_ref_obj: (tr_instruction_data_dec), line:176
|vpiName:tr_instruction_data_dec
|vpiActual:
\_logic_net: (tr_instruction_data_dec), line:138, parent:cpu
|vpiName:tr_instruction_data_dec
|vpiFullName:work@taiga_wrapper.cpu.tr_instruction_data_dec
|vpiNetType:36
|vpiRange:
\_range: , line:138
|vpiLeftRange:
\_constant: , line:138
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:138
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (tr_instruction_data_dec), line:73, parent:decode_block
|vpiName:tr_instruction_data_dec
|vpiFullName:work@taiga_wrapper.cpu.decode_block.tr_instruction_data_dec
|vpiNetType:36
|vpiRange:
\_range: , line:73
|vpiLeftRange:
\_constant: , line:73
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:73
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiGenScopeArray:
\_gen_scope_array: (genblk1), line:177, parent:decode_block
|vpiName:genblk1
|vpiFullName:work@taiga_wrapper.cpu.decode_block.genblk1
|vpiGenScope:
\_gen_scope: , parent:genblk1
|vpiFullName:work@taiga_wrapper.cpu.decode_block.genblk1
|vpiContAssign:
\_cont_assign: , line:178
|vpiRhs:
\_operation: , line:178
|vpiOpType:26
|vpiOperand:
\_operation: , line:178
|vpiOpType:26
|vpiOperand:
\_operation: , line:178
|vpiOpType:14
|vpiOperand:
\_ref_obj: (opcode_trim), line:178
|vpiName:opcode_trim
|vpiFullName:work@taiga_wrapper.cpu.decode_block.genblk1.opcode_trim
|vpiOperand:
\_ref_obj: (ARITH_T), line:178
|vpiName:ARITH_T
|vpiFullName:work@taiga_wrapper.cpu.decode_block.genblk1.ARITH_T
|vpiOperand:
\_ref_obj: (mult_div_op), line:178
|vpiName:mult_div_op
|vpiFullName:work@taiga_wrapper.cpu.decode_block.genblk1.mult_div_op
|vpiOperand:
\_operation: , line:178
|vpiOpType:4
|vpiOperand:
\_bit_select: (fn3), line:178
|vpiName:fn3
|vpiIndex:
\_constant: , line:178
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiLhs:
\_bit_select: (unit_requested), line:178
|vpiName:unit_requested
|vpiFullName:work@taiga_wrapper.cpu.decode_block.genblk1.unit_requested
|vpiIndex:
\_ref_obj: (MUL_UNIT_WB_ID), line:178
|vpiName:MUL_UNIT_WB_ID
|vpiParameter:
\_parameter: (ALU_UNIT_WB_ID), line:190
|vpiName:ALU_UNIT_WB_ID
|INT:32
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (BRANCH_PREDICTOR_WAYS), line:159
|vpiName:BRANCH_PREDICTOR_WAYS
|INT:9
|vpiParameter:
\_parameter: (BRANCH_TABLE_ENTRIES), line:160
|vpiName:BRANCH_TABLE_ENTRIES
|INT:4
|vpiParameter:
\_parameter: (BRANCH_UNIT_ID), line:195
|vpiName:BRANCH_UNIT_ID
|INT:8
|vpiParameter:
\_parameter: (BUS_ADDR_H), line:107
|vpiName:BUS_ADDR_H
|INT:1
|vpiParameter:
\_parameter: (BUS_ADDR_L), line:106
|vpiName:BUS_ADDR_L
|INT:0
|vpiParameter:
\_parameter: (BUS_BIT_CHECK), line:108
|vpiName:BUS_BIT_CHECK
|INT:1
|vpiParameter:
\_parameter: (BUS_TYPE), line:89
|vpiName:BUS_TYPE
|INT:5
|vpiParameter:
\_parameter: (COUNTER_W), line:42
|vpiName:COUNTER_W
|INT:33
|vpiParameter:
\_parameter: (CPU_ID), line:38
|vpiName:CPU_ID
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_ADDR_WIDTH), line:113
|vpiName:C_M_AXI_ADDR_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_DATA_WIDTH), line:114
|vpiName:C_M_AXI_DATA_WIDTH
|INT:1
|vpiParameter:
\_parameter: (DCACHE_LINES), line:133
|vpiName:DCACHE_LINES
|INT:-2146435073
|vpiParameter:
\_parameter: (DCACHE_LINE_ADDR_W), line:135
|vpiName:DCACHE_LINE_ADDR_W
|INT:1073741824
|vpiParameter:
\_parameter: (DCACHE_LINE_W), line:136
|vpiName:DCACHE_LINE_W
|INT:1342177279
|vpiParameter:
\_parameter: (DCACHE_SUB_LINE_ADDR_W), line:137
|vpiName:DCACHE_SUB_LINE_ADDR_W
|INT:4
|vpiParameter:
\_parameter: (DCACHE_TAG_W), line:138
|vpiName:DCACHE_TAG_W
|INT:1610612736
|vpiParameter:
\_parameter: (DCACHE_WAYS), line:134
|vpiName:DCACHE_WAYS
|INT:4
|vpiParameter:
\_parameter: (DIV_ALGORITHM), line:67
|vpiName:DIV_ALGORITHM
|INT:0
|vpiParameter:
\_parameter: (DIV_UNIT_WB_ID), line:192
|vpiName:DIV_UNIT_WB_ID
|INT:2
|vpiParameter:
\_parameter: (DTLB_DEPTH), line:152
|vpiName:DTLB_DEPTH
|INT:512
|vpiParameter:
\_parameter: (DTLB_WAYS), line:151
|vpiName:DTLB_WAYS
|INT:32
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (ENABLE_M_MODE), line:34
|vpiName:ENABLE_M_MODE
|INT:1
|vpiParameter:
\_parameter: (ENABLE_S_MODE), line:36
|vpiName:ENABLE_S_MODE
|INT:0
|vpiParameter:
\_parameter: (ENABLE_TRACE_INTERFACE), line:172
|vpiName:ENABLE_TRACE_INTERFACE
|INT:2
|vpiParameter:
\_parameter: (FETCH_BUFFER_DEPTH), line:168
|vpiName:FETCH_BUFFER_DEPTH
|INT:512
|vpiParameter:
\_parameter: (FPGA_VENDOR), line:27
|vpiName:FPGA_VENDOR
|STRING:"xilinx"
|vpiParameter:
\_parameter: (GC_UNIT_ID), line:196
|vpiName:GC_UNIT_ID
|INT:4
|vpiParameter:
\_parameter: (ICACHE_LINES), line:121
|vpiName:ICACHE_LINES
|INT:2
|vpiParameter:
\_parameter: (ICACHE_LINE_ADDR_W), line:123
|vpiName:ICACHE_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_LINE_W), line:124
|vpiName:ICACHE_LINE_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_SUB_LINE_ADDR_W), line:125
|vpiName:ICACHE_SUB_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_TAG_W), line:126
|vpiName:ICACHE_TAG_W
|INT:-2147483648
|vpiParameter:
\_parameter: (ICACHE_WAYS), line:122
|vpiName:ICACHE_WAYS
|INT:1
|vpiParameter:
\_parameter: (ITLB_DEPTH), line:146
|vpiName:ITLB_DEPTH
|INT:32
|vpiParameter:
\_parameter: (ITLB_WAYS), line:145
|vpiName:ITLB_WAYS
|INT:4
|vpiParameter:
\_parameter: (L1_CONNECTIONS), line:177
|vpiName:L1_CONNECTIONS
|INT:9
|vpiParameter:
\_parameter: (L1_DCACHE_ID), line:178
|vpiName:L1_DCACHE_ID
|INT:4
|vpiParameter:
\_parameter: (L1_DMMU_ID), line:179
|vpiName:L1_DMMU_ID
|INT:2
|vpiParameter:
\_parameter: (L1_ICACHE_ID), line:180
|vpiName:L1_ICACHE_ID
|INT:19
|vpiParameter:
\_parameter: (L1_IMMU_ID), line:181
|vpiName:L1_IMMU_ID
|INT:0
|vpiParameter:
\_parameter: (LS_UNIT_WB_ID), line:191
|vpiName:LS_UNIT_WB_ID
|INT:1
|vpiParameter:
\_parameter: (MAX_INFLIGHT_COUNT), line:167
|vpiName:MAX_INFLIGHT_COUNT
|INT:19
|vpiParameter:
\_parameter: (MEMORY_ADDR_H), line:103
|vpiName:MEMORY_ADDR_H
|INT:12
|vpiParameter:
\_parameter: (MEMORY_ADDR_L), line:102
|vpiName:MEMORY_ADDR_L
|INT:11
|vpiParameter:
\_parameter: (MEMORY_BIT_CHECK), line:104
|vpiName:MEMORY_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (MUL_UNIT_WB_ID), line:193
|vpiName:MUL_UNIT_WB_ID
|INT:512
|vpiParameter:
\_parameter: (NUM_UNITS), line:188
|vpiName:NUM_UNITS
|INT:2
|vpiParameter:
\_parameter: (NUM_WB_UNITS), line:186
|vpiName:NUM_WB_UNITS
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (RAS_DEPTH), line:161
|vpiName:RAS_DEPTH
|INT:2
|vpiParameter:
\_parameter: (RESET_VEC), line:39
|vpiName:RESET_VEC
|INT:-2147483648
|vpiParameter:
\_parameter: (SCRATCH_ADDR_H), line:99
|vpiName:SCRATCH_ADDR_H
|INT:9
|vpiParameter:
\_parameter: (SCRATCH_ADDR_L), line:98
|vpiName:SCRATCH_ADDR_L
|INT:8
|vpiParameter:
\_parameter: (SCRATCH_BIT_CHECK), line:100
|vpiName:SCRATCH_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (USE_AMO), line:70
|vpiName:USE_AMO
|INT:1
|vpiParameter:
\_parameter: (USE_BRANCH_PREDICTOR), line:158
|vpiName:USE_BRANCH_PREDICTOR
|INT:2
|vpiParameter:
\_parameter: (USE_BUS), line:88
|vpiName:USE_BUS
|INT:4
|vpiParameter:
\_parameter: (USE_DCACHE), line:92
|vpiName:USE_DCACHE
|INT:6
|vpiParameter:
\_parameter: (USE_DIV), line:49
|vpiName:USE_DIV
|INT:1
|vpiParameter:
\_parameter: (USE_DTAG_INVALIDATIONS), line:140
|vpiName:USE_DTAG_INVALIDATIONS
|INT:1879048191
|vpiParameter:
\_parameter: (USE_D_SCRATCH_MEM), line:79
|vpiName:USE_D_SCRATCH_MEM
|INT:3
|vpiParameter:
\_parameter: (USE_ICACHE), line:93
|vpiName:USE_ICACHE
|INT:7
|vpiParameter:
\_parameter: (USE_I_SCRATCH_MEM), line:78
|vpiName:USE_I_SCRATCH_MEM
|INT:2
|vpiParameter:
\_parameter: (USE_MUL), line:48
|vpiName:USE_MUL
|INT:1
|vpiParameter:
\_parameter: (WB_UNITS_WIDTH), line:187
|vpiName:WB_UNITS_WIDTH
|INT:32
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiGenScopeArray:
\_gen_scope_array: (genblk2), line:181, parent:decode_block
|vpiName:genblk2
|vpiFullName:work@taiga_wrapper.cpu.decode_block.genblk2
|vpiGenScope:
\_gen_scope: , parent:genblk2
|vpiFullName:work@taiga_wrapper.cpu.decode_block.genblk2
|vpiContAssign:
\_cont_assign: , line:182
|vpiRhs:
\_operation: , line:182
|vpiOpType:26
|vpiOperand:
\_operation: , line:182
|vpiOpType:26
|vpiOperand:
\_operation: , line:182
|vpiOpType:14
|vpiOperand:
\_ref_obj: (opcode_trim), line:182
|vpiName:opcode_trim
|vpiFullName:work@taiga_wrapper.cpu.decode_block.genblk2.opcode_trim
|vpiOperand:
\_ref_obj: (ARITH_T), line:182
|vpiName:ARITH_T
|vpiFullName:work@taiga_wrapper.cpu.decode_block.genblk2.ARITH_T
|vpiOperand:
\_ref_obj: (mult_div_op), line:182
|vpiName:mult_div_op
|vpiFullName:work@taiga_wrapper.cpu.decode_block.genblk2.mult_div_op
|vpiOperand:
\_bit_select: (fn3), line:182
|vpiName:fn3
|vpiFullName:work@taiga_wrapper.cpu.decode_block.genblk2.fn3
|vpiIndex:
\_constant: , line:182
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiLhs:
\_bit_select: (unit_requested), line:182
|vpiName:unit_requested
|vpiFullName:work@taiga_wrapper.cpu.decode_block.genblk2.unit_requested
|vpiIndex:
\_ref_obj: (DIV_UNIT_WB_ID), line:182
|vpiName:DIV_UNIT_WB_ID
|vpiParameter:
\_parameter: (ALU_UNIT_WB_ID), line:190
|vpiName:ALU_UNIT_WB_ID
|INT:32
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (BRANCH_PREDICTOR_WAYS), line:159
|vpiName:BRANCH_PREDICTOR_WAYS
|INT:9
|vpiParameter:
\_parameter: (BRANCH_TABLE_ENTRIES), line:160
|vpiName:BRANCH_TABLE_ENTRIES
|INT:4
|vpiParameter:
\_parameter: (BRANCH_UNIT_ID), line:195
|vpiName:BRANCH_UNIT_ID
|INT:8
|vpiParameter:
\_parameter: (BUS_ADDR_H), line:107
|vpiName:BUS_ADDR_H
|INT:1
|vpiParameter:
\_parameter: (BUS_ADDR_L), line:106
|vpiName:BUS_ADDR_L
|INT:0
|vpiParameter:
\_parameter: (BUS_BIT_CHECK), line:108
|vpiName:BUS_BIT_CHECK
|INT:1
|vpiParameter:
\_parameter: (BUS_TYPE), line:89
|vpiName:BUS_TYPE
|INT:5
|vpiParameter:
\_parameter: (COUNTER_W), line:42
|vpiName:COUNTER_W
|INT:33
|vpiParameter:
\_parameter: (CPU_ID), line:38
|vpiName:CPU_ID
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_ADDR_WIDTH), line:113
|vpiName:C_M_AXI_ADDR_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_DATA_WIDTH), line:114
|vpiName:C_M_AXI_DATA_WIDTH
|INT:1
|vpiParameter:
\_parameter: (DCACHE_LINES), line:133
|vpiName:DCACHE_LINES
|INT:-2146435073
|vpiParameter:
\_parameter: (DCACHE_LINE_ADDR_W), line:135
|vpiName:DCACHE_LINE_ADDR_W
|INT:1073741824
|vpiParameter:
\_parameter: (DCACHE_LINE_W), line:136
|vpiName:DCACHE_LINE_W
|INT:1342177279
|vpiParameter:
\_parameter: (DCACHE_SUB_LINE_ADDR_W), line:137
|vpiName:DCACHE_SUB_LINE_ADDR_W
|INT:4
|vpiParameter:
\_parameter: (DCACHE_TAG_W), line:138
|vpiName:DCACHE_TAG_W
|INT:1610612736
|vpiParameter:
\_parameter: (DCACHE_WAYS), line:134
|vpiName:DCACHE_WAYS
|INT:4
|vpiParameter:
\_parameter: (DIV_ALGORITHM), line:67
|vpiName:DIV_ALGORITHM
|INT:0
|vpiParameter:
\_parameter: (DIV_UNIT_WB_ID), line:192
|vpiName:DIV_UNIT_WB_ID
|INT:2
|vpiParameter:
\_parameter: (DTLB_DEPTH), line:152
|vpiName:DTLB_DEPTH
|INT:512
|vpiParameter:
\_parameter: (DTLB_WAYS), line:151
|vpiName:DTLB_WAYS
|INT:32
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (ENABLE_M_MODE), line:34
|vpiName:ENABLE_M_MODE
|INT:1
|vpiParameter:
\_parameter: (ENABLE_S_MODE), line:36
|vpiName:ENABLE_S_MODE
|INT:0
|vpiParameter:
\_parameter: (ENABLE_TRACE_INTERFACE), line:172
|vpiName:ENABLE_TRACE_INTERFACE
|INT:2
|vpiParameter:
\_parameter: (FETCH_BUFFER_DEPTH), line:168
|vpiName:FETCH_BUFFER_DEPTH
|INT:512
|vpiParameter:
\_parameter: (FPGA_VENDOR), line:27
|vpiName:FPGA_VENDOR
|STRING:"xilinx"
|vpiParameter:
\_parameter: (GC_UNIT_ID), line:196
|vpiName:GC_UNIT_ID
|INT:4
|vpiParameter:
\_parameter: (ICACHE_LINES), line:121
|vpiName:ICACHE_LINES
|INT:2
|vpiParameter:
\_parameter: (ICACHE_LINE_ADDR_W), line:123
|vpiName:ICACHE_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_LINE_W), line:124
|vpiName:ICACHE_LINE_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_SUB_LINE_ADDR_W), line:125
|vpiName:ICACHE_SUB_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_TAG_W), line:126
|vpiName:ICACHE_TAG_W
|INT:-2147483648
|vpiParameter:
\_parameter: (ICACHE_WAYS), line:122
|vpiName:ICACHE_WAYS
|INT:1
|vpiParameter:
\_parameter: (ITLB_DEPTH), line:146
|vpiName:ITLB_DEPTH
|INT:32
|vpiParameter:
\_parameter: (ITLB_WAYS), line:145
|vpiName:ITLB_WAYS
|INT:4
|vpiParameter:
\_parameter: (L1_CONNECTIONS), line:177
|vpiName:L1_CONNECTIONS
|INT:9
|vpiParameter:
\_parameter: (L1_DCACHE_ID), line:178
|vpiName:L1_DCACHE_ID
|INT:4
|vpiParameter:
\_parameter: (L1_DMMU_ID), line:179
|vpiName:L1_DMMU_ID
|INT:2
|vpiParameter:
\_parameter: (L1_ICACHE_ID), line:180
|vpiName:L1_ICACHE_ID
|INT:19
|vpiParameter:
\_parameter: (L1_IMMU_ID), line:181
|vpiName:L1_IMMU_ID
|INT:0
|vpiParameter:
\_parameter: (LS_UNIT_WB_ID), line:191
|vpiName:LS_UNIT_WB_ID
|INT:1
|vpiParameter:
\_parameter: (MAX_INFLIGHT_COUNT), line:167
|vpiName:MAX_INFLIGHT_COUNT
|INT:19
|vpiParameter:
\_parameter: (MEMORY_ADDR_H), line:103
|vpiName:MEMORY_ADDR_H
|INT:12
|vpiParameter:
\_parameter: (MEMORY_ADDR_L), line:102
|vpiName:MEMORY_ADDR_L
|INT:11
|vpiParameter:
\_parameter: (MEMORY_BIT_CHECK), line:104
|vpiName:MEMORY_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (MUL_UNIT_WB_ID), line:193
|vpiName:MUL_UNIT_WB_ID
|INT:512
|vpiParameter:
\_parameter: (NUM_UNITS), line:188
|vpiName:NUM_UNITS
|INT:2
|vpiParameter:
\_parameter: (NUM_WB_UNITS), line:186
|vpiName:NUM_WB_UNITS
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (RAS_DEPTH), line:161
|vpiName:RAS_DEPTH
|INT:2
|vpiParameter:
\_parameter: (RESET_VEC), line:39
|vpiName:RESET_VEC
|INT:-2147483648
|vpiParameter:
\_parameter: (SCRATCH_ADDR_H), line:99
|vpiName:SCRATCH_ADDR_H
|INT:9
|vpiParameter:
\_parameter: (SCRATCH_ADDR_L), line:98
|vpiName:SCRATCH_ADDR_L
|INT:8
|vpiParameter:
\_parameter: (SCRATCH_BIT_CHECK), line:100
|vpiName:SCRATCH_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (USE_AMO), line:70
|vpiName:USE_AMO
|INT:1
|vpiParameter:
\_parameter: (USE_BRANCH_PREDICTOR), line:158
|vpiName:USE_BRANCH_PREDICTOR
|INT:2
|vpiParameter:
\_parameter: (USE_BUS), line:88
|vpiName:USE_BUS
|INT:4
|vpiParameter:
\_parameter: (USE_DCACHE), line:92
|vpiName:USE_DCACHE
|INT:6
|vpiParameter:
\_parameter: (USE_DIV), line:49
|vpiName:USE_DIV
|INT:1
|vpiParameter:
\_parameter: (USE_DTAG_INVALIDATIONS), line:140
|vpiName:USE_DTAG_INVALIDATIONS
|INT:1879048191
|vpiParameter:
\_parameter: (USE_D_SCRATCH_MEM), line:79
|vpiName:USE_D_SCRATCH_MEM
|INT:3
|vpiParameter:
\_parameter: (USE_ICACHE), line:93
|vpiName:USE_ICACHE
|INT:7
|vpiParameter:
\_parameter: (USE_I_SCRATCH_MEM), line:78
|vpiName:USE_I_SCRATCH_MEM
|INT:2
|vpiParameter:
\_parameter: (USE_MUL), line:48
|vpiName:USE_MUL
|INT:1
|vpiParameter:
\_parameter: (WB_UNITS_WIDTH), line:187
|vpiName:WB_UNITS_WIDTH
|INT:32
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiGenScopeArray:
\_gen_scope_array: (genblk3[0]), line:190, parent:decode_block
|vpiName:genblk3[0]
|vpiFullName:work@taiga_wrapper.cpu.decode_block.genblk3[0]
|vpiGenScope:
\_gen_scope: , parent:genblk3[0]
|vpiFullName:work@taiga_wrapper.cpu.decode_block.genblk3[0]
|vpiContAssign:
\_cont_assign: , line:191
|vpiRhs:
\_bit_select: (unit_issue.ready), line:191
|vpiName:unit_issue.ready
|vpiFullName:work@taiga_wrapper.cpu.decode_block.genblk3[0].unit_issue.ready
|vpiIndex:
\_ref_obj: (i), line:191
|vpiName:i
|vpiLhs:
\_bit_select: (unit_ready), line:191
|vpiName:unit_ready
|vpiFullName:work@taiga_wrapper.cpu.decode_block.genblk3[0].unit_ready
|vpiIndex:
\_ref_obj: (i), line:191
|vpiName:i
|vpiParameter:
\_parameter: (ALU_UNIT_WB_ID), line:190
|vpiName:ALU_UNIT_WB_ID
|INT:32
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (BRANCH_PREDICTOR_WAYS), line:159
|vpiName:BRANCH_PREDICTOR_WAYS
|INT:9
|vpiParameter:
\_parameter: (BRANCH_TABLE_ENTRIES), line:160
|vpiName:BRANCH_TABLE_ENTRIES
|INT:4
|vpiParameter:
\_parameter: (BRANCH_UNIT_ID), line:195
|vpiName:BRANCH_UNIT_ID
|INT:8
|vpiParameter:
\_parameter: (BUS_ADDR_H), line:107
|vpiName:BUS_ADDR_H
|INT:1
|vpiParameter:
\_parameter: (BUS_ADDR_L), line:106
|vpiName:BUS_ADDR_L
|INT:0
|vpiParameter:
\_parameter: (BUS_BIT_CHECK), line:108
|vpiName:BUS_BIT_CHECK
|INT:1
|vpiParameter:
\_parameter: (BUS_TYPE), line:89
|vpiName:BUS_TYPE
|INT:5
|vpiParameter:
\_parameter: (COUNTER_W), line:42
|vpiName:COUNTER_W
|INT:33
|vpiParameter:
\_parameter: (CPU_ID), line:38
|vpiName:CPU_ID
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_ADDR_WIDTH), line:113
|vpiName:C_M_AXI_ADDR_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_DATA_WIDTH), line:114
|vpiName:C_M_AXI_DATA_WIDTH
|INT:1
|vpiParameter:
\_parameter: (DCACHE_LINES), line:133
|vpiName:DCACHE_LINES
|INT:-2146435073
|vpiParameter:
\_parameter: (DCACHE_LINE_ADDR_W), line:135
|vpiName:DCACHE_LINE_ADDR_W
|INT:1073741824
|vpiParameter:
\_parameter: (DCACHE_LINE_W), line:136
|vpiName:DCACHE_LINE_W
|INT:1342177279
|vpiParameter:
\_parameter: (DCACHE_SUB_LINE_ADDR_W), line:137
|vpiName:DCACHE_SUB_LINE_ADDR_W
|INT:4
|vpiParameter:
\_parameter: (DCACHE_TAG_W), line:138
|vpiName:DCACHE_TAG_W
|INT:1610612736
|vpiParameter:
\_parameter: (DCACHE_WAYS), line:134
|vpiName:DCACHE_WAYS
|INT:4
|vpiParameter:
\_parameter: (DIV_ALGORITHM), line:67
|vpiName:DIV_ALGORITHM
|INT:0
|vpiParameter:
\_parameter: (DIV_UNIT_WB_ID), line:192
|vpiName:DIV_UNIT_WB_ID
|INT:2
|vpiParameter:
\_parameter: (DTLB_DEPTH), line:152
|vpiName:DTLB_DEPTH
|INT:512
|vpiParameter:
\_parameter: (DTLB_WAYS), line:151
|vpiName:DTLB_WAYS
|INT:32
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (ENABLE_M_MODE), line:34
|vpiName:ENABLE_M_MODE
|INT:1
|vpiParameter:
\_parameter: (ENABLE_S_MODE), line:36
|vpiName:ENABLE_S_MODE
|INT:0
|vpiParameter:
\_parameter: (ENABLE_TRACE_INTERFACE), line:172
|vpiName:ENABLE_TRACE_INTERFACE
|INT:2
|vpiParameter:
\_parameter: (FETCH_BUFFER_DEPTH), line:168
|vpiName:FETCH_BUFFER_DEPTH
|INT:512
|vpiParameter:
\_parameter: (FPGA_VENDOR), line:27
|vpiName:FPGA_VENDOR
|STRING:"xilinx"
|vpiParameter:
\_parameter: (GC_UNIT_ID), line:196
|vpiName:GC_UNIT_ID
|INT:4
|vpiParameter:
\_parameter: (ICACHE_LINES), line:121
|vpiName:ICACHE_LINES
|INT:2
|vpiParameter:
\_parameter: (ICACHE_LINE_ADDR_W), line:123
|vpiName:ICACHE_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_LINE_W), line:124
|vpiName:ICACHE_LINE_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_SUB_LINE_ADDR_W), line:125
|vpiName:ICACHE_SUB_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_TAG_W), line:126
|vpiName:ICACHE_TAG_W
|INT:-2147483648
|vpiParameter:
\_parameter: (ICACHE_WAYS), line:122
|vpiName:ICACHE_WAYS
|INT:1
|vpiParameter:
\_parameter: (ITLB_DEPTH), line:146
|vpiName:ITLB_DEPTH
|INT:32
|vpiParameter:
\_parameter: (ITLB_WAYS), line:145
|vpiName:ITLB_WAYS
|INT:4
|vpiParameter:
\_parameter: (L1_CONNECTIONS), line:177
|vpiName:L1_CONNECTIONS
|INT:9
|vpiParameter:
\_parameter: (L1_DCACHE_ID), line:178
|vpiName:L1_DCACHE_ID
|INT:4
|vpiParameter:
\_parameter: (L1_DMMU_ID), line:179
|vpiName:L1_DMMU_ID
|INT:2
|vpiParameter:
\_parameter: (L1_ICACHE_ID), line:180
|vpiName:L1_ICACHE_ID
|INT:19
|vpiParameter:
\_parameter: (L1_IMMU_ID), line:181
|vpiName:L1_IMMU_ID
|INT:0
|vpiParameter:
\_parameter: (LS_UNIT_WB_ID), line:191
|vpiName:LS_UNIT_WB_ID
|INT:1
|vpiParameter:
\_parameter: (MAX_INFLIGHT_COUNT), line:167
|vpiName:MAX_INFLIGHT_COUNT
|INT:19
|vpiParameter:
\_parameter: (MEMORY_ADDR_H), line:103
|vpiName:MEMORY_ADDR_H
|INT:12
|vpiParameter:
\_parameter: (MEMORY_ADDR_L), line:102
|vpiName:MEMORY_ADDR_L
|INT:11
|vpiParameter:
\_parameter: (MEMORY_BIT_CHECK), line:104
|vpiName:MEMORY_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (MUL_UNIT_WB_ID), line:193
|vpiName:MUL_UNIT_WB_ID
|INT:512
|vpiParameter:
\_parameter: (NUM_UNITS), line:188
|vpiName:NUM_UNITS
|INT:2
|vpiParameter:
\_parameter: (NUM_WB_UNITS), line:186
|vpiName:NUM_WB_UNITS
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (RAS_DEPTH), line:161
|vpiName:RAS_DEPTH
|INT:2
|vpiParameter:
\_parameter: (RESET_VEC), line:39
|vpiName:RESET_VEC
|INT:-2147483648
|vpiParameter:
\_parameter: (SCRATCH_ADDR_H), line:99
|vpiName:SCRATCH_ADDR_H
|INT:9
|vpiParameter:
\_parameter: (SCRATCH_ADDR_L), line:98
|vpiName:SCRATCH_ADDR_L
|INT:8
|vpiParameter:
\_parameter: (SCRATCH_BIT_CHECK), line:100
|vpiName:SCRATCH_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (USE_AMO), line:70
|vpiName:USE_AMO
|INT:1
|vpiParameter:
\_parameter: (USE_BRANCH_PREDICTOR), line:158
|vpiName:USE_BRANCH_PREDICTOR
|INT:2
|vpiParameter:
\_parameter: (USE_BUS), line:88
|vpiName:USE_BUS
|INT:4
|vpiParameter:
\_parameter: (USE_DCACHE), line:92
|vpiName:USE_DCACHE
|INT:6
|vpiParameter:
\_parameter: (USE_DIV), line:49
|vpiName:USE_DIV
|INT:1
|vpiParameter:
\_parameter: (USE_DTAG_INVALIDATIONS), line:140
|vpiName:USE_DTAG_INVALIDATIONS
|INT:1879048191
|vpiParameter:
\_parameter: (USE_D_SCRATCH_MEM), line:79
|vpiName:USE_D_SCRATCH_MEM
|INT:3
|vpiParameter:
\_parameter: (USE_ICACHE), line:93
|vpiName:USE_ICACHE
|INT:7
|vpiParameter:
\_parameter: (USE_I_SCRATCH_MEM), line:78
|vpiName:USE_I_SCRATCH_MEM
|INT:2
|vpiParameter:
\_parameter: (USE_MUL), line:48
|vpiName:USE_MUL
|INT:1
|vpiParameter:
\_parameter: (WB_UNITS_WIDTH), line:187
|vpiName:WB_UNITS_WIDTH
|INT:32
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiParameter:
\_parameter: (i), line:190
|vpiName:i
|INT:0
|vpiGenScopeArray:
\_gen_scope_array: (genblk3[1]), line:190, parent:decode_block
|vpiName:genblk3[1]
|vpiFullName:work@taiga_wrapper.cpu.decode_block.genblk3[1]
|vpiGenScope:
\_gen_scope: , parent:genblk3[1]
|vpiFullName:work@taiga_wrapper.cpu.decode_block.genblk3[1]
|vpiContAssign:
\_cont_assign: , line:191
|vpiRhs:
\_bit_select: (unit_issue.ready), line:191
|vpiName:unit_issue.ready
|vpiFullName:work@taiga_wrapper.cpu.decode_block.genblk3[1].unit_issue.ready
|vpiIndex:
\_ref_obj: (i), line:191
|vpiName:i
|vpiLhs:
\_bit_select: (unit_ready), line:191
|vpiName:unit_ready
|vpiFullName:work@taiga_wrapper.cpu.decode_block.genblk3[1].unit_ready
|vpiIndex:
\_ref_obj: (i), line:191
|vpiName:i
|vpiParameter:
\_parameter: (ALU_UNIT_WB_ID), line:190
|vpiName:ALU_UNIT_WB_ID
|INT:32
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (BRANCH_PREDICTOR_WAYS), line:159
|vpiName:BRANCH_PREDICTOR_WAYS
|INT:9
|vpiParameter:
\_parameter: (BRANCH_TABLE_ENTRIES), line:160
|vpiName:BRANCH_TABLE_ENTRIES
|INT:4
|vpiParameter:
\_parameter: (BRANCH_UNIT_ID), line:195
|vpiName:BRANCH_UNIT_ID
|INT:8
|vpiParameter:
\_parameter: (BUS_ADDR_H), line:107
|vpiName:BUS_ADDR_H
|INT:1
|vpiParameter:
\_parameter: (BUS_ADDR_L), line:106
|vpiName:BUS_ADDR_L
|INT:0
|vpiParameter:
\_parameter: (BUS_BIT_CHECK), line:108
|vpiName:BUS_BIT_CHECK
|INT:1
|vpiParameter:
\_parameter: (BUS_TYPE), line:89
|vpiName:BUS_TYPE
|INT:5
|vpiParameter:
\_parameter: (COUNTER_W), line:42
|vpiName:COUNTER_W
|INT:33
|vpiParameter:
\_parameter: (CPU_ID), line:38
|vpiName:CPU_ID
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_ADDR_WIDTH), line:113
|vpiName:C_M_AXI_ADDR_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_DATA_WIDTH), line:114
|vpiName:C_M_AXI_DATA_WIDTH
|INT:1
|vpiParameter:
\_parameter: (DCACHE_LINES), line:133
|vpiName:DCACHE_LINES
|INT:-2146435073
|vpiParameter:
\_parameter: (DCACHE_LINE_ADDR_W), line:135
|vpiName:DCACHE_LINE_ADDR_W
|INT:1073741824
|vpiParameter:
\_parameter: (DCACHE_LINE_W), line:136
|vpiName:DCACHE_LINE_W
|INT:1342177279
|vpiParameter:
\_parameter: (DCACHE_SUB_LINE_ADDR_W), line:137
|vpiName:DCACHE_SUB_LINE_ADDR_W
|INT:4
|vpiParameter:
\_parameter: (DCACHE_TAG_W), line:138
|vpiName:DCACHE_TAG_W
|INT:1610612736
|vpiParameter:
\_parameter: (DCACHE_WAYS), line:134
|vpiName:DCACHE_WAYS
|INT:4
|vpiParameter:
\_parameter: (DIV_ALGORITHM), line:67
|vpiName:DIV_ALGORITHM
|INT:0
|vpiParameter:
\_parameter: (DIV_UNIT_WB_ID), line:192
|vpiName:DIV_UNIT_WB_ID
|INT:2
|vpiParameter:
\_parameter: (DTLB_DEPTH), line:152
|vpiName:DTLB_DEPTH
|INT:512
|vpiParameter:
\_parameter: (DTLB_WAYS), line:151
|vpiName:DTLB_WAYS
|INT:32
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (ENABLE_M_MODE), line:34
|vpiName:ENABLE_M_MODE
|INT:1
|vpiParameter:
\_parameter: (ENABLE_S_MODE), line:36
|vpiName:ENABLE_S_MODE
|INT:0
|vpiParameter:
\_parameter: (ENABLE_TRACE_INTERFACE), line:172
|vpiName:ENABLE_TRACE_INTERFACE
|INT:2
|vpiParameter:
\_parameter: (FETCH_BUFFER_DEPTH), line:168
|vpiName:FETCH_BUFFER_DEPTH
|INT:512
|vpiParameter:
\_parameter: (FPGA_VENDOR), line:27
|vpiName:FPGA_VENDOR
|STRING:"xilinx"
|vpiParameter:
\_parameter: (GC_UNIT_ID), line:196
|vpiName:GC_UNIT_ID
|INT:4
|vpiParameter:
\_parameter: (ICACHE_LINES), line:121
|vpiName:ICACHE_LINES
|INT:2
|vpiParameter:
\_parameter: (ICACHE_LINE_ADDR_W), line:123
|vpiName:ICACHE_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_LINE_W), line:124
|vpiName:ICACHE_LINE_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_SUB_LINE_ADDR_W), line:125
|vpiName:ICACHE_SUB_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_TAG_W), line:126
|vpiName:ICACHE_TAG_W
|INT:-2147483648
|vpiParameter:
\_parameter: (ICACHE_WAYS), line:122
|vpiName:ICACHE_WAYS
|INT:1
|vpiParameter:
\_parameter: (ITLB_DEPTH), line:146
|vpiName:ITLB_DEPTH
|INT:32
|vpiParameter:
\_parameter: (ITLB_WAYS), line:145
|vpiName:ITLB_WAYS
|INT:4
|vpiParameter:
\_parameter: (L1_CONNECTIONS), line:177
|vpiName:L1_CONNECTIONS
|INT:9
|vpiParameter:
\_parameter: (L1_DCACHE_ID), line:178
|vpiName:L1_DCACHE_ID
|INT:4
|vpiParameter:
\_parameter: (L1_DMMU_ID), line:179
|vpiName:L1_DMMU_ID
|INT:2
|vpiParameter:
\_parameter: (L1_ICACHE_ID), line:180
|vpiName:L1_ICACHE_ID
|INT:19
|vpiParameter:
\_parameter: (L1_IMMU_ID), line:181
|vpiName:L1_IMMU_ID
|INT:0
|vpiParameter:
\_parameter: (LS_UNIT_WB_ID), line:191
|vpiName:LS_UNIT_WB_ID
|INT:1
|vpiParameter:
\_parameter: (MAX_INFLIGHT_COUNT), line:167
|vpiName:MAX_INFLIGHT_COUNT
|INT:19
|vpiParameter:
\_parameter: (MEMORY_ADDR_H), line:103
|vpiName:MEMORY_ADDR_H
|INT:12
|vpiParameter:
\_parameter: (MEMORY_ADDR_L), line:102
|vpiName:MEMORY_ADDR_L
|INT:11
|vpiParameter:
\_parameter: (MEMORY_BIT_CHECK), line:104
|vpiName:MEMORY_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (MUL_UNIT_WB_ID), line:193
|vpiName:MUL_UNIT_WB_ID
|INT:512
|vpiParameter:
\_parameter: (NUM_UNITS), line:188
|vpiName:NUM_UNITS
|INT:2
|vpiParameter:
\_parameter: (NUM_WB_UNITS), line:186
|vpiName:NUM_WB_UNITS
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (RAS_DEPTH), line:161
|vpiName:RAS_DEPTH
|INT:2
|vpiParameter:
\_parameter: (RESET_VEC), line:39
|vpiName:RESET_VEC
|INT:-2147483648
|vpiParameter:
\_parameter: (SCRATCH_ADDR_H), line:99
|vpiName:SCRATCH_ADDR_H
|INT:9
|vpiParameter:
\_parameter: (SCRATCH_ADDR_L), line:98
|vpiName:SCRATCH_ADDR_L
|INT:8
|vpiParameter:
\_parameter: (SCRATCH_BIT_CHECK), line:100
|vpiName:SCRATCH_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (USE_AMO), line:70
|vpiName:USE_AMO
|INT:1
|vpiParameter:
\_parameter: (USE_BRANCH_PREDICTOR), line:158
|vpiName:USE_BRANCH_PREDICTOR
|INT:2
|vpiParameter:
\_parameter: (USE_BUS), line:88
|vpiName:USE_BUS
|INT:4
|vpiParameter:
\_parameter: (USE_DCACHE), line:92
|vpiName:USE_DCACHE
|INT:6
|vpiParameter:
\_parameter: (USE_DIV), line:49
|vpiName:USE_DIV
|INT:1
|vpiParameter:
\_parameter: (USE_DTAG_INVALIDATIONS), line:140
|vpiName:USE_DTAG_INVALIDATIONS
|INT:1879048191
|vpiParameter:
\_parameter: (USE_D_SCRATCH_MEM), line:79
|vpiName:USE_D_SCRATCH_MEM
|INT:3
|vpiParameter:
\_parameter: (USE_ICACHE), line:93
|vpiName:USE_ICACHE
|INT:7
|vpiParameter:
\_parameter: (USE_I_SCRATCH_MEM), line:78
|vpiName:USE_I_SCRATCH_MEM
|INT:2
|vpiParameter:
\_parameter: (USE_MUL), line:48
|vpiName:USE_MUL
|INT:1
|vpiParameter:
\_parameter: (WB_UNITS_WIDTH), line:187
|vpiName:WB_UNITS_WIDTH
|INT:32
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiParameter:
\_parameter: (i), line:190
|vpiName:i
|INT:1
|vpiGenScopeArray:
\_gen_scope_array: (genblk4), line:256, parent:decode_block
|vpiName:genblk4
|vpiFullName:work@taiga_wrapper.cpu.decode_block.genblk4
|vpiGenScope:
\_gen_scope: , parent:genblk4
|vpiFullName:work@taiga_wrapper.cpu.decode_block.genblk4
|vpiContAssign:
\_cont_assign: , line:257
|vpiRhs:
\_ref_obj: (load_reserve), line:257
|vpiName:load_reserve
|vpiFullName:work@taiga_wrapper.cpu.decode_block.genblk4.load_reserve
|vpiLhs:
\_ref_obj: (ls_inputs.amo), line:257
|vpiName:ls_inputs.amo
|vpiFullName:work@taiga_wrapper.cpu.decode_block.genblk4.ls_inputs.amo
|vpiContAssign:
\_cont_assign: , line:258
|vpiRhs:
\_ref_obj: (store_conditional), line:258
|vpiName:store_conditional
|vpiFullName:work@taiga_wrapper.cpu.decode_block.genblk4.store_conditional
|vpiLhs:
\_ref_obj: (ls_inputs.amo), line:258
|vpiName:ls_inputs.amo
|vpiFullName:work@taiga_wrapper.cpu.decode_block.genblk4.ls_inputs.amo
|vpiContAssign:
\_cont_assign: , line:259
|vpiRhs:
\_operation: , line:259
|vpiOpType:28
|vpiOperand:
\_ref_obj: (amo_op), line:259
|vpiName:amo_op
|vpiFullName:work@taiga_wrapper.cpu.decode_block.genblk4.amo_op
|vpiOperand:
\_operation: , line:259
|vpiOpType:4
|vpiOperand:
\_operation: , line:259
|vpiOpType:29
|vpiOperand:
\_ref_obj: (load_reserve), line:259
|vpiName:load_reserve
|vpiFullName:work@taiga_wrapper.cpu.decode_block.genblk4.load_reserve
|vpiOperand:
\_ref_obj: (store_conditional), line:259
|vpiName:store_conditional
|vpiFullName:work@taiga_wrapper.cpu.decode_block.genblk4.store_conditional
|vpiLhs:
\_ref_obj: (ls_inputs.amo), line:259
|vpiName:ls_inputs.amo
|vpiFullName:work@taiga_wrapper.cpu.decode_block.genblk4.ls_inputs.amo
|vpiContAssign:
\_cont_assign: , line:260
|vpiRhs:
\_ref_obj: (amo_type), line:260
|vpiName:amo_type
|vpiFullName:work@taiga_wrapper.cpu.decode_block.genblk4.amo_type
|vpiLhs:
\_ref_obj: (ls_inputs.amo), line:260
|vpiName:ls_inputs.amo
|vpiFullName:work@taiga_wrapper.cpu.decode_block.genblk4.ls_inputs.amo
|vpiContAssign:
\_cont_assign: , line:263
|vpiRhs:
\_constant: , line:263
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiLhs:
\_ref_obj: (ls_inputs.amo), line:263
|vpiName:ls_inputs.amo
|vpiFullName:work@taiga_wrapper.cpu.decode_block.genblk4.ls_inputs.amo
|vpiParameter:
\_parameter: (ALU_UNIT_WB_ID), line:190
|vpiName:ALU_UNIT_WB_ID
|INT:32
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (BRANCH_PREDICTOR_WAYS), line:159
|vpiName:BRANCH_PREDICTOR_WAYS
|INT:9
|vpiParameter:
\_parameter: (BRANCH_TABLE_ENTRIES), line:160
|vpiName:BRANCH_TABLE_ENTRIES
|INT:4
|vpiParameter:
\_parameter: (BRANCH_UNIT_ID), line:195
|vpiName:BRANCH_UNIT_ID
|INT:8
|vpiParameter:
\_parameter: (BUS_ADDR_H), line:107
|vpiName:BUS_ADDR_H
|INT:1
|vpiParameter:
\_parameter: (BUS_ADDR_L), line:106
|vpiName:BUS_ADDR_L
|INT:0
|vpiParameter:
\_parameter: (BUS_BIT_CHECK), line:108
|vpiName:BUS_BIT_CHECK
|INT:1
|vpiParameter:
\_parameter: (BUS_TYPE), line:89
|vpiName:BUS_TYPE
|INT:5
|vpiParameter:
\_parameter: (COUNTER_W), line:42
|vpiName:COUNTER_W
|INT:33
|vpiParameter:
\_parameter: (CPU_ID), line:38
|vpiName:CPU_ID
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_ADDR_WIDTH), line:113
|vpiName:C_M_AXI_ADDR_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_DATA_WIDTH), line:114
|vpiName:C_M_AXI_DATA_WIDTH
|INT:1
|vpiParameter:
\_parameter: (DCACHE_LINES), line:133
|vpiName:DCACHE_LINES
|INT:-2146435073
|vpiParameter:
\_parameter: (DCACHE_LINE_ADDR_W), line:135
|vpiName:DCACHE_LINE_ADDR_W
|INT:1073741824
|vpiParameter:
\_parameter: (DCACHE_LINE_W), line:136
|vpiName:DCACHE_LINE_W
|INT:1342177279
|vpiParameter:
\_parameter: (DCACHE_SUB_LINE_ADDR_W), line:137
|vpiName:DCACHE_SUB_LINE_ADDR_W
|INT:4
|vpiParameter:
\_parameter: (DCACHE_TAG_W), line:138
|vpiName:DCACHE_TAG_W
|INT:1610612736
|vpiParameter:
\_parameter: (DCACHE_WAYS), line:134
|vpiName:DCACHE_WAYS
|INT:4
|vpiParameter:
\_parameter: (DIV_ALGORITHM), line:67
|vpiName:DIV_ALGORITHM
|INT:0
|vpiParameter:
\_parameter: (DIV_UNIT_WB_ID), line:192
|vpiName:DIV_UNIT_WB_ID
|INT:2
|vpiParameter:
\_parameter: (DTLB_DEPTH), line:152
|vpiName:DTLB_DEPTH
|INT:512
|vpiParameter:
\_parameter: (DTLB_WAYS), line:151
|vpiName:DTLB_WAYS
|INT:32
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (ENABLE_M_MODE), line:34
|vpiName:ENABLE_M_MODE
|INT:1
|vpiParameter:
\_parameter: (ENABLE_S_MODE), line:36
|vpiName:ENABLE_S_MODE
|INT:0
|vpiParameter:
\_parameter: (ENABLE_TRACE_INTERFACE), line:172
|vpiName:ENABLE_TRACE_INTERFACE
|INT:2
|vpiParameter:
\_parameter: (FETCH_BUFFER_DEPTH), line:168
|vpiName:FETCH_BUFFER_DEPTH
|INT:512
|vpiParameter:
\_parameter: (FPGA_VENDOR), line:27
|vpiName:FPGA_VENDOR
|STRING:"xilinx"
|vpiParameter:
\_parameter: (GC_UNIT_ID), line:196
|vpiName:GC_UNIT_ID
|INT:4
|vpiParameter:
\_parameter: (ICACHE_LINES), line:121
|vpiName:ICACHE_LINES
|INT:2
|vpiParameter:
\_parameter: (ICACHE_LINE_ADDR_W), line:123
|vpiName:ICACHE_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_LINE_W), line:124
|vpiName:ICACHE_LINE_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_SUB_LINE_ADDR_W), line:125
|vpiName:ICACHE_SUB_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_TAG_W), line:126
|vpiName:ICACHE_TAG_W
|INT:-2147483648
|vpiParameter:
\_parameter: (ICACHE_WAYS), line:122
|vpiName:ICACHE_WAYS
|INT:1
|vpiParameter:
\_parameter: (ITLB_DEPTH), line:146
|vpiName:ITLB_DEPTH
|INT:32
|vpiParameter:
\_parameter: (ITLB_WAYS), line:145
|vpiName:ITLB_WAYS
|INT:4
|vpiParameter:
\_parameter: (L1_CONNECTIONS), line:177
|vpiName:L1_CONNECTIONS
|INT:9
|vpiParameter:
\_parameter: (L1_DCACHE_ID), line:178
|vpiName:L1_DCACHE_ID
|INT:4
|vpiParameter:
\_parameter: (L1_DMMU_ID), line:179
|vpiName:L1_DMMU_ID
|INT:2
|vpiParameter:
\_parameter: (L1_ICACHE_ID), line:180
|vpiName:L1_ICACHE_ID
|INT:19
|vpiParameter:
\_parameter: (L1_IMMU_ID), line:181
|vpiName:L1_IMMU_ID
|INT:0
|vpiParameter:
\_parameter: (LS_UNIT_WB_ID), line:191
|vpiName:LS_UNIT_WB_ID
|INT:1
|vpiParameter:
\_parameter: (MAX_INFLIGHT_COUNT), line:167
|vpiName:MAX_INFLIGHT_COUNT
|INT:19
|vpiParameter:
\_parameter: (MEMORY_ADDR_H), line:103
|vpiName:MEMORY_ADDR_H
|INT:12
|vpiParameter:
\_parameter: (MEMORY_ADDR_L), line:102
|vpiName:MEMORY_ADDR_L
|INT:11
|vpiParameter:
\_parameter: (MEMORY_BIT_CHECK), line:104
|vpiName:MEMORY_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (MUL_UNIT_WB_ID), line:193
|vpiName:MUL_UNIT_WB_ID
|INT:512
|vpiParameter:
\_parameter: (NUM_UNITS), line:188
|vpiName:NUM_UNITS
|INT:2
|vpiParameter:
\_parameter: (NUM_WB_UNITS), line:186
|vpiName:NUM_WB_UNITS
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (RAS_DEPTH), line:161
|vpiName:RAS_DEPTH
|INT:2
|vpiParameter:
\_parameter: (RESET_VEC), line:39
|vpiName:RESET_VEC
|INT:-2147483648
|vpiParameter:
\_parameter: (SCRATCH_ADDR_H), line:99
|vpiName:SCRATCH_ADDR_H
|INT:9
|vpiParameter:
\_parameter: (SCRATCH_ADDR_L), line:98
|vpiName:SCRATCH_ADDR_L
|INT:8
|vpiParameter:
\_parameter: (SCRATCH_BIT_CHECK), line:100
|vpiName:SCRATCH_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (USE_AMO), line:70
|vpiName:USE_AMO
|INT:1
|vpiParameter:
\_parameter: (USE_BRANCH_PREDICTOR), line:158
|vpiName:USE_BRANCH_PREDICTOR
|INT:2
|vpiParameter:
\_parameter: (USE_BUS), line:88
|vpiName:USE_BUS
|INT:4
|vpiParameter:
\_parameter: (USE_DCACHE), line:92
|vpiName:USE_DCACHE
|INT:6
|vpiParameter:
\_parameter: (USE_DIV), line:49
|vpiName:USE_DIV
|INT:1
|vpiParameter:
\_parameter: (USE_DTAG_INVALIDATIONS), line:140
|vpiName:USE_DTAG_INVALIDATIONS
|INT:1879048191
|vpiParameter:
\_parameter: (USE_D_SCRATCH_MEM), line:79
|vpiName:USE_D_SCRATCH_MEM
|INT:3
|vpiParameter:
\_parameter: (USE_ICACHE), line:93
|vpiName:USE_ICACHE
|INT:7
|vpiParameter:
\_parameter: (USE_I_SCRATCH_MEM), line:78
|vpiName:USE_I_SCRATCH_MEM
|INT:2
|vpiParameter:
\_parameter: (USE_MUL), line:48
|vpiName:USE_MUL
|INT:1
|vpiParameter:
\_parameter: (WB_UNITS_WIDTH), line:187
|vpiName:WB_UNITS_WIDTH
|INT:32
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiGenScopeArray:
\_gen_scope_array: (genblk5), line:332, parent:decode_block
|vpiName:genblk5
|vpiFullName:work@taiga_wrapper.cpu.decode_block.genblk5
|vpiGenScope:
\_gen_scope: , parent:genblk5
|vpiFullName:work@taiga_wrapper.cpu.decode_block.genblk5
|vpiContAssign:
\_cont_assign: , line:333
|vpiRhs:
\_ref_obj: (rf_decode.rs1_data), line:333
|vpiName:rf_decode.rs1_data
|vpiFullName:work@taiga_wrapper.cpu.decode_block.genblk5.rf_decode.rs1_data
|vpiLhs:
\_ref_obj: (mul_inputs.rs1), line:333
|vpiName:mul_inputs.rs1
|vpiFullName:work@taiga_wrapper.cpu.decode_block.genblk5.mul_inputs.rs1
|vpiContAssign:
\_cont_assign: , line:334
|vpiRhs:
\_ref_obj: (rf_decode.rs2_data), line:334
|vpiName:rf_decode.rs2_data
|vpiFullName:work@taiga_wrapper.cpu.decode_block.genblk5.rf_decode.rs2_data
|vpiLhs:
\_ref_obj: (mul_inputs.rs2), line:334
|vpiName:mul_inputs.rs2
|vpiFullName:work@taiga_wrapper.cpu.decode_block.genblk5.mul_inputs.rs2
|vpiContAssign:
\_cont_assign: , line:335
|vpiRhs:
\_part_select: , line:335, parent:fn3
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (fn3)
|vpiLeftRange:
\_constant: , line:335
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:335
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiLhs:
\_ref_obj: (mul_inputs.op), line:335
|vpiName:mul_inputs.op
|vpiFullName:work@taiga_wrapper.cpu.decode_block.genblk5.mul_inputs.op
|vpiParameter:
\_parameter: (ALU_UNIT_WB_ID), line:190
|vpiName:ALU_UNIT_WB_ID
|INT:32
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (BRANCH_PREDICTOR_WAYS), line:159
|vpiName:BRANCH_PREDICTOR_WAYS
|INT:9
|vpiParameter:
\_parameter: (BRANCH_TABLE_ENTRIES), line:160
|vpiName:BRANCH_TABLE_ENTRIES
|INT:4
|vpiParameter:
\_parameter: (BRANCH_UNIT_ID), line:195
|vpiName:BRANCH_UNIT_ID
|INT:8
|vpiParameter:
\_parameter: (BUS_ADDR_H), line:107
|vpiName:BUS_ADDR_H
|INT:1
|vpiParameter:
\_parameter: (BUS_ADDR_L), line:106
|vpiName:BUS_ADDR_L
|INT:0
|vpiParameter:
\_parameter: (BUS_BIT_CHECK), line:108
|vpiName:BUS_BIT_CHECK
|INT:1
|vpiParameter:
\_parameter: (BUS_TYPE), line:89
|vpiName:BUS_TYPE
|INT:5
|vpiParameter:
\_parameter: (COUNTER_W), line:42
|vpiName:COUNTER_W
|INT:33
|vpiParameter:
\_parameter: (CPU_ID), line:38
|vpiName:CPU_ID
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_ADDR_WIDTH), line:113
|vpiName:C_M_AXI_ADDR_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_DATA_WIDTH), line:114
|vpiName:C_M_AXI_DATA_WIDTH
|INT:1
|vpiParameter:
\_parameter: (DCACHE_LINES), line:133
|vpiName:DCACHE_LINES
|INT:-2146435073
|vpiParameter:
\_parameter: (DCACHE_LINE_ADDR_W), line:135
|vpiName:DCACHE_LINE_ADDR_W
|INT:1073741824
|vpiParameter:
\_parameter: (DCACHE_LINE_W), line:136
|vpiName:DCACHE_LINE_W
|INT:1342177279
|vpiParameter:
\_parameter: (DCACHE_SUB_LINE_ADDR_W), line:137
|vpiName:DCACHE_SUB_LINE_ADDR_W
|INT:4
|vpiParameter:
\_parameter: (DCACHE_TAG_W), line:138
|vpiName:DCACHE_TAG_W
|INT:1610612736
|vpiParameter:
\_parameter: (DCACHE_WAYS), line:134
|vpiName:DCACHE_WAYS
|INT:4
|vpiParameter:
\_parameter: (DIV_ALGORITHM), line:67
|vpiName:DIV_ALGORITHM
|INT:0
|vpiParameter:
\_parameter: (DIV_UNIT_WB_ID), line:192
|vpiName:DIV_UNIT_WB_ID
|INT:2
|vpiParameter:
\_parameter: (DTLB_DEPTH), line:152
|vpiName:DTLB_DEPTH
|INT:512
|vpiParameter:
\_parameter: (DTLB_WAYS), line:151
|vpiName:DTLB_WAYS
|INT:32
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (ENABLE_M_MODE), line:34
|vpiName:ENABLE_M_MODE
|INT:1
|vpiParameter:
\_parameter: (ENABLE_S_MODE), line:36
|vpiName:ENABLE_S_MODE
|INT:0
|vpiParameter:
\_parameter: (ENABLE_TRACE_INTERFACE), line:172
|vpiName:ENABLE_TRACE_INTERFACE
|INT:2
|vpiParameter:
\_parameter: (FETCH_BUFFER_DEPTH), line:168
|vpiName:FETCH_BUFFER_DEPTH
|INT:512
|vpiParameter:
\_parameter: (FPGA_VENDOR), line:27
|vpiName:FPGA_VENDOR
|STRING:"xilinx"
|vpiParameter:
\_parameter: (GC_UNIT_ID), line:196
|vpiName:GC_UNIT_ID
|INT:4
|vpiParameter:
\_parameter: (ICACHE_LINES), line:121
|vpiName:ICACHE_LINES
|INT:2
|vpiParameter:
\_parameter: (ICACHE_LINE_ADDR_W), line:123
|vpiName:ICACHE_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_LINE_W), line:124
|vpiName:ICACHE_LINE_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_SUB_LINE_ADDR_W), line:125
|vpiName:ICACHE_SUB_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_TAG_W), line:126
|vpiName:ICACHE_TAG_W
|INT:-2147483648
|vpiParameter:
\_parameter: (ICACHE_WAYS), line:122
|vpiName:ICACHE_WAYS
|INT:1
|vpiParameter:
\_parameter: (ITLB_DEPTH), line:146
|vpiName:ITLB_DEPTH
|INT:32
|vpiParameter:
\_parameter: (ITLB_WAYS), line:145
|vpiName:ITLB_WAYS
|INT:4
|vpiParameter:
\_parameter: (L1_CONNECTIONS), line:177
|vpiName:L1_CONNECTIONS
|INT:9
|vpiParameter:
\_parameter: (L1_DCACHE_ID), line:178
|vpiName:L1_DCACHE_ID
|INT:4
|vpiParameter:
\_parameter: (L1_DMMU_ID), line:179
|vpiName:L1_DMMU_ID
|INT:2
|vpiParameter:
\_parameter: (L1_ICACHE_ID), line:180
|vpiName:L1_ICACHE_ID
|INT:19
|vpiParameter:
\_parameter: (L1_IMMU_ID), line:181
|vpiName:L1_IMMU_ID
|INT:0
|vpiParameter:
\_parameter: (LS_UNIT_WB_ID), line:191
|vpiName:LS_UNIT_WB_ID
|INT:1
|vpiParameter:
\_parameter: (MAX_INFLIGHT_COUNT), line:167
|vpiName:MAX_INFLIGHT_COUNT
|INT:19
|vpiParameter:
\_parameter: (MEMORY_ADDR_H), line:103
|vpiName:MEMORY_ADDR_H
|INT:12
|vpiParameter:
\_parameter: (MEMORY_ADDR_L), line:102
|vpiName:MEMORY_ADDR_L
|INT:11
|vpiParameter:
\_parameter: (MEMORY_BIT_CHECK), line:104
|vpiName:MEMORY_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (MUL_UNIT_WB_ID), line:193
|vpiName:MUL_UNIT_WB_ID
|INT:512
|vpiParameter:
\_parameter: (NUM_UNITS), line:188
|vpiName:NUM_UNITS
|INT:2
|vpiParameter:
\_parameter: (NUM_WB_UNITS), line:186
|vpiName:NUM_WB_UNITS
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (RAS_DEPTH), line:161
|vpiName:RAS_DEPTH
|INT:2
|vpiParameter:
\_parameter: (RESET_VEC), line:39
|vpiName:RESET_VEC
|INT:-2147483648
|vpiParameter:
\_parameter: (SCRATCH_ADDR_H), line:99
|vpiName:SCRATCH_ADDR_H
|INT:9
|vpiParameter:
\_parameter: (SCRATCH_ADDR_L), line:98
|vpiName:SCRATCH_ADDR_L
|INT:8
|vpiParameter:
\_parameter: (SCRATCH_BIT_CHECK), line:100
|vpiName:SCRATCH_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (USE_AMO), line:70
|vpiName:USE_AMO
|INT:1
|vpiParameter:
\_parameter: (USE_BRANCH_PREDICTOR), line:158
|vpiName:USE_BRANCH_PREDICTOR
|INT:2
|vpiParameter:
\_parameter: (USE_BUS), line:88
|vpiName:USE_BUS
|INT:4
|vpiParameter:
\_parameter: (USE_DCACHE), line:92
|vpiName:USE_DCACHE
|INT:6
|vpiParameter:
\_parameter: (USE_DIV), line:49
|vpiName:USE_DIV
|INT:1
|vpiParameter:
\_parameter: (USE_DTAG_INVALIDATIONS), line:140
|vpiName:USE_DTAG_INVALIDATIONS
|INT:1879048191
|vpiParameter:
\_parameter: (USE_D_SCRATCH_MEM), line:79
|vpiName:USE_D_SCRATCH_MEM
|INT:3
|vpiParameter:
\_parameter: (USE_ICACHE), line:93
|vpiName:USE_ICACHE
|INT:7
|vpiParameter:
\_parameter: (USE_I_SCRATCH_MEM), line:78
|vpiName:USE_I_SCRATCH_MEM
|INT:2
|vpiParameter:
\_parameter: (USE_MUL), line:48
|vpiName:USE_MUL
|INT:1
|vpiParameter:
\_parameter: (WB_UNITS_WIDTH), line:187
|vpiName:WB_UNITS_WIDTH
|INT:32
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiGenScopeArray:
\_gen_scope_array: (genblk6), line:342, parent:decode_block
|vpiName:genblk6
|vpiFullName:work@taiga_wrapper.cpu.decode_block.genblk6
|vpiGenScope:
\_gen_scope: , parent:genblk6
|vpiFullName:work@taiga_wrapper.cpu.decode_block.genblk6
|vpiNet:
\_logic_net: (prev_div_rs1_addr), line:343
|vpiName:prev_div_rs1_addr
|vpiFullName:work@taiga_wrapper.cpu.decode_block.genblk6.prev_div_rs1_addr
|vpiNetType:36
|vpiRange:
\_range: , line:343
|vpiLeftRange:
\_constant: , line:343
|vpiConstType:7
|vpiDecompile:4
|vpiSize:32
|INT:4
|vpiRightRange:
\_constant: , line:343
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (prev_div_rs2_addr), line:344
|vpiName:prev_div_rs2_addr
|vpiFullName:work@taiga_wrapper.cpu.decode_block.genblk6.prev_div_rs2_addr
|vpiNetType:36
|vpiRange:
\_range: , line:344
|vpiLeftRange:
\_constant: , line:344
|vpiConstType:7
|vpiDecompile:4
|vpiSize:32
|INT:4
|vpiRightRange:
\_constant: , line:344
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (prev_div_result_valid), line:345
|vpiName:prev_div_result_valid
|vpiFullName:work@taiga_wrapper.cpu.decode_block.genblk6.prev_div_result_valid
|vpiNetType:36
|vpiNet:
\_logic_net: (prev_div_result_valid_r), line:346
|vpiName:prev_div_result_valid_r
|vpiFullName:work@taiga_wrapper.cpu.decode_block.genblk6.prev_div_result_valid_r
|vpiNetType:36
|vpiNet:
\_logic_net: (div_rd_overwrites_rs1_or_rs2), line:349
|vpiName:div_rd_overwrites_rs1_or_rs2
|vpiFullName:work@taiga_wrapper.cpu.decode_block.genblk6.div_rd_overwrites_rs1_or_rs2
|vpiNetType:36
|vpiNet:
\_logic_net: (rd_overwrites_previously_saved_rs1_or_rs2), line:350
|vpiName:rd_overwrites_previously_saved_rs1_or_rs2
|vpiFullName:work@taiga_wrapper.cpu.decode_block.genblk6.rd_overwrites_previously_saved_rs1_or_rs2
|vpiNetType:36
|vpiNet:
\_logic_net: (current_op_resuses_rs1_rs2), line:351
|vpiName:current_op_resuses_rs1_rs2
|vpiFullName:work@taiga_wrapper.cpu.decode_block.genblk6.current_op_resuses_rs1_rs2
|vpiNetType:36
|vpiProcess:
\_always: , line:353
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:353
|vpiCondition:
\_operation: , line:353
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:353
|vpiName:clk
|vpiFullName:work@taiga_wrapper.cpu.decode_block.genblk6.clk
|vpiStmt:
\_begin: , line:353
|vpiFullName:work@taiga_wrapper.cpu.decode_block.genblk6
|vpiStmt:
\_if_stmt: , line:354
|vpiCondition:
\_bit_select: (issue), line:354
|vpiName:issue
|vpiFullName:work@taiga_wrapper.cpu.decode_block.genblk6.issue
|vpiIndex:
\_ref_obj: (DIV_UNIT_WB_ID), line:354
|vpiName:DIV_UNIT_WB_ID
|vpiStmt:
\_begin: , line:354
|vpiFullName:work@taiga_wrapper.cpu.decode_block.genblk6
|vpiStmt:
\_assignment: , line:355
|vpiOpType:82
|vpiLhs:
\_ref_obj: (prev_div_rs1_addr), line:355
|vpiName:prev_div_rs1_addr
|vpiFullName:work@taiga_wrapper.cpu.decode_block.genblk6.prev_div_rs1_addr
|vpiRhs:
\_ref_obj: (rs1_addr), line:355
|vpiName:rs1_addr
|vpiFullName:work@taiga_wrapper.cpu.decode_block.genblk6.rs1_addr
|vpiStmt:
\_assignment: , line:356
|vpiOpType:82
|vpiLhs:
\_ref_obj: (prev_div_rs2_addr), line:356
|vpiName:prev_div_rs2_addr
|vpiFullName:work@taiga_wrapper.cpu.decode_block.genblk6.prev_div_rs2_addr
|vpiRhs:
\_ref_obj: (rs2_addr), line:356
|vpiName:rs2_addr
|vpiFullName:work@taiga_wrapper.cpu.decode_block.genblk6.rs2_addr
|vpiProcess:
\_always: , line:364
|vpiAlwaysType:2
|vpiStmt:
\_begin: , line:364
|vpiFullName:work@taiga_wrapper.cpu.decode_block.genblk6
|vpiStmt:
\_assignment: , line:365
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (prev_div_result_valid), line:365
|vpiName:prev_div_result_valid
|vpiFullName:work@taiga_wrapper.cpu.decode_block.genblk6.prev_div_result_valid
|vpiRhs:
\_ref_obj: (prev_div_result_valid_r), line:365
|vpiName:prev_div_result_valid_r
|vpiFullName:work@taiga_wrapper.cpu.decode_block.genblk6.prev_div_result_valid_r
|vpiStmt:
\_if_else: , line:366
|vpiCondition:
\_operation: , line:366
|vpiOpType:28
|vpiOperand:
\_bit_select: (unit_requested), line:366
|vpiName:unit_requested
|vpiFullName:work@taiga_wrapper.cpu.decode_block.genblk6.unit_requested
|vpiIndex:
\_ref_obj: (DIV_UNIT_WB_ID), line:366
|vpiName:DIV_UNIT_WB_ID
|vpiOperand:
\_operation: , line:366
|vpiOpType:4
|vpiOperand:
\_ref_obj: (div_rd_overwrites_rs1_or_rs2), line:366
|vpiName:div_rd_overwrites_rs1_or_rs2
|vpiFullName:work@taiga_wrapper.cpu.decode_block.genblk6.div_rd_overwrites_rs1_or_rs2
|vpiStmt:
\_assignment: , line:367
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (prev_div_result_valid), line:367
|vpiName:prev_div_result_valid
|vpiFullName:work@taiga_wrapper.cpu.decode_block.genblk6.prev_div_result_valid
|vpiRhs:
\_constant: , line:367
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiElseStmt:
\_if_stmt: , line:368
|vpiCondition:
\_operation: , line:368
|vpiOpType:29
|vpiOperand:
\_operation: , line:368
|vpiOpType:28
|vpiOperand:
\_bit_select: (unit_requested), line:368
|vpiName:unit_requested
|vpiFullName:work@taiga_wrapper.cpu.decode_block.genblk6.unit_requested
|vpiIndex:
\_ref_obj: (DIV_UNIT_WB_ID), line:368
|vpiName:DIV_UNIT_WB_ID
|vpiOperand:
\_ref_obj: (div_rd_overwrites_rs1_or_rs2), line:368
|vpiName:div_rd_overwrites_rs1_or_rs2
|vpiFullName:work@taiga_wrapper.cpu.decode_block.genblk6.div_rd_overwrites_rs1_or_rs2
|vpiOperand:
\_operation: , line:368
|vpiOpType:28
|vpiOperand:
\_ref_obj: (uses_rd), line:368
|vpiName:uses_rd
|vpiFullName:work@taiga_wrapper.cpu.decode_block.genblk6.uses_rd
|vpiOperand:
\_ref_obj: (rd_overwrites_previously_saved_rs1_or_rs2), line:368
|vpiName:rd_overwrites_previously_saved_rs1_or_rs2
|vpiFullName:work@taiga_wrapper.cpu.decode_block.genblk6.rd_overwrites_previously_saved_rs1_or_rs2
|vpiStmt:
\_assignment: , line:369
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (prev_div_result_valid), line:369
|vpiName:prev_div_result_valid
|vpiFullName:work@taiga_wrapper.cpu.decode_block.genblk6.prev_div_result_valid
|vpiRhs:
\_constant: , line:369
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiProcess:
\_always: , line:372
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:372
|vpiCondition:
\_operation: , line:372
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:372
|vpiName:clk
|vpiFullName:work@taiga_wrapper.cpu.decode_block.genblk6.clk
|vpiStmt:
\_begin: , line:372
|vpiFullName:work@taiga_wrapper.cpu.decode_block.genblk6
|vpiStmt:
\_if_else: , line:373
|vpiCondition:
\_ref_obj: (rst), line:373
|vpiName:rst
|vpiFullName:work@taiga_wrapper.cpu.decode_block.genblk6.rst
|vpiStmt:
\_assignment: , line:374
|vpiOpType:82
|vpiLhs:
\_ref_obj: (prev_div_result_valid_r), line:374
|vpiName:prev_div_result_valid_r
|vpiFullName:work@taiga_wrapper.cpu.decode_block.genblk6.prev_div_result_valid_r
|vpiRhs:
\_constant: , line:374
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiElseStmt:
\_if_stmt: , line:375
|vpiCondition:
\_ref_obj: (instruction_issued), line:375
|vpiName:instruction_issued
|vpiFullName:work@taiga_wrapper.cpu.decode_block.genblk6.instruction_issued
|vpiStmt:
\_assignment: , line:376
|vpiOpType:82
|vpiLhs:
\_ref_obj: (prev_div_result_valid_r), line:376
|vpiName:prev_div_result_valid_r
|vpiFullName:work@taiga_wrapper.cpu.decode_block.genblk6.prev_div_result_valid_r
|vpiRhs:
\_ref_obj: (prev_div_result_valid), line:376
|vpiName:prev_div_result_valid
|vpiFullName:work@taiga_wrapper.cpu.decode_block.genblk6.prev_div_result_valid
|vpiContAssign:
\_cont_assign: , line:360
|vpiRhs:
\_operation: , line:360
|vpiOpType:27
|vpiOperand:
\_operation: , line:360
|vpiOpType:14
|vpiOperand:
\_ref_obj: (future_rd_addr), line:360
|vpiName:future_rd_addr
|vpiFullName:work@taiga_wrapper.cpu.decode_block.genblk6.future_rd_addr
|vpiOperand:
\_ref_obj: (rs1_addr), line:360
|vpiName:rs1_addr
|vpiFullName:work@taiga_wrapper.cpu.decode_block.genblk6.rs1_addr
|vpiOperand:
\_operation: , line:360
|vpiOpType:14
|vpiOperand:
\_ref_obj: (future_rd_addr), line:360
|vpiName:future_rd_addr
|vpiFullName:work@taiga_wrapper.cpu.decode_block.genblk6.future_rd_addr
|vpiOperand:
\_ref_obj: (rs2_addr), line:360
|vpiName:rs2_addr
|vpiFullName:work@taiga_wrapper.cpu.decode_block.genblk6.rs2_addr
|vpiLhs:
\_ref_obj: (div_rd_overwrites_rs1_or_rs2), line:360
|vpiName:div_rd_overwrites_rs1_or_rs2
|vpiFullName:work@taiga_wrapper.cpu.decode_block.genblk6.div_rd_overwrites_rs1_or_rs2
|vpiContAssign:
\_cont_assign: , line:361
|vpiRhs:
\_operation: , line:361
|vpiOpType:27
|vpiOperand:
\_operation: , line:361
|vpiOpType:14
|vpiOperand:
\_ref_obj: (future_rd_addr), line:361
|vpiName:future_rd_addr
|vpiFullName:work@taiga_wrapper.cpu.decode_block.genblk6.future_rd_addr
|vpiOperand:
\_ref_obj: (prev_div_rs1_addr), line:361
|vpiName:prev_div_rs1_addr
|vpiFullName:work@taiga_wrapper.cpu.decode_block.genblk6.prev_div_rs1_addr
|vpiOperand:
\_operation: , line:361
|vpiOpType:14
|vpiOperand:
\_ref_obj: (future_rd_addr), line:361
|vpiName:future_rd_addr
|vpiFullName:work@taiga_wrapper.cpu.decode_block.genblk6.future_rd_addr
|vpiOperand:
\_ref_obj: (prev_div_rs2_addr), line:361
|vpiName:prev_div_rs2_addr
|vpiFullName:work@taiga_wrapper.cpu.decode_block.genblk6.prev_div_rs2_addr
|vpiLhs:
\_ref_obj: (rd_overwrites_previously_saved_rs1_or_rs2), line:361
|vpiName:rd_overwrites_previously_saved_rs1_or_rs2
|vpiFullName:work@taiga_wrapper.cpu.decode_block.genblk6.rd_overwrites_previously_saved_rs1_or_rs2
|vpiContAssign:
\_cont_assign: , line:362
|vpiRhs:
\_operation: , line:362
|vpiOpType:26
|vpiOperand:
\_operation: , line:362
|vpiOpType:14
|vpiOperand:
\_ref_obj: (prev_div_rs1_addr), line:362
|vpiName:prev_div_rs1_addr
|vpiFullName:work@taiga_wrapper.cpu.decode_block.genblk6.prev_div_rs1_addr
|vpiOperand:
\_ref_obj: (rs1_addr), line:362
|vpiName:rs1_addr
|vpiFullName:work@taiga_wrapper.cpu.decode_block.genblk6.rs1_addr
|vpiOperand:
\_operation: , line:362
|vpiOpType:14
|vpiOperand:
\_ref_obj: (prev_div_rs2_addr), line:362
|vpiName:prev_div_rs2_addr
|vpiFullName:work@taiga_wrapper.cpu.decode_block.genblk6.prev_div_rs2_addr
|vpiOperand:
\_ref_obj: (rs2_addr), line:362
|vpiName:rs2_addr
|vpiFullName:work@taiga_wrapper.cpu.decode_block.genblk6.rs2_addr
|vpiLhs:
\_ref_obj: (current_op_resuses_rs1_rs2), line:362
|vpiName:current_op_resuses_rs1_rs2
|vpiFullName:work@taiga_wrapper.cpu.decode_block.genblk6.current_op_resuses_rs1_rs2
|vpiContAssign:
\_cont_assign: , line:379
|vpiRhs:
\_ref_obj: (rf_decode.rs1_data), line:379
|vpiName:rf_decode.rs1_data
|vpiFullName:work@taiga_wrapper.cpu.decode_block.genblk6.rf_decode.rs1_data
|vpiLhs:
\_ref_obj: (div_inputs.rs1), line:379
|vpiName:div_inputs.rs1
|vpiFullName:work@taiga_wrapper.cpu.decode_block.genblk6.div_inputs.rs1
|vpiContAssign:
\_cont_assign: , line:380
|vpiRhs:
\_ref_obj: (rf_decode.rs2_data), line:380
|vpiName:rf_decode.rs2_data
|vpiFullName:work@taiga_wrapper.cpu.decode_block.genblk6.rf_decode.rs2_data
|vpiLhs:
\_ref_obj: (div_inputs.rs2), line:380
|vpiName:div_inputs.rs2
|vpiFullName:work@taiga_wrapper.cpu.decode_block.genblk6.div_inputs.rs2
|vpiContAssign:
\_cont_assign: , line:381
|vpiRhs:
\_part_select: , line:381, parent:fn3
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (fn3)
|vpiLeftRange:
\_constant: , line:381
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:381
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiLhs:
\_ref_obj: (div_inputs.op), line:381
|vpiName:div_inputs.op
|vpiFullName:work@taiga_wrapper.cpu.decode_block.genblk6.div_inputs.op
|vpiContAssign:
\_cont_assign: , line:382
|vpiRhs:
\_operation: , line:382
|vpiOpType:28
|vpiOperand:
\_ref_obj: (prev_div_result_valid_r), line:382
|vpiName:prev_div_result_valid_r
|vpiFullName:work@taiga_wrapper.cpu.decode_block.genblk6.prev_div_result_valid_r
|vpiOperand:
\_ref_obj: (current_op_resuses_rs1_rs2), line:382
|vpiName:current_op_resuses_rs1_rs2
|vpiFullName:work@taiga_wrapper.cpu.decode_block.genblk6.current_op_resuses_rs1_rs2
|vpiLhs:
\_ref_obj: (div_inputs.reuse_result), line:382
|vpiName:div_inputs.reuse_result
|vpiFullName:work@taiga_wrapper.cpu.decode_block.genblk6.div_inputs.reuse_result
|vpiParameter:
\_parameter: (ALU_UNIT_WB_ID), line:190
|vpiName:ALU_UNIT_WB_ID
|INT:32
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (BRANCH_PREDICTOR_WAYS), line:159
|vpiName:BRANCH_PREDICTOR_WAYS
|INT:9
|vpiParameter:
\_parameter: (BRANCH_TABLE_ENTRIES), line:160
|vpiName:BRANCH_TABLE_ENTRIES
|INT:4
|vpiParameter:
\_parameter: (BRANCH_UNIT_ID), line:195
|vpiName:BRANCH_UNIT_ID
|INT:8
|vpiParameter:
\_parameter: (BUS_ADDR_H), line:107
|vpiName:BUS_ADDR_H
|INT:1
|vpiParameter:
\_parameter: (BUS_ADDR_L), line:106
|vpiName:BUS_ADDR_L
|INT:0
|vpiParameter:
\_parameter: (BUS_BIT_CHECK), line:108
|vpiName:BUS_BIT_CHECK
|INT:1
|vpiParameter:
\_parameter: (BUS_TYPE), line:89
|vpiName:BUS_TYPE
|INT:5
|vpiParameter:
\_parameter: (COUNTER_W), line:42
|vpiName:COUNTER_W
|INT:33
|vpiParameter:
\_parameter: (CPU_ID), line:38
|vpiName:CPU_ID
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_ADDR_WIDTH), line:113
|vpiName:C_M_AXI_ADDR_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_DATA_WIDTH), line:114
|vpiName:C_M_AXI_DATA_WIDTH
|INT:1
|vpiParameter:
\_parameter: (DCACHE_LINES), line:133
|vpiName:DCACHE_LINES
|INT:-2146435073
|vpiParameter:
\_parameter: (DCACHE_LINE_ADDR_W), line:135
|vpiName:DCACHE_LINE_ADDR_W
|INT:1073741824
|vpiParameter:
\_parameter: (DCACHE_LINE_W), line:136
|vpiName:DCACHE_LINE_W
|INT:1342177279
|vpiParameter:
\_parameter: (DCACHE_SUB_LINE_ADDR_W), line:137
|vpiName:DCACHE_SUB_LINE_ADDR_W
|INT:4
|vpiParameter:
\_parameter: (DCACHE_TAG_W), line:138
|vpiName:DCACHE_TAG_W
|INT:1610612736
|vpiParameter:
\_parameter: (DCACHE_WAYS), line:134
|vpiName:DCACHE_WAYS
|INT:4
|vpiParameter:
\_parameter: (DIV_ALGORITHM), line:67
|vpiName:DIV_ALGORITHM
|INT:0
|vpiParameter:
\_parameter: (DIV_UNIT_WB_ID), line:192
|vpiName:DIV_UNIT_WB_ID
|INT:2
|vpiParameter:
\_parameter: (DTLB_DEPTH), line:152
|vpiName:DTLB_DEPTH
|INT:512
|vpiParameter:
\_parameter: (DTLB_WAYS), line:151
|vpiName:DTLB_WAYS
|INT:32
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (ENABLE_M_MODE), line:34
|vpiName:ENABLE_M_MODE
|INT:1
|vpiParameter:
\_parameter: (ENABLE_S_MODE), line:36
|vpiName:ENABLE_S_MODE
|INT:0
|vpiParameter:
\_parameter: (ENABLE_TRACE_INTERFACE), line:172
|vpiName:ENABLE_TRACE_INTERFACE
|INT:2
|vpiParameter:
\_parameter: (FETCH_BUFFER_DEPTH), line:168
|vpiName:FETCH_BUFFER_DEPTH
|INT:512
|vpiParameter:
\_parameter: (FPGA_VENDOR), line:27
|vpiName:FPGA_VENDOR
|STRING:"xilinx"
|vpiParameter:
\_parameter: (GC_UNIT_ID), line:196
|vpiName:GC_UNIT_ID
|INT:4
|vpiParameter:
\_parameter: (ICACHE_LINES), line:121
|vpiName:ICACHE_LINES
|INT:2
|vpiParameter:
\_parameter: (ICACHE_LINE_ADDR_W), line:123
|vpiName:ICACHE_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_LINE_W), line:124
|vpiName:ICACHE_LINE_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_SUB_LINE_ADDR_W), line:125
|vpiName:ICACHE_SUB_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_TAG_W), line:126
|vpiName:ICACHE_TAG_W
|INT:-2147483648
|vpiParameter:
\_parameter: (ICACHE_WAYS), line:122
|vpiName:ICACHE_WAYS
|INT:1
|vpiParameter:
\_parameter: (ITLB_DEPTH), line:146
|vpiName:ITLB_DEPTH
|INT:32
|vpiParameter:
\_parameter: (ITLB_WAYS), line:145
|vpiName:ITLB_WAYS
|INT:4
|vpiParameter:
\_parameter: (L1_CONNECTIONS), line:177
|vpiName:L1_CONNECTIONS
|INT:9
|vpiParameter:
\_parameter: (L1_DCACHE_ID), line:178
|vpiName:L1_DCACHE_ID
|INT:4
|vpiParameter:
\_parameter: (L1_DMMU_ID), line:179
|vpiName:L1_DMMU_ID
|INT:2
|vpiParameter:
\_parameter: (L1_ICACHE_ID), line:180
|vpiName:L1_ICACHE_ID
|INT:19
|vpiParameter:
\_parameter: (L1_IMMU_ID), line:181
|vpiName:L1_IMMU_ID
|INT:0
|vpiParameter:
\_parameter: (LS_UNIT_WB_ID), line:191
|vpiName:LS_UNIT_WB_ID
|INT:1
|vpiParameter:
\_parameter: (MAX_INFLIGHT_COUNT), line:167
|vpiName:MAX_INFLIGHT_COUNT
|INT:19
|vpiParameter:
\_parameter: (MEMORY_ADDR_H), line:103
|vpiName:MEMORY_ADDR_H
|INT:12
|vpiParameter:
\_parameter: (MEMORY_ADDR_L), line:102
|vpiName:MEMORY_ADDR_L
|INT:11
|vpiParameter:
\_parameter: (MEMORY_BIT_CHECK), line:104
|vpiName:MEMORY_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (MUL_UNIT_WB_ID), line:193
|vpiName:MUL_UNIT_WB_ID
|INT:512
|vpiParameter:
\_parameter: (NUM_UNITS), line:188
|vpiName:NUM_UNITS
|INT:2
|vpiParameter:
\_parameter: (NUM_WB_UNITS), line:186
|vpiName:NUM_WB_UNITS
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (RAS_DEPTH), line:161
|vpiName:RAS_DEPTH
|INT:2
|vpiParameter:
\_parameter: (RESET_VEC), line:39
|vpiName:RESET_VEC
|INT:-2147483648
|vpiParameter:
\_parameter: (SCRATCH_ADDR_H), line:99
|vpiName:SCRATCH_ADDR_H
|INT:9
|vpiParameter:
\_parameter: (SCRATCH_ADDR_L), line:98
|vpiName:SCRATCH_ADDR_L
|INT:8
|vpiParameter:
\_parameter: (SCRATCH_BIT_CHECK), line:100
|vpiName:SCRATCH_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (USE_AMO), line:70
|vpiName:USE_AMO
|INT:1
|vpiParameter:
\_parameter: (USE_BRANCH_PREDICTOR), line:158
|vpiName:USE_BRANCH_PREDICTOR
|INT:2
|vpiParameter:
\_parameter: (USE_BUS), line:88
|vpiName:USE_BUS
|INT:4
|vpiParameter:
\_parameter: (USE_DCACHE), line:92
|vpiName:USE_DCACHE
|INT:6
|vpiParameter:
\_parameter: (USE_DIV), line:49
|vpiName:USE_DIV
|INT:1
|vpiParameter:
\_parameter: (USE_DTAG_INVALIDATIONS), line:140
|vpiName:USE_DTAG_INVALIDATIONS
|INT:1879048191
|vpiParameter:
\_parameter: (USE_D_SCRATCH_MEM), line:79
|vpiName:USE_D_SCRATCH_MEM
|INT:3
|vpiParameter:
\_parameter: (USE_ICACHE), line:93
|vpiName:USE_ICACHE
|INT:7
|vpiParameter:
\_parameter: (USE_I_SCRATCH_MEM), line:78
|vpiName:USE_I_SCRATCH_MEM
|INT:2
|vpiParameter:
\_parameter: (USE_MUL), line:48
|vpiName:USE_MUL
|INT:1
|vpiParameter:
\_parameter: (WB_UNITS_WIDTH), line:187
|vpiName:WB_UNITS_WIDTH
|INT:32
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiGenScopeArray:
\_gen_scope_array: (genblk7[0]), line:390, parent:decode_block
|vpiName:genblk7[0]
|vpiFullName:work@taiga_wrapper.cpu.decode_block.genblk7[0]
|vpiGenScope:
\_gen_scope: , parent:genblk7[0]
|vpiFullName:work@taiga_wrapper.cpu.decode_block.genblk7[0]
|vpiProcess:
\_always: , line:394
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:394
|vpiCondition:
\_operation: , line:394
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:394
|vpiName:clk
|vpiFullName:work@taiga_wrapper.cpu.decode_block.genblk7[0].clk
|vpiStmt:
\_begin: , line:394
|vpiFullName:work@taiga_wrapper.cpu.decode_block.genblk7[0]
|vpiStmt:
\_assignment: , line:395
|vpiOpType:82
|vpiLhs:
\_ref_obj: (unit_issue[i].new_request_r), line:395
|vpiName:unit_issue[i].new_request_r
|vpiFullName:work@taiga_wrapper.cpu.decode_block.genblk7[0].unit_issue[i].new_request_r
|vpiRhs:
\_bit_select: (issue), line:395
|vpiName:issue
|vpiFullName:work@taiga_wrapper.cpu.decode_block.genblk7[0].issue
|vpiIndex:
\_ref_obj: (i), line:395
|vpiName:i
|vpiContAssign:
\_cont_assign: , line:391
|vpiRhs:
\_operation: , line:391
|vpiOpType:28
|vpiOperand:
\_operation: , line:391
|vpiOpType:28
|vpiOperand:
\_operation: , line:391
|vpiOpType:28
|vpiOperand:
\_operation: , line:391
|vpiOpType:28
|vpiOperand:
\_operation: , line:391
|vpiOpType:28
|vpiOperand:
\_bit_select: (unit_requested), line:391
|vpiName:unit_requested
|vpiFullName:work@taiga_wrapper.cpu.decode_block.genblk7[0].unit_requested
|vpiIndex:
\_ref_obj: (i), line:391
|vpiName:i
|vpiOperand:
\_bit_select: (unit_ready), line:391
|vpiName:unit_ready
|vpiFullName:work@taiga_wrapper.cpu.decode_block.genblk7[0].unit_ready
|vpiIndex:
\_ref_obj: (i), line:391
|vpiName:i
|vpiFullName:work@taiga_wrapper.cpu.decode_block.genblk7[0].i
|vpiOperand:
\_bit_select: (unit_operands_ready), line:391
|vpiName:unit_operands_ready
|vpiFullName:work@taiga_wrapper.cpu.decode_block.genblk7[0].unit_operands_ready
|vpiIndex:
\_ref_obj: (i), line:391
|vpiName:i
|vpiFullName:work@taiga_wrapper.cpu.decode_block.genblk7[0].i
|vpiOperand:
\_ref_obj: (fb_valid), line:391
|vpiName:fb_valid
|vpiFullName:work@taiga_wrapper.cpu.decode_block.genblk7[0].fb_valid
|vpiOperand:
\_ref_obj: (ti.id_available), line:391
|vpiName:ti.id_available
|vpiFullName:work@taiga_wrapper.cpu.decode_block.genblk7[0].ti.id_available
|vpiOperand:
\_operation: , line:391
|vpiOpType:4
|vpiOperand:
\_ref_obj: (gc_issue_hold), line:391
|vpiName:gc_issue_hold
|vpiFullName:work@taiga_wrapper.cpu.decode_block.genblk7[0].gc_issue_hold
|vpiLhs:
\_ref_obj: (unit_issue[i].possible_issue), line:391
|vpiName:unit_issue[i].possible_issue
|vpiFullName:work@taiga_wrapper.cpu.decode_block.genblk7[0].unit_issue[i].possible_issue
|vpiContAssign:
\_cont_assign: , line:392
|vpiRhs:
\_bit_select: (issue), line:392
|vpiName:issue
|vpiFullName:work@taiga_wrapper.cpu.decode_block.genblk7[0].issue
|vpiIndex:
\_ref_obj: (i), line:392
|vpiName:i
|vpiLhs:
\_ref_obj: (unit_issue[i].new_request), line:392
|vpiName:unit_issue[i].new_request
|vpiFullName:work@taiga_wrapper.cpu.decode_block.genblk7[0].unit_issue[i].new_request
|vpiContAssign:
\_cont_assign: , line:393
|vpiRhs:
\_ref_obj: (ti.issue_id), line:393
|vpiName:ti.issue_id
|vpiFullName:work@taiga_wrapper.cpu.decode_block.genblk7[0].ti.issue_id
|vpiLhs:
\_ref_obj: (unit_issue[i].instruction_id), line:393
|vpiName:unit_issue[i].instruction_id
|vpiFullName:work@taiga_wrapper.cpu.decode_block.genblk7[0].unit_issue[i].instruction_id
|vpiParameter:
\_parameter: (ALU_UNIT_WB_ID), line:190
|vpiName:ALU_UNIT_WB_ID
|INT:32
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (BRANCH_PREDICTOR_WAYS), line:159
|vpiName:BRANCH_PREDICTOR_WAYS
|INT:9
|vpiParameter:
\_parameter: (BRANCH_TABLE_ENTRIES), line:160
|vpiName:BRANCH_TABLE_ENTRIES
|INT:4
|vpiParameter:
\_parameter: (BRANCH_UNIT_ID), line:195
|vpiName:BRANCH_UNIT_ID
|INT:8
|vpiParameter:
\_parameter: (BUS_ADDR_H), line:107
|vpiName:BUS_ADDR_H
|INT:1
|vpiParameter:
\_parameter: (BUS_ADDR_L), line:106
|vpiName:BUS_ADDR_L
|INT:0
|vpiParameter:
\_parameter: (BUS_BIT_CHECK), line:108
|vpiName:BUS_BIT_CHECK
|INT:1
|vpiParameter:
\_parameter: (BUS_TYPE), line:89
|vpiName:BUS_TYPE
|INT:5
|vpiParameter:
\_parameter: (COUNTER_W), line:42
|vpiName:COUNTER_W
|INT:33
|vpiParameter:
\_parameter: (CPU_ID), line:38
|vpiName:CPU_ID
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_ADDR_WIDTH), line:113
|vpiName:C_M_AXI_ADDR_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_DATA_WIDTH), line:114
|vpiName:C_M_AXI_DATA_WIDTH
|INT:1
|vpiParameter:
\_parameter: (DCACHE_LINES), line:133
|vpiName:DCACHE_LINES
|INT:-2146435073
|vpiParameter:
\_parameter: (DCACHE_LINE_ADDR_W), line:135
|vpiName:DCACHE_LINE_ADDR_W
|INT:1073741824
|vpiParameter:
\_parameter: (DCACHE_LINE_W), line:136
|vpiName:DCACHE_LINE_W
|INT:1342177279
|vpiParameter:
\_parameter: (DCACHE_SUB_LINE_ADDR_W), line:137
|vpiName:DCACHE_SUB_LINE_ADDR_W
|INT:4
|vpiParameter:
\_parameter: (DCACHE_TAG_W), line:138
|vpiName:DCACHE_TAG_W
|INT:1610612736
|vpiParameter:
\_parameter: (DCACHE_WAYS), line:134
|vpiName:DCACHE_WAYS
|INT:4
|vpiParameter:
\_parameter: (DIV_ALGORITHM), line:67
|vpiName:DIV_ALGORITHM
|INT:0
|vpiParameter:
\_parameter: (DIV_UNIT_WB_ID), line:192
|vpiName:DIV_UNIT_WB_ID
|INT:2
|vpiParameter:
\_parameter: (DTLB_DEPTH), line:152
|vpiName:DTLB_DEPTH
|INT:512
|vpiParameter:
\_parameter: (DTLB_WAYS), line:151
|vpiName:DTLB_WAYS
|INT:32
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (ENABLE_M_MODE), line:34
|vpiName:ENABLE_M_MODE
|INT:1
|vpiParameter:
\_parameter: (ENABLE_S_MODE), line:36
|vpiName:ENABLE_S_MODE
|INT:0
|vpiParameter:
\_parameter: (ENABLE_TRACE_INTERFACE), line:172
|vpiName:ENABLE_TRACE_INTERFACE
|INT:2
|vpiParameter:
\_parameter: (FETCH_BUFFER_DEPTH), line:168
|vpiName:FETCH_BUFFER_DEPTH
|INT:512
|vpiParameter:
\_parameter: (FPGA_VENDOR), line:27
|vpiName:FPGA_VENDOR
|STRING:"xilinx"
|vpiParameter:
\_parameter: (GC_UNIT_ID), line:196
|vpiName:GC_UNIT_ID
|INT:4
|vpiParameter:
\_parameter: (ICACHE_LINES), line:121
|vpiName:ICACHE_LINES
|INT:2
|vpiParameter:
\_parameter: (ICACHE_LINE_ADDR_W), line:123
|vpiName:ICACHE_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_LINE_W), line:124
|vpiName:ICACHE_LINE_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_SUB_LINE_ADDR_W), line:125
|vpiName:ICACHE_SUB_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_TAG_W), line:126
|vpiName:ICACHE_TAG_W
|INT:-2147483648
|vpiParameter:
\_parameter: (ICACHE_WAYS), line:122
|vpiName:ICACHE_WAYS
|INT:1
|vpiParameter:
\_parameter: (ITLB_DEPTH), line:146
|vpiName:ITLB_DEPTH
|INT:32
|vpiParameter:
\_parameter: (ITLB_WAYS), line:145
|vpiName:ITLB_WAYS
|INT:4
|vpiParameter:
\_parameter: (L1_CONNECTIONS), line:177
|vpiName:L1_CONNECTIONS
|INT:9
|vpiParameter:
\_parameter: (L1_DCACHE_ID), line:178
|vpiName:L1_DCACHE_ID
|INT:4
|vpiParameter:
\_parameter: (L1_DMMU_ID), line:179
|vpiName:L1_DMMU_ID
|INT:2
|vpiParameter:
\_parameter: (L1_ICACHE_ID), line:180
|vpiName:L1_ICACHE_ID
|INT:19
|vpiParameter:
\_parameter: (L1_IMMU_ID), line:181
|vpiName:L1_IMMU_ID
|INT:0
|vpiParameter:
\_parameter: (LS_UNIT_WB_ID), line:191
|vpiName:LS_UNIT_WB_ID
|INT:1
|vpiParameter:
\_parameter: (MAX_INFLIGHT_COUNT), line:167
|vpiName:MAX_INFLIGHT_COUNT
|INT:19
|vpiParameter:
\_parameter: (MEMORY_ADDR_H), line:103
|vpiName:MEMORY_ADDR_H
|INT:12
|vpiParameter:
\_parameter: (MEMORY_ADDR_L), line:102
|vpiName:MEMORY_ADDR_L
|INT:11
|vpiParameter:
\_parameter: (MEMORY_BIT_CHECK), line:104
|vpiName:MEMORY_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (MUL_UNIT_WB_ID), line:193
|vpiName:MUL_UNIT_WB_ID
|INT:512
|vpiParameter:
\_parameter: (NUM_UNITS), line:188
|vpiName:NUM_UNITS
|INT:2
|vpiParameter:
\_parameter: (NUM_WB_UNITS), line:186
|vpiName:NUM_WB_UNITS
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (RAS_DEPTH), line:161
|vpiName:RAS_DEPTH
|INT:2
|vpiParameter:
\_parameter: (RESET_VEC), line:39
|vpiName:RESET_VEC
|INT:-2147483648
|vpiParameter:
\_parameter: (SCRATCH_ADDR_H), line:99
|vpiName:SCRATCH_ADDR_H
|INT:9
|vpiParameter:
\_parameter: (SCRATCH_ADDR_L), line:98
|vpiName:SCRATCH_ADDR_L
|INT:8
|vpiParameter:
\_parameter: (SCRATCH_BIT_CHECK), line:100
|vpiName:SCRATCH_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (USE_AMO), line:70
|vpiName:USE_AMO
|INT:1
|vpiParameter:
\_parameter: (USE_BRANCH_PREDICTOR), line:158
|vpiName:USE_BRANCH_PREDICTOR
|INT:2
|vpiParameter:
\_parameter: (USE_BUS), line:88
|vpiName:USE_BUS
|INT:4
|vpiParameter:
\_parameter: (USE_DCACHE), line:92
|vpiName:USE_DCACHE
|INT:6
|vpiParameter:
\_parameter: (USE_DIV), line:49
|vpiName:USE_DIV
|INT:1
|vpiParameter:
\_parameter: (USE_DTAG_INVALIDATIONS), line:140
|vpiName:USE_DTAG_INVALIDATIONS
|INT:1879048191
|vpiParameter:
\_parameter: (USE_D_SCRATCH_MEM), line:79
|vpiName:USE_D_SCRATCH_MEM
|INT:3
|vpiParameter:
\_parameter: (USE_ICACHE), line:93
|vpiName:USE_ICACHE
|INT:7
|vpiParameter:
\_parameter: (USE_I_SCRATCH_MEM), line:78
|vpiName:USE_I_SCRATCH_MEM
|INT:2
|vpiParameter:
\_parameter: (USE_MUL), line:48
|vpiName:USE_MUL
|INT:1
|vpiParameter:
\_parameter: (WB_UNITS_WIDTH), line:187
|vpiName:WB_UNITS_WIDTH
|INT:32
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiParameter:
\_parameter: (i), line:390
|vpiName:i
|INT:0
|vpiGenScopeArray:
\_gen_scope_array: (genblk7[1]), line:390, parent:decode_block
|vpiName:genblk7[1]
|vpiFullName:work@taiga_wrapper.cpu.decode_block.genblk7[1]
|vpiGenScope:
\_gen_scope: , parent:genblk7[1]
|vpiFullName:work@taiga_wrapper.cpu.decode_block.genblk7[1]
|vpiProcess:
\_always: , line:394
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:394
|vpiCondition:
\_operation: , line:394
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:394
|vpiName:clk
|vpiFullName:work@taiga_wrapper.cpu.decode_block.genblk7[1].clk
|vpiStmt:
\_begin: , line:394
|vpiFullName:work@taiga_wrapper.cpu.decode_block.genblk7[1]
|vpiStmt:
\_assignment: , line:395
|vpiOpType:82
|vpiLhs:
\_ref_obj: (unit_issue[i].new_request_r), line:395
|vpiName:unit_issue[i].new_request_r
|vpiFullName:work@taiga_wrapper.cpu.decode_block.genblk7[1].unit_issue[i].new_request_r
|vpiRhs:
\_bit_select: (issue), line:395
|vpiName:issue
|vpiFullName:work@taiga_wrapper.cpu.decode_block.genblk7[1].issue
|vpiIndex:
\_ref_obj: (i), line:395
|vpiName:i
|vpiContAssign:
\_cont_assign: , line:391
|vpiRhs:
\_operation: , line:391
|vpiOpType:28
|vpiOperand:
\_operation: , line:391
|vpiOpType:28
|vpiOperand:
\_operation: , line:391
|vpiOpType:28
|vpiOperand:
\_operation: , line:391
|vpiOpType:28
|vpiOperand:
\_operation: , line:391
|vpiOpType:28
|vpiOperand:
\_bit_select: (unit_requested), line:391
|vpiName:unit_requested
|vpiFullName:work@taiga_wrapper.cpu.decode_block.genblk7[1].unit_requested
|vpiIndex:
\_ref_obj: (i), line:391
|vpiName:i
|vpiOperand:
\_bit_select: (unit_ready), line:391
|vpiName:unit_ready
|vpiFullName:work@taiga_wrapper.cpu.decode_block.genblk7[1].unit_ready
|vpiIndex:
\_ref_obj: (i), line:391
|vpiName:i
|vpiFullName:work@taiga_wrapper.cpu.decode_block.genblk7[1].i
|vpiOperand:
\_bit_select: (unit_operands_ready), line:391
|vpiName:unit_operands_ready
|vpiFullName:work@taiga_wrapper.cpu.decode_block.genblk7[1].unit_operands_ready
|vpiIndex:
\_ref_obj: (i), line:391
|vpiName:i
|vpiFullName:work@taiga_wrapper.cpu.decode_block.genblk7[1].i
|vpiOperand:
\_ref_obj: (fb_valid), line:391
|vpiName:fb_valid
|vpiFullName:work@taiga_wrapper.cpu.decode_block.genblk7[1].fb_valid
|vpiOperand:
\_ref_obj: (ti.id_available), line:391
|vpiName:ti.id_available
|vpiFullName:work@taiga_wrapper.cpu.decode_block.genblk7[1].ti.id_available
|vpiOperand:
\_operation: , line:391
|vpiOpType:4
|vpiOperand:
\_ref_obj: (gc_issue_hold), line:391
|vpiName:gc_issue_hold
|vpiFullName:work@taiga_wrapper.cpu.decode_block.genblk7[1].gc_issue_hold
|vpiLhs:
\_ref_obj: (unit_issue[i].possible_issue), line:391
|vpiName:unit_issue[i].possible_issue
|vpiFullName:work@taiga_wrapper.cpu.decode_block.genblk7[1].unit_issue[i].possible_issue
|vpiContAssign:
\_cont_assign: , line:392
|vpiRhs:
\_bit_select: (issue), line:392
|vpiName:issue
|vpiFullName:work@taiga_wrapper.cpu.decode_block.genblk7[1].issue
|vpiIndex:
\_ref_obj: (i), line:392
|vpiName:i
|vpiLhs:
\_ref_obj: (unit_issue[i].new_request), line:392
|vpiName:unit_issue[i].new_request
|vpiFullName:work@taiga_wrapper.cpu.decode_block.genblk7[1].unit_issue[i].new_request
|vpiContAssign:
\_cont_assign: , line:393
|vpiRhs:
\_ref_obj: (ti.issue_id), line:393
|vpiName:ti.issue_id
|vpiFullName:work@taiga_wrapper.cpu.decode_block.genblk7[1].ti.issue_id
|vpiLhs:
\_ref_obj: (unit_issue[i].instruction_id), line:393
|vpiName:unit_issue[i].instruction_id
|vpiFullName:work@taiga_wrapper.cpu.decode_block.genblk7[1].unit_issue[i].instruction_id
|vpiParameter:
\_parameter: (ALU_UNIT_WB_ID), line:190
|vpiName:ALU_UNIT_WB_ID
|INT:32
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (BRANCH_PREDICTOR_WAYS), line:159
|vpiName:BRANCH_PREDICTOR_WAYS
|INT:9
|vpiParameter:
\_parameter: (BRANCH_TABLE_ENTRIES), line:160
|vpiName:BRANCH_TABLE_ENTRIES
|INT:4
|vpiParameter:
\_parameter: (BRANCH_UNIT_ID), line:195
|vpiName:BRANCH_UNIT_ID
|INT:8
|vpiParameter:
\_parameter: (BUS_ADDR_H), line:107
|vpiName:BUS_ADDR_H
|INT:1
|vpiParameter:
\_parameter: (BUS_ADDR_L), line:106
|vpiName:BUS_ADDR_L
|INT:0
|vpiParameter:
\_parameter: (BUS_BIT_CHECK), line:108
|vpiName:BUS_BIT_CHECK
|INT:1
|vpiParameter:
\_parameter: (BUS_TYPE), line:89
|vpiName:BUS_TYPE
|INT:5
|vpiParameter:
\_parameter: (COUNTER_W), line:42
|vpiName:COUNTER_W
|INT:33
|vpiParameter:
\_parameter: (CPU_ID), line:38
|vpiName:CPU_ID
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_ADDR_WIDTH), line:113
|vpiName:C_M_AXI_ADDR_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_DATA_WIDTH), line:114
|vpiName:C_M_AXI_DATA_WIDTH
|INT:1
|vpiParameter:
\_parameter: (DCACHE_LINES), line:133
|vpiName:DCACHE_LINES
|INT:-2146435073
|vpiParameter:
\_parameter: (DCACHE_LINE_ADDR_W), line:135
|vpiName:DCACHE_LINE_ADDR_W
|INT:1073741824
|vpiParameter:
\_parameter: (DCACHE_LINE_W), line:136
|vpiName:DCACHE_LINE_W
|INT:1342177279
|vpiParameter:
\_parameter: (DCACHE_SUB_LINE_ADDR_W), line:137
|vpiName:DCACHE_SUB_LINE_ADDR_W
|INT:4
|vpiParameter:
\_parameter: (DCACHE_TAG_W), line:138
|vpiName:DCACHE_TAG_W
|INT:1610612736
|vpiParameter:
\_parameter: (DCACHE_WAYS), line:134
|vpiName:DCACHE_WAYS
|INT:4
|vpiParameter:
\_parameter: (DIV_ALGORITHM), line:67
|vpiName:DIV_ALGORITHM
|INT:0
|vpiParameter:
\_parameter: (DIV_UNIT_WB_ID), line:192
|vpiName:DIV_UNIT_WB_ID
|INT:2
|vpiParameter:
\_parameter: (DTLB_DEPTH), line:152
|vpiName:DTLB_DEPTH
|INT:512
|vpiParameter:
\_parameter: (DTLB_WAYS), line:151
|vpiName:DTLB_WAYS
|INT:32
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (ENABLE_M_MODE), line:34
|vpiName:ENABLE_M_MODE
|INT:1
|vpiParameter:
\_parameter: (ENABLE_S_MODE), line:36
|vpiName:ENABLE_S_MODE
|INT:0
|vpiParameter:
\_parameter: (ENABLE_TRACE_INTERFACE), line:172
|vpiName:ENABLE_TRACE_INTERFACE
|INT:2
|vpiParameter:
\_parameter: (FETCH_BUFFER_DEPTH), line:168
|vpiName:FETCH_BUFFER_DEPTH
|INT:512
|vpiParameter:
\_parameter: (FPGA_VENDOR), line:27
|vpiName:FPGA_VENDOR
|STRING:"xilinx"
|vpiParameter:
\_parameter: (GC_UNIT_ID), line:196
|vpiName:GC_UNIT_ID
|INT:4
|vpiParameter:
\_parameter: (ICACHE_LINES), line:121
|vpiName:ICACHE_LINES
|INT:2
|vpiParameter:
\_parameter: (ICACHE_LINE_ADDR_W), line:123
|vpiName:ICACHE_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_LINE_W), line:124
|vpiName:ICACHE_LINE_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_SUB_LINE_ADDR_W), line:125
|vpiName:ICACHE_SUB_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_TAG_W), line:126
|vpiName:ICACHE_TAG_W
|INT:-2147483648
|vpiParameter:
\_parameter: (ICACHE_WAYS), line:122
|vpiName:ICACHE_WAYS
|INT:1
|vpiParameter:
\_parameter: (ITLB_DEPTH), line:146
|vpiName:ITLB_DEPTH
|INT:32
|vpiParameter:
\_parameter: (ITLB_WAYS), line:145
|vpiName:ITLB_WAYS
|INT:4
|vpiParameter:
\_parameter: (L1_CONNECTIONS), line:177
|vpiName:L1_CONNECTIONS
|INT:9
|vpiParameter:
\_parameter: (L1_DCACHE_ID), line:178
|vpiName:L1_DCACHE_ID
|INT:4
|vpiParameter:
\_parameter: (L1_DMMU_ID), line:179
|vpiName:L1_DMMU_ID
|INT:2
|vpiParameter:
\_parameter: (L1_ICACHE_ID), line:180
|vpiName:L1_ICACHE_ID
|INT:19
|vpiParameter:
\_parameter: (L1_IMMU_ID), line:181
|vpiName:L1_IMMU_ID
|INT:0
|vpiParameter:
\_parameter: (LS_UNIT_WB_ID), line:191
|vpiName:LS_UNIT_WB_ID
|INT:1
|vpiParameter:
\_parameter: (MAX_INFLIGHT_COUNT), line:167
|vpiName:MAX_INFLIGHT_COUNT
|INT:19
|vpiParameter:
\_parameter: (MEMORY_ADDR_H), line:103
|vpiName:MEMORY_ADDR_H
|INT:12
|vpiParameter:
\_parameter: (MEMORY_ADDR_L), line:102
|vpiName:MEMORY_ADDR_L
|INT:11
|vpiParameter:
\_parameter: (MEMORY_BIT_CHECK), line:104
|vpiName:MEMORY_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (MUL_UNIT_WB_ID), line:193
|vpiName:MUL_UNIT_WB_ID
|INT:512
|vpiParameter:
\_parameter: (NUM_UNITS), line:188
|vpiName:NUM_UNITS
|INT:2
|vpiParameter:
\_parameter: (NUM_WB_UNITS), line:186
|vpiName:NUM_WB_UNITS
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (RAS_DEPTH), line:161
|vpiName:RAS_DEPTH
|INT:2
|vpiParameter:
\_parameter: (RESET_VEC), line:39
|vpiName:RESET_VEC
|INT:-2147483648
|vpiParameter:
\_parameter: (SCRATCH_ADDR_H), line:99
|vpiName:SCRATCH_ADDR_H
|INT:9
|vpiParameter:
\_parameter: (SCRATCH_ADDR_L), line:98
|vpiName:SCRATCH_ADDR_L
|INT:8
|vpiParameter:
\_parameter: (SCRATCH_BIT_CHECK), line:100
|vpiName:SCRATCH_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (USE_AMO), line:70
|vpiName:USE_AMO
|INT:1
|vpiParameter:
\_parameter: (USE_BRANCH_PREDICTOR), line:158
|vpiName:USE_BRANCH_PREDICTOR
|INT:2
|vpiParameter:
\_parameter: (USE_BUS), line:88
|vpiName:USE_BUS
|INT:4
|vpiParameter:
\_parameter: (USE_DCACHE), line:92
|vpiName:USE_DCACHE
|INT:6
|vpiParameter:
\_parameter: (USE_DIV), line:49
|vpiName:USE_DIV
|INT:1
|vpiParameter:
\_parameter: (USE_DTAG_INVALIDATIONS), line:140
|vpiName:USE_DTAG_INVALIDATIONS
|INT:1879048191
|vpiParameter:
\_parameter: (USE_D_SCRATCH_MEM), line:79
|vpiName:USE_D_SCRATCH_MEM
|INT:3
|vpiParameter:
\_parameter: (USE_ICACHE), line:93
|vpiName:USE_ICACHE
|INT:7
|vpiParameter:
\_parameter: (USE_I_SCRATCH_MEM), line:78
|vpiName:USE_I_SCRATCH_MEM
|INT:2
|vpiParameter:
\_parameter: (USE_MUL), line:48
|vpiName:USE_MUL
|INT:1
|vpiParameter:
\_parameter: (WB_UNITS_WIDTH), line:187
|vpiName:WB_UNITS_WIDTH
|INT:32
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiParameter:
\_parameter: (i), line:390
|vpiName:i
|INT:1
|vpiGenScopeArray:
\_gen_scope_array: (genblk8), line:425, parent:decode_block
|vpiName:genblk8
|vpiFullName:work@taiga_wrapper.cpu.decode_block.genblk8
|vpiGenScope:
\_gen_scope: , parent:genblk8
|vpiFullName:work@taiga_wrapper.cpu.decode_block.genblk8
|vpiContAssign:
\_cont_assign: , line:426
|vpiRhs:
\_operation: , line:426
|vpiOpType:28
|vpiOperand:
\_operation: , line:426
|vpiOpType:28
|vpiOperand:
\_operation: , line:426
|vpiOpType:7
|vpiOperand:
\_operation: , line:426
|vpiOpType:28
|vpiOperand:
\_ref_obj: (unit_requested), line:426
|vpiName:unit_requested
|vpiFullName:work@taiga_wrapper.cpu.decode_block.genblk8.unit_requested
|vpiOperand:
\_ref_obj: (unit_ready), line:426
|vpiName:unit_ready
|vpiFullName:work@taiga_wrapper.cpu.decode_block.genblk8.unit_ready
|vpiOperand:
\_ref_obj: (issue_valid), line:426
|vpiName:issue_valid
|vpiFullName:work@taiga_wrapper.cpu.decode_block.genblk8.issue_valid
|vpiOperand:
\_operation: , line:426
|vpiOpType:4
|vpiOperand:
\_ref_obj: (load_store_operands_ready), line:426
|vpiName:load_store_operands_ready
|vpiFullName:work@taiga_wrapper.cpu.decode_block.genblk8.load_store_operands_ready
|vpiLhs:
\_ref_obj: (tr_operand_stall), line:426
|vpiName:tr_operand_stall
|vpiFullName:work@taiga_wrapper.cpu.decode_block.genblk8.tr_operand_stall
|vpiContAssign:
\_cont_assign: , line:427
|vpiRhs:
\_operation: , line:427
|vpiOpType:28
|vpiOperand:
\_operation: , line:427
|vpiOpType:28
|vpiOperand:
\_operation: , line:427
|vpiOpType:8
|vpiOperand:
\_operation: , line:427
|vpiOpType:28
|vpiOperand:
\_ref_obj: (unit_requested), line:427
|vpiName:unit_requested
|vpiFullName:work@taiga_wrapper.cpu.decode_block.genblk8.unit_requested
|vpiOperand:
\_ref_obj: (unit_ready), line:427
|vpiName:unit_ready
|vpiFullName:work@taiga_wrapper.cpu.decode_block.genblk8.unit_ready
|vpiOperand:
\_ref_obj: (issue_valid), line:427
|vpiName:issue_valid
|vpiFullName:work@taiga_wrapper.cpu.decode_block.genblk8.issue_valid
|vpiOperand:
\_ref_obj: (load_store_operands_ready), line:427
|vpiName:load_store_operands_ready
|vpiFullName:work@taiga_wrapper.cpu.decode_block.genblk8.load_store_operands_ready
|vpiLhs:
\_ref_obj: (tr_unit_stall), line:427
|vpiName:tr_unit_stall
|vpiFullName:work@taiga_wrapper.cpu.decode_block.genblk8.tr_unit_stall
|vpiContAssign:
\_cont_assign: , line:428
|vpiRhs:
\_operation: , line:428
|vpiOpType:28
|vpiOperand:
\_operation: , line:428
|vpiOpType:28
|vpiOperand:
\_operation: , line:428
|vpiOpType:7
|vpiOperand:
\_operation: , line:428
|vpiOpType:28
|vpiOperand:
\_ref_obj: (unit_requested), line:428
|vpiName:unit_requested
|vpiFullName:work@taiga_wrapper.cpu.decode_block.genblk8.unit_requested
|vpiOperand:
\_ref_obj: (unit_ready), line:428
|vpiName:unit_ready
|vpiFullName:work@taiga_wrapper.cpu.decode_block.genblk8.unit_ready
|vpiOperand:
\_operation: , line:428
|vpiOpType:28
|vpiOperand:
\_operation: , line:428
|vpiOpType:28
|vpiOperand:
\_operation: , line:428
|vpiOpType:28
|vpiOperand:
\_ref_obj: (fb_valid), line:428
|vpiName:fb_valid
|vpiFullName:work@taiga_wrapper.cpu.decode_block.genblk8.fb_valid
|vpiOperand:
\_operation: , line:428
|vpiOpType:4
|vpiOperand:
\_ref_obj: (ti.id_available), line:428
|vpiName:ti.id_available
|vpiFullName:work@taiga_wrapper.cpu.decode_block.genblk8.ti.id_available
|vpiOperand:
\_operation: , line:428
|vpiOpType:4
|vpiOperand:
\_ref_obj: (gc_issue_hold), line:428
|vpiName:gc_issue_hold
|vpiFullName:work@taiga_wrapper.cpu.decode_block.genblk8.gc_issue_hold
|vpiOperand:
\_operation: , line:428
|vpiOpType:4
|vpiOperand:
\_ref_obj: (gc_fetch_flush), line:428
|vpiName:gc_fetch_flush
|vpiFullName:work@taiga_wrapper.cpu.decode_block.genblk8.gc_fetch_flush
|vpiOperand:
\_ref_obj: (load_store_operands_ready), line:428
|vpiName:load_store_operands_ready
|vpiFullName:work@taiga_wrapper.cpu.decode_block.genblk8.load_store_operands_ready
|vpiLhs:
\_ref_obj: (tr_no_id_stall), line:428
|vpiName:tr_no_id_stall
|vpiFullName:work@taiga_wrapper.cpu.decode_block.genblk8.tr_no_id_stall
|vpiContAssign:
\_cont_assign: , line:429
|vpiRhs:
\_operation: , line:429
|vpiOpType:4
|vpiOperand:
\_ref_obj: (fb_valid), line:429
|vpiName:fb_valid
|vpiFullName:work@taiga_wrapper.cpu.decode_block.genblk8.fb_valid
|vpiLhs:
\_ref_obj: (tr_no_instruction_stall), line:429
|vpiName:tr_no_instruction_stall
|vpiFullName:work@taiga_wrapper.cpu.decode_block.genblk8.tr_no_instruction_stall
|vpiContAssign:
\_cont_assign: , line:430
|vpiRhs:
\_operation: , line:430
|vpiOpType:28
|vpiOperand:
\_operation: , line:430
|vpiOpType:28
|vpiOperand:
\_operation: , line:430
|vpiOpType:28
|vpiOperand:
\_ref_obj: (fb_valid), line:430
|vpiName:fb_valid
|vpiFullName:work@taiga_wrapper.cpu.decode_block.genblk8.fb_valid
|vpiOperand:
\_operation: , line:430
|vpiOpType:4
|vpiOperand:
\_ref_obj: (instruction_issued), line:430
|vpiName:instruction_issued
|vpiFullName:work@taiga_wrapper.cpu.decode_block.genblk8.instruction_issued
|vpiOperand:
\_operation: , line:430
|vpiOpType:4
|vpiOperand:
\_operation: , line:430
|vpiOpType:29
|vpiOperand:
\_operation: , line:430
|vpiOpType:29
|vpiOperand:
\_operation: , line:430
|vpiOpType:29
|vpiOperand:
\_ref_obj: (tr_operand_stall), line:430
|vpiName:tr_operand_stall
|vpiFullName:work@taiga_wrapper.cpu.decode_block.genblk8.tr_operand_stall
|vpiOperand:
\_ref_obj: (tr_unit_stall), line:430
|vpiName:tr_unit_stall
|vpiFullName:work@taiga_wrapper.cpu.decode_block.genblk8.tr_unit_stall
|vpiOperand:
\_ref_obj: (tr_no_id_stall), line:430
|vpiName:tr_no_id_stall
|vpiFullName:work@taiga_wrapper.cpu.decode_block.genblk8.tr_no_id_stall
|vpiOperand:
\_ref_obj: (tr_no_instruction_stall), line:430
|vpiName:tr_no_instruction_stall
|vpiFullName:work@taiga_wrapper.cpu.decode_block.genblk8.tr_no_instruction_stall
|vpiOperand:
\_operation: , line:430
|vpiOpType:4
|vpiOperand:
\_ref_obj: (gc_fetch_flush), line:430
|vpiName:gc_fetch_flush
|vpiFullName:work@taiga_wrapper.cpu.decode_block.genblk8.gc_fetch_flush
|vpiLhs:
\_ref_obj: (tr_other_stall), line:430
|vpiName:tr_other_stall
|vpiFullName:work@taiga_wrapper.cpu.decode_block.genblk8.tr_other_stall
|vpiContAssign:
\_cont_assign: , line:431
|vpiRhs:
\_operation: , line:431
|vpiOpType:28
|vpiOperand:
\_ref_obj: (tr_operand_stall), line:431
|vpiName:tr_operand_stall
|vpiFullName:work@taiga_wrapper.cpu.decode_block.genblk8.tr_operand_stall
|vpiOperand:
\_bit_select: (unit_requested), line:431
|vpiName:unit_requested
|vpiFullName:work@taiga_wrapper.cpu.decode_block.genblk8.unit_requested
|vpiIndex:
\_ref_obj: (BRANCH_UNIT_ID), line:431
|vpiName:BRANCH_UNIT_ID
|vpiFullName:work@taiga_wrapper.cpu.decode_block.genblk8.BRANCH_UNIT_ID
|vpiLhs:
\_ref_obj: (tr_branch_operand_stall), line:431
|vpiName:tr_branch_operand_stall
|vpiFullName:work@taiga_wrapper.cpu.decode_block.genblk8.tr_branch_operand_stall
|vpiContAssign:
\_cont_assign: , line:432
|vpiRhs:
\_operation: , line:432
|vpiOpType:28
|vpiOperand:
\_operation: , line:432
|vpiOpType:28
|vpiOperand:
\_ref_obj: (tr_operand_stall), line:432
|vpiName:tr_operand_stall
|vpiFullName:work@taiga_wrapper.cpu.decode_block.genblk8.tr_operand_stall
|vpiOperand:
\_bit_select: (unit_requested), line:432
|vpiName:unit_requested
|vpiFullName:work@taiga_wrapper.cpu.decode_block.genblk8.unit_requested
|vpiIndex:
\_ref_obj: (ALU_UNIT_WB_ID), line:432
|vpiName:ALU_UNIT_WB_ID
|vpiFullName:work@taiga_wrapper.cpu.decode_block.genblk8.ALU_UNIT_WB_ID
|vpiOperand:
\_operation: , line:432
|vpiOpType:4
|vpiOperand:
\_bit_select: (unit_requested), line:432
|vpiName:unit_requested
|vpiIndex:
\_ref_obj: (BRANCH_UNIT_ID), line:432
|vpiName:BRANCH_UNIT_ID
|vpiFullName:work@taiga_wrapper.cpu.decode_block.genblk8.BRANCH_UNIT_ID
|vpiLhs:
\_ref_obj: (tr_alu_operand_stall), line:432
|vpiName:tr_alu_operand_stall
|vpiFullName:work@taiga_wrapper.cpu.decode_block.genblk8.tr_alu_operand_stall
|vpiContAssign:
\_cont_assign: , line:433
|vpiRhs:
\_operation: , line:433
|vpiOpType:28
|vpiOperand:
\_ref_obj: (tr_operand_stall), line:433
|vpiName:tr_operand_stall
|vpiFullName:work@taiga_wrapper.cpu.decode_block.genblk8.tr_operand_stall
|vpiOperand:
\_bit_select: (unit_requested), line:433
|vpiName:unit_requested
|vpiFullName:work@taiga_wrapper.cpu.decode_block.genblk8.unit_requested
|vpiIndex:
\_ref_obj: (LS_UNIT_WB_ID), line:433
|vpiName:LS_UNIT_WB_ID
|vpiFullName:work@taiga_wrapper.cpu.decode_block.genblk8.LS_UNIT_WB_ID
|vpiLhs:
\_ref_obj: (tr_ls_operand_stall), line:433
|vpiName:tr_ls_operand_stall
|vpiFullName:work@taiga_wrapper.cpu.decode_block.genblk8.tr_ls_operand_stall
|vpiContAssign:
\_cont_assign: , line:434
|vpiRhs:
\_operation: , line:434
|vpiOpType:28
|vpiOperand:
\_ref_obj: (tr_operand_stall), line:434
|vpiName:tr_operand_stall
|vpiFullName:work@taiga_wrapper.cpu.decode_block.genblk8.tr_operand_stall
|vpiOperand:
\_bit_select: (unit_requested), line:434
|vpiName:unit_requested
|vpiFullName:work@taiga_wrapper.cpu.decode_block.genblk8.unit_requested
|vpiIndex:
\_ref_obj: (DIV_UNIT_WB_ID), line:434
|vpiName:DIV_UNIT_WB_ID
|vpiFullName:work@taiga_wrapper.cpu.decode_block.genblk8.DIV_UNIT_WB_ID
|vpiLhs:
\_ref_obj: (tr_div_operand_stall), line:434
|vpiName:tr_div_operand_stall
|vpiFullName:work@taiga_wrapper.cpu.decode_block.genblk8.tr_div_operand_stall
|vpiContAssign:
\_cont_assign: , line:436
|vpiRhs:
\_ref_obj: (instruction_issued), line:436
|vpiName:instruction_issued
|vpiFullName:work@taiga_wrapper.cpu.decode_block.genblk8.instruction_issued
|vpiLhs:
\_ref_obj: (tr_instruction_issued_dec), line:436
|vpiName:tr_instruction_issued_dec
|vpiFullName:work@taiga_wrapper.cpu.decode_block.genblk8.tr_instruction_issued_dec
|vpiContAssign:
\_cont_assign: , line:437
|vpiRhs:
\_ref_obj: (fb.pc), line:437
|vpiName:fb.pc
|vpiFullName:work@taiga_wrapper.cpu.decode_block.genblk8.fb.pc
|vpiLhs:
\_ref_obj: (tr_instruction_pc_dec), line:437
|vpiName:tr_instruction_pc_dec
|vpiFullName:work@taiga_wrapper.cpu.decode_block.genblk8.tr_instruction_pc_dec
|vpiContAssign:
\_cont_assign: , line:438
|vpiRhs:
\_ref_obj: (fb.instruction), line:438
|vpiName:fb.instruction
|vpiFullName:work@taiga_wrapper.cpu.decode_block.genblk8.fb.instruction
|vpiLhs:
\_ref_obj: (tr_instruction_data_dec), line:438
|vpiName:tr_instruction_data_dec
|vpiFullName:work@taiga_wrapper.cpu.decode_block.genblk8.tr_instruction_data_dec
|vpiParameter:
\_parameter: (ALU_UNIT_WB_ID), line:190
|vpiName:ALU_UNIT_WB_ID
|INT:32
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (BRANCH_PREDICTOR_WAYS), line:159
|vpiName:BRANCH_PREDICTOR_WAYS
|INT:9
|vpiParameter:
\_parameter: (BRANCH_TABLE_ENTRIES), line:160
|vpiName:BRANCH_TABLE_ENTRIES
|INT:4
|vpiParameter:
\_parameter: (BRANCH_UNIT_ID), line:195
|vpiName:BRANCH_UNIT_ID
|INT:8
|vpiParameter:
\_parameter: (BUS_ADDR_H), line:107
|vpiName:BUS_ADDR_H
|INT:1
|vpiParameter:
\_parameter: (BUS_ADDR_L), line:106
|vpiName:BUS_ADDR_L
|INT:0
|vpiParameter:
\_parameter: (BUS_BIT_CHECK), line:108
|vpiName:BUS_BIT_CHECK
|INT:1
|vpiParameter:
\_parameter: (BUS_TYPE), line:89
|vpiName:BUS_TYPE
|INT:5
|vpiParameter:
\_parameter: (COUNTER_W), line:42
|vpiName:COUNTER_W
|INT:33
|vpiParameter:
\_parameter: (CPU_ID), line:38
|vpiName:CPU_ID
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_ADDR_WIDTH), line:113
|vpiName:C_M_AXI_ADDR_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_DATA_WIDTH), line:114
|vpiName:C_M_AXI_DATA_WIDTH
|INT:1
|vpiParameter:
\_parameter: (DCACHE_LINES), line:133
|vpiName:DCACHE_LINES
|INT:-2146435073
|vpiParameter:
\_parameter: (DCACHE_LINE_ADDR_W), line:135
|vpiName:DCACHE_LINE_ADDR_W
|INT:1073741824
|vpiParameter:
\_parameter: (DCACHE_LINE_W), line:136
|vpiName:DCACHE_LINE_W
|INT:1342177279
|vpiParameter:
\_parameter: (DCACHE_SUB_LINE_ADDR_W), line:137
|vpiName:DCACHE_SUB_LINE_ADDR_W
|INT:4
|vpiParameter:
\_parameter: (DCACHE_TAG_W), line:138
|vpiName:DCACHE_TAG_W
|INT:1610612736
|vpiParameter:
\_parameter: (DCACHE_WAYS), line:134
|vpiName:DCACHE_WAYS
|INT:4
|vpiParameter:
\_parameter: (DIV_ALGORITHM), line:67
|vpiName:DIV_ALGORITHM
|INT:0
|vpiParameter:
\_parameter: (DIV_UNIT_WB_ID), line:192
|vpiName:DIV_UNIT_WB_ID
|INT:2
|vpiParameter:
\_parameter: (DTLB_DEPTH), line:152
|vpiName:DTLB_DEPTH
|INT:512
|vpiParameter:
\_parameter: (DTLB_WAYS), line:151
|vpiName:DTLB_WAYS
|INT:32
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (ENABLE_M_MODE), line:34
|vpiName:ENABLE_M_MODE
|INT:1
|vpiParameter:
\_parameter: (ENABLE_S_MODE), line:36
|vpiName:ENABLE_S_MODE
|INT:0
|vpiParameter:
\_parameter: (ENABLE_TRACE_INTERFACE), line:172
|vpiName:ENABLE_TRACE_INTERFACE
|INT:2
|vpiParameter:
\_parameter: (FETCH_BUFFER_DEPTH), line:168
|vpiName:FETCH_BUFFER_DEPTH
|INT:512
|vpiParameter:
\_parameter: (FPGA_VENDOR), line:27
|vpiName:FPGA_VENDOR
|STRING:"xilinx"
|vpiParameter:
\_parameter: (GC_UNIT_ID), line:196
|vpiName:GC_UNIT_ID
|INT:4
|vpiParameter:
\_parameter: (ICACHE_LINES), line:121
|vpiName:ICACHE_LINES
|INT:2
|vpiParameter:
\_parameter: (ICACHE_LINE_ADDR_W), line:123
|vpiName:ICACHE_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_LINE_W), line:124
|vpiName:ICACHE_LINE_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_SUB_LINE_ADDR_W), line:125
|vpiName:ICACHE_SUB_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_TAG_W), line:126
|vpiName:ICACHE_TAG_W
|INT:-2147483648
|vpiParameter:
\_parameter: (ICACHE_WAYS), line:122
|vpiName:ICACHE_WAYS
|INT:1
|vpiParameter:
\_parameter: (ITLB_DEPTH), line:146
|vpiName:ITLB_DEPTH
|INT:32
|vpiParameter:
\_parameter: (ITLB_WAYS), line:145
|vpiName:ITLB_WAYS
|INT:4
|vpiParameter:
\_parameter: (L1_CONNECTIONS), line:177
|vpiName:L1_CONNECTIONS
|INT:9
|vpiParameter:
\_parameter: (L1_DCACHE_ID), line:178
|vpiName:L1_DCACHE_ID
|INT:4
|vpiParameter:
\_parameter: (L1_DMMU_ID), line:179
|vpiName:L1_DMMU_ID
|INT:2
|vpiParameter:
\_parameter: (L1_ICACHE_ID), line:180
|vpiName:L1_ICACHE_ID
|INT:19
|vpiParameter:
\_parameter: (L1_IMMU_ID), line:181
|vpiName:L1_IMMU_ID
|INT:0
|vpiParameter:
\_parameter: (LS_UNIT_WB_ID), line:191
|vpiName:LS_UNIT_WB_ID
|INT:1
|vpiParameter:
\_parameter: (MAX_INFLIGHT_COUNT), line:167
|vpiName:MAX_INFLIGHT_COUNT
|INT:19
|vpiParameter:
\_parameter: (MEMORY_ADDR_H), line:103
|vpiName:MEMORY_ADDR_H
|INT:12
|vpiParameter:
\_parameter: (MEMORY_ADDR_L), line:102
|vpiName:MEMORY_ADDR_L
|INT:11
|vpiParameter:
\_parameter: (MEMORY_BIT_CHECK), line:104
|vpiName:MEMORY_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (MUL_UNIT_WB_ID), line:193
|vpiName:MUL_UNIT_WB_ID
|INT:512
|vpiParameter:
\_parameter: (NUM_UNITS), line:188
|vpiName:NUM_UNITS
|INT:2
|vpiParameter:
\_parameter: (NUM_WB_UNITS), line:186
|vpiName:NUM_WB_UNITS
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (RAS_DEPTH), line:161
|vpiName:RAS_DEPTH
|INT:2
|vpiParameter:
\_parameter: (RESET_VEC), line:39
|vpiName:RESET_VEC
|INT:-2147483648
|vpiParameter:
\_parameter: (SCRATCH_ADDR_H), line:99
|vpiName:SCRATCH_ADDR_H
|INT:9
|vpiParameter:
\_parameter: (SCRATCH_ADDR_L), line:98
|vpiName:SCRATCH_ADDR_L
|INT:8
|vpiParameter:
\_parameter: (SCRATCH_BIT_CHECK), line:100
|vpiName:SCRATCH_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (USE_AMO), line:70
|vpiName:USE_AMO
|INT:1
|vpiParameter:
\_parameter: (USE_BRANCH_PREDICTOR), line:158
|vpiName:USE_BRANCH_PREDICTOR
|INT:2
|vpiParameter:
\_parameter: (USE_BUS), line:88
|vpiName:USE_BUS
|INT:4
|vpiParameter:
\_parameter: (USE_DCACHE), line:92
|vpiName:USE_DCACHE
|INT:6
|vpiParameter:
\_parameter: (USE_DIV), line:49
|vpiName:USE_DIV
|INT:1
|vpiParameter:
\_parameter: (USE_DTAG_INVALIDATIONS), line:140
|vpiName:USE_DTAG_INVALIDATIONS
|INT:1879048191
|vpiParameter:
\_parameter: (USE_D_SCRATCH_MEM), line:79
|vpiName:USE_D_SCRATCH_MEM
|INT:3
|vpiParameter:
\_parameter: (USE_ICACHE), line:93
|vpiName:USE_ICACHE
|INT:7
|vpiParameter:
\_parameter: (USE_I_SCRATCH_MEM), line:78
|vpiName:USE_I_SCRATCH_MEM
|INT:2
|vpiParameter:
\_parameter: (USE_MUL), line:48
|vpiName:USE_MUL
|INT:1
|vpiParameter:
\_parameter: (WB_UNITS_WIDTH), line:187
|vpiName:WB_UNITS_WIDTH
|INT:32
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiNet:
\_logic_net: (clk), line:27, parent:decode_block
|vpiNet:
\_logic_net: (rst), line:28, parent:decode_block
|vpiNet:
\_logic_net: (pre_decode_pop), line:30, parent:decode_block
|vpiNet:
\_logic_net: (fb_valid), line:31, parent:decode_block
|vpiNet:
\_logic_net: (fb), line:32, parent:decode_block
|vpiNet:
\_logic_net: (alu_inputs), line:37, parent:decode_block
|vpiNet:
\_logic_net: (ls_inputs), line:38, parent:decode_block
|vpiNet:
\_logic_net: (branch_inputs), line:39, parent:decode_block
|vpiNet:
\_logic_net: (gc_inputs), line:40, parent:decode_block
|vpiNet:
\_logic_net: (mul_inputs), line:41, parent:decode_block
|vpiNet:
\_logic_net: (div_inputs), line:42, parent:decode_block
|vpiNet:
\_logic_net: (gc_issue_hold), line:46, parent:decode_block
|vpiNet:
\_logic_net: (gc_fetch_flush), line:47, parent:decode_block
|vpiNet:
\_logic_net: (gc_issue_flush), line:48, parent:decode_block
|vpiNet:
\_logic_net: (gc_flush_required), line:49, parent:decode_block
|vpiNet:
\_logic_net: (load_store_issue), line:51, parent:decode_block
|vpiNet:
\_logic_net: (store_issued_with_data), line:52, parent:decode_block
|vpiNet:
\_logic_net: (store_data), line:53, parent:decode_block
|vpiNet:
\_logic_net: (instruction_issued), line:55, parent:decode_block
|vpiName:instruction_issued
|vpiFullName:work@taiga_wrapper.cpu.decode_block.instruction_issued
|vpiNetType:36
|vpiNet:
\_logic_net: (instruction_issued_no_rd), line:56, parent:decode_block
|vpiNet:
\_logic_net: (instruction_issued_with_rd), line:57, parent:decode_block
|vpiNet:
\_logic_net: (illegal_instruction), line:58, parent:decode_block
|vpiNet:
\_logic_net: (tr_operand_stall), line:61, parent:decode_block
|vpiNet:
\_logic_net: (tr_unit_stall), line:62, parent:decode_block
|vpiNet:
\_logic_net: (tr_no_id_stall), line:63, parent:decode_block
|vpiNet:
\_logic_net: (tr_no_instruction_stall), line:64, parent:decode_block
|vpiNet:
\_logic_net: (tr_other_stall), line:65, parent:decode_block
|vpiNet:
\_logic_net: (tr_branch_operand_stall), line:66, parent:decode_block
|vpiNet:
\_logic_net: (tr_alu_operand_stall), line:67, parent:decode_block
|vpiNet:
\_logic_net: (tr_ls_operand_stall), line:68, parent:decode_block
|vpiNet:
\_logic_net: (tr_div_operand_stall), line:69, parent:decode_block
|vpiNet:
\_logic_net: (tr_instruction_issued_dec), line:71, parent:decode_block
|vpiNet:
\_logic_net: (tr_instruction_pc_dec), line:72, parent:decode_block
|vpiNet:
\_logic_net: (tr_instruction_data_dec), line:73, parent:decode_block
|vpiNet:
\_logic_net: (fn3), line:76, parent:decode_block
|vpiName:fn3
|vpiFullName:work@taiga_wrapper.cpu.decode_block.fn3
|vpiNetType:36
|vpiRange:
\_range: , line:76
|vpiLeftRange:
\_constant: , line:76
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiRightRange:
\_constant: , line:76
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (opcode), line:77, parent:decode_block
|vpiName:opcode
|vpiFullName:work@taiga_wrapper.cpu.decode_block.opcode
|vpiNetType:36
|vpiRange:
\_range: , line:77
|vpiLeftRange:
\_constant: , line:77
|vpiConstType:7
|vpiDecompile:6
|vpiSize:32
|INT:6
|vpiRightRange:
\_constant: , line:77
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (opcode_trim), line:78, parent:decode_block
|vpiName:opcode_trim
|vpiFullName:work@taiga_wrapper.cpu.decode_block.opcode_trim
|vpiNetType:36
|vpiRange:
\_range: , line:78
|vpiLeftRange:
\_constant: , line:78
|vpiConstType:7
|vpiDecompile:4
|vpiSize:32
|INT:4
|vpiRightRange:
\_constant: , line:78
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (uses_rs1), line:80, parent:decode_block
|vpiName:uses_rs1
|vpiFullName:work@taiga_wrapper.cpu.decode_block.uses_rs1
|vpiNetType:36
|vpiNet:
\_logic_net: (uses_rs2), line:81, parent:decode_block
|vpiName:uses_rs2
|vpiFullName:work@taiga_wrapper.cpu.decode_block.uses_rs2
|vpiNetType:36
|vpiNet:
\_logic_net: (uses_rd), line:82, parent:decode_block
|vpiName:uses_rd
|vpiFullName:work@taiga_wrapper.cpu.decode_block.uses_rd
|vpiNetType:36
|vpiNet:
\_logic_net: (rd_zero), line:83, parent:decode_block
|vpiName:rd_zero
|vpiFullName:work@taiga_wrapper.cpu.decode_block.rd_zero
|vpiNetType:36
|vpiNet:
\_logic_net: (rs1_addr), line:85, parent:decode_block
|vpiName:rs1_addr
|vpiFullName:work@taiga_wrapper.cpu.decode_block.rs1_addr
|vpiNetType:36
|vpiRange:
\_range: , line:85
|vpiLeftRange:
\_constant: , line:85
|vpiConstType:7
|vpiDecompile:4
|vpiSize:32
|INT:4
|vpiRightRange:
\_constant: , line:85
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (rs2_addr), line:86, parent:decode_block
|vpiName:rs2_addr
|vpiFullName:work@taiga_wrapper.cpu.decode_block.rs2_addr
|vpiNetType:36
|vpiRange:
\_range: , line:86
|vpiLeftRange:
\_constant: , line:86
|vpiConstType:7
|vpiDecompile:4
|vpiSize:32
|INT:4
|vpiRightRange:
\_constant: , line:86
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (future_rd_addr), line:87, parent:decode_block
|vpiName:future_rd_addr
|vpiFullName:work@taiga_wrapper.cpu.decode_block.future_rd_addr
|vpiNetType:36
|vpiRange:
\_range: , line:87
|vpiLeftRange:
\_constant: , line:87
|vpiConstType:7
|vpiDecompile:4
|vpiSize:32
|INT:4
|vpiRightRange:
\_constant: , line:87
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (nop), line:89, parent:decode_block
|vpiName:nop
|vpiFullName:work@taiga_wrapper.cpu.decode_block.nop
|vpiNetType:36
|vpiNet:
\_logic_net: (store_data_in_use_by_load_op), line:93, parent:decode_block
|vpiName:store_data_in_use_by_load_op
|vpiFullName:work@taiga_wrapper.cpu.decode_block.store_data_in_use_by_load_op
|vpiNetType:36
|vpiNet:
\_logic_net: (load_store_forward_possible), line:94, parent:decode_block
|vpiName:load_store_forward_possible
|vpiFullName:work@taiga_wrapper.cpu.decode_block.load_store_forward_possible
|vpiNetType:36
|vpiNet:
\_logic_net: (issue_valid), line:96, parent:decode_block
|vpiName:issue_valid
|vpiFullName:work@taiga_wrapper.cpu.decode_block.issue_valid
|vpiNetType:36
|vpiNet:
\_logic_net: (load_store_operands_ready), line:97, parent:decode_block
|vpiName:load_store_operands_ready
|vpiFullName:work@taiga_wrapper.cpu.decode_block.load_store_operands_ready
|vpiNetType:36
|vpiNet:
\_logic_net: (operands_ready), line:98, parent:decode_block
|vpiName:operands_ready
|vpiFullName:work@taiga_wrapper.cpu.decode_block.operands_ready
|vpiNetType:36
|vpiNet:
\_logic_net: (unit_operands_ready), line:99, parent:decode_block
|vpiName:unit_operands_ready
|vpiFullName:work@taiga_wrapper.cpu.decode_block.unit_operands_ready
|vpiNetType:36
|vpiRange:
\_range: , line:99
|vpiLeftRange:
\_constant: , line:99
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:99
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (mult_div_op), line:100, parent:decode_block
|vpiName:mult_div_op
|vpiFullName:work@taiga_wrapper.cpu.decode_block.mult_div_op
|vpiNetType:36
|vpiNet:
\_logic_net: (unit_requested_for_id_gen), line:102, parent:decode_block
|vpiName:unit_requested_for_id_gen
|vpiFullName:work@taiga_wrapper.cpu.decode_block.unit_requested_for_id_gen
|vpiNetType:36
|vpiRange:
\_range: , line:102
|vpiLeftRange:
\_constant: , line:102
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:102
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (unit_requested_for_id_gen_int), line:103, parent:decode_block
|vpiName:unit_requested_for_id_gen_int
|vpiFullName:work@taiga_wrapper.cpu.decode_block.unit_requested_for_id_gen_int
|vpiNetType:36
|vpiRange:
\_range: , line:103
|vpiLeftRange:
\_constant: , line:103
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:103
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (unit_requested), line:104, parent:decode_block
|vpiName:unit_requested
|vpiFullName:work@taiga_wrapper.cpu.decode_block.unit_requested
|vpiNetType:36
|vpiRange:
\_range: , line:104
|vpiLeftRange:
\_constant: , line:104
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:104
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (unit_ready), line:105, parent:decode_block
|vpiName:unit_ready
|vpiFullName:work@taiga_wrapper.cpu.decode_block.unit_ready
|vpiNetType:36
|vpiRange:
\_range: , line:105
|vpiLeftRange:
\_constant: , line:105
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:105
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (issue), line:106, parent:decode_block
|vpiName:issue
|vpiFullName:work@taiga_wrapper.cpu.decode_block.issue
|vpiNetType:36
|vpiRange:
\_range: , line:106
|vpiLeftRange:
\_constant: , line:106
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:106
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (valid_opcode), line:108, parent:decode_block
|vpiName:valid_opcode
|vpiFullName:work@taiga_wrapper.cpu.decode_block.valid_opcode
|vpiNetType:36
|vpiNet:
\_logic_net: (ls_offset), line:111, parent:decode_block
|vpiName:ls_offset
|vpiFullName:work@taiga_wrapper.cpu.decode_block.ls_offset
|vpiNetType:36
|vpiRange:
\_range: , line:111
|vpiLeftRange:
\_constant: , line:111
|vpiConstType:7
|vpiDecompile:11
|vpiSize:32
|INT:11
|vpiRightRange:
\_constant: , line:111
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (is_load), line:112, parent:decode_block
|vpiName:is_load
|vpiFullName:work@taiga_wrapper.cpu.decode_block.is_load
|vpiNetType:36
|vpiNet:
\_logic_net: (is_store), line:113, parent:decode_block
|vpiName:is_store
|vpiFullName:work@taiga_wrapper.cpu.decode_block.is_store
|vpiNetType:36
|vpiNet:
\_logic_net: (amo_op), line:114, parent:decode_block
|vpiName:amo_op
|vpiFullName:work@taiga_wrapper.cpu.decode_block.amo_op
|vpiNetType:36
|vpiNet:
\_logic_net: (store_conditional), line:115, parent:decode_block
|vpiName:store_conditional
|vpiFullName:work@taiga_wrapper.cpu.decode_block.store_conditional
|vpiNetType:36
|vpiNet:
\_logic_net: (load_reserve), line:116, parent:decode_block
|vpiName:load_reserve
|vpiFullName:work@taiga_wrapper.cpu.decode_block.load_reserve
|vpiNetType:36
|vpiNet:
\_logic_net: (amo_type), line:117, parent:decode_block
|vpiName:amo_type
|vpiFullName:work@taiga_wrapper.cpu.decode_block.amo_type
|vpiNetType:36
|vpiRange:
\_range: , line:117
|vpiLeftRange:
\_constant: , line:117
|vpiConstType:7
|vpiDecompile:4
|vpiSize:32
|INT:4
|vpiRightRange:
\_constant: , line:117
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (alu_rs1_data), line:221, parent:decode_block
|vpiName:alu_rs1_data
|vpiFullName:work@taiga_wrapper.cpu.decode_block.alu_rs1_data
|vpiNetType:36
|vpiRange:
\_range: , line:221
|vpiLeftRange:
\_constant: , line:221
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiRightRange:
\_constant: , line:221
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (alu_rs2_data), line:222, parent:decode_block
|vpiName:alu_rs2_data
|vpiFullName:work@taiga_wrapper.cpu.decode_block.alu_rs2_data
|vpiNetType:36
|vpiRange:
\_range: , line:222
|vpiLeftRange:
\_constant: , line:222
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiRightRange:
\_constant: , line:222
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (sfence), line:303, parent:decode_block
|vpiName:sfence
|vpiFullName:work@taiga_wrapper.cpu.decode_block.sfence
|vpiNetType:36
|vpiNet:
\_logic_net: (ifence), line:304, parent:decode_block
|vpiName:ifence
|vpiFullName:work@taiga_wrapper.cpu.decode_block.ifence
|vpiNetType:36
|vpiNet:
\_logic_net: (environment_op), line:305, parent:decode_block
|vpiName:environment_op
|vpiFullName:work@taiga_wrapper.cpu.decode_block.environment_op
|vpiNetType:36
|vpiNet:
\_logic_net: (is_csr), line:306, parent:decode_block
|vpiName:is_csr
|vpiFullName:work@taiga_wrapper.cpu.decode_block.is_csr
|vpiNetType:36
|vpiNet:
\_logic_net: (ti), line:34, parent:decode_block
|vpiName:ti
|vpiFullName:work@taiga_wrapper.cpu.decode_block.ti
|vpiNet:
\_logic_net: (rf_decode), line:35, parent:decode_block
|vpiName:rf_decode
|vpiFullName:work@taiga_wrapper.cpu.decode_block.rf_decode
|vpiNet:
\_logic_net: (unit_issue), line:44, parent:decode_block
|vpiName:unit_issue
|vpiFullName:work@taiga_wrapper.cpu.decode_block.unit_issue
|vpiInstance:
\_module: work@taiga (cpu), file:third_party/cores/taiga/examples/zedboard/taiga_wrapper.sv, line:233, parent:work@taiga_wrapper
|vpiArrayNet:
\_array_net: (register_in_use_by_load_op), line:91, parent:decode_block
|vpiName:register_in_use_by_load_op
|vpiFullName:work@taiga_wrapper.cpu.decode_block.register_in_use_by_load_op
|vpiSize:32
|vpiNet:
\_logic_net: , parent:register_in_use_by_load_op
|vpiFullName:work@taiga_wrapper.cpu.decode_block.register_in_use_by_load_op
|vpiNetType:36
|vpiRange:
\_range: , line:91
|vpiLeftRange:
\_constant: , line:91
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:91
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiVariables:
\_logic_var: (issue_id), line:146, parent:decode_block
|vpiName:issue_id
|vpiFullName:work@taiga_wrapper.cpu.decode_block.issue_id
|vpiVariables:
\_struct_var: (inflight_packet), line:149, parent:decode_block
|vpiName:inflight_packet
|vpiFullName:work@taiga_wrapper.cpu.decode_block.inflight_packet
|vpiTypespec:
\_struct_typespec: (inflight_instruction_packet), line:271
|vpiVariables:
\_logic_var: (id), line:109, parent:decode_block
|vpiName:id
|vpiFullName:work@taiga_wrapper.cpu.decode_block.id
|vpiVariables:
\_logic_var: (rs2_id), line:115, parent:decode_block
|vpiName:rs2_id
|vpiFullName:work@taiga_wrapper.cpu.decode_block.rs2_id
|vpiVariables:
\_logic_var: (instruction_id), line:56, parent:decode_block
|vpiName:instruction_id
|vpiFullName:work@taiga_wrapper.cpu.decode_block.instruction_id
|vpiParameter:
\_parameter: (ALU_UNIT_WB_ID), line:190
|vpiName:ALU_UNIT_WB_ID
|INT:32
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (BRANCH_PREDICTOR_WAYS), line:159
|vpiName:BRANCH_PREDICTOR_WAYS
|INT:9
|vpiParameter:
\_parameter: (BRANCH_TABLE_ENTRIES), line:160
|vpiName:BRANCH_TABLE_ENTRIES
|INT:4
|vpiParameter:
\_parameter: (BRANCH_UNIT_ID), line:195
|vpiName:BRANCH_UNIT_ID
|INT:8
|vpiParameter:
\_parameter: (BUS_ADDR_H), line:107
|vpiName:BUS_ADDR_H
|INT:1
|vpiParameter:
\_parameter: (BUS_ADDR_L), line:106
|vpiName:BUS_ADDR_L
|INT:0
|vpiParameter:
\_parameter: (BUS_BIT_CHECK), line:108
|vpiName:BUS_BIT_CHECK
|INT:1
|vpiParameter:
\_parameter: (BUS_TYPE), line:89
|vpiName:BUS_TYPE
|INT:5
|vpiParameter:
\_parameter: (COUNTER_W), line:42
|vpiName:COUNTER_W
|INT:33
|vpiParameter:
\_parameter: (CPU_ID), line:38
|vpiName:CPU_ID
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_ADDR_WIDTH), line:113
|vpiName:C_M_AXI_ADDR_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_DATA_WIDTH), line:114
|vpiName:C_M_AXI_DATA_WIDTH
|INT:1
|vpiParameter:
\_parameter: (DCACHE_LINES), line:133
|vpiName:DCACHE_LINES
|INT:-2146435073
|vpiParameter:
\_parameter: (DCACHE_LINE_ADDR_W), line:135
|vpiName:DCACHE_LINE_ADDR_W
|INT:1073741824
|vpiParameter:
\_parameter: (DCACHE_LINE_W), line:136
|vpiName:DCACHE_LINE_W
|INT:1342177279
|vpiParameter:
\_parameter: (DCACHE_SUB_LINE_ADDR_W), line:137
|vpiName:DCACHE_SUB_LINE_ADDR_W
|INT:4
|vpiParameter:
\_parameter: (DCACHE_TAG_W), line:138
|vpiName:DCACHE_TAG_W
|INT:1610612736
|vpiParameter:
\_parameter: (DCACHE_WAYS), line:134
|vpiName:DCACHE_WAYS
|INT:4
|vpiParameter:
\_parameter: (DIV_ALGORITHM), line:67
|vpiName:DIV_ALGORITHM
|INT:0
|vpiParameter:
\_parameter: (DIV_UNIT_WB_ID), line:192
|vpiName:DIV_UNIT_WB_ID
|INT:2
|vpiParameter:
\_parameter: (DTLB_DEPTH), line:152
|vpiName:DTLB_DEPTH
|INT:512
|vpiParameter:
\_parameter: (DTLB_WAYS), line:151
|vpiName:DTLB_WAYS
|INT:32
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (ENABLE_M_MODE), line:34
|vpiName:ENABLE_M_MODE
|INT:1
|vpiParameter:
\_parameter: (ENABLE_S_MODE), line:36
|vpiName:ENABLE_S_MODE
|INT:0
|vpiParameter:
\_parameter: (ENABLE_TRACE_INTERFACE), line:172
|vpiName:ENABLE_TRACE_INTERFACE
|INT:2
|vpiParameter:
\_parameter: (FETCH_BUFFER_DEPTH), line:168
|vpiName:FETCH_BUFFER_DEPTH
|INT:512
|vpiParameter:
\_parameter: (FPGA_VENDOR), line:27
|vpiName:FPGA_VENDOR
|STRING:"xilinx"
|vpiParameter:
\_parameter: (GC_UNIT_ID), line:196
|vpiName:GC_UNIT_ID
|INT:4
|vpiParameter:
\_parameter: (ICACHE_LINES), line:121
|vpiName:ICACHE_LINES
|INT:2
|vpiParameter:
\_parameter: (ICACHE_LINE_ADDR_W), line:123
|vpiName:ICACHE_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_LINE_W), line:124
|vpiName:ICACHE_LINE_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_SUB_LINE_ADDR_W), line:125
|vpiName:ICACHE_SUB_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_TAG_W), line:126
|vpiName:ICACHE_TAG_W
|INT:-2147483648
|vpiParameter:
\_parameter: (ICACHE_WAYS), line:122
|vpiName:ICACHE_WAYS
|INT:1
|vpiParameter:
\_parameter: (ITLB_DEPTH), line:146
|vpiName:ITLB_DEPTH
|INT:32
|vpiParameter:
\_parameter: (ITLB_WAYS), line:145
|vpiName:ITLB_WAYS
|INT:4
|vpiParameter:
\_parameter: (L1_CONNECTIONS), line:177
|vpiName:L1_CONNECTIONS
|INT:9
|vpiParameter:
\_parameter: (L1_DCACHE_ID), line:178
|vpiName:L1_DCACHE_ID
|INT:4
|vpiParameter:
\_parameter: (L1_DMMU_ID), line:179
|vpiName:L1_DMMU_ID
|INT:2
|vpiParameter:
\_parameter: (L1_ICACHE_ID), line:180
|vpiName:L1_ICACHE_ID
|INT:19
|vpiParameter:
\_parameter: (L1_IMMU_ID), line:181
|vpiName:L1_IMMU_ID
|INT:0
|vpiParameter:
\_parameter: (LS_UNIT_WB_ID), line:191
|vpiName:LS_UNIT_WB_ID
|INT:1
|vpiParameter:
\_parameter: (MAX_INFLIGHT_COUNT), line:167
|vpiName:MAX_INFLIGHT_COUNT
|INT:19
|vpiParameter:
\_parameter: (MEMORY_ADDR_H), line:103
|vpiName:MEMORY_ADDR_H
|INT:12
|vpiParameter:
\_parameter: (MEMORY_ADDR_L), line:102
|vpiName:MEMORY_ADDR_L
|INT:11
|vpiParameter:
\_parameter: (MEMORY_BIT_CHECK), line:104
|vpiName:MEMORY_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (MUL_UNIT_WB_ID), line:193
|vpiName:MUL_UNIT_WB_ID
|INT:512
|vpiParameter:
\_parameter: (NUM_UNITS), line:188
|vpiName:NUM_UNITS
|INT:2
|vpiParameter:
\_parameter: (NUM_WB_UNITS), line:186
|vpiName:NUM_WB_UNITS
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (RAS_DEPTH), line:161
|vpiName:RAS_DEPTH
|INT:2
|vpiParameter:
\_parameter: (RESET_VEC), line:39
|vpiName:RESET_VEC
|INT:-2147483648
|vpiParameter:
\_parameter: (SCRATCH_ADDR_H), line:99
|vpiName:SCRATCH_ADDR_H
|INT:9
|vpiParameter:
\_parameter: (SCRATCH_ADDR_L), line:98
|vpiName:SCRATCH_ADDR_L
|INT:8
|vpiParameter:
\_parameter: (SCRATCH_BIT_CHECK), line:100
|vpiName:SCRATCH_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (USE_AMO), line:70
|vpiName:USE_AMO
|INT:1
|vpiParameter:
\_parameter: (USE_BRANCH_PREDICTOR), line:158
|vpiName:USE_BRANCH_PREDICTOR
|INT:2
|vpiParameter:
\_parameter: (USE_BUS), line:88
|vpiName:USE_BUS
|INT:4
|vpiParameter:
\_parameter: (USE_DCACHE), line:92
|vpiName:USE_DCACHE
|INT:6
|vpiParameter:
\_parameter: (USE_DIV), line:49
|vpiName:USE_DIV
|INT:1
|vpiParameter:
\_parameter: (USE_DTAG_INVALIDATIONS), line:140
|vpiName:USE_DTAG_INVALIDATIONS
|INT:1879048191
|vpiParameter:
\_parameter: (USE_D_SCRATCH_MEM), line:79
|vpiName:USE_D_SCRATCH_MEM
|INT:3
|vpiParameter:
\_parameter: (USE_ICACHE), line:93
|vpiName:USE_ICACHE
|INT:7
|vpiParameter:
\_parameter: (USE_I_SCRATCH_MEM), line:78
|vpiName:USE_I_SCRATCH_MEM
|INT:2
|vpiParameter:
\_parameter: (USE_MUL), line:48
|vpiName:USE_MUL
|INT:1
|vpiParameter:
\_parameter: (WB_UNITS_WIDTH), line:187
|vpiName:WB_UNITS_WIDTH
|INT:32
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiModule:
\_module: work@register_file (register_file_block), file:third_party/cores/taiga/core/taiga.sv, line:177, parent:cpu
|vpiDefName:work@register_file
|vpiName:register_file_block
|vpiFullName:work@taiga_wrapper.cpu.register_file_block
|vpiPort:
\_port: (clk), line:27, parent:register_file_block
|vpiName:clk
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (clk), line:177
|vpiName:clk
|vpiActual:
\_logic_net: (clk), line:27, parent:cpu
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (clk), line:27, parent:register_file_block
|vpiName:clk
|vpiFullName:work@taiga_wrapper.cpu.register_file_block.clk
|vpiNetType:36
|vpiPort:
\_port: (rst), line:28, parent:register_file_block
|vpiName:rst
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (rst), line:177
|vpiName:rst
|vpiActual:
\_logic_net: (rst), line:28, parent:cpu
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (rst), line:28, parent:register_file_block
|vpiName:rst
|vpiFullName:work@taiga_wrapper.cpu.register_file_block.rst
|vpiNetType:36
|vpiPort:
\_port: (gc_supress_writeback), line:29, parent:register_file_block
|vpiName:gc_supress_writeback
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (gc_supress_writeback), line:177
|vpiName:gc_supress_writeback
|vpiActual:
\_logic_net: (gc_supress_writeback), line:97, parent:cpu
|vpiName:gc_supress_writeback
|vpiFullName:work@taiga_wrapper.cpu.gc_supress_writeback
|vpiNetType:36
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (gc_supress_writeback), line:29, parent:register_file_block
|vpiName:gc_supress_writeback
|vpiFullName:work@taiga_wrapper.cpu.register_file_block.gc_supress_writeback
|vpiNetType:36
|vpiPort:
\_port: (instruction_issued), line:31, parent:register_file_block
|vpiName:instruction_issued
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (instruction_issued), line:177
|vpiName:instruction_issued
|vpiActual:
\_logic_net: (instruction_issued), line:111, parent:cpu
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (instruction_issued), line:116
|vpiName:instruction_issued
|vpiNetType:36
|vpiPort:
\_port: (rf_wb), line:32, parent:register_file_block
|vpiName:rf_wb
|vpiDirection:5
|vpiHighConn:
\_ref_obj: (rf_wb), line:177
|vpiName:rf_wb
|vpiActual:
\_interface: work@register_file_writeback_interface (rf_wb), file:third_party/cores/taiga/core/taiga.sv, line:71
|vpiDefName:work@register_file_writeback_interface
|vpiName:rf_wb
|vpiModport:
\_modport: (unit)
|vpiName:unit
|vpiIODecl:
\_io_decl: (rd_addr)
|vpiName:rd_addr
|vpiDirection:1
|vpiIODecl:
\_io_decl: (retiring)
|vpiName:retiring
|vpiDirection:1
|vpiIODecl:
\_io_decl: (rd_nzero)
|vpiName:rd_nzero
|vpiDirection:1
|vpiIODecl:
\_io_decl: (rd_data)
|vpiName:rd_data
|vpiDirection:1
|vpiIODecl:
\_io_decl: (id)
|vpiName:id
|vpiDirection:1
|vpiIODecl:
\_io_decl: (rs1_data)
|vpiName:rs1_data
|vpiDirection:1
|vpiIODecl:
\_io_decl: (rs2_data)
|vpiName:rs2_data
|vpiDirection:1
|vpiIODecl:
\_io_decl: (rs1_valid)
|vpiName:rs1_valid
|vpiDirection:1
|vpiIODecl:
\_io_decl: (rs2_valid)
|vpiName:rs2_valid
|vpiDirection:1
|vpiIODecl:
\_io_decl: (rs1_id)
|vpiName:rs1_id
|vpiDirection:2
|vpiIODecl:
\_io_decl: (rs2_id)
|vpiName:rs2_id
|vpiDirection:2
|vpiInterface:
\_interface: work@register_file_writeback_interface (rf_wb), file:third_party/cores/taiga/core/taiga.sv, line:71
|vpiModport:
\_modport: (writeback)
|vpiName:writeback
|vpiIODecl:
\_io_decl: (rd_addr)
|vpiName:rd_addr
|vpiDirection:2
|vpiIODecl:
\_io_decl: (retiring)
|vpiName:retiring
|vpiDirection:2
|vpiIODecl:
\_io_decl: (rd_nzero)
|vpiName:rd_nzero
|vpiDirection:2
|vpiIODecl:
\_io_decl: (rd_data)
|vpiName:rd_data
|vpiDirection:2
|vpiIODecl:
\_io_decl: (id)
|vpiName:id
|vpiDirection:2
|vpiIODecl:
\_io_decl: (rs1_data)
|vpiName:rs1_data
|vpiDirection:2
|vpiIODecl:
\_io_decl: (rs2_data)
|vpiName:rs2_data
|vpiDirection:2
|vpiIODecl:
\_io_decl: (rs1_valid)
|vpiName:rs1_valid
|vpiDirection:2
|vpiIODecl:
\_io_decl: (rs2_valid)
|vpiName:rs2_valid
|vpiDirection:2
|vpiIODecl:
\_io_decl: (rs1_id)
|vpiName:rs1_id
|vpiDirection:1
|vpiIODecl:
\_io_decl: (rs2_id)
|vpiName:rs2_id
|vpiDirection:1
|vpiInterface:
\_interface: work@register_file_writeback_interface (rf_wb), file:third_party/cores/taiga/core/taiga.sv, line:71
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_modport: (unit)
|vpiName:unit
|vpiIODecl:
\_io_decl: (rd_addr)
|vpiName:rd_addr
|vpiDirection:1
|vpiExpr:
\_logic_net: (rd_addr), line:124
|vpiName:rd_addr
|vpiNetType:36
|vpiRange:
\_range: , line:124
|vpiLeftRange:
\_constant: , line:124
|vpiConstType:7
|vpiDecompile:4
|vpiSize:32
|INT:4
|vpiRightRange:
\_constant: , line:124
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (retiring)
|vpiName:retiring
|vpiDirection:1
|vpiExpr:
\_logic_net: (retiring), line:125
|vpiName:retiring
|vpiNetType:36
|vpiIODecl:
\_io_decl: (rd_nzero)
|vpiName:rd_nzero
|vpiDirection:1
|vpiExpr:
\_logic_net: (rd_nzero), line:126
|vpiName:rd_nzero
|vpiNetType:36
|vpiIODecl:
\_io_decl: (rd_data)
|vpiName:rd_data
|vpiDirection:1
|vpiExpr:
\_logic_net: (rd_data), line:128
|vpiName:rd_data
|vpiNetType:36
|vpiRange:
\_range: , line:128
|vpiLeftRange:
\_constant: , line:128
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiRightRange:
\_constant: , line:128
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (id)
|vpiName:id
|vpiDirection:1
|vpiIODecl:
\_io_decl: (rs1_data)
|vpiName:rs1_data
|vpiDirection:1
|vpiExpr:
\_logic_net: (rs1_data), line:134
|vpiName:rs1_data
|vpiNetType:36
|vpiRange:
\_range: , line:134
|vpiLeftRange:
\_constant: , line:134
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiRightRange:
\_constant: , line:134
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (rs2_data)
|vpiName:rs2_data
|vpiDirection:1
|vpiExpr:
\_logic_net: (rs2_data), line:135
|vpiName:rs2_data
|vpiNetType:36
|vpiRange:
\_range: , line:135
|vpiLeftRange:
\_constant: , line:135
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiRightRange:
\_constant: , line:135
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (rs1_valid)
|vpiName:rs1_valid
|vpiDirection:1
|vpiExpr:
\_logic_net: (rs1_valid), line:136
|vpiName:rs1_valid
|vpiNetType:36
|vpiIODecl:
\_io_decl: (rs2_valid)
|vpiName:rs2_valid
|vpiDirection:1
|vpiExpr:
\_logic_net: (rs2_valid), line:137
|vpiName:rs2_valid
|vpiNetType:36
|vpiIODecl:
\_io_decl: (rs1_id)
|vpiName:rs1_id
|vpiDirection:2
|vpiIODecl:
\_io_decl: (rs2_id)
|vpiName:rs2_id
|vpiDirection:2
|vpiInterface:
\_interface: work@register_file_writeback_interface (rf_wb), file:third_party/cores/taiga/core/taiga.sv, line:177
|vpiDefName:work@register_file_writeback_interface
|vpiName:rf_wb
|vpiModport:
\_modport: (unit)
|vpiModport:
\_modport: (writeback)
|vpiName:writeback
|vpiIODecl:
\_io_decl: (rd_addr)
|vpiName:rd_addr
|vpiDirection:2
|vpiExpr:
\_logic_net: (rd_addr), line:124
|vpiIODecl:
\_io_decl: (retiring)
|vpiName:retiring
|vpiDirection:2
|vpiExpr:
\_logic_net: (retiring), line:125
|vpiIODecl:
\_io_decl: (rd_nzero)
|vpiName:rd_nzero
|vpiDirection:2
|vpiExpr:
\_logic_net: (rd_nzero), line:126
|vpiIODecl:
\_io_decl: (rd_data)
|vpiName:rd_data
|vpiDirection:2
|vpiExpr:
\_logic_net: (rd_data), line:128
|vpiIODecl:
\_io_decl: (id)
|vpiName:id
|vpiDirection:2
|vpiIODecl:
\_io_decl: (rs1_data)
|vpiName:rs1_data
|vpiDirection:2
|vpiExpr:
\_logic_net: (rs1_data), line:134
|vpiIODecl:
\_io_decl: (rs2_data)
|vpiName:rs2_data
|vpiDirection:2
|vpiExpr:
\_logic_net: (rs2_data), line:135
|vpiIODecl:
\_io_decl: (rs1_valid)
|vpiName:rs1_valid
|vpiDirection:2
|vpiExpr:
\_logic_net: (rs1_valid), line:136
|vpiIODecl:
\_io_decl: (rs2_valid)
|vpiName:rs2_valid
|vpiDirection:2
|vpiExpr:
\_logic_net: (rs2_valid), line:137
|vpiIODecl:
\_io_decl: (rs1_id)
|vpiName:rs1_id
|vpiDirection:1
|vpiIODecl:
\_io_decl: (rs2_id)
|vpiName:rs2_id
|vpiDirection:1
|vpiInterface:
\_interface: work@register_file_writeback_interface (rf_wb), file:third_party/cores/taiga/core/taiga.sv, line:177
|vpiPort:
\_port: (rf_decode), line:33, parent:register_file_block
|vpiName:rf_decode
|vpiDirection:5
|vpiHighConn:
\_ref_obj: (rf_decode), line:177
|vpiName:rf_decode
|vpiActual:
\_interface: work@register_file_decode_interface (rf_decode), file:third_party/cores/taiga/core/taiga.sv, line:56
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_modport: (unit)
|vpiName:unit
|vpiIODecl:
\_io_decl: (future_rd_addr)
|vpiName:future_rd_addr
|vpiDirection:1
|vpiExpr:
\_logic_net: (future_rd_addr), line:104
|vpiName:future_rd_addr
|vpiNetType:36
|vpiRange:
\_range: , line:104
|vpiLeftRange:
\_constant: , line:104
|vpiConstType:7
|vpiDecompile:4
|vpiSize:32
|INT:4
|vpiRightRange:
\_constant: , line:104
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (rs1_addr)
|vpiName:rs1_addr
|vpiDirection:1
|vpiExpr:
\_logic_net: (rs1_addr), line:105
|vpiName:rs1_addr
|vpiNetType:36
|vpiRange:
\_range: , line:105
|vpiLeftRange:
\_constant: , line:105
|vpiConstType:7
|vpiDecompile:4
|vpiSize:32
|INT:4
|vpiRightRange:
\_constant: , line:105
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (rs2_addr)
|vpiName:rs2_addr
|vpiDirection:1
|vpiExpr:
\_logic_net: (rs2_addr), line:107
|vpiName:rs2_addr
|vpiNetType:36
|vpiRange:
\_range: , line:107
|vpiLeftRange:
\_constant: , line:107
|vpiConstType:7
|vpiDecompile:4
|vpiSize:32
|INT:4
|vpiRightRange:
\_constant: , line:107
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (instruction_issued)
|vpiName:instruction_issued
|vpiDirection:1
|vpiExpr:
\_logic_net: (instruction_issued), line:116
|vpiIODecl:
\_io_decl: (id)
|vpiName:id
|vpiDirection:1
|vpiIODecl:
\_io_decl: (uses_rs1)
|vpiName:uses_rs1
|vpiDirection:1
|vpiExpr:
\_logic_net: (uses_rs1), line:111
|vpiName:uses_rs1
|vpiNetType:36
|vpiIODecl:
\_io_decl: (uses_rs2)
|vpiName:uses_rs2
|vpiDirection:1
|vpiExpr:
\_logic_net: (uses_rs2), line:112
|vpiName:uses_rs2
|vpiNetType:36
|vpiIODecl:
\_io_decl: (rs1_conflict)
|vpiName:rs1_conflict
|vpiDirection:2
|vpiExpr:
\_logic_net: (rs1_conflict), line:113
|vpiName:rs1_conflict
|vpiNetType:36
|vpiIODecl:
\_io_decl: (rs2_conflict)
|vpiName:rs2_conflict
|vpiDirection:2
|vpiExpr:
\_logic_net: (rs2_conflict), line:114
|vpiName:rs2_conflict
|vpiNetType:36
|vpiIODecl:
\_io_decl: (rs1_data)
|vpiName:rs1_data
|vpiDirection:2
|vpiExpr:
\_logic_net: (rs1_data), line:134
|vpiIODecl:
\_io_decl: (rs2_data)
|vpiName:rs2_data
|vpiDirection:2
|vpiExpr:
\_logic_net: (rs2_data), line:135
|vpiIODecl:
\_io_decl: (rs2_id)
|vpiName:rs2_id
|vpiDirection:2
|vpiInterface:
\_interface: work@register_file_decode_interface (rf_decode), file:third_party/cores/taiga/core/taiga.sv, line:177
|vpiDefName:work@register_file_decode_interface
|vpiName:rf_decode
|vpiModport:
\_modport: (decode)
|vpiName:decode
|vpiIODecl:
\_io_decl: (future_rd_addr)
|vpiName:future_rd_addr
|vpiDirection:2
|vpiExpr:
\_logic_net: (future_rd_addr), line:104
|vpiIODecl:
\_io_decl: (rs1_addr)
|vpiName:rs1_addr
|vpiDirection:2
|vpiExpr:
\_logic_net: (rs1_addr), line:105
|vpiIODecl:
\_io_decl: (rs2_addr)
|vpiName:rs2_addr
|vpiDirection:2
|vpiExpr:
\_logic_net: (rs2_addr), line:107
|vpiIODecl:
\_io_decl: (instruction_issued)
|vpiName:instruction_issued
|vpiDirection:2
|vpiExpr:
\_logic_net: (instruction_issued), line:116
|vpiIODecl:
\_io_decl: (id)
|vpiName:id
|vpiDirection:2
|vpiIODecl:
\_io_decl: (uses_rs1)
|vpiName:uses_rs1
|vpiDirection:2
|vpiExpr:
\_logic_net: (uses_rs1), line:111
|vpiIODecl:
\_io_decl: (uses_rs2)
|vpiName:uses_rs2
|vpiDirection:2
|vpiExpr:
\_logic_net: (uses_rs2), line:112
|vpiIODecl:
\_io_decl: (rs1_conflict)
|vpiName:rs1_conflict
|vpiDirection:1
|vpiExpr:
\_logic_net: (rs1_conflict), line:113
|vpiIODecl:
\_io_decl: (rs2_conflict)
|vpiName:rs2_conflict
|vpiDirection:1
|vpiExpr:
\_logic_net: (rs2_conflict), line:114
|vpiIODecl:
\_io_decl: (rs1_data)
|vpiName:rs1_data
|vpiDirection:1
|vpiExpr:
\_logic_net: (rs1_data), line:134
|vpiIODecl:
\_io_decl: (rs2_data)
|vpiName:rs2_data
|vpiDirection:1
|vpiExpr:
\_logic_net: (rs2_data), line:135
|vpiIODecl:
\_io_decl: (rs2_id)
|vpiName:rs2_id
|vpiDirection:1
|vpiInterface:
\_interface: work@register_file_decode_interface (rf_decode), file:third_party/cores/taiga/core/taiga.sv, line:177
|vpiModport:
\_modport: (unit)
|vpiPort:
\_port: (tr_rs1_forwarding_needed), line:36, parent:register_file_block
|vpiName:tr_rs1_forwarding_needed
|vpiDirection:2
|vpiHighConn:
\_ref_obj: (tr_rs1_forwarding_needed), line:177
|vpiName:tr_rs1_forwarding_needed
|vpiActual:
\_logic_net: (tr_rs1_forwarding_needed), line:145, parent:cpu
|vpiName:tr_rs1_forwarding_needed
|vpiFullName:work@taiga_wrapper.cpu.tr_rs1_forwarding_needed
|vpiNetType:36
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (tr_rs1_forwarding_needed), line:36, parent:register_file_block
|vpiName:tr_rs1_forwarding_needed
|vpiFullName:work@taiga_wrapper.cpu.register_file_block.tr_rs1_forwarding_needed
|vpiNetType:36
|vpiPort:
\_port: (tr_rs2_forwarding_needed), line:37, parent:register_file_block
|vpiName:tr_rs2_forwarding_needed
|vpiDirection:2
|vpiHighConn:
\_ref_obj: (tr_rs2_forwarding_needed), line:177
|vpiName:tr_rs2_forwarding_needed
|vpiActual:
\_logic_net: (tr_rs2_forwarding_needed), line:146, parent:cpu
|vpiName:tr_rs2_forwarding_needed
|vpiFullName:work@taiga_wrapper.cpu.tr_rs2_forwarding_needed
|vpiNetType:36
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (tr_rs2_forwarding_needed), line:37, parent:register_file_block
|vpiName:tr_rs2_forwarding_needed
|vpiFullName:work@taiga_wrapper.cpu.register_file_block.tr_rs2_forwarding_needed
|vpiNetType:36
|vpiPort:
\_port: (tr_rs1_and_rs2_forwarding_needed), line:38, parent:register_file_block
|vpiName:tr_rs1_and_rs2_forwarding_needed
|vpiDirection:2
|vpiHighConn:
\_ref_obj: (tr_rs1_and_rs2_forwarding_needed), line:177
|vpiName:tr_rs1_and_rs2_forwarding_needed
|vpiActual:
\_logic_net: (tr_rs1_and_rs2_forwarding_needed), line:147, parent:cpu
|vpiName:tr_rs1_and_rs2_forwarding_needed
|vpiFullName:work@taiga_wrapper.cpu.tr_rs1_and_rs2_forwarding_needed
|vpiNetType:36
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (tr_rs1_and_rs2_forwarding_needed), line:38, parent:register_file_block
|vpiName:tr_rs1_and_rs2_forwarding_needed
|vpiFullName:work@taiga_wrapper.cpu.register_file_block.tr_rs1_and_rs2_forwarding_needed
|vpiNetType:36
|vpiModule:
\_module: work@id_inuse (inuse_mem), file:third_party/cores/taiga/core/register_file.sv, line:67, parent:register_file_block
|vpiDefName:work@id_inuse
|vpiName:inuse_mem
|vpiFullName:work@taiga_wrapper.cpu.register_file_block.inuse_mem
|vpiPort:
\_port: (clk), line:27, parent:inuse_mem
|vpiName:clk
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (clk), line:67
|vpiName:clk
|vpiActual:
\_logic_net: (clk), line:27, parent:register_file_block
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (clk), line:27, parent:inuse_mem
|vpiName:clk
|vpiFullName:work@taiga_wrapper.cpu.register_file_block.inuse_mem.clk
|vpiNetType:36
|vpiPort:
\_port: (rst), line:28, parent:inuse_mem
|vpiName:rst
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (rst), line:67
|vpiName:rst
|vpiActual:
\_logic_net: (rst), line:28, parent:register_file_block
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (rst), line:28, parent:inuse_mem
|vpiName:rst
|vpiFullName:work@taiga_wrapper.cpu.register_file_block.inuse_mem.rst
|vpiNetType:36
|vpiPort:
\_port: (rs1_addr), line:29, parent:inuse_mem
|vpiName:rs1_addr
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (rs1_addr), line:67
|vpiName:rs1_addr
|vpiActual:
\_logic_net: (rs1_addr), line:105
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (rs1_addr), line:29, parent:inuse_mem
|vpiName:rs1_addr
|vpiFullName:work@taiga_wrapper.cpu.register_file_block.inuse_mem.rs1_addr
|vpiNetType:36
|vpiRange:
\_range: , line:29
|vpiLeftRange:
\_constant: , line:29
|vpiConstType:7
|vpiDecompile:4
|vpiSize:32
|INT:4
|vpiRightRange:
\_constant: , line:29
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiPort:
\_port: (rs2_addr), line:30, parent:inuse_mem
|vpiName:rs2_addr
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (rs2_addr), line:67
|vpiName:rs2_addr
|vpiActual:
\_logic_net: (rs2_addr), line:107
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (rs2_addr), line:30, parent:inuse_mem
|vpiName:rs2_addr
|vpiFullName:work@taiga_wrapper.cpu.register_file_block.inuse_mem.rs2_addr
|vpiNetType:36
|vpiRange:
\_range: , line:30
|vpiLeftRange:
\_constant: , line:30
|vpiConstType:7
|vpiDecompile:4
|vpiSize:32
|INT:4
|vpiRightRange:
\_constant: , line:30
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiPort:
\_port: (issued_rd_addr), line:31, parent:inuse_mem
|vpiName:issued_rd_addr
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (issued_rd_addr), line:67
|vpiName:issued_rd_addr
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (issued_rd_addr), line:31, parent:inuse_mem
|vpiName:issued_rd_addr
|vpiFullName:work@taiga_wrapper.cpu.register_file_block.inuse_mem.issued_rd_addr
|vpiNetType:36
|vpiRange:
\_range: , line:31
|vpiLeftRange:
\_constant: , line:31
|vpiConstType:7
|vpiDecompile:4
|vpiSize:32
|INT:4
|vpiRightRange:
\_constant: , line:31
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiPort:
\_port: (issue_id), line:32, parent:inuse_mem
|vpiName:issue_id
|vpiDirection:1
|vpiTypedef:
\_logic_typespec: (instruction_id_t), line:30
|vpiHighConn:
\_ref_obj: (issue_id), line:67
|vpiName:issue_id
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (issue_id), line:32, parent:inuse_mem
|vpiName:issue_id
|vpiFullName:work@taiga_wrapper.cpu.register_file_block.inuse_mem.issue_id
|vpiPort:
\_port: (retired_id), line:33, parent:inuse_mem
|vpiName:retired_id
|vpiDirection:1
|vpiTypedef:
\_logic_typespec: (instruction_id_t), line:30
|vpiHighConn:
\_ref_obj: (retired_id), line:67
|vpiName:retired_id
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (retired_id), line:33, parent:inuse_mem
|vpiName:retired_id
|vpiFullName:work@taiga_wrapper.cpu.register_file_block.inuse_mem.retired_id
|vpiPort:
\_port: (issued), line:34, parent:inuse_mem
|vpiName:issued
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (issued), line:67
|vpiName:issued
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (issued), line:34, parent:inuse_mem
|vpiName:issued
|vpiFullName:work@taiga_wrapper.cpu.register_file_block.inuse_mem.issued
|vpiNetType:36
|vpiPort:
\_port: (retired), line:35, parent:inuse_mem
|vpiName:retired
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (retired), line:67
|vpiName:retired
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (retired), line:35, parent:inuse_mem
|vpiName:retired
|vpiFullName:work@taiga_wrapper.cpu.register_file_block.inuse_mem.retired
|vpiNetType:36
|vpiPort:
\_port: (rs1_inuse), line:36, parent:inuse_mem
|vpiName:rs1_inuse
|vpiDirection:2
|vpiHighConn:
\_ref_obj: (rs1_inuse), line:67
|vpiName:rs1_inuse
|vpiActual:
\_logic_net: (rs1_inuse), line:44, parent:register_file_block
|vpiName:rs1_inuse
|vpiFullName:work@taiga_wrapper.cpu.register_file_block.rs1_inuse
|vpiNetType:36
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (rs1_inuse), line:36, parent:inuse_mem
|vpiName:rs1_inuse
|vpiFullName:work@taiga_wrapper.cpu.register_file_block.inuse_mem.rs1_inuse
|vpiNetType:36
|vpiPort:
\_port: (rs2_inuse), line:37, parent:inuse_mem
|vpiName:rs2_inuse
|vpiDirection:2
|vpiHighConn:
\_ref_obj: (rs2_inuse), line:67
|vpiName:rs2_inuse
|vpiActual:
\_logic_net: (rs2_inuse), line:45, parent:register_file_block
|vpiName:rs2_inuse
|vpiFullName:work@taiga_wrapper.cpu.register_file_block.rs2_inuse
|vpiNetType:36
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (rs2_inuse), line:37, parent:inuse_mem
|vpiName:rs2_inuse
|vpiFullName:work@taiga_wrapper.cpu.register_file_block.inuse_mem.rs2_inuse
|vpiNetType:36
|vpiNet:
\_logic_net: (clk), line:27, parent:inuse_mem
|vpiNet:
\_logic_net: (rst), line:28, parent:inuse_mem
|vpiNet:
\_logic_net: (rs1_addr), line:29, parent:inuse_mem
|vpiNet:
\_logic_net: (rs2_addr), line:30, parent:inuse_mem
|vpiNet:
\_logic_net: (issued_rd_addr), line:31, parent:inuse_mem
|vpiNet:
\_logic_net: (issue_id), line:32, parent:inuse_mem
|vpiNet:
\_logic_net: (retired_id), line:33, parent:inuse_mem
|vpiNet:
\_logic_net: (issued), line:34, parent:inuse_mem
|vpiNet:
\_logic_net: (retired), line:35, parent:inuse_mem
|vpiNet:
\_logic_net: (rs1_inuse), line:36, parent:inuse_mem
|vpiNet:
\_logic_net: (rs2_inuse), line:37, parent:inuse_mem
|vpiNet:
\_logic_net: (id_inuse), line:42, parent:inuse_mem
|vpiName:id_inuse
|vpiFullName:work@taiga_wrapper.cpu.register_file_block.inuse_mem.id_inuse
|vpiNetType:36
|vpiRange:
\_range: , line:42
|vpiLeftRange:
\_constant: , line:42
|vpiConstType:7
|vpiDecompile:18
|vpiSize:32
|INT:18
|vpiRightRange:
\_constant: , line:42
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (id_inuse_new), line:43, parent:inuse_mem
|vpiName:id_inuse_new
|vpiFullName:work@taiga_wrapper.cpu.register_file_block.inuse_mem.id_inuse_new
|vpiNetType:36
|vpiRange:
\_range: , line:43
|vpiLeftRange:
\_constant: , line:43
|vpiConstType:7
|vpiDecompile:18
|vpiSize:32
|INT:18
|vpiRightRange:
\_constant: , line:43
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (issue_id_one_hot), line:45, parent:inuse_mem
|vpiName:issue_id_one_hot
|vpiFullName:work@taiga_wrapper.cpu.register_file_block.inuse_mem.issue_id_one_hot
|vpiNetType:36
|vpiRange:
\_range: , line:45
|vpiLeftRange:
\_constant: , line:45
|vpiConstType:7
|vpiDecompile:18
|vpiSize:32
|INT:18
|vpiRightRange:
\_constant: , line:45
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (retired_id_one_hot), line:46, parent:inuse_mem
|vpiName:retired_id_one_hot
|vpiFullName:work@taiga_wrapper.cpu.register_file_block.inuse_mem.retired_id_one_hot
|vpiNetType:36
|vpiRange:
\_range: , line:46
|vpiLeftRange:
\_constant: , line:46
|vpiConstType:7
|vpiDecompile:18
|vpiSize:32
|INT:18
|vpiRightRange:
\_constant: , line:46
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiInstance:
\_module: work@register_file (register_file_block), file:third_party/cores/taiga/core/taiga.sv, line:177, parent:cpu
|vpiArrayNet:
\_array_net: (rd_addr_list), line:40, parent:inuse_mem
|vpiName:rd_addr_list
|vpiFullName:work@taiga_wrapper.cpu.register_file_block.inuse_mem.rd_addr_list
|vpiSize:19
|vpiNet:
\_logic_net: , parent:rd_addr_list
|vpiFullName:work@taiga_wrapper.cpu.register_file_block.inuse_mem.rd_addr_list
|vpiNetType:36
|vpiRange:
\_range: , line:40
|vpiLeftRange:
\_constant: , line:40
|vpiConstType:7
|vpiDecompile:4
|vpiSize:32
|INT:4
|vpiRightRange:
\_constant: , line:40
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiRange:
\_range: , line:40
|vpiLeftRange:
\_constant: , line:40
|vpiConstType:7
|vpiDecompile:18
|vpiSize:32
|INT:18
|vpiRightRange:
\_constant: , line:40
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiParameter:
\_parameter: (ALU_UNIT_WB_ID), line:190
|vpiName:ALU_UNIT_WB_ID
|INT:32
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (BRANCH_PREDICTOR_WAYS), line:159
|vpiName:BRANCH_PREDICTOR_WAYS
|INT:9
|vpiParameter:
\_parameter: (BRANCH_TABLE_ENTRIES), line:160
|vpiName:BRANCH_TABLE_ENTRIES
|INT:4
|vpiParameter:
\_parameter: (BRANCH_UNIT_ID), line:195
|vpiName:BRANCH_UNIT_ID
|INT:8
|vpiParameter:
\_parameter: (BUS_ADDR_H), line:107
|vpiName:BUS_ADDR_H
|INT:1
|vpiParameter:
\_parameter: (BUS_ADDR_L), line:106
|vpiName:BUS_ADDR_L
|INT:0
|vpiParameter:
\_parameter: (BUS_BIT_CHECK), line:108
|vpiName:BUS_BIT_CHECK
|INT:1
|vpiParameter:
\_parameter: (BUS_TYPE), line:89
|vpiName:BUS_TYPE
|INT:5
|vpiParameter:
\_parameter: (COUNTER_W), line:42
|vpiName:COUNTER_W
|INT:33
|vpiParameter:
\_parameter: (CPU_ID), line:38
|vpiName:CPU_ID
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_ADDR_WIDTH), line:113
|vpiName:C_M_AXI_ADDR_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_DATA_WIDTH), line:114
|vpiName:C_M_AXI_DATA_WIDTH
|INT:1
|vpiParameter:
\_parameter: (DCACHE_LINES), line:133
|vpiName:DCACHE_LINES
|INT:-2146435073
|vpiParameter:
\_parameter: (DCACHE_LINE_ADDR_W), line:135
|vpiName:DCACHE_LINE_ADDR_W
|INT:1073741824
|vpiParameter:
\_parameter: (DCACHE_LINE_W), line:136
|vpiName:DCACHE_LINE_W
|INT:1342177279
|vpiParameter:
\_parameter: (DCACHE_SUB_LINE_ADDR_W), line:137
|vpiName:DCACHE_SUB_LINE_ADDR_W
|INT:4
|vpiParameter:
\_parameter: (DCACHE_TAG_W), line:138
|vpiName:DCACHE_TAG_W
|INT:1610612736
|vpiParameter:
\_parameter: (DCACHE_WAYS), line:134
|vpiName:DCACHE_WAYS
|INT:4
|vpiParameter:
\_parameter: (DIV_ALGORITHM), line:67
|vpiName:DIV_ALGORITHM
|INT:0
|vpiParameter:
\_parameter: (DIV_UNIT_WB_ID), line:192
|vpiName:DIV_UNIT_WB_ID
|INT:2
|vpiParameter:
\_parameter: (DTLB_DEPTH), line:152
|vpiName:DTLB_DEPTH
|INT:512
|vpiParameter:
\_parameter: (DTLB_WAYS), line:151
|vpiName:DTLB_WAYS
|INT:32
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (ENABLE_M_MODE), line:34
|vpiName:ENABLE_M_MODE
|INT:1
|vpiParameter:
\_parameter: (ENABLE_S_MODE), line:36
|vpiName:ENABLE_S_MODE
|INT:0
|vpiParameter:
\_parameter: (ENABLE_TRACE_INTERFACE), line:172
|vpiName:ENABLE_TRACE_INTERFACE
|INT:2
|vpiParameter:
\_parameter: (FETCH_BUFFER_DEPTH), line:168
|vpiName:FETCH_BUFFER_DEPTH
|INT:512
|vpiParameter:
\_parameter: (FPGA_VENDOR), line:27
|vpiName:FPGA_VENDOR
|STRING:"xilinx"
|vpiParameter:
\_parameter: (GC_UNIT_ID), line:196
|vpiName:GC_UNIT_ID
|INT:4
|vpiParameter:
\_parameter: (ICACHE_LINES), line:121
|vpiName:ICACHE_LINES
|INT:2
|vpiParameter:
\_parameter: (ICACHE_LINE_ADDR_W), line:123
|vpiName:ICACHE_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_LINE_W), line:124
|vpiName:ICACHE_LINE_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_SUB_LINE_ADDR_W), line:125
|vpiName:ICACHE_SUB_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_TAG_W), line:126
|vpiName:ICACHE_TAG_W
|INT:-2147483648
|vpiParameter:
\_parameter: (ICACHE_WAYS), line:122
|vpiName:ICACHE_WAYS
|INT:1
|vpiParameter:
\_parameter: (ITLB_DEPTH), line:146
|vpiName:ITLB_DEPTH
|INT:32
|vpiParameter:
\_parameter: (ITLB_WAYS), line:145
|vpiName:ITLB_WAYS
|INT:4
|vpiParameter:
\_parameter: (L1_CONNECTIONS), line:177
|vpiName:L1_CONNECTIONS
|INT:9
|vpiParameter:
\_parameter: (L1_DCACHE_ID), line:178
|vpiName:L1_DCACHE_ID
|INT:4
|vpiParameter:
\_parameter: (L1_DMMU_ID), line:179
|vpiName:L1_DMMU_ID
|INT:2
|vpiParameter:
\_parameter: (L1_ICACHE_ID), line:180
|vpiName:L1_ICACHE_ID
|INT:19
|vpiParameter:
\_parameter: (L1_IMMU_ID), line:181
|vpiName:L1_IMMU_ID
|INT:0
|vpiParameter:
\_parameter: (LS_UNIT_WB_ID), line:191
|vpiName:LS_UNIT_WB_ID
|INT:1
|vpiParameter:
\_parameter: (MAX_INFLIGHT_COUNT), line:167
|vpiName:MAX_INFLIGHT_COUNT
|INT:19
|vpiParameter:
\_parameter: (MEMORY_ADDR_H), line:103
|vpiName:MEMORY_ADDR_H
|INT:12
|vpiParameter:
\_parameter: (MEMORY_ADDR_L), line:102
|vpiName:MEMORY_ADDR_L
|INT:11
|vpiParameter:
\_parameter: (MEMORY_BIT_CHECK), line:104
|vpiName:MEMORY_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (MUL_UNIT_WB_ID), line:193
|vpiName:MUL_UNIT_WB_ID
|INT:512
|vpiParameter:
\_parameter: (NUM_UNITS), line:188
|vpiName:NUM_UNITS
|INT:2
|vpiParameter:
\_parameter: (NUM_WB_UNITS), line:186
|vpiName:NUM_WB_UNITS
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (RAS_DEPTH), line:161
|vpiName:RAS_DEPTH
|INT:2
|vpiParameter:
\_parameter: (RESET_VEC), line:39
|vpiName:RESET_VEC
|INT:-2147483648
|vpiParameter:
\_parameter: (SCRATCH_ADDR_H), line:99
|vpiName:SCRATCH_ADDR_H
|INT:9
|vpiParameter:
\_parameter: (SCRATCH_ADDR_L), line:98
|vpiName:SCRATCH_ADDR_L
|INT:8
|vpiParameter:
\_parameter: (SCRATCH_BIT_CHECK), line:100
|vpiName:SCRATCH_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (USE_AMO), line:70
|vpiName:USE_AMO
|INT:1
|vpiParameter:
\_parameter: (USE_BRANCH_PREDICTOR), line:158
|vpiName:USE_BRANCH_PREDICTOR
|INT:2
|vpiParameter:
\_parameter: (USE_BUS), line:88
|vpiName:USE_BUS
|INT:4
|vpiParameter:
\_parameter: (USE_DCACHE), line:92
|vpiName:USE_DCACHE
|INT:6
|vpiParameter:
\_parameter: (USE_DIV), line:49
|vpiName:USE_DIV
|INT:1
|vpiParameter:
\_parameter: (USE_DTAG_INVALIDATIONS), line:140
|vpiName:USE_DTAG_INVALIDATIONS
|INT:1879048191
|vpiParameter:
\_parameter: (USE_D_SCRATCH_MEM), line:79
|vpiName:USE_D_SCRATCH_MEM
|INT:3
|vpiParameter:
\_parameter: (USE_ICACHE), line:93
|vpiName:USE_ICACHE
|INT:7
|vpiParameter:
\_parameter: (USE_I_SCRATCH_MEM), line:78
|vpiName:USE_I_SCRATCH_MEM
|INT:2
|vpiParameter:
\_parameter: (USE_MUL), line:48
|vpiName:USE_MUL
|INT:1
|vpiParameter:
\_parameter: (WB_UNITS_WIDTH), line:187
|vpiName:WB_UNITS_WIDTH
|INT:32
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiGenScopeArray:
\_gen_scope_array: (genblk1), line:121, parent:register_file_block
|vpiName:genblk1
|vpiFullName:work@taiga_wrapper.cpu.register_file_block.genblk1
|vpiGenScope:
\_gen_scope: , parent:genblk1
|vpiFullName:work@taiga_wrapper.cpu.register_file_block.genblk1
|vpiContAssign:
\_cont_assign: , line:122
|vpiRhs:
\_operation: , line:122
|vpiOpType:28
|vpiOperand:
\_operation: , line:122
|vpiOpType:28
|vpiOperand:
\_operation: , line:122
|vpiOpType:28
|vpiOperand:
\_ref_obj: (instruction_issued), line:122
|vpiName:instruction_issued
|vpiFullName:work@taiga_wrapper.cpu.register_file_block.genblk1.instruction_issued
|vpiOperand:
\_ref_obj: (rs1_inuse), line:122
|vpiName:rs1_inuse
|vpiFullName:work@taiga_wrapper.cpu.register_file_block.genblk1.rs1_inuse
|vpiOperand:
\_ref_obj: (rf_decode.uses_rs1), line:122
|vpiName:rf_decode.uses_rs1
|vpiFullName:work@taiga_wrapper.cpu.register_file_block.genblk1.rf_decode.uses_rs1
|vpiOperand:
\_operation: , line:122
|vpiOpType:4
|vpiOperand:
\_ref_obj: (tr_rs1_and_rs2_forwarding_needed), line:122
|vpiName:tr_rs1_and_rs2_forwarding_needed
|vpiFullName:work@taiga_wrapper.cpu.register_file_block.genblk1.tr_rs1_and_rs2_forwarding_needed
|vpiLhs:
\_ref_obj: (tr_rs1_forwarding_needed), line:122
|vpiName:tr_rs1_forwarding_needed
|vpiFullName:work@taiga_wrapper.cpu.register_file_block.genblk1.tr_rs1_forwarding_needed
|vpiContAssign:
\_cont_assign: , line:123
|vpiRhs:
\_operation: , line:123
|vpiOpType:28
|vpiOperand:
\_operation: , line:123
|vpiOpType:28
|vpiOperand:
\_operation: , line:123
|vpiOpType:28
|vpiOperand:
\_ref_obj: (instruction_issued), line:123
|vpiName:instruction_issued
|vpiFullName:work@taiga_wrapper.cpu.register_file_block.genblk1.instruction_issued
|vpiOperand:
\_ref_obj: (rs2_inuse), line:123
|vpiName:rs2_inuse
|vpiFullName:work@taiga_wrapper.cpu.register_file_block.genblk1.rs2_inuse
|vpiOperand:
\_ref_obj: (rf_decode.uses_rs2), line:123
|vpiName:rf_decode.uses_rs2
|vpiFullName:work@taiga_wrapper.cpu.register_file_block.genblk1.rf_decode.uses_rs2
|vpiOperand:
\_operation: , line:123
|vpiOpType:4
|vpiOperand:
\_ref_obj: (tr_rs1_and_rs2_forwarding_needed), line:123
|vpiName:tr_rs1_and_rs2_forwarding_needed
|vpiFullName:work@taiga_wrapper.cpu.register_file_block.genblk1.tr_rs1_and_rs2_forwarding_needed
|vpiLhs:
\_ref_obj: (tr_rs2_forwarding_needed), line:123
|vpiName:tr_rs2_forwarding_needed
|vpiFullName:work@taiga_wrapper.cpu.register_file_block.genblk1.tr_rs2_forwarding_needed
|vpiContAssign:
\_cont_assign: , line:124
|vpiRhs:
\_operation: , line:124
|vpiOpType:28
|vpiOperand:
\_operation: , line:124
|vpiOpType:28
|vpiOperand:
\_ref_obj: (instruction_issued), line:124
|vpiName:instruction_issued
|vpiFullName:work@taiga_wrapper.cpu.register_file_block.genblk1.instruction_issued
|vpiOperand:
\_operation: , line:124
|vpiOpType:28
|vpiOperand:
\_ref_obj: (rs1_inuse), line:124
|vpiName:rs1_inuse
|vpiFullName:work@taiga_wrapper.cpu.register_file_block.genblk1.rs1_inuse
|vpiOperand:
\_ref_obj: (rf_decode.uses_rs1), line:124
|vpiName:rf_decode.uses_rs1
|vpiFullName:work@taiga_wrapper.cpu.register_file_block.genblk1.rf_decode.uses_rs1
|vpiOperand:
\_operation: , line:124
|vpiOpType:28
|vpiOperand:
\_ref_obj: (rs2_inuse), line:124
|vpiName:rs2_inuse
|vpiFullName:work@taiga_wrapper.cpu.register_file_block.genblk1.rs2_inuse
|vpiOperand:
\_ref_obj: (rf_decode.uses_rs2), line:124
|vpiName:rf_decode.uses_rs2
|vpiFullName:work@taiga_wrapper.cpu.register_file_block.genblk1.rf_decode.uses_rs2
|vpiLhs:
\_ref_obj: (tr_rs1_and_rs2_forwarding_needed), line:124
|vpiName:tr_rs1_and_rs2_forwarding_needed
|vpiFullName:work@taiga_wrapper.cpu.register_file_block.genblk1.tr_rs1_and_rs2_forwarding_needed
|vpiParameter:
\_parameter: (ALU_UNIT_WB_ID), line:190
|vpiName:ALU_UNIT_WB_ID
|INT:32
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (BRANCH_PREDICTOR_WAYS), line:159
|vpiName:BRANCH_PREDICTOR_WAYS
|INT:9
|vpiParameter:
\_parameter: (BRANCH_TABLE_ENTRIES), line:160
|vpiName:BRANCH_TABLE_ENTRIES
|INT:4
|vpiParameter:
\_parameter: (BRANCH_UNIT_ID), line:195
|vpiName:BRANCH_UNIT_ID
|INT:8
|vpiParameter:
\_parameter: (BUS_ADDR_H), line:107
|vpiName:BUS_ADDR_H
|INT:1
|vpiParameter:
\_parameter: (BUS_ADDR_L), line:106
|vpiName:BUS_ADDR_L
|INT:0
|vpiParameter:
\_parameter: (BUS_BIT_CHECK), line:108
|vpiName:BUS_BIT_CHECK
|INT:1
|vpiParameter:
\_parameter: (BUS_TYPE), line:89
|vpiName:BUS_TYPE
|INT:5
|vpiParameter:
\_parameter: (COUNTER_W), line:42
|vpiName:COUNTER_W
|INT:33
|vpiParameter:
\_parameter: (CPU_ID), line:38
|vpiName:CPU_ID
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_ADDR_WIDTH), line:113
|vpiName:C_M_AXI_ADDR_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_DATA_WIDTH), line:114
|vpiName:C_M_AXI_DATA_WIDTH
|INT:1
|vpiParameter:
\_parameter: (DCACHE_LINES), line:133
|vpiName:DCACHE_LINES
|INT:-2146435073
|vpiParameter:
\_parameter: (DCACHE_LINE_ADDR_W), line:135
|vpiName:DCACHE_LINE_ADDR_W
|INT:1073741824
|vpiParameter:
\_parameter: (DCACHE_LINE_W), line:136
|vpiName:DCACHE_LINE_W
|INT:1342177279
|vpiParameter:
\_parameter: (DCACHE_SUB_LINE_ADDR_W), line:137
|vpiName:DCACHE_SUB_LINE_ADDR_W
|INT:4
|vpiParameter:
\_parameter: (DCACHE_TAG_W), line:138
|vpiName:DCACHE_TAG_W
|INT:1610612736
|vpiParameter:
\_parameter: (DCACHE_WAYS), line:134
|vpiName:DCACHE_WAYS
|INT:4
|vpiParameter:
\_parameter: (DIV_ALGORITHM), line:67
|vpiName:DIV_ALGORITHM
|INT:0
|vpiParameter:
\_parameter: (DIV_UNIT_WB_ID), line:192
|vpiName:DIV_UNIT_WB_ID
|INT:2
|vpiParameter:
\_parameter: (DTLB_DEPTH), line:152
|vpiName:DTLB_DEPTH
|INT:512
|vpiParameter:
\_parameter: (DTLB_WAYS), line:151
|vpiName:DTLB_WAYS
|INT:32
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (ENABLE_M_MODE), line:34
|vpiName:ENABLE_M_MODE
|INT:1
|vpiParameter:
\_parameter: (ENABLE_S_MODE), line:36
|vpiName:ENABLE_S_MODE
|INT:0
|vpiParameter:
\_parameter: (ENABLE_TRACE_INTERFACE), line:172
|vpiName:ENABLE_TRACE_INTERFACE
|INT:2
|vpiParameter:
\_parameter: (FETCH_BUFFER_DEPTH), line:168
|vpiName:FETCH_BUFFER_DEPTH
|INT:512
|vpiParameter:
\_parameter: (FPGA_VENDOR), line:27
|vpiName:FPGA_VENDOR
|STRING:"xilinx"
|vpiParameter:
\_parameter: (GC_UNIT_ID), line:196
|vpiName:GC_UNIT_ID
|INT:4
|vpiParameter:
\_parameter: (ICACHE_LINES), line:121
|vpiName:ICACHE_LINES
|INT:2
|vpiParameter:
\_parameter: (ICACHE_LINE_ADDR_W), line:123
|vpiName:ICACHE_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_LINE_W), line:124
|vpiName:ICACHE_LINE_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_SUB_LINE_ADDR_W), line:125
|vpiName:ICACHE_SUB_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_TAG_W), line:126
|vpiName:ICACHE_TAG_W
|INT:-2147483648
|vpiParameter:
\_parameter: (ICACHE_WAYS), line:122
|vpiName:ICACHE_WAYS
|INT:1
|vpiParameter:
\_parameter: (ITLB_DEPTH), line:146
|vpiName:ITLB_DEPTH
|INT:32
|vpiParameter:
\_parameter: (ITLB_WAYS), line:145
|vpiName:ITLB_WAYS
|INT:4
|vpiParameter:
\_parameter: (L1_CONNECTIONS), line:177
|vpiName:L1_CONNECTIONS
|INT:9
|vpiParameter:
\_parameter: (L1_DCACHE_ID), line:178
|vpiName:L1_DCACHE_ID
|INT:4
|vpiParameter:
\_parameter: (L1_DMMU_ID), line:179
|vpiName:L1_DMMU_ID
|INT:2
|vpiParameter:
\_parameter: (L1_ICACHE_ID), line:180
|vpiName:L1_ICACHE_ID
|INT:19
|vpiParameter:
\_parameter: (L1_IMMU_ID), line:181
|vpiName:L1_IMMU_ID
|INT:0
|vpiParameter:
\_parameter: (LS_UNIT_WB_ID), line:191
|vpiName:LS_UNIT_WB_ID
|INT:1
|vpiParameter:
\_parameter: (MAX_INFLIGHT_COUNT), line:167
|vpiName:MAX_INFLIGHT_COUNT
|INT:19
|vpiParameter:
\_parameter: (MEMORY_ADDR_H), line:103
|vpiName:MEMORY_ADDR_H
|INT:12
|vpiParameter:
\_parameter: (MEMORY_ADDR_L), line:102
|vpiName:MEMORY_ADDR_L
|INT:11
|vpiParameter:
\_parameter: (MEMORY_BIT_CHECK), line:104
|vpiName:MEMORY_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (MUL_UNIT_WB_ID), line:193
|vpiName:MUL_UNIT_WB_ID
|INT:512
|vpiParameter:
\_parameter: (NUM_UNITS), line:188
|vpiName:NUM_UNITS
|INT:2
|vpiParameter:
\_parameter: (NUM_WB_UNITS), line:186
|vpiName:NUM_WB_UNITS
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (RAS_DEPTH), line:161
|vpiName:RAS_DEPTH
|INT:2
|vpiParameter:
\_parameter: (RESET_VEC), line:39
|vpiName:RESET_VEC
|INT:-2147483648
|vpiParameter:
\_parameter: (SCRATCH_ADDR_H), line:99
|vpiName:SCRATCH_ADDR_H
|INT:9
|vpiParameter:
\_parameter: (SCRATCH_ADDR_L), line:98
|vpiName:SCRATCH_ADDR_L
|INT:8
|vpiParameter:
\_parameter: (SCRATCH_BIT_CHECK), line:100
|vpiName:SCRATCH_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (USE_AMO), line:70
|vpiName:USE_AMO
|INT:1
|vpiParameter:
\_parameter: (USE_BRANCH_PREDICTOR), line:158
|vpiName:USE_BRANCH_PREDICTOR
|INT:2
|vpiParameter:
\_parameter: (USE_BUS), line:88
|vpiName:USE_BUS
|INT:4
|vpiParameter:
\_parameter: (USE_DCACHE), line:92
|vpiName:USE_DCACHE
|INT:6
|vpiParameter:
\_parameter: (USE_DIV), line:49
|vpiName:USE_DIV
|INT:1
|vpiParameter:
\_parameter: (USE_DTAG_INVALIDATIONS), line:140
|vpiName:USE_DTAG_INVALIDATIONS
|INT:1879048191
|vpiParameter:
\_parameter: (USE_D_SCRATCH_MEM), line:79
|vpiName:USE_D_SCRATCH_MEM
|INT:3
|vpiParameter:
\_parameter: (USE_ICACHE), line:93
|vpiName:USE_ICACHE
|INT:7
|vpiParameter:
\_parameter: (USE_I_SCRATCH_MEM), line:78
|vpiName:USE_I_SCRATCH_MEM
|INT:2
|vpiParameter:
\_parameter: (USE_MUL), line:48
|vpiName:USE_MUL
|INT:1
|vpiParameter:
\_parameter: (WB_UNITS_WIDTH), line:187
|vpiName:WB_UNITS_WIDTH
|INT:32
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiNet:
\_logic_net: (clk), line:27, parent:register_file_block
|vpiNet:
\_logic_net: (rst), line:28, parent:register_file_block
|vpiNet:
\_logic_net: (gc_supress_writeback), line:29, parent:register_file_block
|vpiNet:
\_logic_net: (instruction_issued), line:31, parent:register_file_block
|vpiName:instruction_issued
|vpiFullName:work@taiga_wrapper.cpu.register_file_block.instruction_issued
|vpiNetType:36
|vpiNet:
\_logic_net: (tr_rs1_forwarding_needed), line:36, parent:register_file_block
|vpiNet:
\_logic_net: (tr_rs2_forwarding_needed), line:37, parent:register_file_block
|vpiNet:
\_logic_net: (tr_rs1_and_rs2_forwarding_needed), line:38, parent:register_file_block
|vpiNet:
\_logic_net: (rs1_inuse), line:44, parent:register_file_block
|vpiNet:
\_logic_net: (rs2_inuse), line:45, parent:register_file_block
|vpiNet:
\_logic_net: (rs1_feedforward), line:47, parent:register_file_block
|vpiName:rs1_feedforward
|vpiFullName:work@taiga_wrapper.cpu.register_file_block.rs1_feedforward
|vpiNetType:36
|vpiNet:
\_logic_net: (rs2_feedforward), line:48, parent:register_file_block
|vpiName:rs2_feedforward
|vpiFullName:work@taiga_wrapper.cpu.register_file_block.rs2_feedforward
|vpiNetType:36
|vpiNet:
\_logic_net: (valid_write), line:50, parent:register_file_block
|vpiName:valid_write
|vpiFullName:work@taiga_wrapper.cpu.register_file_block.valid_write
|vpiNetType:36
|vpiNet:
\_logic_net: (in_use_match), line:51, parent:register_file_block
|vpiName:in_use_match
|vpiFullName:work@taiga_wrapper.cpu.register_file_block.in_use_match
|vpiNetType:36
|vpiNet:
\_logic_net: (sim_registers_unamed), line:110, parent:register_file_block
|vpiName:sim_registers_unamed
|vpiFullName:work@taiga_wrapper.cpu.register_file_block.sim_registers_unamed
|vpiNetType:36
|vpiRange:
\_range: , line:110
|vpiLeftRange:
\_constant: , line:110
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:110
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiRange:
\_range: , line:110
|vpiLeftRange:
\_constant: , line:110
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:110
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (rf_wb), line:32, parent:register_file_block
|vpiName:rf_wb
|vpiFullName:work@taiga_wrapper.cpu.register_file_block.rf_wb
|vpiNet:
\_logic_net: (rf_decode), line:33, parent:register_file_block
|vpiName:rf_decode
|vpiFullName:work@taiga_wrapper.cpu.register_file_block.rf_decode
|vpiInstance:
\_module: work@taiga (cpu), file:third_party/cores/taiga/examples/zedboard/taiga_wrapper.sv, line:233, parent:work@taiga_wrapper
|vpiArrayNet:
\_array_net: (register), line:41, parent:register_file_block
|vpiName:register
|vpiFullName:work@taiga_wrapper.cpu.register_file_block.register
|vpiSize:32
|vpiNet:
\_logic_net: , parent:register
|vpiFullName:work@taiga_wrapper.cpu.register_file_block.register
|vpiNetType:36
|vpiRange:
\_range: , line:41
|vpiLeftRange:
\_constant: , line:41
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiRightRange:
\_constant: , line:41
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiRange:
\_range: , line:41
|vpiLeftRange:
\_constant: , line:41
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:41
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiVariables:
\_array_var: (in_use_by), parent:register_file_block
|vpiArrayType:1
|vpiName:in_use_by
|vpiFullName:work@taiga_wrapper.cpu.register_file_block.in_use_by
|vpiRandType:1
|vpiVisibility:1
|vpiSize:32
|vpiReg:
\_logic_var: (in_use_by), line:42, parent:in_use_by
|vpiName:in_use_by
|vpiFullName:work@taiga_wrapper.cpu.register_file_block.in_use_by.in_use_by
|vpiRange:
\_range: , line:42
|vpiLeftRange:
\_constant: , line:42
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:42
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiVariables:
\_struct_var: (sim_register), line:111, parent:register_file_block
|vpiName:sim_register
|vpiFullName:work@taiga_wrapper.cpu.register_file_block.sim_register
|vpiTypespec:
\_struct_typespec: (simulation_named_regfile), line:476
|vpiParameter:
\_parameter: (ALU_UNIT_WB_ID), line:190
|vpiName:ALU_UNIT_WB_ID
|INT:32
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (BRANCH_PREDICTOR_WAYS), line:159
|vpiName:BRANCH_PREDICTOR_WAYS
|INT:9
|vpiParameter:
\_parameter: (BRANCH_TABLE_ENTRIES), line:160
|vpiName:BRANCH_TABLE_ENTRIES
|INT:4
|vpiParameter:
\_parameter: (BRANCH_UNIT_ID), line:195
|vpiName:BRANCH_UNIT_ID
|INT:8
|vpiParameter:
\_parameter: (BUS_ADDR_H), line:107
|vpiName:BUS_ADDR_H
|INT:1
|vpiParameter:
\_parameter: (BUS_ADDR_L), line:106
|vpiName:BUS_ADDR_L
|INT:0
|vpiParameter:
\_parameter: (BUS_BIT_CHECK), line:108
|vpiName:BUS_BIT_CHECK
|INT:1
|vpiParameter:
\_parameter: (BUS_TYPE), line:89
|vpiName:BUS_TYPE
|INT:5
|vpiParameter:
\_parameter: (COUNTER_W), line:42
|vpiName:COUNTER_W
|INT:33
|vpiParameter:
\_parameter: (CPU_ID), line:38
|vpiName:CPU_ID
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_ADDR_WIDTH), line:113
|vpiName:C_M_AXI_ADDR_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_DATA_WIDTH), line:114
|vpiName:C_M_AXI_DATA_WIDTH
|INT:1
|vpiParameter:
\_parameter: (DCACHE_LINES), line:133
|vpiName:DCACHE_LINES
|INT:-2146435073
|vpiParameter:
\_parameter: (DCACHE_LINE_ADDR_W), line:135
|vpiName:DCACHE_LINE_ADDR_W
|INT:1073741824
|vpiParameter:
\_parameter: (DCACHE_LINE_W), line:136
|vpiName:DCACHE_LINE_W
|INT:1342177279
|vpiParameter:
\_parameter: (DCACHE_SUB_LINE_ADDR_W), line:137
|vpiName:DCACHE_SUB_LINE_ADDR_W
|INT:4
|vpiParameter:
\_parameter: (DCACHE_TAG_W), line:138
|vpiName:DCACHE_TAG_W
|INT:1610612736
|vpiParameter:
\_parameter: (DCACHE_WAYS), line:134
|vpiName:DCACHE_WAYS
|INT:4
|vpiParameter:
\_parameter: (DIV_ALGORITHM), line:67
|vpiName:DIV_ALGORITHM
|INT:0
|vpiParameter:
\_parameter: (DIV_UNIT_WB_ID), line:192
|vpiName:DIV_UNIT_WB_ID
|INT:2
|vpiParameter:
\_parameter: (DTLB_DEPTH), line:152
|vpiName:DTLB_DEPTH
|INT:512
|vpiParameter:
\_parameter: (DTLB_WAYS), line:151
|vpiName:DTLB_WAYS
|INT:32
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (ENABLE_M_MODE), line:34
|vpiName:ENABLE_M_MODE
|INT:1
|vpiParameter:
\_parameter: (ENABLE_S_MODE), line:36
|vpiName:ENABLE_S_MODE
|INT:0
|vpiParameter:
\_parameter: (ENABLE_TRACE_INTERFACE), line:172
|vpiName:ENABLE_TRACE_INTERFACE
|INT:2
|vpiParameter:
\_parameter: (FETCH_BUFFER_DEPTH), line:168
|vpiName:FETCH_BUFFER_DEPTH
|INT:512
|vpiParameter:
\_parameter: (FPGA_VENDOR), line:27
|vpiName:FPGA_VENDOR
|STRING:"xilinx"
|vpiParameter:
\_parameter: (GC_UNIT_ID), line:196
|vpiName:GC_UNIT_ID
|INT:4
|vpiParameter:
\_parameter: (ICACHE_LINES), line:121
|vpiName:ICACHE_LINES
|INT:2
|vpiParameter:
\_parameter: (ICACHE_LINE_ADDR_W), line:123
|vpiName:ICACHE_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_LINE_W), line:124
|vpiName:ICACHE_LINE_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_SUB_LINE_ADDR_W), line:125
|vpiName:ICACHE_SUB_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_TAG_W), line:126
|vpiName:ICACHE_TAG_W
|INT:-2147483648
|vpiParameter:
\_parameter: (ICACHE_WAYS), line:122
|vpiName:ICACHE_WAYS
|INT:1
|vpiParameter:
\_parameter: (ITLB_DEPTH), line:146
|vpiName:ITLB_DEPTH
|INT:32
|vpiParameter:
\_parameter: (ITLB_WAYS), line:145
|vpiName:ITLB_WAYS
|INT:4
|vpiParameter:
\_parameter: (L1_CONNECTIONS), line:177
|vpiName:L1_CONNECTIONS
|INT:9
|vpiParameter:
\_parameter: (L1_DCACHE_ID), line:178
|vpiName:L1_DCACHE_ID
|INT:4
|vpiParameter:
\_parameter: (L1_DMMU_ID), line:179
|vpiName:L1_DMMU_ID
|INT:2
|vpiParameter:
\_parameter: (L1_ICACHE_ID), line:180
|vpiName:L1_ICACHE_ID
|INT:19
|vpiParameter:
\_parameter: (L1_IMMU_ID), line:181
|vpiName:L1_IMMU_ID
|INT:0
|vpiParameter:
\_parameter: (LS_UNIT_WB_ID), line:191
|vpiName:LS_UNIT_WB_ID
|INT:1
|vpiParameter:
\_parameter: (MAX_INFLIGHT_COUNT), line:167
|vpiName:MAX_INFLIGHT_COUNT
|INT:19
|vpiParameter:
\_parameter: (MEMORY_ADDR_H), line:103
|vpiName:MEMORY_ADDR_H
|INT:12
|vpiParameter:
\_parameter: (MEMORY_ADDR_L), line:102
|vpiName:MEMORY_ADDR_L
|INT:11
|vpiParameter:
\_parameter: (MEMORY_BIT_CHECK), line:104
|vpiName:MEMORY_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (MUL_UNIT_WB_ID), line:193
|vpiName:MUL_UNIT_WB_ID
|INT:512
|vpiParameter:
\_parameter: (NUM_UNITS), line:188
|vpiName:NUM_UNITS
|INT:2
|vpiParameter:
\_parameter: (NUM_WB_UNITS), line:186
|vpiName:NUM_WB_UNITS
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (RAS_DEPTH), line:161
|vpiName:RAS_DEPTH
|INT:2
|vpiParameter:
\_parameter: (RESET_VEC), line:39
|vpiName:RESET_VEC
|INT:-2147483648
|vpiParameter:
\_parameter: (SCRATCH_ADDR_H), line:99
|vpiName:SCRATCH_ADDR_H
|INT:9
|vpiParameter:
\_parameter: (SCRATCH_ADDR_L), line:98
|vpiName:SCRATCH_ADDR_L
|INT:8
|vpiParameter:
\_parameter: (SCRATCH_BIT_CHECK), line:100
|vpiName:SCRATCH_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (USE_AMO), line:70
|vpiName:USE_AMO
|INT:1
|vpiParameter:
\_parameter: (USE_BRANCH_PREDICTOR), line:158
|vpiName:USE_BRANCH_PREDICTOR
|INT:2
|vpiParameter:
\_parameter: (USE_BUS), line:88
|vpiName:USE_BUS
|INT:4
|vpiParameter:
\_parameter: (USE_DCACHE), line:92
|vpiName:USE_DCACHE
|INT:6
|vpiParameter:
\_parameter: (USE_DIV), line:49
|vpiName:USE_DIV
|INT:1
|vpiParameter:
\_parameter: (USE_DTAG_INVALIDATIONS), line:140
|vpiName:USE_DTAG_INVALIDATIONS
|INT:1879048191
|vpiParameter:
\_parameter: (USE_D_SCRATCH_MEM), line:79
|vpiName:USE_D_SCRATCH_MEM
|INT:3
|vpiParameter:
\_parameter: (USE_ICACHE), line:93
|vpiName:USE_ICACHE
|INT:7
|vpiParameter:
\_parameter: (USE_I_SCRATCH_MEM), line:78
|vpiName:USE_I_SCRATCH_MEM
|INT:2
|vpiParameter:
\_parameter: (USE_MUL), line:48
|vpiName:USE_MUL
|INT:1
|vpiParameter:
\_parameter: (WB_UNITS_WIDTH), line:187
|vpiName:WB_UNITS_WIDTH
|INT:32
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiModule:
\_module: work@branch_unit (branch_unit_block), file:third_party/cores/taiga/core/taiga.sv, line:181, parent:cpu
|vpiDefName:work@branch_unit
|vpiName:branch_unit_block
|vpiFullName:work@taiga_wrapper.cpu.branch_unit_block
|vpiPort:
\_port: (clk), line:27, parent:branch_unit_block
|vpiName:clk
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (clk), line:181
|vpiName:clk
|vpiActual:
\_logic_net: (clk), line:27, parent:cpu
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (clk), line:27, parent:branch_unit_block
|vpiName:clk
|vpiFullName:work@taiga_wrapper.cpu.branch_unit_block.clk
|vpiNetType:36
|vpiPort:
\_port: (rst), line:28, parent:branch_unit_block
|vpiName:rst
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (rst), line:181
|vpiName:rst
|vpiActual:
\_logic_net: (rst), line:28, parent:cpu
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (rst), line:28, parent:branch_unit_block
|vpiName:rst
|vpiFullName:work@taiga_wrapper.cpu.branch_unit_block.rst
|vpiNetType:36
|vpiPort:
\_port: (issue), line:30, parent:branch_unit_block
|vpiName:issue
|vpiDirection:5
|vpiHighConn:
\_ref_obj: (issue), line:181
|vpiName:issue
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_modport: (unit)
|vpiName:unit
|vpiIODecl:
\_io_decl: (ready)
|vpiName:ready
|vpiDirection:2
|vpiExpr:
\_logic_net: (ready), line:58
|vpiName:ready
|vpiNetType:36
|vpiIODecl:
\_io_decl: (possible_issue)
|vpiName:possible_issue
|vpiDirection:1
|vpiExpr:
\_logic_net: (possible_issue), line:53
|vpiName:possible_issue
|vpiNetType:36
|vpiIODecl:
\_io_decl: (new_request)
|vpiName:new_request
|vpiDirection:1
|vpiExpr:
\_logic_net: (new_request), line:54
|vpiName:new_request
|vpiNetType:36
|vpiIODecl:
\_io_decl: (new_request_r)
|vpiName:new_request_r
|vpiDirection:1
|vpiExpr:
\_logic_net: (new_request_r), line:55
|vpiName:new_request_r
|vpiNetType:36
|vpiIODecl:
\_io_decl: (instruction_id)
|vpiName:instruction_id
|vpiDirection:1
|vpiInterface:
\_interface: work@unit_issue_interface (issue), file:third_party/cores/taiga/core/taiga.sv, line:181
|vpiDefName:work@unit_issue_interface
|vpiName:issue
|vpiModport:
\_modport: (decode)
|vpiName:decode
|vpiIODecl:
\_io_decl: (ready)
|vpiName:ready
|vpiDirection:1
|vpiExpr:
\_logic_net: (ready), line:58
|vpiIODecl:
\_io_decl: (possible_issue)
|vpiName:possible_issue
|vpiDirection:2
|vpiExpr:
\_logic_net: (possible_issue), line:53
|vpiIODecl:
\_io_decl: (new_request)
|vpiName:new_request
|vpiDirection:2
|vpiExpr:
\_logic_net: (new_request), line:54
|vpiIODecl:
\_io_decl: (new_request_r)
|vpiName:new_request_r
|vpiDirection:2
|vpiExpr:
\_logic_net: (new_request_r), line:55
|vpiIODecl:
\_io_decl: (instruction_id)
|vpiName:instruction_id
|vpiDirection:2
|vpiInterface:
\_interface: work@unit_issue_interface (issue), file:third_party/cores/taiga/core/taiga.sv, line:181
|vpiModport:
\_modport: (unit)
|vpiPort:
\_port: (branch_inputs), line:31, parent:branch_unit_block
|vpiName:branch_inputs
|vpiDirection:1
|vpiTypedef:
\_struct_typespec: (branch_inputs_t), line:313
|vpiHighConn:
\_ref_obj: (branch_inputs), line:181
|vpiName:branch_inputs
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (branch_inputs), line:31, parent:branch_unit_block
|vpiName:branch_inputs
|vpiFullName:work@taiga_wrapper.cpu.branch_unit_block.branch_inputs
|vpiPort:
\_port: (br_results), line:32, parent:branch_unit_block
|vpiName:br_results
|vpiDirection:2
|vpiTypedef:
\_struct_typespec: (branch_results_t), line:330
|vpiHighConn:
\_ref_obj: (br_results), line:181
|vpiName:br_results
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (br_results), line:32, parent:branch_unit_block
|vpiName:br_results
|vpiFullName:work@taiga_wrapper.cpu.branch_unit_block.br_results
|vpiPort:
\_port: (ras), line:33, parent:branch_unit_block
|vpiName:ras
|vpiDirection:5
|vpiHighConn:
\_ref_obj: (ras), line:181
|vpiName:ras
|vpiActual:
\_interface: work@ras_interface (ras), file:third_party/cores/taiga/core/taiga.sv, line:54
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_modport: (branch_unit)
|vpiName:branch_unit
|vpiIODecl:
\_io_decl: (push)
|vpiName:push
|vpiDirection:2
|vpiExpr:
\_logic_net: (push), line:65
|vpiName:push
|vpiNetType:36
|vpiIODecl:
\_io_decl: (pop)
|vpiName:pop
|vpiDirection:2
|vpiExpr:
\_logic_net: (pop), line:66
|vpiName:pop
|vpiNetType:36
|vpiIODecl:
\_io_decl: (new_addr)
|vpiName:new_addr
|vpiDirection:2
|vpiExpr:
\_logic_net: (new_addr), line:67
|vpiName:new_addr
|vpiNetType:36
|vpiRange:
\_range: , line:67
|vpiLeftRange:
\_constant: , line:67
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:67
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiInterface:
\_interface: work@ras_interface (ras), file:third_party/cores/taiga/core/taiga.sv, line:181
|vpiDefName:work@ras_interface
|vpiName:ras
|vpiModport:
\_modport: (branch_unit)
|vpiModport:
\_modport: (fetch)
|vpiName:fetch
|vpiIODecl:
\_io_decl: (addr)
|vpiName:addr
|vpiDirection:1
|vpiExpr:
\_logic_net: (addr), line:68
|vpiName:addr
|vpiNetType:36
|vpiRange:
\_range: , line:68
|vpiLeftRange:
\_constant: , line:68
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:68
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (valid)
|vpiName:valid
|vpiDirection:1
|vpiExpr:
\_logic_net: (valid), line:69
|vpiName:valid
|vpiNetType:36
|vpiInterface:
\_interface: work@ras_interface (ras), file:third_party/cores/taiga/core/taiga.sv, line:181
|vpiModport:
\_modport: (self)
|vpiName:self
|vpiIODecl:
\_io_decl: (push)
|vpiName:push
|vpiDirection:1
|vpiExpr:
\_logic_net: (push), line:65
|vpiIODecl:
\_io_decl: (pop)
|vpiName:pop
|vpiDirection:1
|vpiExpr:
\_logic_net: (pop), line:66
|vpiIODecl:
\_io_decl: (new_addr)
|vpiName:new_addr
|vpiDirection:1
|vpiExpr:
\_logic_net: (new_addr), line:67
|vpiIODecl:
\_io_decl: (addr)
|vpiName:addr
|vpiDirection:2
|vpiExpr:
\_logic_net: (addr), line:68
|vpiIODecl:
\_io_decl: (valid)
|vpiName:valid
|vpiDirection:2
|vpiExpr:
\_logic_net: (valid), line:69
|vpiInterface:
\_interface: work@ras_interface (ras), file:third_party/cores/taiga/core/taiga.sv, line:181
|vpiPort:
\_port: (branch_flush), line:34, parent:branch_unit_block
|vpiName:branch_flush
|vpiDirection:2
|vpiHighConn:
\_ref_obj: (branch_flush), line:181
|vpiName:branch_flush
|vpiActual:
\_logic_net: (branch_flush), line:52, parent:cpu
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (branch_flush), line:34, parent:branch_unit_block
|vpiName:branch_flush
|vpiFullName:work@taiga_wrapper.cpu.branch_unit_block.branch_flush
|vpiPort:
\_port: (tr_branch_correct), line:37, parent:branch_unit_block
|vpiName:tr_branch_correct
|vpiDirection:2
|vpiHighConn:
\_ref_obj: (tr_branch_correct), line:181
|vpiName:tr_branch_correct
|vpiActual:
\_logic_net: (tr_branch_correct), line:140, parent:cpu
|vpiName:tr_branch_correct
|vpiFullName:work@taiga_wrapper.cpu.tr_branch_correct
|vpiNetType:36
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (tr_branch_correct), line:37, parent:branch_unit_block
|vpiName:tr_branch_correct
|vpiFullName:work@taiga_wrapper.cpu.branch_unit_block.tr_branch_correct
|vpiNetType:36
|vpiPort:
\_port: (tr_branch_misspredict), line:38, parent:branch_unit_block
|vpiName:tr_branch_misspredict
|vpiDirection:2
|vpiHighConn:
\_ref_obj: (tr_branch_misspredict), line:181
|vpiName:tr_branch_misspredict
|vpiActual:
\_logic_net: (tr_branch_misspredict), line:141, parent:cpu
|vpiName:tr_branch_misspredict
|vpiFullName:work@taiga_wrapper.cpu.tr_branch_misspredict
|vpiNetType:36
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (tr_branch_misspredict), line:38, parent:branch_unit_block
|vpiName:tr_branch_misspredict
|vpiFullName:work@taiga_wrapper.cpu.branch_unit_block.tr_branch_misspredict
|vpiNetType:36
|vpiPort:
\_port: (tr_return_misspredict), line:39, parent:branch_unit_block
|vpiName:tr_return_misspredict
|vpiDirection:2
|vpiHighConn:
\_ref_obj: (tr_return_misspredict), line:181
|vpiName:tr_return_misspredict
|vpiActual:
\_logic_net: (tr_return_misspredict), line:142, parent:cpu
|vpiName:tr_return_misspredict
|vpiFullName:work@taiga_wrapper.cpu.tr_return_misspredict
|vpiNetType:36
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (tr_return_misspredict), line:39, parent:branch_unit_block
|vpiName:tr_return_misspredict
|vpiFullName:work@taiga_wrapper.cpu.branch_unit_block.tr_return_misspredict
|vpiNetType:36
|vpiModule:
\_module: work@branch_comparator (bc), file:third_party/cores/taiga/core/branch_unit.sv, line:96, parent:branch_unit_block
|vpiDefName:work@branch_comparator
|vpiName:bc
|vpiFullName:work@taiga_wrapper.cpu.branch_unit_block.bc
|vpiPort:
\_port: (use_signed), line:27, parent:bc
|vpiName:use_signed
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (branch_inputs.use_signed), line:97
|vpiName:branch_inputs.use_signed
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (use_signed), line:27, parent:bc
|vpiName:use_signed
|vpiFullName:work@taiga_wrapper.cpu.branch_unit_block.bc.use_signed
|vpiNetType:36
|vpiPort:
\_port: (less_than), line:28, parent:bc
|vpiName:less_than
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (branch_inputs.fn3), line:98
|vpiName:branch_inputs.fn3
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (less_than), line:28, parent:bc
|vpiName:less_than
|vpiFullName:work@taiga_wrapper.cpu.branch_unit_block.bc.less_than
|vpiNetType:36
|vpiPort:
\_port: (a), line:29, parent:bc
|vpiName:a
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (branch_inputs.rs1), line:99
|vpiName:branch_inputs.rs1
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (a), line:29, parent:bc
|vpiName:a
|vpiFullName:work@taiga_wrapper.cpu.branch_unit_block.bc.a
|vpiNetType:36
|vpiRange:
\_range: , line:29
|vpiLeftRange:
\_constant: , line:29
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:29
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiPort:
\_port: (b), line:30, parent:bc
|vpiName:b
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (branch_inputs.rs2), line:100
|vpiName:branch_inputs.rs2
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (b), line:30, parent:bc
|vpiName:b
|vpiFullName:work@taiga_wrapper.cpu.branch_unit_block.bc.b
|vpiNetType:36
|vpiRange:
\_range: , line:30
|vpiLeftRange:
\_constant: , line:30
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:30
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiPort:
\_port: (result), line:31, parent:bc
|vpiName:result
|vpiDirection:2
|vpiHighConn:
\_ref_obj: (result), line:101
|vpiName:result
|vpiActual:
\_logic_net: (result), line:52, parent:branch_unit_block
|vpiName:result
|vpiFullName:work@taiga_wrapper.cpu.branch_unit_block.result
|vpiNetType:36
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (result), line:31, parent:bc
|vpiName:result
|vpiFullName:work@taiga_wrapper.cpu.branch_unit_block.bc.result
|vpiNetType:36
|vpiNet:
\_logic_net: (use_signed), line:27, parent:bc
|vpiNet:
\_logic_net: (less_than), line:28, parent:bc
|vpiNet:
\_logic_net: (a), line:29, parent:bc
|vpiNet:
\_logic_net: (b), line:30, parent:bc
|vpiNet:
\_logic_net: (result), line:31, parent:bc
|vpiNet:
\_logic_net: (sign_extended_a), line:34, parent:bc
|vpiName:sign_extended_a
|vpiFullName:work@taiga_wrapper.cpu.branch_unit_block.bc.sign_extended_a
|vpiNetType:36
|vpiRange:
\_range: , line:34
|vpiLeftRange:
\_constant: , line:34
|vpiConstType:7
|vpiDecompile:32
|vpiSize:32
|INT:32
|vpiRightRange:
\_constant: , line:34
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (sign_extended_b), line:35, parent:bc
|vpiName:sign_extended_b
|vpiFullName:work@taiga_wrapper.cpu.branch_unit_block.bc.sign_extended_b
|vpiNetType:36
|vpiRange:
\_range: , line:35
|vpiLeftRange:
\_constant: , line:35
|vpiConstType:7
|vpiDecompile:32
|vpiSize:32
|INT:32
|vpiRightRange:
\_constant: , line:35
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (eq_a), line:37, parent:bc
|vpiName:eq_a
|vpiFullName:work@taiga_wrapper.cpu.branch_unit_block.bc.eq_a
|vpiNetType:36
|vpiRange:
\_range: , line:37
|vpiLeftRange:
\_constant: , line:37
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:37
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (eq_b), line:38, parent:bc
|vpiName:eq_b
|vpiFullName:work@taiga_wrapper.cpu.branch_unit_block.bc.eq_b
|vpiNetType:36
|vpiRange:
\_range: , line:38
|vpiLeftRange:
\_constant: , line:38
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:38
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (ls_a), line:39, parent:bc
|vpiName:ls_a
|vpiFullName:work@taiga_wrapper.cpu.branch_unit_block.bc.ls_a
|vpiNetType:36
|vpiRange:
\_range: , line:39
|vpiLeftRange:
\_constant: , line:39
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:39
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (ls_b), line:40, parent:bc
|vpiName:ls_b
|vpiFullName:work@taiga_wrapper.cpu.branch_unit_block.bc.ls_b
|vpiNetType:36
|vpiRange:
\_range: , line:40
|vpiLeftRange:
\_constant: , line:40
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:40
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (sub_ls_a), line:42, parent:bc
|vpiName:sub_ls_a
|vpiFullName:work@taiga_wrapper.cpu.branch_unit_block.bc.sub_ls_a
|vpiNetType:36
|vpiRange:
\_range: , line:42
|vpiLeftRange:
\_constant: , line:42
|vpiConstType:7
|vpiDecompile:15
|vpiSize:32
|INT:15
|vpiRightRange:
\_constant: , line:42
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (sub_ls_b), line:43, parent:bc
|vpiName:sub_ls_b
|vpiFullName:work@taiga_wrapper.cpu.branch_unit_block.bc.sub_ls_b
|vpiNetType:36
|vpiRange:
\_range: , line:43
|vpiLeftRange:
\_constant: , line:43
|vpiConstType:7
|vpiDecompile:15
|vpiSize:32
|INT:15
|vpiRightRange:
\_constant: , line:43
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (sub_eq_a), line:44, parent:bc
|vpiName:sub_eq_a
|vpiFullName:work@taiga_wrapper.cpu.branch_unit_block.bc.sub_eq_a
|vpiNetType:36
|vpiRange:
\_range: , line:44
|vpiLeftRange:
\_constant: , line:44
|vpiConstType:7
|vpiDecompile:15
|vpiSize:32
|INT:15
|vpiRightRange:
\_constant: , line:44
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (sub_toss), line:46, parent:bc
|vpiName:sub_toss
|vpiFullName:work@taiga_wrapper.cpu.branch_unit_block.bc.sub_toss
|vpiNetType:36
|vpiRange:
\_range: , line:46
|vpiLeftRange:
\_constant: , line:46
|vpiConstType:7
|vpiDecompile:15
|vpiSize:32
|INT:15
|vpiRightRange:
\_constant: , line:46
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (eq_carry_in), line:48, parent:bc
|vpiName:eq_carry_in
|vpiFullName:work@taiga_wrapper.cpu.branch_unit_block.bc.eq_carry_in
|vpiNetType:36
|vpiNet:
\_logic_net: (ls_carry_in), line:49, parent:bc
|vpiName:ls_carry_in
|vpiFullName:work@taiga_wrapper.cpu.branch_unit_block.bc.ls_carry_in
|vpiNetType:36
|vpiNet:
\_logic_net: (carry_in), line:50, parent:bc
|vpiName:carry_in
|vpiFullName:work@taiga_wrapper.cpu.branch_unit_block.bc.carry_in
|vpiNetType:36
|vpiInstance:
\_module: work@branch_unit (branch_unit_block), file:third_party/cores/taiga/core/taiga.sv, line:181, parent:cpu
|vpiParameter:
\_parameter: (ALU_UNIT_WB_ID), line:190
|vpiName:ALU_UNIT_WB_ID
|INT:32
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (BRANCH_PREDICTOR_WAYS), line:159
|vpiName:BRANCH_PREDICTOR_WAYS
|INT:9
|vpiParameter:
\_parameter: (BRANCH_TABLE_ENTRIES), line:160
|vpiName:BRANCH_TABLE_ENTRIES
|INT:4
|vpiParameter:
\_parameter: (BRANCH_UNIT_ID), line:195
|vpiName:BRANCH_UNIT_ID
|INT:8
|vpiParameter:
\_parameter: (BUS_ADDR_H), line:107
|vpiName:BUS_ADDR_H
|INT:1
|vpiParameter:
\_parameter: (BUS_ADDR_L), line:106
|vpiName:BUS_ADDR_L
|INT:0
|vpiParameter:
\_parameter: (BUS_BIT_CHECK), line:108
|vpiName:BUS_BIT_CHECK
|INT:1
|vpiParameter:
\_parameter: (BUS_TYPE), line:89
|vpiName:BUS_TYPE
|INT:5
|vpiParameter:
\_parameter: (COUNTER_W), line:42
|vpiName:COUNTER_W
|INT:33
|vpiParameter:
\_parameter: (CPU_ID), line:38
|vpiName:CPU_ID
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_ADDR_WIDTH), line:113
|vpiName:C_M_AXI_ADDR_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_DATA_WIDTH), line:114
|vpiName:C_M_AXI_DATA_WIDTH
|INT:1
|vpiParameter:
\_parameter: (DCACHE_LINES), line:133
|vpiName:DCACHE_LINES
|INT:-2146435073
|vpiParameter:
\_parameter: (DCACHE_LINE_ADDR_W), line:135
|vpiName:DCACHE_LINE_ADDR_W
|INT:1073741824
|vpiParameter:
\_parameter: (DCACHE_LINE_W), line:136
|vpiName:DCACHE_LINE_W
|INT:1342177279
|vpiParameter:
\_parameter: (DCACHE_SUB_LINE_ADDR_W), line:137
|vpiName:DCACHE_SUB_LINE_ADDR_W
|INT:4
|vpiParameter:
\_parameter: (DCACHE_TAG_W), line:138
|vpiName:DCACHE_TAG_W
|INT:1610612736
|vpiParameter:
\_parameter: (DCACHE_WAYS), line:134
|vpiName:DCACHE_WAYS
|INT:4
|vpiParameter:
\_parameter: (DIV_ALGORITHM), line:67
|vpiName:DIV_ALGORITHM
|INT:0
|vpiParameter:
\_parameter: (DIV_UNIT_WB_ID), line:192
|vpiName:DIV_UNIT_WB_ID
|INT:2
|vpiParameter:
\_parameter: (DTLB_DEPTH), line:152
|vpiName:DTLB_DEPTH
|INT:512
|vpiParameter:
\_parameter: (DTLB_WAYS), line:151
|vpiName:DTLB_WAYS
|INT:32
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (ENABLE_M_MODE), line:34
|vpiName:ENABLE_M_MODE
|INT:1
|vpiParameter:
\_parameter: (ENABLE_S_MODE), line:36
|vpiName:ENABLE_S_MODE
|INT:0
|vpiParameter:
\_parameter: (ENABLE_TRACE_INTERFACE), line:172
|vpiName:ENABLE_TRACE_INTERFACE
|INT:2
|vpiParameter:
\_parameter: (FETCH_BUFFER_DEPTH), line:168
|vpiName:FETCH_BUFFER_DEPTH
|INT:512
|vpiParameter:
\_parameter: (FPGA_VENDOR), line:27
|vpiName:FPGA_VENDOR
|STRING:"xilinx"
|vpiParameter:
\_parameter: (GC_UNIT_ID), line:196
|vpiName:GC_UNIT_ID
|INT:4
|vpiParameter:
\_parameter: (ICACHE_LINES), line:121
|vpiName:ICACHE_LINES
|INT:2
|vpiParameter:
\_parameter: (ICACHE_LINE_ADDR_W), line:123
|vpiName:ICACHE_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_LINE_W), line:124
|vpiName:ICACHE_LINE_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_SUB_LINE_ADDR_W), line:125
|vpiName:ICACHE_SUB_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_TAG_W), line:126
|vpiName:ICACHE_TAG_W
|INT:-2147483648
|vpiParameter:
\_parameter: (ICACHE_WAYS), line:122
|vpiName:ICACHE_WAYS
|INT:1
|vpiParameter:
\_parameter: (ITLB_DEPTH), line:146
|vpiName:ITLB_DEPTH
|INT:32
|vpiParameter:
\_parameter: (ITLB_WAYS), line:145
|vpiName:ITLB_WAYS
|INT:4
|vpiParameter:
\_parameter: (L1_CONNECTIONS), line:177
|vpiName:L1_CONNECTIONS
|INT:9
|vpiParameter:
\_parameter: (L1_DCACHE_ID), line:178
|vpiName:L1_DCACHE_ID
|INT:4
|vpiParameter:
\_parameter: (L1_DMMU_ID), line:179
|vpiName:L1_DMMU_ID
|INT:2
|vpiParameter:
\_parameter: (L1_ICACHE_ID), line:180
|vpiName:L1_ICACHE_ID
|INT:19
|vpiParameter:
\_parameter: (L1_IMMU_ID), line:181
|vpiName:L1_IMMU_ID
|INT:0
|vpiParameter:
\_parameter: (LS_UNIT_WB_ID), line:191
|vpiName:LS_UNIT_WB_ID
|INT:1
|vpiParameter:
\_parameter: (MAX_INFLIGHT_COUNT), line:167
|vpiName:MAX_INFLIGHT_COUNT
|INT:19
|vpiParameter:
\_parameter: (MEMORY_ADDR_H), line:103
|vpiName:MEMORY_ADDR_H
|INT:12
|vpiParameter:
\_parameter: (MEMORY_ADDR_L), line:102
|vpiName:MEMORY_ADDR_L
|INT:11
|vpiParameter:
\_parameter: (MEMORY_BIT_CHECK), line:104
|vpiName:MEMORY_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (MUL_UNIT_WB_ID), line:193
|vpiName:MUL_UNIT_WB_ID
|INT:512
|vpiParameter:
\_parameter: (NUM_UNITS), line:188
|vpiName:NUM_UNITS
|INT:2
|vpiParameter:
\_parameter: (NUM_WB_UNITS), line:186
|vpiName:NUM_WB_UNITS
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (RAS_DEPTH), line:161
|vpiName:RAS_DEPTH
|INT:2
|vpiParameter:
\_parameter: (RESET_VEC), line:39
|vpiName:RESET_VEC
|INT:-2147483648
|vpiParameter:
\_parameter: (SCRATCH_ADDR_H), line:99
|vpiName:SCRATCH_ADDR_H
|INT:9
|vpiParameter:
\_parameter: (SCRATCH_ADDR_L), line:98
|vpiName:SCRATCH_ADDR_L
|INT:8
|vpiParameter:
\_parameter: (SCRATCH_BIT_CHECK), line:100
|vpiName:SCRATCH_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (USE_AMO), line:70
|vpiName:USE_AMO
|INT:1
|vpiParameter:
\_parameter: (USE_BRANCH_PREDICTOR), line:158
|vpiName:USE_BRANCH_PREDICTOR
|INT:2
|vpiParameter:
\_parameter: (USE_BUS), line:88
|vpiName:USE_BUS
|INT:4
|vpiParameter:
\_parameter: (USE_DCACHE), line:92
|vpiName:USE_DCACHE
|INT:6
|vpiParameter:
\_parameter: (USE_DIV), line:49
|vpiName:USE_DIV
|INT:1
|vpiParameter:
\_parameter: (USE_DTAG_INVALIDATIONS), line:140
|vpiName:USE_DTAG_INVALIDATIONS
|INT:1879048191
|vpiParameter:
\_parameter: (USE_D_SCRATCH_MEM), line:79
|vpiName:USE_D_SCRATCH_MEM
|INT:3
|vpiParameter:
\_parameter: (USE_ICACHE), line:93
|vpiName:USE_ICACHE
|INT:7
|vpiParameter:
\_parameter: (USE_I_SCRATCH_MEM), line:78
|vpiName:USE_I_SCRATCH_MEM
|INT:2
|vpiParameter:
\_parameter: (USE_MUL), line:48
|vpiName:USE_MUL
|INT:1
|vpiParameter:
\_parameter: (WB_UNITS_WIDTH), line:187
|vpiName:WB_UNITS_WIDTH
|INT:32
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiGenScopeArray:
\_gen_scope_array: (genblk1), line:171, parent:branch_unit_block
|vpiName:genblk1
|vpiFullName:work@taiga_wrapper.cpu.branch_unit_block.genblk1
|vpiGenScope:
\_gen_scope: , parent:genblk1
|vpiFullName:work@taiga_wrapper.cpu.branch_unit_block.genblk1
|vpiProcess:
\_always: , line:172
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:172
|vpiCondition:
\_operation: , line:172
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:172
|vpiName:clk
|vpiFullName:work@taiga_wrapper.cpu.branch_unit_block.genblk1.clk
|vpiStmt:
\_begin: , line:172
|vpiFullName:work@taiga_wrapper.cpu.branch_unit_block.genblk1
|vpiStmt:
\_if_stmt: , line:173
|vpiCondition:
\_operation: , line:173
|vpiOpType:29
|vpiOperand:
\_ref_obj: (instruction_is_completing), line:173
|vpiName:instruction_is_completing
|vpiFullName:work@taiga_wrapper.cpu.branch_unit_block.genblk1.instruction_is_completing
|vpiOperand:
\_operation: , line:173
|vpiOpType:4
|vpiOperand:
\_ref_obj: (branch_issued_r), line:173
|vpiName:branch_issued_r
|vpiFullName:work@taiga_wrapper.cpu.branch_unit_block.genblk1.branch_issued_r
|vpiStmt:
\_begin: , line:173
|vpiFullName:work@taiga_wrapper.cpu.branch_unit_block.genblk1
|vpiStmt:
\_assignment: , line:174
|vpiOpType:82
|vpiLhs:
\_ref_obj: (is_call), line:174
|vpiName:is_call
|vpiFullName:work@taiga_wrapper.cpu.branch_unit_block.genblk1.is_call
|vpiRhs:
\_ref_obj: (branch_inputs.is_call), line:174
|vpiName:branch_inputs.is_call
|vpiFullName:work@taiga_wrapper.cpu.branch_unit_block.genblk1.branch_inputs.is_call
|vpiStmt:
\_assignment: , line:175
|vpiOpType:82
|vpiLhs:
\_ref_obj: (is_return), line:175
|vpiName:is_return
|vpiFullName:work@taiga_wrapper.cpu.branch_unit_block.genblk1.is_return
|vpiRhs:
\_ref_obj: (branch_inputs.is_return), line:175
|vpiName:branch_inputs.is_return
|vpiFullName:work@taiga_wrapper.cpu.branch_unit_block.genblk1.branch_inputs.is_return
|vpiContAssign:
\_cont_assign: , line:179
|vpiRhs:
\_operation: , line:179
|vpiOpType:28
|vpiOperand:
\_ref_obj: (instruction_is_completing), line:179
|vpiName:instruction_is_completing
|vpiFullName:work@taiga_wrapper.cpu.branch_unit_block.genblk1.instruction_is_completing
|vpiOperand:
\_ref_obj: (is_call), line:179
|vpiName:is_call
|vpiFullName:work@taiga_wrapper.cpu.branch_unit_block.genblk1.is_call
|vpiLhs:
\_ref_obj: (ras.push), line:179
|vpiName:ras.push
|vpiFullName:work@taiga_wrapper.cpu.branch_unit_block.genblk1.ras.push
|vpiContAssign:
\_cont_assign: , line:180
|vpiRhs:
\_operation: , line:180
|vpiOpType:28
|vpiOperand:
\_ref_obj: (instruction_is_completing), line:180
|vpiName:instruction_is_completing
|vpiFullName:work@taiga_wrapper.cpu.branch_unit_block.genblk1.instruction_is_completing
|vpiOperand:
\_ref_obj: (is_return), line:180
|vpiName:is_return
|vpiFullName:work@taiga_wrapper.cpu.branch_unit_block.genblk1.is_return
|vpiLhs:
\_ref_obj: (ras.pop), line:180
|vpiName:ras.pop
|vpiFullName:work@taiga_wrapper.cpu.branch_unit_block.genblk1.ras.pop
|vpiContAssign:
\_cont_assign: , line:181
|vpiRhs:
\_ref_obj: (njump_pc), line:181
|vpiName:njump_pc
|vpiFullName:work@taiga_wrapper.cpu.branch_unit_block.genblk1.njump_pc
|vpiLhs:
\_ref_obj: (ras.new_addr), line:181
|vpiName:ras.new_addr
|vpiFullName:work@taiga_wrapper.cpu.branch_unit_block.genblk1.ras.new_addr
|vpiParameter:
\_parameter: (ALU_UNIT_WB_ID), line:190
|vpiName:ALU_UNIT_WB_ID
|INT:32
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (BRANCH_PREDICTOR_WAYS), line:159
|vpiName:BRANCH_PREDICTOR_WAYS
|INT:9
|vpiParameter:
\_parameter: (BRANCH_TABLE_ENTRIES), line:160
|vpiName:BRANCH_TABLE_ENTRIES
|INT:4
|vpiParameter:
\_parameter: (BRANCH_UNIT_ID), line:195
|vpiName:BRANCH_UNIT_ID
|INT:8
|vpiParameter:
\_parameter: (BUS_ADDR_H), line:107
|vpiName:BUS_ADDR_H
|INT:1
|vpiParameter:
\_parameter: (BUS_ADDR_L), line:106
|vpiName:BUS_ADDR_L
|INT:0
|vpiParameter:
\_parameter: (BUS_BIT_CHECK), line:108
|vpiName:BUS_BIT_CHECK
|INT:1
|vpiParameter:
\_parameter: (BUS_TYPE), line:89
|vpiName:BUS_TYPE
|INT:5
|vpiParameter:
\_parameter: (COUNTER_W), line:42
|vpiName:COUNTER_W
|INT:33
|vpiParameter:
\_parameter: (CPU_ID), line:38
|vpiName:CPU_ID
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_ADDR_WIDTH), line:113
|vpiName:C_M_AXI_ADDR_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_DATA_WIDTH), line:114
|vpiName:C_M_AXI_DATA_WIDTH
|INT:1
|vpiParameter:
\_parameter: (DCACHE_LINES), line:133
|vpiName:DCACHE_LINES
|INT:-2146435073
|vpiParameter:
\_parameter: (DCACHE_LINE_ADDR_W), line:135
|vpiName:DCACHE_LINE_ADDR_W
|INT:1073741824
|vpiParameter:
\_parameter: (DCACHE_LINE_W), line:136
|vpiName:DCACHE_LINE_W
|INT:1342177279
|vpiParameter:
\_parameter: (DCACHE_SUB_LINE_ADDR_W), line:137
|vpiName:DCACHE_SUB_LINE_ADDR_W
|INT:4
|vpiParameter:
\_parameter: (DCACHE_TAG_W), line:138
|vpiName:DCACHE_TAG_W
|INT:1610612736
|vpiParameter:
\_parameter: (DCACHE_WAYS), line:134
|vpiName:DCACHE_WAYS
|INT:4
|vpiParameter:
\_parameter: (DIV_ALGORITHM), line:67
|vpiName:DIV_ALGORITHM
|INT:0
|vpiParameter:
\_parameter: (DIV_UNIT_WB_ID), line:192
|vpiName:DIV_UNIT_WB_ID
|INT:2
|vpiParameter:
\_parameter: (DTLB_DEPTH), line:152
|vpiName:DTLB_DEPTH
|INT:512
|vpiParameter:
\_parameter: (DTLB_WAYS), line:151
|vpiName:DTLB_WAYS
|INT:32
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (ENABLE_M_MODE), line:34
|vpiName:ENABLE_M_MODE
|INT:1
|vpiParameter:
\_parameter: (ENABLE_S_MODE), line:36
|vpiName:ENABLE_S_MODE
|INT:0
|vpiParameter:
\_parameter: (ENABLE_TRACE_INTERFACE), line:172
|vpiName:ENABLE_TRACE_INTERFACE
|INT:2
|vpiParameter:
\_parameter: (FETCH_BUFFER_DEPTH), line:168
|vpiName:FETCH_BUFFER_DEPTH
|INT:512
|vpiParameter:
\_parameter: (FPGA_VENDOR), line:27
|vpiName:FPGA_VENDOR
|STRING:"xilinx"
|vpiParameter:
\_parameter: (GC_UNIT_ID), line:196
|vpiName:GC_UNIT_ID
|INT:4
|vpiParameter:
\_parameter: (ICACHE_LINES), line:121
|vpiName:ICACHE_LINES
|INT:2
|vpiParameter:
\_parameter: (ICACHE_LINE_ADDR_W), line:123
|vpiName:ICACHE_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_LINE_W), line:124
|vpiName:ICACHE_LINE_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_SUB_LINE_ADDR_W), line:125
|vpiName:ICACHE_SUB_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_TAG_W), line:126
|vpiName:ICACHE_TAG_W
|INT:-2147483648
|vpiParameter:
\_parameter: (ICACHE_WAYS), line:122
|vpiName:ICACHE_WAYS
|INT:1
|vpiParameter:
\_parameter: (ITLB_DEPTH), line:146
|vpiName:ITLB_DEPTH
|INT:32
|vpiParameter:
\_parameter: (ITLB_WAYS), line:145
|vpiName:ITLB_WAYS
|INT:4
|vpiParameter:
\_parameter: (L1_CONNECTIONS), line:177
|vpiName:L1_CONNECTIONS
|INT:9
|vpiParameter:
\_parameter: (L1_DCACHE_ID), line:178
|vpiName:L1_DCACHE_ID
|INT:4
|vpiParameter:
\_parameter: (L1_DMMU_ID), line:179
|vpiName:L1_DMMU_ID
|INT:2
|vpiParameter:
\_parameter: (L1_ICACHE_ID), line:180
|vpiName:L1_ICACHE_ID
|INT:19
|vpiParameter:
\_parameter: (L1_IMMU_ID), line:181
|vpiName:L1_IMMU_ID
|INT:0
|vpiParameter:
\_parameter: (LS_UNIT_WB_ID), line:191
|vpiName:LS_UNIT_WB_ID
|INT:1
|vpiParameter:
\_parameter: (MAX_INFLIGHT_COUNT), line:167
|vpiName:MAX_INFLIGHT_COUNT
|INT:19
|vpiParameter:
\_parameter: (MEMORY_ADDR_H), line:103
|vpiName:MEMORY_ADDR_H
|INT:12
|vpiParameter:
\_parameter: (MEMORY_ADDR_L), line:102
|vpiName:MEMORY_ADDR_L
|INT:11
|vpiParameter:
\_parameter: (MEMORY_BIT_CHECK), line:104
|vpiName:MEMORY_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (MUL_UNIT_WB_ID), line:193
|vpiName:MUL_UNIT_WB_ID
|INT:512
|vpiParameter:
\_parameter: (NUM_UNITS), line:188
|vpiName:NUM_UNITS
|INT:2
|vpiParameter:
\_parameter: (NUM_WB_UNITS), line:186
|vpiName:NUM_WB_UNITS
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (RAS_DEPTH), line:161
|vpiName:RAS_DEPTH
|INT:2
|vpiParameter:
\_parameter: (RESET_VEC), line:39
|vpiName:RESET_VEC
|INT:-2147483648
|vpiParameter:
\_parameter: (SCRATCH_ADDR_H), line:99
|vpiName:SCRATCH_ADDR_H
|INT:9
|vpiParameter:
\_parameter: (SCRATCH_ADDR_L), line:98
|vpiName:SCRATCH_ADDR_L
|INT:8
|vpiParameter:
\_parameter: (SCRATCH_BIT_CHECK), line:100
|vpiName:SCRATCH_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (USE_AMO), line:70
|vpiName:USE_AMO
|INT:1
|vpiParameter:
\_parameter: (USE_BRANCH_PREDICTOR), line:158
|vpiName:USE_BRANCH_PREDICTOR
|INT:2
|vpiParameter:
\_parameter: (USE_BUS), line:88
|vpiName:USE_BUS
|INT:4
|vpiParameter:
\_parameter: (USE_DCACHE), line:92
|vpiName:USE_DCACHE
|INT:6
|vpiParameter:
\_parameter: (USE_DIV), line:49
|vpiName:USE_DIV
|INT:1
|vpiParameter:
\_parameter: (USE_DTAG_INVALIDATIONS), line:140
|vpiName:USE_DTAG_INVALIDATIONS
|INT:1879048191
|vpiParameter:
\_parameter: (USE_D_SCRATCH_MEM), line:79
|vpiName:USE_D_SCRATCH_MEM
|INT:3
|vpiParameter:
\_parameter: (USE_ICACHE), line:93
|vpiName:USE_ICACHE
|INT:7
|vpiParameter:
\_parameter: (USE_I_SCRATCH_MEM), line:78
|vpiName:USE_I_SCRATCH_MEM
|INT:2
|vpiParameter:
\_parameter: (USE_MUL), line:48
|vpiName:USE_MUL
|INT:1
|vpiParameter:
\_parameter: (WB_UNITS_WIDTH), line:187
|vpiName:WB_UNITS_WIDTH
|INT:32
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiGenScopeArray:
\_gen_scope_array: (genblk2), line:193, parent:branch_unit_block
|vpiName:genblk2
|vpiFullName:work@taiga_wrapper.cpu.branch_unit_block.genblk2
|vpiGenScope:
\_gen_scope: , parent:genblk2
|vpiFullName:work@taiga_wrapper.cpu.branch_unit_block.genblk2
|vpiContAssign:
\_cont_assign: , line:194
|vpiRhs:
\_operation: , line:194
|vpiOpType:28
|vpiOperand:
\_operation: , line:194
|vpiOpType:28
|vpiOperand:
\_ref_obj: (instruction_is_completing), line:194
|vpiName:instruction_is_completing
|vpiFullName:work@taiga_wrapper.cpu.branch_unit_block.genblk2.instruction_is_completing
|vpiOperand:
\_operation: , line:194
|vpiOpType:4
|vpiOperand:
\_ref_obj: (is_return), line:194
|vpiName:is_return
|vpiFullName:work@taiga_wrapper.cpu.branch_unit_block.genblk2.is_return
|vpiOperand:
\_operation: , line:194
|vpiOpType:4
|vpiOperand:
\_ref_obj: (miss_predict), line:194
|vpiName:miss_predict
|vpiFullName:work@taiga_wrapper.cpu.branch_unit_block.genblk2.miss_predict
|vpiLhs:
\_ref_obj: (tr_branch_correct), line:194
|vpiName:tr_branch_correct
|vpiFullName:work@taiga_wrapper.cpu.branch_unit_block.genblk2.tr_branch_correct
|vpiContAssign:
\_cont_assign: , line:195
|vpiRhs:
\_operation: , line:195
|vpiOpType:28
|vpiOperand:
\_operation: , line:195
|vpiOpType:28
|vpiOperand:
\_ref_obj: (instruction_is_completing), line:195
|vpiName:instruction_is_completing
|vpiFullName:work@taiga_wrapper.cpu.branch_unit_block.genblk2.instruction_is_completing
|vpiOperand:
\_operation: , line:195
|vpiOpType:4
|vpiOperand:
\_ref_obj: (is_return), line:195
|vpiName:is_return
|vpiFullName:work@taiga_wrapper.cpu.branch_unit_block.genblk2.is_return
|vpiOperand:
\_ref_obj: (miss_predict), line:195
|vpiName:miss_predict
|vpiFullName:work@taiga_wrapper.cpu.branch_unit_block.genblk2.miss_predict
|vpiLhs:
\_ref_obj: (tr_branch_misspredict), line:195
|vpiName:tr_branch_misspredict
|vpiFullName:work@taiga_wrapper.cpu.branch_unit_block.genblk2.tr_branch_misspredict
|vpiContAssign:
\_cont_assign: , line:196
|vpiRhs:
\_operation: , line:196
|vpiOpType:28
|vpiOperand:
\_operation: , line:196
|vpiOpType:28
|vpiOperand:
\_ref_obj: (instruction_is_completing), line:196
|vpiName:instruction_is_completing
|vpiFullName:work@taiga_wrapper.cpu.branch_unit_block.genblk2.instruction_is_completing
|vpiOperand:
\_ref_obj: (is_return), line:196
|vpiName:is_return
|vpiFullName:work@taiga_wrapper.cpu.branch_unit_block.genblk2.is_return
|vpiOperand:
\_ref_obj: (miss_predict), line:196
|vpiName:miss_predict
|vpiFullName:work@taiga_wrapper.cpu.branch_unit_block.genblk2.miss_predict
|vpiLhs:
\_ref_obj: (tr_return_misspredict), line:196
|vpiName:tr_return_misspredict
|vpiFullName:work@taiga_wrapper.cpu.branch_unit_block.genblk2.tr_return_misspredict
|vpiParameter:
\_parameter: (ALU_UNIT_WB_ID), line:190
|vpiName:ALU_UNIT_WB_ID
|INT:32
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (BRANCH_PREDICTOR_WAYS), line:159
|vpiName:BRANCH_PREDICTOR_WAYS
|INT:9
|vpiParameter:
\_parameter: (BRANCH_TABLE_ENTRIES), line:160
|vpiName:BRANCH_TABLE_ENTRIES
|INT:4
|vpiParameter:
\_parameter: (BRANCH_UNIT_ID), line:195
|vpiName:BRANCH_UNIT_ID
|INT:8
|vpiParameter:
\_parameter: (BUS_ADDR_H), line:107
|vpiName:BUS_ADDR_H
|INT:1
|vpiParameter:
\_parameter: (BUS_ADDR_L), line:106
|vpiName:BUS_ADDR_L
|INT:0
|vpiParameter:
\_parameter: (BUS_BIT_CHECK), line:108
|vpiName:BUS_BIT_CHECK
|INT:1
|vpiParameter:
\_parameter: (BUS_TYPE), line:89
|vpiName:BUS_TYPE
|INT:5
|vpiParameter:
\_parameter: (COUNTER_W), line:42
|vpiName:COUNTER_W
|INT:33
|vpiParameter:
\_parameter: (CPU_ID), line:38
|vpiName:CPU_ID
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_ADDR_WIDTH), line:113
|vpiName:C_M_AXI_ADDR_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_DATA_WIDTH), line:114
|vpiName:C_M_AXI_DATA_WIDTH
|INT:1
|vpiParameter:
\_parameter: (DCACHE_LINES), line:133
|vpiName:DCACHE_LINES
|INT:-2146435073
|vpiParameter:
\_parameter: (DCACHE_LINE_ADDR_W), line:135
|vpiName:DCACHE_LINE_ADDR_W
|INT:1073741824
|vpiParameter:
\_parameter: (DCACHE_LINE_W), line:136
|vpiName:DCACHE_LINE_W
|INT:1342177279
|vpiParameter:
\_parameter: (DCACHE_SUB_LINE_ADDR_W), line:137
|vpiName:DCACHE_SUB_LINE_ADDR_W
|INT:4
|vpiParameter:
\_parameter: (DCACHE_TAG_W), line:138
|vpiName:DCACHE_TAG_W
|INT:1610612736
|vpiParameter:
\_parameter: (DCACHE_WAYS), line:134
|vpiName:DCACHE_WAYS
|INT:4
|vpiParameter:
\_parameter: (DIV_ALGORITHM), line:67
|vpiName:DIV_ALGORITHM
|INT:0
|vpiParameter:
\_parameter: (DIV_UNIT_WB_ID), line:192
|vpiName:DIV_UNIT_WB_ID
|INT:2
|vpiParameter:
\_parameter: (DTLB_DEPTH), line:152
|vpiName:DTLB_DEPTH
|INT:512
|vpiParameter:
\_parameter: (DTLB_WAYS), line:151
|vpiName:DTLB_WAYS
|INT:32
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (ENABLE_M_MODE), line:34
|vpiName:ENABLE_M_MODE
|INT:1
|vpiParameter:
\_parameter: (ENABLE_S_MODE), line:36
|vpiName:ENABLE_S_MODE
|INT:0
|vpiParameter:
\_parameter: (ENABLE_TRACE_INTERFACE), line:172
|vpiName:ENABLE_TRACE_INTERFACE
|INT:2
|vpiParameter:
\_parameter: (FETCH_BUFFER_DEPTH), line:168
|vpiName:FETCH_BUFFER_DEPTH
|INT:512
|vpiParameter:
\_parameter: (FPGA_VENDOR), line:27
|vpiName:FPGA_VENDOR
|STRING:"xilinx"
|vpiParameter:
\_parameter: (GC_UNIT_ID), line:196
|vpiName:GC_UNIT_ID
|INT:4
|vpiParameter:
\_parameter: (ICACHE_LINES), line:121
|vpiName:ICACHE_LINES
|INT:2
|vpiParameter:
\_parameter: (ICACHE_LINE_ADDR_W), line:123
|vpiName:ICACHE_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_LINE_W), line:124
|vpiName:ICACHE_LINE_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_SUB_LINE_ADDR_W), line:125
|vpiName:ICACHE_SUB_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_TAG_W), line:126
|vpiName:ICACHE_TAG_W
|INT:-2147483648
|vpiParameter:
\_parameter: (ICACHE_WAYS), line:122
|vpiName:ICACHE_WAYS
|INT:1
|vpiParameter:
\_parameter: (ITLB_DEPTH), line:146
|vpiName:ITLB_DEPTH
|INT:32
|vpiParameter:
\_parameter: (ITLB_WAYS), line:145
|vpiName:ITLB_WAYS
|INT:4
|vpiParameter:
\_parameter: (L1_CONNECTIONS), line:177
|vpiName:L1_CONNECTIONS
|INT:9
|vpiParameter:
\_parameter: (L1_DCACHE_ID), line:178
|vpiName:L1_DCACHE_ID
|INT:4
|vpiParameter:
\_parameter: (L1_DMMU_ID), line:179
|vpiName:L1_DMMU_ID
|INT:2
|vpiParameter:
\_parameter: (L1_ICACHE_ID), line:180
|vpiName:L1_ICACHE_ID
|INT:19
|vpiParameter:
\_parameter: (L1_IMMU_ID), line:181
|vpiName:L1_IMMU_ID
|INT:0
|vpiParameter:
\_parameter: (LS_UNIT_WB_ID), line:191
|vpiName:LS_UNIT_WB_ID
|INT:1
|vpiParameter:
\_parameter: (MAX_INFLIGHT_COUNT), line:167
|vpiName:MAX_INFLIGHT_COUNT
|INT:19
|vpiParameter:
\_parameter: (MEMORY_ADDR_H), line:103
|vpiName:MEMORY_ADDR_H
|INT:12
|vpiParameter:
\_parameter: (MEMORY_ADDR_L), line:102
|vpiName:MEMORY_ADDR_L
|INT:11
|vpiParameter:
\_parameter: (MEMORY_BIT_CHECK), line:104
|vpiName:MEMORY_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (MUL_UNIT_WB_ID), line:193
|vpiName:MUL_UNIT_WB_ID
|INT:512
|vpiParameter:
\_parameter: (NUM_UNITS), line:188
|vpiName:NUM_UNITS
|INT:2
|vpiParameter:
\_parameter: (NUM_WB_UNITS), line:186
|vpiName:NUM_WB_UNITS
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (RAS_DEPTH), line:161
|vpiName:RAS_DEPTH
|INT:2
|vpiParameter:
\_parameter: (RESET_VEC), line:39
|vpiName:RESET_VEC
|INT:-2147483648
|vpiParameter:
\_parameter: (SCRATCH_ADDR_H), line:99
|vpiName:SCRATCH_ADDR_H
|INT:9
|vpiParameter:
\_parameter: (SCRATCH_ADDR_L), line:98
|vpiName:SCRATCH_ADDR_L
|INT:8
|vpiParameter:
\_parameter: (SCRATCH_BIT_CHECK), line:100
|vpiName:SCRATCH_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (USE_AMO), line:70
|vpiName:USE_AMO
|INT:1
|vpiParameter:
\_parameter: (USE_BRANCH_PREDICTOR), line:158
|vpiName:USE_BRANCH_PREDICTOR
|INT:2
|vpiParameter:
\_parameter: (USE_BUS), line:88
|vpiName:USE_BUS
|INT:4
|vpiParameter:
\_parameter: (USE_DCACHE), line:92
|vpiName:USE_DCACHE
|INT:6
|vpiParameter:
\_parameter: (USE_DIV), line:49
|vpiName:USE_DIV
|INT:1
|vpiParameter:
\_parameter: (USE_DTAG_INVALIDATIONS), line:140
|vpiName:USE_DTAG_INVALIDATIONS
|INT:1879048191
|vpiParameter:
\_parameter: (USE_D_SCRATCH_MEM), line:79
|vpiName:USE_D_SCRATCH_MEM
|INT:3
|vpiParameter:
\_parameter: (USE_ICACHE), line:93
|vpiName:USE_ICACHE
|INT:7
|vpiParameter:
\_parameter: (USE_I_SCRATCH_MEM), line:78
|vpiName:USE_I_SCRATCH_MEM
|INT:2
|vpiParameter:
\_parameter: (USE_MUL), line:48
|vpiName:USE_MUL
|INT:1
|vpiParameter:
\_parameter: (WB_UNITS_WIDTH), line:187
|vpiName:WB_UNITS_WIDTH
|INT:32
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiNet:
\_logic_net: (clk), line:27, parent:branch_unit_block
|vpiNet:
\_logic_net: (rst), line:28, parent:branch_unit_block
|vpiNet:
\_logic_net: (branch_inputs), line:31, parent:branch_unit_block
|vpiNet:
\_logic_net: (br_results), line:32, parent:branch_unit_block
|vpiNet:
\_logic_net: (branch_flush), line:34, parent:branch_unit_block
|vpiNet:
\_logic_net: (tr_branch_correct), line:37, parent:branch_unit_block
|vpiNet:
\_logic_net: (tr_branch_misspredict), line:38, parent:branch_unit_block
|vpiNet:
\_logic_net: (tr_return_misspredict), line:39, parent:branch_unit_block
|vpiNet:
\_logic_net: (branch_issued_r), line:42, parent:branch_unit_block
|vpiName:branch_issued_r
|vpiFullName:work@taiga_wrapper.cpu.branch_unit_block.branch_issued_r
|vpiNetType:36
|vpiNet:
\_logic_net: (jal_imm), line:44, parent:branch_unit_block
|vpiName:jal_imm
|vpiFullName:work@taiga_wrapper.cpu.branch_unit_block.jal_imm
|vpiNetType:36
|vpiRange:
\_range: , line:44
|vpiLeftRange:
\_constant: , line:44
|vpiConstType:7
|vpiDecompile:19
|vpiSize:32
|INT:19
|vpiRightRange:
\_constant: , line:44
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (jalr_imm), line:45, parent:branch_unit_block
|vpiName:jalr_imm
|vpiFullName:work@taiga_wrapper.cpu.branch_unit_block.jalr_imm
|vpiNetType:36
|vpiRange:
\_range: , line:45
|vpiLeftRange:
\_constant: , line:45
|vpiConstType:7
|vpiDecompile:11
|vpiSize:32
|INT:11
|vpiRightRange:
\_constant: , line:45
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (br_imm), line:46, parent:branch_unit_block
|vpiName:br_imm
|vpiFullName:work@taiga_wrapper.cpu.branch_unit_block.br_imm
|vpiNetType:36
|vpiRange:
\_range: , line:46
|vpiLeftRange:
\_constant: , line:46
|vpiConstType:7
|vpiDecompile:11
|vpiSize:32
|INT:11
|vpiRightRange:
\_constant: , line:46
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (pc_offset), line:48, parent:branch_unit_block
|vpiName:pc_offset
|vpiFullName:work@taiga_wrapper.cpu.branch_unit_block.pc_offset
|vpiNetType:36
|vpiRange:
\_range: , line:48
|vpiLeftRange:
\_constant: , line:48
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:48
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (jump_base), line:49, parent:branch_unit_block
|vpiName:jump_base
|vpiFullName:work@taiga_wrapper.cpu.branch_unit_block.jump_base
|vpiNetType:36
|vpiRange:
\_range: , line:49
|vpiLeftRange:
\_constant: , line:49
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:49
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (jump_pc_dec), line:50, parent:branch_unit_block
|vpiName:jump_pc_dec
|vpiFullName:work@taiga_wrapper.cpu.branch_unit_block.jump_pc_dec
|vpiNetType:36
|vpiRange:
\_range: , line:50
|vpiLeftRange:
\_constant: , line:50
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:50
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (result), line:52, parent:branch_unit_block
|vpiNet:
\_logic_net: (result_ex), line:53, parent:branch_unit_block
|vpiName:result_ex
|vpiFullName:work@taiga_wrapper.cpu.branch_unit_block.result_ex
|vpiNetType:36
|vpiNet:
\_logic_net: (fn3_ex), line:55, parent:branch_unit_block
|vpiName:fn3_ex
|vpiFullName:work@taiga_wrapper.cpu.branch_unit_block.fn3_ex
|vpiNetType:36
|vpiRange:
\_range: , line:55
|vpiLeftRange:
\_constant: , line:55
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiRightRange:
\_constant: , line:55
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (jump_ex), line:56, parent:branch_unit_block
|vpiName:jump_ex
|vpiFullName:work@taiga_wrapper.cpu.branch_unit_block.jump_ex
|vpiNetType:36
|vpiNet:
\_logic_net: (branch_taken), line:59, parent:branch_unit_block
|vpiName:branch_taken
|vpiFullName:work@taiga_wrapper.cpu.branch_unit_block.branch_taken
|vpiNetType:36
|vpiNet:
\_logic_net: (branch_correctly_taken), line:60, parent:branch_unit_block
|vpiName:branch_correctly_taken
|vpiFullName:work@taiga_wrapper.cpu.branch_unit_block.branch_correctly_taken
|vpiNetType:36
|vpiNet:
\_logic_net: (branch_correclty_not_taken), line:61, parent:branch_unit_block
|vpiName:branch_correclty_not_taken
|vpiFullName:work@taiga_wrapper.cpu.branch_unit_block.branch_correclty_not_taken
|vpiNetType:36
|vpiNet:
\_logic_net: (miss_predict), line:62, parent:branch_unit_block
|vpiName:miss_predict
|vpiFullName:work@taiga_wrapper.cpu.branch_unit_block.miss_predict
|vpiNetType:36
|vpiNet:
\_logic_net: (pc_ex), line:64, parent:branch_unit_block
|vpiName:pc_ex
|vpiFullName:work@taiga_wrapper.cpu.branch_unit_block.pc_ex
|vpiNetType:36
|vpiRange:
\_range: , line:64
|vpiLeftRange:
\_constant: , line:64
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:64
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (jump_pc), line:65, parent:branch_unit_block
|vpiName:jump_pc
|vpiFullName:work@taiga_wrapper.cpu.branch_unit_block.jump_pc
|vpiNetType:36
|vpiRange:
\_range: , line:65
|vpiLeftRange:
\_constant: , line:65
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:65
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (njump_pc), line:66, parent:branch_unit_block
|vpiName:njump_pc
|vpiFullName:work@taiga_wrapper.cpu.branch_unit_block.njump_pc
|vpiNetType:36
|vpiRange:
\_range: , line:66
|vpiLeftRange:
\_constant: , line:66
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:66
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (branch_metadata), line:67, parent:branch_unit_block
|vpiName:branch_metadata
|vpiFullName:work@taiga_wrapper.cpu.branch_unit_block.branch_metadata
|vpiNetType:36
|vpiRange:
\_range: , line:67
|vpiLeftRange:
\_constant: , line:67
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:67
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (branch_prediction_used), line:68, parent:branch_unit_block
|vpiName:branch_prediction_used
|vpiFullName:work@taiga_wrapper.cpu.branch_unit_block.branch_prediction_used
|vpiNetType:36
|vpiNet:
\_logic_net: (bp_update_way), line:69, parent:branch_unit_block
|vpiName:bp_update_way
|vpiFullName:work@taiga_wrapper.cpu.branch_unit_block.bp_update_way
|vpiNetType:36
|vpiRange:
\_range: , line:69
|vpiLeftRange:
\_constant: , line:69
|vpiConstType:7
|vpiDecompile:8
|vpiSize:32
|INT:8
|vpiRightRange:
\_constant: , line:69
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (instruction_is_completing), line:71, parent:branch_unit_block
|vpiName:instruction_is_completing
|vpiFullName:work@taiga_wrapper.cpu.branch_unit_block.instruction_is_completing
|vpiNetType:36
|vpiNet:
\_logic_net: (is_call), line:74, parent:branch_unit_block
|vpiName:is_call
|vpiFullName:work@taiga_wrapper.cpu.branch_unit_block.is_call
|vpiNetType:36
|vpiNet:
\_logic_net: (is_return), line:75, parent:branch_unit_block
|vpiName:is_return
|vpiFullName:work@taiga_wrapper.cpu.branch_unit_block.is_return
|vpiNetType:36
|vpiNet:
\_logic_net: (issue), line:30, parent:branch_unit_block
|vpiName:issue
|vpiFullName:work@taiga_wrapper.cpu.branch_unit_block.issue
|vpiNet:
\_logic_net: (ras), line:33, parent:branch_unit_block
|vpiName:ras
|vpiFullName:work@taiga_wrapper.cpu.branch_unit_block.ras
|vpiInstance:
\_module: work@taiga (cpu), file:third_party/cores/taiga/examples/zedboard/taiga_wrapper.sv, line:233, parent:work@taiga_wrapper
|vpiVariables:
\_logic_var: (instruction_id), line:56, parent:branch_unit_block
|vpiName:instruction_id
|vpiFullName:work@taiga_wrapper.cpu.branch_unit_block.instruction_id
|vpiParameter:
\_parameter: (ALU_UNIT_WB_ID), line:190
|vpiName:ALU_UNIT_WB_ID
|INT:32
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (BRANCH_PREDICTOR_WAYS), line:159
|vpiName:BRANCH_PREDICTOR_WAYS
|INT:9
|vpiParameter:
\_parameter: (BRANCH_TABLE_ENTRIES), line:160
|vpiName:BRANCH_TABLE_ENTRIES
|INT:4
|vpiParameter:
\_parameter: (BRANCH_UNIT_ID), line:195
|vpiName:BRANCH_UNIT_ID
|INT:8
|vpiParameter:
\_parameter: (BUS_ADDR_H), line:107
|vpiName:BUS_ADDR_H
|INT:1
|vpiParameter:
\_parameter: (BUS_ADDR_L), line:106
|vpiName:BUS_ADDR_L
|INT:0
|vpiParameter:
\_parameter: (BUS_BIT_CHECK), line:108
|vpiName:BUS_BIT_CHECK
|INT:1
|vpiParameter:
\_parameter: (BUS_TYPE), line:89
|vpiName:BUS_TYPE
|INT:5
|vpiParameter:
\_parameter: (COUNTER_W), line:42
|vpiName:COUNTER_W
|INT:33
|vpiParameter:
\_parameter: (CPU_ID), line:38
|vpiName:CPU_ID
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_ADDR_WIDTH), line:113
|vpiName:C_M_AXI_ADDR_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_DATA_WIDTH), line:114
|vpiName:C_M_AXI_DATA_WIDTH
|INT:1
|vpiParameter:
\_parameter: (DCACHE_LINES), line:133
|vpiName:DCACHE_LINES
|INT:-2146435073
|vpiParameter:
\_parameter: (DCACHE_LINE_ADDR_W), line:135
|vpiName:DCACHE_LINE_ADDR_W
|INT:1073741824
|vpiParameter:
\_parameter: (DCACHE_LINE_W), line:136
|vpiName:DCACHE_LINE_W
|INT:1342177279
|vpiParameter:
\_parameter: (DCACHE_SUB_LINE_ADDR_W), line:137
|vpiName:DCACHE_SUB_LINE_ADDR_W
|INT:4
|vpiParameter:
\_parameter: (DCACHE_TAG_W), line:138
|vpiName:DCACHE_TAG_W
|INT:1610612736
|vpiParameter:
\_parameter: (DCACHE_WAYS), line:134
|vpiName:DCACHE_WAYS
|INT:4
|vpiParameter:
\_parameter: (DIV_ALGORITHM), line:67
|vpiName:DIV_ALGORITHM
|INT:0
|vpiParameter:
\_parameter: (DIV_UNIT_WB_ID), line:192
|vpiName:DIV_UNIT_WB_ID
|INT:2
|vpiParameter:
\_parameter: (DTLB_DEPTH), line:152
|vpiName:DTLB_DEPTH
|INT:512
|vpiParameter:
\_parameter: (DTLB_WAYS), line:151
|vpiName:DTLB_WAYS
|INT:32
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (ENABLE_M_MODE), line:34
|vpiName:ENABLE_M_MODE
|INT:1
|vpiParameter:
\_parameter: (ENABLE_S_MODE), line:36
|vpiName:ENABLE_S_MODE
|INT:0
|vpiParameter:
\_parameter: (ENABLE_TRACE_INTERFACE), line:172
|vpiName:ENABLE_TRACE_INTERFACE
|INT:2
|vpiParameter:
\_parameter: (FETCH_BUFFER_DEPTH), line:168
|vpiName:FETCH_BUFFER_DEPTH
|INT:512
|vpiParameter:
\_parameter: (FPGA_VENDOR), line:27
|vpiName:FPGA_VENDOR
|STRING:"xilinx"
|vpiParameter:
\_parameter: (GC_UNIT_ID), line:196
|vpiName:GC_UNIT_ID
|INT:4
|vpiParameter:
\_parameter: (ICACHE_LINES), line:121
|vpiName:ICACHE_LINES
|INT:2
|vpiParameter:
\_parameter: (ICACHE_LINE_ADDR_W), line:123
|vpiName:ICACHE_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_LINE_W), line:124
|vpiName:ICACHE_LINE_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_SUB_LINE_ADDR_W), line:125
|vpiName:ICACHE_SUB_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_TAG_W), line:126
|vpiName:ICACHE_TAG_W
|INT:-2147483648
|vpiParameter:
\_parameter: (ICACHE_WAYS), line:122
|vpiName:ICACHE_WAYS
|INT:1
|vpiParameter:
\_parameter: (ITLB_DEPTH), line:146
|vpiName:ITLB_DEPTH
|INT:32
|vpiParameter:
\_parameter: (ITLB_WAYS), line:145
|vpiName:ITLB_WAYS
|INT:4
|vpiParameter:
\_parameter: (L1_CONNECTIONS), line:177
|vpiName:L1_CONNECTIONS
|INT:9
|vpiParameter:
\_parameter: (L1_DCACHE_ID), line:178
|vpiName:L1_DCACHE_ID
|INT:4
|vpiParameter:
\_parameter: (L1_DMMU_ID), line:179
|vpiName:L1_DMMU_ID
|INT:2
|vpiParameter:
\_parameter: (L1_ICACHE_ID), line:180
|vpiName:L1_ICACHE_ID
|INT:19
|vpiParameter:
\_parameter: (L1_IMMU_ID), line:181
|vpiName:L1_IMMU_ID
|INT:0
|vpiParameter:
\_parameter: (LS_UNIT_WB_ID), line:191
|vpiName:LS_UNIT_WB_ID
|INT:1
|vpiParameter:
\_parameter: (MAX_INFLIGHT_COUNT), line:167
|vpiName:MAX_INFLIGHT_COUNT
|INT:19
|vpiParameter:
\_parameter: (MEMORY_ADDR_H), line:103
|vpiName:MEMORY_ADDR_H
|INT:12
|vpiParameter:
\_parameter: (MEMORY_ADDR_L), line:102
|vpiName:MEMORY_ADDR_L
|INT:11
|vpiParameter:
\_parameter: (MEMORY_BIT_CHECK), line:104
|vpiName:MEMORY_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (MUL_UNIT_WB_ID), line:193
|vpiName:MUL_UNIT_WB_ID
|INT:512
|vpiParameter:
\_parameter: (NUM_UNITS), line:188
|vpiName:NUM_UNITS
|INT:2
|vpiParameter:
\_parameter: (NUM_WB_UNITS), line:186
|vpiName:NUM_WB_UNITS
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (RAS_DEPTH), line:161
|vpiName:RAS_DEPTH
|INT:2
|vpiParameter:
\_parameter: (RESET_VEC), line:39
|vpiName:RESET_VEC
|INT:-2147483648
|vpiParameter:
\_parameter: (SCRATCH_ADDR_H), line:99
|vpiName:SCRATCH_ADDR_H
|INT:9
|vpiParameter:
\_parameter: (SCRATCH_ADDR_L), line:98
|vpiName:SCRATCH_ADDR_L
|INT:8
|vpiParameter:
\_parameter: (SCRATCH_BIT_CHECK), line:100
|vpiName:SCRATCH_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (USE_AMO), line:70
|vpiName:USE_AMO
|INT:1
|vpiParameter:
\_parameter: (USE_BRANCH_PREDICTOR), line:158
|vpiName:USE_BRANCH_PREDICTOR
|INT:2
|vpiParameter:
\_parameter: (USE_BUS), line:88
|vpiName:USE_BUS
|INT:4
|vpiParameter:
\_parameter: (USE_DCACHE), line:92
|vpiName:USE_DCACHE
|INT:6
|vpiParameter:
\_parameter: (USE_DIV), line:49
|vpiName:USE_DIV
|INT:1
|vpiParameter:
\_parameter: (USE_DTAG_INVALIDATIONS), line:140
|vpiName:USE_DTAG_INVALIDATIONS
|INT:1879048191
|vpiParameter:
\_parameter: (USE_D_SCRATCH_MEM), line:79
|vpiName:USE_D_SCRATCH_MEM
|INT:3
|vpiParameter:
\_parameter: (USE_ICACHE), line:93
|vpiName:USE_ICACHE
|INT:7
|vpiParameter:
\_parameter: (USE_I_SCRATCH_MEM), line:78
|vpiName:USE_I_SCRATCH_MEM
|INT:2
|vpiParameter:
\_parameter: (USE_MUL), line:48
|vpiName:USE_MUL
|INT:1
|vpiParameter:
\_parameter: (WB_UNITS_WIDTH), line:187
|vpiName:WB_UNITS_WIDTH
|INT:32
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiModule:
\_module: work@alu_unit (alu_unit_block), file:third_party/cores/taiga/core/taiga.sv, line:182, parent:cpu
|vpiDefName:work@alu_unit
|vpiName:alu_unit_block
|vpiFullName:work@taiga_wrapper.cpu.alu_unit_block
|vpiPort:
\_port: (clk), line:27, parent:alu_unit_block
|vpiName:clk
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (clk), line:182
|vpiName:clk
|vpiActual:
\_logic_net: (clk), line:27, parent:cpu
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (clk), line:27, parent:alu_unit_block
|vpiName:clk
|vpiFullName:work@taiga_wrapper.cpu.alu_unit_block.clk
|vpiNetType:36
|vpiPort:
\_port: (rst), line:28, parent:alu_unit_block
|vpiName:rst
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (rst), line:182
|vpiName:rst
|vpiActual:
\_logic_net: (rst), line:28, parent:cpu
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (rst), line:28, parent:alu_unit_block
|vpiName:rst
|vpiFullName:work@taiga_wrapper.cpu.alu_unit_block.rst
|vpiNetType:36
|vpiPort:
\_port: (issue), line:29, parent:alu_unit_block
|vpiName:issue
|vpiDirection:5
|vpiHighConn:
\_ref_obj: (issue), line:182
|vpiName:issue
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_modport: (unit)
|vpiName:unit
|vpiIODecl:
\_io_decl: (ready)
|vpiName:ready
|vpiDirection:2
|vpiExpr:
\_logic_net: (ready), line:58
|vpiName:ready
|vpiNetType:36
|vpiIODecl:
\_io_decl: (possible_issue)
|vpiName:possible_issue
|vpiDirection:1
|vpiExpr:
\_logic_net: (possible_issue), line:53
|vpiName:possible_issue
|vpiNetType:36
|vpiIODecl:
\_io_decl: (new_request)
|vpiName:new_request
|vpiDirection:1
|vpiExpr:
\_logic_net: (new_request), line:54
|vpiName:new_request
|vpiNetType:36
|vpiIODecl:
\_io_decl: (new_request_r)
|vpiName:new_request_r
|vpiDirection:1
|vpiExpr:
\_logic_net: (new_request_r), line:55
|vpiName:new_request_r
|vpiNetType:36
|vpiIODecl:
\_io_decl: (instruction_id)
|vpiName:instruction_id
|vpiDirection:1
|vpiInterface:
\_interface: work@unit_issue_interface (issue), file:third_party/cores/taiga/core/taiga.sv, line:182
|vpiDefName:work@unit_issue_interface
|vpiName:issue
|vpiModport:
\_modport: (decode)
|vpiName:decode
|vpiIODecl:
\_io_decl: (ready)
|vpiName:ready
|vpiDirection:1
|vpiExpr:
\_logic_net: (ready), line:58
|vpiIODecl:
\_io_decl: (possible_issue)
|vpiName:possible_issue
|vpiDirection:2
|vpiExpr:
\_logic_net: (possible_issue), line:53
|vpiIODecl:
\_io_decl: (new_request)
|vpiName:new_request
|vpiDirection:2
|vpiExpr:
\_logic_net: (new_request), line:54
|vpiIODecl:
\_io_decl: (new_request_r)
|vpiName:new_request_r
|vpiDirection:2
|vpiExpr:
\_logic_net: (new_request_r), line:55
|vpiIODecl:
\_io_decl: (instruction_id)
|vpiName:instruction_id
|vpiDirection:2
|vpiInterface:
\_interface: work@unit_issue_interface (issue), file:third_party/cores/taiga/core/taiga.sv, line:182
|vpiModport:
\_modport: (unit)
|vpiPort:
\_port: (alu_inputs), line:30, parent:alu_unit_block
|vpiName:alu_inputs
|vpiDirection:1
|vpiTypedef:
\_struct_typespec: (alu_inputs_t), line:301
|vpiHighConn:
\_ref_obj: (alu_inputs), line:182
|vpiName:alu_inputs
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (alu_inputs), line:30, parent:alu_unit_block
|vpiName:alu_inputs
|vpiFullName:work@taiga_wrapper.cpu.alu_unit_block.alu_inputs
|vpiPort:
\_port: (wb), line:31, parent:alu_unit_block
|vpiName:wb
|vpiDirection:2
|vpiTypedef:
\_struct_typespec: (unit_writeback_t), line:295
|vpiHighConn:
\_ref_obj: (wb), line:182
|vpiName:wb
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (wb), line:31, parent:alu_unit_block
|vpiName:wb
|vpiFullName:work@taiga_wrapper.cpu.alu_unit_block.wb
|vpiModule:
\_module: work@barrel_shifter (shifter), file:third_party/cores/taiga/core/alu_unit.sv, line:64, parent:alu_unit_block
|vpiDefName:work@barrel_shifter
|vpiName:shifter
|vpiFullName:work@taiga_wrapper.cpu.alu_unit_block.shifter
|vpiPort:
\_port: (shifter_input), line:27, parent:shifter
|vpiName:shifter_input
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (alu_inputs.shifter_in), line:65
|vpiName:alu_inputs.shifter_in
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (shifter_input), line:27, parent:shifter
|vpiName:shifter_input
|vpiFullName:work@taiga_wrapper.cpu.alu_unit_block.shifter.shifter_input
|vpiNetType:36
|vpiRange:
\_range: , line:27
|vpiLeftRange:
\_constant: , line:27
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiRightRange:
\_constant: , line:27
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiPort:
\_port: (shift_amount), line:28, parent:shifter
|vpiName:shift_amount
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (alu_inputs.shift_amount), line:66
|vpiName:alu_inputs.shift_amount
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (shift_amount), line:28, parent:shifter
|vpiName:shift_amount
|vpiFullName:work@taiga_wrapper.cpu.alu_unit_block.shifter.shift_amount
|vpiNetType:36
|vpiRange:
\_range: , line:28
|vpiLeftRange:
\_constant: , line:28
|vpiConstType:7
|vpiDecompile:4
|vpiSize:32
|INT:4
|vpiRightRange:
\_constant: , line:28
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiPort:
\_port: (arith), line:29, parent:shifter
|vpiName:arith
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (alu_inputs.arith), line:67
|vpiName:alu_inputs.arith
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (arith), line:29, parent:shifter
|vpiName:arith
|vpiFullName:work@taiga_wrapper.cpu.alu_unit_block.shifter.arith
|vpiNetType:36
|vpiPort:
\_port: (lshift), line:30, parent:shifter
|vpiName:lshift
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (alu_inputs.lshift), line:68
|vpiName:alu_inputs.lshift
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (lshift), line:30, parent:shifter
|vpiName:lshift
|vpiFullName:work@taiga_wrapper.cpu.alu_unit_block.shifter.lshift
|vpiNetType:36
|vpiPort:
\_port: (shifted_resultr), line:31, parent:shifter
|vpiName:shifted_resultr
|vpiDirection:2
|vpiHighConn:
\_ref_obj: (rshift_result), line:69
|vpiName:rshift_result
|vpiActual:
\_logic_net: (rshift_result), line:36, parent:alu_unit_block
|vpiName:rshift_result
|vpiFullName:work@taiga_wrapper.cpu.alu_unit_block.rshift_result
|vpiNetType:36
|vpiRange:
\_range: , line:36
|vpiLeftRange:
\_constant: , line:36
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiRightRange:
\_constant: , line:36
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (shifted_resultr), line:31, parent:shifter
|vpiName:shifted_resultr
|vpiFullName:work@taiga_wrapper.cpu.alu_unit_block.shifter.shifted_resultr
|vpiNetType:36
|vpiRange:
\_range: , line:31
|vpiLeftRange:
\_constant: , line:31
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiRightRange:
\_constant: , line:31
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiPort:
\_port: (shifted_resultl), line:32, parent:shifter
|vpiName:shifted_resultl
|vpiDirection:2
|vpiHighConn:
\_ref_obj: (lshift_result), line:70
|vpiName:lshift_result
|vpiActual:
\_logic_net: (lshift_result), line:37, parent:alu_unit_block
|vpiName:lshift_result
|vpiFullName:work@taiga_wrapper.cpu.alu_unit_block.lshift_result
|vpiNetType:36
|vpiRange:
\_range: , line:37
|vpiLeftRange:
\_constant: , line:37
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiRightRange:
\_constant: , line:37
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (shifted_resultl), line:32, parent:shifter
|vpiName:shifted_resultl
|vpiFullName:work@taiga_wrapper.cpu.alu_unit_block.shifter.shifted_resultl
|vpiNetType:36
|vpiRange:
\_range: , line:32
|vpiLeftRange:
\_constant: , line:32
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiRightRange:
\_constant: , line:32
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (shifter_input), line:27, parent:shifter
|vpiNet:
\_logic_net: (shift_amount), line:28, parent:shifter
|vpiNet:
\_logic_net: (arith), line:29, parent:shifter
|vpiNet:
\_logic_net: (lshift), line:30, parent:shifter
|vpiNet:
\_logic_net: (shifted_resultr), line:31, parent:shifter
|vpiNet:
\_logic_net: (shifted_resultl), line:32, parent:shifter
|vpiNet:
\_logic_net: (shiftx8), line:35, parent:shifter
|vpiName:shiftx8
|vpiFullName:work@taiga_wrapper.cpu.alu_unit_block.shifter.shiftx8
|vpiNetType:36
|vpiRange:
\_range: , line:35
|vpiLeftRange:
\_constant: , line:35
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiRightRange:
\_constant: , line:35
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (shiftx2), line:35, parent:shifter
|vpiName:shiftx2
|vpiFullName:work@taiga_wrapper.cpu.alu_unit_block.shifter.shiftx2
|vpiNetType:36
|vpiRange:
\_range: , line:35
|vpiLeftRange:
\_constant: , line:35
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiRightRange:
\_constant: , line:35
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (shiftx1), line:35, parent:shifter
|vpiName:shiftx1
|vpiFullName:work@taiga_wrapper.cpu.alu_unit_block.shifter.shiftx1
|vpiNetType:36
|vpiRange:
\_range: , line:35
|vpiLeftRange:
\_constant: , line:35
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiRightRange:
\_constant: , line:35
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (preshifted_input), line:36, parent:shifter
|vpiName:preshifted_input
|vpiFullName:work@taiga_wrapper.cpu.alu_unit_block.shifter.preshifted_input
|vpiNetType:36
|vpiRange:
\_range: , line:36
|vpiLeftRange:
\_constant: , line:36
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiRightRange:
\_constant: , line:36
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiInstance:
\_module: work@alu_unit (alu_unit_block), file:third_party/cores/taiga/core/taiga.sv, line:182, parent:cpu
|vpiParameter:
\_parameter: (ALU_UNIT_WB_ID), line:190
|vpiName:ALU_UNIT_WB_ID
|INT:32
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (BRANCH_PREDICTOR_WAYS), line:159
|vpiName:BRANCH_PREDICTOR_WAYS
|INT:9
|vpiParameter:
\_parameter: (BRANCH_TABLE_ENTRIES), line:160
|vpiName:BRANCH_TABLE_ENTRIES
|INT:4
|vpiParameter:
\_parameter: (BRANCH_UNIT_ID), line:195
|vpiName:BRANCH_UNIT_ID
|INT:8
|vpiParameter:
\_parameter: (BUS_ADDR_H), line:107
|vpiName:BUS_ADDR_H
|INT:1
|vpiParameter:
\_parameter: (BUS_ADDR_L), line:106
|vpiName:BUS_ADDR_L
|INT:0
|vpiParameter:
\_parameter: (BUS_BIT_CHECK), line:108
|vpiName:BUS_BIT_CHECK
|INT:1
|vpiParameter:
\_parameter: (BUS_TYPE), line:89
|vpiName:BUS_TYPE
|INT:5
|vpiParameter:
\_parameter: (COUNTER_W), line:42
|vpiName:COUNTER_W
|INT:33
|vpiParameter:
\_parameter: (CPU_ID), line:38
|vpiName:CPU_ID
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_ADDR_WIDTH), line:113
|vpiName:C_M_AXI_ADDR_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_DATA_WIDTH), line:114
|vpiName:C_M_AXI_DATA_WIDTH
|INT:1
|vpiParameter:
\_parameter: (DCACHE_LINES), line:133
|vpiName:DCACHE_LINES
|INT:-2146435073
|vpiParameter:
\_parameter: (DCACHE_LINE_ADDR_W), line:135
|vpiName:DCACHE_LINE_ADDR_W
|INT:1073741824
|vpiParameter:
\_parameter: (DCACHE_LINE_W), line:136
|vpiName:DCACHE_LINE_W
|INT:1342177279
|vpiParameter:
\_parameter: (DCACHE_SUB_LINE_ADDR_W), line:137
|vpiName:DCACHE_SUB_LINE_ADDR_W
|INT:4
|vpiParameter:
\_parameter: (DCACHE_TAG_W), line:138
|vpiName:DCACHE_TAG_W
|INT:1610612736
|vpiParameter:
\_parameter: (DCACHE_WAYS), line:134
|vpiName:DCACHE_WAYS
|INT:4
|vpiParameter:
\_parameter: (DIV_ALGORITHM), line:67
|vpiName:DIV_ALGORITHM
|INT:0
|vpiParameter:
\_parameter: (DIV_UNIT_WB_ID), line:192
|vpiName:DIV_UNIT_WB_ID
|INT:2
|vpiParameter:
\_parameter: (DTLB_DEPTH), line:152
|vpiName:DTLB_DEPTH
|INT:512
|vpiParameter:
\_parameter: (DTLB_WAYS), line:151
|vpiName:DTLB_WAYS
|INT:32
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (ENABLE_M_MODE), line:34
|vpiName:ENABLE_M_MODE
|INT:1
|vpiParameter:
\_parameter: (ENABLE_S_MODE), line:36
|vpiName:ENABLE_S_MODE
|INT:0
|vpiParameter:
\_parameter: (ENABLE_TRACE_INTERFACE), line:172
|vpiName:ENABLE_TRACE_INTERFACE
|INT:2
|vpiParameter:
\_parameter: (FETCH_BUFFER_DEPTH), line:168
|vpiName:FETCH_BUFFER_DEPTH
|INT:512
|vpiParameter:
\_parameter: (FPGA_VENDOR), line:27
|vpiName:FPGA_VENDOR
|STRING:"xilinx"
|vpiParameter:
\_parameter: (GC_UNIT_ID), line:196
|vpiName:GC_UNIT_ID
|INT:4
|vpiParameter:
\_parameter: (ICACHE_LINES), line:121
|vpiName:ICACHE_LINES
|INT:2
|vpiParameter:
\_parameter: (ICACHE_LINE_ADDR_W), line:123
|vpiName:ICACHE_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_LINE_W), line:124
|vpiName:ICACHE_LINE_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_SUB_LINE_ADDR_W), line:125
|vpiName:ICACHE_SUB_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_TAG_W), line:126
|vpiName:ICACHE_TAG_W
|INT:-2147483648
|vpiParameter:
\_parameter: (ICACHE_WAYS), line:122
|vpiName:ICACHE_WAYS
|INT:1
|vpiParameter:
\_parameter: (ITLB_DEPTH), line:146
|vpiName:ITLB_DEPTH
|INT:32
|vpiParameter:
\_parameter: (ITLB_WAYS), line:145
|vpiName:ITLB_WAYS
|INT:4
|vpiParameter:
\_parameter: (L1_CONNECTIONS), line:177
|vpiName:L1_CONNECTIONS
|INT:9
|vpiParameter:
\_parameter: (L1_DCACHE_ID), line:178
|vpiName:L1_DCACHE_ID
|INT:4
|vpiParameter:
\_parameter: (L1_DMMU_ID), line:179
|vpiName:L1_DMMU_ID
|INT:2
|vpiParameter:
\_parameter: (L1_ICACHE_ID), line:180
|vpiName:L1_ICACHE_ID
|INT:19
|vpiParameter:
\_parameter: (L1_IMMU_ID), line:181
|vpiName:L1_IMMU_ID
|INT:0
|vpiParameter:
\_parameter: (LS_UNIT_WB_ID), line:191
|vpiName:LS_UNIT_WB_ID
|INT:1
|vpiParameter:
\_parameter: (MAX_INFLIGHT_COUNT), line:167
|vpiName:MAX_INFLIGHT_COUNT
|INT:19
|vpiParameter:
\_parameter: (MEMORY_ADDR_H), line:103
|vpiName:MEMORY_ADDR_H
|INT:12
|vpiParameter:
\_parameter: (MEMORY_ADDR_L), line:102
|vpiName:MEMORY_ADDR_L
|INT:11
|vpiParameter:
\_parameter: (MEMORY_BIT_CHECK), line:104
|vpiName:MEMORY_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (MUL_UNIT_WB_ID), line:193
|vpiName:MUL_UNIT_WB_ID
|INT:512
|vpiParameter:
\_parameter: (NUM_UNITS), line:188
|vpiName:NUM_UNITS
|INT:2
|vpiParameter:
\_parameter: (NUM_WB_UNITS), line:186
|vpiName:NUM_WB_UNITS
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (RAS_DEPTH), line:161
|vpiName:RAS_DEPTH
|INT:2
|vpiParameter:
\_parameter: (RESET_VEC), line:39
|vpiName:RESET_VEC
|INT:-2147483648
|vpiParameter:
\_parameter: (SCRATCH_ADDR_H), line:99
|vpiName:SCRATCH_ADDR_H
|INT:9
|vpiParameter:
\_parameter: (SCRATCH_ADDR_L), line:98
|vpiName:SCRATCH_ADDR_L
|INT:8
|vpiParameter:
\_parameter: (SCRATCH_BIT_CHECK), line:100
|vpiName:SCRATCH_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (USE_AMO), line:70
|vpiName:USE_AMO
|INT:1
|vpiParameter:
\_parameter: (USE_BRANCH_PREDICTOR), line:158
|vpiName:USE_BRANCH_PREDICTOR
|INT:2
|vpiParameter:
\_parameter: (USE_BUS), line:88
|vpiName:USE_BUS
|INT:4
|vpiParameter:
\_parameter: (USE_DCACHE), line:92
|vpiName:USE_DCACHE
|INT:6
|vpiParameter:
\_parameter: (USE_DIV), line:49
|vpiName:USE_DIV
|INT:1
|vpiParameter:
\_parameter: (USE_DTAG_INVALIDATIONS), line:140
|vpiName:USE_DTAG_INVALIDATIONS
|INT:1879048191
|vpiParameter:
\_parameter: (USE_D_SCRATCH_MEM), line:79
|vpiName:USE_D_SCRATCH_MEM
|INT:3
|vpiParameter:
\_parameter: (USE_ICACHE), line:93
|vpiName:USE_ICACHE
|INT:7
|vpiParameter:
\_parameter: (USE_I_SCRATCH_MEM), line:78
|vpiName:USE_I_SCRATCH_MEM
|INT:2
|vpiParameter:
\_parameter: (USE_MUL), line:48
|vpiName:USE_MUL
|INT:1
|vpiParameter:
\_parameter: (WB_UNITS_WIDTH), line:187
|vpiName:WB_UNITS_WIDTH
|INT:32
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiNet:
\_logic_net: (clk), line:27, parent:alu_unit_block
|vpiNet:
\_logic_net: (rst), line:28, parent:alu_unit_block
|vpiNet:
\_logic_net: (alu_inputs), line:30, parent:alu_unit_block
|vpiNet:
\_logic_net: (wb), line:31, parent:alu_unit_block
|vpiNet:
\_logic_net: (add_sub_result), line:34, parent:alu_unit_block
|vpiName:add_sub_result
|vpiFullName:work@taiga_wrapper.cpu.alu_unit_block.add_sub_result
|vpiNetType:36
|vpiRange:
\_range: , line:34
|vpiLeftRange:
\_constant: , line:34
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:34
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (add_sub_carry_in), line:35, parent:alu_unit_block
|vpiName:add_sub_carry_in
|vpiFullName:work@taiga_wrapper.cpu.alu_unit_block.add_sub_carry_in
|vpiNetType:36
|vpiNet:
\_logic_net: (rshift_result), line:36, parent:alu_unit_block
|vpiNet:
\_logic_net: (lshift_result), line:37, parent:alu_unit_block
|vpiNet:
\_logic_net: (adder_in1), line:39, parent:alu_unit_block
|vpiName:adder_in1
|vpiFullName:work@taiga_wrapper.cpu.alu_unit_block.adder_in1
|vpiNetType:36
|vpiRange:
\_range: , line:39
|vpiLeftRange:
\_constant: , line:39
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:39
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (adder_in2), line:40, parent:alu_unit_block
|vpiName:adder_in2
|vpiFullName:work@taiga_wrapper.cpu.alu_unit_block.adder_in2
|vpiNetType:36
|vpiRange:
\_range: , line:40
|vpiLeftRange:
\_constant: , line:40
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:40
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (result), line:42, parent:alu_unit_block
|vpiName:result
|vpiFullName:work@taiga_wrapper.cpu.alu_unit_block.result
|vpiNetType:36
|vpiRange:
\_range: , line:42
|vpiLeftRange:
\_constant: , line:42
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiRightRange:
\_constant: , line:42
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (issue), line:29, parent:alu_unit_block
|vpiName:issue
|vpiFullName:work@taiga_wrapper.cpu.alu_unit_block.issue
|vpiInstance:
\_module: work@taiga (cpu), file:third_party/cores/taiga/examples/zedboard/taiga_wrapper.sv, line:233, parent:work@taiga_wrapper
|vpiVariables:
\_logic_var: (instruction_id), line:56, parent:alu_unit_block
|vpiName:instruction_id
|vpiFullName:work@taiga_wrapper.cpu.alu_unit_block.instruction_id
|vpiParameter:
\_parameter: (ALU_UNIT_WB_ID), line:190
|vpiName:ALU_UNIT_WB_ID
|INT:32
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (BRANCH_PREDICTOR_WAYS), line:159
|vpiName:BRANCH_PREDICTOR_WAYS
|INT:9
|vpiParameter:
\_parameter: (BRANCH_TABLE_ENTRIES), line:160
|vpiName:BRANCH_TABLE_ENTRIES
|INT:4
|vpiParameter:
\_parameter: (BRANCH_UNIT_ID), line:195
|vpiName:BRANCH_UNIT_ID
|INT:8
|vpiParameter:
\_parameter: (BUS_ADDR_H), line:107
|vpiName:BUS_ADDR_H
|INT:1
|vpiParameter:
\_parameter: (BUS_ADDR_L), line:106
|vpiName:BUS_ADDR_L
|INT:0
|vpiParameter:
\_parameter: (BUS_BIT_CHECK), line:108
|vpiName:BUS_BIT_CHECK
|INT:1
|vpiParameter:
\_parameter: (BUS_TYPE), line:89
|vpiName:BUS_TYPE
|INT:5
|vpiParameter:
\_parameter: (COUNTER_W), line:42
|vpiName:COUNTER_W
|INT:33
|vpiParameter:
\_parameter: (CPU_ID), line:38
|vpiName:CPU_ID
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_ADDR_WIDTH), line:113
|vpiName:C_M_AXI_ADDR_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_DATA_WIDTH), line:114
|vpiName:C_M_AXI_DATA_WIDTH
|INT:1
|vpiParameter:
\_parameter: (DCACHE_LINES), line:133
|vpiName:DCACHE_LINES
|INT:-2146435073
|vpiParameter:
\_parameter: (DCACHE_LINE_ADDR_W), line:135
|vpiName:DCACHE_LINE_ADDR_W
|INT:1073741824
|vpiParameter:
\_parameter: (DCACHE_LINE_W), line:136
|vpiName:DCACHE_LINE_W
|INT:1342177279
|vpiParameter:
\_parameter: (DCACHE_SUB_LINE_ADDR_W), line:137
|vpiName:DCACHE_SUB_LINE_ADDR_W
|INT:4
|vpiParameter:
\_parameter: (DCACHE_TAG_W), line:138
|vpiName:DCACHE_TAG_W
|INT:1610612736
|vpiParameter:
\_parameter: (DCACHE_WAYS), line:134
|vpiName:DCACHE_WAYS
|INT:4
|vpiParameter:
\_parameter: (DIV_ALGORITHM), line:67
|vpiName:DIV_ALGORITHM
|INT:0
|vpiParameter:
\_parameter: (DIV_UNIT_WB_ID), line:192
|vpiName:DIV_UNIT_WB_ID
|INT:2
|vpiParameter:
\_parameter: (DTLB_DEPTH), line:152
|vpiName:DTLB_DEPTH
|INT:512
|vpiParameter:
\_parameter: (DTLB_WAYS), line:151
|vpiName:DTLB_WAYS
|INT:32
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (ENABLE_M_MODE), line:34
|vpiName:ENABLE_M_MODE
|INT:1
|vpiParameter:
\_parameter: (ENABLE_S_MODE), line:36
|vpiName:ENABLE_S_MODE
|INT:0
|vpiParameter:
\_parameter: (ENABLE_TRACE_INTERFACE), line:172
|vpiName:ENABLE_TRACE_INTERFACE
|INT:2
|vpiParameter:
\_parameter: (FETCH_BUFFER_DEPTH), line:168
|vpiName:FETCH_BUFFER_DEPTH
|INT:512
|vpiParameter:
\_parameter: (FPGA_VENDOR), line:27
|vpiName:FPGA_VENDOR
|STRING:"xilinx"
|vpiParameter:
\_parameter: (GC_UNIT_ID), line:196
|vpiName:GC_UNIT_ID
|INT:4
|vpiParameter:
\_parameter: (ICACHE_LINES), line:121
|vpiName:ICACHE_LINES
|INT:2
|vpiParameter:
\_parameter: (ICACHE_LINE_ADDR_W), line:123
|vpiName:ICACHE_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_LINE_W), line:124
|vpiName:ICACHE_LINE_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_SUB_LINE_ADDR_W), line:125
|vpiName:ICACHE_SUB_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_TAG_W), line:126
|vpiName:ICACHE_TAG_W
|INT:-2147483648
|vpiParameter:
\_parameter: (ICACHE_WAYS), line:122
|vpiName:ICACHE_WAYS
|INT:1
|vpiParameter:
\_parameter: (ITLB_DEPTH), line:146
|vpiName:ITLB_DEPTH
|INT:32
|vpiParameter:
\_parameter: (ITLB_WAYS), line:145
|vpiName:ITLB_WAYS
|INT:4
|vpiParameter:
\_parameter: (L1_CONNECTIONS), line:177
|vpiName:L1_CONNECTIONS
|INT:9
|vpiParameter:
\_parameter: (L1_DCACHE_ID), line:178
|vpiName:L1_DCACHE_ID
|INT:4
|vpiParameter:
\_parameter: (L1_DMMU_ID), line:179
|vpiName:L1_DMMU_ID
|INT:2
|vpiParameter:
\_parameter: (L1_ICACHE_ID), line:180
|vpiName:L1_ICACHE_ID
|INT:19
|vpiParameter:
\_parameter: (L1_IMMU_ID), line:181
|vpiName:L1_IMMU_ID
|INT:0
|vpiParameter:
\_parameter: (LS_UNIT_WB_ID), line:191
|vpiName:LS_UNIT_WB_ID
|INT:1
|vpiParameter:
\_parameter: (MAX_INFLIGHT_COUNT), line:167
|vpiName:MAX_INFLIGHT_COUNT
|INT:19
|vpiParameter:
\_parameter: (MEMORY_ADDR_H), line:103
|vpiName:MEMORY_ADDR_H
|INT:12
|vpiParameter:
\_parameter: (MEMORY_ADDR_L), line:102
|vpiName:MEMORY_ADDR_L
|INT:11
|vpiParameter:
\_parameter: (MEMORY_BIT_CHECK), line:104
|vpiName:MEMORY_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (MUL_UNIT_WB_ID), line:193
|vpiName:MUL_UNIT_WB_ID
|INT:512
|vpiParameter:
\_parameter: (NUM_UNITS), line:188
|vpiName:NUM_UNITS
|INT:2
|vpiParameter:
\_parameter: (NUM_WB_UNITS), line:186
|vpiName:NUM_WB_UNITS
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (RAS_DEPTH), line:161
|vpiName:RAS_DEPTH
|INT:2
|vpiParameter:
\_parameter: (RESET_VEC), line:39
|vpiName:RESET_VEC
|INT:-2147483648
|vpiParameter:
\_parameter: (SCRATCH_ADDR_H), line:99
|vpiName:SCRATCH_ADDR_H
|INT:9
|vpiParameter:
\_parameter: (SCRATCH_ADDR_L), line:98
|vpiName:SCRATCH_ADDR_L
|INT:8
|vpiParameter:
\_parameter: (SCRATCH_BIT_CHECK), line:100
|vpiName:SCRATCH_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (USE_AMO), line:70
|vpiName:USE_AMO
|INT:1
|vpiParameter:
\_parameter: (USE_BRANCH_PREDICTOR), line:158
|vpiName:USE_BRANCH_PREDICTOR
|INT:2
|vpiParameter:
\_parameter: (USE_BUS), line:88
|vpiName:USE_BUS
|INT:4
|vpiParameter:
\_parameter: (USE_DCACHE), line:92
|vpiName:USE_DCACHE
|INT:6
|vpiParameter:
\_parameter: (USE_DIV), line:49
|vpiName:USE_DIV
|INT:1
|vpiParameter:
\_parameter: (USE_DTAG_INVALIDATIONS), line:140
|vpiName:USE_DTAG_INVALIDATIONS
|INT:1879048191
|vpiParameter:
\_parameter: (USE_D_SCRATCH_MEM), line:79
|vpiName:USE_D_SCRATCH_MEM
|INT:3
|vpiParameter:
\_parameter: (USE_ICACHE), line:93
|vpiName:USE_ICACHE
|INT:7
|vpiParameter:
\_parameter: (USE_I_SCRATCH_MEM), line:78
|vpiName:USE_I_SCRATCH_MEM
|INT:2
|vpiParameter:
\_parameter: (USE_MUL), line:48
|vpiName:USE_MUL
|INT:1
|vpiParameter:
\_parameter: (WB_UNITS_WIDTH), line:187
|vpiName:WB_UNITS_WIDTH
|INT:32
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiModule:
\_module: work@load_store_unit (load_store_unit_block), file:third_party/cores/taiga/core/taiga.sv, line:183, parent:cpu
|vpiDefName:work@load_store_unit
|vpiName:load_store_unit_block
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block
|vpiPort:
\_port: (clk), line:27, parent:load_store_unit_block
|vpiName:clk
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (clk), line:183
|vpiName:clk
|vpiActual:
\_logic_net: (clk), line:27, parent:cpu
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (clk), line:27, parent:load_store_unit_block
|vpiName:clk
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.clk
|vpiNetType:36
|vpiPort:
\_port: (rst), line:28, parent:load_store_unit_block
|vpiName:rst
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (rst), line:183
|vpiName:rst
|vpiActual:
\_logic_net: (rst), line:28, parent:cpu
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (rst), line:28, parent:load_store_unit_block
|vpiName:rst
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.rst
|vpiNetType:36
|vpiPort:
\_port: (ls_inputs), line:29, parent:load_store_unit_block
|vpiName:ls_inputs
|vpiDirection:1
|vpiTypedef:
\_struct_typespec: (load_store_inputs_t), line:369
|vpiHighConn:
\_ref_obj: (ls_inputs), line:183
|vpiName:ls_inputs
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (ls_inputs), line:29, parent:load_store_unit_block
|vpiName:ls_inputs
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.ls_inputs
|vpiPort:
\_port: (issue), line:30, parent:load_store_unit_block
|vpiName:issue
|vpiDirection:5
|vpiHighConn:
\_ref_obj: (issue), line:183
|vpiName:issue
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_modport: (unit)
|vpiName:unit
|vpiIODecl:
\_io_decl: (ready)
|vpiName:ready
|vpiDirection:2
|vpiExpr:
\_logic_net: (ready), line:58
|vpiName:ready
|vpiNetType:36
|vpiIODecl:
\_io_decl: (possible_issue)
|vpiName:possible_issue
|vpiDirection:1
|vpiExpr:
\_logic_net: (possible_issue), line:53
|vpiName:possible_issue
|vpiNetType:36
|vpiIODecl:
\_io_decl: (new_request)
|vpiName:new_request
|vpiDirection:1
|vpiExpr:
\_logic_net: (new_request), line:54
|vpiName:new_request
|vpiNetType:36
|vpiIODecl:
\_io_decl: (new_request_r)
|vpiName:new_request_r
|vpiDirection:1
|vpiExpr:
\_logic_net: (new_request_r), line:55
|vpiName:new_request_r
|vpiNetType:36
|vpiIODecl:
\_io_decl: (instruction_id)
|vpiName:instruction_id
|vpiDirection:1
|vpiInterface:
\_interface: work@unit_issue_interface (issue), file:third_party/cores/taiga/core/taiga.sv, line:183
|vpiDefName:work@unit_issue_interface
|vpiName:issue
|vpiModport:
\_modport: (decode)
|vpiName:decode
|vpiIODecl:
\_io_decl: (ready)
|vpiName:ready
|vpiDirection:1
|vpiExpr:
\_logic_net: (ready), line:58
|vpiIODecl:
\_io_decl: (possible_issue)
|vpiName:possible_issue
|vpiDirection:2
|vpiExpr:
\_logic_net: (possible_issue), line:53
|vpiIODecl:
\_io_decl: (new_request)
|vpiName:new_request
|vpiDirection:2
|vpiExpr:
\_logic_net: (new_request), line:54
|vpiIODecl:
\_io_decl: (new_request_r)
|vpiName:new_request_r
|vpiDirection:2
|vpiExpr:
\_logic_net: (new_request_r), line:55
|vpiIODecl:
\_io_decl: (instruction_id)
|vpiName:instruction_id
|vpiDirection:2
|vpiInterface:
\_interface: work@unit_issue_interface (issue), file:third_party/cores/taiga/core/taiga.sv, line:183
|vpiModport:
\_modport: (unit)
|vpiPort:
\_port: (dcache_on), line:32, parent:load_store_unit_block
|vpiName:dcache_on
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (dcache_on), line:183
|vpiName:dcache_on
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (dcache_on), line:32, parent:load_store_unit_block
|vpiName:dcache_on
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.dcache_on
|vpiNetType:36
|vpiPort:
\_port: (clear_reservation), line:33, parent:load_store_unit_block
|vpiName:clear_reservation
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (clear_reservation), line:183
|vpiName:clear_reservation
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (clear_reservation), line:33, parent:load_store_unit_block
|vpiName:clear_reservation
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.clear_reservation
|vpiNetType:36
|vpiPort:
\_port: (tlb), line:34, parent:load_store_unit_block
|vpiName:tlb
|vpiDirection:5
|vpiHighConn:
\_ref_obj: (tlb), line:183
|vpiName:tlb
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_modport: (mem)
|vpiName:mem
|vpiIODecl:
\_io_decl: (new_request)
|vpiName:new_request
|vpiDirection:2
|vpiExpr:
\_logic_net: (new_request), line:54
|vpiIODecl:
\_io_decl: (virtual_address)
|vpiName:virtual_address
|vpiDirection:2
|vpiExpr:
\_logic_net: (virtual_address), line:194
|vpiName:virtual_address
|vpiNetType:36
|vpiRange:
\_range: , line:194
|vpiLeftRange:
\_constant: , line:194
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:194
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (rnw)
|vpiName:rnw
|vpiDirection:2
|vpiExpr:
\_logic_net: (rnw), line:196
|vpiName:rnw
|vpiNetType:36
|vpiIODecl:
\_io_decl: (execute)
|vpiName:execute
|vpiDirection:2
|vpiExpr:
\_logic_net: (execute), line:197
|vpiName:execute
|vpiNetType:36
|vpiIODecl:
\_io_decl: (complete)
|vpiName:complete
|vpiDirection:1
|vpiExpr:
\_logic_net: (complete), line:199
|vpiName:complete
|vpiNetType:36
|vpiIODecl:
\_io_decl: (physical_address)
|vpiName:physical_address
|vpiDirection:1
|vpiExpr:
\_logic_net: (physical_address), line:200
|vpiName:physical_address
|vpiNetType:36
|vpiRange:
\_range: , line:200
|vpiLeftRange:
\_constant: , line:200
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:200
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiInterface:
\_interface: work@tlb_interface (tlb), file:third_party/cores/taiga/core/taiga.sv, line:183
|vpiDefName:work@tlb_interface
|vpiName:tlb
|vpiModport:
\_modport: (fence)
|vpiName:fence
|vpiIODecl:
\_io_decl: (flush)
|vpiName:flush
|vpiDirection:2
|vpiExpr:
\_logic_net: (flush), line:202
|vpiName:flush
|vpiNetType:36
|vpiIODecl:
\_io_decl: (flush_complete)
|vpiName:flush_complete
|vpiDirection:1
|vpiExpr:
\_logic_net: (flush_complete), line:203
|vpiName:flush_complete
|vpiNetType:36
|vpiInterface:
\_interface: work@tlb_interface (tlb), file:third_party/cores/taiga/core/taiga.sv, line:183
|vpiModport:
\_modport: (mem)
|vpiModport:
\_modport: (tlb)
|vpiName:tlb
|vpiIODecl:
\_io_decl: (virtual_address)
|vpiName:virtual_address
|vpiDirection:1
|vpiExpr:
\_logic_net: (virtual_address), line:194
|vpiIODecl:
\_io_decl: (new_request)
|vpiName:new_request
|vpiDirection:1
|vpiExpr:
\_logic_net: (new_request), line:54
|vpiIODecl:
\_io_decl: (flush)
|vpiName:flush
|vpiDirection:1
|vpiExpr:
\_logic_net: (flush), line:202
|vpiIODecl:
\_io_decl: (rnw)
|vpiName:rnw
|vpiDirection:1
|vpiExpr:
\_logic_net: (rnw), line:196
|vpiIODecl:
\_io_decl: (execute)
|vpiName:execute
|vpiDirection:1
|vpiExpr:
\_logic_net: (execute), line:197
|vpiIODecl:
\_io_decl: (complete)
|vpiName:complete
|vpiDirection:2
|vpiExpr:
\_logic_net: (complete), line:199
|vpiIODecl:
\_io_decl: (physical_address)
|vpiName:physical_address
|vpiDirection:2
|vpiExpr:
\_logic_net: (physical_address), line:200
|vpiIODecl:
\_io_decl: (flush_complete)
|vpiName:flush_complete
|vpiDirection:2
|vpiExpr:
\_logic_net: (flush_complete), line:203
|vpiInterface:
\_interface: work@tlb_interface (tlb), file:third_party/cores/taiga/core/taiga.sv, line:183
|vpiPort:
\_port: (gc_fetch_flush), line:36, parent:load_store_unit_block
|vpiName:gc_fetch_flush
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (gc_fetch_flush), line:183
|vpiName:gc_fetch_flush
|vpiActual:
\_logic_net: (gc_fetch_flush), line:95, parent:cpu
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (gc_fetch_flush), line:36, parent:load_store_unit_block
|vpiName:gc_fetch_flush
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.gc_fetch_flush
|vpiNetType:36
|vpiPort:
\_port: (gc_issue_flush), line:37, parent:load_store_unit_block
|vpiName:gc_issue_flush
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (gc_issue_flush), line:183
|vpiName:gc_issue_flush
|vpiActual:
\_logic_net: (gc_issue_flush), line:94, parent:cpu
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (gc_issue_flush), line:37, parent:load_store_unit_block
|vpiName:gc_issue_flush
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.gc_issue_flush
|vpiNetType:36
|vpiPort:
\_port: (l1_request), line:39, parent:load_store_unit_block
|vpiName:l1_request
|vpiDirection:5
|vpiHighConn:
\_ref_obj: (l1_request), line:183
|vpiName:l1_request
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_modport: (master)
|vpiName:master
|vpiIODecl:
\_io_decl: (addr)
|vpiName:addr
|vpiDirection:2
|vpiExpr:
\_logic_net: (addr), line:123
|vpiName:addr
|vpiNetType:36
|vpiRange:
\_range: , line:123
|vpiLeftRange:
\_constant: , line:123
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:123
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (data)
|vpiName:data
|vpiDirection:2
|vpiExpr:
\_logic_net: (data), line:124
|vpiName:data
|vpiNetType:36
|vpiRange:
\_range: , line:124
|vpiLeftRange:
\_constant: , line:124
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:124
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (rnw)
|vpiName:rnw
|vpiDirection:2
|vpiExpr:
\_logic_net: (rnw), line:196
|vpiIODecl:
\_io_decl: (be)
|vpiName:be
|vpiDirection:2
|vpiExpr:
\_logic_net: (be), line:126
|vpiName:be
|vpiNetType:36
|vpiRange:
\_range: , line:126
|vpiLeftRange:
\_constant: , line:126
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiRightRange:
\_constant: , line:126
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (size)
|vpiName:size
|vpiDirection:2
|vpiExpr:
\_logic_net: (size), line:127
|vpiName:size
|vpiNetType:36
|vpiRange:
\_range: , line:127
|vpiLeftRange:
\_constant: , line:127
|vpiConstType:7
|vpiDecompile:4
|vpiSize:32
|INT:4
|vpiRightRange:
\_constant: , line:127
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (is_amo)
|vpiName:is_amo
|vpiDirection:2
|vpiExpr:
\_logic_net: (is_amo), line:128
|vpiName:is_amo
|vpiNetType:36
|vpiIODecl:
\_io_decl: (amo)
|vpiName:amo
|vpiDirection:2
|vpiExpr:
\_logic_net: (amo), line:129
|vpiName:amo
|vpiNetType:36
|vpiRange:
\_range: , line:129
|vpiLeftRange:
\_constant: , line:129
|vpiConstType:7
|vpiDecompile:4
|vpiSize:32
|INT:4
|vpiRightRange:
\_constant: , line:129
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (request)
|vpiName:request
|vpiDirection:2
|vpiExpr:
\_logic_net: (request), line:131
|vpiName:request
|vpiNetType:36
|vpiIODecl:
\_io_decl: (ack)
|vpiName:ack
|vpiDirection:1
|vpiExpr:
\_logic_net: (ack), line:132
|vpiName:ack
|vpiNetType:36
|vpiInterface:
\_interface: work@l1_arbiter_request_interface (l1_request), file:third_party/cores/taiga/core/taiga.sv, line:183
|vpiDefName:work@l1_arbiter_request_interface
|vpiName:l1_request
|vpiModport:
\_modport: (master)
|vpiModport:
\_modport: (slave)
|vpiName:slave
|vpiIODecl:
\_io_decl: (addr)
|vpiName:addr
|vpiDirection:1
|vpiExpr:
\_logic_net: (addr), line:123
|vpiIODecl:
\_io_decl: (data)
|vpiName:data
|vpiDirection:1
|vpiExpr:
\_logic_net: (data), line:124
|vpiIODecl:
\_io_decl: (rnw)
|vpiName:rnw
|vpiDirection:1
|vpiExpr:
\_logic_net: (rnw), line:196
|vpiIODecl:
\_io_decl: (be)
|vpiName:be
|vpiDirection:1
|vpiExpr:
\_logic_net: (be), line:126
|vpiIODecl:
\_io_decl: (size)
|vpiName:size
|vpiDirection:1
|vpiExpr:
\_logic_net: (size), line:127
|vpiIODecl:
\_io_decl: (is_amo)
|vpiName:is_amo
|vpiDirection:1
|vpiExpr:
\_logic_net: (is_amo), line:128
|vpiIODecl:
\_io_decl: (amo)
|vpiName:amo
|vpiDirection:1
|vpiExpr:
\_logic_net: (amo), line:129
|vpiIODecl:
\_io_decl: (request)
|vpiName:request
|vpiDirection:1
|vpiExpr:
\_logic_net: (request), line:131
|vpiIODecl:
\_io_decl: (ack)
|vpiName:ack
|vpiDirection:2
|vpiExpr:
\_logic_net: (ack), line:132
|vpiInterface:
\_interface: work@l1_arbiter_request_interface (l1_request), file:third_party/cores/taiga/core/taiga.sv, line:183
|vpiPort:
\_port: (l1_response), line:40, parent:load_store_unit_block
|vpiName:l1_response
|vpiDirection:5
|vpiHighConn:
\_ref_obj: (l1_response), line:183
|vpiName:l1_response
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_modport: (master)
|vpiName:master
|vpiIODecl:
\_io_decl: (inv_addr)
|vpiName:inv_addr
|vpiDirection:1
|vpiExpr:
\_logic_net: (inv_addr), line:149
|vpiName:inv_addr
|vpiNetType:36
|vpiRange:
\_range: , line:149
|vpiLeftRange:
\_constant: , line:149
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:149
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiIODecl:
\_io_decl: (inv_valid)
|vpiName:inv_valid
|vpiDirection:1
|vpiExpr:
\_logic_net: (inv_valid), line:150
|vpiName:inv_valid
|vpiNetType:36
|vpiIODecl:
\_io_decl: (data)
|vpiName:data
|vpiDirection:1
|vpiExpr:
\_logic_net: (data), line:124
|vpiIODecl:
\_io_decl: (data_valid)
|vpiName:data_valid
|vpiDirection:1
|vpiExpr:
\_logic_net: (data_valid), line:153
|vpiName:data_valid
|vpiNetType:36
|vpiIODecl:
\_io_decl: (inv_ack)
|vpiName:inv_ack
|vpiDirection:2
|vpiExpr:
\_logic_net: (inv_ack), line:151
|vpiName:inv_ack
|vpiNetType:36
|vpiInterface:
\_interface: work@l1_arbiter_return_interface (l1_response), file:third_party/cores/taiga/core/taiga.sv, line:183
|vpiDefName:work@l1_arbiter_return_interface
|vpiName:l1_response
|vpiModport:
\_modport: (master)
|vpiModport:
\_modport: (slave)
|vpiName:slave
|vpiIODecl:
\_io_decl: (inv_addr)
|vpiName:inv_addr
|vpiDirection:2
|vpiExpr:
\_logic_net: (inv_addr), line:149
|vpiIODecl:
\_io_decl: (inv_valid)
|vpiName:inv_valid
|vpiDirection:2
|vpiExpr:
\_logic_net: (inv_valid), line:150
|vpiIODecl:
\_io_decl: (data)
|vpiName:data
|vpiDirection:2
|vpiExpr:
\_logic_net: (data), line:124
|vpiIODecl:
\_io_decl: (data_valid)
|vpiName:data_valid
|vpiDirection:2
|vpiExpr:
\_logic_net: (data_valid), line:153
|vpiIODecl:
\_io_decl: (inv_ack)
|vpiName:inv_ack
|vpiDirection:1
|vpiExpr:
\_logic_net: (inv_ack), line:151
|vpiInterface:
\_interface: work@l1_arbiter_return_interface (l1_response), file:third_party/cores/taiga/core/taiga.sv, line:183
|vpiPort:
\_port: (sc_complete), line:41, parent:load_store_unit_block
|vpiName:sc_complete
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (sc_complete), line:183
|vpiName:sc_complete
|vpiActual:
\_logic_net: (sc_complete), line:47, parent:cpu
|vpiName:sc_complete
|vpiFullName:work@taiga_wrapper.cpu.sc_complete
|vpiNetType:36
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (sc_complete), line:41, parent:load_store_unit_block
|vpiName:sc_complete
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.sc_complete
|vpiPort:
\_port: (sc_success), line:42, parent:load_store_unit_block
|vpiName:sc_success
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (sc_success), line:183
|vpiName:sc_success
|vpiActual:
\_logic_net: (sc_success), line:48, parent:cpu
|vpiName:sc_success
|vpiFullName:work@taiga_wrapper.cpu.sc_success
|vpiNetType:36
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (sc_success), line:42, parent:load_store_unit_block
|vpiName:sc_success
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.sc_success
|vpiPort:
\_port: (m_axi), line:44, parent:load_store_unit_block
|vpiName:m_axi
|vpiDirection:5
|vpiHighConn:
\_ref_obj: (m_axi), line:183
|vpiName:m_axi
|vpiActual:
\_interface: work@axi_interface (m_axi), file:third_party/cores/taiga/examples/zedboard/taiga_wrapper.sv, line:233
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_modport: (master)
|vpiName:master
|vpiIODecl:
\_io_decl: (arready)
|vpiName:arready
|vpiDirection:1
|vpiExpr:
\_logic_net: (arready), line:29
|vpiName:arready
|vpiNetType:36
|vpiIODecl:
\_io_decl: (rvalid)
|vpiName:rvalid
|vpiDirection:1
|vpiExpr:
\_logic_net: (rvalid), line:40
|vpiName:rvalid
|vpiNetType:36
|vpiIODecl:
\_io_decl: (rdata)
|vpiName:rdata
|vpiDirection:1
|vpiExpr:
\_logic_net: (rdata), line:41
|vpiName:rdata
|vpiNetType:36
|vpiRange:
\_range: , line:41
|vpiLeftRange:
\_constant: , line:41
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiRightRange:
\_constant: , line:41
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (rresp)
|vpiName:rresp
|vpiDirection:1
|vpiExpr:
\_logic_net: (rresp), line:42
|vpiName:rresp
|vpiNetType:36
|vpiRange:
\_range: , line:42
|vpiLeftRange:
\_constant: , line:42
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:42
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (rlast)
|vpiName:rlast
|vpiDirection:1
|vpiExpr:
\_logic_net: (rlast), line:43
|vpiName:rlast
|vpiNetType:36
|vpiIODecl:
\_io_decl: (rid)
|vpiName:rid
|vpiDirection:1
|vpiExpr:
\_logic_net: (rid), line:44
|vpiName:rid
|vpiNetType:36
|vpiRange:
\_range: , line:44
|vpiLeftRange:
\_constant: , line:44
|vpiConstType:7
|vpiDecompile:5
|vpiSize:32
|INT:5
|vpiRightRange:
\_constant: , line:44
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (awready)
|vpiName:awready
|vpiDirection:1
|vpiExpr:
\_logic_net: (awready), line:48
|vpiName:awready
|vpiNetType:36
|vpiIODecl:
\_io_decl: (wready)
|vpiName:wready
|vpiDirection:1
|vpiExpr:
\_logic_net: (wready), line:58
|vpiName:wready
|vpiNetType:36
|vpiIODecl:
\_io_decl: (bvalid)
|vpiName:bvalid
|vpiDirection:1
|vpiExpr:
\_logic_net: (bvalid), line:66
|vpiName:bvalid
|vpiNetType:36
|vpiIODecl:
\_io_decl: (bresp)
|vpiName:bresp
|vpiDirection:1
|vpiExpr:
\_logic_net: (bresp), line:67
|vpiName:bresp
|vpiNetType:36
|vpiRange:
\_range: , line:67
|vpiLeftRange:
\_constant: , line:67
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:67
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (bid)
|vpiName:bid
|vpiDirection:1
|vpiExpr:
\_logic_net: (bid), line:68
|vpiName:bid
|vpiNetType:36
|vpiRange:
\_range: , line:68
|vpiLeftRange:
\_constant: , line:68
|vpiConstType:7
|vpiDecompile:5
|vpiSize:32
|INT:5
|vpiRightRange:
\_constant: , line:68
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (arvalid)
|vpiName:arvalid
|vpiDirection:2
|vpiExpr:
\_logic_net: (arvalid), line:30
|vpiName:arvalid
|vpiNetType:36
|vpiIODecl:
\_io_decl: (araddr)
|vpiName:araddr
|vpiDirection:2
|vpiExpr:
\_logic_net: (araddr), line:31
|vpiName:araddr
|vpiNetType:36
|vpiRange:
\_range: , line:31
|vpiLeftRange:
\_constant: , line:31
|vpiConstType:7
|vpiDecompile:18446744073709551615
|vpiSize:32
|INT:-1
|vpiRightRange:
\_constant: , line:31
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (arlen)
|vpiName:arlen
|vpiDirection:2
|vpiExpr:
\_logic_net: (arlen), line:32
|vpiName:arlen
|vpiNetType:36
|vpiRange:
\_range: , line:32
|vpiLeftRange:
\_constant: , line:32
|vpiConstType:7
|vpiDecompile:7
|vpiSize:32
|INT:7
|vpiRightRange:
\_constant: , line:32
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (arsize)
|vpiName:arsize
|vpiDirection:2
|vpiExpr:
\_logic_net: (arsize), line:33
|vpiName:arsize
|vpiNetType:36
|vpiRange:
\_range: , line:33
|vpiLeftRange:
\_constant: , line:33
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiRightRange:
\_constant: , line:33
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (arburst)
|vpiName:arburst
|vpiDirection:2
|vpiExpr:
\_logic_net: (arburst), line:34
|vpiName:arburst
|vpiNetType:36
|vpiRange:
\_range: , line:34
|vpiLeftRange:
\_constant: , line:34
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:34
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (arcache)
|vpiName:arcache
|vpiDirection:2
|vpiExpr:
\_logic_net: (arcache), line:35
|vpiName:arcache
|vpiNetType:36
|vpiRange:
\_range: , line:35
|vpiLeftRange:
\_constant: , line:35
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiRightRange:
\_constant: , line:35
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (arid)
|vpiName:arid
|vpiDirection:2
|vpiExpr:
\_logic_net: (arid), line:36
|vpiName:arid
|vpiNetType:36
|vpiRange:
\_range: , line:36
|vpiLeftRange:
\_constant: , line:36
|vpiConstType:7
|vpiDecompile:5
|vpiSize:32
|INT:5
|vpiRightRange:
\_constant: , line:36
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (rready)
|vpiName:rready
|vpiDirection:2
|vpiExpr:
\_logic_net: (rready), line:39
|vpiName:rready
|vpiNetType:36
|vpiIODecl:
\_io_decl: (awvalid)
|vpiName:awvalid
|vpiDirection:2
|vpiExpr:
\_logic_net: (awvalid), line:49
|vpiName:awvalid
|vpiNetType:36
|vpiIODecl:
\_io_decl: (awaddr)
|vpiName:awaddr
|vpiDirection:2
|vpiExpr:
\_logic_net: (awaddr), line:50
|vpiName:awaddr
|vpiNetType:36
|vpiRange:
\_range: , line:50
|vpiLeftRange:
\_constant: , line:50
|vpiConstType:7
|vpiDecompile:18446744073709551615
|vpiSize:32
|INT:-1
|vpiRightRange:
\_constant: , line:50
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (awlen)
|vpiName:awlen
|vpiDirection:2
|vpiExpr:
\_logic_net: (awlen), line:51
|vpiName:awlen
|vpiNetType:36
|vpiRange:
\_range: , line:51
|vpiLeftRange:
\_constant: , line:51
|vpiConstType:7
|vpiDecompile:7
|vpiSize:32
|INT:7
|vpiRightRange:
\_constant: , line:51
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (awsize)
|vpiName:awsize
|vpiDirection:2
|vpiExpr:
\_logic_net: (awsize), line:52
|vpiName:awsize
|vpiNetType:36
|vpiRange:
\_range: , line:52
|vpiLeftRange:
\_constant: , line:52
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiRightRange:
\_constant: , line:52
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (awburst)
|vpiName:awburst
|vpiDirection:2
|vpiExpr:
\_logic_net: (awburst), line:53
|vpiName:awburst
|vpiNetType:36
|vpiRange:
\_range: , line:53
|vpiLeftRange:
\_constant: , line:53
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:53
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (awcache)
|vpiName:awcache
|vpiDirection:2
|vpiExpr:
\_logic_net: (awcache), line:54
|vpiName:awcache
|vpiNetType:36
|vpiRange:
\_range: , line:54
|vpiLeftRange:
\_constant: , line:54
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiRightRange:
\_constant: , line:54
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (awid)
|vpiName:awid
|vpiDirection:2
|vpiExpr:
\_logic_net: (awid), line:55
|vpiName:awid
|vpiNetType:36
|vpiRange:
\_range: , line:55
|vpiLeftRange:
\_constant: , line:55
|vpiConstType:7
|vpiDecompile:5
|vpiSize:32
|INT:5
|vpiRightRange:
\_constant: , line:55
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (wvalid)
|vpiName:wvalid
|vpiDirection:2
|vpiExpr:
\_logic_net: (wvalid), line:59
|vpiName:wvalid
|vpiNetType:36
|vpiIODecl:
\_io_decl: (wdata)
|vpiName:wdata
|vpiDirection:2
|vpiExpr:
\_logic_net: (wdata), line:60
|vpiName:wdata
|vpiNetType:36
|vpiRange:
\_range: , line:60
|vpiLeftRange:
\_constant: , line:60
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiRightRange:
\_constant: , line:60
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (wstrb)
|vpiName:wstrb
|vpiDirection:2
|vpiExpr:
\_logic_net: (wstrb), line:61
|vpiName:wstrb
|vpiNetType:36
|vpiRange:
\_range: , line:61
|vpiLeftRange:
\_constant: , line:61
|vpiConstType:7
|vpiDecompile:18446744073709551615
|vpiSize:32
|INT:-1
|vpiRightRange:
\_constant: , line:61
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (wlast)
|vpiName:wlast
|vpiDirection:2
|vpiExpr:
\_logic_net: (wlast), line:62
|vpiName:wlast
|vpiNetType:36
|vpiIODecl:
\_io_decl: (bready)
|vpiName:bready
|vpiDirection:2
|vpiExpr:
\_logic_net: (bready), line:65
|vpiName:bready
|vpiNetType:36
|vpiInterface:
\_interface: work@axi_interface (m_axi), file:third_party/cores/taiga/core/taiga.sv, line:183
|vpiDefName:work@axi_interface
|vpiName:m_axi
|vpiModport:
\_modport: (master)
|vpiModport:
\_modport: (slave)
|vpiName:slave
|vpiIODecl:
\_io_decl: (arvalid)
|vpiName:arvalid
|vpiDirection:1
|vpiExpr:
\_logic_net: (arvalid), line:30
|vpiIODecl:
\_io_decl: (araddr)
|vpiName:araddr
|vpiDirection:1
|vpiExpr:
\_logic_net: (araddr), line:31
|vpiIODecl:
\_io_decl: (arlen)
|vpiName:arlen
|vpiDirection:1
|vpiExpr:
\_logic_net: (arlen), line:32
|vpiIODecl:
\_io_decl: (arsize)
|vpiName:arsize
|vpiDirection:1
|vpiExpr:
\_logic_net: (arsize), line:33
|vpiIODecl:
\_io_decl: (arburst)
|vpiName:arburst
|vpiDirection:1
|vpiExpr:
\_logic_net: (arburst), line:34
|vpiIODecl:
\_io_decl: (arcache)
|vpiName:arcache
|vpiDirection:1
|vpiExpr:
\_logic_net: (arcache), line:35
|vpiIODecl:
\_io_decl: (rready)
|vpiName:rready
|vpiDirection:1
|vpiExpr:
\_logic_net: (rready), line:39
|vpiIODecl:
\_io_decl: (awvalid)
|vpiName:awvalid
|vpiDirection:1
|vpiExpr:
\_logic_net: (awvalid), line:49
|vpiIODecl:
\_io_decl: (awaddr)
|vpiName:awaddr
|vpiDirection:1
|vpiExpr:
\_logic_net: (awaddr), line:50
|vpiIODecl:
\_io_decl: (awlen)
|vpiName:awlen
|vpiDirection:1
|vpiExpr:
\_logic_net: (awlen), line:51
|vpiIODecl:
\_io_decl: (awsize)
|vpiName:awsize
|vpiDirection:1
|vpiExpr:
\_logic_net: (awsize), line:52
|vpiIODecl:
\_io_decl: (awburst)
|vpiName:awburst
|vpiDirection:1
|vpiExpr:
\_logic_net: (awburst), line:53
|vpiIODecl:
\_io_decl: (awcache)
|vpiName:awcache
|vpiDirection:1
|vpiExpr:
\_logic_net: (awcache), line:54
|vpiIODecl:
\_io_decl: (arid)
|vpiName:arid
|vpiDirection:1
|vpiExpr:
\_logic_net: (arid), line:36
|vpiIODecl:
\_io_decl: (wvalid)
|vpiName:wvalid
|vpiDirection:1
|vpiExpr:
\_logic_net: (wvalid), line:59
|vpiIODecl:
\_io_decl: (wdata)
|vpiName:wdata
|vpiDirection:1
|vpiExpr:
\_logic_net: (wdata), line:60
|vpiIODecl:
\_io_decl: (wstrb)
|vpiName:wstrb
|vpiDirection:1
|vpiExpr:
\_logic_net: (wstrb), line:61
|vpiIODecl:
\_io_decl: (wlast)
|vpiName:wlast
|vpiDirection:1
|vpiExpr:
\_logic_net: (wlast), line:62
|vpiIODecl:
\_io_decl: (awid)
|vpiName:awid
|vpiDirection:1
|vpiExpr:
\_logic_net: (awid), line:55
|vpiIODecl:
\_io_decl: (bready)
|vpiName:bready
|vpiDirection:1
|vpiExpr:
\_logic_net: (bready), line:65
|vpiIODecl:
\_io_decl: (arready)
|vpiName:arready
|vpiDirection:2
|vpiExpr:
\_logic_net: (arready), line:29
|vpiIODecl:
\_io_decl: (rvalid)
|vpiName:rvalid
|vpiDirection:2
|vpiExpr:
\_logic_net: (rvalid), line:40
|vpiIODecl:
\_io_decl: (rdata)
|vpiName:rdata
|vpiDirection:2
|vpiExpr:
\_logic_net: (rdata), line:41
|vpiIODecl:
\_io_decl: (rresp)
|vpiName:rresp
|vpiDirection:2
|vpiExpr:
\_logic_net: (rresp), line:42
|vpiIODecl:
\_io_decl: (rlast)
|vpiName:rlast
|vpiDirection:2
|vpiExpr:
\_logic_net: (rlast), line:43
|vpiIODecl:
\_io_decl: (rid)
|vpiName:rid
|vpiDirection:2
|vpiExpr:
\_logic_net: (rid), line:44
|vpiIODecl:
\_io_decl: (awready)
|vpiName:awready
|vpiDirection:2
|vpiExpr:
\_logic_net: (awready), line:48
|vpiIODecl:
\_io_decl: (wready)
|vpiName:wready
|vpiDirection:2
|vpiExpr:
\_logic_net: (wready), line:58
|vpiIODecl:
\_io_decl: (bvalid)
|vpiName:bvalid
|vpiDirection:2
|vpiExpr:
\_logic_net: (bvalid), line:66
|vpiIODecl:
\_io_decl: (bresp)
|vpiName:bresp
|vpiDirection:2
|vpiExpr:
\_logic_net: (bresp), line:67
|vpiIODecl:
\_io_decl: (bid)
|vpiName:bid
|vpiDirection:2
|vpiExpr:
\_logic_net: (bid), line:68
|vpiInterface:
\_interface: work@axi_interface (m_axi), file:third_party/cores/taiga/core/taiga.sv, line:183
|vpiPort:
\_port: (m_avalon), line:45, parent:load_store_unit_block
|vpiName:m_avalon
|vpiDirection:5
|vpiHighConn:
\_ref_obj: (m_avalon), line:183
|vpiName:m_avalon
|vpiActual:
\_interface: work@avalon_interface (m_avalon), file:third_party/cores/taiga/examples/zedboard/taiga_wrapper.sv, line:233
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_modport: (master)
|vpiName:master
|vpiIODecl:
\_io_decl: (readdata)
|vpiName:readdata
|vpiDirection:1
|vpiExpr:
\_logic_net: (readdata), line:92
|vpiName:readdata
|vpiNetType:36
|vpiRange:
\_range: , line:92
|vpiLeftRange:
\_constant: , line:92
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:92
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (waitrequest)
|vpiName:waitrequest
|vpiDirection:1
|vpiExpr:
\_logic_net: (waitrequest), line:94
|vpiName:waitrequest
|vpiNetType:36
|vpiIODecl:
\_io_decl: (readdatavalid)
|vpiName:readdatavalid
|vpiDirection:1
|vpiExpr:
\_logic_net: (readdatavalid), line:95
|vpiName:readdatavalid
|vpiNetType:36
|vpiIODecl:
\_io_decl: (writeresponsevalid)
|vpiName:writeresponsevalid
|vpiDirection:1
|vpiExpr:
\_logic_net: (writeresponsevalid), line:96
|vpiName:writeresponsevalid
|vpiNetType:36
|vpiIODecl:
\_io_decl: (addr)
|vpiName:addr
|vpiDirection:2
|vpiExpr:
\_logic_net: (addr), line:123
|vpiIODecl:
\_io_decl: (read)
|vpiName:read
|vpiDirection:2
|vpiExpr:
\_logic_net: (read), line:89
|vpiName:read
|vpiNetType:36
|vpiIODecl:
\_io_decl: (write)
|vpiName:write
|vpiDirection:2
|vpiExpr:
\_logic_net: (write), line:90
|vpiName:write
|vpiNetType:36
|vpiIODecl:
\_io_decl: (byteenable)
|vpiName:byteenable
|vpiDirection:2
|vpiExpr:
\_logic_net: (byteenable), line:91
|vpiName:byteenable
|vpiNetType:36
|vpiRange:
\_range: , line:91
|vpiLeftRange:
\_constant: , line:91
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiRightRange:
\_constant: , line:91
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (writedata)
|vpiName:writedata
|vpiDirection:2
|vpiExpr:
\_logic_net: (writedata), line:93
|vpiName:writedata
|vpiNetType:36
|vpiRange:
\_range: , line:93
|vpiLeftRange:
\_constant: , line:93
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:93
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiInterface:
\_interface: work@avalon_interface (m_avalon), file:third_party/cores/taiga/core/taiga.sv, line:183
|vpiDefName:work@avalon_interface
|vpiName:m_avalon
|vpiModport:
\_modport: (master)
|vpiModport:
\_modport: (slave)
|vpiName:slave
|vpiIODecl:
\_io_decl: (readdata)
|vpiName:readdata
|vpiDirection:2
|vpiExpr:
\_logic_net: (readdata), line:92
|vpiIODecl:
\_io_decl: (waitrequest)
|vpiName:waitrequest
|vpiDirection:2
|vpiExpr:
\_logic_net: (waitrequest), line:94
|vpiIODecl:
\_io_decl: (readdatavalid)
|vpiName:readdatavalid
|vpiDirection:2
|vpiExpr:
\_logic_net: (readdatavalid), line:95
|vpiIODecl:
\_io_decl: (writeresponsevalid)
|vpiName:writeresponsevalid
|vpiDirection:2
|vpiExpr:
\_logic_net: (writeresponsevalid), line:96
|vpiIODecl:
\_io_decl: (addr)
|vpiName:addr
|vpiDirection:1
|vpiExpr:
\_logic_net: (addr), line:123
|vpiIODecl:
\_io_decl: (read)
|vpiName:read
|vpiDirection:1
|vpiExpr:
\_logic_net: (read), line:89
|vpiIODecl:
\_io_decl: (write)
|vpiName:write
|vpiDirection:1
|vpiExpr:
\_logic_net: (write), line:90
|vpiIODecl:
\_io_decl: (byteenable)
|vpiName:byteenable
|vpiDirection:1
|vpiExpr:
\_logic_net: (byteenable), line:91
|vpiIODecl:
\_io_decl: (writedata)
|vpiName:writedata
|vpiDirection:1
|vpiExpr:
\_logic_net: (writedata), line:93
|vpiInterface:
\_interface: work@avalon_interface (m_avalon), file:third_party/cores/taiga/core/taiga.sv, line:183
|vpiPort:
\_port: (m_wishbone), line:46, parent:load_store_unit_block
|vpiName:m_wishbone
|vpiDirection:5
|vpiHighConn:
\_ref_obj: (m_wishbone), line:183
|vpiName:m_wishbone
|vpiActual:
\_interface: work@wishbone_interface (m_wishbone), file:third_party/cores/taiga/examples/zedboard/taiga_wrapper.sv, line:233
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_modport: (master)
|vpiName:master
|vpiIODecl:
\_io_decl: (readdata)
|vpiName:readdata
|vpiDirection:1
|vpiExpr:
\_logic_net: (readdata), line:92
|vpiIODecl:
\_io_decl: (ack)
|vpiName:ack
|vpiDirection:1
|vpiExpr:
\_logic_net: (ack), line:132
|vpiIODecl:
\_io_decl: (addr)
|vpiName:addr
|vpiDirection:2
|vpiExpr:
\_logic_net: (addr), line:123
|vpiIODecl:
\_io_decl: (we)
|vpiName:we
|vpiDirection:2
|vpiExpr:
\_logic_net: (we), line:107
|vpiName:we
|vpiNetType:36
|vpiIODecl:
\_io_decl: (sel)
|vpiName:sel
|vpiDirection:2
|vpiExpr:
\_logic_net: (sel), line:108
|vpiName:sel
|vpiNetType:36
|vpiRange:
\_range: , line:108
|vpiLeftRange:
\_constant: , line:108
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiRightRange:
\_constant: , line:108
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (writedata)
|vpiName:writedata
|vpiDirection:2
|vpiExpr:
\_logic_net: (writedata), line:93
|vpiIODecl:
\_io_decl: (stb)
|vpiName:stb
|vpiDirection:2
|vpiExpr:
\_logic_net: (stb), line:111
|vpiName:stb
|vpiNetType:36
|vpiIODecl:
\_io_decl: (cyc)
|vpiName:cyc
|vpiDirection:2
|vpiExpr:
\_logic_net: (cyc), line:112
|vpiName:cyc
|vpiNetType:36
|vpiInterface:
\_interface: work@wishbone_interface (m_wishbone), file:third_party/cores/taiga/core/taiga.sv, line:183
|vpiDefName:work@wishbone_interface
|vpiName:m_wishbone
|vpiModport:
\_modport: (master)
|vpiModport:
\_modport: (slave)
|vpiName:slave
|vpiIODecl:
\_io_decl: (readdata)
|vpiName:readdata
|vpiDirection:2
|vpiExpr:
\_logic_net: (readdata), line:92
|vpiIODecl:
\_io_decl: (ack)
|vpiName:ack
|vpiDirection:2
|vpiExpr:
\_logic_net: (ack), line:132
|vpiIODecl:
\_io_decl: (addr)
|vpiName:addr
|vpiDirection:1
|vpiExpr:
\_logic_net: (addr), line:123
|vpiIODecl:
\_io_decl: (we)
|vpiName:we
|vpiDirection:1
|vpiExpr:
\_logic_net: (we), line:107
|vpiIODecl:
\_io_decl: (sel)
|vpiName:sel
|vpiDirection:1
|vpiExpr:
\_logic_net: (sel), line:108
|vpiIODecl:
\_io_decl: (writedata)
|vpiName:writedata
|vpiDirection:1
|vpiExpr:
\_logic_net: (writedata), line:93
|vpiIODecl:
\_io_decl: (stb)
|vpiName:stb
|vpiDirection:1
|vpiExpr:
\_logic_net: (stb), line:111
|vpiIODecl:
\_io_decl: (cyc)
|vpiName:cyc
|vpiDirection:1
|vpiExpr:
\_logic_net: (cyc), line:112
|vpiInterface:
\_interface: work@wishbone_interface (m_wishbone), file:third_party/cores/taiga/core/taiga.sv, line:183
|vpiPort:
\_port: (data_bram), line:48, parent:load_store_unit_block
|vpiName:data_bram
|vpiDirection:5
|vpiHighConn:
\_ref_obj: (data_bram), line:183
|vpiName:data_bram
|vpiActual:
\_interface: work@local_memory_interface (data_bram), file:third_party/cores/taiga/examples/zedboard/taiga_wrapper.sv, line:233
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_modport: (master)
|vpiName:master
|vpiIODecl:
\_io_decl: (addr)
|vpiName:addr
|vpiDirection:2
|vpiExpr:
\_logic_net: (addr), line:123
|vpiIODecl:
\_io_decl: (en)
|vpiName:en
|vpiDirection:2
|vpiExpr:
\_logic_net: (en), line:26
|vpiName:en
|vpiNetType:36
|vpiIODecl:
\_io_decl: (be)
|vpiName:be
|vpiDirection:2
|vpiExpr:
\_logic_net: (be), line:126
|vpiIODecl:
\_io_decl: (data_in)
|vpiName:data_in
|vpiDirection:2
|vpiExpr:
\_logic_net: (data_in), line:28
|vpiName:data_in
|vpiNetType:36
|vpiRange:
\_range: , line:28
|vpiLeftRange:
\_constant: , line:28
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:28
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (data_out)
|vpiName:data_out
|vpiDirection:1
|vpiExpr:
\_logic_net: (data_out), line:29
|vpiName:data_out
|vpiNetType:36
|vpiRange:
\_range: , line:29
|vpiLeftRange:
\_constant: , line:29
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:29
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiInterface:
\_interface: work@local_memory_interface (data_bram), file:third_party/cores/taiga/core/taiga.sv, line:183
|vpiDefName:work@local_memory_interface
|vpiName:data_bram
|vpiModport:
\_modport: (master)
|vpiModport:
\_modport: (slave)
|vpiName:slave
|vpiIODecl:
\_io_decl: (addr)
|vpiName:addr
|vpiDirection:1
|vpiExpr:
\_logic_net: (addr), line:123
|vpiIODecl:
\_io_decl: (en)
|vpiName:en
|vpiDirection:1
|vpiExpr:
\_logic_net: (en), line:26
|vpiIODecl:
\_io_decl: (be)
|vpiName:be
|vpiDirection:1
|vpiExpr:
\_logic_net: (be), line:126
|vpiIODecl:
\_io_decl: (data_in)
|vpiName:data_in
|vpiDirection:1
|vpiExpr:
\_logic_net: (data_in), line:28
|vpiIODecl:
\_io_decl: (data_out)
|vpiName:data_out
|vpiDirection:2
|vpiExpr:
\_logic_net: (data_out), line:29
|vpiInterface:
\_interface: work@local_memory_interface (data_bram), file:third_party/cores/taiga/core/taiga.sv, line:183
|vpiPort:
\_port: (store_done_id), line:51, parent:load_store_unit_block
|vpiName:store_done_id
|vpiDirection:2
|vpiTypedef:
\_logic_typespec: (instruction_id_t), line:30
|vpiHighConn:
\_ref_obj: (store_done_id), line:183
|vpiName:store_done_id
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (store_done_id), line:51, parent:load_store_unit_block
|vpiName:store_done_id
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.store_done_id
|vpiPort:
\_port: (store_complete), line:52, parent:load_store_unit_block
|vpiName:store_complete
|vpiDirection:2
|vpiHighConn:
\_ref_obj: (store_complete), line:183
|vpiName:store_complete
|vpiActual:
\_logic_net: (store_complete), line:119, parent:cpu
|vpiName:store_complete
|vpiFullName:work@taiga_wrapper.cpu.store_complete
|vpiNetType:36
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (store_complete), line:52, parent:load_store_unit_block
|vpiName:store_complete
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.store_complete
|vpiNetType:36
|vpiPort:
\_port: (store_forwarding), line:54, parent:load_store_unit_block
|vpiName:store_forwarding
|vpiDirection:5
|vpiHighConn:
\_ref_obj: (store_forwarding), line:183
|vpiName:store_forwarding
|vpiActual:
\_interface: work@post_issue_forwarding_interface (store_forwarding), file:third_party/cores/taiga/core/taiga.sv, line:120
|vpiDefName:work@post_issue_forwarding_interface
|vpiName:store_forwarding
|vpiModport:
\_modport: (unit)
|vpiName:unit
|vpiIODecl:
\_io_decl: (data)
|vpiName:data
|vpiDirection:1
|vpiIODecl:
\_io_decl: (data_valid)
|vpiName:data_valid
|vpiDirection:1
|vpiIODecl:
\_io_decl: (id)
|vpiName:id
|vpiDirection:2
|vpiInterface:
\_interface: work@post_issue_forwarding_interface (store_forwarding), file:third_party/cores/taiga/core/taiga.sv, line:120
|vpiModport:
\_modport: (wb)
|vpiName:wb
|vpiIODecl:
\_io_decl: (data)
|vpiName:data
|vpiDirection:2
|vpiIODecl:
\_io_decl: (data_valid)
|vpiName:data_valid
|vpiDirection:2
|vpiIODecl:
\_io_decl: (id)
|vpiName:id
|vpiDirection:1
|vpiInterface:
\_interface: work@post_issue_forwarding_interface (store_forwarding), file:third_party/cores/taiga/core/taiga.sv, line:120
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_modport: (unit)
|vpiName:unit
|vpiIODecl:
\_io_decl: (data)
|vpiName:data
|vpiDirection:1
|vpiExpr:
\_logic_net: (data), line:124
|vpiIODecl:
\_io_decl: (data_valid)
|vpiName:data_valid
|vpiDirection:1
|vpiExpr:
\_logic_net: (data_valid), line:153
|vpiIODecl:
\_io_decl: (id)
|vpiName:id
|vpiDirection:2
|vpiInterface:
\_interface: work@post_issue_forwarding_interface (store_forwarding), file:third_party/cores/taiga/core/taiga.sv, line:183
|vpiDefName:work@post_issue_forwarding_interface
|vpiName:store_forwarding
|vpiModport:
\_modport: (unit)
|vpiModport:
\_modport: (wb)
|vpiName:wb
|vpiIODecl:
\_io_decl: (data)
|vpiName:data
|vpiDirection:2
|vpiExpr:
\_logic_net: (data), line:124
|vpiIODecl:
\_io_decl: (data_valid)
|vpiName:data_valid
|vpiDirection:2
|vpiExpr:
\_logic_net: (data_valid), line:153
|vpiIODecl:
\_io_decl: (id)
|vpiName:id
|vpiDirection:1
|vpiInterface:
\_interface: work@post_issue_forwarding_interface (store_forwarding), file:third_party/cores/taiga/core/taiga.sv, line:183
|vpiPort:
\_port: (csr_rd), line:56, parent:load_store_unit_block
|vpiName:csr_rd
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (csr_rd), line:183
|vpiName:csr_rd
|vpiActual:
\_logic_net: (csr_rd), line:103, parent:cpu
|vpiName:csr_rd
|vpiFullName:work@taiga_wrapper.cpu.csr_rd
|vpiNetType:36
|vpiRange:
\_range: , line:103
|vpiLeftRange:
\_constant: , line:103
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:103
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (csr_rd), line:56, parent:load_store_unit_block
|vpiName:csr_rd
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.csr_rd
|vpiNetType:36
|vpiRange:
\_range: , line:56
|vpiLeftRange:
\_constant: , line:56
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:56
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiPort:
\_port: (csr_id), line:57, parent:load_store_unit_block
|vpiName:csr_id
|vpiDirection:1
|vpiTypedef:
\_logic_typespec: (instruction_id_t), line:30
|vpiHighConn:
\_ref_obj: (csr_id), line:183
|vpiName:csr_id
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (csr_id), line:57, parent:load_store_unit_block
|vpiName:csr_id
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.csr_id
|vpiPort:
\_port: (csr_done), line:58, parent:load_store_unit_block
|vpiName:csr_done
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (csr_done), line:183
|vpiName:csr_done
|vpiActual:
\_logic_net: (csr_done), line:105, parent:cpu
|vpiName:csr_done
|vpiFullName:work@taiga_wrapper.cpu.csr_done
|vpiNetType:36
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (csr_done), line:58, parent:load_store_unit_block
|vpiName:csr_done
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.csr_done
|vpiNetType:36
|vpiPort:
\_port: (ls_exception), line:60, parent:load_store_unit_block
|vpiName:ls_exception
|vpiDirection:2
|vpiTypedef:
\_struct_typespec: (exception_packet_t), line:263
|vpiHighConn:
\_ref_obj: (ls_exception), line:183
|vpiName:ls_exception
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (ls_exception), line:60, parent:load_store_unit_block
|vpiName:ls_exception
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.ls_exception
|vpiPort:
\_port: (ls_exception_valid), line:61, parent:load_store_unit_block
|vpiName:ls_exception_valid
|vpiDirection:2
|vpiHighConn:
\_ref_obj: (ls_exception_valid), line:183
|vpiName:ls_exception_valid
|vpiActual:
\_logic_net: (ls_exception_valid), line:67, parent:cpu
|vpiName:ls_exception_valid
|vpiFullName:work@taiga_wrapper.cpu.ls_exception_valid
|vpiNetType:36
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (ls_exception_valid), line:61, parent:load_store_unit_block
|vpiName:ls_exception_valid
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.ls_exception_valid
|vpiNetType:36
|vpiPort:
\_port: (wb), line:63, parent:load_store_unit_block
|vpiName:wb
|vpiDirection:2
|vpiTypedef:
\_struct_typespec: (unit_writeback_t), line:295
|vpiHighConn:
\_ref_obj: (wb), line:183
|vpiName:wb
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (wb), line:63, parent:load_store_unit_block
|vpiName:wb
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.wb
|vpiInterface:
\_interface: work@ls_sub_unit_interface (bram), file:third_party/cores/taiga/core/load_store_unit.sv, line:77, parent:load_store_unit_block
|vpiDefName:work@ls_sub_unit_interface
|vpiName:bram
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.bram
|vpiModport:
\_modport: (ls), parent:bram
|vpiName:ls
|vpiIODecl:
\_io_decl: (new_request), parent:ls
|vpiName:new_request
|vpiDirection:2
|vpiIODecl:
\_io_decl: (data_valid), parent:ls
|vpiName:data_valid
|vpiDirection:1
|vpiIODecl:
\_io_decl: (ready), parent:ls
|vpiName:ready
|vpiDirection:1
|vpiInterface:
\_interface: work@ls_sub_unit_interface (bram), file:third_party/cores/taiga/core/load_store_unit.sv, line:77, parent:load_store_unit_block
|vpiModport:
\_modport: (sub_unit), parent:bram
|vpiName:sub_unit
|vpiIODecl:
\_io_decl: (new_request), parent:sub_unit
|vpiName:new_request
|vpiDirection:1
|vpiIODecl:
\_io_decl: (data_valid), parent:sub_unit
|vpiName:data_valid
|vpiDirection:2
|vpiIODecl:
\_io_decl: (ready), parent:sub_unit
|vpiName:ready
|vpiDirection:2
|vpiInterface:
\_interface: work@ls_sub_unit_interface (bram), file:third_party/cores/taiga/core/load_store_unit.sv, line:77, parent:load_store_unit_block
|vpiNet:
\_logic_net: (data_valid), line:213, parent:bram
|vpiName:data_valid
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.bram.data_valid
|vpiNetType:36
|vpiNet:
\_logic_net: (ready), line:214, parent:bram
|vpiName:ready
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.bram.ready
|vpiNetType:36
|vpiNet:
\_logic_net: (new_request), line:215, parent:bram
|vpiName:new_request
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.bram.new_request
|vpiNetType:36
|vpiInstance:
\_module: work@load_store_unit (load_store_unit_block), file:third_party/cores/taiga/core/taiga.sv, line:183, parent:cpu
|vpiInterface:
\_interface: work@ls_sub_unit_interface (bus), file:third_party/cores/taiga/core/load_store_unit.sv, line:78, parent:load_store_unit_block
|vpiDefName:work@ls_sub_unit_interface
|vpiName:bus
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.bus
|vpiModport:
\_modport: (ls), parent:bus
|vpiName:ls
|vpiIODecl:
\_io_decl: (new_request), parent:ls
|vpiName:new_request
|vpiDirection:2
|vpiIODecl:
\_io_decl: (data_valid), parent:ls
|vpiName:data_valid
|vpiDirection:1
|vpiIODecl:
\_io_decl: (ready), parent:ls
|vpiName:ready
|vpiDirection:1
|vpiInterface:
\_interface: work@ls_sub_unit_interface (bus), file:third_party/cores/taiga/core/load_store_unit.sv, line:78, parent:load_store_unit_block
|vpiModport:
\_modport: (sub_unit), parent:bus
|vpiName:sub_unit
|vpiIODecl:
\_io_decl: (new_request), parent:sub_unit
|vpiName:new_request
|vpiDirection:1
|vpiIODecl:
\_io_decl: (data_valid), parent:sub_unit
|vpiName:data_valid
|vpiDirection:2
|vpiIODecl:
\_io_decl: (ready), parent:sub_unit
|vpiName:ready
|vpiDirection:2
|vpiInterface:
\_interface: work@ls_sub_unit_interface (bus), file:third_party/cores/taiga/core/load_store_unit.sv, line:78, parent:load_store_unit_block
|vpiNet:
\_logic_net: (data_valid), line:213, parent:bus
|vpiName:data_valid
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.bus.data_valid
|vpiNetType:36
|vpiNet:
\_logic_net: (ready), line:214, parent:bus
|vpiName:ready
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.bus.ready
|vpiNetType:36
|vpiNet:
\_logic_net: (new_request), line:215, parent:bus
|vpiName:new_request
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.bus.new_request
|vpiNetType:36
|vpiInstance:
\_module: work@load_store_unit (load_store_unit_block), file:third_party/cores/taiga/core/taiga.sv, line:183, parent:cpu
|vpiInterface:
\_interface: work@ls_sub_unit_interface (cache), file:third_party/cores/taiga/core/load_store_unit.sv, line:79, parent:load_store_unit_block
|vpiDefName:work@ls_sub_unit_interface
|vpiName:cache
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.cache
|vpiModport:
\_modport: (ls), parent:cache
|vpiName:ls
|vpiIODecl:
\_io_decl: (new_request), parent:ls
|vpiName:new_request
|vpiDirection:2
|vpiIODecl:
\_io_decl: (data_valid), parent:ls
|vpiName:data_valid
|vpiDirection:1
|vpiIODecl:
\_io_decl: (ready), parent:ls
|vpiName:ready
|vpiDirection:1
|vpiInterface:
\_interface: work@ls_sub_unit_interface (cache), file:third_party/cores/taiga/core/load_store_unit.sv, line:79, parent:load_store_unit_block
|vpiModport:
\_modport: (sub_unit), parent:cache
|vpiName:sub_unit
|vpiIODecl:
\_io_decl: (new_request), parent:sub_unit
|vpiName:new_request
|vpiDirection:1
|vpiIODecl:
\_io_decl: (data_valid), parent:sub_unit
|vpiName:data_valid
|vpiDirection:2
|vpiIODecl:
\_io_decl: (ready), parent:sub_unit
|vpiName:ready
|vpiDirection:2
|vpiInterface:
\_interface: work@ls_sub_unit_interface (cache), file:third_party/cores/taiga/core/load_store_unit.sv, line:79, parent:load_store_unit_block
|vpiNet:
\_logic_net: (data_valid), line:213, parent:cache
|vpiName:data_valid
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.cache.data_valid
|vpiNetType:36
|vpiNet:
\_logic_net: (ready), line:214, parent:cache
|vpiName:ready
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.cache.ready
|vpiNetType:36
|vpiNet:
\_logic_net: (new_request), line:215, parent:cache
|vpiName:new_request
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.cache.new_request
|vpiNetType:36
|vpiInstance:
\_module: work@load_store_unit (load_store_unit_block), file:third_party/cores/taiga/core/taiga.sv, line:183, parent:cpu
|vpiInterface:
\_interface: work@fifo_interface (input_fifo), file:third_party/cores/taiga/core/load_store_unit.sv, line:131, parent:load_store_unit_block
|vpiDefName:work@fifo_interface
|vpiName:input_fifo
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.input_fifo
|vpiModport:
\_modport: (dequeue), parent:input_fifo
|vpiName:dequeue
|vpiIODecl:
\_io_decl: (valid), parent:dequeue
|vpiName:valid
|vpiDirection:1
|vpiIODecl:
\_io_decl: (data_out), parent:dequeue
|vpiName:data_out
|vpiDirection:1
|vpiIODecl:
\_io_decl: (pop), parent:dequeue
|vpiName:pop
|vpiDirection:2
|vpiInterface:
\_interface: work@fifo_interface (input_fifo), file:third_party/cores/taiga/core/load_store_unit.sv, line:131, parent:load_store_unit_block
|vpiModport:
\_modport: (enqueue), parent:input_fifo
|vpiName:enqueue
|vpiIODecl:
\_io_decl: (full), parent:enqueue
|vpiName:full
|vpiDirection:1
|vpiIODecl:
\_io_decl: (data_in), parent:enqueue
|vpiName:data_in
|vpiDirection:2
|vpiIODecl:
\_io_decl: (push), parent:enqueue
|vpiName:push
|vpiDirection:2
|vpiIODecl:
\_io_decl: (supress_push), parent:enqueue
|vpiName:supress_push
|vpiDirection:2
|vpiInterface:
\_interface: work@fifo_interface (input_fifo), file:third_party/cores/taiga/core/load_store_unit.sv, line:131, parent:load_store_unit_block
|vpiModport:
\_modport: (structure), parent:input_fifo
|vpiName:structure
|vpiIODecl:
\_io_decl: (push), parent:structure
|vpiName:push
|vpiDirection:1
|vpiIODecl:
\_io_decl: (pop), parent:structure
|vpiName:pop
|vpiDirection:1
|vpiIODecl:
\_io_decl: (data_in), parent:structure
|vpiName:data_in
|vpiDirection:1
|vpiIODecl:
\_io_decl: (supress_push), parent:structure
|vpiName:supress_push
|vpiDirection:1
|vpiIODecl:
\_io_decl: (data_out), parent:structure
|vpiName:data_out
|vpiDirection:2
|vpiIODecl:
\_io_decl: (valid), parent:structure
|vpiName:valid
|vpiDirection:2
|vpiIODecl:
\_io_decl: (full), parent:structure
|vpiName:full
|vpiDirection:2
|vpiInterface:
\_interface: work@fifo_interface (input_fifo), file:third_party/cores/taiga/core/load_store_unit.sv, line:131, parent:load_store_unit_block
|vpiNet:
\_logic_net: (push), line:158, parent:input_fifo
|vpiName:push
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.input_fifo.push
|vpiNetType:36
|vpiNet:
\_logic_net: (pop), line:159, parent:input_fifo
|vpiName:pop
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.input_fifo.pop
|vpiNetType:36
|vpiNet:
\_logic_net: (data_in), line:160, parent:input_fifo
|vpiName:data_in
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.input_fifo.data_in
|vpiNetType:36
|vpiRange:
\_range: , line:160
|vpiLeftRange:
\_constant: , line:160
|vpiDecompile:-1
|INT:-1
|vpiRightRange:
\_constant: , line:160
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (data_out), line:161, parent:input_fifo
|vpiName:data_out
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.input_fifo.data_out
|vpiNetType:36
|vpiRange:
\_range: , line:161
|vpiLeftRange:
\_constant: , line:161
|vpiDecompile:-1
|INT:-1
|vpiRightRange:
\_constant: , line:161
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (valid), line:162, parent:input_fifo
|vpiName:valid
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.input_fifo.valid
|vpiNetType:36
|vpiNet:
\_logic_net: (full), line:163, parent:input_fifo
|vpiName:full
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.input_fifo.full
|vpiNetType:36
|vpiNet:
\_logic_net: (supress_push), line:164, parent:input_fifo
|vpiName:supress_push
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.input_fifo.supress_push
|vpiNetType:36
|vpiNet:
\_logic_net: (push), line:158, parent:input_fifo
|vpiName:push
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.input_fifo.push
|vpiNetType:36
|vpiNet:
\_logic_net: (pop), line:159, parent:input_fifo
|vpiName:pop
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.input_fifo.pop
|vpiNetType:36
|vpiNet:
\_logic_net: (data_in), line:160, parent:input_fifo
|vpiName:data_in
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.input_fifo.data_in
|vpiNetType:36
|vpiRange:
\_range: , line:160
|vpiLeftRange:
\_constant: , line:160
|vpiDecompile:-1
|INT:-1
|vpiRightRange:
\_constant: , line:160
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (data_out), line:161, parent:input_fifo
|vpiName:data_out
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.input_fifo.data_out
|vpiNetType:36
|vpiRange:
\_range: , line:161
|vpiLeftRange:
\_constant: , line:161
|vpiDecompile:-1
|INT:-1
|vpiRightRange:
\_constant: , line:161
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (valid), line:162, parent:input_fifo
|vpiName:valid
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.input_fifo.valid
|vpiNetType:36
|vpiNet:
\_logic_net: (full), line:163, parent:input_fifo
|vpiName:full
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.input_fifo.full
|vpiNetType:36
|vpiNet:
\_logic_net: (supress_push), line:164, parent:input_fifo
|vpiName:supress_push
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.input_fifo.supress_push
|vpiNetType:36
|vpiInstance:
\_module: work@load_store_unit (load_store_unit_block), file:third_party/cores/taiga/core/taiga.sv, line:183, parent:cpu
|vpiInterface:
\_interface: work@fifo_interface (load_attributes), file:third_party/cores/taiga/core/load_store_unit.sv, line:132, parent:load_store_unit_block
|vpiDefName:work@fifo_interface
|vpiName:load_attributes
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.load_attributes
|vpiModport:
\_modport: (dequeue), parent:load_attributes
|vpiName:dequeue
|vpiIODecl:
\_io_decl: (valid), parent:dequeue
|vpiName:valid
|vpiDirection:1
|vpiIODecl:
\_io_decl: (data_out), parent:dequeue
|vpiName:data_out
|vpiDirection:1
|vpiIODecl:
\_io_decl: (pop), parent:dequeue
|vpiName:pop
|vpiDirection:2
|vpiInterface:
\_interface: work@fifo_interface (load_attributes), file:third_party/cores/taiga/core/load_store_unit.sv, line:132, parent:load_store_unit_block
|vpiModport:
\_modport: (enqueue), parent:load_attributes
|vpiName:enqueue
|vpiIODecl:
\_io_decl: (full), parent:enqueue
|vpiName:full
|vpiDirection:1
|vpiIODecl:
\_io_decl: (data_in), parent:enqueue
|vpiName:data_in
|vpiDirection:2
|vpiIODecl:
\_io_decl: (push), parent:enqueue
|vpiName:push
|vpiDirection:2
|vpiIODecl:
\_io_decl: (supress_push), parent:enqueue
|vpiName:supress_push
|vpiDirection:2
|vpiInterface:
\_interface: work@fifo_interface (load_attributes), file:third_party/cores/taiga/core/load_store_unit.sv, line:132, parent:load_store_unit_block
|vpiModport:
\_modport: (structure), parent:load_attributes
|vpiName:structure
|vpiIODecl:
\_io_decl: (push), parent:structure
|vpiName:push
|vpiDirection:1
|vpiIODecl:
\_io_decl: (pop), parent:structure
|vpiName:pop
|vpiDirection:1
|vpiIODecl:
\_io_decl: (data_in), parent:structure
|vpiName:data_in
|vpiDirection:1
|vpiIODecl:
\_io_decl: (supress_push), parent:structure
|vpiName:supress_push
|vpiDirection:1
|vpiIODecl:
\_io_decl: (data_out), parent:structure
|vpiName:data_out
|vpiDirection:2
|vpiIODecl:
\_io_decl: (valid), parent:structure
|vpiName:valid
|vpiDirection:2
|vpiIODecl:
\_io_decl: (full), parent:structure
|vpiName:full
|vpiDirection:2
|vpiInterface:
\_interface: work@fifo_interface (load_attributes), file:third_party/cores/taiga/core/load_store_unit.sv, line:132, parent:load_store_unit_block
|vpiNet:
\_logic_net: (push), line:158, parent:load_attributes
|vpiName:push
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.load_attributes.push
|vpiNetType:36
|vpiNet:
\_logic_net: (pop), line:159, parent:load_attributes
|vpiName:pop
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.load_attributes.pop
|vpiNetType:36
|vpiNet:
\_logic_net: (data_in), line:160, parent:load_attributes
|vpiName:data_in
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.load_attributes.data_in
|vpiNetType:36
|vpiRange:
\_range: , line:160
|vpiLeftRange:
\_constant: , line:160
|vpiDecompile:-1
|INT:-1
|vpiRightRange:
\_constant: , line:160
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (data_out), line:161, parent:load_attributes
|vpiName:data_out
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.load_attributes.data_out
|vpiNetType:36
|vpiRange:
\_range: , line:161
|vpiLeftRange:
\_constant: , line:161
|vpiDecompile:-1
|INT:-1
|vpiRightRange:
\_constant: , line:161
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (valid), line:162, parent:load_attributes
|vpiName:valid
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.load_attributes.valid
|vpiNetType:36
|vpiNet:
\_logic_net: (full), line:163, parent:load_attributes
|vpiName:full
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.load_attributes.full
|vpiNetType:36
|vpiNet:
\_logic_net: (supress_push), line:164, parent:load_attributes
|vpiName:supress_push
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.load_attributes.supress_push
|vpiNetType:36
|vpiNet:
\_logic_net: (push), line:158, parent:load_attributes
|vpiName:push
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.load_attributes.push
|vpiNetType:36
|vpiNet:
\_logic_net: (pop), line:159, parent:load_attributes
|vpiName:pop
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.load_attributes.pop
|vpiNetType:36
|vpiNet:
\_logic_net: (data_in), line:160, parent:load_attributes
|vpiName:data_in
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.load_attributes.data_in
|vpiNetType:36
|vpiRange:
\_range: , line:160
|vpiLeftRange:
\_constant: , line:160
|vpiDecompile:-1
|INT:-1
|vpiRightRange:
\_constant: , line:160
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (data_out), line:161, parent:load_attributes
|vpiName:data_out
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.load_attributes.data_out
|vpiNetType:36
|vpiRange:
\_range: , line:161
|vpiLeftRange:
\_constant: , line:161
|vpiDecompile:-1
|INT:-1
|vpiRightRange:
\_constant: , line:161
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (valid), line:162, parent:load_attributes
|vpiName:valid
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.load_attributes.valid
|vpiNetType:36
|vpiNet:
\_logic_net: (full), line:163, parent:load_attributes
|vpiName:full
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.load_attributes.full
|vpiNetType:36
|vpiNet:
\_logic_net: (supress_push), line:164, parent:load_attributes
|vpiName:supress_push
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.load_attributes.supress_push
|vpiNetType:36
|vpiInstance:
\_module: work@load_store_unit (load_store_unit_block), file:third_party/cores/taiga/core/taiga.sv, line:183, parent:cpu
|vpiModule:
\_module: work@taiga_fifo (ls_input_fifo), file:third_party/cores/taiga/core/load_store_unit.sv, line:138, parent:load_store_unit_block
|vpiDefName:work@taiga_fifo
|vpiName:ls_input_fifo
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.ls_input_fifo
|vpiPort:
\_port: (fifo), line:33, parent:ls_input_fifo
|vpiName:fifo
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (input_fifo), line:139
|vpiName:input_fifo
|vpiActual:
\_interface: work@fifo_interface (input_fifo), file:third_party/cores/taiga/core/load_store_unit.sv, line:131
|vpiDefName:work@fifo_interface
|vpiName:input_fifo
|vpiModport:
\_modport: (dequeue)
|vpiName:dequeue
|vpiIODecl:
\_io_decl: (valid)
|vpiName:valid
|vpiDirection:1
|vpiIODecl:
\_io_decl: (data_out)
|vpiName:data_out
|vpiDirection:1
|vpiIODecl:
\_io_decl: (pop)
|vpiName:pop
|vpiDirection:2
|vpiInterface:
\_interface: work@fifo_interface (input_fifo), file:third_party/cores/taiga/core/load_store_unit.sv, line:131
|vpiModport:
\_modport: (enqueue)
|vpiName:enqueue
|vpiIODecl:
\_io_decl: (full)
|vpiName:full
|vpiDirection:1
|vpiIODecl:
\_io_decl: (data_in)
|vpiName:data_in
|vpiDirection:2
|vpiIODecl:
\_io_decl: (push)
|vpiName:push
|vpiDirection:2
|vpiIODecl:
\_io_decl: (supress_push)
|vpiName:supress_push
|vpiDirection:2
|vpiInterface:
\_interface: work@fifo_interface (input_fifo), file:third_party/cores/taiga/core/load_store_unit.sv, line:131
|vpiModport:
\_modport: (structure)
|vpiName:structure
|vpiIODecl:
\_io_decl: (push)
|vpiName:push
|vpiDirection:1
|vpiIODecl:
\_io_decl: (pop)
|vpiName:pop
|vpiDirection:1
|vpiIODecl:
\_io_decl: (data_in)
|vpiName:data_in
|vpiDirection:1
|vpiIODecl:
\_io_decl: (supress_push)
|vpiName:supress_push
|vpiDirection:1
|vpiIODecl:
\_io_decl: (data_out)
|vpiName:data_out
|vpiDirection:2
|vpiIODecl:
\_io_decl: (valid)
|vpiName:valid
|vpiDirection:2
|vpiIODecl:
\_io_decl: (full)
|vpiName:full
|vpiDirection:2
|vpiInterface:
\_interface: work@fifo_interface (input_fifo), file:third_party/cores/taiga/core/load_store_unit.sv, line:131
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_interface: work@fifo_interface (fifo), file:third_party/cores/taiga/core/load_store_unit.sv, line:138
|vpiDefName:work@fifo_interface
|vpiName:fifo
|vpiModport:
\_modport: (dequeue)
|vpiName:dequeue
|vpiIODecl:
\_io_decl: (valid)
|vpiName:valid
|vpiDirection:1
|vpiExpr:
\_logic_net: (valid), line:162
|vpiName:valid
|vpiNetType:36
|vpiIODecl:
\_io_decl: (data_out)
|vpiName:data_out
|vpiDirection:1
|vpiExpr:
\_logic_net: (data_out), line:161
|vpiName:data_out
|vpiNetType:36
|vpiRange:
\_range: , line:161
|vpiLeftRange:
\_constant: , line:161
|vpiDecompile:-1
|INT:-1
|vpiRightRange:
\_constant: , line:161
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (pop)
|vpiName:pop
|vpiDirection:2
|vpiExpr:
\_logic_net: (pop), line:159
|vpiName:pop
|vpiNetType:36
|vpiInterface:
\_interface: work@fifo_interface (fifo), file:third_party/cores/taiga/core/load_store_unit.sv, line:138
|vpiModport:
\_modport: (enqueue)
|vpiName:enqueue
|vpiIODecl:
\_io_decl: (full)
|vpiName:full
|vpiDirection:1
|vpiExpr:
\_logic_net: (full), line:163
|vpiName:full
|vpiNetType:36
|vpiIODecl:
\_io_decl: (data_in)
|vpiName:data_in
|vpiDirection:2
|vpiExpr:
\_logic_net: (data_in), line:160
|vpiName:data_in
|vpiNetType:36
|vpiRange:
\_range: , line:160
|vpiLeftRange:
\_constant: , line:160
|vpiDecompile:-1
|INT:-1
|vpiRightRange:
\_constant: , line:160
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (push)
|vpiName:push
|vpiDirection:2
|vpiExpr:
\_logic_net: (push), line:158
|vpiName:push
|vpiNetType:36
|vpiIODecl:
\_io_decl: (supress_push)
|vpiName:supress_push
|vpiDirection:2
|vpiExpr:
\_logic_net: (supress_push), line:164
|vpiName:supress_push
|vpiNetType:36
|vpiInterface:
\_interface: work@fifo_interface (fifo), file:third_party/cores/taiga/core/load_store_unit.sv, line:138
|vpiModport:
\_modport: (structure)
|vpiName:structure
|vpiIODecl:
\_io_decl: (push)
|vpiName:push
|vpiDirection:1
|vpiExpr:
\_logic_net: (push), line:158
|vpiIODecl:
\_io_decl: (pop)
|vpiName:pop
|vpiDirection:1
|vpiExpr:
\_logic_net: (pop), line:159
|vpiIODecl:
\_io_decl: (data_in)
|vpiName:data_in
|vpiDirection:1
|vpiExpr:
\_logic_net: (data_in), line:160
|vpiIODecl:
\_io_decl: (supress_push)
|vpiName:supress_push
|vpiDirection:1
|vpiExpr:
\_logic_net: (supress_push), line:164
|vpiIODecl:
\_io_decl: (data_out)
|vpiName:data_out
|vpiDirection:2
|vpiExpr:
\_logic_net: (data_out), line:161
|vpiIODecl:
\_io_decl: (valid)
|vpiName:valid
|vpiDirection:2
|vpiExpr:
\_logic_net: (valid), line:162
|vpiIODecl:
\_io_decl: (full)
|vpiName:full
|vpiDirection:2
|vpiExpr:
\_logic_net: (full), line:163
|vpiInterface:
\_interface: work@fifo_interface (fifo), file:third_party/cores/taiga/core/load_store_unit.sv, line:138
|vpiPort:
\_port: (clk), line:34, parent:ls_input_fifo
|vpiName:clk
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (clk), line:139
|vpiName:clk
|vpiActual:
\_logic_net: (clk), line:27, parent:load_store_unit_block
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (rst), line:34, parent:ls_input_fifo
|vpiName:rst
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.ls_input_fifo.rst
|vpiNetType:36
|vpiPort:
\_port: (rst), line:35, parent:ls_input_fifo
|vpiName:rst
|vpiDirection:5
|vpiHighConn:
\_ref_obj: (rst), line:139
|vpiName:rst
|vpiActual:
\_logic_net: (rst), line:28, parent:load_store_unit_block
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_modport: (structure)
|vpiName:structure
|vpiIODecl:
\_io_decl: (push)
|vpiName:push
|vpiDirection:1
|vpiExpr:
\_logic_net: (push), line:158
|vpiIODecl:
\_io_decl: (pop)
|vpiName:pop
|vpiDirection:1
|vpiExpr:
\_logic_net: (pop), line:159
|vpiIODecl:
\_io_decl: (data_in)
|vpiName:data_in
|vpiDirection:1
|vpiExpr:
\_logic_net: (data_in), line:160
|vpiIODecl:
\_io_decl: (supress_push)
|vpiName:supress_push
|vpiDirection:1
|vpiExpr:
\_logic_net: (supress_push), line:164
|vpiIODecl:
\_io_decl: (data_out)
|vpiName:data_out
|vpiDirection:2
|vpiExpr:
\_logic_net: (data_out), line:161
|vpiIODecl:
\_io_decl: (valid)
|vpiName:valid
|vpiDirection:2
|vpiExpr:
\_logic_net: (valid), line:162
|vpiIODecl:
\_io_decl: (full)
|vpiName:full
|vpiDirection:2
|vpiExpr:
\_logic_net: (full), line:163
|vpiInterface:
\_interface: work@fifo_interface (fifo), file:third_party/cores/taiga/core/load_store_unit.sv, line:138
|vpiDefName:work@fifo_interface
|vpiName:fifo
|vpiModport:
\_modport: (dequeue)
|vpiName:dequeue
|vpiIODecl:
\_io_decl: (valid)
|vpiName:valid
|vpiDirection:1
|vpiExpr:
\_logic_net: (valid), line:162
|vpiIODecl:
\_io_decl: (data_out)
|vpiName:data_out
|vpiDirection:1
|vpiExpr:
\_logic_net: (data_out), line:161
|vpiIODecl:
\_io_decl: (pop)
|vpiName:pop
|vpiDirection:2
|vpiExpr:
\_logic_net: (pop), line:159
|vpiInterface:
\_interface: work@fifo_interface (fifo), file:third_party/cores/taiga/core/load_store_unit.sv, line:138
|vpiModport:
\_modport: (enqueue)
|vpiName:enqueue
|vpiIODecl:
\_io_decl: (full)
|vpiName:full
|vpiDirection:1
|vpiExpr:
\_logic_net: (full), line:163
|vpiIODecl:
\_io_decl: (data_in)
|vpiName:data_in
|vpiDirection:2
|vpiExpr:
\_logic_net: (data_in), line:160
|vpiIODecl:
\_io_decl: (push)
|vpiName:push
|vpiDirection:2
|vpiExpr:
\_logic_net: (push), line:158
|vpiIODecl:
\_io_decl: (supress_push)
|vpiName:supress_push
|vpiDirection:2
|vpiExpr:
\_logic_net: (supress_push), line:164
|vpiInterface:
\_interface: work@fifo_interface (fifo), file:third_party/cores/taiga/core/load_store_unit.sv, line:138
|vpiModport:
\_modport: (structure)
|vpiPort:
\_port: (fifo), parent:ls_input_fifo
|vpiName:fifo
|vpiHighConn:
\_ref_obj: (fifo), line:139
|vpiName:fifo
|vpiGenScopeArray:
\_gen_scope_array: (genblk1), line:65, parent:ls_input_fifo
|vpiName:genblk1
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.ls_input_fifo.genblk1
|vpiGenScope:
\_gen_scope: , parent:genblk1
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.ls_input_fifo.genblk1
|vpiProcess:
\_always: , line:68
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:68
|vpiCondition:
\_operation: , line:68
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:68
|vpiName:clk
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.ls_input_fifo.genblk1.clk
|vpiStmt:
\_begin: , line:68
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.ls_input_fifo.genblk1
|vpiStmt:
\_if_else: , line:69
|vpiCondition:
\_ref_obj: (rst), line:69
|vpiName:rst
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.ls_input_fifo.genblk1.rst
|vpiStmt:
\_assignment: , line:70
|vpiOpType:82
|vpiLhs:
\_ref_obj: (inflight_count), line:70
|vpiName:inflight_count
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.ls_input_fifo.genblk1.inflight_count
|vpiRhs:
\_constant: , line:70
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiElseStmt:
\_assignment: , line:72
|vpiOpType:82
|vpiLhs:
\_ref_obj: (inflight_count), line:72
|vpiName:inflight_count
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.ls_input_fifo.genblk1.inflight_count
|vpiRhs:
\_operation: , line:72
|vpiOpType:11
|vpiOperand:
\_operation: , line:72
|vpiOpType:24
|vpiOperand:
\_ref_obj: (inflight_count), line:72
|vpiName:inflight_count
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.ls_input_fifo.genblk1.inflight_count
|vpiOperand:
\_operation: , line:72
|vpiOpType:67
|vpiOperand:
\_ref_obj: (fifo.pop), line:72
|vpiName:fifo.pop
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.ls_input_fifo.genblk1.fifo.pop
|vpiOperand:
\_operation: , line:72
|vpiOpType:67
|vpiOperand:
\_ref_obj: (supressed_push), line:72
|vpiName:supressed_push
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.ls_input_fifo.genblk1.supressed_push
|vpiProcess:
\_always: , line:78
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:78
|vpiCondition:
\_operation: , line:78
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:78
|vpiName:clk
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.ls_input_fifo.genblk1.clk
|vpiStmt:
\_begin: , line:78
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.ls_input_fifo.genblk1
|vpiStmt:
\_if_else: , line:79
|vpiCondition:
\_ref_obj: (rst), line:79
|vpiName:rst
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.ls_input_fifo.genblk1.rst
|vpiStmt:
\_begin: , line:79
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.ls_input_fifo.genblk1
|vpiStmt:
\_assignment: , line:80
|vpiOpType:82
|vpiLhs:
\_ref_obj: (read_index), line:80
|vpiName:read_index
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.ls_input_fifo.genblk1.read_index
|vpiRhs:
\_constant: , line:80
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiStmt:
\_assignment: , line:81
|vpiOpType:82
|vpiLhs:
\_ref_obj: (write_index), line:81
|vpiName:write_index
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.ls_input_fifo.genblk1.write_index
|vpiRhs:
\_constant: , line:81
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiElseStmt:
\_begin: , line:83
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.ls_input_fifo.genblk1
|vpiStmt:
\_assignment: , line:84
|vpiOpType:82
|vpiLhs:
\_ref_obj: (read_index), line:84
|vpiName:read_index
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.ls_input_fifo.genblk1.read_index
|vpiRhs:
\_operation: , line:84
|vpiOpType:24
|vpiOperand:
\_ref_obj: (read_index), line:84
|vpiName:read_index
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.ls_input_fifo.genblk1.read_index
|vpiOperand:
\_operation: , line:84
|vpiOpType:67
|vpiOperand:
\_ref_obj: (fifo.pop), line:84
|vpiName:fifo.pop
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.ls_input_fifo.genblk1.fifo.pop
|vpiTypespec:
\_void_typespec: (LOG2_FIFO_DEPTH), line:84
|vpiName:LOG2_FIFO_DEPTH
|vpiStmt:
\_assignment: , line:85
|vpiOpType:82
|vpiLhs:
\_ref_obj: (write_index), line:85
|vpiName:write_index
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.ls_input_fifo.genblk1.write_index
|vpiRhs:
\_operation: , line:85
|vpiOpType:24
|vpiOperand:
\_ref_obj: (write_index), line:85
|vpiName:write_index
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.ls_input_fifo.genblk1.write_index
|vpiOperand:
\_operation: , line:85
|vpiOpType:67
|vpiOperand:
\_ref_obj: (supressed_push), line:85
|vpiName:supressed_push
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.ls_input_fifo.genblk1.supressed_push
|vpiTypespec:
\_void_typespec: (LOG2_FIFO_DEPTH), line:85
|vpiName:LOG2_FIFO_DEPTH
|vpiProcess:
\_always: , line:89
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:89
|vpiCondition:
\_operation: , line:89
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:89
|vpiName:clk
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.ls_input_fifo.genblk1.clk
|vpiStmt:
\_begin: , line:89
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.ls_input_fifo.genblk1
|vpiStmt:
\_if_stmt: , line:90
|vpiCondition:
\_ref_obj: (fifo.push), line:90
|vpiName:fifo.push
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.ls_input_fifo.genblk1.fifo.push
|vpiStmt:
\_assignment: , line:91
|vpiOpType:82
|vpiLhs:
\_bit_select: (lut_ram), line:91
|vpiName:lut_ram
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.ls_input_fifo.genblk1.lut_ram
|vpiIndex:
\_ref_obj: (write_index), line:91
|vpiName:write_index
|vpiRhs:
\_ref_obj: (fifo.data_in), line:91
|vpiName:fifo.data_in
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.ls_input_fifo.genblk1.fifo.data_in
|vpiContAssign:
\_cont_assign: , line:75
|vpiRhs:
\_bit_select: (inflight_count), line:75
|vpiName:inflight_count
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.ls_input_fifo.genblk1.inflight_count
|vpiIndex:
\_ref_obj: (LOG2_FIFO_DEPTH), line:75
|vpiName:LOG2_FIFO_DEPTH
|vpiLhs:
\_ref_obj: (fifo.valid), line:75
|vpiName:fifo.valid
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.ls_input_fifo.genblk1.fifo.valid
|vpiContAssign:
\_cont_assign: , line:76
|vpiRhs:
\_operation: , line:76
|vpiOpType:28
|vpiOperand:
\_ref_obj: (fifo.valid), line:76
|vpiName:fifo.valid
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.ls_input_fifo.genblk1.fifo.valid
|vpiOperand:
\_operation: , line:76
|vpiOpType:8
|vpiOperand:
\_part_select: , line:76, parent:inflight_count
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (inflight_count)
|vpiLeftRange:
\_operation: , line:76
|vpiOpType:11
|vpiOperand:
\_ref_obj: (LOG2_FIFO_DEPTH), line:76
|vpiName:LOG2_FIFO_DEPTH
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.ls_input_fifo.genblk1.LOG2_FIFO_DEPTH
|vpiOperand:
\_constant: , line:76
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:76
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiLhs:
\_ref_obj: (fifo.full), line:76
|vpiName:fifo.full
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.ls_input_fifo.genblk1.fifo.full
|vpiContAssign:
\_cont_assign: , line:93
|vpiRhs:
\_bit_select: (lut_ram), line:93
|vpiName:lut_ram
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.ls_input_fifo.genblk1.lut_ram
|vpiIndex:
\_ref_obj: (read_index), line:93
|vpiName:read_index
|vpiLhs:
\_ref_obj: (fifo.data_out), line:93
|vpiName:fifo.data_out
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.ls_input_fifo.genblk1.fifo.data_out
|vpiParameter:
\_parameter: (ALU_UNIT_WB_ID), line:190
|vpiName:ALU_UNIT_WB_ID
|INT:32
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (BRANCH_PREDICTOR_WAYS), line:159
|vpiName:BRANCH_PREDICTOR_WAYS
|INT:9
|vpiParameter:
\_parameter: (BRANCH_TABLE_ENTRIES), line:160
|vpiName:BRANCH_TABLE_ENTRIES
|INT:4
|vpiParameter:
\_parameter: (BRANCH_UNIT_ID), line:195
|vpiName:BRANCH_UNIT_ID
|INT:8
|vpiParameter:
\_parameter: (BUS_ADDR_H), line:107
|vpiName:BUS_ADDR_H
|INT:1
|vpiParameter:
\_parameter: (BUS_ADDR_L), line:106
|vpiName:BUS_ADDR_L
|INT:0
|vpiParameter:
\_parameter: (BUS_BIT_CHECK), line:108
|vpiName:BUS_BIT_CHECK
|INT:1
|vpiParameter:
\_parameter: (BUS_TYPE), line:89
|vpiName:BUS_TYPE
|INT:5
|vpiParameter:
\_parameter: (COUNTER_W), line:42
|vpiName:COUNTER_W
|INT:33
|vpiParameter:
\_parameter: (CPU_ID), line:38
|vpiName:CPU_ID
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_ADDR_WIDTH), line:113
|vpiName:C_M_AXI_ADDR_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_DATA_WIDTH), line:114
|vpiName:C_M_AXI_DATA_WIDTH
|INT:1
|vpiParameter:
\_parameter: (DCACHE_LINES), line:133
|vpiName:DCACHE_LINES
|INT:-2146435073
|vpiParameter:
\_parameter: (DCACHE_LINE_ADDR_W), line:135
|vpiName:DCACHE_LINE_ADDR_W
|INT:1073741824
|vpiParameter:
\_parameter: (DCACHE_LINE_W), line:136
|vpiName:DCACHE_LINE_W
|INT:1342177279
|vpiParameter:
\_parameter: (DCACHE_SUB_LINE_ADDR_W), line:137
|vpiName:DCACHE_SUB_LINE_ADDR_W
|INT:4
|vpiParameter:
\_parameter: (DCACHE_TAG_W), line:138
|vpiName:DCACHE_TAG_W
|INT:1610612736
|vpiParameter:
\_parameter: (DCACHE_WAYS), line:134
|vpiName:DCACHE_WAYS
|INT:4
|vpiParameter:
\_parameter: (DIV_ALGORITHM), line:67
|vpiName:DIV_ALGORITHM
|INT:0
|vpiParameter:
\_parameter: (DIV_UNIT_WB_ID), line:192
|vpiName:DIV_UNIT_WB_ID
|INT:2
|vpiParameter:
\_parameter: (DTLB_DEPTH), line:152
|vpiName:DTLB_DEPTH
|INT:512
|vpiParameter:
\_parameter: (DTLB_WAYS), line:151
|vpiName:DTLB_WAYS
|INT:32
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (ENABLE_M_MODE), line:34
|vpiName:ENABLE_M_MODE
|INT:1
|vpiParameter:
\_parameter: (ENABLE_S_MODE), line:36
|vpiName:ENABLE_S_MODE
|INT:0
|vpiParameter:
\_parameter: (ENABLE_TRACE_INTERFACE), line:172
|vpiName:ENABLE_TRACE_INTERFACE
|INT:2
|vpiParameter:
\_parameter: (FETCH_BUFFER_DEPTH), line:168
|vpiName:FETCH_BUFFER_DEPTH
|INT:512
|vpiParameter:
\_parameter: (FPGA_VENDOR), line:27
|vpiName:FPGA_VENDOR
|STRING:"xilinx"
|vpiParameter:
\_parameter: (GC_UNIT_ID), line:196
|vpiName:GC_UNIT_ID
|INT:4
|vpiParameter:
\_parameter: (ICACHE_LINES), line:121
|vpiName:ICACHE_LINES
|INT:2
|vpiParameter:
\_parameter: (ICACHE_LINE_ADDR_W), line:123
|vpiName:ICACHE_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_LINE_W), line:124
|vpiName:ICACHE_LINE_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_SUB_LINE_ADDR_W), line:125
|vpiName:ICACHE_SUB_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_TAG_W), line:126
|vpiName:ICACHE_TAG_W
|INT:-2147483648
|vpiParameter:
\_parameter: (ICACHE_WAYS), line:122
|vpiName:ICACHE_WAYS
|INT:1
|vpiParameter:
\_parameter: (ITLB_DEPTH), line:146
|vpiName:ITLB_DEPTH
|INT:32
|vpiParameter:
\_parameter: (ITLB_WAYS), line:145
|vpiName:ITLB_WAYS
|INT:4
|vpiParameter:
\_parameter: (L1_CONNECTIONS), line:177
|vpiName:L1_CONNECTIONS
|INT:9
|vpiParameter:
\_parameter: (L1_DCACHE_ID), line:178
|vpiName:L1_DCACHE_ID
|INT:4
|vpiParameter:
\_parameter: (L1_DMMU_ID), line:179
|vpiName:L1_DMMU_ID
|INT:2
|vpiParameter:
\_parameter: (L1_ICACHE_ID), line:180
|vpiName:L1_ICACHE_ID
|INT:19
|vpiParameter:
\_parameter: (L1_IMMU_ID), line:181
|vpiName:L1_IMMU_ID
|INT:0
|vpiParameter:
\_parameter: (LS_UNIT_WB_ID), line:191
|vpiName:LS_UNIT_WB_ID
|INT:1
|vpiParameter:
\_parameter: (MAX_INFLIGHT_COUNT), line:167
|vpiName:MAX_INFLIGHT_COUNT
|INT:19
|vpiParameter:
\_parameter: (MEMORY_ADDR_H), line:103
|vpiName:MEMORY_ADDR_H
|INT:12
|vpiParameter:
\_parameter: (MEMORY_ADDR_L), line:102
|vpiName:MEMORY_ADDR_L
|INT:11
|vpiParameter:
\_parameter: (MEMORY_BIT_CHECK), line:104
|vpiName:MEMORY_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (MUL_UNIT_WB_ID), line:193
|vpiName:MUL_UNIT_WB_ID
|INT:512
|vpiParameter:
\_parameter: (NUM_UNITS), line:188
|vpiName:NUM_UNITS
|INT:2
|vpiParameter:
\_parameter: (NUM_WB_UNITS), line:186
|vpiName:NUM_WB_UNITS
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (RAS_DEPTH), line:161
|vpiName:RAS_DEPTH
|INT:2
|vpiParameter:
\_parameter: (RESET_VEC), line:39
|vpiName:RESET_VEC
|INT:-2147483648
|vpiParameter:
\_parameter: (SCRATCH_ADDR_H), line:99
|vpiName:SCRATCH_ADDR_H
|INT:9
|vpiParameter:
\_parameter: (SCRATCH_ADDR_L), line:98
|vpiName:SCRATCH_ADDR_L
|INT:8
|vpiParameter:
\_parameter: (SCRATCH_BIT_CHECK), line:100
|vpiName:SCRATCH_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (USE_AMO), line:70
|vpiName:USE_AMO
|INT:1
|vpiParameter:
\_parameter: (USE_BRANCH_PREDICTOR), line:158
|vpiName:USE_BRANCH_PREDICTOR
|INT:2
|vpiParameter:
\_parameter: (USE_BUS), line:88
|vpiName:USE_BUS
|INT:4
|vpiParameter:
\_parameter: (USE_DCACHE), line:92
|vpiName:USE_DCACHE
|INT:6
|vpiParameter:
\_parameter: (USE_DIV), line:49
|vpiName:USE_DIV
|INT:1
|vpiParameter:
\_parameter: (USE_DTAG_INVALIDATIONS), line:140
|vpiName:USE_DTAG_INVALIDATIONS
|INT:1879048191
|vpiParameter:
\_parameter: (USE_D_SCRATCH_MEM), line:79
|vpiName:USE_D_SCRATCH_MEM
|INT:3
|vpiParameter:
\_parameter: (USE_ICACHE), line:93
|vpiName:USE_ICACHE
|INT:7
|vpiParameter:
\_parameter: (USE_I_SCRATCH_MEM), line:78
|vpiName:USE_I_SCRATCH_MEM
|INT:2
|vpiParameter:
\_parameter: (USE_MUL), line:48
|vpiName:USE_MUL
|INT:1
|vpiParameter:
\_parameter: (WB_UNITS_WIDTH), line:187
|vpiName:WB_UNITS_WIDTH
|INT:32
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiNet:
\_logic_net: (clk), line:33, parent:ls_input_fifo
|vpiName:clk
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.ls_input_fifo.clk
|vpiNetType:36
|vpiNet:
\_logic_net: (rst), line:34, parent:ls_input_fifo
|vpiNet:
\_logic_net: (write_index), line:41, parent:ls_input_fifo
|vpiName:write_index
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.ls_input_fifo.write_index
|vpiNetType:36
|vpiRange:
\_range: , line:41
|vpiLeftRange:
\_constant: , line:41
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:41
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (read_index), line:42, parent:ls_input_fifo
|vpiName:read_index
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.ls_input_fifo.read_index
|vpiNetType:36
|vpiRange:
\_range: , line:42
|vpiLeftRange:
\_constant: , line:42
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:42
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (inflight_count), line:43, parent:ls_input_fifo
|vpiName:inflight_count
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.ls_input_fifo.inflight_count
|vpiNetType:36
|vpiRange:
\_range: , line:43
|vpiLeftRange:
\_constant: , line:43
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiRightRange:
\_constant: , line:43
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (supressed_push), line:44, parent:ls_input_fifo
|vpiName:supressed_push
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.ls_input_fifo.supressed_push
|vpiNetType:36
|vpiNet:
\_logic_net: (fifo), line:35, parent:ls_input_fifo
|vpiName:fifo
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.ls_input_fifo.fifo
|vpiInstance:
\_module: work@load_store_unit (load_store_unit_block), file:third_party/cores/taiga/core/taiga.sv, line:183, parent:cpu
|vpiArrayNet:
\_array_net: (lut_ram), line:40, parent:ls_input_fifo
|vpiName:lut_ram
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.ls_input_fifo.lut_ram
|vpiSize:2
|vpiNet:
\_logic_net: , parent:lut_ram
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.ls_input_fifo.lut_ram
|vpiNetType:36
|vpiRange:
\_range: , line:40
|vpiLeftRange:
\_constant: , line:40
|vpiDecompile:-1
|INT:-1
|vpiRightRange:
\_constant: , line:40
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiRange:
\_range: , line:40
|vpiLeftRange:
\_constant: , line:40
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:40
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiParameter:
\_parameter: (ALU_UNIT_WB_ID), line:190
|vpiName:ALU_UNIT_WB_ID
|INT:32
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (BRANCH_PREDICTOR_WAYS), line:159
|vpiName:BRANCH_PREDICTOR_WAYS
|INT:9
|vpiParameter:
\_parameter: (BRANCH_TABLE_ENTRIES), line:160
|vpiName:BRANCH_TABLE_ENTRIES
|INT:4
|vpiParameter:
\_parameter: (BRANCH_UNIT_ID), line:195
|vpiName:BRANCH_UNIT_ID
|INT:8
|vpiParameter:
\_parameter: (BUS_ADDR_H), line:107
|vpiName:BUS_ADDR_H
|INT:1
|vpiParameter:
\_parameter: (BUS_ADDR_L), line:106
|vpiName:BUS_ADDR_L
|INT:0
|vpiParameter:
\_parameter: (BUS_BIT_CHECK), line:108
|vpiName:BUS_BIT_CHECK
|INT:1
|vpiParameter:
\_parameter: (BUS_TYPE), line:89
|vpiName:BUS_TYPE
|INT:5
|vpiParameter:
\_parameter: (COUNTER_W), line:42
|vpiName:COUNTER_W
|INT:33
|vpiParameter:
\_parameter: (CPU_ID), line:38
|vpiName:CPU_ID
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_ADDR_WIDTH), line:113
|vpiName:C_M_AXI_ADDR_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_DATA_WIDTH), line:114
|vpiName:C_M_AXI_DATA_WIDTH
|INT:1
|vpiParameter:
\_parameter: (DATA_WIDTH), line:138
|vpiName:DATA_WIDTH
|INT:0
|vpiParameter:
\_parameter: (DCACHE_LINES), line:133
|vpiName:DCACHE_LINES
|INT:-2146435073
|vpiParameter:
\_parameter: (DCACHE_LINE_ADDR_W), line:135
|vpiName:DCACHE_LINE_ADDR_W
|INT:1073741824
|vpiParameter:
\_parameter: (DCACHE_LINE_W), line:136
|vpiName:DCACHE_LINE_W
|INT:1342177279
|vpiParameter:
\_parameter: (DCACHE_SUB_LINE_ADDR_W), line:137
|vpiName:DCACHE_SUB_LINE_ADDR_W
|INT:4
|vpiParameter:
\_parameter: (DCACHE_TAG_W), line:138
|vpiName:DCACHE_TAG_W
|INT:1610612736
|vpiParameter:
\_parameter: (DCACHE_WAYS), line:134
|vpiName:DCACHE_WAYS
|INT:4
|vpiParameter:
\_parameter: (DIV_ALGORITHM), line:67
|vpiName:DIV_ALGORITHM
|INT:0
|vpiParameter:
\_parameter: (DIV_UNIT_WB_ID), line:192
|vpiName:DIV_UNIT_WB_ID
|INT:2
|vpiParameter:
\_parameter: (DTLB_DEPTH), line:152
|vpiName:DTLB_DEPTH
|INT:512
|vpiParameter:
\_parameter: (DTLB_WAYS), line:151
|vpiName:DTLB_WAYS
|INT:32
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (ENABLE_M_MODE), line:34
|vpiName:ENABLE_M_MODE
|INT:1
|vpiParameter:
\_parameter: (ENABLE_S_MODE), line:36
|vpiName:ENABLE_S_MODE
|INT:0
|vpiParameter:
\_parameter: (ENABLE_TRACE_INTERFACE), line:172
|vpiName:ENABLE_TRACE_INTERFACE
|INT:2
|vpiParameter:
\_parameter: (FETCH_BUFFER_DEPTH), line:168
|vpiName:FETCH_BUFFER_DEPTH
|INT:512
|vpiParameter:
\_parameter: (FIFO_DEPTH), line:138
|vpiName:FIFO_DEPTH
|INT:19
|vpiParameter:
\_parameter: (FPGA_VENDOR), line:27
|vpiName:FPGA_VENDOR
|STRING:"xilinx"
|vpiParameter:
\_parameter: (GC_UNIT_ID), line:196
|vpiName:GC_UNIT_ID
|INT:4
|vpiParameter:
\_parameter: (ICACHE_LINES), line:121
|vpiName:ICACHE_LINES
|INT:2
|vpiParameter:
\_parameter: (ICACHE_LINE_ADDR_W), line:123
|vpiName:ICACHE_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_LINE_W), line:124
|vpiName:ICACHE_LINE_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_SUB_LINE_ADDR_W), line:125
|vpiName:ICACHE_SUB_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_TAG_W), line:126
|vpiName:ICACHE_TAG_W
|INT:-2147483648
|vpiParameter:
\_parameter: (ICACHE_WAYS), line:122
|vpiName:ICACHE_WAYS
|INT:1
|vpiParameter:
\_parameter: (ITLB_DEPTH), line:146
|vpiName:ITLB_DEPTH
|INT:32
|vpiParameter:
\_parameter: (ITLB_WAYS), line:145
|vpiName:ITLB_WAYS
|INT:4
|vpiParameter:
\_parameter: (L1_CONNECTIONS), line:177
|vpiName:L1_CONNECTIONS
|INT:9
|vpiParameter:
\_parameter: (L1_DCACHE_ID), line:178
|vpiName:L1_DCACHE_ID
|INT:4
|vpiParameter:
\_parameter: (L1_DMMU_ID), line:179
|vpiName:L1_DMMU_ID
|INT:2
|vpiParameter:
\_parameter: (L1_ICACHE_ID), line:180
|vpiName:L1_ICACHE_ID
|INT:19
|vpiParameter:
\_parameter: (L1_IMMU_ID), line:181
|vpiName:L1_IMMU_ID
|INT:0
|vpiParameter:
\_parameter: (LOG2_FIFO_DEPTH), line:38
|vpiName:LOG2_FIFO_DEPTH
|INT:2
|vpiParameter:
\_parameter: (LS_UNIT_WB_ID), line:191
|vpiName:LS_UNIT_WB_ID
|INT:1
|vpiParameter:
\_parameter: (MAX_INFLIGHT_COUNT), line:167
|vpiName:MAX_INFLIGHT_COUNT
|INT:19
|vpiParameter:
\_parameter: (MEMORY_ADDR_H), line:103
|vpiName:MEMORY_ADDR_H
|INT:12
|vpiParameter:
\_parameter: (MEMORY_ADDR_L), line:102
|vpiName:MEMORY_ADDR_L
|INT:11
|vpiParameter:
\_parameter: (MEMORY_BIT_CHECK), line:104
|vpiName:MEMORY_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (MUL_UNIT_WB_ID), line:193
|vpiName:MUL_UNIT_WB_ID
|INT:512
|vpiParameter:
\_parameter: (NUM_UNITS), line:188
|vpiName:NUM_UNITS
|INT:2
|vpiParameter:
\_parameter: (NUM_WB_UNITS), line:186
|vpiName:NUM_WB_UNITS
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (RAS_DEPTH), line:161
|vpiName:RAS_DEPTH
|INT:2
|vpiParameter:
\_parameter: (RESET_VEC), line:39
|vpiName:RESET_VEC
|INT:-2147483648
|vpiParameter:
\_parameter: (SCRATCH_ADDR_H), line:99
|vpiName:SCRATCH_ADDR_H
|INT:9
|vpiParameter:
\_parameter: (SCRATCH_ADDR_L), line:98
|vpiName:SCRATCH_ADDR_L
|INT:8
|vpiParameter:
\_parameter: (SCRATCH_BIT_CHECK), line:100
|vpiName:SCRATCH_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (USE_AMO), line:70
|vpiName:USE_AMO
|INT:1
|vpiParameter:
\_parameter: (USE_BRANCH_PREDICTOR), line:158
|vpiName:USE_BRANCH_PREDICTOR
|INT:2
|vpiParameter:
\_parameter: (USE_BUS), line:88
|vpiName:USE_BUS
|INT:4
|vpiParameter:
\_parameter: (USE_DCACHE), line:92
|vpiName:USE_DCACHE
|INT:6
|vpiParameter:
\_parameter: (USE_DIV), line:49
|vpiName:USE_DIV
|INT:1
|vpiParameter:
\_parameter: (USE_DTAG_INVALIDATIONS), line:140
|vpiName:USE_DTAG_INVALIDATIONS
|INT:1879048191
|vpiParameter:
\_parameter: (USE_D_SCRATCH_MEM), line:79
|vpiName:USE_D_SCRATCH_MEM
|INT:3
|vpiParameter:
\_parameter: (USE_ICACHE), line:93
|vpiName:USE_ICACHE
|INT:7
|vpiParameter:
\_parameter: (USE_I_SCRATCH_MEM), line:78
|vpiName:USE_I_SCRATCH_MEM
|INT:2
|vpiParameter:
\_parameter: (USE_MUL), line:48
|vpiName:USE_MUL
|INT:1
|vpiParameter:
\_parameter: (WB_UNITS_WIDTH), line:187
|vpiName:WB_UNITS_WIDTH
|INT:32
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiModule:
\_module: work@one_hot_to_integer (hit_way_conv), file:third_party/cores/taiga/core/load_store_unit.sv, line:260, parent:load_store_unit_block
|vpiDefName:work@one_hot_to_integer
|vpiName:hit_way_conv
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.hit_way_conv
|vpiPort:
\_port: (clk), line:31, parent:hit_way_conv
|vpiName:clk
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (clk), line:260
|vpiName:clk
|vpiActual:
\_logic_net: (clk), line:27, parent:load_store_unit_block
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (clk), line:31, parent:hit_way_conv
|vpiName:clk
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.hit_way_conv.clk
|vpiNetType:36
|vpiPort:
\_port: (rst), line:32, parent:hit_way_conv
|vpiName:rst
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (rst), line:260
|vpiName:rst
|vpiActual:
\_logic_net: (rst), line:28, parent:load_store_unit_block
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (rst), line:32, parent:hit_way_conv
|vpiName:rst
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.hit_way_conv.rst
|vpiNetType:36
|vpiPort:
\_port: (one_hot), line:33, parent:hit_way_conv
|vpiName:one_hot
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (one_hot), line:260
|vpiName:one_hot
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (one_hot), line:33, parent:hit_way_conv
|vpiName:one_hot
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.hit_way_conv.one_hot
|vpiNetType:36
|vpiRange:
\_range: , line:33
|vpiLeftRange:
\_constant: , line:33
|vpiConstType:7
|vpiDecompile:12
|vpiSize:32
|INT:12
|vpiRightRange:
\_constant: , line:33
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiPort:
\_port: (int_out), line:34, parent:hit_way_conv
|vpiName:int_out
|vpiDirection:2
|vpiHighConn:
\_ref_obj: (int_out), line:260
|vpiName:int_out
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (int_out), line:34, parent:hit_way_conv
|vpiName:int_out
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.hit_way_conv.int_out
|vpiNetType:36
|vpiRange:
\_range: , line:34
|vpiLeftRange:
\_constant: , line:34
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiRightRange:
\_constant: , line:34
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiGenScopeArray:
\_gen_scope_array: (genblk1), line:40, parent:hit_way_conv
|vpiName:genblk1
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.hit_way_conv.genblk1
|vpiGenScope:
\_gen_scope: , parent:genblk1
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.hit_way_conv.genblk1
|vpiProcess:
\_always: , line:41
|vpiAlwaysType:2
|vpiStmt:
\_begin: , line:41
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.hit_way_conv.genblk1
|vpiStmt:
\_assignment: , line:42
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (int_out), line:42
|vpiName:int_out
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.hit_way_conv.genblk1.int_out
|vpiRhs:
\_constant: , line:42
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiStmt:
\_foreach_stmt: , line:43
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.hit_way_conv.genblk1
|vpiVariables:
\_chandle_var: (one_hot), line:43
|vpiName:one_hot
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.hit_way_conv.genblk1.one_hot
|vpiLoopVars:
\_chandle_var: (i), line:43
|vpiName:i
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.hit_way_conv.genblk1.i
|vpiStmt:
\_if_stmt: , line:44
|vpiCondition:
\_bit_select: (one_hot), line:44
|vpiName:one_hot
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.hit_way_conv.genblk1.one_hot
|vpiIndex:
\_ref_obj: (i), line:44
|vpiName:i
|vpiStmt:
\_assignment: , line:44
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (int_out), line:44
|vpiName:int_out
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.hit_way_conv.genblk1.int_out
|vpiRhs:
\_part_select: , line:44, parent:i
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (i)
|vpiLeftRange:
\_operation: , line:44
|vpiOpType:11
|vpiOperand:
\_sys_func_call: ($clog2), line:44
|vpiName:$clog2
|vpiArgument:
\_ref_obj: (C_WIDTH), line:44
|vpiName:C_WIDTH
|vpiOperand:
\_constant: , line:44
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:44
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (clk), line:31, parent:hit_way_conv
|vpiNet:
\_logic_net: (rst), line:32, parent:hit_way_conv
|vpiNet:
\_logic_net: (one_hot), line:33, parent:hit_way_conv
|vpiNet:
\_logic_net: (int_out), line:34, parent:hit_way_conv
|vpiInstance:
\_module: work@load_store_unit (load_store_unit_block), file:third_party/cores/taiga/core/taiga.sv, line:183, parent:cpu
|vpiParameter:
\_parameter: (C_WIDTH), line:260
|vpiName:C_WIDTH
|INT:13
|vpiModule:
\_module: work@taiga_fifo (attributes_fifo), file:third_party/cores/taiga/core/load_store_unit.sv, line:261, parent:load_store_unit_block
|vpiDefName:work@taiga_fifo
|vpiName:attributes_fifo
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.attributes_fifo
|vpiPort:
\_port: (fifo), line:33, parent:attributes_fifo
|vpiName:fifo
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (load_attributes), line:262
|vpiName:load_attributes
|vpiActual:
\_interface: work@fifo_interface (load_attributes), file:third_party/cores/taiga/core/load_store_unit.sv, line:132
|vpiDefName:work@fifo_interface
|vpiName:load_attributes
|vpiModport:
\_modport: (dequeue)
|vpiName:dequeue
|vpiIODecl:
\_io_decl: (valid)
|vpiName:valid
|vpiDirection:1
|vpiIODecl:
\_io_decl: (data_out)
|vpiName:data_out
|vpiDirection:1
|vpiIODecl:
\_io_decl: (pop)
|vpiName:pop
|vpiDirection:2
|vpiInterface:
\_interface: work@fifo_interface (load_attributes), file:third_party/cores/taiga/core/load_store_unit.sv, line:132
|vpiModport:
\_modport: (enqueue)
|vpiName:enqueue
|vpiIODecl:
\_io_decl: (full)
|vpiName:full
|vpiDirection:1
|vpiIODecl:
\_io_decl: (data_in)
|vpiName:data_in
|vpiDirection:2
|vpiIODecl:
\_io_decl: (push)
|vpiName:push
|vpiDirection:2
|vpiIODecl:
\_io_decl: (supress_push)
|vpiName:supress_push
|vpiDirection:2
|vpiInterface:
\_interface: work@fifo_interface (load_attributes), file:third_party/cores/taiga/core/load_store_unit.sv, line:132
|vpiModport:
\_modport: (structure)
|vpiName:structure
|vpiIODecl:
\_io_decl: (push)
|vpiName:push
|vpiDirection:1
|vpiIODecl:
\_io_decl: (pop)
|vpiName:pop
|vpiDirection:1
|vpiIODecl:
\_io_decl: (data_in)
|vpiName:data_in
|vpiDirection:1
|vpiIODecl:
\_io_decl: (supress_push)
|vpiName:supress_push
|vpiDirection:1
|vpiIODecl:
\_io_decl: (data_out)
|vpiName:data_out
|vpiDirection:2
|vpiIODecl:
\_io_decl: (valid)
|vpiName:valid
|vpiDirection:2
|vpiIODecl:
\_io_decl: (full)
|vpiName:full
|vpiDirection:2
|vpiInterface:
\_interface: work@fifo_interface (load_attributes), file:third_party/cores/taiga/core/load_store_unit.sv, line:132
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_interface: work@fifo_interface (fifo), file:third_party/cores/taiga/core/load_store_unit.sv, line:261
|vpiDefName:work@fifo_interface
|vpiName:fifo
|vpiModport:
\_modport: (dequeue)
|vpiName:dequeue
|vpiIODecl:
\_io_decl: (valid)
|vpiName:valid
|vpiDirection:1
|vpiExpr:
\_logic_net: (valid), line:162
|vpiName:valid
|vpiNetType:36
|vpiIODecl:
\_io_decl: (data_out)
|vpiName:data_out
|vpiDirection:1
|vpiExpr:
\_logic_net: (data_out), line:161
|vpiName:data_out
|vpiNetType:36
|vpiRange:
\_range: , line:161
|vpiLeftRange:
\_constant: , line:161
|vpiDecompile:-1
|INT:-1
|vpiRightRange:
\_constant: , line:161
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (pop)
|vpiName:pop
|vpiDirection:2
|vpiExpr:
\_logic_net: (pop), line:159
|vpiName:pop
|vpiNetType:36
|vpiInterface:
\_interface: work@fifo_interface (fifo), file:third_party/cores/taiga/core/load_store_unit.sv, line:261
|vpiModport:
\_modport: (enqueue)
|vpiName:enqueue
|vpiIODecl:
\_io_decl: (full)
|vpiName:full
|vpiDirection:1
|vpiExpr:
\_logic_net: (full), line:163
|vpiName:full
|vpiNetType:36
|vpiIODecl:
\_io_decl: (data_in)
|vpiName:data_in
|vpiDirection:2
|vpiExpr:
\_logic_net: (data_in), line:160
|vpiName:data_in
|vpiNetType:36
|vpiRange:
\_range: , line:160
|vpiLeftRange:
\_constant: , line:160
|vpiDecompile:-1
|INT:-1
|vpiRightRange:
\_constant: , line:160
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (push)
|vpiName:push
|vpiDirection:2
|vpiExpr:
\_logic_net: (push), line:158
|vpiName:push
|vpiNetType:36
|vpiIODecl:
\_io_decl: (supress_push)
|vpiName:supress_push
|vpiDirection:2
|vpiExpr:
\_logic_net: (supress_push), line:164
|vpiName:supress_push
|vpiNetType:36
|vpiInterface:
\_interface: work@fifo_interface (fifo), file:third_party/cores/taiga/core/load_store_unit.sv, line:261
|vpiModport:
\_modport: (structure)
|vpiName:structure
|vpiIODecl:
\_io_decl: (push)
|vpiName:push
|vpiDirection:1
|vpiExpr:
\_logic_net: (push), line:158
|vpiIODecl:
\_io_decl: (pop)
|vpiName:pop
|vpiDirection:1
|vpiExpr:
\_logic_net: (pop), line:159
|vpiIODecl:
\_io_decl: (data_in)
|vpiName:data_in
|vpiDirection:1
|vpiExpr:
\_logic_net: (data_in), line:160
|vpiIODecl:
\_io_decl: (supress_push)
|vpiName:supress_push
|vpiDirection:1
|vpiExpr:
\_logic_net: (supress_push), line:164
|vpiIODecl:
\_io_decl: (data_out)
|vpiName:data_out
|vpiDirection:2
|vpiExpr:
\_logic_net: (data_out), line:161
|vpiIODecl:
\_io_decl: (valid)
|vpiName:valid
|vpiDirection:2
|vpiExpr:
\_logic_net: (valid), line:162
|vpiIODecl:
\_io_decl: (full)
|vpiName:full
|vpiDirection:2
|vpiExpr:
\_logic_net: (full), line:163
|vpiInterface:
\_interface: work@fifo_interface (fifo), file:third_party/cores/taiga/core/load_store_unit.sv, line:261
|vpiPort:
\_port: (clk), line:34, parent:attributes_fifo
|vpiName:clk
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (clk), line:262
|vpiName:clk
|vpiActual:
\_logic_net: (clk), line:27, parent:load_store_unit_block
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (rst), line:34, parent:attributes_fifo
|vpiName:rst
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.attributes_fifo.rst
|vpiNetType:36
|vpiPort:
\_port: (rst), line:35, parent:attributes_fifo
|vpiName:rst
|vpiDirection:5
|vpiHighConn:
\_ref_obj: (rst), line:262
|vpiName:rst
|vpiActual:
\_logic_net: (rst), line:28, parent:load_store_unit_block
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_modport: (structure)
|vpiName:structure
|vpiIODecl:
\_io_decl: (push)
|vpiName:push
|vpiDirection:1
|vpiExpr:
\_logic_net: (push), line:158
|vpiIODecl:
\_io_decl: (pop)
|vpiName:pop
|vpiDirection:1
|vpiExpr:
\_logic_net: (pop), line:159
|vpiIODecl:
\_io_decl: (data_in)
|vpiName:data_in
|vpiDirection:1
|vpiExpr:
\_logic_net: (data_in), line:160
|vpiIODecl:
\_io_decl: (supress_push)
|vpiName:supress_push
|vpiDirection:1
|vpiExpr:
\_logic_net: (supress_push), line:164
|vpiIODecl:
\_io_decl: (data_out)
|vpiName:data_out
|vpiDirection:2
|vpiExpr:
\_logic_net: (data_out), line:161
|vpiIODecl:
\_io_decl: (valid)
|vpiName:valid
|vpiDirection:2
|vpiExpr:
\_logic_net: (valid), line:162
|vpiIODecl:
\_io_decl: (full)
|vpiName:full
|vpiDirection:2
|vpiExpr:
\_logic_net: (full), line:163
|vpiInterface:
\_interface: work@fifo_interface (fifo), file:third_party/cores/taiga/core/load_store_unit.sv, line:261
|vpiDefName:work@fifo_interface
|vpiName:fifo
|vpiModport:
\_modport: (dequeue)
|vpiName:dequeue
|vpiIODecl:
\_io_decl: (valid)
|vpiName:valid
|vpiDirection:1
|vpiExpr:
\_logic_net: (valid), line:162
|vpiIODecl:
\_io_decl: (data_out)
|vpiName:data_out
|vpiDirection:1
|vpiExpr:
\_logic_net: (data_out), line:161
|vpiIODecl:
\_io_decl: (pop)
|vpiName:pop
|vpiDirection:2
|vpiExpr:
\_logic_net: (pop), line:159
|vpiInterface:
\_interface: work@fifo_interface (fifo), file:third_party/cores/taiga/core/load_store_unit.sv, line:261
|vpiModport:
\_modport: (enqueue)
|vpiName:enqueue
|vpiIODecl:
\_io_decl: (full)
|vpiName:full
|vpiDirection:1
|vpiExpr:
\_logic_net: (full), line:163
|vpiIODecl:
\_io_decl: (data_in)
|vpiName:data_in
|vpiDirection:2
|vpiExpr:
\_logic_net: (data_in), line:160
|vpiIODecl:
\_io_decl: (push)
|vpiName:push
|vpiDirection:2
|vpiExpr:
\_logic_net: (push), line:158
|vpiIODecl:
\_io_decl: (supress_push)
|vpiName:supress_push
|vpiDirection:2
|vpiExpr:
\_logic_net: (supress_push), line:164
|vpiInterface:
\_interface: work@fifo_interface (fifo), file:third_party/cores/taiga/core/load_store_unit.sv, line:261
|vpiModport:
\_modport: (structure)
|vpiPort:
\_port: (fifo), parent:attributes_fifo
|vpiName:fifo
|vpiHighConn:
\_ref_obj: (fifo), line:262
|vpiName:fifo
|vpiGenScopeArray:
\_gen_scope_array: (genblk1), line:65, parent:attributes_fifo
|vpiName:genblk1
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.attributes_fifo.genblk1
|vpiGenScope:
\_gen_scope: , parent:genblk1
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.attributes_fifo.genblk1
|vpiProcess:
\_always: , line:68
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:68
|vpiCondition:
\_operation: , line:68
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:68
|vpiName:clk
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.attributes_fifo.genblk1.clk
|vpiStmt:
\_begin: , line:68
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.attributes_fifo.genblk1
|vpiStmt:
\_if_else: , line:69
|vpiCondition:
\_ref_obj: (rst), line:69
|vpiName:rst
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.attributes_fifo.genblk1.rst
|vpiStmt:
\_assignment: , line:70
|vpiOpType:82
|vpiLhs:
\_ref_obj: (inflight_count), line:70
|vpiName:inflight_count
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.attributes_fifo.genblk1.inflight_count
|vpiRhs:
\_constant: , line:70
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiElseStmt:
\_assignment: , line:72
|vpiOpType:82
|vpiLhs:
\_ref_obj: (inflight_count), line:72
|vpiName:inflight_count
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.attributes_fifo.genblk1.inflight_count
|vpiRhs:
\_operation: , line:72
|vpiOpType:11
|vpiOperand:
\_operation: , line:72
|vpiOpType:24
|vpiOperand:
\_ref_obj: (inflight_count), line:72
|vpiName:inflight_count
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.attributes_fifo.genblk1.inflight_count
|vpiOperand:
\_operation: , line:72
|vpiOpType:67
|vpiOperand:
\_ref_obj: (fifo.pop), line:72
|vpiName:fifo.pop
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.attributes_fifo.genblk1.fifo.pop
|vpiOperand:
\_operation: , line:72
|vpiOpType:67
|vpiOperand:
\_ref_obj: (supressed_push), line:72
|vpiName:supressed_push
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.attributes_fifo.genblk1.supressed_push
|vpiProcess:
\_always: , line:78
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:78
|vpiCondition:
\_operation: , line:78
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:78
|vpiName:clk
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.attributes_fifo.genblk1.clk
|vpiStmt:
\_begin: , line:78
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.attributes_fifo.genblk1
|vpiStmt:
\_if_else: , line:79
|vpiCondition:
\_ref_obj: (rst), line:79
|vpiName:rst
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.attributes_fifo.genblk1.rst
|vpiStmt:
\_begin: , line:79
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.attributes_fifo.genblk1
|vpiStmt:
\_assignment: , line:80
|vpiOpType:82
|vpiLhs:
\_ref_obj: (read_index), line:80
|vpiName:read_index
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.attributes_fifo.genblk1.read_index
|vpiRhs:
\_constant: , line:80
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiStmt:
\_assignment: , line:81
|vpiOpType:82
|vpiLhs:
\_ref_obj: (write_index), line:81
|vpiName:write_index
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.attributes_fifo.genblk1.write_index
|vpiRhs:
\_constant: , line:81
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiElseStmt:
\_begin: , line:83
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.attributes_fifo.genblk1
|vpiStmt:
\_assignment: , line:84
|vpiOpType:82
|vpiLhs:
\_ref_obj: (read_index), line:84
|vpiName:read_index
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.attributes_fifo.genblk1.read_index
|vpiRhs:
\_operation: , line:84
|vpiOpType:24
|vpiOperand:
\_ref_obj: (read_index), line:84
|vpiName:read_index
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.attributes_fifo.genblk1.read_index
|vpiOperand:
\_operation: , line:84
|vpiOpType:67
|vpiOperand:
\_ref_obj: (fifo.pop), line:84
|vpiName:fifo.pop
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.attributes_fifo.genblk1.fifo.pop
|vpiTypespec:
\_void_typespec: (LOG2_FIFO_DEPTH), line:84
|vpiName:LOG2_FIFO_DEPTH
|vpiStmt:
\_assignment: , line:85
|vpiOpType:82
|vpiLhs:
\_ref_obj: (write_index), line:85
|vpiName:write_index
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.attributes_fifo.genblk1.write_index
|vpiRhs:
\_operation: , line:85
|vpiOpType:24
|vpiOperand:
\_ref_obj: (write_index), line:85
|vpiName:write_index
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.attributes_fifo.genblk1.write_index
|vpiOperand:
\_operation: , line:85
|vpiOpType:67
|vpiOperand:
\_ref_obj: (supressed_push), line:85
|vpiName:supressed_push
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.attributes_fifo.genblk1.supressed_push
|vpiTypespec:
\_void_typespec: (LOG2_FIFO_DEPTH), line:85
|vpiName:LOG2_FIFO_DEPTH
|vpiProcess:
\_always: , line:89
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:89
|vpiCondition:
\_operation: , line:89
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:89
|vpiName:clk
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.attributes_fifo.genblk1.clk
|vpiStmt:
\_begin: , line:89
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.attributes_fifo.genblk1
|vpiStmt:
\_if_stmt: , line:90
|vpiCondition:
\_ref_obj: (fifo.push), line:90
|vpiName:fifo.push
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.attributes_fifo.genblk1.fifo.push
|vpiStmt:
\_assignment: , line:91
|vpiOpType:82
|vpiLhs:
\_bit_select: (lut_ram), line:91
|vpiName:lut_ram
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.attributes_fifo.genblk1.lut_ram
|vpiIndex:
\_ref_obj: (write_index), line:91
|vpiName:write_index
|vpiRhs:
\_ref_obj: (fifo.data_in), line:91
|vpiName:fifo.data_in
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.attributes_fifo.genblk1.fifo.data_in
|vpiContAssign:
\_cont_assign: , line:75
|vpiRhs:
\_bit_select: (inflight_count), line:75
|vpiName:inflight_count
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.attributes_fifo.genblk1.inflight_count
|vpiIndex:
\_ref_obj: (LOG2_FIFO_DEPTH), line:75
|vpiName:LOG2_FIFO_DEPTH
|vpiLhs:
\_ref_obj: (fifo.valid), line:75
|vpiName:fifo.valid
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.attributes_fifo.genblk1.fifo.valid
|vpiContAssign:
\_cont_assign: , line:76
|vpiRhs:
\_operation: , line:76
|vpiOpType:28
|vpiOperand:
\_ref_obj: (fifo.valid), line:76
|vpiName:fifo.valid
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.attributes_fifo.genblk1.fifo.valid
|vpiOperand:
\_operation: , line:76
|vpiOpType:8
|vpiOperand:
\_part_select: , line:76, parent:inflight_count
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (inflight_count)
|vpiLeftRange:
\_operation: , line:76
|vpiOpType:11
|vpiOperand:
\_ref_obj: (LOG2_FIFO_DEPTH), line:76
|vpiName:LOG2_FIFO_DEPTH
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.attributes_fifo.genblk1.LOG2_FIFO_DEPTH
|vpiOperand:
\_constant: , line:76
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:76
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiLhs:
\_ref_obj: (fifo.full), line:76
|vpiName:fifo.full
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.attributes_fifo.genblk1.fifo.full
|vpiContAssign:
\_cont_assign: , line:93
|vpiRhs:
\_bit_select: (lut_ram), line:93
|vpiName:lut_ram
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.attributes_fifo.genblk1.lut_ram
|vpiIndex:
\_ref_obj: (read_index), line:93
|vpiName:read_index
|vpiLhs:
\_ref_obj: (fifo.data_out), line:93
|vpiName:fifo.data_out
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.attributes_fifo.genblk1.fifo.data_out
|vpiParameter:
\_parameter: (ALU_UNIT_WB_ID), line:190
|vpiName:ALU_UNIT_WB_ID
|INT:32
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (BRANCH_PREDICTOR_WAYS), line:159
|vpiName:BRANCH_PREDICTOR_WAYS
|INT:9
|vpiParameter:
\_parameter: (BRANCH_TABLE_ENTRIES), line:160
|vpiName:BRANCH_TABLE_ENTRIES
|INT:4
|vpiParameter:
\_parameter: (BRANCH_UNIT_ID), line:195
|vpiName:BRANCH_UNIT_ID
|INT:8
|vpiParameter:
\_parameter: (BUS_ADDR_H), line:107
|vpiName:BUS_ADDR_H
|INT:1
|vpiParameter:
\_parameter: (BUS_ADDR_L), line:106
|vpiName:BUS_ADDR_L
|INT:0
|vpiParameter:
\_parameter: (BUS_BIT_CHECK), line:108
|vpiName:BUS_BIT_CHECK
|INT:1
|vpiParameter:
\_parameter: (BUS_TYPE), line:89
|vpiName:BUS_TYPE
|INT:5
|vpiParameter:
\_parameter: (COUNTER_W), line:42
|vpiName:COUNTER_W
|INT:33
|vpiParameter:
\_parameter: (CPU_ID), line:38
|vpiName:CPU_ID
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_ADDR_WIDTH), line:113
|vpiName:C_M_AXI_ADDR_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_DATA_WIDTH), line:114
|vpiName:C_M_AXI_DATA_WIDTH
|INT:1
|vpiParameter:
\_parameter: (DCACHE_LINES), line:133
|vpiName:DCACHE_LINES
|INT:-2146435073
|vpiParameter:
\_parameter: (DCACHE_LINE_ADDR_W), line:135
|vpiName:DCACHE_LINE_ADDR_W
|INT:1073741824
|vpiParameter:
\_parameter: (DCACHE_LINE_W), line:136
|vpiName:DCACHE_LINE_W
|INT:1342177279
|vpiParameter:
\_parameter: (DCACHE_SUB_LINE_ADDR_W), line:137
|vpiName:DCACHE_SUB_LINE_ADDR_W
|INT:4
|vpiParameter:
\_parameter: (DCACHE_TAG_W), line:138
|vpiName:DCACHE_TAG_W
|INT:1610612736
|vpiParameter:
\_parameter: (DCACHE_WAYS), line:134
|vpiName:DCACHE_WAYS
|INT:4
|vpiParameter:
\_parameter: (DIV_ALGORITHM), line:67
|vpiName:DIV_ALGORITHM
|INT:0
|vpiParameter:
\_parameter: (DIV_UNIT_WB_ID), line:192
|vpiName:DIV_UNIT_WB_ID
|INT:2
|vpiParameter:
\_parameter: (DTLB_DEPTH), line:152
|vpiName:DTLB_DEPTH
|INT:512
|vpiParameter:
\_parameter: (DTLB_WAYS), line:151
|vpiName:DTLB_WAYS
|INT:32
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (ENABLE_M_MODE), line:34
|vpiName:ENABLE_M_MODE
|INT:1
|vpiParameter:
\_parameter: (ENABLE_S_MODE), line:36
|vpiName:ENABLE_S_MODE
|INT:0
|vpiParameter:
\_parameter: (ENABLE_TRACE_INTERFACE), line:172
|vpiName:ENABLE_TRACE_INTERFACE
|INT:2
|vpiParameter:
\_parameter: (FETCH_BUFFER_DEPTH), line:168
|vpiName:FETCH_BUFFER_DEPTH
|INT:512
|vpiParameter:
\_parameter: (FPGA_VENDOR), line:27
|vpiName:FPGA_VENDOR
|STRING:"xilinx"
|vpiParameter:
\_parameter: (GC_UNIT_ID), line:196
|vpiName:GC_UNIT_ID
|INT:4
|vpiParameter:
\_parameter: (ICACHE_LINES), line:121
|vpiName:ICACHE_LINES
|INT:2
|vpiParameter:
\_parameter: (ICACHE_LINE_ADDR_W), line:123
|vpiName:ICACHE_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_LINE_W), line:124
|vpiName:ICACHE_LINE_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_SUB_LINE_ADDR_W), line:125
|vpiName:ICACHE_SUB_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_TAG_W), line:126
|vpiName:ICACHE_TAG_W
|INT:-2147483648
|vpiParameter:
\_parameter: (ICACHE_WAYS), line:122
|vpiName:ICACHE_WAYS
|INT:1
|vpiParameter:
\_parameter: (ITLB_DEPTH), line:146
|vpiName:ITLB_DEPTH
|INT:32
|vpiParameter:
\_parameter: (ITLB_WAYS), line:145
|vpiName:ITLB_WAYS
|INT:4
|vpiParameter:
\_parameter: (L1_CONNECTIONS), line:177
|vpiName:L1_CONNECTIONS
|INT:9
|vpiParameter:
\_parameter: (L1_DCACHE_ID), line:178
|vpiName:L1_DCACHE_ID
|INT:4
|vpiParameter:
\_parameter: (L1_DMMU_ID), line:179
|vpiName:L1_DMMU_ID
|INT:2
|vpiParameter:
\_parameter: (L1_ICACHE_ID), line:180
|vpiName:L1_ICACHE_ID
|INT:19
|vpiParameter:
\_parameter: (L1_IMMU_ID), line:181
|vpiName:L1_IMMU_ID
|INT:0
|vpiParameter:
\_parameter: (LS_UNIT_WB_ID), line:191
|vpiName:LS_UNIT_WB_ID
|INT:1
|vpiParameter:
\_parameter: (MAX_INFLIGHT_COUNT), line:167
|vpiName:MAX_INFLIGHT_COUNT
|INT:19
|vpiParameter:
\_parameter: (MEMORY_ADDR_H), line:103
|vpiName:MEMORY_ADDR_H
|INT:12
|vpiParameter:
\_parameter: (MEMORY_ADDR_L), line:102
|vpiName:MEMORY_ADDR_L
|INT:11
|vpiParameter:
\_parameter: (MEMORY_BIT_CHECK), line:104
|vpiName:MEMORY_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (MUL_UNIT_WB_ID), line:193
|vpiName:MUL_UNIT_WB_ID
|INT:512
|vpiParameter:
\_parameter: (NUM_UNITS), line:188
|vpiName:NUM_UNITS
|INT:2
|vpiParameter:
\_parameter: (NUM_WB_UNITS), line:186
|vpiName:NUM_WB_UNITS
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (RAS_DEPTH), line:161
|vpiName:RAS_DEPTH
|INT:2
|vpiParameter:
\_parameter: (RESET_VEC), line:39
|vpiName:RESET_VEC
|INT:-2147483648
|vpiParameter:
\_parameter: (SCRATCH_ADDR_H), line:99
|vpiName:SCRATCH_ADDR_H
|INT:9
|vpiParameter:
\_parameter: (SCRATCH_ADDR_L), line:98
|vpiName:SCRATCH_ADDR_L
|INT:8
|vpiParameter:
\_parameter: (SCRATCH_BIT_CHECK), line:100
|vpiName:SCRATCH_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (USE_AMO), line:70
|vpiName:USE_AMO
|INT:1
|vpiParameter:
\_parameter: (USE_BRANCH_PREDICTOR), line:158
|vpiName:USE_BRANCH_PREDICTOR
|INT:2
|vpiParameter:
\_parameter: (USE_BUS), line:88
|vpiName:USE_BUS
|INT:4
|vpiParameter:
\_parameter: (USE_DCACHE), line:92
|vpiName:USE_DCACHE
|INT:6
|vpiParameter:
\_parameter: (USE_DIV), line:49
|vpiName:USE_DIV
|INT:1
|vpiParameter:
\_parameter: (USE_DTAG_INVALIDATIONS), line:140
|vpiName:USE_DTAG_INVALIDATIONS
|INT:1879048191
|vpiParameter:
\_parameter: (USE_D_SCRATCH_MEM), line:79
|vpiName:USE_D_SCRATCH_MEM
|INT:3
|vpiParameter:
\_parameter: (USE_ICACHE), line:93
|vpiName:USE_ICACHE
|INT:7
|vpiParameter:
\_parameter: (USE_I_SCRATCH_MEM), line:78
|vpiName:USE_I_SCRATCH_MEM
|INT:2
|vpiParameter:
\_parameter: (USE_MUL), line:48
|vpiName:USE_MUL
|INT:1
|vpiParameter:
\_parameter: (WB_UNITS_WIDTH), line:187
|vpiName:WB_UNITS_WIDTH
|INT:32
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiNet:
\_logic_net: (clk), line:33, parent:attributes_fifo
|vpiName:clk
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.attributes_fifo.clk
|vpiNetType:36
|vpiNet:
\_logic_net: (rst), line:34, parent:attributes_fifo
|vpiNet:
\_logic_net: (write_index), line:41, parent:attributes_fifo
|vpiName:write_index
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.attributes_fifo.write_index
|vpiNetType:36
|vpiRange:
\_range: , line:41
|vpiLeftRange:
\_constant: , line:41
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:41
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (read_index), line:42, parent:attributes_fifo
|vpiName:read_index
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.attributes_fifo.read_index
|vpiNetType:36
|vpiRange:
\_range: , line:42
|vpiLeftRange:
\_constant: , line:42
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:42
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (inflight_count), line:43, parent:attributes_fifo
|vpiName:inflight_count
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.attributes_fifo.inflight_count
|vpiNetType:36
|vpiRange:
\_range: , line:43
|vpiLeftRange:
\_constant: , line:43
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiRightRange:
\_constant: , line:43
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (supressed_push), line:44, parent:attributes_fifo
|vpiName:supressed_push
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.attributes_fifo.supressed_push
|vpiNetType:36
|vpiNet:
\_logic_net: (fifo), line:35, parent:attributes_fifo
|vpiName:fifo
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.attributes_fifo.fifo
|vpiInstance:
\_module: work@load_store_unit (load_store_unit_block), file:third_party/cores/taiga/core/taiga.sv, line:183, parent:cpu
|vpiArrayNet:
\_array_net: (lut_ram), line:40, parent:attributes_fifo
|vpiName:lut_ram
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.attributes_fifo.lut_ram
|vpiSize:2
|vpiNet:
\_logic_net: , parent:lut_ram
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.attributes_fifo.lut_ram
|vpiNetType:36
|vpiRange:
\_range: , line:40
|vpiLeftRange:
\_constant: , line:40
|vpiDecompile:-1
|INT:-1
|vpiRightRange:
\_constant: , line:40
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiRange:
\_range: , line:40
|vpiLeftRange:
\_constant: , line:40
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:40
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiParameter:
\_parameter: (ALU_UNIT_WB_ID), line:190
|vpiName:ALU_UNIT_WB_ID
|INT:32
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (BRANCH_PREDICTOR_WAYS), line:159
|vpiName:BRANCH_PREDICTOR_WAYS
|INT:9
|vpiParameter:
\_parameter: (BRANCH_TABLE_ENTRIES), line:160
|vpiName:BRANCH_TABLE_ENTRIES
|INT:4
|vpiParameter:
\_parameter: (BRANCH_UNIT_ID), line:195
|vpiName:BRANCH_UNIT_ID
|INT:8
|vpiParameter:
\_parameter: (BUS_ADDR_H), line:107
|vpiName:BUS_ADDR_H
|INT:1
|vpiParameter:
\_parameter: (BUS_ADDR_L), line:106
|vpiName:BUS_ADDR_L
|INT:0
|vpiParameter:
\_parameter: (BUS_BIT_CHECK), line:108
|vpiName:BUS_BIT_CHECK
|INT:1
|vpiParameter:
\_parameter: (BUS_TYPE), line:89
|vpiName:BUS_TYPE
|INT:5
|vpiParameter:
\_parameter: (COUNTER_W), line:42
|vpiName:COUNTER_W
|INT:33
|vpiParameter:
\_parameter: (CPU_ID), line:38
|vpiName:CPU_ID
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_ADDR_WIDTH), line:113
|vpiName:C_M_AXI_ADDR_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_DATA_WIDTH), line:114
|vpiName:C_M_AXI_DATA_WIDTH
|INT:1
|vpiParameter:
\_parameter: (DATA_WIDTH), line:261
|vpiName:DATA_WIDTH
|INT:0
|vpiParameter:
\_parameter: (DCACHE_LINES), line:133
|vpiName:DCACHE_LINES
|INT:-2146435073
|vpiParameter:
\_parameter: (DCACHE_LINE_ADDR_W), line:135
|vpiName:DCACHE_LINE_ADDR_W
|INT:1073741824
|vpiParameter:
\_parameter: (DCACHE_LINE_W), line:136
|vpiName:DCACHE_LINE_W
|INT:1342177279
|vpiParameter:
\_parameter: (DCACHE_SUB_LINE_ADDR_W), line:137
|vpiName:DCACHE_SUB_LINE_ADDR_W
|INT:4
|vpiParameter:
\_parameter: (DCACHE_TAG_W), line:138
|vpiName:DCACHE_TAG_W
|INT:1610612736
|vpiParameter:
\_parameter: (DCACHE_WAYS), line:134
|vpiName:DCACHE_WAYS
|INT:4
|vpiParameter:
\_parameter: (DIV_ALGORITHM), line:67
|vpiName:DIV_ALGORITHM
|INT:0
|vpiParameter:
\_parameter: (DIV_UNIT_WB_ID), line:192
|vpiName:DIV_UNIT_WB_ID
|INT:2
|vpiParameter:
\_parameter: (DTLB_DEPTH), line:152
|vpiName:DTLB_DEPTH
|INT:512
|vpiParameter:
\_parameter: (DTLB_WAYS), line:151
|vpiName:DTLB_WAYS
|INT:32
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (ENABLE_M_MODE), line:34
|vpiName:ENABLE_M_MODE
|INT:1
|vpiParameter:
\_parameter: (ENABLE_S_MODE), line:36
|vpiName:ENABLE_S_MODE
|INT:0
|vpiParameter:
\_parameter: (ENABLE_TRACE_INTERFACE), line:172
|vpiName:ENABLE_TRACE_INTERFACE
|INT:2
|vpiParameter:
\_parameter: (FETCH_BUFFER_DEPTH), line:168
|vpiName:FETCH_BUFFER_DEPTH
|INT:512
|vpiParameter:
\_parameter: (FIFO_DEPTH), line:261
|vpiName:FIFO_DEPTH
|INT:6
|vpiParameter:
\_parameter: (FPGA_VENDOR), line:27
|vpiName:FPGA_VENDOR
|STRING:"xilinx"
|vpiParameter:
\_parameter: (GC_UNIT_ID), line:196
|vpiName:GC_UNIT_ID
|INT:4
|vpiParameter:
\_parameter: (ICACHE_LINES), line:121
|vpiName:ICACHE_LINES
|INT:2
|vpiParameter:
\_parameter: (ICACHE_LINE_ADDR_W), line:123
|vpiName:ICACHE_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_LINE_W), line:124
|vpiName:ICACHE_LINE_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_SUB_LINE_ADDR_W), line:125
|vpiName:ICACHE_SUB_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_TAG_W), line:126
|vpiName:ICACHE_TAG_W
|INT:-2147483648
|vpiParameter:
\_parameter: (ICACHE_WAYS), line:122
|vpiName:ICACHE_WAYS
|INT:1
|vpiParameter:
\_parameter: (ITLB_DEPTH), line:146
|vpiName:ITLB_DEPTH
|INT:32
|vpiParameter:
\_parameter: (ITLB_WAYS), line:145
|vpiName:ITLB_WAYS
|INT:4
|vpiParameter:
\_parameter: (L1_CONNECTIONS), line:177
|vpiName:L1_CONNECTIONS
|INT:9
|vpiParameter:
\_parameter: (L1_DCACHE_ID), line:178
|vpiName:L1_DCACHE_ID
|INT:4
|vpiParameter:
\_parameter: (L1_DMMU_ID), line:179
|vpiName:L1_DMMU_ID
|INT:2
|vpiParameter:
\_parameter: (L1_ICACHE_ID), line:180
|vpiName:L1_ICACHE_ID
|INT:19
|vpiParameter:
\_parameter: (L1_IMMU_ID), line:181
|vpiName:L1_IMMU_ID
|INT:0
|vpiParameter:
\_parameter: (LOG2_FIFO_DEPTH), line:38
|vpiName:LOG2_FIFO_DEPTH
|INT:2
|vpiParameter:
\_parameter: (LS_UNIT_WB_ID), line:191
|vpiName:LS_UNIT_WB_ID
|INT:1
|vpiParameter:
\_parameter: (MAX_INFLIGHT_COUNT), line:167
|vpiName:MAX_INFLIGHT_COUNT
|INT:19
|vpiParameter:
\_parameter: (MEMORY_ADDR_H), line:103
|vpiName:MEMORY_ADDR_H
|INT:12
|vpiParameter:
\_parameter: (MEMORY_ADDR_L), line:102
|vpiName:MEMORY_ADDR_L
|INT:11
|vpiParameter:
\_parameter: (MEMORY_BIT_CHECK), line:104
|vpiName:MEMORY_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (MUL_UNIT_WB_ID), line:193
|vpiName:MUL_UNIT_WB_ID
|INT:512
|vpiParameter:
\_parameter: (NUM_UNITS), line:188
|vpiName:NUM_UNITS
|INT:2
|vpiParameter:
\_parameter: (NUM_WB_UNITS), line:186
|vpiName:NUM_WB_UNITS
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (RAS_DEPTH), line:161
|vpiName:RAS_DEPTH
|INT:2
|vpiParameter:
\_parameter: (RESET_VEC), line:39
|vpiName:RESET_VEC
|INT:-2147483648
|vpiParameter:
\_parameter: (SCRATCH_ADDR_H), line:99
|vpiName:SCRATCH_ADDR_H
|INT:9
|vpiParameter:
\_parameter: (SCRATCH_ADDR_L), line:98
|vpiName:SCRATCH_ADDR_L
|INT:8
|vpiParameter:
\_parameter: (SCRATCH_BIT_CHECK), line:100
|vpiName:SCRATCH_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (USE_AMO), line:70
|vpiName:USE_AMO
|INT:1
|vpiParameter:
\_parameter: (USE_BRANCH_PREDICTOR), line:158
|vpiName:USE_BRANCH_PREDICTOR
|INT:2
|vpiParameter:
\_parameter: (USE_BUS), line:88
|vpiName:USE_BUS
|INT:4
|vpiParameter:
\_parameter: (USE_DCACHE), line:92
|vpiName:USE_DCACHE
|INT:6
|vpiParameter:
\_parameter: (USE_DIV), line:49
|vpiName:USE_DIV
|INT:1
|vpiParameter:
\_parameter: (USE_DTAG_INVALIDATIONS), line:140
|vpiName:USE_DTAG_INVALIDATIONS
|INT:1879048191
|vpiParameter:
\_parameter: (USE_D_SCRATCH_MEM), line:79
|vpiName:USE_D_SCRATCH_MEM
|INT:3
|vpiParameter:
\_parameter: (USE_ICACHE), line:93
|vpiName:USE_ICACHE
|INT:7
|vpiParameter:
\_parameter: (USE_I_SCRATCH_MEM), line:78
|vpiName:USE_I_SCRATCH_MEM
|INT:2
|vpiParameter:
\_parameter: (USE_MUL), line:48
|vpiName:USE_MUL
|INT:1
|vpiParameter:
\_parameter: (WB_UNITS_WIDTH), line:187
|vpiName:WB_UNITS_WIDTH
|INT:32
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiGenScopeArray:
\_gen_scope_array: (genblk1), line:277, parent:load_store_unit_block
|vpiName:genblk1
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk1
|vpiGenScope:
\_gen_scope: , parent:genblk1
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk1
|vpiContAssign:
\_cont_assign: , line:278
|vpiRhs:
\_ref_obj: (bram.address_range_check), line:278
|vpiName:bram.address_range_check
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk1.bram.address_range_check
|vpiLhs:
\_bit_select: (sub_unit_address_match), line:278
|vpiName:sub_unit_address_match
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk1.sub_unit_address_match
|vpiIndex:
\_ref_obj: (BRAM_ID), line:278
|vpiName:BRAM_ID
|vpiContAssign:
\_cont_assign: , line:279
|vpiRhs:
\_operation: , line:279
|vpiOpType:28
|vpiOperand:
\_bit_select: (sub_unit_address_match), line:279
|vpiName:sub_unit_address_match
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk1.sub_unit_address_match
|vpiIndex:
\_ref_obj: (BRAM_ID), line:279
|vpiName:BRAM_ID
|vpiOperand:
\_ref_obj: (issue_request), line:279
|vpiName:issue_request
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk1.issue_request
|vpiLhs:
\_ref_obj: (bram.new_request), line:279
|vpiName:bram.new_request
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk1.bram.new_request
|vpiContAssign:
\_cont_assign: , line:281
|vpiRhs:
\_ref_obj: (bram.ready), line:281
|vpiName:bram.ready
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk1.bram.ready
|vpiLhs:
\_bit_select: (unit_ready), line:281
|vpiName:unit_ready
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk1.unit_ready
|vpiIndex:
\_ref_obj: (BRAM_ID), line:281
|vpiName:BRAM_ID
|vpiContAssign:
\_cont_assign: , line:282
|vpiRhs:
\_ref_obj: (bram.data_valid), line:282
|vpiName:bram.data_valid
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk1.bram.data_valid
|vpiLhs:
\_bit_select: (unit_data_valid), line:282
|vpiName:unit_data_valid
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk1.unit_data_valid
|vpiIndex:
\_ref_obj: (BRAM_ID), line:282
|vpiName:BRAM_ID
|vpiModule:
\_module: work@dbram (d_bram), file:third_party/cores/taiga/core/load_store_unit.sv, line:284
|vpiDefName:work@dbram
|vpiName:d_bram
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk1.d_bram
|vpiPort:
\_port: (clk), line:27, parent:d_bram
|vpiName:clk
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (clk), line:284
|vpiName:clk
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (clk), line:27, parent:d_bram
|vpiName:clk
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk1.d_bram.clk
|vpiNetType:36
|vpiPort:
\_port: (rst), line:28, parent:d_bram
|vpiName:rst
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (rst), line:284
|vpiName:rst
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (rst), line:28, parent:d_bram
|vpiName:rst
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk1.d_bram.rst
|vpiNetType:36
|vpiPort:
\_port: (ls_inputs), line:30, parent:d_bram
|vpiName:ls_inputs
|vpiDirection:1
|vpiTypedef:
\_struct_typespec: (data_access_shared_inputs_t), line:427
|vpiHighConn:
\_ref_obj: (ls_inputs), line:284
|vpiName:ls_inputs
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (ls_inputs), line:30, parent:d_bram
|vpiName:ls_inputs
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk1.d_bram.ls_inputs
|vpiPort:
\_port: (ls), line:31, parent:d_bram
|vpiName:ls
|vpiDirection:5
|vpiHighConn:
\_ref_obj: (ls), line:284
|vpiName:ls
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_modport: (sub_unit)
|vpiName:sub_unit
|vpiIODecl:
\_io_decl: (new_request)
|vpiName:new_request
|vpiDirection:1
|vpiExpr:
\_logic_net: (new_request), line:215
|vpiName:new_request
|vpiNetType:36
|vpiIODecl:
\_io_decl: (data_valid)
|vpiName:data_valid
|vpiDirection:2
|vpiExpr:
\_logic_net: (data_valid), line:213
|vpiName:data_valid
|vpiNetType:36
|vpiIODecl:
\_io_decl: (ready)
|vpiName:ready
|vpiDirection:2
|vpiExpr:
\_logic_net: (ready), line:214
|vpiName:ready
|vpiNetType:36
|vpiInterface:
\_interface: work@ls_sub_unit_interface (ls), file:third_party/cores/taiga/core/load_store_unit.sv, line:284
|vpiDefName:work@ls_sub_unit_interface
|vpiName:ls
|vpiModport:
\_modport: (ls)
|vpiName:ls
|vpiIODecl:
\_io_decl: (new_request)
|vpiName:new_request
|vpiDirection:2
|vpiExpr:
\_logic_net: (new_request), line:215
|vpiIODecl:
\_io_decl: (data_valid)
|vpiName:data_valid
|vpiDirection:1
|vpiExpr:
\_logic_net: (data_valid), line:213
|vpiIODecl:
\_io_decl: (ready)
|vpiName:ready
|vpiDirection:1
|vpiExpr:
\_logic_net: (ready), line:214
|vpiInterface:
\_interface: work@ls_sub_unit_interface (ls), file:third_party/cores/taiga/core/load_store_unit.sv, line:284
|vpiModport:
\_modport: (sub_unit)
|vpiPort:
\_port: (data_out), line:32, parent:d_bram
|vpiName:data_out
|vpiDirection:2
|vpiHighConn:
\_ref_obj: (data_out), line:284
|vpiName:data_out
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (data_out), line:29
|vpiName:data_out
|vpiNetType:36
|vpiRange:
\_range: , line:29
|vpiLeftRange:
\_constant: , line:29
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:29
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiPort:
\_port: (data_bram), line:34, parent:d_bram
|vpiName:data_bram
|vpiDirection:5
|vpiHighConn:
\_ref_obj: (data_bram), line:284
|vpiName:data_bram
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_modport: (master)
|vpiName:master
|vpiIODecl:
\_io_decl: (addr)
|vpiName:addr
|vpiDirection:2
|vpiExpr:
\_logic_net: (addr), line:25
|vpiName:addr
|vpiNetType:36
|vpiRange:
\_range: , line:25
|vpiLeftRange:
\_constant: , line:25
|vpiConstType:7
|vpiDecompile:29
|vpiSize:32
|INT:29
|vpiRightRange:
\_constant: , line:25
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (en)
|vpiName:en
|vpiDirection:2
|vpiExpr:
\_logic_net: (en), line:26
|vpiName:en
|vpiNetType:36
|vpiIODecl:
\_io_decl: (be)
|vpiName:be
|vpiDirection:2
|vpiExpr:
\_logic_net: (be), line:27
|vpiName:be
|vpiNetType:36
|vpiRange:
\_range: , line:27
|vpiLeftRange:
\_constant: , line:27
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiRightRange:
\_constant: , line:27
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (data_in)
|vpiName:data_in
|vpiDirection:2
|vpiExpr:
\_logic_net: (data_in), line:28
|vpiName:data_in
|vpiNetType:36
|vpiRange:
\_range: , line:28
|vpiLeftRange:
\_constant: , line:28
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:28
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (data_out)
|vpiName:data_out
|vpiDirection:1
|vpiExpr:
\_logic_net: (data_out), line:29
|vpiInterface:
\_interface: work@local_memory_interface (data_bram), file:third_party/cores/taiga/core/load_store_unit.sv, line:284
|vpiDefName:work@local_memory_interface
|vpiName:data_bram
|vpiModport:
\_modport: (master)
|vpiModport:
\_modport: (slave)
|vpiName:slave
|vpiIODecl:
\_io_decl: (addr)
|vpiName:addr
|vpiDirection:1
|vpiExpr:
\_logic_net: (addr), line:25
|vpiIODecl:
\_io_decl: (en)
|vpiName:en
|vpiDirection:1
|vpiExpr:
\_logic_net: (en), line:26
|vpiIODecl:
\_io_decl: (be)
|vpiName:be
|vpiDirection:1
|vpiExpr:
\_logic_net: (be), line:27
|vpiIODecl:
\_io_decl: (data_in)
|vpiName:data_in
|vpiDirection:1
|vpiExpr:
\_logic_net: (data_in), line:28
|vpiIODecl:
\_io_decl: (data_out)
|vpiName:data_out
|vpiDirection:2
|vpiExpr:
\_logic_net: (data_out), line:29
|vpiInterface:
\_interface: work@local_memory_interface (data_bram), file:third_party/cores/taiga/core/load_store_unit.sv, line:284
|vpiNet:
\_logic_net: (clk), line:27, parent:d_bram
|vpiNet:
\_logic_net: (rst), line:28, parent:d_bram
|vpiNet:
\_logic_net: (ls_inputs), line:30, parent:d_bram
|vpiNet:
\_logic_net: (data_out), line:32, parent:d_bram
|vpiName:data_out
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk1.d_bram.data_out
|vpiNetType:36
|vpiRange:
\_range: , line:32
|vpiLeftRange:
\_constant: , line:32
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:32
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (ls), line:31, parent:d_bram
|vpiName:ls
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk1.d_bram.ls
|vpiNet:
\_logic_net: (data_bram), line:34, parent:d_bram
|vpiName:data_bram
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk1.d_bram.data_bram
|vpiParameter:
\_parameter: (ALU_UNIT_WB_ID), line:190
|vpiName:ALU_UNIT_WB_ID
|INT:32
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (BRANCH_PREDICTOR_WAYS), line:159
|vpiName:BRANCH_PREDICTOR_WAYS
|INT:9
|vpiParameter:
\_parameter: (BRANCH_TABLE_ENTRIES), line:160
|vpiName:BRANCH_TABLE_ENTRIES
|INT:4
|vpiParameter:
\_parameter: (BRANCH_UNIT_ID), line:195
|vpiName:BRANCH_UNIT_ID
|INT:8
|vpiParameter:
\_parameter: (BUS_ADDR_H), line:107
|vpiName:BUS_ADDR_H
|INT:1
|vpiParameter:
\_parameter: (BUS_ADDR_L), line:106
|vpiName:BUS_ADDR_L
|INT:0
|vpiParameter:
\_parameter: (BUS_BIT_CHECK), line:108
|vpiName:BUS_BIT_CHECK
|INT:1
|vpiParameter:
\_parameter: (BUS_TYPE), line:89
|vpiName:BUS_TYPE
|INT:5
|vpiParameter:
\_parameter: (COUNTER_W), line:42
|vpiName:COUNTER_W
|INT:33
|vpiParameter:
\_parameter: (CPU_ID), line:38
|vpiName:CPU_ID
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_ADDR_WIDTH), line:113
|vpiName:C_M_AXI_ADDR_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_DATA_WIDTH), line:114
|vpiName:C_M_AXI_DATA_WIDTH
|INT:1
|vpiParameter:
\_parameter: (DCACHE_LINES), line:133
|vpiName:DCACHE_LINES
|INT:-2146435073
|vpiParameter:
\_parameter: (DCACHE_LINE_ADDR_W), line:135
|vpiName:DCACHE_LINE_ADDR_W
|INT:1073741824
|vpiParameter:
\_parameter: (DCACHE_LINE_W), line:136
|vpiName:DCACHE_LINE_W
|INT:1342177279
|vpiParameter:
\_parameter: (DCACHE_SUB_LINE_ADDR_W), line:137
|vpiName:DCACHE_SUB_LINE_ADDR_W
|INT:4
|vpiParameter:
\_parameter: (DCACHE_TAG_W), line:138
|vpiName:DCACHE_TAG_W
|INT:1610612736
|vpiParameter:
\_parameter: (DCACHE_WAYS), line:134
|vpiName:DCACHE_WAYS
|INT:4
|vpiParameter:
\_parameter: (DIV_ALGORITHM), line:67
|vpiName:DIV_ALGORITHM
|INT:0
|vpiParameter:
\_parameter: (DIV_UNIT_WB_ID), line:192
|vpiName:DIV_UNIT_WB_ID
|INT:2
|vpiParameter:
\_parameter: (DTLB_DEPTH), line:152
|vpiName:DTLB_DEPTH
|INT:512
|vpiParameter:
\_parameter: (DTLB_WAYS), line:151
|vpiName:DTLB_WAYS
|INT:32
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (ENABLE_M_MODE), line:34
|vpiName:ENABLE_M_MODE
|INT:1
|vpiParameter:
\_parameter: (ENABLE_S_MODE), line:36
|vpiName:ENABLE_S_MODE
|INT:0
|vpiParameter:
\_parameter: (ENABLE_TRACE_INTERFACE), line:172
|vpiName:ENABLE_TRACE_INTERFACE
|INT:2
|vpiParameter:
\_parameter: (FETCH_BUFFER_DEPTH), line:168
|vpiName:FETCH_BUFFER_DEPTH
|INT:512
|vpiParameter:
\_parameter: (FPGA_VENDOR), line:27
|vpiName:FPGA_VENDOR
|STRING:"xilinx"
|vpiParameter:
\_parameter: (GC_UNIT_ID), line:196
|vpiName:GC_UNIT_ID
|INT:4
|vpiParameter:
\_parameter: (ICACHE_LINES), line:121
|vpiName:ICACHE_LINES
|INT:2
|vpiParameter:
\_parameter: (ICACHE_LINE_ADDR_W), line:123
|vpiName:ICACHE_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_LINE_W), line:124
|vpiName:ICACHE_LINE_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_SUB_LINE_ADDR_W), line:125
|vpiName:ICACHE_SUB_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_TAG_W), line:126
|vpiName:ICACHE_TAG_W
|INT:-2147483648
|vpiParameter:
\_parameter: (ICACHE_WAYS), line:122
|vpiName:ICACHE_WAYS
|INT:1
|vpiParameter:
\_parameter: (ITLB_DEPTH), line:146
|vpiName:ITLB_DEPTH
|INT:32
|vpiParameter:
\_parameter: (ITLB_WAYS), line:145
|vpiName:ITLB_WAYS
|INT:4
|vpiParameter:
\_parameter: (L1_CONNECTIONS), line:177
|vpiName:L1_CONNECTIONS
|INT:9
|vpiParameter:
\_parameter: (L1_DCACHE_ID), line:178
|vpiName:L1_DCACHE_ID
|INT:4
|vpiParameter:
\_parameter: (L1_DMMU_ID), line:179
|vpiName:L1_DMMU_ID
|INT:2
|vpiParameter:
\_parameter: (L1_ICACHE_ID), line:180
|vpiName:L1_ICACHE_ID
|INT:19
|vpiParameter:
\_parameter: (L1_IMMU_ID), line:181
|vpiName:L1_IMMU_ID
|INT:0
|vpiParameter:
\_parameter: (LS_UNIT_WB_ID), line:191
|vpiName:LS_UNIT_WB_ID
|INT:1
|vpiParameter:
\_parameter: (MAX_INFLIGHT_COUNT), line:167
|vpiName:MAX_INFLIGHT_COUNT
|INT:19
|vpiParameter:
\_parameter: (MEMORY_ADDR_H), line:103
|vpiName:MEMORY_ADDR_H
|INT:12
|vpiParameter:
\_parameter: (MEMORY_ADDR_L), line:102
|vpiName:MEMORY_ADDR_L
|INT:11
|vpiParameter:
\_parameter: (MEMORY_BIT_CHECK), line:104
|vpiName:MEMORY_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (MUL_UNIT_WB_ID), line:193
|vpiName:MUL_UNIT_WB_ID
|INT:512
|vpiParameter:
\_parameter: (NUM_UNITS), line:188
|vpiName:NUM_UNITS
|INT:2
|vpiParameter:
\_parameter: (NUM_WB_UNITS), line:186
|vpiName:NUM_WB_UNITS
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (RAS_DEPTH), line:161
|vpiName:RAS_DEPTH
|INT:2
|vpiParameter:
\_parameter: (RESET_VEC), line:39
|vpiName:RESET_VEC
|INT:-2147483648
|vpiParameter:
\_parameter: (SCRATCH_ADDR_H), line:99
|vpiName:SCRATCH_ADDR_H
|INT:9
|vpiParameter:
\_parameter: (SCRATCH_ADDR_L), line:98
|vpiName:SCRATCH_ADDR_L
|INT:8
|vpiParameter:
\_parameter: (SCRATCH_BIT_CHECK), line:100
|vpiName:SCRATCH_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (USE_AMO), line:70
|vpiName:USE_AMO
|INT:1
|vpiParameter:
\_parameter: (USE_BRANCH_PREDICTOR), line:158
|vpiName:USE_BRANCH_PREDICTOR
|INT:2
|vpiParameter:
\_parameter: (USE_BUS), line:88
|vpiName:USE_BUS
|INT:4
|vpiParameter:
\_parameter: (USE_DCACHE), line:92
|vpiName:USE_DCACHE
|INT:6
|vpiParameter:
\_parameter: (USE_DIV), line:49
|vpiName:USE_DIV
|INT:1
|vpiParameter:
\_parameter: (USE_DTAG_INVALIDATIONS), line:140
|vpiName:USE_DTAG_INVALIDATIONS
|INT:1879048191
|vpiParameter:
\_parameter: (USE_D_SCRATCH_MEM), line:79
|vpiName:USE_D_SCRATCH_MEM
|INT:3
|vpiParameter:
\_parameter: (USE_ICACHE), line:93
|vpiName:USE_ICACHE
|INT:7
|vpiParameter:
\_parameter: (USE_I_SCRATCH_MEM), line:78
|vpiName:USE_I_SCRATCH_MEM
|INT:2
|vpiParameter:
\_parameter: (USE_MUL), line:48
|vpiName:USE_MUL
|INT:1
|vpiParameter:
\_parameter: (WB_UNITS_WIDTH), line:187
|vpiName:WB_UNITS_WIDTH
|INT:32
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiParameter:
\_parameter: (ALU_UNIT_WB_ID), line:190
|vpiName:ALU_UNIT_WB_ID
|INT:32
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (BRANCH_PREDICTOR_WAYS), line:159
|vpiName:BRANCH_PREDICTOR_WAYS
|INT:9
|vpiParameter:
\_parameter: (BRANCH_TABLE_ENTRIES), line:160
|vpiName:BRANCH_TABLE_ENTRIES
|INT:4
|vpiParameter:
\_parameter: (BRANCH_UNIT_ID), line:195
|vpiName:BRANCH_UNIT_ID
|INT:8
|vpiParameter:
\_parameter: (BUS_ADDR_H), line:107
|vpiName:BUS_ADDR_H
|INT:1
|vpiParameter:
\_parameter: (BUS_ADDR_L), line:106
|vpiName:BUS_ADDR_L
|INT:0
|vpiParameter:
\_parameter: (BUS_BIT_CHECK), line:108
|vpiName:BUS_BIT_CHECK
|INT:1
|vpiParameter:
\_parameter: (BUS_TYPE), line:89
|vpiName:BUS_TYPE
|INT:5
|vpiParameter:
\_parameter: (COUNTER_W), line:42
|vpiName:COUNTER_W
|INT:33
|vpiParameter:
\_parameter: (CPU_ID), line:38
|vpiName:CPU_ID
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_ADDR_WIDTH), line:113
|vpiName:C_M_AXI_ADDR_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_DATA_WIDTH), line:114
|vpiName:C_M_AXI_DATA_WIDTH
|INT:1
|vpiParameter:
\_parameter: (DCACHE_LINES), line:133
|vpiName:DCACHE_LINES
|INT:-2146435073
|vpiParameter:
\_parameter: (DCACHE_LINE_ADDR_W), line:135
|vpiName:DCACHE_LINE_ADDR_W
|INT:1073741824
|vpiParameter:
\_parameter: (DCACHE_LINE_W), line:136
|vpiName:DCACHE_LINE_W
|INT:1342177279
|vpiParameter:
\_parameter: (DCACHE_SUB_LINE_ADDR_W), line:137
|vpiName:DCACHE_SUB_LINE_ADDR_W
|INT:4
|vpiParameter:
\_parameter: (DCACHE_TAG_W), line:138
|vpiName:DCACHE_TAG_W
|INT:1610612736
|vpiParameter:
\_parameter: (DCACHE_WAYS), line:134
|vpiName:DCACHE_WAYS
|INT:4
|vpiParameter:
\_parameter: (DIV_ALGORITHM), line:67
|vpiName:DIV_ALGORITHM
|INT:0
|vpiParameter:
\_parameter: (DIV_UNIT_WB_ID), line:192
|vpiName:DIV_UNIT_WB_ID
|INT:2
|vpiParameter:
\_parameter: (DTLB_DEPTH), line:152
|vpiName:DTLB_DEPTH
|INT:512
|vpiParameter:
\_parameter: (DTLB_WAYS), line:151
|vpiName:DTLB_WAYS
|INT:32
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (ENABLE_M_MODE), line:34
|vpiName:ENABLE_M_MODE
|INT:1
|vpiParameter:
\_parameter: (ENABLE_S_MODE), line:36
|vpiName:ENABLE_S_MODE
|INT:0
|vpiParameter:
\_parameter: (ENABLE_TRACE_INTERFACE), line:172
|vpiName:ENABLE_TRACE_INTERFACE
|INT:2
|vpiParameter:
\_parameter: (FETCH_BUFFER_DEPTH), line:168
|vpiName:FETCH_BUFFER_DEPTH
|INT:512
|vpiParameter:
\_parameter: (FPGA_VENDOR), line:27
|vpiName:FPGA_VENDOR
|STRING:"xilinx"
|vpiParameter:
\_parameter: (GC_UNIT_ID), line:196
|vpiName:GC_UNIT_ID
|INT:4
|vpiParameter:
\_parameter: (ICACHE_LINES), line:121
|vpiName:ICACHE_LINES
|INT:2
|vpiParameter:
\_parameter: (ICACHE_LINE_ADDR_W), line:123
|vpiName:ICACHE_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_LINE_W), line:124
|vpiName:ICACHE_LINE_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_SUB_LINE_ADDR_W), line:125
|vpiName:ICACHE_SUB_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_TAG_W), line:126
|vpiName:ICACHE_TAG_W
|INT:-2147483648
|vpiParameter:
\_parameter: (ICACHE_WAYS), line:122
|vpiName:ICACHE_WAYS
|INT:1
|vpiParameter:
\_parameter: (ITLB_DEPTH), line:146
|vpiName:ITLB_DEPTH
|INT:32
|vpiParameter:
\_parameter: (ITLB_WAYS), line:145
|vpiName:ITLB_WAYS
|INT:4
|vpiParameter:
\_parameter: (L1_CONNECTIONS), line:177
|vpiName:L1_CONNECTIONS
|INT:9
|vpiParameter:
\_parameter: (L1_DCACHE_ID), line:178
|vpiName:L1_DCACHE_ID
|INT:4
|vpiParameter:
\_parameter: (L1_DMMU_ID), line:179
|vpiName:L1_DMMU_ID
|INT:2
|vpiParameter:
\_parameter: (L1_ICACHE_ID), line:180
|vpiName:L1_ICACHE_ID
|INT:19
|vpiParameter:
\_parameter: (L1_IMMU_ID), line:181
|vpiName:L1_IMMU_ID
|INT:0
|vpiParameter:
\_parameter: (LS_UNIT_WB_ID), line:191
|vpiName:LS_UNIT_WB_ID
|INT:1
|vpiParameter:
\_parameter: (MAX_INFLIGHT_COUNT), line:167
|vpiName:MAX_INFLIGHT_COUNT
|INT:19
|vpiParameter:
\_parameter: (MEMORY_ADDR_H), line:103
|vpiName:MEMORY_ADDR_H
|INT:12
|vpiParameter:
\_parameter: (MEMORY_ADDR_L), line:102
|vpiName:MEMORY_ADDR_L
|INT:11
|vpiParameter:
\_parameter: (MEMORY_BIT_CHECK), line:104
|vpiName:MEMORY_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (MUL_UNIT_WB_ID), line:193
|vpiName:MUL_UNIT_WB_ID
|INT:512
|vpiParameter:
\_parameter: (NUM_UNITS), line:188
|vpiName:NUM_UNITS
|INT:2
|vpiParameter:
\_parameter: (NUM_WB_UNITS), line:186
|vpiName:NUM_WB_UNITS
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (RAS_DEPTH), line:161
|vpiName:RAS_DEPTH
|INT:2
|vpiParameter:
\_parameter: (RESET_VEC), line:39
|vpiName:RESET_VEC
|INT:-2147483648
|vpiParameter:
\_parameter: (SCRATCH_ADDR_H), line:99
|vpiName:SCRATCH_ADDR_H
|INT:9
|vpiParameter:
\_parameter: (SCRATCH_ADDR_L), line:98
|vpiName:SCRATCH_ADDR_L
|INT:8
|vpiParameter:
\_parameter: (SCRATCH_BIT_CHECK), line:100
|vpiName:SCRATCH_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (USE_AMO), line:70
|vpiName:USE_AMO
|INT:1
|vpiParameter:
\_parameter: (USE_BRANCH_PREDICTOR), line:158
|vpiName:USE_BRANCH_PREDICTOR
|INT:2
|vpiParameter:
\_parameter: (USE_BUS), line:88
|vpiName:USE_BUS
|INT:4
|vpiParameter:
\_parameter: (USE_DCACHE), line:92
|vpiName:USE_DCACHE
|INT:6
|vpiParameter:
\_parameter: (USE_DIV), line:49
|vpiName:USE_DIV
|INT:1
|vpiParameter:
\_parameter: (USE_DTAG_INVALIDATIONS), line:140
|vpiName:USE_DTAG_INVALIDATIONS
|INT:1879048191
|vpiParameter:
\_parameter: (USE_D_SCRATCH_MEM), line:79
|vpiName:USE_D_SCRATCH_MEM
|INT:3
|vpiParameter:
\_parameter: (USE_ICACHE), line:93
|vpiName:USE_ICACHE
|INT:7
|vpiParameter:
\_parameter: (USE_I_SCRATCH_MEM), line:78
|vpiName:USE_I_SCRATCH_MEM
|INT:2
|vpiParameter:
\_parameter: (USE_MUL), line:48
|vpiName:USE_MUL
|INT:1
|vpiParameter:
\_parameter: (WB_UNITS_WIDTH), line:187
|vpiName:WB_UNITS_WIDTH
|INT:32
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiGenScopeArray:
\_gen_scope_array: (genblk2), line:288, parent:load_store_unit_block
|vpiName:genblk2
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk2
|vpiGenScope:
\_gen_scope: , parent:genblk2
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk2
|vpiContAssign:
\_cont_assign: , line:289
|vpiRhs:
\_ref_obj: (bus.address_range_check), line:289
|vpiName:bus.address_range_check
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk2.bus.address_range_check
|vpiLhs:
\_bit_select: (sub_unit_address_match), line:289
|vpiName:sub_unit_address_match
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk2.sub_unit_address_match
|vpiIndex:
\_ref_obj: (BUS_ID), line:289
|vpiName:BUS_ID
|vpiContAssign:
\_cont_assign: , line:290
|vpiRhs:
\_operation: , line:290
|vpiOpType:28
|vpiOperand:
\_bit_select: (sub_unit_address_match), line:290
|vpiName:sub_unit_address_match
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk2.sub_unit_address_match
|vpiIndex:
\_ref_obj: (BUS_ID), line:290
|vpiName:BUS_ID
|vpiOperand:
\_ref_obj: (issue_request), line:290
|vpiName:issue_request
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk2.issue_request
|vpiLhs:
\_ref_obj: (bus.new_request), line:290
|vpiName:bus.new_request
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk2.bus.new_request
|vpiContAssign:
\_cont_assign: , line:292
|vpiRhs:
\_ref_obj: (bus.ready), line:292
|vpiName:bus.ready
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk2.bus.ready
|vpiLhs:
\_bit_select: (unit_ready), line:292
|vpiName:unit_ready
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk2.unit_ready
|vpiIndex:
\_ref_obj: (BUS_ID), line:292
|vpiName:BUS_ID
|vpiContAssign:
\_cont_assign: , line:293
|vpiRhs:
\_ref_obj: (bus.data_valid), line:293
|vpiName:bus.data_valid
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk2.bus.data_valid
|vpiLhs:
\_bit_select: (unit_data_valid), line:293
|vpiName:unit_data_valid
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk2.unit_data_valid
|vpiIndex:
\_ref_obj: (BUS_ID), line:293
|vpiName:BUS_ID
|vpiGenScopeArray:
\_gen_scope_array: (genblk1), line:297
|vpiName:genblk1
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk2.genblk1
|vpiGenScope:
\_gen_scope: , parent:genblk1
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk2.genblk1
|vpiGenScopeArray:
\_gen_scope_array: (genblk1), line:299
|vpiName:genblk1
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk2.genblk1.genblk1
|vpiGenScope:
\_gen_scope: , parent:genblk1
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk2.genblk1.genblk1
|vpiParameter:
\_parameter: (ALU_UNIT_WB_ID), line:190
|vpiName:ALU_UNIT_WB_ID
|INT:32
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (BRANCH_PREDICTOR_WAYS), line:159
|vpiName:BRANCH_PREDICTOR_WAYS
|INT:9
|vpiParameter:
\_parameter: (BRANCH_TABLE_ENTRIES), line:160
|vpiName:BRANCH_TABLE_ENTRIES
|INT:4
|vpiParameter:
\_parameter: (BRANCH_UNIT_ID), line:195
|vpiName:BRANCH_UNIT_ID
|INT:8
|vpiParameter:
\_parameter: (BUS_ADDR_H), line:107
|vpiName:BUS_ADDR_H
|INT:1
|vpiParameter:
\_parameter: (BUS_ADDR_L), line:106
|vpiName:BUS_ADDR_L
|INT:0
|vpiParameter:
\_parameter: (BUS_BIT_CHECK), line:108
|vpiName:BUS_BIT_CHECK
|INT:1
|vpiParameter:
\_parameter: (BUS_TYPE), line:89
|vpiName:BUS_TYPE
|INT:5
|vpiParameter:
\_parameter: (COUNTER_W), line:42
|vpiName:COUNTER_W
|INT:33
|vpiParameter:
\_parameter: (CPU_ID), line:38
|vpiName:CPU_ID
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_ADDR_WIDTH), line:113
|vpiName:C_M_AXI_ADDR_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_DATA_WIDTH), line:114
|vpiName:C_M_AXI_DATA_WIDTH
|INT:1
|vpiParameter:
\_parameter: (DCACHE_LINES), line:133
|vpiName:DCACHE_LINES
|INT:-2146435073
|vpiParameter:
\_parameter: (DCACHE_LINE_ADDR_W), line:135
|vpiName:DCACHE_LINE_ADDR_W
|INT:1073741824
|vpiParameter:
\_parameter: (DCACHE_LINE_W), line:136
|vpiName:DCACHE_LINE_W
|INT:1342177279
|vpiParameter:
\_parameter: (DCACHE_SUB_LINE_ADDR_W), line:137
|vpiName:DCACHE_SUB_LINE_ADDR_W
|INT:4
|vpiParameter:
\_parameter: (DCACHE_TAG_W), line:138
|vpiName:DCACHE_TAG_W
|INT:1610612736
|vpiParameter:
\_parameter: (DCACHE_WAYS), line:134
|vpiName:DCACHE_WAYS
|INT:4
|vpiParameter:
\_parameter: (DIV_ALGORITHM), line:67
|vpiName:DIV_ALGORITHM
|INT:0
|vpiParameter:
\_parameter: (DIV_UNIT_WB_ID), line:192
|vpiName:DIV_UNIT_WB_ID
|INT:2
|vpiParameter:
\_parameter: (DTLB_DEPTH), line:152
|vpiName:DTLB_DEPTH
|INT:512
|vpiParameter:
\_parameter: (DTLB_WAYS), line:151
|vpiName:DTLB_WAYS
|INT:32
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (ENABLE_M_MODE), line:34
|vpiName:ENABLE_M_MODE
|INT:1
|vpiParameter:
\_parameter: (ENABLE_S_MODE), line:36
|vpiName:ENABLE_S_MODE
|INT:0
|vpiParameter:
\_parameter: (ENABLE_TRACE_INTERFACE), line:172
|vpiName:ENABLE_TRACE_INTERFACE
|INT:2
|vpiParameter:
\_parameter: (FETCH_BUFFER_DEPTH), line:168
|vpiName:FETCH_BUFFER_DEPTH
|INT:512
|vpiParameter:
\_parameter: (FPGA_VENDOR), line:27
|vpiName:FPGA_VENDOR
|STRING:"xilinx"
|vpiParameter:
\_parameter: (GC_UNIT_ID), line:196
|vpiName:GC_UNIT_ID
|INT:4
|vpiParameter:
\_parameter: (ICACHE_LINES), line:121
|vpiName:ICACHE_LINES
|INT:2
|vpiParameter:
\_parameter: (ICACHE_LINE_ADDR_W), line:123
|vpiName:ICACHE_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_LINE_W), line:124
|vpiName:ICACHE_LINE_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_SUB_LINE_ADDR_W), line:125
|vpiName:ICACHE_SUB_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_TAG_W), line:126
|vpiName:ICACHE_TAG_W
|INT:-2147483648
|vpiParameter:
\_parameter: (ICACHE_WAYS), line:122
|vpiName:ICACHE_WAYS
|INT:1
|vpiParameter:
\_parameter: (ITLB_DEPTH), line:146
|vpiName:ITLB_DEPTH
|INT:32
|vpiParameter:
\_parameter: (ITLB_WAYS), line:145
|vpiName:ITLB_WAYS
|INT:4
|vpiParameter:
\_parameter: (L1_CONNECTIONS), line:177
|vpiName:L1_CONNECTIONS
|INT:9
|vpiParameter:
\_parameter: (L1_DCACHE_ID), line:178
|vpiName:L1_DCACHE_ID
|INT:4
|vpiParameter:
\_parameter: (L1_DMMU_ID), line:179
|vpiName:L1_DMMU_ID
|INT:2
|vpiParameter:
\_parameter: (L1_ICACHE_ID), line:180
|vpiName:L1_ICACHE_ID
|INT:19
|vpiParameter:
\_parameter: (L1_IMMU_ID), line:181
|vpiName:L1_IMMU_ID
|INT:0
|vpiParameter:
\_parameter: (LS_UNIT_WB_ID), line:191
|vpiName:LS_UNIT_WB_ID
|INT:1
|vpiParameter:
\_parameter: (MAX_INFLIGHT_COUNT), line:167
|vpiName:MAX_INFLIGHT_COUNT
|INT:19
|vpiParameter:
\_parameter: (MEMORY_ADDR_H), line:103
|vpiName:MEMORY_ADDR_H
|INT:12
|vpiParameter:
\_parameter: (MEMORY_ADDR_L), line:102
|vpiName:MEMORY_ADDR_L
|INT:11
|vpiParameter:
\_parameter: (MEMORY_BIT_CHECK), line:104
|vpiName:MEMORY_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (MUL_UNIT_WB_ID), line:193
|vpiName:MUL_UNIT_WB_ID
|INT:512
|vpiParameter:
\_parameter: (NUM_UNITS), line:188
|vpiName:NUM_UNITS
|INT:2
|vpiParameter:
\_parameter: (NUM_WB_UNITS), line:186
|vpiName:NUM_WB_UNITS
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (RAS_DEPTH), line:161
|vpiName:RAS_DEPTH
|INT:2
|vpiParameter:
\_parameter: (RESET_VEC), line:39
|vpiName:RESET_VEC
|INT:-2147483648
|vpiParameter:
\_parameter: (SCRATCH_ADDR_H), line:99
|vpiName:SCRATCH_ADDR_H
|INT:9
|vpiParameter:
\_parameter: (SCRATCH_ADDR_L), line:98
|vpiName:SCRATCH_ADDR_L
|INT:8
|vpiParameter:
\_parameter: (SCRATCH_BIT_CHECK), line:100
|vpiName:SCRATCH_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (USE_AMO), line:70
|vpiName:USE_AMO
|INT:1
|vpiParameter:
\_parameter: (USE_BRANCH_PREDICTOR), line:158
|vpiName:USE_BRANCH_PREDICTOR
|INT:2
|vpiParameter:
\_parameter: (USE_BUS), line:88
|vpiName:USE_BUS
|INT:4
|vpiParameter:
\_parameter: (USE_DCACHE), line:92
|vpiName:USE_DCACHE
|INT:6
|vpiParameter:
\_parameter: (USE_DIV), line:49
|vpiName:USE_DIV
|INT:1
|vpiParameter:
\_parameter: (USE_DTAG_INVALIDATIONS), line:140
|vpiName:USE_DTAG_INVALIDATIONS
|INT:1879048191
|vpiParameter:
\_parameter: (USE_D_SCRATCH_MEM), line:79
|vpiName:USE_D_SCRATCH_MEM
|INT:3
|vpiParameter:
\_parameter: (USE_ICACHE), line:93
|vpiName:USE_ICACHE
|INT:7
|vpiParameter:
\_parameter: (USE_I_SCRATCH_MEM), line:78
|vpiName:USE_I_SCRATCH_MEM
|INT:2
|vpiParameter:
\_parameter: (USE_MUL), line:48
|vpiName:USE_MUL
|INT:1
|vpiParameter:
\_parameter: (WB_UNITS_WIDTH), line:187
|vpiName:WB_UNITS_WIDTH
|INT:32
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiParameter:
\_parameter: (ALU_UNIT_WB_ID), line:190
|vpiName:ALU_UNIT_WB_ID
|INT:32
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (BRANCH_PREDICTOR_WAYS), line:159
|vpiName:BRANCH_PREDICTOR_WAYS
|INT:9
|vpiParameter:
\_parameter: (BRANCH_TABLE_ENTRIES), line:160
|vpiName:BRANCH_TABLE_ENTRIES
|INT:4
|vpiParameter:
\_parameter: (BRANCH_UNIT_ID), line:195
|vpiName:BRANCH_UNIT_ID
|INT:8
|vpiParameter:
\_parameter: (BUS_ADDR_H), line:107
|vpiName:BUS_ADDR_H
|INT:1
|vpiParameter:
\_parameter: (BUS_ADDR_L), line:106
|vpiName:BUS_ADDR_L
|INT:0
|vpiParameter:
\_parameter: (BUS_BIT_CHECK), line:108
|vpiName:BUS_BIT_CHECK
|INT:1
|vpiParameter:
\_parameter: (BUS_TYPE), line:89
|vpiName:BUS_TYPE
|INT:5
|vpiParameter:
\_parameter: (COUNTER_W), line:42
|vpiName:COUNTER_W
|INT:33
|vpiParameter:
\_parameter: (CPU_ID), line:38
|vpiName:CPU_ID
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_ADDR_WIDTH), line:113
|vpiName:C_M_AXI_ADDR_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_DATA_WIDTH), line:114
|vpiName:C_M_AXI_DATA_WIDTH
|INT:1
|vpiParameter:
\_parameter: (DCACHE_LINES), line:133
|vpiName:DCACHE_LINES
|INT:-2146435073
|vpiParameter:
\_parameter: (DCACHE_LINE_ADDR_W), line:135
|vpiName:DCACHE_LINE_ADDR_W
|INT:1073741824
|vpiParameter:
\_parameter: (DCACHE_LINE_W), line:136
|vpiName:DCACHE_LINE_W
|INT:1342177279
|vpiParameter:
\_parameter: (DCACHE_SUB_LINE_ADDR_W), line:137
|vpiName:DCACHE_SUB_LINE_ADDR_W
|INT:4
|vpiParameter:
\_parameter: (DCACHE_TAG_W), line:138
|vpiName:DCACHE_TAG_W
|INT:1610612736
|vpiParameter:
\_parameter: (DCACHE_WAYS), line:134
|vpiName:DCACHE_WAYS
|INT:4
|vpiParameter:
\_parameter: (DIV_ALGORITHM), line:67
|vpiName:DIV_ALGORITHM
|INT:0
|vpiParameter:
\_parameter: (DIV_UNIT_WB_ID), line:192
|vpiName:DIV_UNIT_WB_ID
|INT:2
|vpiParameter:
\_parameter: (DTLB_DEPTH), line:152
|vpiName:DTLB_DEPTH
|INT:512
|vpiParameter:
\_parameter: (DTLB_WAYS), line:151
|vpiName:DTLB_WAYS
|INT:32
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (ENABLE_M_MODE), line:34
|vpiName:ENABLE_M_MODE
|INT:1
|vpiParameter:
\_parameter: (ENABLE_S_MODE), line:36
|vpiName:ENABLE_S_MODE
|INT:0
|vpiParameter:
\_parameter: (ENABLE_TRACE_INTERFACE), line:172
|vpiName:ENABLE_TRACE_INTERFACE
|INT:2
|vpiParameter:
\_parameter: (FETCH_BUFFER_DEPTH), line:168
|vpiName:FETCH_BUFFER_DEPTH
|INT:512
|vpiParameter:
\_parameter: (FPGA_VENDOR), line:27
|vpiName:FPGA_VENDOR
|STRING:"xilinx"
|vpiParameter:
\_parameter: (GC_UNIT_ID), line:196
|vpiName:GC_UNIT_ID
|INT:4
|vpiParameter:
\_parameter: (ICACHE_LINES), line:121
|vpiName:ICACHE_LINES
|INT:2
|vpiParameter:
\_parameter: (ICACHE_LINE_ADDR_W), line:123
|vpiName:ICACHE_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_LINE_W), line:124
|vpiName:ICACHE_LINE_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_SUB_LINE_ADDR_W), line:125
|vpiName:ICACHE_SUB_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_TAG_W), line:126
|vpiName:ICACHE_TAG_W
|INT:-2147483648
|vpiParameter:
\_parameter: (ICACHE_WAYS), line:122
|vpiName:ICACHE_WAYS
|INT:1
|vpiParameter:
\_parameter: (ITLB_DEPTH), line:146
|vpiName:ITLB_DEPTH
|INT:32
|vpiParameter:
\_parameter: (ITLB_WAYS), line:145
|vpiName:ITLB_WAYS
|INT:4
|vpiParameter:
\_parameter: (L1_CONNECTIONS), line:177
|vpiName:L1_CONNECTIONS
|INT:9
|vpiParameter:
\_parameter: (L1_DCACHE_ID), line:178
|vpiName:L1_DCACHE_ID
|INT:4
|vpiParameter:
\_parameter: (L1_DMMU_ID), line:179
|vpiName:L1_DMMU_ID
|INT:2
|vpiParameter:
\_parameter: (L1_ICACHE_ID), line:180
|vpiName:L1_ICACHE_ID
|INT:19
|vpiParameter:
\_parameter: (L1_IMMU_ID), line:181
|vpiName:L1_IMMU_ID
|INT:0
|vpiParameter:
\_parameter: (LS_UNIT_WB_ID), line:191
|vpiName:LS_UNIT_WB_ID
|INT:1
|vpiParameter:
\_parameter: (MAX_INFLIGHT_COUNT), line:167
|vpiName:MAX_INFLIGHT_COUNT
|INT:19
|vpiParameter:
\_parameter: (MEMORY_ADDR_H), line:103
|vpiName:MEMORY_ADDR_H
|INT:12
|vpiParameter:
\_parameter: (MEMORY_ADDR_L), line:102
|vpiName:MEMORY_ADDR_L
|INT:11
|vpiParameter:
\_parameter: (MEMORY_BIT_CHECK), line:104
|vpiName:MEMORY_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (MUL_UNIT_WB_ID), line:193
|vpiName:MUL_UNIT_WB_ID
|INT:512
|vpiParameter:
\_parameter: (NUM_UNITS), line:188
|vpiName:NUM_UNITS
|INT:2
|vpiParameter:
\_parameter: (NUM_WB_UNITS), line:186
|vpiName:NUM_WB_UNITS
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (RAS_DEPTH), line:161
|vpiName:RAS_DEPTH
|INT:2
|vpiParameter:
\_parameter: (RESET_VEC), line:39
|vpiName:RESET_VEC
|INT:-2147483648
|vpiParameter:
\_parameter: (SCRATCH_ADDR_H), line:99
|vpiName:SCRATCH_ADDR_H
|INT:9
|vpiParameter:
\_parameter: (SCRATCH_ADDR_L), line:98
|vpiName:SCRATCH_ADDR_L
|INT:8
|vpiParameter:
\_parameter: (SCRATCH_BIT_CHECK), line:100
|vpiName:SCRATCH_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (USE_AMO), line:70
|vpiName:USE_AMO
|INT:1
|vpiParameter:
\_parameter: (USE_BRANCH_PREDICTOR), line:158
|vpiName:USE_BRANCH_PREDICTOR
|INT:2
|vpiParameter:
\_parameter: (USE_BUS), line:88
|vpiName:USE_BUS
|INT:4
|vpiParameter:
\_parameter: (USE_DCACHE), line:92
|vpiName:USE_DCACHE
|INT:6
|vpiParameter:
\_parameter: (USE_DIV), line:49
|vpiName:USE_DIV
|INT:1
|vpiParameter:
\_parameter: (USE_DTAG_INVALIDATIONS), line:140
|vpiName:USE_DTAG_INVALIDATIONS
|INT:1879048191
|vpiParameter:
\_parameter: (USE_D_SCRATCH_MEM), line:79
|vpiName:USE_D_SCRATCH_MEM
|INT:3
|vpiParameter:
\_parameter: (USE_ICACHE), line:93
|vpiName:USE_ICACHE
|INT:7
|vpiParameter:
\_parameter: (USE_I_SCRATCH_MEM), line:78
|vpiName:USE_I_SCRATCH_MEM
|INT:2
|vpiParameter:
\_parameter: (USE_MUL), line:48
|vpiName:USE_MUL
|INT:1
|vpiParameter:
\_parameter: (WB_UNITS_WIDTH), line:187
|vpiName:WB_UNITS_WIDTH
|INT:32
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiParameter:
\_parameter: (ALU_UNIT_WB_ID), line:190
|vpiName:ALU_UNIT_WB_ID
|INT:32
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (BRANCH_PREDICTOR_WAYS), line:159
|vpiName:BRANCH_PREDICTOR_WAYS
|INT:9
|vpiParameter:
\_parameter: (BRANCH_TABLE_ENTRIES), line:160
|vpiName:BRANCH_TABLE_ENTRIES
|INT:4
|vpiParameter:
\_parameter: (BRANCH_UNIT_ID), line:195
|vpiName:BRANCH_UNIT_ID
|INT:8
|vpiParameter:
\_parameter: (BUS_ADDR_H), line:107
|vpiName:BUS_ADDR_H
|INT:1
|vpiParameter:
\_parameter: (BUS_ADDR_L), line:106
|vpiName:BUS_ADDR_L
|INT:0
|vpiParameter:
\_parameter: (BUS_BIT_CHECK), line:108
|vpiName:BUS_BIT_CHECK
|INT:1
|vpiParameter:
\_parameter: (BUS_TYPE), line:89
|vpiName:BUS_TYPE
|INT:5
|vpiParameter:
\_parameter: (COUNTER_W), line:42
|vpiName:COUNTER_W
|INT:33
|vpiParameter:
\_parameter: (CPU_ID), line:38
|vpiName:CPU_ID
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_ADDR_WIDTH), line:113
|vpiName:C_M_AXI_ADDR_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_DATA_WIDTH), line:114
|vpiName:C_M_AXI_DATA_WIDTH
|INT:1
|vpiParameter:
\_parameter: (DCACHE_LINES), line:133
|vpiName:DCACHE_LINES
|INT:-2146435073
|vpiParameter:
\_parameter: (DCACHE_LINE_ADDR_W), line:135
|vpiName:DCACHE_LINE_ADDR_W
|INT:1073741824
|vpiParameter:
\_parameter: (DCACHE_LINE_W), line:136
|vpiName:DCACHE_LINE_W
|INT:1342177279
|vpiParameter:
\_parameter: (DCACHE_SUB_LINE_ADDR_W), line:137
|vpiName:DCACHE_SUB_LINE_ADDR_W
|INT:4
|vpiParameter:
\_parameter: (DCACHE_TAG_W), line:138
|vpiName:DCACHE_TAG_W
|INT:1610612736
|vpiParameter:
\_parameter: (DCACHE_WAYS), line:134
|vpiName:DCACHE_WAYS
|INT:4
|vpiParameter:
\_parameter: (DIV_ALGORITHM), line:67
|vpiName:DIV_ALGORITHM
|INT:0
|vpiParameter:
\_parameter: (DIV_UNIT_WB_ID), line:192
|vpiName:DIV_UNIT_WB_ID
|INT:2
|vpiParameter:
\_parameter: (DTLB_DEPTH), line:152
|vpiName:DTLB_DEPTH
|INT:512
|vpiParameter:
\_parameter: (DTLB_WAYS), line:151
|vpiName:DTLB_WAYS
|INT:32
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (ENABLE_M_MODE), line:34
|vpiName:ENABLE_M_MODE
|INT:1
|vpiParameter:
\_parameter: (ENABLE_S_MODE), line:36
|vpiName:ENABLE_S_MODE
|INT:0
|vpiParameter:
\_parameter: (ENABLE_TRACE_INTERFACE), line:172
|vpiName:ENABLE_TRACE_INTERFACE
|INT:2
|vpiParameter:
\_parameter: (FETCH_BUFFER_DEPTH), line:168
|vpiName:FETCH_BUFFER_DEPTH
|INT:512
|vpiParameter:
\_parameter: (FPGA_VENDOR), line:27
|vpiName:FPGA_VENDOR
|STRING:"xilinx"
|vpiParameter:
\_parameter: (GC_UNIT_ID), line:196
|vpiName:GC_UNIT_ID
|INT:4
|vpiParameter:
\_parameter: (ICACHE_LINES), line:121
|vpiName:ICACHE_LINES
|INT:2
|vpiParameter:
\_parameter: (ICACHE_LINE_ADDR_W), line:123
|vpiName:ICACHE_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_LINE_W), line:124
|vpiName:ICACHE_LINE_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_SUB_LINE_ADDR_W), line:125
|vpiName:ICACHE_SUB_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_TAG_W), line:126
|vpiName:ICACHE_TAG_W
|INT:-2147483648
|vpiParameter:
\_parameter: (ICACHE_WAYS), line:122
|vpiName:ICACHE_WAYS
|INT:1
|vpiParameter:
\_parameter: (ITLB_DEPTH), line:146
|vpiName:ITLB_DEPTH
|INT:32
|vpiParameter:
\_parameter: (ITLB_WAYS), line:145
|vpiName:ITLB_WAYS
|INT:4
|vpiParameter:
\_parameter: (L1_CONNECTIONS), line:177
|vpiName:L1_CONNECTIONS
|INT:9
|vpiParameter:
\_parameter: (L1_DCACHE_ID), line:178
|vpiName:L1_DCACHE_ID
|INT:4
|vpiParameter:
\_parameter: (L1_DMMU_ID), line:179
|vpiName:L1_DMMU_ID
|INT:2
|vpiParameter:
\_parameter: (L1_ICACHE_ID), line:180
|vpiName:L1_ICACHE_ID
|INT:19
|vpiParameter:
\_parameter: (L1_IMMU_ID), line:181
|vpiName:L1_IMMU_ID
|INT:0
|vpiParameter:
\_parameter: (LS_UNIT_WB_ID), line:191
|vpiName:LS_UNIT_WB_ID
|INT:1
|vpiParameter:
\_parameter: (MAX_INFLIGHT_COUNT), line:167
|vpiName:MAX_INFLIGHT_COUNT
|INT:19
|vpiParameter:
\_parameter: (MEMORY_ADDR_H), line:103
|vpiName:MEMORY_ADDR_H
|INT:12
|vpiParameter:
\_parameter: (MEMORY_ADDR_L), line:102
|vpiName:MEMORY_ADDR_L
|INT:11
|vpiParameter:
\_parameter: (MEMORY_BIT_CHECK), line:104
|vpiName:MEMORY_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (MUL_UNIT_WB_ID), line:193
|vpiName:MUL_UNIT_WB_ID
|INT:512
|vpiParameter:
\_parameter: (NUM_UNITS), line:188
|vpiName:NUM_UNITS
|INT:2
|vpiParameter:
\_parameter: (NUM_WB_UNITS), line:186
|vpiName:NUM_WB_UNITS
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (RAS_DEPTH), line:161
|vpiName:RAS_DEPTH
|INT:2
|vpiParameter:
\_parameter: (RESET_VEC), line:39
|vpiName:RESET_VEC
|INT:-2147483648
|vpiParameter:
\_parameter: (SCRATCH_ADDR_H), line:99
|vpiName:SCRATCH_ADDR_H
|INT:9
|vpiParameter:
\_parameter: (SCRATCH_ADDR_L), line:98
|vpiName:SCRATCH_ADDR_L
|INT:8
|vpiParameter:
\_parameter: (SCRATCH_BIT_CHECK), line:100
|vpiName:SCRATCH_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (USE_AMO), line:70
|vpiName:USE_AMO
|INT:1
|vpiParameter:
\_parameter: (USE_BRANCH_PREDICTOR), line:158
|vpiName:USE_BRANCH_PREDICTOR
|INT:2
|vpiParameter:
\_parameter: (USE_BUS), line:88
|vpiName:USE_BUS
|INT:4
|vpiParameter:
\_parameter: (USE_DCACHE), line:92
|vpiName:USE_DCACHE
|INT:6
|vpiParameter:
\_parameter: (USE_DIV), line:49
|vpiName:USE_DIV
|INT:1
|vpiParameter:
\_parameter: (USE_DTAG_INVALIDATIONS), line:140
|vpiName:USE_DTAG_INVALIDATIONS
|INT:1879048191
|vpiParameter:
\_parameter: (USE_D_SCRATCH_MEM), line:79
|vpiName:USE_D_SCRATCH_MEM
|INT:3
|vpiParameter:
\_parameter: (USE_ICACHE), line:93
|vpiName:USE_ICACHE
|INT:7
|vpiParameter:
\_parameter: (USE_I_SCRATCH_MEM), line:78
|vpiName:USE_I_SCRATCH_MEM
|INT:2
|vpiParameter:
\_parameter: (USE_MUL), line:48
|vpiName:USE_MUL
|INT:1
|vpiParameter:
\_parameter: (WB_UNITS_WIDTH), line:187
|vpiName:WB_UNITS_WIDTH
|INT:32
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiGenScopeArray:
\_gen_scope_array: (genblk3), line:305, parent:load_store_unit_block
|vpiName:genblk3
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3
|vpiGenScope:
\_gen_scope: , parent:genblk3
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3
|vpiContAssign:
\_cont_assign: , line:306
|vpiRhs:
\_ref_obj: (cache.address_range_check), line:306
|vpiName:cache.address_range_check
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.cache.address_range_check
|vpiLhs:
\_bit_select: (sub_unit_address_match), line:306
|vpiName:sub_unit_address_match
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.sub_unit_address_match
|vpiIndex:
\_ref_obj: (DCACHE_ID), line:306
|vpiName:DCACHE_ID
|vpiContAssign:
\_cont_assign: , line:307
|vpiRhs:
\_operation: , line:307
|vpiOpType:28
|vpiOperand:
\_bit_select: (sub_unit_address_match), line:307
|vpiName:sub_unit_address_match
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.sub_unit_address_match
|vpiIndex:
\_ref_obj: (DCACHE_ID), line:307
|vpiName:DCACHE_ID
|vpiOperand:
\_ref_obj: (issue_request), line:307
|vpiName:issue_request
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.issue_request
|vpiLhs:
\_ref_obj: (cache.new_request), line:307
|vpiName:cache.new_request
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.cache.new_request
|vpiContAssign:
\_cont_assign: , line:309
|vpiRhs:
\_ref_obj: (cache.ready), line:309
|vpiName:cache.ready
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.cache.ready
|vpiLhs:
\_bit_select: (unit_ready), line:309
|vpiName:unit_ready
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.unit_ready
|vpiIndex:
\_ref_obj: (DCACHE_ID), line:309
|vpiName:DCACHE_ID
|vpiContAssign:
\_cont_assign: , line:310
|vpiRhs:
\_ref_obj: (cache.data_valid), line:310
|vpiName:cache.data_valid
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.cache.data_valid
|vpiLhs:
\_bit_select: (unit_data_valid), line:310
|vpiName:unit_data_valid
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.unit_data_valid
|vpiIndex:
\_ref_obj: (DCACHE_ID), line:310
|vpiName:DCACHE_ID
|vpiModule:
\_module: work@dcache (data_cache), file:third_party/cores/taiga/core/load_store_unit.sv, line:312
|vpiDefName:work@dcache
|vpiName:data_cache
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache
|vpiPort:
\_port: (clk), line:27, parent:data_cache
|vpiName:clk
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (clk), line:312
|vpiName:clk
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (clk), line:27, parent:data_cache
|vpiName:clk
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.clk
|vpiNetType:36
|vpiPort:
\_port: (rst), line:28, parent:data_cache
|vpiName:rst
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (rst), line:312
|vpiName:rst
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (rst), line:28, parent:data_cache
|vpiName:rst
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.rst
|vpiNetType:36
|vpiPort:
\_port: (dcache_on), line:29, parent:data_cache
|vpiName:dcache_on
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (dcache_on), line:312
|vpiName:dcache_on
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (dcache_on), line:29, parent:data_cache
|vpiName:dcache_on
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.dcache_on
|vpiNetType:36
|vpiPort:
\_port: (l1_request), line:30, parent:data_cache
|vpiName:l1_request
|vpiDirection:5
|vpiHighConn:
\_ref_obj: (l1_request), line:312
|vpiName:l1_request
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_modport: (master)
|vpiName:master
|vpiIODecl:
\_io_decl: (addr)
|vpiName:addr
|vpiDirection:2
|vpiExpr:
\_logic_net: (addr), line:123
|vpiName:addr
|vpiNetType:36
|vpiRange:
\_range: , line:123
|vpiLeftRange:
\_constant: , line:123
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:123
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (data)
|vpiName:data
|vpiDirection:2
|vpiExpr:
\_logic_net: (data), line:124
|vpiName:data
|vpiNetType:36
|vpiRange:
\_range: , line:124
|vpiLeftRange:
\_constant: , line:124
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:124
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (rnw)
|vpiName:rnw
|vpiDirection:2
|vpiExpr:
\_logic_net: (rnw), line:125
|vpiName:rnw
|vpiNetType:36
|vpiIODecl:
\_io_decl: (be)
|vpiName:be
|vpiDirection:2
|vpiExpr:
\_logic_net: (be), line:126
|vpiName:be
|vpiNetType:36
|vpiRange:
\_range: , line:126
|vpiLeftRange:
\_constant: , line:126
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiRightRange:
\_constant: , line:126
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (size)
|vpiName:size
|vpiDirection:2
|vpiExpr:
\_logic_net: (size), line:127
|vpiName:size
|vpiNetType:36
|vpiRange:
\_range: , line:127
|vpiLeftRange:
\_constant: , line:127
|vpiConstType:7
|vpiDecompile:4
|vpiSize:32
|INT:4
|vpiRightRange:
\_constant: , line:127
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (is_amo)
|vpiName:is_amo
|vpiDirection:2
|vpiExpr:
\_logic_net: (is_amo), line:128
|vpiName:is_amo
|vpiNetType:36
|vpiIODecl:
\_io_decl: (amo)
|vpiName:amo
|vpiDirection:2
|vpiExpr:
\_logic_net: (amo), line:129
|vpiName:amo
|vpiNetType:36
|vpiRange:
\_range: , line:129
|vpiLeftRange:
\_constant: , line:129
|vpiConstType:7
|vpiDecompile:4
|vpiSize:32
|INT:4
|vpiRightRange:
\_constant: , line:129
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (request)
|vpiName:request
|vpiDirection:2
|vpiExpr:
\_logic_net: (request), line:131
|vpiName:request
|vpiNetType:36
|vpiIODecl:
\_io_decl: (ack)
|vpiName:ack
|vpiDirection:1
|vpiExpr:
\_logic_net: (ack), line:132
|vpiName:ack
|vpiNetType:36
|vpiInterface:
\_interface: work@l1_arbiter_request_interface (l1_request), file:third_party/cores/taiga/core/load_store_unit.sv, line:312
|vpiDefName:work@l1_arbiter_request_interface
|vpiName:l1_request
|vpiModport:
\_modport: (master)
|vpiModport:
\_modport: (slave)
|vpiName:slave
|vpiIODecl:
\_io_decl: (addr)
|vpiName:addr
|vpiDirection:1
|vpiExpr:
\_logic_net: (addr), line:123
|vpiIODecl:
\_io_decl: (data)
|vpiName:data
|vpiDirection:1
|vpiExpr:
\_logic_net: (data), line:124
|vpiIODecl:
\_io_decl: (rnw)
|vpiName:rnw
|vpiDirection:1
|vpiExpr:
\_logic_net: (rnw), line:125
|vpiIODecl:
\_io_decl: (be)
|vpiName:be
|vpiDirection:1
|vpiExpr:
\_logic_net: (be), line:126
|vpiIODecl:
\_io_decl: (size)
|vpiName:size
|vpiDirection:1
|vpiExpr:
\_logic_net: (size), line:127
|vpiIODecl:
\_io_decl: (is_amo)
|vpiName:is_amo
|vpiDirection:1
|vpiExpr:
\_logic_net: (is_amo), line:128
|vpiIODecl:
\_io_decl: (amo)
|vpiName:amo
|vpiDirection:1
|vpiExpr:
\_logic_net: (amo), line:129
|vpiIODecl:
\_io_decl: (request)
|vpiName:request
|vpiDirection:1
|vpiExpr:
\_logic_net: (request), line:131
|vpiIODecl:
\_io_decl: (ack)
|vpiName:ack
|vpiDirection:2
|vpiExpr:
\_logic_net: (ack), line:132
|vpiInterface:
\_interface: work@l1_arbiter_request_interface (l1_request), file:third_party/cores/taiga/core/load_store_unit.sv, line:312
|vpiPort:
\_port: (l1_response), line:31, parent:data_cache
|vpiName:l1_response
|vpiDirection:5
|vpiHighConn:
\_ref_obj: (l1_response), line:312
|vpiName:l1_response
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_modport: (master)
|vpiName:master
|vpiIODecl:
\_io_decl: (inv_addr)
|vpiName:inv_addr
|vpiDirection:1
|vpiExpr:
\_logic_net: (inv_addr), line:149
|vpiName:inv_addr
|vpiNetType:36
|vpiRange:
\_range: , line:149
|vpiLeftRange:
\_constant: , line:149
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:149
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiIODecl:
\_io_decl: (inv_valid)
|vpiName:inv_valid
|vpiDirection:1
|vpiExpr:
\_logic_net: (inv_valid), line:150
|vpiName:inv_valid
|vpiNetType:36
|vpiIODecl:
\_io_decl: (data)
|vpiName:data
|vpiDirection:1
|vpiExpr:
\_logic_net: (data), line:124
|vpiIODecl:
\_io_decl: (data_valid)
|vpiName:data_valid
|vpiDirection:1
|vpiExpr:
\_logic_net: (data_valid), line:153
|vpiName:data_valid
|vpiNetType:36
|vpiIODecl:
\_io_decl: (inv_ack)
|vpiName:inv_ack
|vpiDirection:2
|vpiExpr:
\_logic_net: (inv_ack), line:151
|vpiName:inv_ack
|vpiNetType:36
|vpiInterface:
\_interface: work@l1_arbiter_return_interface (l1_response), file:third_party/cores/taiga/core/load_store_unit.sv, line:312
|vpiDefName:work@l1_arbiter_return_interface
|vpiName:l1_response
|vpiModport:
\_modport: (master)
|vpiModport:
\_modport: (slave)
|vpiName:slave
|vpiIODecl:
\_io_decl: (inv_addr)
|vpiName:inv_addr
|vpiDirection:2
|vpiExpr:
\_logic_net: (inv_addr), line:149
|vpiIODecl:
\_io_decl: (inv_valid)
|vpiName:inv_valid
|vpiDirection:2
|vpiExpr:
\_logic_net: (inv_valid), line:150
|vpiIODecl:
\_io_decl: (data)
|vpiName:data
|vpiDirection:2
|vpiExpr:
\_logic_net: (data), line:124
|vpiIODecl:
\_io_decl: (data_valid)
|vpiName:data_valid
|vpiDirection:2
|vpiExpr:
\_logic_net: (data_valid), line:153
|vpiIODecl:
\_io_decl: (inv_ack)
|vpiName:inv_ack
|vpiDirection:1
|vpiExpr:
\_logic_net: (inv_ack), line:151
|vpiInterface:
\_interface: work@l1_arbiter_return_interface (l1_response), file:third_party/cores/taiga/core/load_store_unit.sv, line:312
|vpiPort:
\_port: (sc_complete), line:32, parent:data_cache
|vpiName:sc_complete
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (sc_complete), line:312
|vpiName:sc_complete
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (sc_complete), line:32, parent:data_cache
|vpiName:sc_complete
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.sc_complete
|vpiPort:
\_port: (sc_success), line:33, parent:data_cache
|vpiName:sc_success
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (sc_success), line:312
|vpiName:sc_success
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (sc_success), line:33, parent:data_cache
|vpiName:sc_success
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.sc_success
|vpiPort:
\_port: (clear_reservation), line:34, parent:data_cache
|vpiName:clear_reservation
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (clear_reservation), line:312
|vpiName:clear_reservation
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (clear_reservation), line:34, parent:data_cache
|vpiName:clear_reservation
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.clear_reservation
|vpiPort:
\_port: (ls_inputs), line:36, parent:data_cache
|vpiName:ls_inputs
|vpiDirection:1
|vpiTypedef:
\_struct_typespec: (data_access_shared_inputs_t), line:427
|vpiHighConn:
\_ref_obj: (ls_inputs), line:312
|vpiName:ls_inputs
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (ls_inputs), line:36, parent:data_cache
|vpiName:ls_inputs
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.ls_inputs
|vpiPort:
\_port: (data_out), line:37, parent:data_cache
|vpiName:data_out
|vpiDirection:2
|vpiHighConn:
\_ref_obj: (data_out), line:312
|vpiName:data_out
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (data_out), line:37, parent:data_cache
|vpiName:data_out
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.data_out
|vpiNetType:36
|vpiRange:
\_range: , line:37
|vpiLeftRange:
\_constant: , line:37
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:37
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiPort:
\_port: (amo), line:39, parent:data_cache
|vpiName:amo
|vpiDirection:1
|vpiTypedef:
\_struct_typespec: (amo_details_t), line:362
|vpiHighConn:
\_ref_obj: (amo), line:312
|vpiName:amo
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (amo), line:129
|vpiPort:
\_port: (ls), line:40, parent:data_cache
|vpiName:ls
|vpiDirection:5
|vpiHighConn:
\_ref_obj: (ls), line:312
|vpiName:ls
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_modport: (sub_unit)
|vpiName:sub_unit
|vpiIODecl:
\_io_decl: (new_request)
|vpiName:new_request
|vpiDirection:1
|vpiExpr:
\_logic_net: (new_request), line:215
|vpiName:new_request
|vpiNetType:36
|vpiIODecl:
\_io_decl: (data_valid)
|vpiName:data_valid
|vpiDirection:2
|vpiExpr:
\_logic_net: (data_valid), line:153
|vpiIODecl:
\_io_decl: (ready)
|vpiName:ready
|vpiDirection:2
|vpiExpr:
\_logic_net: (ready), line:214
|vpiName:ready
|vpiNetType:36
|vpiInterface:
\_interface: work@ls_sub_unit_interface (ls), file:third_party/cores/taiga/core/load_store_unit.sv, line:312
|vpiDefName:work@ls_sub_unit_interface
|vpiName:ls
|vpiModport:
\_modport: (ls)
|vpiName:ls
|vpiIODecl:
\_io_decl: (new_request)
|vpiName:new_request
|vpiDirection:2
|vpiExpr:
\_logic_net: (new_request), line:215
|vpiIODecl:
\_io_decl: (data_valid)
|vpiName:data_valid
|vpiDirection:1
|vpiExpr:
\_logic_net: (data_valid), line:153
|vpiIODecl:
\_io_decl: (ready)
|vpiName:ready
|vpiDirection:1
|vpiExpr:
\_logic_net: (ready), line:214
|vpiInterface:
\_interface: work@ls_sub_unit_interface (ls), file:third_party/cores/taiga/core/load_store_unit.sv, line:312
|vpiModport:
\_modport: (sub_unit)
|vpiModule:
\_module: work@cycler (replacement_policy), file:third_party/cores/taiga/core/dcache.sv, line:170, parent:data_cache
|vpiDefName:work@cycler
|vpiName:replacement_policy
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.replacement_policy
|vpiPort:
\_port: (clk), line:29, parent:replacement_policy
|vpiName:clk
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (clk), line:170
|vpiName:clk
|vpiActual:
\_logic_net: (clk), line:27, parent:data_cache
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (clk), line:29, parent:replacement_policy
|vpiName:clk
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.replacement_policy.clk
|vpiNetType:36
|vpiPort:
\_port: (rst), line:30, parent:replacement_policy
|vpiName:rst
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (rst), line:170
|vpiName:rst
|vpiActual:
\_logic_net: (rst), line:28, parent:data_cache
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (rst), line:30, parent:replacement_policy
|vpiName:rst
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.replacement_policy.rst
|vpiNetType:36
|vpiPort:
\_port: (en), line:31, parent:replacement_policy
|vpiName:en
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (en), line:170
|vpiName:en
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (en), line:31, parent:replacement_policy
|vpiName:en
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.replacement_policy.en
|vpiNetType:36
|vpiPort:
\_port: (one_hot), line:32, parent:replacement_policy
|vpiName:one_hot
|vpiDirection:2
|vpiHighConn:
\_ref_obj: (one_hot), line:170
|vpiName:one_hot
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (one_hot), line:32, parent:replacement_policy
|vpiName:one_hot
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.replacement_policy.one_hot
|vpiNetType:36
|vpiRange:
\_range: , line:32
|vpiLeftRange:
\_constant: , line:32
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiRightRange:
\_constant: , line:32
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiGenScopeArray:
\_gen_scope_array: (genblk1), line:39, parent:replacement_policy
|vpiName:genblk1
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.replacement_policy.genblk1
|vpiGenScope:
\_gen_scope: , parent:genblk1
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.replacement_policy.genblk1
|vpiProcess:
\_always: , line:40
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:40
|vpiCondition:
\_operation: , line:40
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:40
|vpiName:clk
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.replacement_policy.genblk1.clk
|vpiStmt:
\_begin: , line:40
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.replacement_policy.genblk1
|vpiStmt:
\_if_else: , line:41
|vpiCondition:
\_ref_obj: (rst), line:41
|vpiName:rst
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.replacement_policy.genblk1.rst
|vpiStmt:
\_assignment: , line:42
|vpiOpType:82
|vpiLhs:
\_ref_obj: (one_hot), line:42
|vpiName:one_hot
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.replacement_policy.genblk1.one_hot
|vpiRhs:
\_constant: , line:42
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiElseStmt:
\_if_stmt: , line:43
|vpiCondition:
\_ref_obj: (en), line:43
|vpiName:en
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.replacement_policy.genblk1.en
|vpiStmt:
\_assignment: , line:44
|vpiOpType:82
|vpiLhs:
\_ref_obj: (one_hot), line:44
|vpiName:one_hot
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.replacement_policy.genblk1.one_hot
|vpiRhs:
\_operation: , line:44
|vpiOpType:33
|vpiOperand:
\_part_select: , line:44, parent:one_hot
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (one_hot)
|vpiLeftRange:
\_operation: , line:44
|vpiOpType:11
|vpiOperand:
\_ref_obj: (C_WIDTH), line:44
|vpiName:C_WIDTH
|vpiOperand:
\_constant: , line:44
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiRightRange:
\_constant: , line:44
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiOperand:
\_bit_select: (one_hot), line:44
|vpiName:one_hot
|vpiIndex:
\_operation: , line:44
|vpiOpType:11
|vpiOperand:
\_ref_obj: (C_WIDTH), line:44
|vpiName:C_WIDTH
|vpiOperand:
\_constant: , line:44
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiNet:
\_logic_net: (clk), line:29, parent:replacement_policy
|vpiNet:
\_logic_net: (rst), line:30, parent:replacement_policy
|vpiNet:
\_logic_net: (en), line:31, parent:replacement_policy
|vpiNet:
\_logic_net: (one_hot), line:32, parent:replacement_policy
|vpiInstance:
\_module: work@dcache (data_cache), file:third_party/cores/taiga/core/load_store_unit.sv, line:312
|vpiParameter:
\_parameter: (C_WIDTH), line:170
|vpiName:C_WIDTH
|INT:4
|vpiModule:
\_module: work@one_hot_to_integer (hit_way_conv), file:third_party/cores/taiga/core/dcache.sv, line:173, parent:data_cache
|vpiDefName:work@one_hot_to_integer
|vpiName:hit_way_conv
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.hit_way_conv
|vpiPort:
\_port: (clk), line:31, parent:hit_way_conv
|vpiName:clk
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (clk), line:173
|vpiName:clk
|vpiActual:
\_logic_net: (clk), line:27, parent:data_cache
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (clk), line:31, parent:hit_way_conv
|vpiName:clk
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.hit_way_conv.clk
|vpiNetType:36
|vpiPort:
\_port: (rst), line:32, parent:hit_way_conv
|vpiName:rst
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (rst), line:173
|vpiName:rst
|vpiActual:
\_logic_net: (rst), line:28, parent:data_cache
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (rst), line:32, parent:hit_way_conv
|vpiName:rst
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.hit_way_conv.rst
|vpiNetType:36
|vpiPort:
\_port: (one_hot), line:33, parent:hit_way_conv
|vpiName:one_hot
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (one_hot), line:173
|vpiName:one_hot
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (one_hot), line:33, parent:hit_way_conv
|vpiName:one_hot
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.hit_way_conv.one_hot
|vpiNetType:36
|vpiRange:
\_range: , line:33
|vpiLeftRange:
\_constant: , line:33
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiRightRange:
\_constant: , line:33
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiPort:
\_port: (int_out), line:34, parent:hit_way_conv
|vpiName:int_out
|vpiDirection:2
|vpiHighConn:
\_ref_obj: (int_out), line:173
|vpiName:int_out
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (int_out), line:34, parent:hit_way_conv
|vpiName:int_out
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.hit_way_conv.int_out
|vpiNetType:36
|vpiRange:
\_range: , line:34
|vpiLeftRange:
\_constant: , line:34
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiRightRange:
\_constant: , line:34
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiGenScopeArray:
\_gen_scope_array: (genblk1), line:40, parent:hit_way_conv
|vpiName:genblk1
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.hit_way_conv.genblk1
|vpiGenScope:
\_gen_scope: , parent:genblk1
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.hit_way_conv.genblk1
|vpiProcess:
\_always: , line:41
|vpiAlwaysType:2
|vpiStmt:
\_begin: , line:41
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.hit_way_conv.genblk1
|vpiStmt:
\_assignment: , line:42
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (int_out), line:42
|vpiName:int_out
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.hit_way_conv.genblk1.int_out
|vpiRhs:
\_constant: , line:42
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiStmt:
\_foreach_stmt: , line:43
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.hit_way_conv.genblk1
|vpiVariables:
\_chandle_var: (one_hot), line:43
|vpiName:one_hot
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.hit_way_conv.genblk1.one_hot
|vpiLoopVars:
\_chandle_var: (i), line:43
|vpiName:i
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.hit_way_conv.genblk1.i
|vpiStmt:
\_if_stmt: , line:44
|vpiCondition:
\_bit_select: (one_hot), line:44
|vpiName:one_hot
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.hit_way_conv.genblk1.one_hot
|vpiIndex:
\_ref_obj: (i), line:44
|vpiName:i
|vpiStmt:
\_assignment: , line:44
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (int_out), line:44
|vpiName:int_out
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.hit_way_conv.genblk1.int_out
|vpiRhs:
\_part_select: , line:44, parent:i
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (i)
|vpiLeftRange:
\_operation: , line:44
|vpiOpType:11
|vpiOperand:
\_sys_func_call: ($clog2), line:44
|vpiName:$clog2
|vpiArgument:
\_ref_obj: (C_WIDTH), line:44
|vpiName:C_WIDTH
|vpiOperand:
\_constant: , line:44
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:44
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (clk), line:31, parent:hit_way_conv
|vpiNet:
\_logic_net: (rst), line:32, parent:hit_way_conv
|vpiNet:
\_logic_net: (one_hot), line:33, parent:hit_way_conv
|vpiNet:
\_logic_net: (int_out), line:34, parent:hit_way_conv
|vpiInstance:
\_module: work@dcache (data_cache), file:third_party/cores/taiga/core/load_store_unit.sv, line:312
|vpiParameter:
\_parameter: (C_WIDTH), line:173
|vpiName:C_WIDTH
|INT:4
|vpiModule:
\_module: work@one_hot_to_integer (update_way_conv), file:third_party/cores/taiga/core/dcache.sv, line:174, parent:data_cache
|vpiDefName:work@one_hot_to_integer
|vpiName:update_way_conv
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.update_way_conv
|vpiPort:
\_port: (clk), line:31, parent:update_way_conv
|vpiName:clk
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (clk), line:174
|vpiName:clk
|vpiActual:
\_logic_net: (clk), line:27, parent:data_cache
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (clk), line:31, parent:update_way_conv
|vpiName:clk
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.update_way_conv.clk
|vpiNetType:36
|vpiPort:
\_port: (rst), line:32, parent:update_way_conv
|vpiName:rst
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (rst), line:174
|vpiName:rst
|vpiActual:
\_logic_net: (rst), line:28, parent:data_cache
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (rst), line:32, parent:update_way_conv
|vpiName:rst
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.update_way_conv.rst
|vpiNetType:36
|vpiPort:
\_port: (one_hot), line:33, parent:update_way_conv
|vpiName:one_hot
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (one_hot), line:174
|vpiName:one_hot
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (one_hot), line:33, parent:update_way_conv
|vpiName:one_hot
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.update_way_conv.one_hot
|vpiNetType:36
|vpiRange:
\_range: , line:33
|vpiLeftRange:
\_constant: , line:33
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiRightRange:
\_constant: , line:33
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiPort:
\_port: (int_out), line:34, parent:update_way_conv
|vpiName:int_out
|vpiDirection:2
|vpiHighConn:
\_ref_obj: (int_out), line:174
|vpiName:int_out
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (int_out), line:34, parent:update_way_conv
|vpiName:int_out
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.update_way_conv.int_out
|vpiNetType:36
|vpiRange:
\_range: , line:34
|vpiLeftRange:
\_constant: , line:34
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiRightRange:
\_constant: , line:34
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiGenScopeArray:
\_gen_scope_array: (genblk1), line:40, parent:update_way_conv
|vpiName:genblk1
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.update_way_conv.genblk1
|vpiGenScope:
\_gen_scope: , parent:genblk1
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.update_way_conv.genblk1
|vpiProcess:
\_always: , line:41
|vpiAlwaysType:2
|vpiStmt:
\_begin: , line:41
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.update_way_conv.genblk1
|vpiStmt:
\_assignment: , line:42
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (int_out), line:42
|vpiName:int_out
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.update_way_conv.genblk1.int_out
|vpiRhs:
\_constant: , line:42
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiStmt:
\_foreach_stmt: , line:43
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.update_way_conv.genblk1
|vpiVariables:
\_chandle_var: (one_hot), line:43
|vpiName:one_hot
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.update_way_conv.genblk1.one_hot
|vpiLoopVars:
\_chandle_var: (i), line:43
|vpiName:i
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.update_way_conv.genblk1.i
|vpiStmt:
\_if_stmt: , line:44
|vpiCondition:
\_bit_select: (one_hot), line:44
|vpiName:one_hot
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.update_way_conv.genblk1.one_hot
|vpiIndex:
\_ref_obj: (i), line:44
|vpiName:i
|vpiStmt:
\_assignment: , line:44
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (int_out), line:44
|vpiName:int_out
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.update_way_conv.genblk1.int_out
|vpiRhs:
\_part_select: , line:44, parent:i
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (i)
|vpiLeftRange:
\_operation: , line:44
|vpiOpType:11
|vpiOperand:
\_sys_func_call: ($clog2), line:44
|vpiName:$clog2
|vpiArgument:
\_ref_obj: (C_WIDTH), line:44
|vpiName:C_WIDTH
|vpiOperand:
\_constant: , line:44
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:44
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (clk), line:31, parent:update_way_conv
|vpiNet:
\_logic_net: (rst), line:32, parent:update_way_conv
|vpiNet:
\_logic_net: (one_hot), line:33, parent:update_way_conv
|vpiNet:
\_logic_net: (int_out), line:34, parent:update_way_conv
|vpiInstance:
\_module: work@dcache (data_cache), file:third_party/cores/taiga/core/load_store_unit.sv, line:312
|vpiParameter:
\_parameter: (C_WIDTH), line:174
|vpiName:C_WIDTH
|INT:4
|vpiModule:
\_module: work@dtag_banks (dcache_tag_banks), file:third_party/cores/taiga/core/dcache.sv, line:189, parent:data_cache
|vpiDefName:work@dtag_banks
|vpiName:dcache_tag_banks
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.dcache_tag_banks
|vpiPort:
\_port: (clk), line:27, parent:dcache_tag_banks
|vpiName:clk
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (clk), line:189
|vpiName:clk
|vpiActual:
\_logic_net: (clk), line:27, parent:data_cache
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (clk), line:27, parent:dcache_tag_banks
|vpiName:clk
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.dcache_tag_banks.clk
|vpiNetType:36
|vpiPort:
\_port: (rst), line:28, parent:dcache_tag_banks
|vpiName:rst
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (rst), line:189
|vpiName:rst
|vpiActual:
\_logic_net: (rst), line:28, parent:data_cache
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (rst), line:28, parent:dcache_tag_banks
|vpiName:rst
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.dcache_tag_banks.rst
|vpiNetType:36
|vpiPort:
\_port: (stage1_addr), line:30, parent:dcache_tag_banks
|vpiName:stage1_addr
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (stage1_addr), line:189
|vpiName:stage1_addr
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (stage1_addr), line:30, parent:dcache_tag_banks
|vpiName:stage1_addr
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.dcache_tag_banks.stage1_addr
|vpiNetType:36
|vpiRange:
\_range: , line:30
|vpiLeftRange:
\_constant: , line:30
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:30
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiPort:
\_port: (stage2_addr), line:31, parent:dcache_tag_banks
|vpiName:stage2_addr
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (stage2_addr), line:189
|vpiName:stage2_addr
|vpiActual:
\_logic_net: (stage2_addr), line:67, parent:data_cache
|vpiName:stage2_addr
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.stage2_addr
|vpiNetType:36
|vpiRange:
\_range: , line:67
|vpiLeftRange:
\_constant: , line:67
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:67
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (stage2_addr), line:31, parent:dcache_tag_banks
|vpiName:stage2_addr
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.dcache_tag_banks.stage2_addr
|vpiNetType:36
|vpiRange:
\_range: , line:31
|vpiLeftRange:
\_constant: , line:31
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:31
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiPort:
\_port: (inv_addr), line:32, parent:dcache_tag_banks
|vpiName:inv_addr
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (inv_addr), line:189
|vpiName:inv_addr
|vpiActual:
\_logic_net: (inv_addr), line:149
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (inv_addr), line:32, parent:dcache_tag_banks
|vpiName:inv_addr
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.dcache_tag_banks.inv_addr
|vpiNetType:36
|vpiRange:
\_range: , line:32
|vpiLeftRange:
\_constant: , line:32
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:32
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiPort:
\_port: (update_way), line:34, parent:dcache_tag_banks
|vpiName:update_way
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (update_way), line:189
|vpiName:update_way
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (update_way), line:34, parent:dcache_tag_banks
|vpiName:update_way
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.dcache_tag_banks.update_way
|vpiNetType:36
|vpiRange:
\_range: , line:34
|vpiLeftRange:
\_constant: , line:34
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiRightRange:
\_constant: , line:34
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiPort:
\_port: (update), line:35, parent:dcache_tag_banks
|vpiName:update
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (update), line:189
|vpiName:update
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (update), line:35, parent:dcache_tag_banks
|vpiName:update
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.dcache_tag_banks.update
|vpiNetType:36
|vpiPort:
\_port: (stage1_adv), line:37, parent:dcache_tag_banks
|vpiName:stage1_adv
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (stage1_adv), line:189
|vpiName:stage1_adv
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (stage1_adv), line:37, parent:dcache_tag_banks
|vpiName:stage1_adv
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.dcache_tag_banks.stage1_adv
|vpiNetType:36
|vpiPort:
\_port: (stage1_inv), line:38, parent:dcache_tag_banks
|vpiName:stage1_inv
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (stage1_inv), line:189
|vpiName:stage1_inv
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (stage1_inv), line:38, parent:dcache_tag_banks
|vpiName:stage1_inv
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.dcache_tag_banks.stage1_inv
|vpiNetType:36
|vpiPort:
\_port: (extern_inv), line:40, parent:dcache_tag_banks
|vpiName:extern_inv
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (extern_inv), line:189
|vpiName:extern_inv
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (extern_inv), line:40, parent:dcache_tag_banks
|vpiName:extern_inv
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.dcache_tag_banks.extern_inv
|vpiNetType:36
|vpiPort:
\_port: (extern_inv_complete), line:41, parent:dcache_tag_banks
|vpiName:extern_inv_complete
|vpiDirection:2
|vpiHighConn:
\_ref_obj: (extern_inv_complete), line:189
|vpiName:extern_inv_complete
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (extern_inv_complete), line:41, parent:dcache_tag_banks
|vpiName:extern_inv_complete
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.dcache_tag_banks.extern_inv_complete
|vpiNetType:36
|vpiPort:
\_port: (tag_hit), line:43, parent:dcache_tag_banks
|vpiName:tag_hit
|vpiDirection:2
|vpiHighConn:
\_ref_obj: (tag_hit), line:189
|vpiName:tag_hit
|vpiActual:
\_logic_net: (tag_hit), line:48, parent:data_cache
|vpiName:tag_hit
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.tag_hit
|vpiNetType:36
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (tag_hit), line:43, parent:dcache_tag_banks
|vpiName:tag_hit
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.dcache_tag_banks.tag_hit
|vpiPort:
\_port: (tag_hit_way), line:44, parent:dcache_tag_banks
|vpiName:tag_hit_way
|vpiDirection:2
|vpiHighConn:
\_ref_obj: (tag_hit_way), line:189
|vpiName:tag_hit_way
|vpiActual:
\_logic_net: (tag_hit_way), line:49, parent:data_cache
|vpiName:tag_hit_way
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.tag_hit_way
|vpiNetType:36
|vpiRange:
\_range: , line:49
|vpiLeftRange:
\_constant: , line:49
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiRightRange:
\_constant: , line:49
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (tag_hit_way), line:44, parent:dcache_tag_banks
|vpiName:tag_hit_way
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.dcache_tag_banks.tag_hit_way
|vpiNetType:36
|vpiRange:
\_range: , line:44
|vpiLeftRange:
\_constant: , line:44
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiRightRange:
\_constant: , line:44
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiGenScopeArray:
\_gen_scope_array: (dtag_bank_gen[0]), line:107, parent:dcache_tag_banks
|vpiName:dtag_bank_gen[0]
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.dcache_tag_banks.dtag_bank_gen[0]
|vpiGenScope:
\_gen_scope: , parent:dtag_bank_gen[0]
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.dcache_tag_banks.dtag_bank_gen[0]
|vpiContAssign:
\_cont_assign: , line:108
|vpiRhs:
\_operation: , line:108
|vpiOpType:29
|vpiOperand:
\_bit_select: (update_way), line:108
|vpiName:update_way
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.dcache_tag_banks.dtag_bank_gen[0].update_way
|vpiIndex:
\_ref_obj: (i), line:108
|vpiName:i
|vpiOperand:
\_operation: , line:108
|vpiOpType:28
|vpiOperand:
\_bit_select: (inv_hit_way), line:108
|vpiName:inv_hit_way
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.dcache_tag_banks.dtag_bank_gen[0].inv_hit_way
|vpiIndex:
\_ref_obj: (i), line:108
|vpiName:i
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.dcache_tag_banks.dtag_bank_gen[0].i
|vpiOperand:
\_ref_obj: (extern_inv_complete), line:108
|vpiName:extern_inv_complete
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.dcache_tag_banks.dtag_bank_gen[0].extern_inv_complete
|vpiLhs:
\_bit_select: (update_tag_way), line:108
|vpiName:update_tag_way
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.dcache_tag_banks.dtag_bank_gen[0].update_tag_way
|vpiIndex:
\_ref_obj: (i), line:108
|vpiName:i
|vpiContAssign:
\_cont_assign: , line:120
|vpiRhs:
\_operation: , line:120
|vpiOpType:14
|vpiOperand:
\_ref_obj: (inv_hit_comparison_tagline), line:120
|vpiName:inv_hit_comparison_tagline
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.dcache_tag_banks.dtag_bank_gen[0].inv_hit_comparison_tagline
|vpiOperand:
\_bit_select: (inv_tag_line), line:120
|vpiName:inv_tag_line
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.dcache_tag_banks.dtag_bank_gen[0].inv_tag_line
|vpiIndex:
\_ref_obj: (i), line:120
|vpiName:i
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.dcache_tag_banks.dtag_bank_gen[0].i
|vpiLhs:
\_bit_select: (inv_hit_way), line:120
|vpiName:inv_hit_way
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.dcache_tag_banks.dtag_bank_gen[0].inv_hit_way
|vpiIndex:
\_ref_obj: (i), line:120
|vpiName:i
|vpiContAssign:
\_cont_assign: , line:121
|vpiRhs:
\_operation: , line:121
|vpiOpType:14
|vpiOperand:
\_ref_obj: (stage2_hit_comparison_tagline), line:121
|vpiName:stage2_hit_comparison_tagline
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.dcache_tag_banks.dtag_bank_gen[0].stage2_hit_comparison_tagline
|vpiOperand:
\_bit_select: (tag_line), line:121
|vpiName:tag_line
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.dcache_tag_banks.dtag_bank_gen[0].tag_line
|vpiIndex:
\_ref_obj: (i), line:121
|vpiName:i
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.dcache_tag_banks.dtag_bank_gen[0].i
|vpiLhs:
\_bit_select: (tag_hit_way), line:121
|vpiName:tag_hit_way
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.dcache_tag_banks.dtag_bank_gen[0].tag_hit_way
|vpiIndex:
\_ref_obj: (i), line:121
|vpiName:i
|vpiModule:
\_module: work@tag_bank (dtag_bank), file:third_party/cores/taiga/core/dtag_banks.sv, line:110
|vpiDefName:work@tag_bank
|vpiName:dtag_bank
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.dcache_tag_banks.dtag_bank_gen[0].dtag_bank
|vpiPort:
\_port: (clk), line:32, parent:dtag_bank
|vpiName:clk
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (clk), line:110
|vpiName:clk
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (clk), line:32, parent:dtag_bank
|vpiName:clk
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.dcache_tag_banks.dtag_bank_gen[0].dtag_bank.clk
|vpiNetType:36
|vpiPort:
\_port: (rst), line:33, parent:dtag_bank
|vpiName:rst
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (rst), line:110
|vpiName:rst
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (rst), line:33, parent:dtag_bank
|vpiName:rst
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.dcache_tag_banks.dtag_bank_gen[0].dtag_bank.rst
|vpiNetType:36
|vpiPort:
\_port: (addr_a), line:35, parent:dtag_bank
|vpiName:addr_a
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (addr_a), line:110
|vpiName:addr_a
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (addr_a), line:35, parent:dtag_bank
|vpiName:addr_a
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.dcache_tag_banks.dtag_bank_gen[0].dtag_bank.addr_a
|vpiNetType:36
|vpiRange:
\_range: , line:35
|vpiLeftRange:
\_constant: , line:35
|vpiConstType:7
|vpiDecompile:8
|vpiSize:32
|INT:8
|vpiRightRange:
\_constant: , line:35
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiPort:
\_port: (addr_b), line:36, parent:dtag_bank
|vpiName:addr_b
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (addr_b), line:110
|vpiName:addr_b
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (addr_b), line:36, parent:dtag_bank
|vpiName:addr_b
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.dcache_tag_banks.dtag_bank_gen[0].dtag_bank.addr_b
|vpiNetType:36
|vpiRange:
\_range: , line:36
|vpiLeftRange:
\_constant: , line:36
|vpiConstType:7
|vpiDecompile:8
|vpiSize:32
|INT:8
|vpiRightRange:
\_constant: , line:36
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiPort:
\_port: (en_a), line:37, parent:dtag_bank
|vpiName:en_a
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (en_a), line:110
|vpiName:en_a
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (en_a), line:37, parent:dtag_bank
|vpiName:en_a
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.dcache_tag_banks.dtag_bank_gen[0].dtag_bank.en_a
|vpiNetType:36
|vpiPort:
\_port: (en_b), line:38, parent:dtag_bank
|vpiName:en_b
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (en_b), line:110
|vpiName:en_b
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (en_b), line:38, parent:dtag_bank
|vpiName:en_b
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.dcache_tag_banks.dtag_bank_gen[0].dtag_bank.en_b
|vpiNetType:36
|vpiPort:
\_port: (wen_a), line:39, parent:dtag_bank
|vpiName:wen_a
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (wen_a), line:110
|vpiName:wen_a
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (wen_a), line:39, parent:dtag_bank
|vpiName:wen_a
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.dcache_tag_banks.dtag_bank_gen[0].dtag_bank.wen_a
|vpiNetType:36
|vpiPort:
\_port: (wen_b), line:40, parent:dtag_bank
|vpiName:wen_b
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (wen_b), line:110
|vpiName:wen_b
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (wen_b), line:40, parent:dtag_bank
|vpiName:wen_b
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.dcache_tag_banks.dtag_bank_gen[0].dtag_bank.wen_b
|vpiNetType:36
|vpiPort:
\_port: (data_in_a), line:41, parent:dtag_bank
|vpiName:data_in_a
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (data_in_a), line:110
|vpiName:data_in_a
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (data_in_a), line:41, parent:dtag_bank
|vpiName:data_in_a
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.dcache_tag_banks.dtag_bank_gen[0].dtag_bank.data_in_a
|vpiNetType:36
|vpiRange:
\_range: , line:41
|vpiLeftRange:
\_constant: , line:41
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:41
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiPort:
\_port: (data_in_b), line:42, parent:dtag_bank
|vpiName:data_in_b
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (data_in_b), line:110
|vpiName:data_in_b
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (data_in_b), line:42, parent:dtag_bank
|vpiName:data_in_b
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.dcache_tag_banks.dtag_bank_gen[0].dtag_bank.data_in_b
|vpiNetType:36
|vpiRange:
\_range: , line:42
|vpiLeftRange:
\_constant: , line:42
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:42
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiPort:
\_port: (data_out_a), line:43, parent:dtag_bank
|vpiName:data_out_a
|vpiDirection:2
|vpiHighConn:
\_ref_obj: (data_out_a), line:110
|vpiName:data_out_a
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (data_out_a), line:43, parent:dtag_bank
|vpiName:data_out_a
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.dcache_tag_banks.dtag_bank_gen[0].dtag_bank.data_out_a
|vpiNetType:36
|vpiRange:
\_range: , line:43
|vpiLeftRange:
\_constant: , line:43
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:43
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiPort:
\_port: (data_out_b), line:44, parent:dtag_bank
|vpiName:data_out_b
|vpiDirection:2
|vpiHighConn:
\_ref_obj: (data_out_b), line:110
|vpiName:data_out_b
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (data_out_b), line:44, parent:dtag_bank
|vpiName:data_out_b
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.dcache_tag_banks.dtag_bank_gen[0].dtag_bank.data_out_b
|vpiNetType:36
|vpiRange:
\_range: , line:44
|vpiLeftRange:
\_constant: , line:44
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:44
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (clk), line:32, parent:dtag_bank
|vpiNet:
\_logic_net: (rst), line:33, parent:dtag_bank
|vpiNet:
\_logic_net: (addr_a), line:35, parent:dtag_bank
|vpiNet:
\_logic_net: (addr_b), line:36, parent:dtag_bank
|vpiNet:
\_logic_net: (en_a), line:37, parent:dtag_bank
|vpiNet:
\_logic_net: (en_b), line:38, parent:dtag_bank
|vpiNet:
\_logic_net: (wen_a), line:39, parent:dtag_bank
|vpiNet:
\_logic_net: (wen_b), line:40, parent:dtag_bank
|vpiNet:
\_logic_net: (data_in_a), line:41, parent:dtag_bank
|vpiNet:
\_logic_net: (data_in_b), line:42, parent:dtag_bank
|vpiNet:
\_logic_net: (data_out_a), line:43, parent:dtag_bank
|vpiNet:
\_logic_net: (data_out_b), line:44, parent:dtag_bank
|vpiNet:
\_logic_net: (i), line:49, parent:dtag_bank
|vpiName:i
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.dcache_tag_banks.dtag_bank_gen[0].dtag_bank.i
|vpiArrayNet:
\_array_net: (tag_entry), line:47, parent:dtag_bank
|vpiName:tag_entry
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.dcache_tag_banks.dtag_bank_gen[0].dtag_bank.tag_entry
|vpiSize:512
|vpiNet:
\_logic_net: , parent:tag_entry
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.dcache_tag_banks.dtag_bank_gen[0].dtag_bank.tag_entry
|vpiNetType:36
|vpiRange:
\_range: , line:47
|vpiLeftRange:
\_constant: , line:47
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:47
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiRange:
\_range: , line:47
|vpiLeftRange:
\_constant: , line:47
|vpiConstType:7
|vpiDecompile:511
|vpiSize:32
|INT:511
|vpiRightRange:
\_constant: , line:47
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiParameter:
\_parameter: (ALU_UNIT_WB_ID), line:190
|vpiName:ALU_UNIT_WB_ID
|INT:32
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (BRANCH_PREDICTOR_WAYS), line:159
|vpiName:BRANCH_PREDICTOR_WAYS
|INT:9
|vpiParameter:
\_parameter: (BRANCH_TABLE_ENTRIES), line:160
|vpiName:BRANCH_TABLE_ENTRIES
|INT:4
|vpiParameter:
\_parameter: (BRANCH_UNIT_ID), line:195
|vpiName:BRANCH_UNIT_ID
|INT:8
|vpiParameter:
\_parameter: (BUS_ADDR_H), line:107
|vpiName:BUS_ADDR_H
|INT:1
|vpiParameter:
\_parameter: (BUS_ADDR_L), line:106
|vpiName:BUS_ADDR_L
|INT:0
|vpiParameter:
\_parameter: (BUS_BIT_CHECK), line:108
|vpiName:BUS_BIT_CHECK
|INT:1
|vpiParameter:
\_parameter: (BUS_TYPE), line:89
|vpiName:BUS_TYPE
|INT:5
|vpiParameter:
\_parameter: (COUNTER_W), line:42
|vpiName:COUNTER_W
|INT:33
|vpiParameter:
\_parameter: (CPU_ID), line:38
|vpiName:CPU_ID
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_ADDR_WIDTH), line:113
|vpiName:C_M_AXI_ADDR_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_DATA_WIDTH), line:114
|vpiName:C_M_AXI_DATA_WIDTH
|INT:1
|vpiParameter:
\_parameter: (DCACHE_LINES), line:133
|vpiName:DCACHE_LINES
|INT:-2146435073
|vpiParameter:
\_parameter: (DCACHE_LINE_ADDR_W), line:135
|vpiName:DCACHE_LINE_ADDR_W
|INT:1073741824
|vpiParameter:
\_parameter: (DCACHE_LINE_W), line:136
|vpiName:DCACHE_LINE_W
|INT:1342177279
|vpiParameter:
\_parameter: (DCACHE_SUB_LINE_ADDR_W), line:137
|vpiName:DCACHE_SUB_LINE_ADDR_W
|INT:4
|vpiParameter:
\_parameter: (DCACHE_TAG_W), line:138
|vpiName:DCACHE_TAG_W
|INT:1610612736
|vpiParameter:
\_parameter: (DCACHE_WAYS), line:134
|vpiName:DCACHE_WAYS
|INT:4
|vpiParameter:
\_parameter: (DIV_ALGORITHM), line:67
|vpiName:DIV_ALGORITHM
|INT:0
|vpiParameter:
\_parameter: (DIV_UNIT_WB_ID), line:192
|vpiName:DIV_UNIT_WB_ID
|INT:2
|vpiParameter:
\_parameter: (DTLB_DEPTH), line:152
|vpiName:DTLB_DEPTH
|INT:512
|vpiParameter:
\_parameter: (DTLB_WAYS), line:151
|vpiName:DTLB_WAYS
|INT:32
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (ENABLE_M_MODE), line:110
|vpiName:ENABLE_M_MODE
|INT:-2146435073
|vpiParameter:
\_parameter: (ENABLE_S_MODE), line:36
|vpiName:ENABLE_S_MODE
|INT:0
|vpiParameter:
\_parameter: (ENABLE_TRACE_INTERFACE), line:172
|vpiName:ENABLE_TRACE_INTERFACE
|INT:2
|vpiParameter:
\_parameter: (FETCH_BUFFER_DEPTH), line:168
|vpiName:FETCH_BUFFER_DEPTH
|INT:512
|vpiParameter:
\_parameter: (FPGA_VENDOR), line:110
|vpiName:FPGA_VENDOR
|INT:0
|vpiParameter:
\_parameter: (GC_UNIT_ID), line:196
|vpiName:GC_UNIT_ID
|INT:4
|vpiParameter:
\_parameter: (ICACHE_LINES), line:121
|vpiName:ICACHE_LINES
|INT:2
|vpiParameter:
\_parameter: (ICACHE_LINE_ADDR_W), line:123
|vpiName:ICACHE_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_LINE_W), line:124
|vpiName:ICACHE_LINE_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_SUB_LINE_ADDR_W), line:125
|vpiName:ICACHE_SUB_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_TAG_W), line:126
|vpiName:ICACHE_TAG_W
|INT:-2147483648
|vpiParameter:
\_parameter: (ICACHE_WAYS), line:122
|vpiName:ICACHE_WAYS
|INT:1
|vpiParameter:
\_parameter: (ITLB_DEPTH), line:146
|vpiName:ITLB_DEPTH
|INT:32
|vpiParameter:
\_parameter: (ITLB_WAYS), line:145
|vpiName:ITLB_WAYS
|INT:4
|vpiParameter:
\_parameter: (L1_CONNECTIONS), line:177
|vpiName:L1_CONNECTIONS
|INT:9
|vpiParameter:
\_parameter: (L1_DCACHE_ID), line:178
|vpiName:L1_DCACHE_ID
|INT:4
|vpiParameter:
\_parameter: (L1_DMMU_ID), line:179
|vpiName:L1_DMMU_ID
|INT:2
|vpiParameter:
\_parameter: (L1_ICACHE_ID), line:180
|vpiName:L1_ICACHE_ID
|INT:19
|vpiParameter:
\_parameter: (L1_IMMU_ID), line:181
|vpiName:L1_IMMU_ID
|INT:0
|vpiParameter:
\_parameter: (LINES), line:28
|vpiName:LINES
|INT:512
|vpiParameter:
\_parameter: (LS_UNIT_WB_ID), line:191
|vpiName:LS_UNIT_WB_ID
|INT:1
|vpiParameter:
\_parameter: (MAX_INFLIGHT_COUNT), line:167
|vpiName:MAX_INFLIGHT_COUNT
|INT:19
|vpiParameter:
\_parameter: (MEMORY_ADDR_H), line:103
|vpiName:MEMORY_ADDR_H
|INT:12
|vpiParameter:
\_parameter: (MEMORY_ADDR_L), line:102
|vpiName:MEMORY_ADDR_L
|INT:11
|vpiParameter:
\_parameter: (MEMORY_BIT_CHECK), line:104
|vpiName:MEMORY_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (MUL_UNIT_WB_ID), line:193
|vpiName:MUL_UNIT_WB_ID
|INT:512
|vpiParameter:
\_parameter: (NUM_UNITS), line:188
|vpiName:NUM_UNITS
|INT:2
|vpiParameter:
\_parameter: (NUM_WB_UNITS), line:186
|vpiName:NUM_WB_UNITS
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (RAS_DEPTH), line:161
|vpiName:RAS_DEPTH
|INT:2
|vpiParameter:
\_parameter: (RESET_VEC), line:39
|vpiName:RESET_VEC
|INT:-2147483648
|vpiParameter:
\_parameter: (SCRATCH_ADDR_H), line:99
|vpiName:SCRATCH_ADDR_H
|INT:9
|vpiParameter:
\_parameter: (SCRATCH_ADDR_L), line:98
|vpiName:SCRATCH_ADDR_L
|INT:8
|vpiParameter:
\_parameter: (SCRATCH_BIT_CHECK), line:100
|vpiName:SCRATCH_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (USE_AMO), line:70
|vpiName:USE_AMO
|INT:1
|vpiParameter:
\_parameter: (USE_BRANCH_PREDICTOR), line:158
|vpiName:USE_BRANCH_PREDICTOR
|INT:2
|vpiParameter:
\_parameter: (USE_BUS), line:88
|vpiName:USE_BUS
|INT:4
|vpiParameter:
\_parameter: (USE_DCACHE), line:92
|vpiName:USE_DCACHE
|INT:6
|vpiParameter:
\_parameter: (USE_DIV), line:49
|vpiName:USE_DIV
|INT:1
|vpiParameter:
\_parameter: (USE_DTAG_INVALIDATIONS), line:140
|vpiName:USE_DTAG_INVALIDATIONS
|INT:1879048191
|vpiParameter:
\_parameter: (USE_D_SCRATCH_MEM), line:79
|vpiName:USE_D_SCRATCH_MEM
|INT:3
|vpiParameter:
\_parameter: (USE_ICACHE), line:93
|vpiName:USE_ICACHE
|INT:7
|vpiParameter:
\_parameter: (USE_I_SCRATCH_MEM), line:78
|vpiName:USE_I_SCRATCH_MEM
|INT:2
|vpiParameter:
\_parameter: (USE_MUL), line:48
|vpiName:USE_MUL
|INT:1
|vpiParameter:
\_parameter: (WB_UNITS_WIDTH), line:187
|vpiName:WB_UNITS_WIDTH
|INT:32
|vpiParameter:
\_parameter: (WIDTH), line:27
|vpiName:WIDTH
|INT:32
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiParameter:
\_parameter: (ALU_UNIT_WB_ID), line:190
|vpiName:ALU_UNIT_WB_ID
|INT:32
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (BRANCH_PREDICTOR_WAYS), line:159
|vpiName:BRANCH_PREDICTOR_WAYS
|INT:9
|vpiParameter:
\_parameter: (BRANCH_TABLE_ENTRIES), line:160
|vpiName:BRANCH_TABLE_ENTRIES
|INT:4
|vpiParameter:
\_parameter: (BRANCH_UNIT_ID), line:195
|vpiName:BRANCH_UNIT_ID
|INT:8
|vpiParameter:
\_parameter: (BUS_ADDR_H), line:107
|vpiName:BUS_ADDR_H
|INT:1
|vpiParameter:
\_parameter: (BUS_ADDR_L), line:106
|vpiName:BUS_ADDR_L
|INT:0
|vpiParameter:
\_parameter: (BUS_BIT_CHECK), line:108
|vpiName:BUS_BIT_CHECK
|INT:1
|vpiParameter:
\_parameter: (BUS_TYPE), line:89
|vpiName:BUS_TYPE
|INT:5
|vpiParameter:
\_parameter: (COUNTER_W), line:42
|vpiName:COUNTER_W
|INT:33
|vpiParameter:
\_parameter: (CPU_ID), line:38
|vpiName:CPU_ID
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_ADDR_WIDTH), line:113
|vpiName:C_M_AXI_ADDR_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_DATA_WIDTH), line:114
|vpiName:C_M_AXI_DATA_WIDTH
|INT:1
|vpiParameter:
\_parameter: (DCACHE_LINES), line:133
|vpiName:DCACHE_LINES
|INT:-2146435073
|vpiParameter:
\_parameter: (DCACHE_LINE_ADDR_W), line:135
|vpiName:DCACHE_LINE_ADDR_W
|INT:1073741824
|vpiParameter:
\_parameter: (DCACHE_LINE_W), line:136
|vpiName:DCACHE_LINE_W
|INT:1342177279
|vpiParameter:
\_parameter: (DCACHE_SUB_LINE_ADDR_W), line:137
|vpiName:DCACHE_SUB_LINE_ADDR_W
|INT:4
|vpiParameter:
\_parameter: (DCACHE_TAG_W), line:138
|vpiName:DCACHE_TAG_W
|INT:1610612736
|vpiParameter:
\_parameter: (DCACHE_WAYS), line:134
|vpiName:DCACHE_WAYS
|INT:4
|vpiParameter:
\_parameter: (DIV_ALGORITHM), line:67
|vpiName:DIV_ALGORITHM
|INT:0
|vpiParameter:
\_parameter: (DIV_UNIT_WB_ID), line:192
|vpiName:DIV_UNIT_WB_ID
|INT:2
|vpiParameter:
\_parameter: (DTLB_DEPTH), line:152
|vpiName:DTLB_DEPTH
|INT:512
|vpiParameter:
\_parameter: (DTLB_WAYS), line:151
|vpiName:DTLB_WAYS
|INT:32
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (ENABLE_M_MODE), line:34
|vpiName:ENABLE_M_MODE
|INT:1
|vpiParameter:
\_parameter: (ENABLE_S_MODE), line:36
|vpiName:ENABLE_S_MODE
|INT:0
|vpiParameter:
\_parameter: (ENABLE_TRACE_INTERFACE), line:172
|vpiName:ENABLE_TRACE_INTERFACE
|INT:2
|vpiParameter:
\_parameter: (FETCH_BUFFER_DEPTH), line:168
|vpiName:FETCH_BUFFER_DEPTH
|INT:512
|vpiParameter:
\_parameter: (FPGA_VENDOR), line:27
|vpiName:FPGA_VENDOR
|STRING:"xilinx"
|vpiParameter:
\_parameter: (GC_UNIT_ID), line:196
|vpiName:GC_UNIT_ID
|INT:4
|vpiParameter:
\_parameter: (ICACHE_LINES), line:121
|vpiName:ICACHE_LINES
|INT:2
|vpiParameter:
\_parameter: (ICACHE_LINE_ADDR_W), line:123
|vpiName:ICACHE_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_LINE_W), line:124
|vpiName:ICACHE_LINE_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_SUB_LINE_ADDR_W), line:125
|vpiName:ICACHE_SUB_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_TAG_W), line:126
|vpiName:ICACHE_TAG_W
|INT:-2147483648
|vpiParameter:
\_parameter: (ICACHE_WAYS), line:122
|vpiName:ICACHE_WAYS
|INT:1
|vpiParameter:
\_parameter: (ITLB_DEPTH), line:146
|vpiName:ITLB_DEPTH
|INT:32
|vpiParameter:
\_parameter: (ITLB_WAYS), line:145
|vpiName:ITLB_WAYS
|INT:4
|vpiParameter:
\_parameter: (L1_CONNECTIONS), line:177
|vpiName:L1_CONNECTIONS
|INT:9
|vpiParameter:
\_parameter: (L1_DCACHE_ID), line:178
|vpiName:L1_DCACHE_ID
|INT:4
|vpiParameter:
\_parameter: (L1_DMMU_ID), line:179
|vpiName:L1_DMMU_ID
|INT:2
|vpiParameter:
\_parameter: (L1_ICACHE_ID), line:180
|vpiName:L1_ICACHE_ID
|INT:19
|vpiParameter:
\_parameter: (L1_IMMU_ID), line:181
|vpiName:L1_IMMU_ID
|INT:0
|vpiParameter:
\_parameter: (LS_UNIT_WB_ID), line:191
|vpiName:LS_UNIT_WB_ID
|INT:1
|vpiParameter:
\_parameter: (MAX_INFLIGHT_COUNT), line:167
|vpiName:MAX_INFLIGHT_COUNT
|INT:19
|vpiParameter:
\_parameter: (MEMORY_ADDR_H), line:103
|vpiName:MEMORY_ADDR_H
|INT:12
|vpiParameter:
\_parameter: (MEMORY_ADDR_L), line:102
|vpiName:MEMORY_ADDR_L
|INT:11
|vpiParameter:
\_parameter: (MEMORY_BIT_CHECK), line:104
|vpiName:MEMORY_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (MUL_UNIT_WB_ID), line:193
|vpiName:MUL_UNIT_WB_ID
|INT:512
|vpiParameter:
\_parameter: (NUM_UNITS), line:188
|vpiName:NUM_UNITS
|INT:2
|vpiParameter:
\_parameter: (NUM_WB_UNITS), line:186
|vpiName:NUM_WB_UNITS
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (RAS_DEPTH), line:161
|vpiName:RAS_DEPTH
|INT:2
|vpiParameter:
\_parameter: (RESET_VEC), line:39
|vpiName:RESET_VEC
|INT:-2147483648
|vpiParameter:
\_parameter: (SCRATCH_ADDR_H), line:99
|vpiName:SCRATCH_ADDR_H
|INT:9
|vpiParameter:
\_parameter: (SCRATCH_ADDR_L), line:98
|vpiName:SCRATCH_ADDR_L
|INT:8
|vpiParameter:
\_parameter: (SCRATCH_BIT_CHECK), line:100
|vpiName:SCRATCH_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (USE_AMO), line:70
|vpiName:USE_AMO
|INT:1
|vpiParameter:
\_parameter: (USE_BRANCH_PREDICTOR), line:158
|vpiName:USE_BRANCH_PREDICTOR
|INT:2
|vpiParameter:
\_parameter: (USE_BUS), line:88
|vpiName:USE_BUS
|INT:4
|vpiParameter:
\_parameter: (USE_DCACHE), line:92
|vpiName:USE_DCACHE
|INT:6
|vpiParameter:
\_parameter: (USE_DIV), line:49
|vpiName:USE_DIV
|INT:1
|vpiParameter:
\_parameter: (USE_DTAG_INVALIDATIONS), line:140
|vpiName:USE_DTAG_INVALIDATIONS
|INT:1879048191
|vpiParameter:
\_parameter: (USE_D_SCRATCH_MEM), line:79
|vpiName:USE_D_SCRATCH_MEM
|INT:3
|vpiParameter:
\_parameter: (USE_ICACHE), line:93
|vpiName:USE_ICACHE
|INT:7
|vpiParameter:
\_parameter: (USE_I_SCRATCH_MEM), line:78
|vpiName:USE_I_SCRATCH_MEM
|INT:2
|vpiParameter:
\_parameter: (USE_MUL), line:48
|vpiName:USE_MUL
|INT:1
|vpiParameter:
\_parameter: (WB_UNITS_WIDTH), line:187
|vpiName:WB_UNITS_WIDTH
|INT:32
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiParameter:
\_parameter: (i), line:107
|vpiName:i
|INT:0
|vpiGenScopeArray:
\_gen_scope_array: (dtag_bank_gen[1]), line:107, parent:dcache_tag_banks
|vpiName:dtag_bank_gen[1]
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.dcache_tag_banks.dtag_bank_gen[1]
|vpiGenScope:
\_gen_scope: , parent:dtag_bank_gen[1]
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.dcache_tag_banks.dtag_bank_gen[1]
|vpiContAssign:
\_cont_assign: , line:108
|vpiRhs:
\_operation: , line:108
|vpiOpType:29
|vpiOperand:
\_bit_select: (update_way), line:108
|vpiName:update_way
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.dcache_tag_banks.dtag_bank_gen[1].update_way
|vpiIndex:
\_ref_obj: (i), line:108
|vpiName:i
|vpiOperand:
\_operation: , line:108
|vpiOpType:28
|vpiOperand:
\_bit_select: (inv_hit_way), line:108
|vpiName:inv_hit_way
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.dcache_tag_banks.dtag_bank_gen[1].inv_hit_way
|vpiIndex:
\_ref_obj: (i), line:108
|vpiName:i
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.dcache_tag_banks.dtag_bank_gen[1].i
|vpiOperand:
\_ref_obj: (extern_inv_complete), line:108
|vpiName:extern_inv_complete
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.dcache_tag_banks.dtag_bank_gen[1].extern_inv_complete
|vpiLhs:
\_bit_select: (update_tag_way), line:108
|vpiName:update_tag_way
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.dcache_tag_banks.dtag_bank_gen[1].update_tag_way
|vpiIndex:
\_ref_obj: (i), line:108
|vpiName:i
|vpiContAssign:
\_cont_assign: , line:120
|vpiRhs:
\_operation: , line:120
|vpiOpType:14
|vpiOperand:
\_ref_obj: (inv_hit_comparison_tagline), line:120
|vpiName:inv_hit_comparison_tagline
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.dcache_tag_banks.dtag_bank_gen[1].inv_hit_comparison_tagline
|vpiOperand:
\_bit_select: (inv_tag_line), line:120
|vpiName:inv_tag_line
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.dcache_tag_banks.dtag_bank_gen[1].inv_tag_line
|vpiIndex:
\_ref_obj: (i), line:120
|vpiName:i
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.dcache_tag_banks.dtag_bank_gen[1].i
|vpiLhs:
\_bit_select: (inv_hit_way), line:120
|vpiName:inv_hit_way
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.dcache_tag_banks.dtag_bank_gen[1].inv_hit_way
|vpiIndex:
\_ref_obj: (i), line:120
|vpiName:i
|vpiContAssign:
\_cont_assign: , line:121
|vpiRhs:
\_operation: , line:121
|vpiOpType:14
|vpiOperand:
\_ref_obj: (stage2_hit_comparison_tagline), line:121
|vpiName:stage2_hit_comparison_tagline
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.dcache_tag_banks.dtag_bank_gen[1].stage2_hit_comparison_tagline
|vpiOperand:
\_bit_select: (tag_line), line:121
|vpiName:tag_line
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.dcache_tag_banks.dtag_bank_gen[1].tag_line
|vpiIndex:
\_ref_obj: (i), line:121
|vpiName:i
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.dcache_tag_banks.dtag_bank_gen[1].i
|vpiLhs:
\_bit_select: (tag_hit_way), line:121
|vpiName:tag_hit_way
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.dcache_tag_banks.dtag_bank_gen[1].tag_hit_way
|vpiIndex:
\_ref_obj: (i), line:121
|vpiName:i
|vpiModule:
\_module: work@tag_bank (dtag_bank), file:third_party/cores/taiga/core/dtag_banks.sv, line:110
|vpiDefName:work@tag_bank
|vpiName:dtag_bank
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.dcache_tag_banks.dtag_bank_gen[1].dtag_bank
|vpiPort:
\_port: (clk), line:32, parent:dtag_bank
|vpiName:clk
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (clk), line:110
|vpiName:clk
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (clk), line:32, parent:dtag_bank
|vpiName:clk
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.dcache_tag_banks.dtag_bank_gen[1].dtag_bank.clk
|vpiNetType:36
|vpiPort:
\_port: (rst), line:33, parent:dtag_bank
|vpiName:rst
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (rst), line:110
|vpiName:rst
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (rst), line:33, parent:dtag_bank
|vpiName:rst
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.dcache_tag_banks.dtag_bank_gen[1].dtag_bank.rst
|vpiNetType:36
|vpiPort:
\_port: (addr_a), line:35, parent:dtag_bank
|vpiName:addr_a
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (addr_a), line:110
|vpiName:addr_a
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (addr_a), line:35, parent:dtag_bank
|vpiName:addr_a
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.dcache_tag_banks.dtag_bank_gen[1].dtag_bank.addr_a
|vpiNetType:36
|vpiRange:
\_range: , line:35
|vpiLeftRange:
\_constant: , line:35
|vpiConstType:7
|vpiDecompile:8
|vpiSize:32
|INT:8
|vpiRightRange:
\_constant: , line:35
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiPort:
\_port: (addr_b), line:36, parent:dtag_bank
|vpiName:addr_b
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (addr_b), line:110
|vpiName:addr_b
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (addr_b), line:36, parent:dtag_bank
|vpiName:addr_b
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.dcache_tag_banks.dtag_bank_gen[1].dtag_bank.addr_b
|vpiNetType:36
|vpiRange:
\_range: , line:36
|vpiLeftRange:
\_constant: , line:36
|vpiConstType:7
|vpiDecompile:8
|vpiSize:32
|INT:8
|vpiRightRange:
\_constant: , line:36
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiPort:
\_port: (en_a), line:37, parent:dtag_bank
|vpiName:en_a
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (en_a), line:110
|vpiName:en_a
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (en_a), line:37, parent:dtag_bank
|vpiName:en_a
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.dcache_tag_banks.dtag_bank_gen[1].dtag_bank.en_a
|vpiNetType:36
|vpiPort:
\_port: (en_b), line:38, parent:dtag_bank
|vpiName:en_b
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (en_b), line:110
|vpiName:en_b
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (en_b), line:38, parent:dtag_bank
|vpiName:en_b
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.dcache_tag_banks.dtag_bank_gen[1].dtag_bank.en_b
|vpiNetType:36
|vpiPort:
\_port: (wen_a), line:39, parent:dtag_bank
|vpiName:wen_a
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (wen_a), line:110
|vpiName:wen_a
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (wen_a), line:39, parent:dtag_bank
|vpiName:wen_a
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.dcache_tag_banks.dtag_bank_gen[1].dtag_bank.wen_a
|vpiNetType:36
|vpiPort:
\_port: (wen_b), line:40, parent:dtag_bank
|vpiName:wen_b
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (wen_b), line:110
|vpiName:wen_b
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (wen_b), line:40, parent:dtag_bank
|vpiName:wen_b
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.dcache_tag_banks.dtag_bank_gen[1].dtag_bank.wen_b
|vpiNetType:36
|vpiPort:
\_port: (data_in_a), line:41, parent:dtag_bank
|vpiName:data_in_a
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (data_in_a), line:110
|vpiName:data_in_a
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (data_in_a), line:41, parent:dtag_bank
|vpiName:data_in_a
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.dcache_tag_banks.dtag_bank_gen[1].dtag_bank.data_in_a
|vpiNetType:36
|vpiRange:
\_range: , line:41
|vpiLeftRange:
\_constant: , line:41
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:41
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiPort:
\_port: (data_in_b), line:42, parent:dtag_bank
|vpiName:data_in_b
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (data_in_b), line:110
|vpiName:data_in_b
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (data_in_b), line:42, parent:dtag_bank
|vpiName:data_in_b
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.dcache_tag_banks.dtag_bank_gen[1].dtag_bank.data_in_b
|vpiNetType:36
|vpiRange:
\_range: , line:42
|vpiLeftRange:
\_constant: , line:42
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:42
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiPort:
\_port: (data_out_a), line:43, parent:dtag_bank
|vpiName:data_out_a
|vpiDirection:2
|vpiHighConn:
\_ref_obj: (data_out_a), line:110
|vpiName:data_out_a
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (data_out_a), line:43, parent:dtag_bank
|vpiName:data_out_a
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.dcache_tag_banks.dtag_bank_gen[1].dtag_bank.data_out_a
|vpiNetType:36
|vpiRange:
\_range: , line:43
|vpiLeftRange:
\_constant: , line:43
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:43
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiPort:
\_port: (data_out_b), line:44, parent:dtag_bank
|vpiName:data_out_b
|vpiDirection:2
|vpiHighConn:
\_ref_obj: (data_out_b), line:110
|vpiName:data_out_b
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (data_out_b), line:44, parent:dtag_bank
|vpiName:data_out_b
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.dcache_tag_banks.dtag_bank_gen[1].dtag_bank.data_out_b
|vpiNetType:36
|vpiRange:
\_range: , line:44
|vpiLeftRange:
\_constant: , line:44
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:44
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (clk), line:32, parent:dtag_bank
|vpiNet:
\_logic_net: (rst), line:33, parent:dtag_bank
|vpiNet:
\_logic_net: (addr_a), line:35, parent:dtag_bank
|vpiNet:
\_logic_net: (addr_b), line:36, parent:dtag_bank
|vpiNet:
\_logic_net: (en_a), line:37, parent:dtag_bank
|vpiNet:
\_logic_net: (en_b), line:38, parent:dtag_bank
|vpiNet:
\_logic_net: (wen_a), line:39, parent:dtag_bank
|vpiNet:
\_logic_net: (wen_b), line:40, parent:dtag_bank
|vpiNet:
\_logic_net: (data_in_a), line:41, parent:dtag_bank
|vpiNet:
\_logic_net: (data_in_b), line:42, parent:dtag_bank
|vpiNet:
\_logic_net: (data_out_a), line:43, parent:dtag_bank
|vpiNet:
\_logic_net: (data_out_b), line:44, parent:dtag_bank
|vpiNet:
\_logic_net: (i), line:49, parent:dtag_bank
|vpiName:i
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.dcache_tag_banks.dtag_bank_gen[1].dtag_bank.i
|vpiArrayNet:
\_array_net: (tag_entry), line:47, parent:dtag_bank
|vpiName:tag_entry
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.dcache_tag_banks.dtag_bank_gen[1].dtag_bank.tag_entry
|vpiSize:512
|vpiNet:
\_logic_net: , parent:tag_entry
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.dcache_tag_banks.dtag_bank_gen[1].dtag_bank.tag_entry
|vpiNetType:36
|vpiRange:
\_range: , line:47
|vpiLeftRange:
\_constant: , line:47
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:47
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiRange:
\_range: , line:47
|vpiLeftRange:
\_constant: , line:47
|vpiConstType:7
|vpiDecompile:511
|vpiSize:32
|INT:511
|vpiRightRange:
\_constant: , line:47
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiParameter:
\_parameter: (ALU_UNIT_WB_ID), line:190
|vpiName:ALU_UNIT_WB_ID
|INT:32
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (BRANCH_PREDICTOR_WAYS), line:159
|vpiName:BRANCH_PREDICTOR_WAYS
|INT:9
|vpiParameter:
\_parameter: (BRANCH_TABLE_ENTRIES), line:160
|vpiName:BRANCH_TABLE_ENTRIES
|INT:4
|vpiParameter:
\_parameter: (BRANCH_UNIT_ID), line:195
|vpiName:BRANCH_UNIT_ID
|INT:8
|vpiParameter:
\_parameter: (BUS_ADDR_H), line:107
|vpiName:BUS_ADDR_H
|INT:1
|vpiParameter:
\_parameter: (BUS_ADDR_L), line:106
|vpiName:BUS_ADDR_L
|INT:0
|vpiParameter:
\_parameter: (BUS_BIT_CHECK), line:108
|vpiName:BUS_BIT_CHECK
|INT:1
|vpiParameter:
\_parameter: (BUS_TYPE), line:89
|vpiName:BUS_TYPE
|INT:5
|vpiParameter:
\_parameter: (COUNTER_W), line:42
|vpiName:COUNTER_W
|INT:33
|vpiParameter:
\_parameter: (CPU_ID), line:38
|vpiName:CPU_ID
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_ADDR_WIDTH), line:113
|vpiName:C_M_AXI_ADDR_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_DATA_WIDTH), line:114
|vpiName:C_M_AXI_DATA_WIDTH
|INT:1
|vpiParameter:
\_parameter: (DCACHE_LINES), line:133
|vpiName:DCACHE_LINES
|INT:-2146435073
|vpiParameter:
\_parameter: (DCACHE_LINE_ADDR_W), line:135
|vpiName:DCACHE_LINE_ADDR_W
|INT:1073741824
|vpiParameter:
\_parameter: (DCACHE_LINE_W), line:136
|vpiName:DCACHE_LINE_W
|INT:1342177279
|vpiParameter:
\_parameter: (DCACHE_SUB_LINE_ADDR_W), line:137
|vpiName:DCACHE_SUB_LINE_ADDR_W
|INT:4
|vpiParameter:
\_parameter: (DCACHE_TAG_W), line:138
|vpiName:DCACHE_TAG_W
|INT:1610612736
|vpiParameter:
\_parameter: (DCACHE_WAYS), line:134
|vpiName:DCACHE_WAYS
|INT:4
|vpiParameter:
\_parameter: (DIV_ALGORITHM), line:67
|vpiName:DIV_ALGORITHM
|INT:0
|vpiParameter:
\_parameter: (DIV_UNIT_WB_ID), line:192
|vpiName:DIV_UNIT_WB_ID
|INT:2
|vpiParameter:
\_parameter: (DTLB_DEPTH), line:152
|vpiName:DTLB_DEPTH
|INT:512
|vpiParameter:
\_parameter: (DTLB_WAYS), line:151
|vpiName:DTLB_WAYS
|INT:32
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (ENABLE_M_MODE), line:110
|vpiName:ENABLE_M_MODE
|INT:-2146435073
|vpiParameter:
\_parameter: (ENABLE_S_MODE), line:36
|vpiName:ENABLE_S_MODE
|INT:0
|vpiParameter:
\_parameter: (ENABLE_TRACE_INTERFACE), line:172
|vpiName:ENABLE_TRACE_INTERFACE
|INT:2
|vpiParameter:
\_parameter: (FETCH_BUFFER_DEPTH), line:168
|vpiName:FETCH_BUFFER_DEPTH
|INT:512
|vpiParameter:
\_parameter: (FPGA_VENDOR), line:110
|vpiName:FPGA_VENDOR
|INT:0
|vpiParameter:
\_parameter: (GC_UNIT_ID), line:196
|vpiName:GC_UNIT_ID
|INT:4
|vpiParameter:
\_parameter: (ICACHE_LINES), line:121
|vpiName:ICACHE_LINES
|INT:2
|vpiParameter:
\_parameter: (ICACHE_LINE_ADDR_W), line:123
|vpiName:ICACHE_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_LINE_W), line:124
|vpiName:ICACHE_LINE_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_SUB_LINE_ADDR_W), line:125
|vpiName:ICACHE_SUB_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_TAG_W), line:126
|vpiName:ICACHE_TAG_W
|INT:-2147483648
|vpiParameter:
\_parameter: (ICACHE_WAYS), line:122
|vpiName:ICACHE_WAYS
|INT:1
|vpiParameter:
\_parameter: (ITLB_DEPTH), line:146
|vpiName:ITLB_DEPTH
|INT:32
|vpiParameter:
\_parameter: (ITLB_WAYS), line:145
|vpiName:ITLB_WAYS
|INT:4
|vpiParameter:
\_parameter: (L1_CONNECTIONS), line:177
|vpiName:L1_CONNECTIONS
|INT:9
|vpiParameter:
\_parameter: (L1_DCACHE_ID), line:178
|vpiName:L1_DCACHE_ID
|INT:4
|vpiParameter:
\_parameter: (L1_DMMU_ID), line:179
|vpiName:L1_DMMU_ID
|INT:2
|vpiParameter:
\_parameter: (L1_ICACHE_ID), line:180
|vpiName:L1_ICACHE_ID
|INT:19
|vpiParameter:
\_parameter: (L1_IMMU_ID), line:181
|vpiName:L1_IMMU_ID
|INT:0
|vpiParameter:
\_parameter: (LINES), line:28
|vpiName:LINES
|INT:512
|vpiParameter:
\_parameter: (LS_UNIT_WB_ID), line:191
|vpiName:LS_UNIT_WB_ID
|INT:1
|vpiParameter:
\_parameter: (MAX_INFLIGHT_COUNT), line:167
|vpiName:MAX_INFLIGHT_COUNT
|INT:19
|vpiParameter:
\_parameter: (MEMORY_ADDR_H), line:103
|vpiName:MEMORY_ADDR_H
|INT:12
|vpiParameter:
\_parameter: (MEMORY_ADDR_L), line:102
|vpiName:MEMORY_ADDR_L
|INT:11
|vpiParameter:
\_parameter: (MEMORY_BIT_CHECK), line:104
|vpiName:MEMORY_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (MUL_UNIT_WB_ID), line:193
|vpiName:MUL_UNIT_WB_ID
|INT:512
|vpiParameter:
\_parameter: (NUM_UNITS), line:188
|vpiName:NUM_UNITS
|INT:2
|vpiParameter:
\_parameter: (NUM_WB_UNITS), line:186
|vpiName:NUM_WB_UNITS
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (RAS_DEPTH), line:161
|vpiName:RAS_DEPTH
|INT:2
|vpiParameter:
\_parameter: (RESET_VEC), line:39
|vpiName:RESET_VEC
|INT:-2147483648
|vpiParameter:
\_parameter: (SCRATCH_ADDR_H), line:99
|vpiName:SCRATCH_ADDR_H
|INT:9
|vpiParameter:
\_parameter: (SCRATCH_ADDR_L), line:98
|vpiName:SCRATCH_ADDR_L
|INT:8
|vpiParameter:
\_parameter: (SCRATCH_BIT_CHECK), line:100
|vpiName:SCRATCH_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (USE_AMO), line:70
|vpiName:USE_AMO
|INT:1
|vpiParameter:
\_parameter: (USE_BRANCH_PREDICTOR), line:158
|vpiName:USE_BRANCH_PREDICTOR
|INT:2
|vpiParameter:
\_parameter: (USE_BUS), line:88
|vpiName:USE_BUS
|INT:4
|vpiParameter:
\_parameter: (USE_DCACHE), line:92
|vpiName:USE_DCACHE
|INT:6
|vpiParameter:
\_parameter: (USE_DIV), line:49
|vpiName:USE_DIV
|INT:1
|vpiParameter:
\_parameter: (USE_DTAG_INVALIDATIONS), line:140
|vpiName:USE_DTAG_INVALIDATIONS
|INT:1879048191
|vpiParameter:
\_parameter: (USE_D_SCRATCH_MEM), line:79
|vpiName:USE_D_SCRATCH_MEM
|INT:3
|vpiParameter:
\_parameter: (USE_ICACHE), line:93
|vpiName:USE_ICACHE
|INT:7
|vpiParameter:
\_parameter: (USE_I_SCRATCH_MEM), line:78
|vpiName:USE_I_SCRATCH_MEM
|INT:2
|vpiParameter:
\_parameter: (USE_MUL), line:48
|vpiName:USE_MUL
|INT:1
|vpiParameter:
\_parameter: (WB_UNITS_WIDTH), line:187
|vpiName:WB_UNITS_WIDTH
|INT:32
|vpiParameter:
\_parameter: (WIDTH), line:27
|vpiName:WIDTH
|INT:32
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiParameter:
\_parameter: (ALU_UNIT_WB_ID), line:190
|vpiName:ALU_UNIT_WB_ID
|INT:32
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (BRANCH_PREDICTOR_WAYS), line:159
|vpiName:BRANCH_PREDICTOR_WAYS
|INT:9
|vpiParameter:
\_parameter: (BRANCH_TABLE_ENTRIES), line:160
|vpiName:BRANCH_TABLE_ENTRIES
|INT:4
|vpiParameter:
\_parameter: (BRANCH_UNIT_ID), line:195
|vpiName:BRANCH_UNIT_ID
|INT:8
|vpiParameter:
\_parameter: (BUS_ADDR_H), line:107
|vpiName:BUS_ADDR_H
|INT:1
|vpiParameter:
\_parameter: (BUS_ADDR_L), line:106
|vpiName:BUS_ADDR_L
|INT:0
|vpiParameter:
\_parameter: (BUS_BIT_CHECK), line:108
|vpiName:BUS_BIT_CHECK
|INT:1
|vpiParameter:
\_parameter: (BUS_TYPE), line:89
|vpiName:BUS_TYPE
|INT:5
|vpiParameter:
\_parameter: (COUNTER_W), line:42
|vpiName:COUNTER_W
|INT:33
|vpiParameter:
\_parameter: (CPU_ID), line:38
|vpiName:CPU_ID
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_ADDR_WIDTH), line:113
|vpiName:C_M_AXI_ADDR_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_DATA_WIDTH), line:114
|vpiName:C_M_AXI_DATA_WIDTH
|INT:1
|vpiParameter:
\_parameter: (DCACHE_LINES), line:133
|vpiName:DCACHE_LINES
|INT:-2146435073
|vpiParameter:
\_parameter: (DCACHE_LINE_ADDR_W), line:135
|vpiName:DCACHE_LINE_ADDR_W
|INT:1073741824
|vpiParameter:
\_parameter: (DCACHE_LINE_W), line:136
|vpiName:DCACHE_LINE_W
|INT:1342177279
|vpiParameter:
\_parameter: (DCACHE_SUB_LINE_ADDR_W), line:137
|vpiName:DCACHE_SUB_LINE_ADDR_W
|INT:4
|vpiParameter:
\_parameter: (DCACHE_TAG_W), line:138
|vpiName:DCACHE_TAG_W
|INT:1610612736
|vpiParameter:
\_parameter: (DCACHE_WAYS), line:134
|vpiName:DCACHE_WAYS
|INT:4
|vpiParameter:
\_parameter: (DIV_ALGORITHM), line:67
|vpiName:DIV_ALGORITHM
|INT:0
|vpiParameter:
\_parameter: (DIV_UNIT_WB_ID), line:192
|vpiName:DIV_UNIT_WB_ID
|INT:2
|vpiParameter:
\_parameter: (DTLB_DEPTH), line:152
|vpiName:DTLB_DEPTH
|INT:512
|vpiParameter:
\_parameter: (DTLB_WAYS), line:151
|vpiName:DTLB_WAYS
|INT:32
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (ENABLE_M_MODE), line:34
|vpiName:ENABLE_M_MODE
|INT:1
|vpiParameter:
\_parameter: (ENABLE_S_MODE), line:36
|vpiName:ENABLE_S_MODE
|INT:0
|vpiParameter:
\_parameter: (ENABLE_TRACE_INTERFACE), line:172
|vpiName:ENABLE_TRACE_INTERFACE
|INT:2
|vpiParameter:
\_parameter: (FETCH_BUFFER_DEPTH), line:168
|vpiName:FETCH_BUFFER_DEPTH
|INT:512
|vpiParameter:
\_parameter: (FPGA_VENDOR), line:27
|vpiName:FPGA_VENDOR
|STRING:"xilinx"
|vpiParameter:
\_parameter: (GC_UNIT_ID), line:196
|vpiName:GC_UNIT_ID
|INT:4
|vpiParameter:
\_parameter: (ICACHE_LINES), line:121
|vpiName:ICACHE_LINES
|INT:2
|vpiParameter:
\_parameter: (ICACHE_LINE_ADDR_W), line:123
|vpiName:ICACHE_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_LINE_W), line:124
|vpiName:ICACHE_LINE_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_SUB_LINE_ADDR_W), line:125
|vpiName:ICACHE_SUB_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_TAG_W), line:126
|vpiName:ICACHE_TAG_W
|INT:-2147483648
|vpiParameter:
\_parameter: (ICACHE_WAYS), line:122
|vpiName:ICACHE_WAYS
|INT:1
|vpiParameter:
\_parameter: (ITLB_DEPTH), line:146
|vpiName:ITLB_DEPTH
|INT:32
|vpiParameter:
\_parameter: (ITLB_WAYS), line:145
|vpiName:ITLB_WAYS
|INT:4
|vpiParameter:
\_parameter: (L1_CONNECTIONS), line:177
|vpiName:L1_CONNECTIONS
|INT:9
|vpiParameter:
\_parameter: (L1_DCACHE_ID), line:178
|vpiName:L1_DCACHE_ID
|INT:4
|vpiParameter:
\_parameter: (L1_DMMU_ID), line:179
|vpiName:L1_DMMU_ID
|INT:2
|vpiParameter:
\_parameter: (L1_ICACHE_ID), line:180
|vpiName:L1_ICACHE_ID
|INT:19
|vpiParameter:
\_parameter: (L1_IMMU_ID), line:181
|vpiName:L1_IMMU_ID
|INT:0
|vpiParameter:
\_parameter: (LS_UNIT_WB_ID), line:191
|vpiName:LS_UNIT_WB_ID
|INT:1
|vpiParameter:
\_parameter: (MAX_INFLIGHT_COUNT), line:167
|vpiName:MAX_INFLIGHT_COUNT
|INT:19
|vpiParameter:
\_parameter: (MEMORY_ADDR_H), line:103
|vpiName:MEMORY_ADDR_H
|INT:12
|vpiParameter:
\_parameter: (MEMORY_ADDR_L), line:102
|vpiName:MEMORY_ADDR_L
|INT:11
|vpiParameter:
\_parameter: (MEMORY_BIT_CHECK), line:104
|vpiName:MEMORY_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (MUL_UNIT_WB_ID), line:193
|vpiName:MUL_UNIT_WB_ID
|INT:512
|vpiParameter:
\_parameter: (NUM_UNITS), line:188
|vpiName:NUM_UNITS
|INT:2
|vpiParameter:
\_parameter: (NUM_WB_UNITS), line:186
|vpiName:NUM_WB_UNITS
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (RAS_DEPTH), line:161
|vpiName:RAS_DEPTH
|INT:2
|vpiParameter:
\_parameter: (RESET_VEC), line:39
|vpiName:RESET_VEC
|INT:-2147483648
|vpiParameter:
\_parameter: (SCRATCH_ADDR_H), line:99
|vpiName:SCRATCH_ADDR_H
|INT:9
|vpiParameter:
\_parameter: (SCRATCH_ADDR_L), line:98
|vpiName:SCRATCH_ADDR_L
|INT:8
|vpiParameter:
\_parameter: (SCRATCH_BIT_CHECK), line:100
|vpiName:SCRATCH_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (USE_AMO), line:70
|vpiName:USE_AMO
|INT:1
|vpiParameter:
\_parameter: (USE_BRANCH_PREDICTOR), line:158
|vpiName:USE_BRANCH_PREDICTOR
|INT:2
|vpiParameter:
\_parameter: (USE_BUS), line:88
|vpiName:USE_BUS
|INT:4
|vpiParameter:
\_parameter: (USE_DCACHE), line:92
|vpiName:USE_DCACHE
|INT:6
|vpiParameter:
\_parameter: (USE_DIV), line:49
|vpiName:USE_DIV
|INT:1
|vpiParameter:
\_parameter: (USE_DTAG_INVALIDATIONS), line:140
|vpiName:USE_DTAG_INVALIDATIONS
|INT:1879048191
|vpiParameter:
\_parameter: (USE_D_SCRATCH_MEM), line:79
|vpiName:USE_D_SCRATCH_MEM
|INT:3
|vpiParameter:
\_parameter: (USE_ICACHE), line:93
|vpiName:USE_ICACHE
|INT:7
|vpiParameter:
\_parameter: (USE_I_SCRATCH_MEM), line:78
|vpiName:USE_I_SCRATCH_MEM
|INT:2
|vpiParameter:
\_parameter: (USE_MUL), line:48
|vpiName:USE_MUL
|INT:1
|vpiParameter:
\_parameter: (WB_UNITS_WIDTH), line:187
|vpiName:WB_UNITS_WIDTH
|INT:32
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiParameter:
\_parameter: (i), line:107
|vpiName:i
|INT:1
|vpiGenScopeArray:
\_gen_scope_array: (dtag_bank_gen[2]), line:107, parent:dcache_tag_banks
|vpiName:dtag_bank_gen[2]
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.dcache_tag_banks.dtag_bank_gen[2]
|vpiGenScope:
\_gen_scope: , parent:dtag_bank_gen[2]
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.dcache_tag_banks.dtag_bank_gen[2]
|vpiContAssign:
\_cont_assign: , line:108
|vpiRhs:
\_operation: , line:108
|vpiOpType:29
|vpiOperand:
\_bit_select: (update_way), line:108
|vpiName:update_way
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.dcache_tag_banks.dtag_bank_gen[2].update_way
|vpiIndex:
\_ref_obj: (i), line:108
|vpiName:i
|vpiOperand:
\_operation: , line:108
|vpiOpType:28
|vpiOperand:
\_bit_select: (inv_hit_way), line:108
|vpiName:inv_hit_way
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.dcache_tag_banks.dtag_bank_gen[2].inv_hit_way
|vpiIndex:
\_ref_obj: (i), line:108
|vpiName:i
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.dcache_tag_banks.dtag_bank_gen[2].i
|vpiOperand:
\_ref_obj: (extern_inv_complete), line:108
|vpiName:extern_inv_complete
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.dcache_tag_banks.dtag_bank_gen[2].extern_inv_complete
|vpiLhs:
\_bit_select: (update_tag_way), line:108
|vpiName:update_tag_way
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.dcache_tag_banks.dtag_bank_gen[2].update_tag_way
|vpiIndex:
\_ref_obj: (i), line:108
|vpiName:i
|vpiContAssign:
\_cont_assign: , line:120
|vpiRhs:
\_operation: , line:120
|vpiOpType:14
|vpiOperand:
\_ref_obj: (inv_hit_comparison_tagline), line:120
|vpiName:inv_hit_comparison_tagline
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.dcache_tag_banks.dtag_bank_gen[2].inv_hit_comparison_tagline
|vpiOperand:
\_bit_select: (inv_tag_line), line:120
|vpiName:inv_tag_line
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.dcache_tag_banks.dtag_bank_gen[2].inv_tag_line
|vpiIndex:
\_ref_obj: (i), line:120
|vpiName:i
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.dcache_tag_banks.dtag_bank_gen[2].i
|vpiLhs:
\_bit_select: (inv_hit_way), line:120
|vpiName:inv_hit_way
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.dcache_tag_banks.dtag_bank_gen[2].inv_hit_way
|vpiIndex:
\_ref_obj: (i), line:120
|vpiName:i
|vpiContAssign:
\_cont_assign: , line:121
|vpiRhs:
\_operation: , line:121
|vpiOpType:14
|vpiOperand:
\_ref_obj: (stage2_hit_comparison_tagline), line:121
|vpiName:stage2_hit_comparison_tagline
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.dcache_tag_banks.dtag_bank_gen[2].stage2_hit_comparison_tagline
|vpiOperand:
\_bit_select: (tag_line), line:121
|vpiName:tag_line
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.dcache_tag_banks.dtag_bank_gen[2].tag_line
|vpiIndex:
\_ref_obj: (i), line:121
|vpiName:i
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.dcache_tag_banks.dtag_bank_gen[2].i
|vpiLhs:
\_bit_select: (tag_hit_way), line:121
|vpiName:tag_hit_way
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.dcache_tag_banks.dtag_bank_gen[2].tag_hit_way
|vpiIndex:
\_ref_obj: (i), line:121
|vpiName:i
|vpiModule:
\_module: work@tag_bank (dtag_bank), file:third_party/cores/taiga/core/dtag_banks.sv, line:110
|vpiDefName:work@tag_bank
|vpiName:dtag_bank
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.dcache_tag_banks.dtag_bank_gen[2].dtag_bank
|vpiPort:
\_port: (clk), line:32, parent:dtag_bank
|vpiName:clk
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (clk), line:110
|vpiName:clk
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (clk), line:32, parent:dtag_bank
|vpiName:clk
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.dcache_tag_banks.dtag_bank_gen[2].dtag_bank.clk
|vpiNetType:36
|vpiPort:
\_port: (rst), line:33, parent:dtag_bank
|vpiName:rst
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (rst), line:110
|vpiName:rst
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (rst), line:33, parent:dtag_bank
|vpiName:rst
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.dcache_tag_banks.dtag_bank_gen[2].dtag_bank.rst
|vpiNetType:36
|vpiPort:
\_port: (addr_a), line:35, parent:dtag_bank
|vpiName:addr_a
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (addr_a), line:110
|vpiName:addr_a
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (addr_a), line:35, parent:dtag_bank
|vpiName:addr_a
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.dcache_tag_banks.dtag_bank_gen[2].dtag_bank.addr_a
|vpiNetType:36
|vpiRange:
\_range: , line:35
|vpiLeftRange:
\_constant: , line:35
|vpiConstType:7
|vpiDecompile:8
|vpiSize:32
|INT:8
|vpiRightRange:
\_constant: , line:35
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiPort:
\_port: (addr_b), line:36, parent:dtag_bank
|vpiName:addr_b
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (addr_b), line:110
|vpiName:addr_b
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (addr_b), line:36, parent:dtag_bank
|vpiName:addr_b
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.dcache_tag_banks.dtag_bank_gen[2].dtag_bank.addr_b
|vpiNetType:36
|vpiRange:
\_range: , line:36
|vpiLeftRange:
\_constant: , line:36
|vpiConstType:7
|vpiDecompile:8
|vpiSize:32
|INT:8
|vpiRightRange:
\_constant: , line:36
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiPort:
\_port: (en_a), line:37, parent:dtag_bank
|vpiName:en_a
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (en_a), line:110
|vpiName:en_a
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (en_a), line:37, parent:dtag_bank
|vpiName:en_a
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.dcache_tag_banks.dtag_bank_gen[2].dtag_bank.en_a
|vpiNetType:36
|vpiPort:
\_port: (en_b), line:38, parent:dtag_bank
|vpiName:en_b
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (en_b), line:110
|vpiName:en_b
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (en_b), line:38, parent:dtag_bank
|vpiName:en_b
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.dcache_tag_banks.dtag_bank_gen[2].dtag_bank.en_b
|vpiNetType:36
|vpiPort:
\_port: (wen_a), line:39, parent:dtag_bank
|vpiName:wen_a
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (wen_a), line:110
|vpiName:wen_a
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (wen_a), line:39, parent:dtag_bank
|vpiName:wen_a
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.dcache_tag_banks.dtag_bank_gen[2].dtag_bank.wen_a
|vpiNetType:36
|vpiPort:
\_port: (wen_b), line:40, parent:dtag_bank
|vpiName:wen_b
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (wen_b), line:110
|vpiName:wen_b
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (wen_b), line:40, parent:dtag_bank
|vpiName:wen_b
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.dcache_tag_banks.dtag_bank_gen[2].dtag_bank.wen_b
|vpiNetType:36
|vpiPort:
\_port: (data_in_a), line:41, parent:dtag_bank
|vpiName:data_in_a
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (data_in_a), line:110
|vpiName:data_in_a
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (data_in_a), line:41, parent:dtag_bank
|vpiName:data_in_a
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.dcache_tag_banks.dtag_bank_gen[2].dtag_bank.data_in_a
|vpiNetType:36
|vpiRange:
\_range: , line:41
|vpiLeftRange:
\_constant: , line:41
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:41
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiPort:
\_port: (data_in_b), line:42, parent:dtag_bank
|vpiName:data_in_b
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (data_in_b), line:110
|vpiName:data_in_b
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (data_in_b), line:42, parent:dtag_bank
|vpiName:data_in_b
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.dcache_tag_banks.dtag_bank_gen[2].dtag_bank.data_in_b
|vpiNetType:36
|vpiRange:
\_range: , line:42
|vpiLeftRange:
\_constant: , line:42
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:42
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiPort:
\_port: (data_out_a), line:43, parent:dtag_bank
|vpiName:data_out_a
|vpiDirection:2
|vpiHighConn:
\_ref_obj: (data_out_a), line:110
|vpiName:data_out_a
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (data_out_a), line:43, parent:dtag_bank
|vpiName:data_out_a
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.dcache_tag_banks.dtag_bank_gen[2].dtag_bank.data_out_a
|vpiNetType:36
|vpiRange:
\_range: , line:43
|vpiLeftRange:
\_constant: , line:43
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:43
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiPort:
\_port: (data_out_b), line:44, parent:dtag_bank
|vpiName:data_out_b
|vpiDirection:2
|vpiHighConn:
\_ref_obj: (data_out_b), line:110
|vpiName:data_out_b
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (data_out_b), line:44, parent:dtag_bank
|vpiName:data_out_b
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.dcache_tag_banks.dtag_bank_gen[2].dtag_bank.data_out_b
|vpiNetType:36
|vpiRange:
\_range: , line:44
|vpiLeftRange:
\_constant: , line:44
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:44
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (clk), line:32, parent:dtag_bank
|vpiNet:
\_logic_net: (rst), line:33, parent:dtag_bank
|vpiNet:
\_logic_net: (addr_a), line:35, parent:dtag_bank
|vpiNet:
\_logic_net: (addr_b), line:36, parent:dtag_bank
|vpiNet:
\_logic_net: (en_a), line:37, parent:dtag_bank
|vpiNet:
\_logic_net: (en_b), line:38, parent:dtag_bank
|vpiNet:
\_logic_net: (wen_a), line:39, parent:dtag_bank
|vpiNet:
\_logic_net: (wen_b), line:40, parent:dtag_bank
|vpiNet:
\_logic_net: (data_in_a), line:41, parent:dtag_bank
|vpiNet:
\_logic_net: (data_in_b), line:42, parent:dtag_bank
|vpiNet:
\_logic_net: (data_out_a), line:43, parent:dtag_bank
|vpiNet:
\_logic_net: (data_out_b), line:44, parent:dtag_bank
|vpiNet:
\_logic_net: (i), line:49, parent:dtag_bank
|vpiName:i
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.dcache_tag_banks.dtag_bank_gen[2].dtag_bank.i
|vpiArrayNet:
\_array_net: (tag_entry), line:47, parent:dtag_bank
|vpiName:tag_entry
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.dcache_tag_banks.dtag_bank_gen[2].dtag_bank.tag_entry
|vpiSize:512
|vpiNet:
\_logic_net: , parent:tag_entry
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.dcache_tag_banks.dtag_bank_gen[2].dtag_bank.tag_entry
|vpiNetType:36
|vpiRange:
\_range: , line:47
|vpiLeftRange:
\_constant: , line:47
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:47
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiRange:
\_range: , line:47
|vpiLeftRange:
\_constant: , line:47
|vpiConstType:7
|vpiDecompile:511
|vpiSize:32
|INT:511
|vpiRightRange:
\_constant: , line:47
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiParameter:
\_parameter: (ALU_UNIT_WB_ID), line:190
|vpiName:ALU_UNIT_WB_ID
|INT:32
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (BRANCH_PREDICTOR_WAYS), line:159
|vpiName:BRANCH_PREDICTOR_WAYS
|INT:9
|vpiParameter:
\_parameter: (BRANCH_TABLE_ENTRIES), line:160
|vpiName:BRANCH_TABLE_ENTRIES
|INT:4
|vpiParameter:
\_parameter: (BRANCH_UNIT_ID), line:195
|vpiName:BRANCH_UNIT_ID
|INT:8
|vpiParameter:
\_parameter: (BUS_ADDR_H), line:107
|vpiName:BUS_ADDR_H
|INT:1
|vpiParameter:
\_parameter: (BUS_ADDR_L), line:106
|vpiName:BUS_ADDR_L
|INT:0
|vpiParameter:
\_parameter: (BUS_BIT_CHECK), line:108
|vpiName:BUS_BIT_CHECK
|INT:1
|vpiParameter:
\_parameter: (BUS_TYPE), line:89
|vpiName:BUS_TYPE
|INT:5
|vpiParameter:
\_parameter: (COUNTER_W), line:42
|vpiName:COUNTER_W
|INT:33
|vpiParameter:
\_parameter: (CPU_ID), line:38
|vpiName:CPU_ID
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_ADDR_WIDTH), line:113
|vpiName:C_M_AXI_ADDR_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_DATA_WIDTH), line:114
|vpiName:C_M_AXI_DATA_WIDTH
|INT:1
|vpiParameter:
\_parameter: (DCACHE_LINES), line:133
|vpiName:DCACHE_LINES
|INT:-2146435073
|vpiParameter:
\_parameter: (DCACHE_LINE_ADDR_W), line:135
|vpiName:DCACHE_LINE_ADDR_W
|INT:1073741824
|vpiParameter:
\_parameter: (DCACHE_LINE_W), line:136
|vpiName:DCACHE_LINE_W
|INT:1342177279
|vpiParameter:
\_parameter: (DCACHE_SUB_LINE_ADDR_W), line:137
|vpiName:DCACHE_SUB_LINE_ADDR_W
|INT:4
|vpiParameter:
\_parameter: (DCACHE_TAG_W), line:138
|vpiName:DCACHE_TAG_W
|INT:1610612736
|vpiParameter:
\_parameter: (DCACHE_WAYS), line:134
|vpiName:DCACHE_WAYS
|INT:4
|vpiParameter:
\_parameter: (DIV_ALGORITHM), line:67
|vpiName:DIV_ALGORITHM
|INT:0
|vpiParameter:
\_parameter: (DIV_UNIT_WB_ID), line:192
|vpiName:DIV_UNIT_WB_ID
|INT:2
|vpiParameter:
\_parameter: (DTLB_DEPTH), line:152
|vpiName:DTLB_DEPTH
|INT:512
|vpiParameter:
\_parameter: (DTLB_WAYS), line:151
|vpiName:DTLB_WAYS
|INT:32
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (ENABLE_M_MODE), line:110
|vpiName:ENABLE_M_MODE
|INT:-2146435073
|vpiParameter:
\_parameter: (ENABLE_S_MODE), line:36
|vpiName:ENABLE_S_MODE
|INT:0
|vpiParameter:
\_parameter: (ENABLE_TRACE_INTERFACE), line:172
|vpiName:ENABLE_TRACE_INTERFACE
|INT:2
|vpiParameter:
\_parameter: (FETCH_BUFFER_DEPTH), line:168
|vpiName:FETCH_BUFFER_DEPTH
|INT:512
|vpiParameter:
\_parameter: (FPGA_VENDOR), line:110
|vpiName:FPGA_VENDOR
|INT:0
|vpiParameter:
\_parameter: (GC_UNIT_ID), line:196
|vpiName:GC_UNIT_ID
|INT:4
|vpiParameter:
\_parameter: (ICACHE_LINES), line:121
|vpiName:ICACHE_LINES
|INT:2
|vpiParameter:
\_parameter: (ICACHE_LINE_ADDR_W), line:123
|vpiName:ICACHE_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_LINE_W), line:124
|vpiName:ICACHE_LINE_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_SUB_LINE_ADDR_W), line:125
|vpiName:ICACHE_SUB_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_TAG_W), line:126
|vpiName:ICACHE_TAG_W
|INT:-2147483648
|vpiParameter:
\_parameter: (ICACHE_WAYS), line:122
|vpiName:ICACHE_WAYS
|INT:1
|vpiParameter:
\_parameter: (ITLB_DEPTH), line:146
|vpiName:ITLB_DEPTH
|INT:32
|vpiParameter:
\_parameter: (ITLB_WAYS), line:145
|vpiName:ITLB_WAYS
|INT:4
|vpiParameter:
\_parameter: (L1_CONNECTIONS), line:177
|vpiName:L1_CONNECTIONS
|INT:9
|vpiParameter:
\_parameter: (L1_DCACHE_ID), line:178
|vpiName:L1_DCACHE_ID
|INT:4
|vpiParameter:
\_parameter: (L1_DMMU_ID), line:179
|vpiName:L1_DMMU_ID
|INT:2
|vpiParameter:
\_parameter: (L1_ICACHE_ID), line:180
|vpiName:L1_ICACHE_ID
|INT:19
|vpiParameter:
\_parameter: (L1_IMMU_ID), line:181
|vpiName:L1_IMMU_ID
|INT:0
|vpiParameter:
\_parameter: (LINES), line:28
|vpiName:LINES
|INT:512
|vpiParameter:
\_parameter: (LS_UNIT_WB_ID), line:191
|vpiName:LS_UNIT_WB_ID
|INT:1
|vpiParameter:
\_parameter: (MAX_INFLIGHT_COUNT), line:167
|vpiName:MAX_INFLIGHT_COUNT
|INT:19
|vpiParameter:
\_parameter: (MEMORY_ADDR_H), line:103
|vpiName:MEMORY_ADDR_H
|INT:12
|vpiParameter:
\_parameter: (MEMORY_ADDR_L), line:102
|vpiName:MEMORY_ADDR_L
|INT:11
|vpiParameter:
\_parameter: (MEMORY_BIT_CHECK), line:104
|vpiName:MEMORY_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (MUL_UNIT_WB_ID), line:193
|vpiName:MUL_UNIT_WB_ID
|INT:512
|vpiParameter:
\_parameter: (NUM_UNITS), line:188
|vpiName:NUM_UNITS
|INT:2
|vpiParameter:
\_parameter: (NUM_WB_UNITS), line:186
|vpiName:NUM_WB_UNITS
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (RAS_DEPTH), line:161
|vpiName:RAS_DEPTH
|INT:2
|vpiParameter:
\_parameter: (RESET_VEC), line:39
|vpiName:RESET_VEC
|INT:-2147483648
|vpiParameter:
\_parameter: (SCRATCH_ADDR_H), line:99
|vpiName:SCRATCH_ADDR_H
|INT:9
|vpiParameter:
\_parameter: (SCRATCH_ADDR_L), line:98
|vpiName:SCRATCH_ADDR_L
|INT:8
|vpiParameter:
\_parameter: (SCRATCH_BIT_CHECK), line:100
|vpiName:SCRATCH_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (USE_AMO), line:70
|vpiName:USE_AMO
|INT:1
|vpiParameter:
\_parameter: (USE_BRANCH_PREDICTOR), line:158
|vpiName:USE_BRANCH_PREDICTOR
|INT:2
|vpiParameter:
\_parameter: (USE_BUS), line:88
|vpiName:USE_BUS
|INT:4
|vpiParameter:
\_parameter: (USE_DCACHE), line:92
|vpiName:USE_DCACHE
|INT:6
|vpiParameter:
\_parameter: (USE_DIV), line:49
|vpiName:USE_DIV
|INT:1
|vpiParameter:
\_parameter: (USE_DTAG_INVALIDATIONS), line:140
|vpiName:USE_DTAG_INVALIDATIONS
|INT:1879048191
|vpiParameter:
\_parameter: (USE_D_SCRATCH_MEM), line:79
|vpiName:USE_D_SCRATCH_MEM
|INT:3
|vpiParameter:
\_parameter: (USE_ICACHE), line:93
|vpiName:USE_ICACHE
|INT:7
|vpiParameter:
\_parameter: (USE_I_SCRATCH_MEM), line:78
|vpiName:USE_I_SCRATCH_MEM
|INT:2
|vpiParameter:
\_parameter: (USE_MUL), line:48
|vpiName:USE_MUL
|INT:1
|vpiParameter:
\_parameter: (WB_UNITS_WIDTH), line:187
|vpiName:WB_UNITS_WIDTH
|INT:32
|vpiParameter:
\_parameter: (WIDTH), line:27
|vpiName:WIDTH
|INT:32
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiParameter:
\_parameter: (ALU_UNIT_WB_ID), line:190
|vpiName:ALU_UNIT_WB_ID
|INT:32
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (BRANCH_PREDICTOR_WAYS), line:159
|vpiName:BRANCH_PREDICTOR_WAYS
|INT:9
|vpiParameter:
\_parameter: (BRANCH_TABLE_ENTRIES), line:160
|vpiName:BRANCH_TABLE_ENTRIES
|INT:4
|vpiParameter:
\_parameter: (BRANCH_UNIT_ID), line:195
|vpiName:BRANCH_UNIT_ID
|INT:8
|vpiParameter:
\_parameter: (BUS_ADDR_H), line:107
|vpiName:BUS_ADDR_H
|INT:1
|vpiParameter:
\_parameter: (BUS_ADDR_L), line:106
|vpiName:BUS_ADDR_L
|INT:0
|vpiParameter:
\_parameter: (BUS_BIT_CHECK), line:108
|vpiName:BUS_BIT_CHECK
|INT:1
|vpiParameter:
\_parameter: (BUS_TYPE), line:89
|vpiName:BUS_TYPE
|INT:5
|vpiParameter:
\_parameter: (COUNTER_W), line:42
|vpiName:COUNTER_W
|INT:33
|vpiParameter:
\_parameter: (CPU_ID), line:38
|vpiName:CPU_ID
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_ADDR_WIDTH), line:113
|vpiName:C_M_AXI_ADDR_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_DATA_WIDTH), line:114
|vpiName:C_M_AXI_DATA_WIDTH
|INT:1
|vpiParameter:
\_parameter: (DCACHE_LINES), line:133
|vpiName:DCACHE_LINES
|INT:-2146435073
|vpiParameter:
\_parameter: (DCACHE_LINE_ADDR_W), line:135
|vpiName:DCACHE_LINE_ADDR_W
|INT:1073741824
|vpiParameter:
\_parameter: (DCACHE_LINE_W), line:136
|vpiName:DCACHE_LINE_W
|INT:1342177279
|vpiParameter:
\_parameter: (DCACHE_SUB_LINE_ADDR_W), line:137
|vpiName:DCACHE_SUB_LINE_ADDR_W
|INT:4
|vpiParameter:
\_parameter: (DCACHE_TAG_W), line:138
|vpiName:DCACHE_TAG_W
|INT:1610612736
|vpiParameter:
\_parameter: (DCACHE_WAYS), line:134
|vpiName:DCACHE_WAYS
|INT:4
|vpiParameter:
\_parameter: (DIV_ALGORITHM), line:67
|vpiName:DIV_ALGORITHM
|INT:0
|vpiParameter:
\_parameter: (DIV_UNIT_WB_ID), line:192
|vpiName:DIV_UNIT_WB_ID
|INT:2
|vpiParameter:
\_parameter: (DTLB_DEPTH), line:152
|vpiName:DTLB_DEPTH
|INT:512
|vpiParameter:
\_parameter: (DTLB_WAYS), line:151
|vpiName:DTLB_WAYS
|INT:32
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (ENABLE_M_MODE), line:34
|vpiName:ENABLE_M_MODE
|INT:1
|vpiParameter:
\_parameter: (ENABLE_S_MODE), line:36
|vpiName:ENABLE_S_MODE
|INT:0
|vpiParameter:
\_parameter: (ENABLE_TRACE_INTERFACE), line:172
|vpiName:ENABLE_TRACE_INTERFACE
|INT:2
|vpiParameter:
\_parameter: (FETCH_BUFFER_DEPTH), line:168
|vpiName:FETCH_BUFFER_DEPTH
|INT:512
|vpiParameter:
\_parameter: (FPGA_VENDOR), line:27
|vpiName:FPGA_VENDOR
|STRING:"xilinx"
|vpiParameter:
\_parameter: (GC_UNIT_ID), line:196
|vpiName:GC_UNIT_ID
|INT:4
|vpiParameter:
\_parameter: (ICACHE_LINES), line:121
|vpiName:ICACHE_LINES
|INT:2
|vpiParameter:
\_parameter: (ICACHE_LINE_ADDR_W), line:123
|vpiName:ICACHE_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_LINE_W), line:124
|vpiName:ICACHE_LINE_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_SUB_LINE_ADDR_W), line:125
|vpiName:ICACHE_SUB_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_TAG_W), line:126
|vpiName:ICACHE_TAG_W
|INT:-2147483648
|vpiParameter:
\_parameter: (ICACHE_WAYS), line:122
|vpiName:ICACHE_WAYS
|INT:1
|vpiParameter:
\_parameter: (ITLB_DEPTH), line:146
|vpiName:ITLB_DEPTH
|INT:32
|vpiParameter:
\_parameter: (ITLB_WAYS), line:145
|vpiName:ITLB_WAYS
|INT:4
|vpiParameter:
\_parameter: (L1_CONNECTIONS), line:177
|vpiName:L1_CONNECTIONS
|INT:9
|vpiParameter:
\_parameter: (L1_DCACHE_ID), line:178
|vpiName:L1_DCACHE_ID
|INT:4
|vpiParameter:
\_parameter: (L1_DMMU_ID), line:179
|vpiName:L1_DMMU_ID
|INT:2
|vpiParameter:
\_parameter: (L1_ICACHE_ID), line:180
|vpiName:L1_ICACHE_ID
|INT:19
|vpiParameter:
\_parameter: (L1_IMMU_ID), line:181
|vpiName:L1_IMMU_ID
|INT:0
|vpiParameter:
\_parameter: (LS_UNIT_WB_ID), line:191
|vpiName:LS_UNIT_WB_ID
|INT:1
|vpiParameter:
\_parameter: (MAX_INFLIGHT_COUNT), line:167
|vpiName:MAX_INFLIGHT_COUNT
|INT:19
|vpiParameter:
\_parameter: (MEMORY_ADDR_H), line:103
|vpiName:MEMORY_ADDR_H
|INT:12
|vpiParameter:
\_parameter: (MEMORY_ADDR_L), line:102
|vpiName:MEMORY_ADDR_L
|INT:11
|vpiParameter:
\_parameter: (MEMORY_BIT_CHECK), line:104
|vpiName:MEMORY_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (MUL_UNIT_WB_ID), line:193
|vpiName:MUL_UNIT_WB_ID
|INT:512
|vpiParameter:
\_parameter: (NUM_UNITS), line:188
|vpiName:NUM_UNITS
|INT:2
|vpiParameter:
\_parameter: (NUM_WB_UNITS), line:186
|vpiName:NUM_WB_UNITS
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (RAS_DEPTH), line:161
|vpiName:RAS_DEPTH
|INT:2
|vpiParameter:
\_parameter: (RESET_VEC), line:39
|vpiName:RESET_VEC
|INT:-2147483648
|vpiParameter:
\_parameter: (SCRATCH_ADDR_H), line:99
|vpiName:SCRATCH_ADDR_H
|INT:9
|vpiParameter:
\_parameter: (SCRATCH_ADDR_L), line:98
|vpiName:SCRATCH_ADDR_L
|INT:8
|vpiParameter:
\_parameter: (SCRATCH_BIT_CHECK), line:100
|vpiName:SCRATCH_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (USE_AMO), line:70
|vpiName:USE_AMO
|INT:1
|vpiParameter:
\_parameter: (USE_BRANCH_PREDICTOR), line:158
|vpiName:USE_BRANCH_PREDICTOR
|INT:2
|vpiParameter:
\_parameter: (USE_BUS), line:88
|vpiName:USE_BUS
|INT:4
|vpiParameter:
\_parameter: (USE_DCACHE), line:92
|vpiName:USE_DCACHE
|INT:6
|vpiParameter:
\_parameter: (USE_DIV), line:49
|vpiName:USE_DIV
|INT:1
|vpiParameter:
\_parameter: (USE_DTAG_INVALIDATIONS), line:140
|vpiName:USE_DTAG_INVALIDATIONS
|INT:1879048191
|vpiParameter:
\_parameter: (USE_D_SCRATCH_MEM), line:79
|vpiName:USE_D_SCRATCH_MEM
|INT:3
|vpiParameter:
\_parameter: (USE_ICACHE), line:93
|vpiName:USE_ICACHE
|INT:7
|vpiParameter:
\_parameter: (USE_I_SCRATCH_MEM), line:78
|vpiName:USE_I_SCRATCH_MEM
|INT:2
|vpiParameter:
\_parameter: (USE_MUL), line:48
|vpiName:USE_MUL
|INT:1
|vpiParameter:
\_parameter: (WB_UNITS_WIDTH), line:187
|vpiName:WB_UNITS_WIDTH
|INT:32
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiParameter:
\_parameter: (i), line:107
|vpiName:i
|INT:2
|vpiGenScopeArray:
\_gen_scope_array: (dtag_bank_gen[3]), line:107, parent:dcache_tag_banks
|vpiName:dtag_bank_gen[3]
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.dcache_tag_banks.dtag_bank_gen[3]
|vpiGenScope:
\_gen_scope: , parent:dtag_bank_gen[3]
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.dcache_tag_banks.dtag_bank_gen[3]
|vpiContAssign:
\_cont_assign: , line:108
|vpiRhs:
\_operation: , line:108
|vpiOpType:29
|vpiOperand:
\_bit_select: (update_way), line:108
|vpiName:update_way
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.dcache_tag_banks.dtag_bank_gen[3].update_way
|vpiIndex:
\_ref_obj: (i), line:108
|vpiName:i
|vpiOperand:
\_operation: , line:108
|vpiOpType:28
|vpiOperand:
\_bit_select: (inv_hit_way), line:108
|vpiName:inv_hit_way
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.dcache_tag_banks.dtag_bank_gen[3].inv_hit_way
|vpiIndex:
\_ref_obj: (i), line:108
|vpiName:i
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.dcache_tag_banks.dtag_bank_gen[3].i
|vpiOperand:
\_ref_obj: (extern_inv_complete), line:108
|vpiName:extern_inv_complete
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.dcache_tag_banks.dtag_bank_gen[3].extern_inv_complete
|vpiLhs:
\_bit_select: (update_tag_way), line:108
|vpiName:update_tag_way
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.dcache_tag_banks.dtag_bank_gen[3].update_tag_way
|vpiIndex:
\_ref_obj: (i), line:108
|vpiName:i
|vpiContAssign:
\_cont_assign: , line:120
|vpiRhs:
\_operation: , line:120
|vpiOpType:14
|vpiOperand:
\_ref_obj: (inv_hit_comparison_tagline), line:120
|vpiName:inv_hit_comparison_tagline
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.dcache_tag_banks.dtag_bank_gen[3].inv_hit_comparison_tagline
|vpiOperand:
\_bit_select: (inv_tag_line), line:120
|vpiName:inv_tag_line
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.dcache_tag_banks.dtag_bank_gen[3].inv_tag_line
|vpiIndex:
\_ref_obj: (i), line:120
|vpiName:i
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.dcache_tag_banks.dtag_bank_gen[3].i
|vpiLhs:
\_bit_select: (inv_hit_way), line:120
|vpiName:inv_hit_way
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.dcache_tag_banks.dtag_bank_gen[3].inv_hit_way
|vpiIndex:
\_ref_obj: (i), line:120
|vpiName:i
|vpiContAssign:
\_cont_assign: , line:121
|vpiRhs:
\_operation: , line:121
|vpiOpType:14
|vpiOperand:
\_ref_obj: (stage2_hit_comparison_tagline), line:121
|vpiName:stage2_hit_comparison_tagline
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.dcache_tag_banks.dtag_bank_gen[3].stage2_hit_comparison_tagline
|vpiOperand:
\_bit_select: (tag_line), line:121
|vpiName:tag_line
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.dcache_tag_banks.dtag_bank_gen[3].tag_line
|vpiIndex:
\_ref_obj: (i), line:121
|vpiName:i
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.dcache_tag_banks.dtag_bank_gen[3].i
|vpiLhs:
\_bit_select: (tag_hit_way), line:121
|vpiName:tag_hit_way
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.dcache_tag_banks.dtag_bank_gen[3].tag_hit_way
|vpiIndex:
\_ref_obj: (i), line:121
|vpiName:i
|vpiModule:
\_module: work@tag_bank (dtag_bank), file:third_party/cores/taiga/core/dtag_banks.sv, line:110
|vpiDefName:work@tag_bank
|vpiName:dtag_bank
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.dcache_tag_banks.dtag_bank_gen[3].dtag_bank
|vpiPort:
\_port: (clk), line:32, parent:dtag_bank
|vpiName:clk
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (clk), line:110
|vpiName:clk
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (clk), line:32, parent:dtag_bank
|vpiName:clk
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.dcache_tag_banks.dtag_bank_gen[3].dtag_bank.clk
|vpiNetType:36
|vpiPort:
\_port: (rst), line:33, parent:dtag_bank
|vpiName:rst
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (rst), line:110
|vpiName:rst
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (rst), line:33, parent:dtag_bank
|vpiName:rst
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.dcache_tag_banks.dtag_bank_gen[3].dtag_bank.rst
|vpiNetType:36
|vpiPort:
\_port: (addr_a), line:35, parent:dtag_bank
|vpiName:addr_a
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (addr_a), line:110
|vpiName:addr_a
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (addr_a), line:35, parent:dtag_bank
|vpiName:addr_a
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.dcache_tag_banks.dtag_bank_gen[3].dtag_bank.addr_a
|vpiNetType:36
|vpiRange:
\_range: , line:35
|vpiLeftRange:
\_constant: , line:35
|vpiConstType:7
|vpiDecompile:8
|vpiSize:32
|INT:8
|vpiRightRange:
\_constant: , line:35
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiPort:
\_port: (addr_b), line:36, parent:dtag_bank
|vpiName:addr_b
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (addr_b), line:110
|vpiName:addr_b
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (addr_b), line:36, parent:dtag_bank
|vpiName:addr_b
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.dcache_tag_banks.dtag_bank_gen[3].dtag_bank.addr_b
|vpiNetType:36
|vpiRange:
\_range: , line:36
|vpiLeftRange:
\_constant: , line:36
|vpiConstType:7
|vpiDecompile:8
|vpiSize:32
|INT:8
|vpiRightRange:
\_constant: , line:36
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiPort:
\_port: (en_a), line:37, parent:dtag_bank
|vpiName:en_a
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (en_a), line:110
|vpiName:en_a
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (en_a), line:37, parent:dtag_bank
|vpiName:en_a
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.dcache_tag_banks.dtag_bank_gen[3].dtag_bank.en_a
|vpiNetType:36
|vpiPort:
\_port: (en_b), line:38, parent:dtag_bank
|vpiName:en_b
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (en_b), line:110
|vpiName:en_b
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (en_b), line:38, parent:dtag_bank
|vpiName:en_b
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.dcache_tag_banks.dtag_bank_gen[3].dtag_bank.en_b
|vpiNetType:36
|vpiPort:
\_port: (wen_a), line:39, parent:dtag_bank
|vpiName:wen_a
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (wen_a), line:110
|vpiName:wen_a
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (wen_a), line:39, parent:dtag_bank
|vpiName:wen_a
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.dcache_tag_banks.dtag_bank_gen[3].dtag_bank.wen_a
|vpiNetType:36
|vpiPort:
\_port: (wen_b), line:40, parent:dtag_bank
|vpiName:wen_b
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (wen_b), line:110
|vpiName:wen_b
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (wen_b), line:40, parent:dtag_bank
|vpiName:wen_b
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.dcache_tag_banks.dtag_bank_gen[3].dtag_bank.wen_b
|vpiNetType:36
|vpiPort:
\_port: (data_in_a), line:41, parent:dtag_bank
|vpiName:data_in_a
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (data_in_a), line:110
|vpiName:data_in_a
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (data_in_a), line:41, parent:dtag_bank
|vpiName:data_in_a
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.dcache_tag_banks.dtag_bank_gen[3].dtag_bank.data_in_a
|vpiNetType:36
|vpiRange:
\_range: , line:41
|vpiLeftRange:
\_constant: , line:41
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:41
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiPort:
\_port: (data_in_b), line:42, parent:dtag_bank
|vpiName:data_in_b
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (data_in_b), line:110
|vpiName:data_in_b
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (data_in_b), line:42, parent:dtag_bank
|vpiName:data_in_b
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.dcache_tag_banks.dtag_bank_gen[3].dtag_bank.data_in_b
|vpiNetType:36
|vpiRange:
\_range: , line:42
|vpiLeftRange:
\_constant: , line:42
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:42
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiPort:
\_port: (data_out_a), line:43, parent:dtag_bank
|vpiName:data_out_a
|vpiDirection:2
|vpiHighConn:
\_ref_obj: (data_out_a), line:110
|vpiName:data_out_a
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (data_out_a), line:43, parent:dtag_bank
|vpiName:data_out_a
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.dcache_tag_banks.dtag_bank_gen[3].dtag_bank.data_out_a
|vpiNetType:36
|vpiRange:
\_range: , line:43
|vpiLeftRange:
\_constant: , line:43
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:43
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiPort:
\_port: (data_out_b), line:44, parent:dtag_bank
|vpiName:data_out_b
|vpiDirection:2
|vpiHighConn:
\_ref_obj: (data_out_b), line:110
|vpiName:data_out_b
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (data_out_b), line:44, parent:dtag_bank
|vpiName:data_out_b
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.dcache_tag_banks.dtag_bank_gen[3].dtag_bank.data_out_b
|vpiNetType:36
|vpiRange:
\_range: , line:44
|vpiLeftRange:
\_constant: , line:44
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:44
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (clk), line:32, parent:dtag_bank
|vpiNet:
\_logic_net: (rst), line:33, parent:dtag_bank
|vpiNet:
\_logic_net: (addr_a), line:35, parent:dtag_bank
|vpiNet:
\_logic_net: (addr_b), line:36, parent:dtag_bank
|vpiNet:
\_logic_net: (en_a), line:37, parent:dtag_bank
|vpiNet:
\_logic_net: (en_b), line:38, parent:dtag_bank
|vpiNet:
\_logic_net: (wen_a), line:39, parent:dtag_bank
|vpiNet:
\_logic_net: (wen_b), line:40, parent:dtag_bank
|vpiNet:
\_logic_net: (data_in_a), line:41, parent:dtag_bank
|vpiNet:
\_logic_net: (data_in_b), line:42, parent:dtag_bank
|vpiNet:
\_logic_net: (data_out_a), line:43, parent:dtag_bank
|vpiNet:
\_logic_net: (data_out_b), line:44, parent:dtag_bank
|vpiNet:
\_logic_net: (i), line:49, parent:dtag_bank
|vpiName:i
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.dcache_tag_banks.dtag_bank_gen[3].dtag_bank.i
|vpiArrayNet:
\_array_net: (tag_entry), line:47, parent:dtag_bank
|vpiName:tag_entry
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.dcache_tag_banks.dtag_bank_gen[3].dtag_bank.tag_entry
|vpiSize:512
|vpiNet:
\_logic_net: , parent:tag_entry
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.dcache_tag_banks.dtag_bank_gen[3].dtag_bank.tag_entry
|vpiNetType:36
|vpiRange:
\_range: , line:47
|vpiLeftRange:
\_constant: , line:47
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:47
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiRange:
\_range: , line:47
|vpiLeftRange:
\_constant: , line:47
|vpiConstType:7
|vpiDecompile:511
|vpiSize:32
|INT:511
|vpiRightRange:
\_constant: , line:47
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiParameter:
\_parameter: (ALU_UNIT_WB_ID), line:190
|vpiName:ALU_UNIT_WB_ID
|INT:32
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (BRANCH_PREDICTOR_WAYS), line:159
|vpiName:BRANCH_PREDICTOR_WAYS
|INT:9
|vpiParameter:
\_parameter: (BRANCH_TABLE_ENTRIES), line:160
|vpiName:BRANCH_TABLE_ENTRIES
|INT:4
|vpiParameter:
\_parameter: (BRANCH_UNIT_ID), line:195
|vpiName:BRANCH_UNIT_ID
|INT:8
|vpiParameter:
\_parameter: (BUS_ADDR_H), line:107
|vpiName:BUS_ADDR_H
|INT:1
|vpiParameter:
\_parameter: (BUS_ADDR_L), line:106
|vpiName:BUS_ADDR_L
|INT:0
|vpiParameter:
\_parameter: (BUS_BIT_CHECK), line:108
|vpiName:BUS_BIT_CHECK
|INT:1
|vpiParameter:
\_parameter: (BUS_TYPE), line:89
|vpiName:BUS_TYPE
|INT:5
|vpiParameter:
\_parameter: (COUNTER_W), line:42
|vpiName:COUNTER_W
|INT:33
|vpiParameter:
\_parameter: (CPU_ID), line:38
|vpiName:CPU_ID
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_ADDR_WIDTH), line:113
|vpiName:C_M_AXI_ADDR_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_DATA_WIDTH), line:114
|vpiName:C_M_AXI_DATA_WIDTH
|INT:1
|vpiParameter:
\_parameter: (DCACHE_LINES), line:133
|vpiName:DCACHE_LINES
|INT:-2146435073
|vpiParameter:
\_parameter: (DCACHE_LINE_ADDR_W), line:135
|vpiName:DCACHE_LINE_ADDR_W
|INT:1073741824
|vpiParameter:
\_parameter: (DCACHE_LINE_W), line:136
|vpiName:DCACHE_LINE_W
|INT:1342177279
|vpiParameter:
\_parameter: (DCACHE_SUB_LINE_ADDR_W), line:137
|vpiName:DCACHE_SUB_LINE_ADDR_W
|INT:4
|vpiParameter:
\_parameter: (DCACHE_TAG_W), line:138
|vpiName:DCACHE_TAG_W
|INT:1610612736
|vpiParameter:
\_parameter: (DCACHE_WAYS), line:134
|vpiName:DCACHE_WAYS
|INT:4
|vpiParameter:
\_parameter: (DIV_ALGORITHM), line:67
|vpiName:DIV_ALGORITHM
|INT:0
|vpiParameter:
\_parameter: (DIV_UNIT_WB_ID), line:192
|vpiName:DIV_UNIT_WB_ID
|INT:2
|vpiParameter:
\_parameter: (DTLB_DEPTH), line:152
|vpiName:DTLB_DEPTH
|INT:512
|vpiParameter:
\_parameter: (DTLB_WAYS), line:151
|vpiName:DTLB_WAYS
|INT:32
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (ENABLE_M_MODE), line:110
|vpiName:ENABLE_M_MODE
|INT:-2146435073
|vpiParameter:
\_parameter: (ENABLE_S_MODE), line:36
|vpiName:ENABLE_S_MODE
|INT:0
|vpiParameter:
\_parameter: (ENABLE_TRACE_INTERFACE), line:172
|vpiName:ENABLE_TRACE_INTERFACE
|INT:2
|vpiParameter:
\_parameter: (FETCH_BUFFER_DEPTH), line:168
|vpiName:FETCH_BUFFER_DEPTH
|INT:512
|vpiParameter:
\_parameter: (FPGA_VENDOR), line:110
|vpiName:FPGA_VENDOR
|INT:0
|vpiParameter:
\_parameter: (GC_UNIT_ID), line:196
|vpiName:GC_UNIT_ID
|INT:4
|vpiParameter:
\_parameter: (ICACHE_LINES), line:121
|vpiName:ICACHE_LINES
|INT:2
|vpiParameter:
\_parameter: (ICACHE_LINE_ADDR_W), line:123
|vpiName:ICACHE_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_LINE_W), line:124
|vpiName:ICACHE_LINE_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_SUB_LINE_ADDR_W), line:125
|vpiName:ICACHE_SUB_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_TAG_W), line:126
|vpiName:ICACHE_TAG_W
|INT:-2147483648
|vpiParameter:
\_parameter: (ICACHE_WAYS), line:122
|vpiName:ICACHE_WAYS
|INT:1
|vpiParameter:
\_parameter: (ITLB_DEPTH), line:146
|vpiName:ITLB_DEPTH
|INT:32
|vpiParameter:
\_parameter: (ITLB_WAYS), line:145
|vpiName:ITLB_WAYS
|INT:4
|vpiParameter:
\_parameter: (L1_CONNECTIONS), line:177
|vpiName:L1_CONNECTIONS
|INT:9
|vpiParameter:
\_parameter: (L1_DCACHE_ID), line:178
|vpiName:L1_DCACHE_ID
|INT:4
|vpiParameter:
\_parameter: (L1_DMMU_ID), line:179
|vpiName:L1_DMMU_ID
|INT:2
|vpiParameter:
\_parameter: (L1_ICACHE_ID), line:180
|vpiName:L1_ICACHE_ID
|INT:19
|vpiParameter:
\_parameter: (L1_IMMU_ID), line:181
|vpiName:L1_IMMU_ID
|INT:0
|vpiParameter:
\_parameter: (LINES), line:28
|vpiName:LINES
|INT:512
|vpiParameter:
\_parameter: (LS_UNIT_WB_ID), line:191
|vpiName:LS_UNIT_WB_ID
|INT:1
|vpiParameter:
\_parameter: (MAX_INFLIGHT_COUNT), line:167
|vpiName:MAX_INFLIGHT_COUNT
|INT:19
|vpiParameter:
\_parameter: (MEMORY_ADDR_H), line:103
|vpiName:MEMORY_ADDR_H
|INT:12
|vpiParameter:
\_parameter: (MEMORY_ADDR_L), line:102
|vpiName:MEMORY_ADDR_L
|INT:11
|vpiParameter:
\_parameter: (MEMORY_BIT_CHECK), line:104
|vpiName:MEMORY_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (MUL_UNIT_WB_ID), line:193
|vpiName:MUL_UNIT_WB_ID
|INT:512
|vpiParameter:
\_parameter: (NUM_UNITS), line:188
|vpiName:NUM_UNITS
|INT:2
|vpiParameter:
\_parameter: (NUM_WB_UNITS), line:186
|vpiName:NUM_WB_UNITS
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (RAS_DEPTH), line:161
|vpiName:RAS_DEPTH
|INT:2
|vpiParameter:
\_parameter: (RESET_VEC), line:39
|vpiName:RESET_VEC
|INT:-2147483648
|vpiParameter:
\_parameter: (SCRATCH_ADDR_H), line:99
|vpiName:SCRATCH_ADDR_H
|INT:9
|vpiParameter:
\_parameter: (SCRATCH_ADDR_L), line:98
|vpiName:SCRATCH_ADDR_L
|INT:8
|vpiParameter:
\_parameter: (SCRATCH_BIT_CHECK), line:100
|vpiName:SCRATCH_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (USE_AMO), line:70
|vpiName:USE_AMO
|INT:1
|vpiParameter:
\_parameter: (USE_BRANCH_PREDICTOR), line:158
|vpiName:USE_BRANCH_PREDICTOR
|INT:2
|vpiParameter:
\_parameter: (USE_BUS), line:88
|vpiName:USE_BUS
|INT:4
|vpiParameter:
\_parameter: (USE_DCACHE), line:92
|vpiName:USE_DCACHE
|INT:6
|vpiParameter:
\_parameter: (USE_DIV), line:49
|vpiName:USE_DIV
|INT:1
|vpiParameter:
\_parameter: (USE_DTAG_INVALIDATIONS), line:140
|vpiName:USE_DTAG_INVALIDATIONS
|INT:1879048191
|vpiParameter:
\_parameter: (USE_D_SCRATCH_MEM), line:79
|vpiName:USE_D_SCRATCH_MEM
|INT:3
|vpiParameter:
\_parameter: (USE_ICACHE), line:93
|vpiName:USE_ICACHE
|INT:7
|vpiParameter:
\_parameter: (USE_I_SCRATCH_MEM), line:78
|vpiName:USE_I_SCRATCH_MEM
|INT:2
|vpiParameter:
\_parameter: (USE_MUL), line:48
|vpiName:USE_MUL
|INT:1
|vpiParameter:
\_parameter: (WB_UNITS_WIDTH), line:187
|vpiName:WB_UNITS_WIDTH
|INT:32
|vpiParameter:
\_parameter: (WIDTH), line:27
|vpiName:WIDTH
|INT:32
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiParameter:
\_parameter: (ALU_UNIT_WB_ID), line:190
|vpiName:ALU_UNIT_WB_ID
|INT:32
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (BRANCH_PREDICTOR_WAYS), line:159
|vpiName:BRANCH_PREDICTOR_WAYS
|INT:9
|vpiParameter:
\_parameter: (BRANCH_TABLE_ENTRIES), line:160
|vpiName:BRANCH_TABLE_ENTRIES
|INT:4
|vpiParameter:
\_parameter: (BRANCH_UNIT_ID), line:195
|vpiName:BRANCH_UNIT_ID
|INT:8
|vpiParameter:
\_parameter: (BUS_ADDR_H), line:107
|vpiName:BUS_ADDR_H
|INT:1
|vpiParameter:
\_parameter: (BUS_ADDR_L), line:106
|vpiName:BUS_ADDR_L
|INT:0
|vpiParameter:
\_parameter: (BUS_BIT_CHECK), line:108
|vpiName:BUS_BIT_CHECK
|INT:1
|vpiParameter:
\_parameter: (BUS_TYPE), line:89
|vpiName:BUS_TYPE
|INT:5
|vpiParameter:
\_parameter: (COUNTER_W), line:42
|vpiName:COUNTER_W
|INT:33
|vpiParameter:
\_parameter: (CPU_ID), line:38
|vpiName:CPU_ID
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_ADDR_WIDTH), line:113
|vpiName:C_M_AXI_ADDR_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_DATA_WIDTH), line:114
|vpiName:C_M_AXI_DATA_WIDTH
|INT:1
|vpiParameter:
\_parameter: (DCACHE_LINES), line:133
|vpiName:DCACHE_LINES
|INT:-2146435073
|vpiParameter:
\_parameter: (DCACHE_LINE_ADDR_W), line:135
|vpiName:DCACHE_LINE_ADDR_W
|INT:1073741824
|vpiParameter:
\_parameter: (DCACHE_LINE_W), line:136
|vpiName:DCACHE_LINE_W
|INT:1342177279
|vpiParameter:
\_parameter: (DCACHE_SUB_LINE_ADDR_W), line:137
|vpiName:DCACHE_SUB_LINE_ADDR_W
|INT:4
|vpiParameter:
\_parameter: (DCACHE_TAG_W), line:138
|vpiName:DCACHE_TAG_W
|INT:1610612736
|vpiParameter:
\_parameter: (DCACHE_WAYS), line:134
|vpiName:DCACHE_WAYS
|INT:4
|vpiParameter:
\_parameter: (DIV_ALGORITHM), line:67
|vpiName:DIV_ALGORITHM
|INT:0
|vpiParameter:
\_parameter: (DIV_UNIT_WB_ID), line:192
|vpiName:DIV_UNIT_WB_ID
|INT:2
|vpiParameter:
\_parameter: (DTLB_DEPTH), line:152
|vpiName:DTLB_DEPTH
|INT:512
|vpiParameter:
\_parameter: (DTLB_WAYS), line:151
|vpiName:DTLB_WAYS
|INT:32
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (ENABLE_M_MODE), line:34
|vpiName:ENABLE_M_MODE
|INT:1
|vpiParameter:
\_parameter: (ENABLE_S_MODE), line:36
|vpiName:ENABLE_S_MODE
|INT:0
|vpiParameter:
\_parameter: (ENABLE_TRACE_INTERFACE), line:172
|vpiName:ENABLE_TRACE_INTERFACE
|INT:2
|vpiParameter:
\_parameter: (FETCH_BUFFER_DEPTH), line:168
|vpiName:FETCH_BUFFER_DEPTH
|INT:512
|vpiParameter:
\_parameter: (FPGA_VENDOR), line:27
|vpiName:FPGA_VENDOR
|STRING:"xilinx"
|vpiParameter:
\_parameter: (GC_UNIT_ID), line:196
|vpiName:GC_UNIT_ID
|INT:4
|vpiParameter:
\_parameter: (ICACHE_LINES), line:121
|vpiName:ICACHE_LINES
|INT:2
|vpiParameter:
\_parameter: (ICACHE_LINE_ADDR_W), line:123
|vpiName:ICACHE_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_LINE_W), line:124
|vpiName:ICACHE_LINE_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_SUB_LINE_ADDR_W), line:125
|vpiName:ICACHE_SUB_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_TAG_W), line:126
|vpiName:ICACHE_TAG_W
|INT:-2147483648
|vpiParameter:
\_parameter: (ICACHE_WAYS), line:122
|vpiName:ICACHE_WAYS
|INT:1
|vpiParameter:
\_parameter: (ITLB_DEPTH), line:146
|vpiName:ITLB_DEPTH
|INT:32
|vpiParameter:
\_parameter: (ITLB_WAYS), line:145
|vpiName:ITLB_WAYS
|INT:4
|vpiParameter:
\_parameter: (L1_CONNECTIONS), line:177
|vpiName:L1_CONNECTIONS
|INT:9
|vpiParameter:
\_parameter: (L1_DCACHE_ID), line:178
|vpiName:L1_DCACHE_ID
|INT:4
|vpiParameter:
\_parameter: (L1_DMMU_ID), line:179
|vpiName:L1_DMMU_ID
|INT:2
|vpiParameter:
\_parameter: (L1_ICACHE_ID), line:180
|vpiName:L1_ICACHE_ID
|INT:19
|vpiParameter:
\_parameter: (L1_IMMU_ID), line:181
|vpiName:L1_IMMU_ID
|INT:0
|vpiParameter:
\_parameter: (LS_UNIT_WB_ID), line:191
|vpiName:LS_UNIT_WB_ID
|INT:1
|vpiParameter:
\_parameter: (MAX_INFLIGHT_COUNT), line:167
|vpiName:MAX_INFLIGHT_COUNT
|INT:19
|vpiParameter:
\_parameter: (MEMORY_ADDR_H), line:103
|vpiName:MEMORY_ADDR_H
|INT:12
|vpiParameter:
\_parameter: (MEMORY_ADDR_L), line:102
|vpiName:MEMORY_ADDR_L
|INT:11
|vpiParameter:
\_parameter: (MEMORY_BIT_CHECK), line:104
|vpiName:MEMORY_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (MUL_UNIT_WB_ID), line:193
|vpiName:MUL_UNIT_WB_ID
|INT:512
|vpiParameter:
\_parameter: (NUM_UNITS), line:188
|vpiName:NUM_UNITS
|INT:2
|vpiParameter:
\_parameter: (NUM_WB_UNITS), line:186
|vpiName:NUM_WB_UNITS
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (RAS_DEPTH), line:161
|vpiName:RAS_DEPTH
|INT:2
|vpiParameter:
\_parameter: (RESET_VEC), line:39
|vpiName:RESET_VEC
|INT:-2147483648
|vpiParameter:
\_parameter: (SCRATCH_ADDR_H), line:99
|vpiName:SCRATCH_ADDR_H
|INT:9
|vpiParameter:
\_parameter: (SCRATCH_ADDR_L), line:98
|vpiName:SCRATCH_ADDR_L
|INT:8
|vpiParameter:
\_parameter: (SCRATCH_BIT_CHECK), line:100
|vpiName:SCRATCH_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (USE_AMO), line:70
|vpiName:USE_AMO
|INT:1
|vpiParameter:
\_parameter: (USE_BRANCH_PREDICTOR), line:158
|vpiName:USE_BRANCH_PREDICTOR
|INT:2
|vpiParameter:
\_parameter: (USE_BUS), line:88
|vpiName:USE_BUS
|INT:4
|vpiParameter:
\_parameter: (USE_DCACHE), line:92
|vpiName:USE_DCACHE
|INT:6
|vpiParameter:
\_parameter: (USE_DIV), line:49
|vpiName:USE_DIV
|INT:1
|vpiParameter:
\_parameter: (USE_DTAG_INVALIDATIONS), line:140
|vpiName:USE_DTAG_INVALIDATIONS
|INT:1879048191
|vpiParameter:
\_parameter: (USE_D_SCRATCH_MEM), line:79
|vpiName:USE_D_SCRATCH_MEM
|INT:3
|vpiParameter:
\_parameter: (USE_ICACHE), line:93
|vpiName:USE_ICACHE
|INT:7
|vpiParameter:
\_parameter: (USE_I_SCRATCH_MEM), line:78
|vpiName:USE_I_SCRATCH_MEM
|INT:2
|vpiParameter:
\_parameter: (USE_MUL), line:48
|vpiName:USE_MUL
|INT:1
|vpiParameter:
\_parameter: (WB_UNITS_WIDTH), line:187
|vpiName:WB_UNITS_WIDTH
|INT:32
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiParameter:
\_parameter: (i), line:107
|vpiName:i
|INT:3
|vpiNet:
\_logic_net: (clk), line:27, parent:dcache_tag_banks
|vpiNet:
\_logic_net: (rst), line:28, parent:dcache_tag_banks
|vpiNet:
\_logic_net: (stage1_addr), line:30, parent:dcache_tag_banks
|vpiNet:
\_logic_net: (stage2_addr), line:31, parent:dcache_tag_banks
|vpiNet:
\_logic_net: (inv_addr), line:32, parent:dcache_tag_banks
|vpiNet:
\_logic_net: (update_way), line:34, parent:dcache_tag_banks
|vpiNet:
\_logic_net: (update), line:35, parent:dcache_tag_banks
|vpiNet:
\_logic_net: (stage1_adv), line:37, parent:dcache_tag_banks
|vpiNet:
\_logic_net: (stage1_inv), line:38, parent:dcache_tag_banks
|vpiNet:
\_logic_net: (extern_inv), line:40, parent:dcache_tag_banks
|vpiNet:
\_logic_net: (extern_inv_complete), line:41, parent:dcache_tag_banks
|vpiNet:
\_logic_net: (tag_hit), line:43, parent:dcache_tag_banks
|vpiNet:
\_logic_net: (tag_hit_way), line:44, parent:dcache_tag_banks
|vpiNet:
\_logic_net: (miss_or_extern_invalidate), line:65, parent:dcache_tag_banks
|vpiName:miss_or_extern_invalidate
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.dcache_tag_banks.miss_or_extern_invalidate
|vpiNetType:36
|vpiNet:
\_logic_net: (update_tag_way), line:66, parent:dcache_tag_banks
|vpiName:update_tag_way
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.dcache_tag_banks.update_tag_way
|vpiNetType:36
|vpiRange:
\_range: , line:66
|vpiLeftRange:
\_constant: , line:66
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiRightRange:
\_constant: , line:66
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (inv_tags_accessed), line:68, parent:dcache_tag_banks
|vpiName:inv_tags_accessed
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.dcache_tag_banks.inv_tags_accessed
|vpiNetType:36
|vpiNet:
\_logic_net: (inv_hit_way), line:70, parent:dcache_tag_banks
|vpiName:inv_hit_way
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.dcache_tag_banks.inv_hit_way
|vpiNetType:36
|vpiRange:
\_range: , line:70
|vpiLeftRange:
\_constant: , line:70
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiRightRange:
\_constant: , line:70
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (inv_hit_way_r), line:71, parent:dcache_tag_banks
|vpiName:inv_hit_way_r
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.dcache_tag_banks.inv_hit_way_r
|vpiNetType:36
|vpiRange:
\_range: , line:71
|vpiLeftRange:
\_constant: , line:71
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiRightRange:
\_constant: , line:71
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (update_port_addr), line:73, parent:dcache_tag_banks
|vpiName:update_port_addr
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.dcache_tag_banks.update_port_addr
|vpiNetType:36
|vpiRange:
\_range: , line:73
|vpiLeftRange:
\_constant: , line:73
|vpiConstType:7
|vpiDecompile:1073741823
|vpiSize:32
|INT:1073741823
|vpiRightRange:
\_constant: , line:73
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiInstance:
\_module: work@dcache (data_cache), file:third_party/cores/taiga/core/load_store_unit.sv, line:312
|vpiVariables:
\_array_var: (tag_line), parent:dcache_tag_banks
|vpiArrayType:1
|vpiName:tag_line
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.dcache_tag_banks.tag_line
|vpiRandType:1
|vpiVisibility:1
|vpiSize:4
|vpiReg:
\_struct_var: , line:60, parent:tag_line
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.dcache_tag_banks.tag_line
|vpiTypespec:
\_struct_typespec: (dtag_entry_t), line:47
|vpiRange:
\_range: , line:60
|vpiLeftRange:
\_constant: , line:60
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiRightRange:
\_constant: , line:60
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiVariables:
\_array_var: (inv_tag_line), parent:dcache_tag_banks
|vpiArrayType:1
|vpiName:inv_tag_line
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.dcache_tag_banks.inv_tag_line
|vpiRandType:1
|vpiVisibility:1
|vpiSize:4
|vpiReg:
\_struct_var: , line:61, parent:inv_tag_line
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.dcache_tag_banks.inv_tag_line
|vpiTypespec:
\_struct_typespec: (dtag_entry_t), line:47
|vpiRange:
\_range: , line:61
|vpiLeftRange:
\_constant: , line:61
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiRightRange:
\_constant: , line:61
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiVariables:
\_struct_var: (new_tagline), line:63, parent:dcache_tag_banks
|vpiName:new_tagline
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.dcache_tag_banks.new_tagline
|vpiTypespec:
\_struct_typespec: (dtag_entry_t), line:47
|vpiVariables:
\_struct_var: (stage2_hit_comparison_tagline), line:99, parent:dcache_tag_banks
|vpiName:stage2_hit_comparison_tagline
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.dcache_tag_banks.stage2_hit_comparison_tagline
|vpiTypespec:
\_struct_typespec: (dtag_entry_t), line:47
|vpiVariables:
\_struct_var: (inv_hit_comparison_tagline), line:100, parent:dcache_tag_banks
|vpiName:inv_hit_comparison_tagline
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.dcache_tag_banks.inv_hit_comparison_tagline
|vpiTypespec:
\_struct_typespec: (dtag_entry_t), line:47
|vpiParameter:
\_parameter: (ALU_UNIT_WB_ID), line:190
|vpiName:ALU_UNIT_WB_ID
|INT:32
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (BRANCH_PREDICTOR_WAYS), line:159
|vpiName:BRANCH_PREDICTOR_WAYS
|INT:9
|vpiParameter:
\_parameter: (BRANCH_TABLE_ENTRIES), line:160
|vpiName:BRANCH_TABLE_ENTRIES
|INT:4
|vpiParameter:
\_parameter: (BRANCH_UNIT_ID), line:195
|vpiName:BRANCH_UNIT_ID
|INT:8
|vpiParameter:
\_parameter: (BUS_ADDR_H), line:107
|vpiName:BUS_ADDR_H
|INT:1
|vpiParameter:
\_parameter: (BUS_ADDR_L), line:106
|vpiName:BUS_ADDR_L
|INT:0
|vpiParameter:
\_parameter: (BUS_BIT_CHECK), line:108
|vpiName:BUS_BIT_CHECK
|INT:1
|vpiParameter:
\_parameter: (BUS_TYPE), line:89
|vpiName:BUS_TYPE
|INT:5
|vpiParameter:
\_parameter: (COUNTER_W), line:42
|vpiName:COUNTER_W
|INT:33
|vpiParameter:
\_parameter: (CPU_ID), line:38
|vpiName:CPU_ID
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_ADDR_WIDTH), line:113
|vpiName:C_M_AXI_ADDR_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_DATA_WIDTH), line:114
|vpiName:C_M_AXI_DATA_WIDTH
|INT:1
|vpiParameter:
\_parameter: (DCACHE_LINES), line:133
|vpiName:DCACHE_LINES
|INT:-2146435073
|vpiParameter:
\_parameter: (DCACHE_LINE_ADDR_W), line:135
|vpiName:DCACHE_LINE_ADDR_W
|INT:1073741824
|vpiParameter:
\_parameter: (DCACHE_LINE_W), line:136
|vpiName:DCACHE_LINE_W
|INT:1342177279
|vpiParameter:
\_parameter: (DCACHE_SUB_LINE_ADDR_W), line:137
|vpiName:DCACHE_SUB_LINE_ADDR_W
|INT:4
|vpiParameter:
\_parameter: (DCACHE_TAG_W), line:138
|vpiName:DCACHE_TAG_W
|INT:1610612736
|vpiParameter:
\_parameter: (DCACHE_WAYS), line:134
|vpiName:DCACHE_WAYS
|INT:4
|vpiParameter:
\_parameter: (DIV_ALGORITHM), line:67
|vpiName:DIV_ALGORITHM
|INT:0
|vpiParameter:
\_parameter: (DIV_UNIT_WB_ID), line:192
|vpiName:DIV_UNIT_WB_ID
|INT:2
|vpiParameter:
\_parameter: (DTLB_DEPTH), line:152
|vpiName:DTLB_DEPTH
|INT:512
|vpiParameter:
\_parameter: (DTLB_WAYS), line:151
|vpiName:DTLB_WAYS
|INT:32
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (ENABLE_M_MODE), line:34
|vpiName:ENABLE_M_MODE
|INT:1
|vpiParameter:
\_parameter: (ENABLE_S_MODE), line:36
|vpiName:ENABLE_S_MODE
|INT:0
|vpiParameter:
\_parameter: (ENABLE_TRACE_INTERFACE), line:172
|vpiName:ENABLE_TRACE_INTERFACE
|INT:2
|vpiParameter:
\_parameter: (FETCH_BUFFER_DEPTH), line:168
|vpiName:FETCH_BUFFER_DEPTH
|INT:512
|vpiParameter:
\_parameter: (FPGA_VENDOR), line:27
|vpiName:FPGA_VENDOR
|STRING:"xilinx"
|vpiParameter:
\_parameter: (GC_UNIT_ID), line:196
|vpiName:GC_UNIT_ID
|INT:4
|vpiParameter:
\_parameter: (ICACHE_LINES), line:121
|vpiName:ICACHE_LINES
|INT:2
|vpiParameter:
\_parameter: (ICACHE_LINE_ADDR_W), line:123
|vpiName:ICACHE_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_LINE_W), line:124
|vpiName:ICACHE_LINE_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_SUB_LINE_ADDR_W), line:125
|vpiName:ICACHE_SUB_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_TAG_W), line:126
|vpiName:ICACHE_TAG_W
|INT:-2147483648
|vpiParameter:
\_parameter: (ICACHE_WAYS), line:122
|vpiName:ICACHE_WAYS
|INT:1
|vpiParameter:
\_parameter: (ITLB_DEPTH), line:146
|vpiName:ITLB_DEPTH
|INT:32
|vpiParameter:
\_parameter: (ITLB_WAYS), line:145
|vpiName:ITLB_WAYS
|INT:4
|vpiParameter:
\_parameter: (L1_CONNECTIONS), line:177
|vpiName:L1_CONNECTIONS
|INT:9
|vpiParameter:
\_parameter: (L1_DCACHE_ID), line:178
|vpiName:L1_DCACHE_ID
|INT:4
|vpiParameter:
\_parameter: (L1_DMMU_ID), line:179
|vpiName:L1_DMMU_ID
|INT:2
|vpiParameter:
\_parameter: (L1_ICACHE_ID), line:180
|vpiName:L1_ICACHE_ID
|INT:19
|vpiParameter:
\_parameter: (L1_IMMU_ID), line:181
|vpiName:L1_IMMU_ID
|INT:0
|vpiParameter:
\_parameter: (LS_UNIT_WB_ID), line:191
|vpiName:LS_UNIT_WB_ID
|INT:1
|vpiParameter:
\_parameter: (MAX_INFLIGHT_COUNT), line:167
|vpiName:MAX_INFLIGHT_COUNT
|INT:19
|vpiParameter:
\_parameter: (MEMORY_ADDR_H), line:103
|vpiName:MEMORY_ADDR_H
|INT:12
|vpiParameter:
\_parameter: (MEMORY_ADDR_L), line:102
|vpiName:MEMORY_ADDR_L
|INT:11
|vpiParameter:
\_parameter: (MEMORY_BIT_CHECK), line:104
|vpiName:MEMORY_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (MUL_UNIT_WB_ID), line:193
|vpiName:MUL_UNIT_WB_ID
|INT:512
|vpiParameter:
\_parameter: (NUM_UNITS), line:188
|vpiName:NUM_UNITS
|INT:2
|vpiParameter:
\_parameter: (NUM_WB_UNITS), line:186
|vpiName:NUM_WB_UNITS
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (RAS_DEPTH), line:161
|vpiName:RAS_DEPTH
|INT:2
|vpiParameter:
\_parameter: (RESET_VEC), line:39
|vpiName:RESET_VEC
|INT:-2147483648
|vpiParameter:
\_parameter: (SCRATCH_ADDR_H), line:99
|vpiName:SCRATCH_ADDR_H
|INT:9
|vpiParameter:
\_parameter: (SCRATCH_ADDR_L), line:98
|vpiName:SCRATCH_ADDR_L
|INT:8
|vpiParameter:
\_parameter: (SCRATCH_BIT_CHECK), line:100
|vpiName:SCRATCH_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (USE_AMO), line:70
|vpiName:USE_AMO
|INT:1
|vpiParameter:
\_parameter: (USE_BRANCH_PREDICTOR), line:158
|vpiName:USE_BRANCH_PREDICTOR
|INT:2
|vpiParameter:
\_parameter: (USE_BUS), line:88
|vpiName:USE_BUS
|INT:4
|vpiParameter:
\_parameter: (USE_DCACHE), line:92
|vpiName:USE_DCACHE
|INT:6
|vpiParameter:
\_parameter: (USE_DIV), line:49
|vpiName:USE_DIV
|INT:1
|vpiParameter:
\_parameter: (USE_DTAG_INVALIDATIONS), line:140
|vpiName:USE_DTAG_INVALIDATIONS
|INT:1879048191
|vpiParameter:
\_parameter: (USE_D_SCRATCH_MEM), line:79
|vpiName:USE_D_SCRATCH_MEM
|INT:3
|vpiParameter:
\_parameter: (USE_ICACHE), line:93
|vpiName:USE_ICACHE
|INT:7
|vpiParameter:
\_parameter: (USE_I_SCRATCH_MEM), line:78
|vpiName:USE_I_SCRATCH_MEM
|INT:2
|vpiParameter:
\_parameter: (USE_MUL), line:48
|vpiName:USE_MUL
|INT:1
|vpiParameter:
\_parameter: (WB_UNITS_WIDTH), line:187
|vpiName:WB_UNITS_WIDTH
|INT:32
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiModule:
\_module: work@ddata_bank (data_bank), file:third_party/cores/taiga/core/dcache.sv, line:237, parent:data_cache
|vpiDefName:work@ddata_bank
|vpiName:data_bank
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.data_bank
|vpiPort:
\_port: (clk), line:30, parent:data_bank
|vpiName:clk
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (clk), line:238
|vpiName:clk
|vpiActual:
\_logic_net: (clk), line:27, parent:data_cache
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (clk), line:30, parent:data_bank
|vpiName:clk
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.data_bank.clk
|vpiNetType:36
|vpiPort:
\_port: (addr_a), line:31, parent:data_bank
|vpiName:addr_a
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (data_bank_addr_a), line:239
|vpiName:data_bank_addr_a
|vpiActual:
\_logic_net: (data_bank_addr_a), line:45, parent:data_cache
|vpiName:data_bank_addr_a
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.data_bank_addr_a
|vpiNetType:36
|vpiRange:
\_range: , line:45
|vpiLeftRange:
\_constant: , line:45
|vpiDecompile:-1
|INT:-1
|vpiRightRange:
\_constant: , line:45
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (addr_a), line:31, parent:data_bank
|vpiName:addr_a
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.data_bank.addr_a
|vpiNetType:36
|vpiRange:
\_range: , line:31
|vpiLeftRange:
\_constant: , line:31
|vpiDecompile:-1
|INT:-1
|vpiRightRange:
\_constant: , line:31
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiPort:
\_port: (addr_b), line:32, parent:data_bank
|vpiName:addr_b
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (data_bank_addr_b), line:240
|vpiName:data_bank_addr_b
|vpiActual:
\_logic_net: (data_bank_addr_b), line:46, parent:data_cache
|vpiName:data_bank_addr_b
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.data_bank_addr_b
|vpiNetType:36
|vpiRange:
\_range: , line:46
|vpiLeftRange:
\_constant: , line:46
|vpiDecompile:-1
|INT:-1
|vpiRightRange:
\_constant: , line:46
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (en_a), line:32, parent:data_bank
|vpiName:en_a
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.data_bank.en_a
|vpiNetType:36
|vpiPort:
\_port: (en_a), line:33, parent:data_bank
|vpiName:en_a
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (second_cycle), line:241
|vpiName:second_cycle
|vpiActual:
\_logic_net: (second_cycle), line:85, parent:data_cache
|vpiName:second_cycle
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.second_cycle
|vpiNetType:36
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (be_a), line:33, parent:data_bank
|vpiName:be_a
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.data_bank.be_a
|vpiNetType:36
|vpiRange:
\_range: , line:33
|vpiLeftRange:
\_constant: , line:33
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiRightRange:
\_constant: , line:33
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiPort:
\_port: (en_b), line:34, parent:data_bank
|vpiName:en_b
|vpiDirection:1
|vpiHighConn:
\_operation: , line:242
|vpiOpType:29
|vpiOperand:
\_ref_obj: (l1_response.data_valid), line:242
|vpiName:l1_response.data_valid
|vpiOperand:
\_operation: , line:242
|vpiOpType:28
|vpiOperand:
\_ref_obj: (sc_complete), line:242
|vpiName:sc_complete
|vpiOperand:
\_ref_obj: (sc_success), line:242
|vpiName:sc_success
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (data_in_a), line:34, parent:data_bank
|vpiName:data_in_a
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.data_bank.data_in_a
|vpiNetType:36
|vpiRange:
\_range: , line:34
|vpiLeftRange:
\_constant: , line:34
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:34
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiPort:
\_port: (be_a), line:35, parent:data_bank
|vpiName:be_a
|vpiDirection:2
|vpiHighConn:
\_ref_obj: (write_hit_be), line:243
|vpiName:write_hit_be
|vpiActual:
\_logic_net: (write_hit_be), line:83, parent:data_cache
|vpiName:write_hit_be
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.write_hit_be
|vpiNetType:36
|vpiRange:
\_range: , line:83
|vpiLeftRange:
\_constant: , line:83
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiRightRange:
\_constant: , line:83
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (data_out_a), line:35, parent:data_bank
|vpiName:data_out_a
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.data_bank.data_out_a
|vpiNetType:36
|vpiRange:
\_range: , line:35
|vpiLeftRange:
\_constant: , line:35
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:35
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiPort:
\_port: (data_in_a), line:38, parent:data_bank
|vpiName:data_in_a
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (stage2_data), line:244
|vpiName:stage2_data
|vpiActual:
\_logic_net: (stage2_data), line:72, parent:data_cache
|vpiName:stage2_data
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.stage2_data
|vpiNetType:36
|vpiRange:
\_range: , line:72
|vpiLeftRange:
\_constant: , line:72
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:72
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (addr_b), line:38, parent:data_bank
|vpiName:addr_b
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.data_bank.addr_b
|vpiNetType:36
|vpiRange:
\_range: , line:38
|vpiLeftRange:
\_constant: , line:38
|vpiDecompile:-1
|INT:-1
|vpiRightRange:
\_constant: , line:38
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiPort:
\_port: (data_in_b), line:39, parent:data_bank
|vpiName:data_in_b
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (new_line_data), line:245
|vpiName:new_line_data
|vpiActual:
\_logic_net: (new_line_data), line:79, parent:data_cache
|vpiName:new_line_data
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.new_line_data
|vpiNetType:36
|vpiRange:
\_range: , line:79
|vpiLeftRange:
\_constant: , line:79
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:79
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (en_b), line:39, parent:data_bank
|vpiName:en_b
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.data_bank.en_b
|vpiNetType:36
|vpiPort:
\_port: (data_out_a), line:40, parent:data_bank
|vpiName:data_out_a
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (dbank_data_out), line:246
|vpiName:dbank_data_out
|vpiActual:
\_logic_net: (dbank_data_out), line:76, parent:data_cache
|vpiName:dbank_data_out
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.dbank_data_out
|vpiNetType:36
|vpiRange:
\_range: , line:76
|vpiLeftRange:
\_constant: , line:76
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:76
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (data_in_b), line:40, parent:data_bank
|vpiName:data_in_b
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.data_bank.data_in_b
|vpiNetType:36
|vpiRange:
\_range: , line:40
|vpiLeftRange:
\_constant: , line:40
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:40
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiModule:
\_module: work@byte_en_BRAM (ram_block), file:third_party/cores/taiga/core/ddata_bank.sv, line:43, parent:data_bank
|vpiDefName:work@byte_en_BRAM
|vpiName:ram_block
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.data_bank.ram_block
|vpiPort:
\_port: (clk), line:32, parent:ram_block
|vpiName:clk
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (clk), line:43
|vpiName:clk
|vpiActual:
\_logic_net: (clk), line:30, parent:data_bank
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (clk), line:32, parent:ram_block
|vpiName:clk
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.data_bank.ram_block.clk
|vpiNetType:36
|vpiPort:
\_port: (addr_a), line:33, parent:ram_block
|vpiName:addr_a
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (addr_a), line:43
|vpiName:addr_a
|vpiActual:
\_logic_net: (addr_a), line:31, parent:data_bank
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (addr_a), line:33, parent:ram_block
|vpiName:addr_a
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.data_bank.ram_block.addr_a
|vpiNetType:36
|vpiRange:
\_range: , line:33
|vpiLeftRange:
\_constant: , line:33
|vpiConstType:7
|vpiDecompile:11
|vpiSize:32
|INT:11
|vpiRightRange:
\_constant: , line:33
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiPort:
\_port: (en_a), line:34, parent:ram_block
|vpiName:en_a
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (en_a), line:43
|vpiName:en_a
|vpiActual:
\_logic_net: (en_a), line:32, parent:data_bank
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (en_a), line:34, parent:ram_block
|vpiName:en_a
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.data_bank.ram_block.en_a
|vpiNetType:36
|vpiPort:
\_port: (be_a), line:35, parent:ram_block
|vpiName:be_a
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (be_a), line:43
|vpiName:be_a
|vpiActual:
\_logic_net: (be_a), line:33, parent:data_bank
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (be_a), line:35, parent:ram_block
|vpiName:be_a
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.data_bank.ram_block.be_a
|vpiNetType:36
|vpiRange:
\_range: , line:35
|vpiLeftRange:
\_constant: , line:35
|vpiConstType:7
|vpiDecompile:18446744073709551615
|vpiSize:32
|INT:-1
|vpiRightRange:
\_constant: , line:35
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiPort:
\_port: (data_in_a), line:36, parent:ram_block
|vpiName:data_in_a
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (data_in_a), line:43
|vpiName:data_in_a
|vpiActual:
\_logic_net: (data_in_a), line:34, parent:data_bank
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (data_in_a), line:36, parent:ram_block
|vpiName:data_in_a
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.data_bank.ram_block.data_in_a
|vpiNetType:36
|vpiRange:
\_range: , line:36
|vpiLeftRange:
\_constant: , line:36
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiRightRange:
\_constant: , line:36
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiPort:
\_port: (data_out_a), line:37, parent:ram_block
|vpiName:data_out_a
|vpiDirection:2
|vpiHighConn:
\_ref_obj: (data_out_a), line:43
|vpiName:data_out_a
|vpiActual:
\_logic_net: (data_out_a), line:35, parent:data_bank
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (data_out_a), line:37, parent:ram_block
|vpiName:data_out_a
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.data_bank.ram_block.data_out_a
|vpiNetType:36
|vpiRange:
\_range: , line:37
|vpiLeftRange:
\_constant: , line:37
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiRightRange:
\_constant: , line:37
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiPort:
\_port: (addr_b), line:39, parent:ram_block
|vpiName:addr_b
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (addr_b), line:43
|vpiName:addr_b
|vpiActual:
\_logic_net: (addr_b), line:38, parent:data_bank
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (addr_b), line:39, parent:ram_block
|vpiName:addr_b
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.data_bank.ram_block.addr_b
|vpiNetType:36
|vpiRange:
\_range: , line:39
|vpiLeftRange:
\_constant: , line:39
|vpiConstType:7
|vpiDecompile:11
|vpiSize:32
|INT:11
|vpiRightRange:
\_constant: , line:39
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiPort:
\_port: (en_b), line:40, parent:ram_block
|vpiName:en_b
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (en_b), line:43
|vpiName:en_b
|vpiActual:
\_logic_net: (en_b), line:39, parent:data_bank
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (en_b), line:40, parent:ram_block
|vpiName:en_b
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.data_bank.ram_block.en_b
|vpiNetType:36
|vpiPort:
\_port: (be_b), line:41, parent:ram_block
|vpiName:be_b
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (be_b), line:43
|vpiName:be_b
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (be_b), line:41, parent:ram_block
|vpiName:be_b
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.data_bank.ram_block.be_b
|vpiNetType:36
|vpiRange:
\_range: , line:41
|vpiLeftRange:
\_constant: , line:41
|vpiConstType:7
|vpiDecompile:18446744073709551615
|vpiSize:32
|INT:-1
|vpiRightRange:
\_constant: , line:41
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiPort:
\_port: (data_in_b), line:42, parent:ram_block
|vpiName:data_in_b
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (data_in_b), line:43
|vpiName:data_in_b
|vpiActual:
\_logic_net: (data_in_b), line:40, parent:data_bank
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (data_in_b), line:42, parent:ram_block
|vpiName:data_in_b
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.data_bank.ram_block.data_in_b
|vpiNetType:36
|vpiRange:
\_range: , line:42
|vpiLeftRange:
\_constant: , line:42
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiRightRange:
\_constant: , line:42
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiPort:
\_port: (data_out_b), line:43, parent:ram_block
|vpiName:data_out_b
|vpiDirection:2
|vpiHighConn:
\_ref_obj: (data_out_b), line:43
|vpiName:data_out_b
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (data_out_b), line:43, parent:ram_block
|vpiName:data_out_b
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.data_bank.ram_block.data_out_b
|vpiNetType:36
|vpiRange:
\_range: , line:43
|vpiLeftRange:
\_constant: , line:43
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiRightRange:
\_constant: , line:43
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiGenScopeArray:
\_gen_scope_array: (genblk1), line:47, parent:ram_block
|vpiName:genblk1
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.data_bank.ram_block.genblk1
|vpiGenScope:
\_gen_scope: , parent:genblk1
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.data_bank.ram_block.genblk1
|vpiModule:
\_module: work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.data_bank.ram_block.genblk1::intel_byte_enable_ram (ram_block), file:third_party/cores/taiga/core/byte_en_BRAM.sv, line:50
|vpiDefName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.data_bank.ram_block.genblk1::intel_byte_enable_ram
|vpiName:ram_block
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.data_bank.ram_block.genblk1.ram_block
|vpiParameter:
\_parameter: (ALU_UNIT_WB_ID), line:190
|vpiName:ALU_UNIT_WB_ID
|INT:32
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (BRANCH_PREDICTOR_WAYS), line:159
|vpiName:BRANCH_PREDICTOR_WAYS
|INT:9
|vpiParameter:
\_parameter: (BRANCH_TABLE_ENTRIES), line:160
|vpiName:BRANCH_TABLE_ENTRIES
|INT:4
|vpiParameter:
\_parameter: (BRANCH_UNIT_ID), line:195
|vpiName:BRANCH_UNIT_ID
|INT:8
|vpiParameter:
\_parameter: (BUS_ADDR_H), line:107
|vpiName:BUS_ADDR_H
|INT:1
|vpiParameter:
\_parameter: (BUS_ADDR_L), line:106
|vpiName:BUS_ADDR_L
|INT:0
|vpiParameter:
\_parameter: (BUS_BIT_CHECK), line:108
|vpiName:BUS_BIT_CHECK
|INT:1
|vpiParameter:
\_parameter: (BUS_TYPE), line:89
|vpiName:BUS_TYPE
|INT:5
|vpiParameter:
\_parameter: (COUNTER_W), line:42
|vpiName:COUNTER_W
|INT:33
|vpiParameter:
\_parameter: (CPU_ID), line:38
|vpiName:CPU_ID
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_ADDR_WIDTH), line:113
|vpiName:C_M_AXI_ADDR_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_DATA_WIDTH), line:114
|vpiName:C_M_AXI_DATA_WIDTH
|INT:1
|vpiParameter:
\_parameter: (DCACHE_LINES), line:133
|vpiName:DCACHE_LINES
|INT:-2146435073
|vpiParameter:
\_parameter: (DCACHE_LINE_ADDR_W), line:135
|vpiName:DCACHE_LINE_ADDR_W
|INT:1073741824
|vpiParameter:
\_parameter: (DCACHE_LINE_W), line:136
|vpiName:DCACHE_LINE_W
|INT:1342177279
|vpiParameter:
\_parameter: (DCACHE_SUB_LINE_ADDR_W), line:137
|vpiName:DCACHE_SUB_LINE_ADDR_W
|INT:4
|vpiParameter:
\_parameter: (DCACHE_TAG_W), line:138
|vpiName:DCACHE_TAG_W
|INT:1610612736
|vpiParameter:
\_parameter: (DCACHE_WAYS), line:134
|vpiName:DCACHE_WAYS
|INT:4
|vpiParameter:
\_parameter: (DIV_ALGORITHM), line:67
|vpiName:DIV_ALGORITHM
|INT:0
|vpiParameter:
\_parameter: (DIV_UNIT_WB_ID), line:192
|vpiName:DIV_UNIT_WB_ID
|INT:2
|vpiParameter:
\_parameter: (DTLB_DEPTH), line:152
|vpiName:DTLB_DEPTH
|INT:512
|vpiParameter:
\_parameter: (DTLB_WAYS), line:151
|vpiName:DTLB_WAYS
|INT:32
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (ENABLE_M_MODE), line:34
|vpiName:ENABLE_M_MODE
|INT:1
|vpiParameter:
\_parameter: (ENABLE_S_MODE), line:36
|vpiName:ENABLE_S_MODE
|INT:0
|vpiParameter:
\_parameter: (ENABLE_TRACE_INTERFACE), line:172
|vpiName:ENABLE_TRACE_INTERFACE
|INT:2
|vpiParameter:
\_parameter: (FETCH_BUFFER_DEPTH), line:168
|vpiName:FETCH_BUFFER_DEPTH
|INT:512
|vpiParameter:
\_parameter: (FPGA_VENDOR), line:27
|vpiName:FPGA_VENDOR
|STRING:"xilinx"
|vpiParameter:
\_parameter: (GC_UNIT_ID), line:196
|vpiName:GC_UNIT_ID
|INT:4
|vpiParameter:
\_parameter: (ICACHE_LINES), line:121
|vpiName:ICACHE_LINES
|INT:2
|vpiParameter:
\_parameter: (ICACHE_LINE_ADDR_W), line:123
|vpiName:ICACHE_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_LINE_W), line:124
|vpiName:ICACHE_LINE_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_SUB_LINE_ADDR_W), line:125
|vpiName:ICACHE_SUB_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_TAG_W), line:126
|vpiName:ICACHE_TAG_W
|INT:-2147483648
|vpiParameter:
\_parameter: (ICACHE_WAYS), line:122
|vpiName:ICACHE_WAYS
|INT:1
|vpiParameter:
\_parameter: (ITLB_DEPTH), line:146
|vpiName:ITLB_DEPTH
|INT:32
|vpiParameter:
\_parameter: (ITLB_WAYS), line:145
|vpiName:ITLB_WAYS
|INT:4
|vpiParameter:
\_parameter: (L1_CONNECTIONS), line:177
|vpiName:L1_CONNECTIONS
|INT:9
|vpiParameter:
\_parameter: (L1_DCACHE_ID), line:178
|vpiName:L1_DCACHE_ID
|INT:4
|vpiParameter:
\_parameter: (L1_DMMU_ID), line:179
|vpiName:L1_DMMU_ID
|INT:2
|vpiParameter:
\_parameter: (L1_ICACHE_ID), line:180
|vpiName:L1_ICACHE_ID
|INT:19
|vpiParameter:
\_parameter: (L1_IMMU_ID), line:181
|vpiName:L1_IMMU_ID
|INT:0
|vpiParameter:
\_parameter: (LS_UNIT_WB_ID), line:191
|vpiName:LS_UNIT_WB_ID
|INT:1
|vpiParameter:
\_parameter: (MAX_INFLIGHT_COUNT), line:167
|vpiName:MAX_INFLIGHT_COUNT
|INT:19
|vpiParameter:
\_parameter: (MEMORY_ADDR_H), line:103
|vpiName:MEMORY_ADDR_H
|INT:12
|vpiParameter:
\_parameter: (MEMORY_ADDR_L), line:102
|vpiName:MEMORY_ADDR_L
|INT:11
|vpiParameter:
\_parameter: (MEMORY_BIT_CHECK), line:104
|vpiName:MEMORY_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (MUL_UNIT_WB_ID), line:193
|vpiName:MUL_UNIT_WB_ID
|INT:512
|vpiParameter:
\_parameter: (NUM_UNITS), line:188
|vpiName:NUM_UNITS
|INT:2
|vpiParameter:
\_parameter: (NUM_WB_UNITS), line:186
|vpiName:NUM_WB_UNITS
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (RAS_DEPTH), line:161
|vpiName:RAS_DEPTH
|INT:2
|vpiParameter:
\_parameter: (RESET_VEC), line:39
|vpiName:RESET_VEC
|INT:-2147483648
|vpiParameter:
\_parameter: (SCRATCH_ADDR_H), line:99
|vpiName:SCRATCH_ADDR_H
|INT:9
|vpiParameter:
\_parameter: (SCRATCH_ADDR_L), line:98
|vpiName:SCRATCH_ADDR_L
|INT:8
|vpiParameter:
\_parameter: (SCRATCH_BIT_CHECK), line:100
|vpiName:SCRATCH_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (USE_AMO), line:70
|vpiName:USE_AMO
|INT:1
|vpiParameter:
\_parameter: (USE_BRANCH_PREDICTOR), line:158
|vpiName:USE_BRANCH_PREDICTOR
|INT:2
|vpiParameter:
\_parameter: (USE_BUS), line:88
|vpiName:USE_BUS
|INT:4
|vpiParameter:
\_parameter: (USE_DCACHE), line:92
|vpiName:USE_DCACHE
|INT:6
|vpiParameter:
\_parameter: (USE_DIV), line:49
|vpiName:USE_DIV
|INT:1
|vpiParameter:
\_parameter: (USE_DTAG_INVALIDATIONS), line:140
|vpiName:USE_DTAG_INVALIDATIONS
|INT:1879048191
|vpiParameter:
\_parameter: (USE_D_SCRATCH_MEM), line:79
|vpiName:USE_D_SCRATCH_MEM
|INT:3
|vpiParameter:
\_parameter: (USE_ICACHE), line:93
|vpiName:USE_ICACHE
|INT:7
|vpiParameter:
\_parameter: (USE_I_SCRATCH_MEM), line:78
|vpiName:USE_I_SCRATCH_MEM
|INT:2
|vpiParameter:
\_parameter: (USE_MUL), line:48
|vpiName:USE_MUL
|INT:1
|vpiParameter:
\_parameter: (WB_UNITS_WIDTH), line:187
|vpiName:WB_UNITS_WIDTH
|INT:32
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiNet:
\_logic_net: (clk), line:32, parent:ram_block
|vpiNet:
\_logic_net: (addr_a), line:33, parent:ram_block
|vpiNet:
\_logic_net: (en_a), line:34, parent:ram_block
|vpiNet:
\_logic_net: (be_a), line:35, parent:ram_block
|vpiNet:
\_logic_net: (data_in_a), line:36, parent:ram_block
|vpiNet:
\_logic_net: (data_out_a), line:37, parent:ram_block
|vpiNet:
\_logic_net: (addr_b), line:39, parent:ram_block
|vpiNet:
\_logic_net: (en_b), line:40, parent:ram_block
|vpiNet:
\_logic_net: (be_b), line:41, parent:ram_block
|vpiNet:
\_logic_net: (data_in_b), line:42, parent:ram_block
|vpiNet:
\_logic_net: (data_out_b), line:43, parent:ram_block
|vpiInstance:
\_module: work@ddata_bank (data_bank), file:third_party/cores/taiga/core/dcache.sv, line:237, parent:data_cache
|vpiParameter:
\_parameter: (ALU_UNIT_WB_ID), line:190
|vpiName:ALU_UNIT_WB_ID
|INT:32
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (BRANCH_PREDICTOR_WAYS), line:159
|vpiName:BRANCH_PREDICTOR_WAYS
|INT:9
|vpiParameter:
\_parameter: (BRANCH_TABLE_ENTRIES), line:160
|vpiName:BRANCH_TABLE_ENTRIES
|INT:4
|vpiParameter:
\_parameter: (BRANCH_UNIT_ID), line:195
|vpiName:BRANCH_UNIT_ID
|INT:8
|vpiParameter:
\_parameter: (BUS_ADDR_H), line:107
|vpiName:BUS_ADDR_H
|INT:1
|vpiParameter:
\_parameter: (BUS_ADDR_L), line:106
|vpiName:BUS_ADDR_L
|INT:0
|vpiParameter:
\_parameter: (BUS_BIT_CHECK), line:108
|vpiName:BUS_BIT_CHECK
|INT:1
|vpiParameter:
\_parameter: (BUS_TYPE), line:89
|vpiName:BUS_TYPE
|INT:5
|vpiParameter:
\_parameter: (COUNTER_W), line:42
|vpiName:COUNTER_W
|INT:33
|vpiParameter:
\_parameter: (CPU_ID), line:38
|vpiName:CPU_ID
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_ADDR_WIDTH), line:113
|vpiName:C_M_AXI_ADDR_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_DATA_WIDTH), line:114
|vpiName:C_M_AXI_DATA_WIDTH
|INT:1
|vpiParameter:
\_parameter: (DCACHE_LINES), line:133
|vpiName:DCACHE_LINES
|INT:-2146435073
|vpiParameter:
\_parameter: (DCACHE_LINE_ADDR_W), line:135
|vpiName:DCACHE_LINE_ADDR_W
|INT:1073741824
|vpiParameter:
\_parameter: (DCACHE_LINE_W), line:136
|vpiName:DCACHE_LINE_W
|INT:1342177279
|vpiParameter:
\_parameter: (DCACHE_SUB_LINE_ADDR_W), line:137
|vpiName:DCACHE_SUB_LINE_ADDR_W
|INT:4
|vpiParameter:
\_parameter: (DCACHE_TAG_W), line:138
|vpiName:DCACHE_TAG_W
|INT:1610612736
|vpiParameter:
\_parameter: (DCACHE_WAYS), line:134
|vpiName:DCACHE_WAYS
|INT:4
|vpiParameter:
\_parameter: (DIV_ALGORITHM), line:67
|vpiName:DIV_ALGORITHM
|INT:0
|vpiParameter:
\_parameter: (DIV_UNIT_WB_ID), line:192
|vpiName:DIV_UNIT_WB_ID
|INT:2
|vpiParameter:
\_parameter: (DTLB_DEPTH), line:152
|vpiName:DTLB_DEPTH
|INT:512
|vpiParameter:
\_parameter: (DTLB_WAYS), line:151
|vpiName:DTLB_WAYS
|INT:32
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (ENABLE_M_MODE), line:43
|vpiName:ENABLE_M_MODE
|STRING:""
|vpiParameter:
\_parameter: (ENABLE_S_MODE), line:43
|vpiName:ENABLE_S_MODE
|INT:0
|vpiParameter:
\_parameter: (ENABLE_TRACE_INTERFACE), line:172
|vpiName:ENABLE_TRACE_INTERFACE
|INT:2
|vpiParameter:
\_parameter: (FETCH_BUFFER_DEPTH), line:168
|vpiName:FETCH_BUFFER_DEPTH
|INT:512
|vpiParameter:
\_parameter: (FPGA_VENDOR), line:43
|vpiName:FPGA_VENDOR
|INT:-1
|vpiParameter:
\_parameter: (GC_UNIT_ID), line:196
|vpiName:GC_UNIT_ID
|INT:4
|vpiParameter:
\_parameter: (ICACHE_LINES), line:121
|vpiName:ICACHE_LINES
|INT:2
|vpiParameter:
\_parameter: (ICACHE_LINE_ADDR_W), line:123
|vpiName:ICACHE_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_LINE_W), line:124
|vpiName:ICACHE_LINE_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_SUB_LINE_ADDR_W), line:125
|vpiName:ICACHE_SUB_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_TAG_W), line:126
|vpiName:ICACHE_TAG_W
|INT:-2147483648
|vpiParameter:
\_parameter: (ICACHE_WAYS), line:122
|vpiName:ICACHE_WAYS
|INT:1
|vpiParameter:
\_parameter: (ITLB_DEPTH), line:146
|vpiName:ITLB_DEPTH
|INT:32
|vpiParameter:
\_parameter: (ITLB_WAYS), line:145
|vpiName:ITLB_WAYS
|INT:4
|vpiParameter:
\_parameter: (L1_CONNECTIONS), line:177
|vpiName:L1_CONNECTIONS
|INT:9
|vpiParameter:
\_parameter: (L1_DCACHE_ID), line:178
|vpiName:L1_DCACHE_ID
|INT:4
|vpiParameter:
\_parameter: (L1_DMMU_ID), line:179
|vpiName:L1_DMMU_ID
|INT:2
|vpiParameter:
\_parameter: (L1_ICACHE_ID), line:180
|vpiName:L1_ICACHE_ID
|INT:19
|vpiParameter:
\_parameter: (L1_IMMU_ID), line:181
|vpiName:L1_IMMU_ID
|INT:0
|vpiParameter:
\_parameter: (LINES), line:27
|vpiName:LINES
|INT:4096
|vpiParameter:
\_parameter: (LS_UNIT_WB_ID), line:191
|vpiName:LS_UNIT_WB_ID
|INT:1
|vpiParameter:
\_parameter: (MAX_INFLIGHT_COUNT), line:167
|vpiName:MAX_INFLIGHT_COUNT
|INT:19
|vpiParameter:
\_parameter: (MEMORY_ADDR_H), line:103
|vpiName:MEMORY_ADDR_H
|INT:12
|vpiParameter:
\_parameter: (MEMORY_ADDR_L), line:102
|vpiName:MEMORY_ADDR_L
|INT:11
|vpiParameter:
\_parameter: (MEMORY_BIT_CHECK), line:104
|vpiName:MEMORY_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (MUL_UNIT_WB_ID), line:193
|vpiName:MUL_UNIT_WB_ID
|INT:512
|vpiParameter:
\_parameter: (NUM_UNITS), line:188
|vpiName:NUM_UNITS
|INT:2
|vpiParameter:
\_parameter: (NUM_WB_UNITS), line:186
|vpiName:NUM_WB_UNITS
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (RAS_DEPTH), line:161
|vpiName:RAS_DEPTH
|INT:2
|vpiParameter:
\_parameter: (RESET_VEC), line:39
|vpiName:RESET_VEC
|INT:-2147483648
|vpiParameter:
\_parameter: (SCRATCH_ADDR_H), line:99
|vpiName:SCRATCH_ADDR_H
|INT:9
|vpiParameter:
\_parameter: (SCRATCH_ADDR_L), line:98
|vpiName:SCRATCH_ADDR_L
|INT:8
|vpiParameter:
\_parameter: (SCRATCH_BIT_CHECK), line:100
|vpiName:SCRATCH_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (USE_AMO), line:70
|vpiName:USE_AMO
|INT:1
|vpiParameter:
\_parameter: (USE_BRANCH_PREDICTOR), line:158
|vpiName:USE_BRANCH_PREDICTOR
|INT:2
|vpiParameter:
\_parameter: (USE_BUS), line:88
|vpiName:USE_BUS
|INT:4
|vpiParameter:
\_parameter: (USE_DCACHE), line:92
|vpiName:USE_DCACHE
|INT:6
|vpiParameter:
\_parameter: (USE_DIV), line:49
|vpiName:USE_DIV
|INT:1
|vpiParameter:
\_parameter: (USE_DTAG_INVALIDATIONS), line:140
|vpiName:USE_DTAG_INVALIDATIONS
|INT:1879048191
|vpiParameter:
\_parameter: (USE_D_SCRATCH_MEM), line:79
|vpiName:USE_D_SCRATCH_MEM
|INT:3
|vpiParameter:
\_parameter: (USE_ICACHE), line:93
|vpiName:USE_ICACHE
|INT:7
|vpiParameter:
\_parameter: (USE_I_SCRATCH_MEM), line:78
|vpiName:USE_I_SCRATCH_MEM
|INT:2
|vpiParameter:
\_parameter: (USE_MUL), line:48
|vpiName:USE_MUL
|INT:1
|vpiParameter:
\_parameter: (USE_PRELOAD_FILE), line:29
|vpiName:USE_PRELOAD_FILE
|INT:0
|vpiParameter:
\_parameter: (WB_UNITS_WIDTH), line:187
|vpiName:WB_UNITS_WIDTH
|INT:32
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiParameter:
\_parameter: (preload_file), line:28
|vpiName:preload_file
|STRING:""
|vpiNet:
\_logic_net: (clk), line:30, parent:data_bank
|vpiNet:
\_logic_net: (addr_a), line:31, parent:data_bank
|vpiNet:
\_logic_net: (en_a), line:32, parent:data_bank
|vpiNet:
\_logic_net: (be_a), line:33, parent:data_bank
|vpiNet:
\_logic_net: (data_in_a), line:34, parent:data_bank
|vpiNet:
\_logic_net: (data_out_a), line:35, parent:data_bank
|vpiNet:
\_logic_net: (addr_b), line:38, parent:data_bank
|vpiNet:
\_logic_net: (en_b), line:39, parent:data_bank
|vpiNet:
\_logic_net: (data_in_b), line:40, parent:data_bank
|vpiInstance:
\_module: work@dcache (data_cache), file:third_party/cores/taiga/core/load_store_unit.sv, line:312
|vpiParameter:
\_parameter: (ALU_UNIT_WB_ID), line:190
|vpiName:ALU_UNIT_WB_ID
|INT:32
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (BRANCH_PREDICTOR_WAYS), line:159
|vpiName:BRANCH_PREDICTOR_WAYS
|INT:9
|vpiParameter:
\_parameter: (BRANCH_TABLE_ENTRIES), line:160
|vpiName:BRANCH_TABLE_ENTRIES
|INT:4
|vpiParameter:
\_parameter: (BRANCH_UNIT_ID), line:195
|vpiName:BRANCH_UNIT_ID
|INT:8
|vpiParameter:
\_parameter: (BUS_ADDR_H), line:107
|vpiName:BUS_ADDR_H
|INT:1
|vpiParameter:
\_parameter: (BUS_ADDR_L), line:106
|vpiName:BUS_ADDR_L
|INT:0
|vpiParameter:
\_parameter: (BUS_BIT_CHECK), line:108
|vpiName:BUS_BIT_CHECK
|INT:1
|vpiParameter:
\_parameter: (BUS_TYPE), line:89
|vpiName:BUS_TYPE
|INT:5
|vpiParameter:
\_parameter: (COUNTER_W), line:42
|vpiName:COUNTER_W
|INT:33
|vpiParameter:
\_parameter: (CPU_ID), line:38
|vpiName:CPU_ID
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_ADDR_WIDTH), line:113
|vpiName:C_M_AXI_ADDR_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_DATA_WIDTH), line:114
|vpiName:C_M_AXI_DATA_WIDTH
|INT:1
|vpiParameter:
\_parameter: (DCACHE_LINES), line:133
|vpiName:DCACHE_LINES
|INT:-2146435073
|vpiParameter:
\_parameter: (DCACHE_LINE_ADDR_W), line:135
|vpiName:DCACHE_LINE_ADDR_W
|INT:1073741824
|vpiParameter:
\_parameter: (DCACHE_LINE_W), line:136
|vpiName:DCACHE_LINE_W
|INT:1342177279
|vpiParameter:
\_parameter: (DCACHE_SUB_LINE_ADDR_W), line:137
|vpiName:DCACHE_SUB_LINE_ADDR_W
|INT:4
|vpiParameter:
\_parameter: (DCACHE_TAG_W), line:138
|vpiName:DCACHE_TAG_W
|INT:1610612736
|vpiParameter:
\_parameter: (DCACHE_WAYS), line:134
|vpiName:DCACHE_WAYS
|INT:4
|vpiParameter:
\_parameter: (DIV_ALGORITHM), line:67
|vpiName:DIV_ALGORITHM
|INT:0
|vpiParameter:
\_parameter: (DIV_UNIT_WB_ID), line:192
|vpiName:DIV_UNIT_WB_ID
|INT:2
|vpiParameter:
\_parameter: (DTLB_DEPTH), line:152
|vpiName:DTLB_DEPTH
|INT:512
|vpiParameter:
\_parameter: (DTLB_WAYS), line:151
|vpiName:DTLB_WAYS
|INT:32
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (ENABLE_M_MODE), line:34
|vpiName:ENABLE_M_MODE
|INT:1
|vpiParameter:
\_parameter: (ENABLE_S_MODE), line:36
|vpiName:ENABLE_S_MODE
|INT:0
|vpiParameter:
\_parameter: (ENABLE_TRACE_INTERFACE), line:172
|vpiName:ENABLE_TRACE_INTERFACE
|INT:2
|vpiParameter:
\_parameter: (FETCH_BUFFER_DEPTH), line:168
|vpiName:FETCH_BUFFER_DEPTH
|INT:512
|vpiParameter:
\_parameter: (FPGA_VENDOR), line:27
|vpiName:FPGA_VENDOR
|STRING:"xilinx"
|vpiParameter:
\_parameter: (GC_UNIT_ID), line:196
|vpiName:GC_UNIT_ID
|INT:4
|vpiParameter:
\_parameter: (ICACHE_LINES), line:121
|vpiName:ICACHE_LINES
|INT:2
|vpiParameter:
\_parameter: (ICACHE_LINE_ADDR_W), line:123
|vpiName:ICACHE_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_LINE_W), line:124
|vpiName:ICACHE_LINE_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_SUB_LINE_ADDR_W), line:125
|vpiName:ICACHE_SUB_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_TAG_W), line:126
|vpiName:ICACHE_TAG_W
|INT:-2147483648
|vpiParameter:
\_parameter: (ICACHE_WAYS), line:122
|vpiName:ICACHE_WAYS
|INT:1
|vpiParameter:
\_parameter: (ITLB_DEPTH), line:146
|vpiName:ITLB_DEPTH
|INT:32
|vpiParameter:
\_parameter: (ITLB_WAYS), line:145
|vpiName:ITLB_WAYS
|INT:4
|vpiParameter:
\_parameter: (L1_CONNECTIONS), line:177
|vpiName:L1_CONNECTIONS
|INT:9
|vpiParameter:
\_parameter: (L1_DCACHE_ID), line:178
|vpiName:L1_DCACHE_ID
|INT:4
|vpiParameter:
\_parameter: (L1_DMMU_ID), line:179
|vpiName:L1_DMMU_ID
|INT:2
|vpiParameter:
\_parameter: (L1_ICACHE_ID), line:180
|vpiName:L1_ICACHE_ID
|INT:19
|vpiParameter:
\_parameter: (L1_IMMU_ID), line:181
|vpiName:L1_IMMU_ID
|INT:0
|vpiParameter:
\_parameter: (LINES), line:237
|vpiName:LINES
|INT:-1
|vpiParameter:
\_parameter: (LS_UNIT_WB_ID), line:191
|vpiName:LS_UNIT_WB_ID
|INT:1
|vpiParameter:
\_parameter: (MAX_INFLIGHT_COUNT), line:167
|vpiName:MAX_INFLIGHT_COUNT
|INT:19
|vpiParameter:
\_parameter: (MEMORY_ADDR_H), line:103
|vpiName:MEMORY_ADDR_H
|INT:12
|vpiParameter:
\_parameter: (MEMORY_ADDR_L), line:102
|vpiName:MEMORY_ADDR_L
|INT:11
|vpiParameter:
\_parameter: (MEMORY_BIT_CHECK), line:104
|vpiName:MEMORY_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (MUL_UNIT_WB_ID), line:193
|vpiName:MUL_UNIT_WB_ID
|INT:512
|vpiParameter:
\_parameter: (NUM_UNITS), line:188
|vpiName:NUM_UNITS
|INT:2
|vpiParameter:
\_parameter: (NUM_WB_UNITS), line:186
|vpiName:NUM_WB_UNITS
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (RAS_DEPTH), line:161
|vpiName:RAS_DEPTH
|INT:2
|vpiParameter:
\_parameter: (RESET_VEC), line:39
|vpiName:RESET_VEC
|INT:-2147483648
|vpiParameter:
\_parameter: (SCRATCH_ADDR_H), line:99
|vpiName:SCRATCH_ADDR_H
|INT:9
|vpiParameter:
\_parameter: (SCRATCH_ADDR_L), line:98
|vpiName:SCRATCH_ADDR_L
|INT:8
|vpiParameter:
\_parameter: (SCRATCH_BIT_CHECK), line:100
|vpiName:SCRATCH_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (USE_AMO), line:70
|vpiName:USE_AMO
|INT:1
|vpiParameter:
\_parameter: (USE_BRANCH_PREDICTOR), line:158
|vpiName:USE_BRANCH_PREDICTOR
|INT:2
|vpiParameter:
\_parameter: (USE_BUS), line:88
|vpiName:USE_BUS
|INT:4
|vpiParameter:
\_parameter: (USE_DCACHE), line:92
|vpiName:USE_DCACHE
|INT:6
|vpiParameter:
\_parameter: (USE_DIV), line:49
|vpiName:USE_DIV
|INT:1
|vpiParameter:
\_parameter: (USE_DTAG_INVALIDATIONS), line:140
|vpiName:USE_DTAG_INVALIDATIONS
|INT:1879048191
|vpiParameter:
\_parameter: (USE_D_SCRATCH_MEM), line:79
|vpiName:USE_D_SCRATCH_MEM
|INT:3
|vpiParameter:
\_parameter: (USE_ICACHE), line:93
|vpiName:USE_ICACHE
|INT:7
|vpiParameter:
\_parameter: (USE_I_SCRATCH_MEM), line:78
|vpiName:USE_I_SCRATCH_MEM
|INT:2
|vpiParameter:
\_parameter: (USE_MUL), line:48
|vpiName:USE_MUL
|INT:1
|vpiParameter:
\_parameter: (WB_UNITS_WIDTH), line:187
|vpiName:WB_UNITS_WIDTH
|INT:32
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiGenScopeArray:
\_gen_scope_array: (genblk1), line:211, parent:data_cache
|vpiName:genblk1
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.genblk1
|vpiGenScope:
\_gen_scope: , parent:genblk1
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.genblk1
|vpiModule:
\_module: work@amo_alu (amo_unit), file:third_party/cores/taiga/core/dcache.sv, line:212
|vpiDefName:work@amo_alu
|vpiName:amo_unit
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.genblk1.amo_unit
|vpiPort:
\_port: (amo_alu_inputs), line:27, parent:amo_unit
|vpiName:amo_alu_inputs
|vpiDirection:1
|vpiTypedef:
\_struct_typespec: (amo_alu_inputs_t), line:356
|vpiHighConn:
\_ref_obj: (amo_alu_inputs), line:212
|vpiName:amo_alu_inputs
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (amo_alu_inputs), line:27, parent:amo_unit
|vpiName:amo_alu_inputs
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.genblk1.amo_unit.amo_alu_inputs
|vpiPort:
\_port: (result), line:28, parent:amo_unit
|vpiName:result
|vpiDirection:2
|vpiHighConn:
\_ref_obj: (result), line:212
|vpiName:result
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (result), line:28, parent:amo_unit
|vpiName:result
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.genblk1.amo_unit.result
|vpiNetType:36
|vpiRange:
\_range: , line:28
|vpiLeftRange:
\_constant: , line:28
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:28
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (amo_alu_inputs), line:27, parent:amo_unit
|vpiNet:
\_logic_net: (result), line:28, parent:amo_unit
|vpiNet:
\_logic_net: (rs1_smaller_than_rs2), line:31, parent:amo_unit
|vpiName:rs1_smaller_than_rs2
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.genblk1.amo_unit.rs1_smaller_than_rs2
|vpiNetType:36
|vpiNet:
\_logic_net: (rs1_ext), line:32, parent:amo_unit
|vpiName:rs1_ext
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.genblk1.amo_unit.rs1_ext
|vpiNetType:36
|vpiNet:
\_logic_net: (rs2_ext), line:33, parent:amo_unit
|vpiName:rs2_ext
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.genblk1.amo_unit.rs2_ext
|vpiNetType:36
|vpiParameter:
\_parameter: (ALU_UNIT_WB_ID), line:190
|vpiName:ALU_UNIT_WB_ID
|INT:32
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (BRANCH_PREDICTOR_WAYS), line:159
|vpiName:BRANCH_PREDICTOR_WAYS
|INT:9
|vpiParameter:
\_parameter: (BRANCH_TABLE_ENTRIES), line:160
|vpiName:BRANCH_TABLE_ENTRIES
|INT:4
|vpiParameter:
\_parameter: (BRANCH_UNIT_ID), line:195
|vpiName:BRANCH_UNIT_ID
|INT:8
|vpiParameter:
\_parameter: (BUS_ADDR_H), line:107
|vpiName:BUS_ADDR_H
|INT:1
|vpiParameter:
\_parameter: (BUS_ADDR_L), line:106
|vpiName:BUS_ADDR_L
|INT:0
|vpiParameter:
\_parameter: (BUS_BIT_CHECK), line:108
|vpiName:BUS_BIT_CHECK
|INT:1
|vpiParameter:
\_parameter: (BUS_TYPE), line:89
|vpiName:BUS_TYPE
|INT:5
|vpiParameter:
\_parameter: (COUNTER_W), line:42
|vpiName:COUNTER_W
|INT:33
|vpiParameter:
\_parameter: (CPU_ID), line:38
|vpiName:CPU_ID
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_ADDR_WIDTH), line:113
|vpiName:C_M_AXI_ADDR_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_DATA_WIDTH), line:114
|vpiName:C_M_AXI_DATA_WIDTH
|INT:1
|vpiParameter:
\_parameter: (DCACHE_LINES), line:133
|vpiName:DCACHE_LINES
|INT:-2146435073
|vpiParameter:
\_parameter: (DCACHE_LINE_ADDR_W), line:135
|vpiName:DCACHE_LINE_ADDR_W
|INT:1073741824
|vpiParameter:
\_parameter: (DCACHE_LINE_W), line:136
|vpiName:DCACHE_LINE_W
|INT:1342177279
|vpiParameter:
\_parameter: (DCACHE_SUB_LINE_ADDR_W), line:137
|vpiName:DCACHE_SUB_LINE_ADDR_W
|INT:4
|vpiParameter:
\_parameter: (DCACHE_TAG_W), line:138
|vpiName:DCACHE_TAG_W
|INT:1610612736
|vpiParameter:
\_parameter: (DCACHE_WAYS), line:134
|vpiName:DCACHE_WAYS
|INT:4
|vpiParameter:
\_parameter: (DIV_ALGORITHM), line:67
|vpiName:DIV_ALGORITHM
|INT:0
|vpiParameter:
\_parameter: (DIV_UNIT_WB_ID), line:192
|vpiName:DIV_UNIT_WB_ID
|INT:2
|vpiParameter:
\_parameter: (DTLB_DEPTH), line:152
|vpiName:DTLB_DEPTH
|INT:512
|vpiParameter:
\_parameter: (DTLB_WAYS), line:151
|vpiName:DTLB_WAYS
|INT:32
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (ENABLE_M_MODE), line:34
|vpiName:ENABLE_M_MODE
|INT:1
|vpiParameter:
\_parameter: (ENABLE_S_MODE), line:36
|vpiName:ENABLE_S_MODE
|INT:0
|vpiParameter:
\_parameter: (ENABLE_TRACE_INTERFACE), line:172
|vpiName:ENABLE_TRACE_INTERFACE
|INT:2
|vpiParameter:
\_parameter: (FETCH_BUFFER_DEPTH), line:168
|vpiName:FETCH_BUFFER_DEPTH
|INT:512
|vpiParameter:
\_parameter: (FPGA_VENDOR), line:27
|vpiName:FPGA_VENDOR
|STRING:"xilinx"
|vpiParameter:
\_parameter: (GC_UNIT_ID), line:196
|vpiName:GC_UNIT_ID
|INT:4
|vpiParameter:
\_parameter: (ICACHE_LINES), line:121
|vpiName:ICACHE_LINES
|INT:2
|vpiParameter:
\_parameter: (ICACHE_LINE_ADDR_W), line:123
|vpiName:ICACHE_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_LINE_W), line:124
|vpiName:ICACHE_LINE_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_SUB_LINE_ADDR_W), line:125
|vpiName:ICACHE_SUB_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_TAG_W), line:126
|vpiName:ICACHE_TAG_W
|INT:-2147483648
|vpiParameter:
\_parameter: (ICACHE_WAYS), line:122
|vpiName:ICACHE_WAYS
|INT:1
|vpiParameter:
\_parameter: (ITLB_DEPTH), line:146
|vpiName:ITLB_DEPTH
|INT:32
|vpiParameter:
\_parameter: (ITLB_WAYS), line:145
|vpiName:ITLB_WAYS
|INT:4
|vpiParameter:
\_parameter: (L1_CONNECTIONS), line:177
|vpiName:L1_CONNECTIONS
|INT:9
|vpiParameter:
\_parameter: (L1_DCACHE_ID), line:178
|vpiName:L1_DCACHE_ID
|INT:4
|vpiParameter:
\_parameter: (L1_DMMU_ID), line:179
|vpiName:L1_DMMU_ID
|INT:2
|vpiParameter:
\_parameter: (L1_ICACHE_ID), line:180
|vpiName:L1_ICACHE_ID
|INT:19
|vpiParameter:
\_parameter: (L1_IMMU_ID), line:181
|vpiName:L1_IMMU_ID
|INT:0
|vpiParameter:
\_parameter: (LS_UNIT_WB_ID), line:191
|vpiName:LS_UNIT_WB_ID
|INT:1
|vpiParameter:
\_parameter: (MAX_INFLIGHT_COUNT), line:167
|vpiName:MAX_INFLIGHT_COUNT
|INT:19
|vpiParameter:
\_parameter: (MEMORY_ADDR_H), line:103
|vpiName:MEMORY_ADDR_H
|INT:12
|vpiParameter:
\_parameter: (MEMORY_ADDR_L), line:102
|vpiName:MEMORY_ADDR_L
|INT:11
|vpiParameter:
\_parameter: (MEMORY_BIT_CHECK), line:104
|vpiName:MEMORY_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (MUL_UNIT_WB_ID), line:193
|vpiName:MUL_UNIT_WB_ID
|INT:512
|vpiParameter:
\_parameter: (NUM_UNITS), line:188
|vpiName:NUM_UNITS
|INT:2
|vpiParameter:
\_parameter: (NUM_WB_UNITS), line:186
|vpiName:NUM_WB_UNITS
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (RAS_DEPTH), line:161
|vpiName:RAS_DEPTH
|INT:2
|vpiParameter:
\_parameter: (RESET_VEC), line:39
|vpiName:RESET_VEC
|INT:-2147483648
|vpiParameter:
\_parameter: (SCRATCH_ADDR_H), line:99
|vpiName:SCRATCH_ADDR_H
|INT:9
|vpiParameter:
\_parameter: (SCRATCH_ADDR_L), line:98
|vpiName:SCRATCH_ADDR_L
|INT:8
|vpiParameter:
\_parameter: (SCRATCH_BIT_CHECK), line:100
|vpiName:SCRATCH_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (USE_AMO), line:70
|vpiName:USE_AMO
|INT:1
|vpiParameter:
\_parameter: (USE_BRANCH_PREDICTOR), line:158
|vpiName:USE_BRANCH_PREDICTOR
|INT:2
|vpiParameter:
\_parameter: (USE_BUS), line:88
|vpiName:USE_BUS
|INT:4
|vpiParameter:
\_parameter: (USE_DCACHE), line:92
|vpiName:USE_DCACHE
|INT:6
|vpiParameter:
\_parameter: (USE_DIV), line:49
|vpiName:USE_DIV
|INT:1
|vpiParameter:
\_parameter: (USE_DTAG_INVALIDATIONS), line:140
|vpiName:USE_DTAG_INVALIDATIONS
|INT:1879048191
|vpiParameter:
\_parameter: (USE_D_SCRATCH_MEM), line:79
|vpiName:USE_D_SCRATCH_MEM
|INT:3
|vpiParameter:
\_parameter: (USE_ICACHE), line:93
|vpiName:USE_ICACHE
|INT:7
|vpiParameter:
\_parameter: (USE_I_SCRATCH_MEM), line:78
|vpiName:USE_I_SCRATCH_MEM
|INT:2
|vpiParameter:
\_parameter: (USE_MUL), line:48
|vpiName:USE_MUL
|INT:1
|vpiParameter:
\_parameter: (WB_UNITS_WIDTH), line:187
|vpiName:WB_UNITS_WIDTH
|INT:32
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiParameter:
\_parameter: (ALU_UNIT_WB_ID), line:190
|vpiName:ALU_UNIT_WB_ID
|INT:32
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (BRANCH_PREDICTOR_WAYS), line:159
|vpiName:BRANCH_PREDICTOR_WAYS
|INT:9
|vpiParameter:
\_parameter: (BRANCH_TABLE_ENTRIES), line:160
|vpiName:BRANCH_TABLE_ENTRIES
|INT:4
|vpiParameter:
\_parameter: (BRANCH_UNIT_ID), line:195
|vpiName:BRANCH_UNIT_ID
|INT:8
|vpiParameter:
\_parameter: (BUS_ADDR_H), line:107
|vpiName:BUS_ADDR_H
|INT:1
|vpiParameter:
\_parameter: (BUS_ADDR_L), line:106
|vpiName:BUS_ADDR_L
|INT:0
|vpiParameter:
\_parameter: (BUS_BIT_CHECK), line:108
|vpiName:BUS_BIT_CHECK
|INT:1
|vpiParameter:
\_parameter: (BUS_TYPE), line:89
|vpiName:BUS_TYPE
|INT:5
|vpiParameter:
\_parameter: (COUNTER_W), line:42
|vpiName:COUNTER_W
|INT:33
|vpiParameter:
\_parameter: (CPU_ID), line:38
|vpiName:CPU_ID
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_ADDR_WIDTH), line:113
|vpiName:C_M_AXI_ADDR_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_DATA_WIDTH), line:114
|vpiName:C_M_AXI_DATA_WIDTH
|INT:1
|vpiParameter:
\_parameter: (DCACHE_LINES), line:133
|vpiName:DCACHE_LINES
|INT:-2146435073
|vpiParameter:
\_parameter: (DCACHE_LINE_ADDR_W), line:135
|vpiName:DCACHE_LINE_ADDR_W
|INT:1073741824
|vpiParameter:
\_parameter: (DCACHE_LINE_W), line:136
|vpiName:DCACHE_LINE_W
|INT:1342177279
|vpiParameter:
\_parameter: (DCACHE_SUB_LINE_ADDR_W), line:137
|vpiName:DCACHE_SUB_LINE_ADDR_W
|INT:4
|vpiParameter:
\_parameter: (DCACHE_TAG_W), line:138
|vpiName:DCACHE_TAG_W
|INT:1610612736
|vpiParameter:
\_parameter: (DCACHE_WAYS), line:134
|vpiName:DCACHE_WAYS
|INT:4
|vpiParameter:
\_parameter: (DIV_ALGORITHM), line:67
|vpiName:DIV_ALGORITHM
|INT:0
|vpiParameter:
\_parameter: (DIV_UNIT_WB_ID), line:192
|vpiName:DIV_UNIT_WB_ID
|INT:2
|vpiParameter:
\_parameter: (DTLB_DEPTH), line:152
|vpiName:DTLB_DEPTH
|INT:512
|vpiParameter:
\_parameter: (DTLB_WAYS), line:151
|vpiName:DTLB_WAYS
|INT:32
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (ENABLE_M_MODE), line:34
|vpiName:ENABLE_M_MODE
|INT:1
|vpiParameter:
\_parameter: (ENABLE_S_MODE), line:36
|vpiName:ENABLE_S_MODE
|INT:0
|vpiParameter:
\_parameter: (ENABLE_TRACE_INTERFACE), line:172
|vpiName:ENABLE_TRACE_INTERFACE
|INT:2
|vpiParameter:
\_parameter: (FETCH_BUFFER_DEPTH), line:168
|vpiName:FETCH_BUFFER_DEPTH
|INT:512
|vpiParameter:
\_parameter: (FPGA_VENDOR), line:27
|vpiName:FPGA_VENDOR
|STRING:"xilinx"
|vpiParameter:
\_parameter: (GC_UNIT_ID), line:196
|vpiName:GC_UNIT_ID
|INT:4
|vpiParameter:
\_parameter: (ICACHE_LINES), line:121
|vpiName:ICACHE_LINES
|INT:2
|vpiParameter:
\_parameter: (ICACHE_LINE_ADDR_W), line:123
|vpiName:ICACHE_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_LINE_W), line:124
|vpiName:ICACHE_LINE_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_SUB_LINE_ADDR_W), line:125
|vpiName:ICACHE_SUB_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_TAG_W), line:126
|vpiName:ICACHE_TAG_W
|INT:-2147483648
|vpiParameter:
\_parameter: (ICACHE_WAYS), line:122
|vpiName:ICACHE_WAYS
|INT:1
|vpiParameter:
\_parameter: (ITLB_DEPTH), line:146
|vpiName:ITLB_DEPTH
|INT:32
|vpiParameter:
\_parameter: (ITLB_WAYS), line:145
|vpiName:ITLB_WAYS
|INT:4
|vpiParameter:
\_parameter: (L1_CONNECTIONS), line:177
|vpiName:L1_CONNECTIONS
|INT:9
|vpiParameter:
\_parameter: (L1_DCACHE_ID), line:178
|vpiName:L1_DCACHE_ID
|INT:4
|vpiParameter:
\_parameter: (L1_DMMU_ID), line:179
|vpiName:L1_DMMU_ID
|INT:2
|vpiParameter:
\_parameter: (L1_ICACHE_ID), line:180
|vpiName:L1_ICACHE_ID
|INT:19
|vpiParameter:
\_parameter: (L1_IMMU_ID), line:181
|vpiName:L1_IMMU_ID
|INT:0
|vpiParameter:
\_parameter: (LS_UNIT_WB_ID), line:191
|vpiName:LS_UNIT_WB_ID
|INT:1
|vpiParameter:
\_parameter: (MAX_INFLIGHT_COUNT), line:167
|vpiName:MAX_INFLIGHT_COUNT
|INT:19
|vpiParameter:
\_parameter: (MEMORY_ADDR_H), line:103
|vpiName:MEMORY_ADDR_H
|INT:12
|vpiParameter:
\_parameter: (MEMORY_ADDR_L), line:102
|vpiName:MEMORY_ADDR_L
|INT:11
|vpiParameter:
\_parameter: (MEMORY_BIT_CHECK), line:104
|vpiName:MEMORY_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (MUL_UNIT_WB_ID), line:193
|vpiName:MUL_UNIT_WB_ID
|INT:512
|vpiParameter:
\_parameter: (NUM_UNITS), line:188
|vpiName:NUM_UNITS
|INT:2
|vpiParameter:
\_parameter: (NUM_WB_UNITS), line:186
|vpiName:NUM_WB_UNITS
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (RAS_DEPTH), line:161
|vpiName:RAS_DEPTH
|INT:2
|vpiParameter:
\_parameter: (RESET_VEC), line:39
|vpiName:RESET_VEC
|INT:-2147483648
|vpiParameter:
\_parameter: (SCRATCH_ADDR_H), line:99
|vpiName:SCRATCH_ADDR_H
|INT:9
|vpiParameter:
\_parameter: (SCRATCH_ADDR_L), line:98
|vpiName:SCRATCH_ADDR_L
|INT:8
|vpiParameter:
\_parameter: (SCRATCH_BIT_CHECK), line:100
|vpiName:SCRATCH_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (USE_AMO), line:70
|vpiName:USE_AMO
|INT:1
|vpiParameter:
\_parameter: (USE_BRANCH_PREDICTOR), line:158
|vpiName:USE_BRANCH_PREDICTOR
|INT:2
|vpiParameter:
\_parameter: (USE_BUS), line:88
|vpiName:USE_BUS
|INT:4
|vpiParameter:
\_parameter: (USE_DCACHE), line:92
|vpiName:USE_DCACHE
|INT:6
|vpiParameter:
\_parameter: (USE_DIV), line:49
|vpiName:USE_DIV
|INT:1
|vpiParameter:
\_parameter: (USE_DTAG_INVALIDATIONS), line:140
|vpiName:USE_DTAG_INVALIDATIONS
|INT:1879048191
|vpiParameter:
\_parameter: (USE_D_SCRATCH_MEM), line:79
|vpiName:USE_D_SCRATCH_MEM
|INT:3
|vpiParameter:
\_parameter: (USE_ICACHE), line:93
|vpiName:USE_ICACHE
|INT:7
|vpiParameter:
\_parameter: (USE_I_SCRATCH_MEM), line:78
|vpiName:USE_I_SCRATCH_MEM
|INT:2
|vpiParameter:
\_parameter: (USE_MUL), line:48
|vpiName:USE_MUL
|INT:1
|vpiParameter:
\_parameter: (WB_UNITS_WIDTH), line:187
|vpiName:WB_UNITS_WIDTH
|INT:32
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiNet:
\_logic_net: (clk), line:27, parent:data_cache
|vpiNet:
\_logic_net: (rst), line:28, parent:data_cache
|vpiNet:
\_logic_net: (dcache_on), line:29, parent:data_cache
|vpiNet:
\_logic_net: (sc_complete), line:32, parent:data_cache
|vpiNet:
\_logic_net: (sc_success), line:33, parent:data_cache
|vpiNet:
\_logic_net: (clear_reservation), line:34, parent:data_cache
|vpiNet:
\_logic_net: (ls_inputs), line:36, parent:data_cache
|vpiNet:
\_logic_net: (data_out), line:37, parent:data_cache
|vpiNet:
\_logic_net: (amo), line:39, parent:data_cache
|vpiName:amo
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.amo
|vpiNet:
\_logic_net: (data_bank_addr_a), line:45, parent:data_cache
|vpiNet:
\_logic_net: (data_bank_addr_b), line:46, parent:data_cache
|vpiNet:
\_logic_net: (tag_hit), line:48, parent:data_cache
|vpiNet:
\_logic_net: (tag_hit_way), line:49, parent:data_cache
|vpiNet:
\_logic_net: (tag_hit_way_int), line:51, parent:data_cache
|vpiName:tag_hit_way_int
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.tag_hit_way_int
|vpiNetType:36
|vpiRange:
\_range: , line:51
|vpiLeftRange:
\_constant: , line:51
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:51
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (tag_update), line:53, parent:data_cache
|vpiName:tag_update
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.tag_update
|vpiNetType:36
|vpiNet:
\_logic_net: (tag_update_way), line:54, parent:data_cache
|vpiName:tag_update_way
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.tag_update_way
|vpiNetType:36
|vpiRange:
\_range: , line:54
|vpiLeftRange:
\_constant: , line:54
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiRightRange:
\_constant: , line:54
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (replacement_way), line:55, parent:data_cache
|vpiName:replacement_way
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.replacement_way
|vpiNetType:36
|vpiRange:
\_range: , line:55
|vpiLeftRange:
\_constant: , line:55
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiRightRange:
\_constant: , line:55
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (replacement_way_int), line:57, parent:data_cache
|vpiName:replacement_way_int
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.replacement_way_int
|vpiNetType:36
|vpiRange:
\_range: , line:57
|vpiLeftRange:
\_constant: , line:57
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:57
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (tag_update_way_int), line:58, parent:data_cache
|vpiName:tag_update_way_int
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.tag_update_way_int
|vpiNetType:36
|vpiRange:
\_range: , line:58
|vpiLeftRange:
\_constant: , line:58
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:58
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (word_count), line:60, parent:data_cache
|vpiName:word_count
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.word_count
|vpiNetType:36
|vpiRange:
\_range: , line:60
|vpiLeftRange:
\_constant: , line:60
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiRightRange:
\_constant: , line:60
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (sc_write_index), line:61, parent:data_cache
|vpiName:sc_write_index
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.sc_write_index
|vpiNetType:36
|vpiRange:
\_range: , line:61
|vpiLeftRange:
\_constant: , line:61
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiRightRange:
\_constant: , line:61
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (update_word_index), line:62, parent:data_cache
|vpiName:update_word_index
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.update_word_index
|vpiNetType:36
|vpiRange:
\_range: , line:62
|vpiLeftRange:
\_constant: , line:62
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiRightRange:
\_constant: , line:62
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (line_complete), line:64, parent:data_cache
|vpiName:line_complete
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.line_complete
|vpiNetType:36
|vpiNet:
\_logic_net: (reservation), line:65, parent:data_cache
|vpiName:reservation
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.reservation
|vpiNetType:36
|vpiNet:
\_logic_net: (stage2_addr), line:67, parent:data_cache
|vpiNet:
\_logic_net: (stage2_load), line:68, parent:data_cache
|vpiName:stage2_load
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.stage2_load
|vpiNetType:36
|vpiNet:
\_logic_net: (stage2_store), line:69, parent:data_cache
|vpiName:stage2_store
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.stage2_store
|vpiNetType:36
|vpiNet:
\_logic_net: (stage2_be), line:70, parent:data_cache
|vpiName:stage2_be
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.stage2_be
|vpiNetType:36
|vpiRange:
\_range: , line:70
|vpiLeftRange:
\_constant: , line:70
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiRightRange:
\_constant: , line:70
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (stage2_fn3), line:71, parent:data_cache
|vpiName:stage2_fn3
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.stage2_fn3
|vpiNetType:36
|vpiRange:
\_range: , line:71
|vpiLeftRange:
\_constant: , line:71
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiRightRange:
\_constant: , line:71
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (stage2_data), line:72, parent:data_cache
|vpiNet:
\_logic_net: (dbank_data_out), line:76, parent:data_cache
|vpiNet:
\_logic_net: (hit_data), line:77, parent:data_cache
|vpiName:hit_data
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.hit_data
|vpiNetType:36
|vpiRange:
\_range: , line:77
|vpiLeftRange:
\_constant: , line:77
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:77
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (miss_data), line:78, parent:data_cache
|vpiName:miss_data
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.miss_data
|vpiNetType:36
|vpiRange:
\_range: , line:78
|vpiLeftRange:
\_constant: , line:78
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:78
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (new_line_data), line:79, parent:data_cache
|vpiNet:
\_logic_net: (amo_result), line:80, parent:data_cache
|vpiName:amo_result
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.amo_result
|vpiNetType:36
|vpiRange:
\_range: , line:80
|vpiLeftRange:
\_constant: , line:80
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:80
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (amo_rs2), line:81, parent:data_cache
|vpiName:amo_rs2
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.amo_rs2
|vpiNetType:36
|vpiRange:
\_range: , line:81
|vpiLeftRange:
\_constant: , line:81
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:81
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (write_hit_be), line:83, parent:data_cache
|vpiNet:
\_logic_net: (second_cycle), line:85, parent:data_cache
|vpiNet:
\_logic_net: (request), line:87, parent:data_cache
|vpiName:request
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.request
|vpiNetType:36
|vpiNet:
\_logic_net: (is_target_word), line:89, parent:data_cache
|vpiName:is_target_word
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.is_target_word
|vpiNetType:36
|vpiNet:
\_logic_net: (hit_allowed), line:91, parent:data_cache
|vpiName:hit_allowed
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.hit_allowed
|vpiNetType:36
|vpiNet:
\_logic_net: (read_hit_allowed), line:92, parent:data_cache
|vpiName:read_hit_allowed
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.read_hit_allowed
|vpiNetType:36
|vpiNet:
\_logic_net: (read_hit_data_valid), line:93, parent:data_cache
|vpiName:read_hit_data_valid
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.read_hit_data_valid
|vpiNetType:36
|vpiNet:
\_logic_net: (address_range_valid), line:95, parent:data_cache
|vpiName:address_range_valid
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.address_range_valid
|vpiNetType:36
|vpiNet:
\_logic_net: (idle), line:97, parent:data_cache
|vpiName:idle
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.idle
|vpiNetType:36
|vpiNet:
\_logic_net: (read_miss_complete), line:98, parent:data_cache
|vpiName:read_miss_complete
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.read_miss_complete
|vpiNetType:36
|vpiNet:
\_logic_net: (store_complete), line:100, parent:data_cache
|vpiName:store_complete
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.store_complete
|vpiNetType:36
|vpiNet:
\_logic_net: (stage2_amo_with_load), line:178, parent:data_cache
|vpiName:stage2_amo_with_load
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.stage2_amo_with_load
|vpiNetType:36
|vpiNet:
\_logic_net: (l1_request), line:30, parent:data_cache
|vpiName:l1_request
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.l1_request
|vpiNet:
\_logic_net: (l1_response), line:31, parent:data_cache
|vpiName:l1_response
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.l1_response
|vpiNet:
\_logic_net: (ls), line:40, parent:data_cache
|vpiName:ls
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.ls
|vpiVariables:
\_struct_var: (stage2_amo), line:74, parent:data_cache
|vpiName:stage2_amo
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.stage2_amo
|vpiTypespec:
\_struct_typespec: (amo_details_t), line:362
|vpiVariables:
\_struct_var: (amo_alu_inputs), line:101, parent:data_cache
|vpiName:amo_alu_inputs
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.genblk3.data_cache.amo_alu_inputs
|vpiTypespec:
\_struct_typespec: (amo_alu_inputs_t), line:356
|vpiParameter:
\_parameter: (ALU_UNIT_WB_ID), line:190
|vpiName:ALU_UNIT_WB_ID
|INT:32
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (BRANCH_PREDICTOR_WAYS), line:159
|vpiName:BRANCH_PREDICTOR_WAYS
|INT:9
|vpiParameter:
\_parameter: (BRANCH_TABLE_ENTRIES), line:160
|vpiName:BRANCH_TABLE_ENTRIES
|INT:4
|vpiParameter:
\_parameter: (BRANCH_UNIT_ID), line:195
|vpiName:BRANCH_UNIT_ID
|INT:8
|vpiParameter:
\_parameter: (BUS_ADDR_H), line:107
|vpiName:BUS_ADDR_H
|INT:1
|vpiParameter:
\_parameter: (BUS_ADDR_L), line:106
|vpiName:BUS_ADDR_L
|INT:0
|vpiParameter:
\_parameter: (BUS_BIT_CHECK), line:108
|vpiName:BUS_BIT_CHECK
|INT:1
|vpiParameter:
\_parameter: (BUS_TYPE), line:89
|vpiName:BUS_TYPE
|INT:5
|vpiParameter:
\_parameter: (COUNTER_W), line:42
|vpiName:COUNTER_W
|INT:33
|vpiParameter:
\_parameter: (CPU_ID), line:38
|vpiName:CPU_ID
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_ADDR_WIDTH), line:113
|vpiName:C_M_AXI_ADDR_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_DATA_WIDTH), line:114
|vpiName:C_M_AXI_DATA_WIDTH
|INT:1
|vpiParameter:
\_parameter: (DCACHE_LINES), line:133
|vpiName:DCACHE_LINES
|INT:-2146435073
|vpiParameter:
\_parameter: (DCACHE_LINE_ADDR_W), line:135
|vpiName:DCACHE_LINE_ADDR_W
|INT:1073741824
|vpiParameter:
\_parameter: (DCACHE_LINE_W), line:136
|vpiName:DCACHE_LINE_W
|INT:1342177279
|vpiParameter:
\_parameter: (DCACHE_SIZE_IN_WORDS), line:43
|vpiName:DCACHE_SIZE_IN_WORDS
|INT:-1
|vpiParameter:
\_parameter: (DCACHE_SUB_LINE_ADDR_W), line:137
|vpiName:DCACHE_SUB_LINE_ADDR_W
|INT:4
|vpiParameter:
\_parameter: (DCACHE_TAG_W), line:138
|vpiName:DCACHE_TAG_W
|INT:1610612736
|vpiParameter:
\_parameter: (DCACHE_WAYS), line:134
|vpiName:DCACHE_WAYS
|INT:4
|vpiParameter:
\_parameter: (DIV_ALGORITHM), line:67
|vpiName:DIV_ALGORITHM
|INT:0
|vpiParameter:
\_parameter: (DIV_UNIT_WB_ID), line:192
|vpiName:DIV_UNIT_WB_ID
|INT:2
|vpiParameter:
\_parameter: (DTLB_DEPTH), line:152
|vpiName:DTLB_DEPTH
|INT:512
|vpiParameter:
\_parameter: (DTLB_WAYS), line:151
|vpiName:DTLB_WAYS
|INT:32
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (ENABLE_M_MODE), line:34
|vpiName:ENABLE_M_MODE
|INT:1
|vpiParameter:
\_parameter: (ENABLE_S_MODE), line:36
|vpiName:ENABLE_S_MODE
|INT:0
|vpiParameter:
\_parameter: (ENABLE_TRACE_INTERFACE), line:172
|vpiName:ENABLE_TRACE_INTERFACE
|INT:2
|vpiParameter:
\_parameter: (FETCH_BUFFER_DEPTH), line:168
|vpiName:FETCH_BUFFER_DEPTH
|INT:512
|vpiParameter:
\_parameter: (FPGA_VENDOR), line:27
|vpiName:FPGA_VENDOR
|STRING:"xilinx"
|vpiParameter:
\_parameter: (GC_UNIT_ID), line:196
|vpiName:GC_UNIT_ID
|INT:4
|vpiParameter:
\_parameter: (ICACHE_LINES), line:121
|vpiName:ICACHE_LINES
|INT:2
|vpiParameter:
\_parameter: (ICACHE_LINE_ADDR_W), line:123
|vpiName:ICACHE_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_LINE_W), line:124
|vpiName:ICACHE_LINE_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_SUB_LINE_ADDR_W), line:125
|vpiName:ICACHE_SUB_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_TAG_W), line:126
|vpiName:ICACHE_TAG_W
|INT:-2147483648
|vpiParameter:
\_parameter: (ICACHE_WAYS), line:122
|vpiName:ICACHE_WAYS
|INT:1
|vpiParameter:
\_parameter: (ITLB_DEPTH), line:146
|vpiName:ITLB_DEPTH
|INT:32
|vpiParameter:
\_parameter: (ITLB_WAYS), line:145
|vpiName:ITLB_WAYS
|INT:4
|vpiParameter:
\_parameter: (L1_CONNECTIONS), line:177
|vpiName:L1_CONNECTIONS
|INT:9
|vpiParameter:
\_parameter: (L1_DCACHE_ID), line:178
|vpiName:L1_DCACHE_ID
|INT:4
|vpiParameter:
\_parameter: (L1_DMMU_ID), line:179
|vpiName:L1_DMMU_ID
|INT:2
|vpiParameter:
\_parameter: (L1_ICACHE_ID), line:180
|vpiName:L1_ICACHE_ID
|INT:19
|vpiParameter:
\_parameter: (L1_IMMU_ID), line:181
|vpiName:L1_IMMU_ID
|INT:0
|vpiParameter:
\_parameter: (LS_UNIT_WB_ID), line:191
|vpiName:LS_UNIT_WB_ID
|INT:1
|vpiParameter:
\_parameter: (MAX_INFLIGHT_COUNT), line:167
|vpiName:MAX_INFLIGHT_COUNT
|INT:19
|vpiParameter:
\_parameter: (MEMORY_ADDR_H), line:103
|vpiName:MEMORY_ADDR_H
|INT:12
|vpiParameter:
\_parameter: (MEMORY_ADDR_L), line:102
|vpiName:MEMORY_ADDR_L
|INT:11
|vpiParameter:
\_parameter: (MEMORY_BIT_CHECK), line:104
|vpiName:MEMORY_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (MUL_UNIT_WB_ID), line:193
|vpiName:MUL_UNIT_WB_ID
|INT:512
|vpiParameter:
\_parameter: (NUM_UNITS), line:188
|vpiName:NUM_UNITS
|INT:2
|vpiParameter:
\_parameter: (NUM_WB_UNITS), line:186
|vpiName:NUM_WB_UNITS
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (RAS_DEPTH), line:161
|vpiName:RAS_DEPTH
|INT:2
|vpiParameter:
\_parameter: (RESET_VEC), line:39
|vpiName:RESET_VEC
|INT:-2147483648
|vpiParameter:
\_parameter: (SCRATCH_ADDR_H), line:99
|vpiName:SCRATCH_ADDR_H
|INT:9
|vpiParameter:
\_parameter: (SCRATCH_ADDR_L), line:98
|vpiName:SCRATCH_ADDR_L
|INT:8
|vpiParameter:
\_parameter: (SCRATCH_BIT_CHECK), line:100
|vpiName:SCRATCH_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (USE_AMO), line:70
|vpiName:USE_AMO
|INT:1
|vpiParameter:
\_parameter: (USE_BRANCH_PREDICTOR), line:158
|vpiName:USE_BRANCH_PREDICTOR
|INT:2
|vpiParameter:
\_parameter: (USE_BUS), line:88
|vpiName:USE_BUS
|INT:4
|vpiParameter:
\_parameter: (USE_DCACHE), line:92
|vpiName:USE_DCACHE
|INT:6
|vpiParameter:
\_parameter: (USE_DIV), line:49
|vpiName:USE_DIV
|INT:1
|vpiParameter:
\_parameter: (USE_DTAG_INVALIDATIONS), line:140
|vpiName:USE_DTAG_INVALIDATIONS
|INT:1879048191
|vpiParameter:
\_parameter: (USE_D_SCRATCH_MEM), line:79
|vpiName:USE_D_SCRATCH_MEM
|INT:3
|vpiParameter:
\_parameter: (USE_ICACHE), line:93
|vpiName:USE_ICACHE
|INT:7
|vpiParameter:
\_parameter: (USE_I_SCRATCH_MEM), line:78
|vpiName:USE_I_SCRATCH_MEM
|INT:2
|vpiParameter:
\_parameter: (USE_MUL), line:48
|vpiName:USE_MUL
|INT:1
|vpiParameter:
\_parameter: (WB_UNITS_WIDTH), line:187
|vpiName:WB_UNITS_WIDTH
|INT:32
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiParameter:
\_parameter: (ALU_UNIT_WB_ID), line:190
|vpiName:ALU_UNIT_WB_ID
|INT:32
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (BRANCH_PREDICTOR_WAYS), line:159
|vpiName:BRANCH_PREDICTOR_WAYS
|INT:9
|vpiParameter:
\_parameter: (BRANCH_TABLE_ENTRIES), line:160
|vpiName:BRANCH_TABLE_ENTRIES
|INT:4
|vpiParameter:
\_parameter: (BRANCH_UNIT_ID), line:195
|vpiName:BRANCH_UNIT_ID
|INT:8
|vpiParameter:
\_parameter: (BUS_ADDR_H), line:107
|vpiName:BUS_ADDR_H
|INT:1
|vpiParameter:
\_parameter: (BUS_ADDR_L), line:106
|vpiName:BUS_ADDR_L
|INT:0
|vpiParameter:
\_parameter: (BUS_BIT_CHECK), line:108
|vpiName:BUS_BIT_CHECK
|INT:1
|vpiParameter:
\_parameter: (BUS_TYPE), line:89
|vpiName:BUS_TYPE
|INT:5
|vpiParameter:
\_parameter: (COUNTER_W), line:42
|vpiName:COUNTER_W
|INT:33
|vpiParameter:
\_parameter: (CPU_ID), line:38
|vpiName:CPU_ID
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_ADDR_WIDTH), line:113
|vpiName:C_M_AXI_ADDR_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_DATA_WIDTH), line:114
|vpiName:C_M_AXI_DATA_WIDTH
|INT:1
|vpiParameter:
\_parameter: (DCACHE_LINES), line:133
|vpiName:DCACHE_LINES
|INT:-2146435073
|vpiParameter:
\_parameter: (DCACHE_LINE_ADDR_W), line:135
|vpiName:DCACHE_LINE_ADDR_W
|INT:1073741824
|vpiParameter:
\_parameter: (DCACHE_LINE_W), line:136
|vpiName:DCACHE_LINE_W
|INT:1342177279
|vpiParameter:
\_parameter: (DCACHE_SUB_LINE_ADDR_W), line:137
|vpiName:DCACHE_SUB_LINE_ADDR_W
|INT:4
|vpiParameter:
\_parameter: (DCACHE_TAG_W), line:138
|vpiName:DCACHE_TAG_W
|INT:1610612736
|vpiParameter:
\_parameter: (DCACHE_WAYS), line:134
|vpiName:DCACHE_WAYS
|INT:4
|vpiParameter:
\_parameter: (DIV_ALGORITHM), line:67
|vpiName:DIV_ALGORITHM
|INT:0
|vpiParameter:
\_parameter: (DIV_UNIT_WB_ID), line:192
|vpiName:DIV_UNIT_WB_ID
|INT:2
|vpiParameter:
\_parameter: (DTLB_DEPTH), line:152
|vpiName:DTLB_DEPTH
|INT:512
|vpiParameter:
\_parameter: (DTLB_WAYS), line:151
|vpiName:DTLB_WAYS
|INT:32
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (ENABLE_M_MODE), line:34
|vpiName:ENABLE_M_MODE
|INT:1
|vpiParameter:
\_parameter: (ENABLE_S_MODE), line:36
|vpiName:ENABLE_S_MODE
|INT:0
|vpiParameter:
\_parameter: (ENABLE_TRACE_INTERFACE), line:172
|vpiName:ENABLE_TRACE_INTERFACE
|INT:2
|vpiParameter:
\_parameter: (FETCH_BUFFER_DEPTH), line:168
|vpiName:FETCH_BUFFER_DEPTH
|INT:512
|vpiParameter:
\_parameter: (FPGA_VENDOR), line:27
|vpiName:FPGA_VENDOR
|STRING:"xilinx"
|vpiParameter:
\_parameter: (GC_UNIT_ID), line:196
|vpiName:GC_UNIT_ID
|INT:4
|vpiParameter:
\_parameter: (ICACHE_LINES), line:121
|vpiName:ICACHE_LINES
|INT:2
|vpiParameter:
\_parameter: (ICACHE_LINE_ADDR_W), line:123
|vpiName:ICACHE_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_LINE_W), line:124
|vpiName:ICACHE_LINE_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_SUB_LINE_ADDR_W), line:125
|vpiName:ICACHE_SUB_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_TAG_W), line:126
|vpiName:ICACHE_TAG_W
|INT:-2147483648
|vpiParameter:
\_parameter: (ICACHE_WAYS), line:122
|vpiName:ICACHE_WAYS
|INT:1
|vpiParameter:
\_parameter: (ITLB_DEPTH), line:146
|vpiName:ITLB_DEPTH
|INT:32
|vpiParameter:
\_parameter: (ITLB_WAYS), line:145
|vpiName:ITLB_WAYS
|INT:4
|vpiParameter:
\_parameter: (L1_CONNECTIONS), line:177
|vpiName:L1_CONNECTIONS
|INT:9
|vpiParameter:
\_parameter: (L1_DCACHE_ID), line:178
|vpiName:L1_DCACHE_ID
|INT:4
|vpiParameter:
\_parameter: (L1_DMMU_ID), line:179
|vpiName:L1_DMMU_ID
|INT:2
|vpiParameter:
\_parameter: (L1_ICACHE_ID), line:180
|vpiName:L1_ICACHE_ID
|INT:19
|vpiParameter:
\_parameter: (L1_IMMU_ID), line:181
|vpiName:L1_IMMU_ID
|INT:0
|vpiParameter:
\_parameter: (LS_UNIT_WB_ID), line:191
|vpiName:LS_UNIT_WB_ID
|INT:1
|vpiParameter:
\_parameter: (MAX_INFLIGHT_COUNT), line:167
|vpiName:MAX_INFLIGHT_COUNT
|INT:19
|vpiParameter:
\_parameter: (MEMORY_ADDR_H), line:103
|vpiName:MEMORY_ADDR_H
|INT:12
|vpiParameter:
\_parameter: (MEMORY_ADDR_L), line:102
|vpiName:MEMORY_ADDR_L
|INT:11
|vpiParameter:
\_parameter: (MEMORY_BIT_CHECK), line:104
|vpiName:MEMORY_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (MUL_UNIT_WB_ID), line:193
|vpiName:MUL_UNIT_WB_ID
|INT:512
|vpiParameter:
\_parameter: (NUM_UNITS), line:188
|vpiName:NUM_UNITS
|INT:2
|vpiParameter:
\_parameter: (NUM_WB_UNITS), line:186
|vpiName:NUM_WB_UNITS
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (RAS_DEPTH), line:161
|vpiName:RAS_DEPTH
|INT:2
|vpiParameter:
\_parameter: (RESET_VEC), line:39
|vpiName:RESET_VEC
|INT:-2147483648
|vpiParameter:
\_parameter: (SCRATCH_ADDR_H), line:99
|vpiName:SCRATCH_ADDR_H
|INT:9
|vpiParameter:
\_parameter: (SCRATCH_ADDR_L), line:98
|vpiName:SCRATCH_ADDR_L
|INT:8
|vpiParameter:
\_parameter: (SCRATCH_BIT_CHECK), line:100
|vpiName:SCRATCH_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (USE_AMO), line:70
|vpiName:USE_AMO
|INT:1
|vpiParameter:
\_parameter: (USE_BRANCH_PREDICTOR), line:158
|vpiName:USE_BRANCH_PREDICTOR
|INT:2
|vpiParameter:
\_parameter: (USE_BUS), line:88
|vpiName:USE_BUS
|INT:4
|vpiParameter:
\_parameter: (USE_DCACHE), line:92
|vpiName:USE_DCACHE
|INT:6
|vpiParameter:
\_parameter: (USE_DIV), line:49
|vpiName:USE_DIV
|INT:1
|vpiParameter:
\_parameter: (USE_DTAG_INVALIDATIONS), line:140
|vpiName:USE_DTAG_INVALIDATIONS
|INT:1879048191
|vpiParameter:
\_parameter: (USE_D_SCRATCH_MEM), line:79
|vpiName:USE_D_SCRATCH_MEM
|INT:3
|vpiParameter:
\_parameter: (USE_ICACHE), line:93
|vpiName:USE_ICACHE
|INT:7
|vpiParameter:
\_parameter: (USE_I_SCRATCH_MEM), line:78
|vpiName:USE_I_SCRATCH_MEM
|INT:2
|vpiParameter:
\_parameter: (USE_MUL), line:48
|vpiName:USE_MUL
|INT:1
|vpiParameter:
\_parameter: (WB_UNITS_WIDTH), line:187
|vpiName:WB_UNITS_WIDTH
|INT:32
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiNet:
\_logic_net: (clk), line:27, parent:load_store_unit_block
|vpiNet:
\_logic_net: (rst), line:28, parent:load_store_unit_block
|vpiNet:
\_logic_net: (ls_inputs), line:29, parent:load_store_unit_block
|vpiNet:
\_logic_net: (dcache_on), line:32, parent:load_store_unit_block
|vpiNet:
\_logic_net: (clear_reservation), line:33, parent:load_store_unit_block
|vpiNet:
\_logic_net: (gc_fetch_flush), line:36, parent:load_store_unit_block
|vpiNet:
\_logic_net: (gc_issue_flush), line:37, parent:load_store_unit_block
|vpiNet:
\_logic_net: (sc_complete), line:41, parent:load_store_unit_block
|vpiNet:
\_logic_net: (sc_success), line:42, parent:load_store_unit_block
|vpiNet:
\_logic_net: (store_done_id), line:51, parent:load_store_unit_block
|vpiNet:
\_logic_net: (store_complete), line:52, parent:load_store_unit_block
|vpiNet:
\_logic_net: (csr_rd), line:56, parent:load_store_unit_block
|vpiNet:
\_logic_net: (csr_id), line:57, parent:load_store_unit_block
|vpiNet:
\_logic_net: (csr_done), line:58, parent:load_store_unit_block
|vpiNet:
\_logic_net: (ls_exception), line:60, parent:load_store_unit_block
|vpiNet:
\_logic_net: (ls_exception_valid), line:61, parent:load_store_unit_block
|vpiNet:
\_logic_net: (wb), line:63, parent:load_store_unit_block
|vpiNet:
\_logic_net: (units_ready), line:81, parent:load_store_unit_block
|vpiName:units_ready
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.units_ready
|vpiNetType:36
|vpiNet:
\_logic_net: (store_ready), line:82, parent:load_store_unit_block
|vpiName:store_ready
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.store_ready
|vpiNetType:36
|vpiNet:
\_logic_net: (issue_request), line:83, parent:load_store_unit_block
|vpiName:issue_request
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.issue_request
|vpiNetType:36
|vpiNet:
\_logic_net: (load_complete), line:84, parent:load_store_unit_block
|vpiName:load_complete
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.load_complete
|vpiNetType:36
|vpiNet:
\_logic_net: (virtual_address), line:86, parent:load_store_unit_block
|vpiName:virtual_address
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.virtual_address
|vpiNetType:36
|vpiRange:
\_range: , line:86
|vpiLeftRange:
\_constant: , line:86
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:86
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (be), line:87, parent:load_store_unit_block
|vpiName:be
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.be
|vpiNetType:36
|vpiRange:
\_range: , line:87
|vpiLeftRange:
\_constant: , line:87
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiRightRange:
\_constant: , line:87
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (unit_muxed_load_data), line:89, parent:load_store_unit_block
|vpiName:unit_muxed_load_data
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.unit_muxed_load_data
|vpiNetType:36
|vpiRange:
\_range: , line:89
|vpiLeftRange:
\_constant: , line:89
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:89
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (aligned_load_data), line:90, parent:load_store_unit_block
|vpiName:aligned_load_data
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.aligned_load_data
|vpiNetType:36
|vpiRange:
\_range: , line:90
|vpiLeftRange:
\_constant: , line:90
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:90
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (final_load_data), line:91, parent:load_store_unit_block
|vpiName:final_load_data
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.final_load_data
|vpiNetType:36
|vpiRange:
\_range: , line:91
|vpiLeftRange:
\_constant: , line:91
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:91
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (stage1_raw_data), line:93, parent:load_store_unit_block
|vpiName:stage1_raw_data
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.stage1_raw_data
|vpiNetType:36
|vpiRange:
\_range: , line:93
|vpiLeftRange:
\_constant: , line:93
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:93
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (unit_ready), line:96, parent:load_store_unit_block
|vpiName:unit_ready
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.unit_ready
|vpiNetType:36
|vpiRange:
\_range: , line:96
|vpiLeftRange:
\_constant: , line:96
|vpiConstType:7
|vpiDecompile:12
|vpiSize:32
|INT:12
|vpiRightRange:
\_constant: , line:96
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (unit_data_valid), line:97, parent:load_store_unit_block
|vpiName:unit_data_valid
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.unit_data_valid
|vpiNetType:36
|vpiRange:
\_range: , line:97
|vpiLeftRange:
\_constant: , line:97
|vpiConstType:7
|vpiDecompile:12
|vpiSize:32
|INT:12
|vpiRightRange:
\_constant: , line:97
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (last_unit), line:98, parent:load_store_unit_block
|vpiName:last_unit
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.last_unit
|vpiNetType:36
|vpiRange:
\_range: , line:98
|vpiLeftRange:
\_constant: , line:98
|vpiConstType:7
|vpiDecompile:12
|vpiSize:32
|INT:12
|vpiRightRange:
\_constant: , line:98
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (current_unit), line:99, parent:load_store_unit_block
|vpiName:current_unit
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.current_unit
|vpiNetType:36
|vpiRange:
\_range: , line:99
|vpiLeftRange:
\_constant: , line:99
|vpiConstType:7
|vpiDecompile:12
|vpiSize:32
|INT:12
|vpiRightRange:
\_constant: , line:99
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (unaligned_addr), line:101, parent:load_store_unit_block
|vpiName:unaligned_addr
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.unaligned_addr
|vpiNetType:36
|vpiNet:
\_logic_net: (sub_unit_address_match), line:102, parent:load_store_unit_block
|vpiName:sub_unit_address_match
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.sub_unit_address_match
|vpiNetType:36
|vpiRange:
\_range: , line:102
|vpiLeftRange:
\_constant: , line:102
|vpiConstType:7
|vpiDecompile:12
|vpiSize:32
|INT:12
|vpiRightRange:
\_constant: , line:102
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (unit_stall), line:104, parent:load_store_unit_block
|vpiName:unit_stall
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.unit_stall
|vpiNetType:36
|vpiNet:
\_logic_net: (exception_complete), line:347, parent:load_store_unit_block
|vpiName:exception_complete
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.exception_complete
|vpiNetType:36
|vpiNet:
\_logic_net: (ls_done), line:348, parent:load_store_unit_block
|vpiName:ls_done
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.ls_done
|vpiNetType:36
|vpiNet:
\_logic_net: (issue), line:30, parent:load_store_unit_block
|vpiName:issue
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.issue
|vpiNet:
\_logic_net: (tlb), line:34, parent:load_store_unit_block
|vpiName:tlb
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.tlb
|vpiNet:
\_logic_net: (l1_request), line:39, parent:load_store_unit_block
|vpiName:l1_request
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.l1_request
|vpiNet:
\_logic_net: (l1_response), line:40, parent:load_store_unit_block
|vpiName:l1_response
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.l1_response
|vpiNet:
\_logic_net: (m_axi), line:44, parent:load_store_unit_block
|vpiName:m_axi
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.m_axi
|vpiNet:
\_logic_net: (m_avalon), line:45, parent:load_store_unit_block
|vpiName:m_avalon
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.m_avalon
|vpiNet:
\_logic_net: (m_wishbone), line:46, parent:load_store_unit_block
|vpiName:m_wishbone
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.m_wishbone
|vpiNet:
\_logic_net: (data_bram), line:48, parent:load_store_unit_block
|vpiName:data_bram
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.data_bram
|vpiNet:
\_logic_net: (store_forwarding), line:54, parent:load_store_unit_block
|vpiName:store_forwarding
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.store_forwarding
|vpiInstance:
\_module: work@taiga (cpu), file:third_party/cores/taiga/examples/zedboard/taiga_wrapper.sv, line:233, parent:work@taiga_wrapper
|vpiArrayNet:
\_array_net: (unit_data_array), line:95, parent:load_store_unit_block
|vpiName:unit_data_array
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.unit_data_array
|vpiSize:13
|vpiNet:
\_logic_net: , parent:unit_data_array
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.unit_data_array
|vpiNetType:36
|vpiRange:
\_range: , line:95
|vpiLeftRange:
\_constant: , line:95
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:95
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiRange:
\_range: , line:95
|vpiLeftRange:
\_constant: , line:95
|vpiConstType:7
|vpiDecompile:12
|vpiSize:32
|INT:12
|vpiRightRange:
\_constant: , line:95
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiVariables:
\_struct_var: (shared_inputs), line:76, parent:load_store_unit_block
|vpiName:shared_inputs
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.shared_inputs
|vpiTypespec:
\_struct_typespec: (data_access_shared_inputs_t), line:427
|vpiVariables:
\_struct_var: (fifo_inputs), line:119, parent:load_store_unit_block
|vpiName:fifo_inputs
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.fifo_inputs
|vpiTypespec:
\_struct_typespec: (load_store_input_fifo_t), line:106
|vpiVariables:
\_struct_var: (load_attributes_in), line:127, parent:load_store_unit_block
|vpiName:load_attributes_in
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.load_attributes_in
|vpiTypespec:
\_struct_typespec: (load_attributes_t), line:121
|vpiVariables:
\_struct_var: (stage2_attr), line:127, parent:load_store_unit_block
|vpiName:stage2_attr
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.stage2_attr
|vpiTypespec:
\_struct_typespec: (load_attributes_t), line:121
|vpiVariables:
\_struct_var: (stage1), line:128, parent:load_store_unit_block
|vpiName:stage1
|vpiFullName:work@taiga_wrapper.cpu.load_store_unit_block.stage1
|vpiTypespec:
\_struct_typespec: (load_store_input_fifo_t), line:106
|vpiParameter:
\_parameter: (ALU_UNIT_WB_ID), line:190
|vpiName:ALU_UNIT_WB_ID
|INT:32
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (ATTRIBUTES_DEPTH), line:74
|vpiName:ATTRIBUTES_DEPTH
|INT:6
|vpiParameter:
\_parameter: (BRAM_ID), line:69
|vpiName:BRAM_ID
|INT:0
|vpiParameter:
\_parameter: (BRANCH_PREDICTOR_WAYS), line:159
|vpiName:BRANCH_PREDICTOR_WAYS
|INT:9
|vpiParameter:
\_parameter: (BRANCH_TABLE_ENTRIES), line:160
|vpiName:BRANCH_TABLE_ENTRIES
|INT:4
|vpiParameter:
\_parameter: (BRANCH_UNIT_ID), line:195
|vpiName:BRANCH_UNIT_ID
|INT:8
|vpiParameter:
\_parameter: (BUS_ADDR_H), line:107
|vpiName:BUS_ADDR_H
|INT:1
|vpiParameter:
\_parameter: (BUS_ADDR_L), line:106
|vpiName:BUS_ADDR_L
|INT:0
|vpiParameter:
\_parameter: (BUS_BIT_CHECK), line:108
|vpiName:BUS_BIT_CHECK
|INT:1
|vpiParameter:
\_parameter: (BUS_ID), line:70
|vpiName:BUS_ID
|INT:3
|vpiParameter:
\_parameter: (BUS_TYPE), line:89
|vpiName:BUS_TYPE
|INT:5
|vpiParameter:
\_parameter: (COUNTER_W), line:42
|vpiName:COUNTER_W
|INT:33
|vpiParameter:
\_parameter: (CPU_ID), line:38
|vpiName:CPU_ID
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_ADDR_WIDTH), line:113
|vpiName:C_M_AXI_ADDR_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_DATA_WIDTH), line:114
|vpiName:C_M_AXI_DATA_WIDTH
|INT:1
|vpiParameter:
\_parameter: (DCACHE_ID), line:71
|vpiName:DCACHE_ID
|INT:7
|vpiParameter:
\_parameter: (DCACHE_LINES), line:133
|vpiName:DCACHE_LINES
|INT:-2146435073
|vpiParameter:
\_parameter: (DCACHE_LINE_ADDR_W), line:135
|vpiName:DCACHE_LINE_ADDR_W
|INT:1073741824
|vpiParameter:
\_parameter: (DCACHE_LINE_W), line:136
|vpiName:DCACHE_LINE_W
|INT:1342177279
|vpiParameter:
\_parameter: (DCACHE_SUB_LINE_ADDR_W), line:137
|vpiName:DCACHE_SUB_LINE_ADDR_W
|INT:4
|vpiParameter:
\_parameter: (DCACHE_TAG_W), line:138
|vpiName:DCACHE_TAG_W
|INT:1610612736
|vpiParameter:
\_parameter: (DCACHE_WAYS), line:134
|vpiName:DCACHE_WAYS
|INT:4
|vpiParameter:
\_parameter: (DIV_ALGORITHM), line:67
|vpiName:DIV_ALGORITHM
|INT:0
|vpiParameter:
\_parameter: (DIV_UNIT_WB_ID), line:192
|vpiName:DIV_UNIT_WB_ID
|INT:2
|vpiParameter:
\_parameter: (DTLB_DEPTH), line:152
|vpiName:DTLB_DEPTH
|INT:512
|vpiParameter:
\_parameter: (DTLB_WAYS), line:151
|vpiName:DTLB_WAYS
|INT:32
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (ENABLE_M_MODE), line:34
|vpiName:ENABLE_M_MODE
|INT:1
|vpiParameter:
\_parameter: (ENABLE_S_MODE), line:36
|vpiName:ENABLE_S_MODE
|INT:0
|vpiParameter:
\_parameter: (ENABLE_TRACE_INTERFACE), line:172
|vpiName:ENABLE_TRACE_INTERFACE
|INT:2
|vpiParameter:
\_parameter: (FETCH_BUFFER_DEPTH), line:168
|vpiName:FETCH_BUFFER_DEPTH
|INT:512
|vpiParameter:
\_parameter: (FPGA_VENDOR), line:27
|vpiName:FPGA_VENDOR
|STRING:"xilinx"
|vpiParameter:
\_parameter: (GC_UNIT_ID), line:196
|vpiName:GC_UNIT_ID
|INT:4
|vpiParameter:
\_parameter: (ICACHE_LINES), line:121
|vpiName:ICACHE_LINES
|INT:2
|vpiParameter:
\_parameter: (ICACHE_LINE_ADDR_W), line:123
|vpiName:ICACHE_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_LINE_W), line:124
|vpiName:ICACHE_LINE_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_SUB_LINE_ADDR_W), line:125
|vpiName:ICACHE_SUB_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_TAG_W), line:126
|vpiName:ICACHE_TAG_W
|INT:-2147483648
|vpiParameter:
\_parameter: (ICACHE_WAYS), line:122
|vpiName:ICACHE_WAYS
|INT:1
|vpiParameter:
\_parameter: (ITLB_DEPTH), line:146
|vpiName:ITLB_DEPTH
|INT:32
|vpiParameter:
\_parameter: (ITLB_WAYS), line:145
|vpiName:ITLB_WAYS
|INT:4
|vpiParameter:
\_parameter: (L1_CONNECTIONS), line:177
|vpiName:L1_CONNECTIONS
|INT:9
|vpiParameter:
\_parameter: (L1_DCACHE_ID), line:178
|vpiName:L1_DCACHE_ID
|INT:4
|vpiParameter:
\_parameter: (L1_DMMU_ID), line:179
|vpiName:L1_DMMU_ID
|INT:2
|vpiParameter:
\_parameter: (L1_ICACHE_ID), line:180
|vpiName:L1_ICACHE_ID
|INT:19
|vpiParameter:
\_parameter: (L1_IMMU_ID), line:181
|vpiName:L1_IMMU_ID
|INT:0
|vpiParameter:
\_parameter: (LS_UNIT_WB_ID), line:191
|vpiName:LS_UNIT_WB_ID
|INT:1
|vpiParameter:
\_parameter: (MAX_INFLIGHT_COUNT), line:167
|vpiName:MAX_INFLIGHT_COUNT
|INT:19
|vpiParameter:
\_parameter: (MEMORY_ADDR_H), line:103
|vpiName:MEMORY_ADDR_H
|INT:12
|vpiParameter:
\_parameter: (MEMORY_ADDR_L), line:102
|vpiName:MEMORY_ADDR_L
|INT:11
|vpiParameter:
\_parameter: (MEMORY_BIT_CHECK), line:104
|vpiName:MEMORY_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (MUL_UNIT_WB_ID), line:193
|vpiName:MUL_UNIT_WB_ID
|INT:512
|vpiParameter:
\_parameter: (NUM_SUB_UNITS), line:66
|vpiName:NUM_SUB_UNITS
|INT:13
|vpiParameter:
\_parameter: (NUM_SUB_UNITS_W), line:67
|vpiName:NUM_SUB_UNITS_W
|INT:0
|vpiParameter:
\_parameter: (NUM_UNITS), line:188
|vpiName:NUM_UNITS
|INT:2
|vpiParameter:
\_parameter: (NUM_WB_UNITS), line:186
|vpiName:NUM_WB_UNITS
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (RAS_DEPTH), line:161
|vpiName:RAS_DEPTH
|INT:2
|vpiParameter:
\_parameter: (RESET_VEC), line:39
|vpiName:RESET_VEC
|INT:-2147483648
|vpiParameter:
\_parameter: (SCRATCH_ADDR_H), line:99
|vpiName:SCRATCH_ADDR_H
|INT:9
|vpiParameter:
\_parameter: (SCRATCH_ADDR_L), line:98
|vpiName:SCRATCH_ADDR_L
|INT:8
|vpiParameter:
\_parameter: (SCRATCH_BIT_CHECK), line:100
|vpiName:SCRATCH_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (USE_AMO), line:70
|vpiName:USE_AMO
|INT:1
|vpiParameter:
\_parameter: (USE_BRANCH_PREDICTOR), line:158
|vpiName:USE_BRANCH_PREDICTOR
|INT:2
|vpiParameter:
\_parameter: (USE_BUS), line:88
|vpiName:USE_BUS
|INT:4
|vpiParameter:
\_parameter: (USE_DCACHE), line:92
|vpiName:USE_DCACHE
|INT:6
|vpiParameter:
\_parameter: (USE_DIV), line:49
|vpiName:USE_DIV
|INT:1
|vpiParameter:
\_parameter: (USE_DTAG_INVALIDATIONS), line:140
|vpiName:USE_DTAG_INVALIDATIONS
|INT:1879048191
|vpiParameter:
\_parameter: (USE_D_SCRATCH_MEM), line:79
|vpiName:USE_D_SCRATCH_MEM
|INT:3
|vpiParameter:
\_parameter: (USE_ICACHE), line:93
|vpiName:USE_ICACHE
|INT:7
|vpiParameter:
\_parameter: (USE_I_SCRATCH_MEM), line:78
|vpiName:USE_I_SCRATCH_MEM
|INT:2
|vpiParameter:
\_parameter: (USE_MUL), line:48
|vpiName:USE_MUL
|INT:1
|vpiParameter:
\_parameter: (WB_UNITS_WIDTH), line:187
|vpiName:WB_UNITS_WIDTH
|INT:32
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiModule:
\_module: work@gc_unit (gc_unit_block), file:third_party/cores/taiga/core/taiga.sv, line:193, parent:cpu
|vpiDefName:work@gc_unit
|vpiName:gc_unit_block
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block
|vpiPort:
\_port: (clk), line:28, parent:gc_unit_block
|vpiName:clk
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (clk), line:193
|vpiName:clk
|vpiActual:
\_logic_net: (clk), line:27, parent:cpu
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (clk), line:28, parent:gc_unit_block
|vpiName:clk
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.clk
|vpiNetType:36
|vpiPort:
\_port: (rst), line:29, parent:gc_unit_block
|vpiName:rst
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (rst), line:193
|vpiName:rst
|vpiActual:
\_logic_net: (rst), line:28, parent:cpu
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (rst), line:29, parent:gc_unit_block
|vpiName:rst
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.rst
|vpiNetType:36
|vpiPort:
\_port: (issue), line:33, parent:gc_unit_block
|vpiName:issue
|vpiDirection:5
|vpiHighConn:
\_ref_obj: (issue), line:193
|vpiName:issue
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_modport: (unit)
|vpiName:unit
|vpiIODecl:
\_io_decl: (ready)
|vpiName:ready
|vpiDirection:2
|vpiExpr:
\_logic_net: (ready), line:58
|vpiName:ready
|vpiNetType:36
|vpiIODecl:
\_io_decl: (possible_issue)
|vpiName:possible_issue
|vpiDirection:1
|vpiExpr:
\_logic_net: (possible_issue), line:53
|vpiName:possible_issue
|vpiNetType:36
|vpiIODecl:
\_io_decl: (new_request)
|vpiName:new_request
|vpiDirection:1
|vpiExpr:
\_logic_net: (new_request), line:54
|vpiName:new_request
|vpiNetType:36
|vpiIODecl:
\_io_decl: (new_request_r)
|vpiName:new_request_r
|vpiDirection:1
|vpiExpr:
\_logic_net: (new_request_r), line:55
|vpiName:new_request_r
|vpiNetType:36
|vpiIODecl:
\_io_decl: (instruction_id)
|vpiName:instruction_id
|vpiDirection:1
|vpiInterface:
\_interface: work@unit_issue_interface (issue), file:third_party/cores/taiga/core/taiga.sv, line:193
|vpiDefName:work@unit_issue_interface
|vpiName:issue
|vpiModport:
\_modport: (decode)
|vpiName:decode
|vpiIODecl:
\_io_decl: (ready)
|vpiName:ready
|vpiDirection:1
|vpiExpr:
\_logic_net: (ready), line:58
|vpiIODecl:
\_io_decl: (possible_issue)
|vpiName:possible_issue
|vpiDirection:2
|vpiExpr:
\_logic_net: (possible_issue), line:53
|vpiIODecl:
\_io_decl: (new_request)
|vpiName:new_request
|vpiDirection:2
|vpiExpr:
\_logic_net: (new_request), line:54
|vpiIODecl:
\_io_decl: (new_request_r)
|vpiName:new_request_r
|vpiDirection:2
|vpiExpr:
\_logic_net: (new_request_r), line:55
|vpiIODecl:
\_io_decl: (instruction_id)
|vpiName:instruction_id
|vpiDirection:2
|vpiInterface:
\_interface: work@unit_issue_interface (issue), file:third_party/cores/taiga/core/taiga.sv, line:193
|vpiModport:
\_modport: (unit)
|vpiPort:
\_port: (gc_inputs), line:34, parent:gc_unit_block
|vpiName:gc_inputs
|vpiDirection:1
|vpiTypedef:
\_struct_typespec: (gc_inputs_t), line:404
|vpiHighConn:
\_ref_obj: (gc_inputs), line:193
|vpiName:gc_inputs
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (gc_inputs), line:34, parent:gc_unit_block
|vpiName:gc_inputs
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.gc_inputs
|vpiPort:
\_port: (instruction_issued_no_rd), line:35, parent:gc_unit_block
|vpiName:instruction_issued_no_rd
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (instruction_issued_no_rd), line:193
|vpiName:instruction_issued_no_rd
|vpiActual:
\_logic_net: (instruction_issued_no_rd), line:112, parent:cpu
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (instruction_issued_no_rd), line:35, parent:gc_unit_block
|vpiName:instruction_issued_no_rd
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.instruction_issued_no_rd
|vpiNetType:36
|vpiPort:
\_port: (gc_flush_required), line:36, parent:gc_unit_block
|vpiName:gc_flush_required
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (gc_flush_required), line:193
|vpiName:gc_flush_required
|vpiActual:
\_logic_net: (gc_flush_required), line:115, parent:cpu
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (gc_flush_required), line:36, parent:gc_unit_block
|vpiName:gc_flush_required
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.gc_flush_required
|vpiNetType:36
|vpiPort:
\_port: (branch_flush), line:38, parent:gc_unit_block
|vpiName:branch_flush
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (branch_flush), line:193
|vpiName:branch_flush
|vpiActual:
\_logic_net: (branch_flush), line:52, parent:cpu
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (branch_flush), line:38, parent:gc_unit_block
|vpiName:branch_flush
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.branch_flush
|vpiNetType:36
|vpiPort:
\_port: (ls_exception), line:41, parent:gc_unit_block
|vpiName:ls_exception
|vpiDirection:1
|vpiTypedef:
\_struct_typespec: (exception_packet_t), line:263
|vpiHighConn:
\_ref_obj: (ls_exception), line:193
|vpiName:ls_exception
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (ls_exception), line:41, parent:gc_unit_block
|vpiName:ls_exception
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.ls_exception
|vpiPort:
\_port: (ls_exception_valid), line:42, parent:gc_unit_block
|vpiName:ls_exception_valid
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (ls_exception_valid), line:193
|vpiName:ls_exception_valid
|vpiActual:
\_logic_net: (ls_exception_valid), line:67, parent:cpu
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (ls_exception_valid), line:42, parent:gc_unit_block
|vpiName:ls_exception_valid
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.ls_exception_valid
|vpiNetType:36
|vpiPort:
\_port: (tlb_on), line:45, parent:gc_unit_block
|vpiName:tlb_on
|vpiDirection:2
|vpiHighConn:
\_ref_obj: (tlb_on), line:193
|vpiName:tlb_on
|vpiActual:
\_logic_net: (tlb_on), line:78, parent:cpu
|vpiName:tlb_on
|vpiFullName:work@taiga_wrapper.cpu.tlb_on
|vpiNetType:36
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (tlb_on), line:45, parent:gc_unit_block
|vpiName:tlb_on
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.tlb_on
|vpiNetType:36
|vpiPort:
\_port: (asid), line:46, parent:gc_unit_block
|vpiName:asid
|vpiDirection:2
|vpiHighConn:
\_ref_obj: (asid), line:193
|vpiName:asid
|vpiActual:
\_logic_net: (asid), line:79, parent:cpu
|vpiName:asid
|vpiFullName:work@taiga_wrapper.cpu.asid
|vpiNetType:36
|vpiRange:
\_range: , line:79
|vpiLeftRange:
\_constant: , line:79
|vpiConstType:7
|vpiDecompile:10
|vpiSize:32
|INT:10
|vpiRightRange:
\_constant: , line:79
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (asid), line:46, parent:gc_unit_block
|vpiName:asid
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.asid
|vpiNetType:36
|vpiRange:
\_range: , line:46
|vpiLeftRange:
\_constant: , line:46
|vpiConstType:7
|vpiDecompile:10
|vpiSize:32
|INT:10
|vpiRightRange:
\_constant: , line:46
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiPort:
\_port: (immu), line:49, parent:gc_unit_block
|vpiName:immu
|vpiDirection:5
|vpiHighConn:
\_ref_obj: (immu), line:193
|vpiName:immu
|vpiActual:
\_interface: work@mmu_interface (immu), file:third_party/cores/taiga/core/taiga.sv, line:73
|vpiDefName:work@mmu_interface
|vpiName:immu
|vpiModport:
\_modport: (csr)
|vpiName:csr
|vpiIODecl:
\_io_decl: (ppn)
|vpiName:ppn
|vpiDirection:2
|vpiIODecl:
\_io_decl: (mxr)
|vpiName:mxr
|vpiDirection:2
|vpiIODecl:
\_io_decl: (pum)
|vpiName:pum
|vpiDirection:2
|vpiIODecl:
\_io_decl: (privilege)
|vpiName:privilege
|vpiDirection:2
|vpiInterface:
\_interface: work@mmu_interface (immu), file:third_party/cores/taiga/core/taiga.sv, line:73
|vpiModport:
\_modport: (mmu)
|vpiName:mmu
|vpiIODecl:
\_io_decl: (virtual_address)
|vpiName:virtual_address
|vpiDirection:1
|vpiIODecl:
\_io_decl: (new_request)
|vpiName:new_request
|vpiDirection:1
|vpiIODecl:
\_io_decl: (execute)
|vpiName:execute
|vpiDirection:1
|vpiIODecl:
\_io_decl: (rnw)
|vpiName:rnw
|vpiDirection:1
|vpiIODecl:
\_io_decl: (ppn)
|vpiName:ppn
|vpiDirection:1
|vpiIODecl:
\_io_decl: (mxr)
|vpiName:mxr
|vpiDirection:1
|vpiIODecl:
\_io_decl: (pum)
|vpiName:pum
|vpiDirection:1
|vpiIODecl:
\_io_decl: (privilege)
|vpiName:privilege
|vpiDirection:1
|vpiIODecl:
\_io_decl: (write_entry)
|vpiName:write_entry
|vpiDirection:2
|vpiIODecl:
\_io_decl: (new_phys_addr)
|vpiName:new_phys_addr
|vpiDirection:2
|vpiInterface:
\_interface: work@mmu_interface (immu), file:third_party/cores/taiga/core/taiga.sv, line:73
|vpiModport:
\_modport: (tlb)
|vpiName:tlb
|vpiIODecl:
\_io_decl: (write_entry)
|vpiName:write_entry
|vpiDirection:1
|vpiIODecl:
\_io_decl: (new_phys_addr)
|vpiName:new_phys_addr
|vpiDirection:1
|vpiIODecl:
\_io_decl: (new_request)
|vpiName:new_request
|vpiDirection:2
|vpiIODecl:
\_io_decl: (virtual_address)
|vpiName:virtual_address
|vpiDirection:2
|vpiIODecl:
\_io_decl: (execute)
|vpiName:execute
|vpiDirection:2
|vpiIODecl:
\_io_decl: (rnw)
|vpiName:rnw
|vpiDirection:2
|vpiInterface:
\_interface: work@mmu_interface (immu), file:third_party/cores/taiga/core/taiga.sv, line:73
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_modport: (csr)
|vpiName:csr
|vpiIODecl:
\_io_decl: (ppn)
|vpiName:ppn
|vpiDirection:2
|vpiExpr:
\_logic_net: (ppn), line:182
|vpiName:ppn
|vpiNetType:36
|vpiRange:
\_range: , line:182
|vpiLeftRange:
\_constant: , line:182
|vpiConstType:7
|vpiDecompile:21
|vpiSize:32
|INT:21
|vpiRightRange:
\_constant: , line:182
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (mxr)
|vpiName:mxr
|vpiDirection:2
|vpiExpr:
\_logic_net: (mxr), line:183
|vpiName:mxr
|vpiNetType:36
|vpiIODecl:
\_io_decl: (pum)
|vpiName:pum
|vpiDirection:2
|vpiExpr:
\_logic_net: (pum), line:184
|vpiName:pum
|vpiNetType:36
|vpiIODecl:
\_io_decl: (privilege)
|vpiName:privilege
|vpiDirection:2
|vpiExpr:
\_logic_net: (privilege), line:185
|vpiName:privilege
|vpiNetType:36
|vpiRange:
\_range: , line:185
|vpiLeftRange:
\_constant: , line:185
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:185
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiInterface:
\_interface: work@mmu_interface (immu), file:third_party/cores/taiga/core/taiga.sv, line:193
|vpiDefName:work@mmu_interface
|vpiName:immu
|vpiModport:
\_modport: (csr)
|vpiModport:
\_modport: (mmu)
|vpiName:mmu
|vpiIODecl:
\_io_decl: (virtual_address)
|vpiName:virtual_address
|vpiDirection:1
|vpiExpr:
\_logic_net: (virtual_address), line:175
|vpiName:virtual_address
|vpiNetType:36
|vpiRange:
\_range: , line:175
|vpiLeftRange:
\_constant: , line:175
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:175
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (new_request)
|vpiName:new_request
|vpiDirection:1
|vpiExpr:
\_logic_net: (new_request), line:54
|vpiIODecl:
\_io_decl: (execute)
|vpiName:execute
|vpiDirection:1
|vpiExpr:
\_logic_net: (execute), line:173
|vpiName:execute
|vpiNetType:36
|vpiIODecl:
\_io_decl: (rnw)
|vpiName:rnw
|vpiDirection:1
|vpiExpr:
\_logic_net: (rnw), line:174
|vpiName:rnw
|vpiNetType:36
|vpiIODecl:
\_io_decl: (ppn)
|vpiName:ppn
|vpiDirection:1
|vpiExpr:
\_logic_net: (ppn), line:182
|vpiIODecl:
\_io_decl: (mxr)
|vpiName:mxr
|vpiDirection:1
|vpiExpr:
\_logic_net: (mxr), line:183
|vpiIODecl:
\_io_decl: (pum)
|vpiName:pum
|vpiDirection:1
|vpiExpr:
\_logic_net: (pum), line:184
|vpiIODecl:
\_io_decl: (privilege)
|vpiName:privilege
|vpiDirection:1
|vpiExpr:
\_logic_net: (privilege), line:185
|vpiIODecl:
\_io_decl: (write_entry)
|vpiName:write_entry
|vpiDirection:2
|vpiExpr:
\_logic_net: (write_entry), line:178
|vpiName:write_entry
|vpiNetType:36
|vpiIODecl:
\_io_decl: (new_phys_addr)
|vpiName:new_phys_addr
|vpiDirection:2
|vpiExpr:
\_logic_net: (new_phys_addr), line:179
|vpiName:new_phys_addr
|vpiNetType:36
|vpiRange:
\_range: , line:179
|vpiLeftRange:
\_constant: , line:179
|vpiConstType:7
|vpiDecompile:19
|vpiSize:32
|INT:19
|vpiRightRange:
\_constant: , line:179
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiInterface:
\_interface: work@mmu_interface (immu), file:third_party/cores/taiga/core/taiga.sv, line:193
|vpiModport:
\_modport: (tlb)
|vpiName:tlb
|vpiIODecl:
\_io_decl: (write_entry)
|vpiName:write_entry
|vpiDirection:1
|vpiExpr:
\_logic_net: (write_entry), line:178
|vpiIODecl:
\_io_decl: (new_phys_addr)
|vpiName:new_phys_addr
|vpiDirection:1
|vpiExpr:
\_logic_net: (new_phys_addr), line:179
|vpiIODecl:
\_io_decl: (new_request)
|vpiName:new_request
|vpiDirection:2
|vpiExpr:
\_logic_net: (new_request), line:54
|vpiIODecl:
\_io_decl: (virtual_address)
|vpiName:virtual_address
|vpiDirection:2
|vpiExpr:
\_logic_net: (virtual_address), line:175
|vpiIODecl:
\_io_decl: (execute)
|vpiName:execute
|vpiDirection:2
|vpiExpr:
\_logic_net: (execute), line:173
|vpiIODecl:
\_io_decl: (rnw)
|vpiName:rnw
|vpiDirection:2
|vpiExpr:
\_logic_net: (rnw), line:174
|vpiInterface:
\_interface: work@mmu_interface (immu), file:third_party/cores/taiga/core/taiga.sv, line:193
|vpiPort:
\_port: (dmmu), line:50, parent:gc_unit_block
|vpiName:dmmu
|vpiDirection:5
|vpiHighConn:
\_ref_obj: (dmmu), line:193
|vpiName:dmmu
|vpiActual:
\_interface: work@mmu_interface (dmmu), file:third_party/cores/taiga/core/taiga.sv, line:74
|vpiDefName:work@mmu_interface
|vpiName:dmmu
|vpiModport:
\_modport: (csr)
|vpiName:csr
|vpiIODecl:
\_io_decl: (ppn)
|vpiName:ppn
|vpiDirection:2
|vpiIODecl:
\_io_decl: (mxr)
|vpiName:mxr
|vpiDirection:2
|vpiIODecl:
\_io_decl: (pum)
|vpiName:pum
|vpiDirection:2
|vpiIODecl:
\_io_decl: (privilege)
|vpiName:privilege
|vpiDirection:2
|vpiInterface:
\_interface: work@mmu_interface (dmmu), file:third_party/cores/taiga/core/taiga.sv, line:74
|vpiModport:
\_modport: (mmu)
|vpiName:mmu
|vpiIODecl:
\_io_decl: (virtual_address)
|vpiName:virtual_address
|vpiDirection:1
|vpiIODecl:
\_io_decl: (new_request)
|vpiName:new_request
|vpiDirection:1
|vpiIODecl:
\_io_decl: (execute)
|vpiName:execute
|vpiDirection:1
|vpiIODecl:
\_io_decl: (rnw)
|vpiName:rnw
|vpiDirection:1
|vpiIODecl:
\_io_decl: (ppn)
|vpiName:ppn
|vpiDirection:1
|vpiIODecl:
\_io_decl: (mxr)
|vpiName:mxr
|vpiDirection:1
|vpiIODecl:
\_io_decl: (pum)
|vpiName:pum
|vpiDirection:1
|vpiIODecl:
\_io_decl: (privilege)
|vpiName:privilege
|vpiDirection:1
|vpiIODecl:
\_io_decl: (write_entry)
|vpiName:write_entry
|vpiDirection:2
|vpiIODecl:
\_io_decl: (new_phys_addr)
|vpiName:new_phys_addr
|vpiDirection:2
|vpiInterface:
\_interface: work@mmu_interface (dmmu), file:third_party/cores/taiga/core/taiga.sv, line:74
|vpiModport:
\_modport: (tlb)
|vpiName:tlb
|vpiIODecl:
\_io_decl: (write_entry)
|vpiName:write_entry
|vpiDirection:1
|vpiIODecl:
\_io_decl: (new_phys_addr)
|vpiName:new_phys_addr
|vpiDirection:1
|vpiIODecl:
\_io_decl: (new_request)
|vpiName:new_request
|vpiDirection:2
|vpiIODecl:
\_io_decl: (virtual_address)
|vpiName:virtual_address
|vpiDirection:2
|vpiIODecl:
\_io_decl: (execute)
|vpiName:execute
|vpiDirection:2
|vpiIODecl:
\_io_decl: (rnw)
|vpiName:rnw
|vpiDirection:2
|vpiInterface:
\_interface: work@mmu_interface (dmmu), file:third_party/cores/taiga/core/taiga.sv, line:74
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_modport: (csr)
|vpiName:csr
|vpiIODecl:
\_io_decl: (ppn)
|vpiName:ppn
|vpiDirection:2
|vpiExpr:
\_logic_net: (ppn), line:182
|vpiIODecl:
\_io_decl: (mxr)
|vpiName:mxr
|vpiDirection:2
|vpiExpr:
\_logic_net: (mxr), line:183
|vpiIODecl:
\_io_decl: (pum)
|vpiName:pum
|vpiDirection:2
|vpiExpr:
\_logic_net: (pum), line:184
|vpiIODecl:
\_io_decl: (privilege)
|vpiName:privilege
|vpiDirection:2
|vpiExpr:
\_logic_net: (privilege), line:185
|vpiInterface:
\_interface: work@mmu_interface (dmmu), file:third_party/cores/taiga/core/taiga.sv, line:193
|vpiDefName:work@mmu_interface
|vpiName:dmmu
|vpiModport:
\_modport: (csr)
|vpiModport:
\_modport: (mmu)
|vpiName:mmu
|vpiIODecl:
\_io_decl: (virtual_address)
|vpiName:virtual_address
|vpiDirection:1
|vpiExpr:
\_logic_net: (virtual_address), line:175
|vpiIODecl:
\_io_decl: (new_request)
|vpiName:new_request
|vpiDirection:1
|vpiExpr:
\_logic_net: (new_request), line:54
|vpiIODecl:
\_io_decl: (execute)
|vpiName:execute
|vpiDirection:1
|vpiExpr:
\_logic_net: (execute), line:173
|vpiIODecl:
\_io_decl: (rnw)
|vpiName:rnw
|vpiDirection:1
|vpiExpr:
\_logic_net: (rnw), line:174
|vpiIODecl:
\_io_decl: (ppn)
|vpiName:ppn
|vpiDirection:1
|vpiExpr:
\_logic_net: (ppn), line:182
|vpiIODecl:
\_io_decl: (mxr)
|vpiName:mxr
|vpiDirection:1
|vpiExpr:
\_logic_net: (mxr), line:183
|vpiIODecl:
\_io_decl: (pum)
|vpiName:pum
|vpiDirection:1
|vpiExpr:
\_logic_net: (pum), line:184
|vpiIODecl:
\_io_decl: (privilege)
|vpiName:privilege
|vpiDirection:1
|vpiExpr:
\_logic_net: (privilege), line:185
|vpiIODecl:
\_io_decl: (write_entry)
|vpiName:write_entry
|vpiDirection:2
|vpiExpr:
\_logic_net: (write_entry), line:178
|vpiIODecl:
\_io_decl: (new_phys_addr)
|vpiName:new_phys_addr
|vpiDirection:2
|vpiExpr:
\_logic_net: (new_phys_addr), line:179
|vpiInterface:
\_interface: work@mmu_interface (dmmu), file:third_party/cores/taiga/core/taiga.sv, line:193
|vpiModport:
\_modport: (tlb)
|vpiName:tlb
|vpiIODecl:
\_io_decl: (write_entry)
|vpiName:write_entry
|vpiDirection:1
|vpiExpr:
\_logic_net: (write_entry), line:178
|vpiIODecl:
\_io_decl: (new_phys_addr)
|vpiName:new_phys_addr
|vpiDirection:1
|vpiExpr:
\_logic_net: (new_phys_addr), line:179
|vpiIODecl:
\_io_decl: (new_request)
|vpiName:new_request
|vpiDirection:2
|vpiExpr:
\_logic_net: (new_request), line:54
|vpiIODecl:
\_io_decl: (virtual_address)
|vpiName:virtual_address
|vpiDirection:2
|vpiExpr:
\_logic_net: (virtual_address), line:175
|vpiIODecl:
\_io_decl: (execute)
|vpiName:execute
|vpiDirection:2
|vpiExpr:
\_logic_net: (execute), line:173
|vpiIODecl:
\_io_decl: (rnw)
|vpiName:rnw
|vpiDirection:2
|vpiExpr:
\_logic_net: (rnw), line:174
|vpiInterface:
\_interface: work@mmu_interface (dmmu), file:third_party/cores/taiga/core/taiga.sv, line:193
|vpiPort:
\_port: (instruction_complete), line:53, parent:gc_unit_block
|vpiName:instruction_complete
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (instruction_complete), line:193
|vpiName:instruction_complete
|vpiActual:
\_logic_net: (instruction_complete), line:114, parent:cpu
|vpiName:instruction_complete
|vpiFullName:work@taiga_wrapper.cpu.instruction_complete
|vpiNetType:36
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (instruction_complete), line:53, parent:gc_unit_block
|vpiName:instruction_complete
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.instruction_complete
|vpiNetType:36
|vpiPort:
\_port: (instruction_queue_empty), line:54, parent:gc_unit_block
|vpiName:instruction_queue_empty
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (instruction_queue_empty), line:193
|vpiName:instruction_queue_empty
|vpiActual:
\_logic_net: (instruction_queue_empty), line:109, parent:cpu
|vpiName:instruction_queue_empty
|vpiFullName:work@taiga_wrapper.cpu.instruction_queue_empty
|vpiNetType:36
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (instruction_queue_empty), line:54, parent:gc_unit_block
|vpiName:instruction_queue_empty
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.instruction_queue_empty
|vpiNetType:36
|vpiPort:
\_port: (oldest_id), line:55, parent:gc_unit_block
|vpiName:oldest_id
|vpiDirection:1
|vpiTypedef:
\_logic_typespec: (instruction_id_t), line:30
|vpiHighConn:
\_ref_obj: (oldest_id), line:193
|vpiName:oldest_id
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (oldest_id), line:55, parent:gc_unit_block
|vpiName:oldest_id
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.oldest_id
|vpiPort:
\_port: (interrupt), line:59, parent:gc_unit_block
|vpiName:interrupt
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (interrupt), line:193
|vpiName:interrupt
|vpiActual:
\_logic_net: (interrupt), line:42, parent:cpu
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (interrupt), line:59, parent:gc_unit_block
|vpiName:interrupt
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.interrupt
|vpiNetType:36
|vpiPort:
\_port: (timer_interrupt), line:60, parent:gc_unit_block
|vpiName:timer_interrupt
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (timer_interrupt), line:193
|vpiName:timer_interrupt
|vpiActual:
\_logic_net: (timer_interrupt), line:41, parent:cpu
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (timer_interrupt), line:60, parent:gc_unit_block
|vpiName:timer_interrupt
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.timer_interrupt
|vpiNetType:36
|vpiPort:
\_port: (gc_issue_hold), line:63, parent:gc_unit_block
|vpiName:gc_issue_hold
|vpiDirection:2
|vpiHighConn:
\_ref_obj: (gc_issue_hold), line:193
|vpiName:gc_issue_hold
|vpiActual:
\_logic_net: (gc_issue_hold), line:93, parent:cpu
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (gc_issue_hold), line:63, parent:gc_unit_block
|vpiName:gc_issue_hold
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.gc_issue_hold
|vpiNetType:36
|vpiPort:
\_port: (gc_issue_flush), line:64, parent:gc_unit_block
|vpiName:gc_issue_flush
|vpiDirection:2
|vpiHighConn:
\_ref_obj: (gc_issue_flush), line:193
|vpiName:gc_issue_flush
|vpiActual:
\_logic_net: (gc_issue_flush), line:94, parent:cpu
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (gc_issue_flush), line:64, parent:gc_unit_block
|vpiName:gc_issue_flush
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.gc_issue_flush
|vpiNetType:36
|vpiPort:
\_port: (gc_fetch_flush), line:65, parent:gc_unit_block
|vpiName:gc_fetch_flush
|vpiDirection:2
|vpiHighConn:
\_ref_obj: (gc_fetch_flush), line:193
|vpiName:gc_fetch_flush
|vpiActual:
\_logic_net: (gc_fetch_flush), line:95, parent:cpu
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (gc_fetch_flush), line:65, parent:gc_unit_block
|vpiName:gc_fetch_flush
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.gc_fetch_flush
|vpiNetType:36
|vpiPort:
\_port: (gc_fetch_pc_override), line:66, parent:gc_unit_block
|vpiName:gc_fetch_pc_override
|vpiDirection:2
|vpiHighConn:
\_ref_obj: (gc_fetch_pc_override), line:193
|vpiName:gc_fetch_pc_override
|vpiActual:
\_logic_net: (gc_fetch_pc_override), line:96, parent:cpu
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (gc_fetch_pc_override), line:66, parent:gc_unit_block
|vpiName:gc_fetch_pc_override
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.gc_fetch_pc_override
|vpiNetType:36
|vpiPort:
\_port: (gc_supress_writeback), line:67, parent:gc_unit_block
|vpiName:gc_supress_writeback
|vpiDirection:2
|vpiHighConn:
\_ref_obj: (gc_supress_writeback), line:193
|vpiName:gc_supress_writeback
|vpiActual:
\_logic_net: (gc_supress_writeback), line:97, parent:cpu
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (gc_supress_writeback), line:67, parent:gc_unit_block
|vpiName:gc_supress_writeback
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.gc_supress_writeback
|vpiNetType:36
|vpiPort:
\_port: (gc_fetch_pc), line:69, parent:gc_unit_block
|vpiName:gc_fetch_pc
|vpiDirection:2
|vpiHighConn:
\_ref_obj: (gc_fetch_pc), line:193
|vpiName:gc_fetch_pc
|vpiActual:
\_logic_net: (gc_fetch_pc), line:100, parent:cpu
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (gc_fetch_pc), line:69, parent:gc_unit_block
|vpiName:gc_fetch_pc
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.gc_fetch_pc
|vpiNetType:36
|vpiRange:
\_range: , line:69
|vpiLeftRange:
\_constant: , line:69
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:69
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiPort:
\_port: (csr_rd), line:72, parent:gc_unit_block
|vpiName:csr_rd
|vpiDirection:2
|vpiHighConn:
\_ref_obj: (csr_rd), line:193
|vpiName:csr_rd
|vpiActual:
\_logic_net: (csr_rd), line:103, parent:cpu
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (csr_rd), line:72, parent:gc_unit_block
|vpiName:csr_rd
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_rd
|vpiNetType:36
|vpiRange:
\_range: , line:72
|vpiLeftRange:
\_constant: , line:72
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:72
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiPort:
\_port: (csr_id), line:73, parent:gc_unit_block
|vpiName:csr_id
|vpiDirection:2
|vpiTypedef:
\_logic_typespec: (instruction_id_t), line:30
|vpiHighConn:
\_ref_obj: (csr_id), line:193
|vpiName:csr_id
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (csr_id), line:73, parent:gc_unit_block
|vpiName:csr_id
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_id
|vpiPort:
\_port: (csr_done), line:74, parent:gc_unit_block
|vpiName:csr_done
|vpiDirection:2
|vpiHighConn:
\_ref_obj: (csr_done), line:193
|vpiName:csr_done
|vpiActual:
\_logic_net: (csr_done), line:105, parent:cpu
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (csr_done), line:74, parent:gc_unit_block
|vpiName:csr_done
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_done
|vpiNetType:36
|vpiModule:
\_module: work@shift_counter (tlb_clear_counter), file:third_party/cores/taiga/core/gc_unit.sv, line:215, parent:gc_unit_block
|vpiDefName:work@shift_counter
|vpiName:tlb_clear_counter
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.tlb_clear_counter
|vpiPort:
\_port: (clk), line:27, parent:tlb_clear_counter
|vpiName:clk
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (clk), line:215
|vpiName:clk
|vpiActual:
\_logic_net: (clk), line:28, parent:gc_unit_block
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (clk), line:27, parent:tlb_clear_counter
|vpiName:clk
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.tlb_clear_counter.clk
|vpiNetType:36
|vpiPort:
\_port: (start), line:29, parent:tlb_clear_counter
|vpiName:start
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (start), line:215
|vpiName:start
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (start), line:29, parent:tlb_clear_counter
|vpiName:start
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.tlb_clear_counter.start
|vpiNetType:36
|vpiPort:
\_port: (done), line:30, parent:tlb_clear_counter
|vpiName:done
|vpiDirection:2
|vpiHighConn:
\_ref_obj: (done), line:215
|vpiName:done
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (done), line:30, parent:tlb_clear_counter
|vpiName:done
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.tlb_clear_counter.done
|vpiNetType:36
|vpiNet:
\_logic_net: (clk), line:27, parent:tlb_clear_counter
|vpiNet:
\_logic_net: (start), line:29, parent:tlb_clear_counter
|vpiNet:
\_logic_net: (done), line:30, parent:tlb_clear_counter
|vpiNet:
\_logic_net: (counter), line:33, parent:tlb_clear_counter
|vpiName:counter
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.tlb_clear_counter.counter
|vpiNetType:36
|vpiRange:
\_range: , line:33
|vpiLeftRange:
\_constant: , line:33
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiRightRange:
\_constant: , line:33
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiInstance:
\_module: work@gc_unit (gc_unit_block), file:third_party/cores/taiga/core/taiga.sv, line:193, parent:cpu
|vpiParameter:
\_parameter: (ALU_UNIT_WB_ID), line:190
|vpiName:ALU_UNIT_WB_ID
|INT:32
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (BRANCH_PREDICTOR_WAYS), line:159
|vpiName:BRANCH_PREDICTOR_WAYS
|INT:9
|vpiParameter:
\_parameter: (BRANCH_TABLE_ENTRIES), line:160
|vpiName:BRANCH_TABLE_ENTRIES
|INT:4
|vpiParameter:
\_parameter: (BRANCH_UNIT_ID), line:195
|vpiName:BRANCH_UNIT_ID
|INT:8
|vpiParameter:
\_parameter: (BUS_ADDR_H), line:107
|vpiName:BUS_ADDR_H
|INT:1
|vpiParameter:
\_parameter: (BUS_ADDR_L), line:106
|vpiName:BUS_ADDR_L
|INT:0
|vpiParameter:
\_parameter: (BUS_BIT_CHECK), line:108
|vpiName:BUS_BIT_CHECK
|INT:1
|vpiParameter:
\_parameter: (BUS_TYPE), line:89
|vpiName:BUS_TYPE
|INT:5
|vpiParameter:
\_parameter: (COUNTER_W), line:42
|vpiName:COUNTER_W
|INT:33
|vpiParameter:
\_parameter: (CPU_ID), line:38
|vpiName:CPU_ID
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_ADDR_WIDTH), line:113
|vpiName:C_M_AXI_ADDR_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_DATA_WIDTH), line:114
|vpiName:C_M_AXI_DATA_WIDTH
|INT:1
|vpiParameter:
\_parameter: (DCACHE_LINES), line:133
|vpiName:DCACHE_LINES
|INT:-2146435073
|vpiParameter:
\_parameter: (DCACHE_LINE_ADDR_W), line:135
|vpiName:DCACHE_LINE_ADDR_W
|INT:1073741824
|vpiParameter:
\_parameter: (DCACHE_LINE_W), line:136
|vpiName:DCACHE_LINE_W
|INT:1342177279
|vpiParameter:
\_parameter: (DCACHE_SUB_LINE_ADDR_W), line:137
|vpiName:DCACHE_SUB_LINE_ADDR_W
|INT:4
|vpiParameter:
\_parameter: (DCACHE_TAG_W), line:138
|vpiName:DCACHE_TAG_W
|INT:1610612736
|vpiParameter:
\_parameter: (DCACHE_WAYS), line:134
|vpiName:DCACHE_WAYS
|INT:4
|vpiParameter:
\_parameter: (DEPTH), line:215
|vpiName:DEPTH
|INT:1
|vpiParameter:
\_parameter: (DIV_ALGORITHM), line:67
|vpiName:DIV_ALGORITHM
|INT:0
|vpiParameter:
\_parameter: (DIV_UNIT_WB_ID), line:192
|vpiName:DIV_UNIT_WB_ID
|INT:2
|vpiParameter:
\_parameter: (DTLB_DEPTH), line:152
|vpiName:DTLB_DEPTH
|INT:512
|vpiParameter:
\_parameter: (DTLB_WAYS), line:151
|vpiName:DTLB_WAYS
|INT:32
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (ENABLE_M_MODE), line:34
|vpiName:ENABLE_M_MODE
|INT:1
|vpiParameter:
\_parameter: (ENABLE_S_MODE), line:36
|vpiName:ENABLE_S_MODE
|INT:0
|vpiParameter:
\_parameter: (ENABLE_TRACE_INTERFACE), line:172
|vpiName:ENABLE_TRACE_INTERFACE
|INT:2
|vpiParameter:
\_parameter: (FETCH_BUFFER_DEPTH), line:168
|vpiName:FETCH_BUFFER_DEPTH
|INT:512
|vpiParameter:
\_parameter: (FPGA_VENDOR), line:27
|vpiName:FPGA_VENDOR
|STRING:"xilinx"
|vpiParameter:
\_parameter: (GC_UNIT_ID), line:196
|vpiName:GC_UNIT_ID
|INT:4
|vpiParameter:
\_parameter: (ICACHE_LINES), line:121
|vpiName:ICACHE_LINES
|INT:2
|vpiParameter:
\_parameter: (ICACHE_LINE_ADDR_W), line:123
|vpiName:ICACHE_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_LINE_W), line:124
|vpiName:ICACHE_LINE_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_SUB_LINE_ADDR_W), line:125
|vpiName:ICACHE_SUB_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_TAG_W), line:126
|vpiName:ICACHE_TAG_W
|INT:-2147483648
|vpiParameter:
\_parameter: (ICACHE_WAYS), line:122
|vpiName:ICACHE_WAYS
|INT:1
|vpiParameter:
\_parameter: (ITLB_DEPTH), line:146
|vpiName:ITLB_DEPTH
|INT:32
|vpiParameter:
\_parameter: (ITLB_WAYS), line:145
|vpiName:ITLB_WAYS
|INT:4
|vpiParameter:
\_parameter: (L1_CONNECTIONS), line:177
|vpiName:L1_CONNECTIONS
|INT:9
|vpiParameter:
\_parameter: (L1_DCACHE_ID), line:178
|vpiName:L1_DCACHE_ID
|INT:4
|vpiParameter:
\_parameter: (L1_DMMU_ID), line:179
|vpiName:L1_DMMU_ID
|INT:2
|vpiParameter:
\_parameter: (L1_ICACHE_ID), line:180
|vpiName:L1_ICACHE_ID
|INT:19
|vpiParameter:
\_parameter: (L1_IMMU_ID), line:181
|vpiName:L1_IMMU_ID
|INT:0
|vpiParameter:
\_parameter: (LS_UNIT_WB_ID), line:191
|vpiName:LS_UNIT_WB_ID
|INT:1
|vpiParameter:
\_parameter: (MAX_INFLIGHT_COUNT), line:167
|vpiName:MAX_INFLIGHT_COUNT
|INT:19
|vpiParameter:
\_parameter: (MEMORY_ADDR_H), line:103
|vpiName:MEMORY_ADDR_H
|INT:12
|vpiParameter:
\_parameter: (MEMORY_ADDR_L), line:102
|vpiName:MEMORY_ADDR_L
|INT:11
|vpiParameter:
\_parameter: (MEMORY_BIT_CHECK), line:104
|vpiName:MEMORY_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (MUL_UNIT_WB_ID), line:193
|vpiName:MUL_UNIT_WB_ID
|INT:512
|vpiParameter:
\_parameter: (NUM_UNITS), line:188
|vpiName:NUM_UNITS
|INT:2
|vpiParameter:
\_parameter: (NUM_WB_UNITS), line:186
|vpiName:NUM_WB_UNITS
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (RAS_DEPTH), line:161
|vpiName:RAS_DEPTH
|INT:2
|vpiParameter:
\_parameter: (RESET_VEC), line:39
|vpiName:RESET_VEC
|INT:-2147483648
|vpiParameter:
\_parameter: (SCRATCH_ADDR_H), line:99
|vpiName:SCRATCH_ADDR_H
|INT:9
|vpiParameter:
\_parameter: (SCRATCH_ADDR_L), line:98
|vpiName:SCRATCH_ADDR_L
|INT:8
|vpiParameter:
\_parameter: (SCRATCH_BIT_CHECK), line:100
|vpiName:SCRATCH_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (USE_AMO), line:70
|vpiName:USE_AMO
|INT:1
|vpiParameter:
\_parameter: (USE_BRANCH_PREDICTOR), line:158
|vpiName:USE_BRANCH_PREDICTOR
|INT:2
|vpiParameter:
\_parameter: (USE_BUS), line:88
|vpiName:USE_BUS
|INT:4
|vpiParameter:
\_parameter: (USE_DCACHE), line:92
|vpiName:USE_DCACHE
|INT:6
|vpiParameter:
\_parameter: (USE_DIV), line:49
|vpiName:USE_DIV
|INT:1
|vpiParameter:
\_parameter: (USE_DTAG_INVALIDATIONS), line:140
|vpiName:USE_DTAG_INVALIDATIONS
|INT:1879048191
|vpiParameter:
\_parameter: (USE_D_SCRATCH_MEM), line:79
|vpiName:USE_D_SCRATCH_MEM
|INT:3
|vpiParameter:
\_parameter: (USE_ICACHE), line:93
|vpiName:USE_ICACHE
|INT:7
|vpiParameter:
\_parameter: (USE_I_SCRATCH_MEM), line:78
|vpiName:USE_I_SCRATCH_MEM
|INT:2
|vpiParameter:
\_parameter: (USE_MUL), line:48
|vpiName:USE_MUL
|INT:1
|vpiParameter:
\_parameter: (WB_UNITS_WIDTH), line:187
|vpiName:WB_UNITS_WIDTH
|INT:32
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiModule:
\_module: work@csr_regs (csr_registers), file:third_party/cores/taiga/core/gc_unit.sv, line:260, parent:gc_unit_block
|vpiDefName:work@csr_regs
|vpiName:csr_registers
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers
|vpiPort:
\_port: (clk), line:28, parent:csr_registers
|vpiName:clk
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (clk), line:260
|vpiName:clk
|vpiActual:
\_logic_net: (clk), line:28, parent:gc_unit_block
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (clk), line:28, parent:csr_registers
|vpiName:clk
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.clk
|vpiNetType:36
|vpiPort:
\_port: (rst), line:29, parent:csr_registers
|vpiName:rst
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (rst), line:260
|vpiName:rst
|vpiActual:
\_logic_net: (rst), line:29, parent:gc_unit_block
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (rst), line:29, parent:csr_registers
|vpiName:rst
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.rst
|vpiNetType:36
|vpiPort:
\_port: (csr_inputs), line:32, parent:csr_registers
|vpiName:csr_inputs
|vpiDirection:1
|vpiTypedef:
\_struct_typespec: (csr_inputs_t), line:396
|vpiHighConn:
\_ref_obj: (csr_inputs), line:260
|vpiName:csr_inputs
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (csr_inputs), line:32, parent:csr_registers
|vpiName:csr_inputs
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.csr_inputs
|vpiPort:
\_port: (new_request), line:33, parent:csr_registers
|vpiName:new_request
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (new_request), line:260
|vpiName:new_request
|vpiActual:
\_logic_net: (new_request), line:54
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (new_request), line:172
|vpiName:new_request
|vpiNetType:36
|vpiPort:
\_port: (read_regs), line:34, parent:csr_registers
|vpiName:read_regs
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (read_regs), line:260
|vpiName:read_regs
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (read_regs), line:34, parent:csr_registers
|vpiName:read_regs
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.read_regs
|vpiPort:
\_port: (commit), line:35, parent:csr_registers
|vpiName:commit
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (commit), line:260
|vpiName:commit
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (commit), line:35, parent:csr_registers
|vpiName:commit
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.commit
|vpiPort:
\_port: (gc_exception), line:36, parent:csr_registers
|vpiName:gc_exception
|vpiDirection:1
|vpiTypedef:
\_struct_typespec: (exception_packet_t), line:263
|vpiHighConn:
\_ref_obj: (gc_exception), line:260
|vpiName:gc_exception
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (gc_exception), line:36, parent:csr_registers
|vpiName:gc_exception
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.gc_exception
|vpiPort:
\_port: (csr_exception), line:37, parent:csr_registers
|vpiName:csr_exception
|vpiDirection:2
|vpiTypedef:
\_struct_typespec: (exception_packet_t), line:263
|vpiHighConn:
\_ref_obj: (csr_exception), line:260
|vpiName:csr_exception
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (csr_exception), line:37, parent:csr_registers
|vpiName:csr_exception
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.csr_exception
|vpiPort:
\_port: (current_privilege), line:38, parent:csr_registers
|vpiName:current_privilege
|vpiDirection:2
|vpiHighConn:
\_ref_obj: (current_privilege), line:260
|vpiName:current_privilege
|vpiActual:
\_logic_net: (current_privilege), line:146, parent:gc_unit_block
|vpiName:current_privilege
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.current_privilege
|vpiNetType:36
|vpiRange:
\_range: , line:146
|vpiLeftRange:
\_constant: , line:146
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:146
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (current_privilege), line:38, parent:csr_registers
|vpiName:current_privilege
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.current_privilege
|vpiNetType:36
|vpiRange:
\_range: , line:38
|vpiLeftRange:
\_constant: , line:38
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:38
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiPort:
\_port: (instruction_issued_no_rd), line:41, parent:csr_registers
|vpiName:instruction_issued_no_rd
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (instruction_issued_no_rd), line:260
|vpiName:instruction_issued_no_rd
|vpiActual:
\_logic_net: (instruction_issued_no_rd), line:35, parent:gc_unit_block
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (instruction_issued_no_rd), line:41, parent:csr_registers
|vpiName:instruction_issued_no_rd
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.instruction_issued_no_rd
|vpiNetType:36
|vpiPort:
\_port: (mret), line:44, parent:csr_registers
|vpiName:mret
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (mret), line:260
|vpiName:mret
|vpiActual:
\_logic_net: (mret), line:140, parent:gc_unit_block
|vpiName:mret
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.mret
|vpiNetType:36
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (mret), line:44, parent:csr_registers
|vpiName:mret
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.mret
|vpiNetType:36
|vpiPort:
\_port: (sret), line:45, parent:csr_registers
|vpiName:sret
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (sret), line:260
|vpiName:sret
|vpiActual:
\_logic_net: (sret), line:141, parent:gc_unit_block
|vpiName:sret
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.sret
|vpiNetType:36
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (sret), line:45, parent:csr_registers
|vpiName:sret
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.sret
|vpiNetType:36
|vpiPort:
\_port: (tlb_on), line:48, parent:csr_registers
|vpiName:tlb_on
|vpiDirection:2
|vpiHighConn:
\_ref_obj: (tlb_on), line:260
|vpiName:tlb_on
|vpiActual:
\_logic_net: (tlb_on), line:45, parent:gc_unit_block
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (tlb_on), line:48, parent:csr_registers
|vpiName:tlb_on
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.tlb_on
|vpiNetType:36
|vpiPort:
\_port: (asid), line:49, parent:csr_registers
|vpiName:asid
|vpiDirection:2
|vpiHighConn:
\_ref_obj: (asid), line:260
|vpiName:asid
|vpiActual:
\_logic_net: (asid), line:46, parent:gc_unit_block
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (asid), line:49, parent:csr_registers
|vpiName:asid
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.asid
|vpiNetType:36
|vpiRange:
\_range: , line:49
|vpiLeftRange:
\_constant: , line:49
|vpiConstType:7
|vpiDecompile:10
|vpiSize:32
|INT:10
|vpiRightRange:
\_constant: , line:49
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiPort:
\_port: (immu), line:52, parent:csr_registers
|vpiName:immu
|vpiDirection:5
|vpiHighConn:
\_ref_obj: (immu), line:260
|vpiName:immu
|vpiActual:
\_interface: work@mmu_interface (immu), file:third_party/cores/taiga/core/taiga.sv, line:193
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_modport: (csr)
|vpiName:csr
|vpiIODecl:
\_io_decl: (ppn)
|vpiName:ppn
|vpiDirection:2
|vpiExpr:
\_logic_net: (ppn), line:182
|vpiName:ppn
|vpiNetType:36
|vpiRange:
\_range: , line:182
|vpiLeftRange:
\_constant: , line:182
|vpiConstType:7
|vpiDecompile:21
|vpiSize:32
|INT:21
|vpiRightRange:
\_constant: , line:182
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (mxr)
|vpiName:mxr
|vpiDirection:2
|vpiExpr:
\_logic_net: (mxr), line:183
|vpiName:mxr
|vpiNetType:36
|vpiIODecl:
\_io_decl: (pum)
|vpiName:pum
|vpiDirection:2
|vpiExpr:
\_logic_net: (pum), line:184
|vpiName:pum
|vpiNetType:36
|vpiIODecl:
\_io_decl: (privilege)
|vpiName:privilege
|vpiDirection:2
|vpiExpr:
\_logic_net: (privilege), line:185
|vpiName:privilege
|vpiNetType:36
|vpiRange:
\_range: , line:185
|vpiLeftRange:
\_constant: , line:185
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:185
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiInterface:
\_interface: work@mmu_interface (immu), file:third_party/cores/taiga/core/gc_unit.sv, line:260
|vpiDefName:work@mmu_interface
|vpiName:immu
|vpiModport:
\_modport: (csr)
|vpiModport:
\_modport: (mmu)
|vpiName:mmu
|vpiIODecl:
\_io_decl: (virtual_address)
|vpiName:virtual_address
|vpiDirection:1
|vpiExpr:
\_logic_net: (virtual_address), line:175
|vpiName:virtual_address
|vpiNetType:36
|vpiRange:
\_range: , line:175
|vpiLeftRange:
\_constant: , line:175
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:175
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (new_request)
|vpiName:new_request
|vpiDirection:1
|vpiExpr:
\_logic_net: (new_request), line:172
|vpiIODecl:
\_io_decl: (execute)
|vpiName:execute
|vpiDirection:1
|vpiExpr:
\_logic_net: (execute), line:173
|vpiName:execute
|vpiNetType:36
|vpiIODecl:
\_io_decl: (rnw)
|vpiName:rnw
|vpiDirection:1
|vpiExpr:
\_logic_net: (rnw), line:174
|vpiName:rnw
|vpiNetType:36
|vpiIODecl:
\_io_decl: (ppn)
|vpiName:ppn
|vpiDirection:1
|vpiExpr:
\_logic_net: (ppn), line:182
|vpiIODecl:
\_io_decl: (mxr)
|vpiName:mxr
|vpiDirection:1
|vpiExpr:
\_logic_net: (mxr), line:183
|vpiIODecl:
\_io_decl: (pum)
|vpiName:pum
|vpiDirection:1
|vpiExpr:
\_logic_net: (pum), line:184
|vpiIODecl:
\_io_decl: (privilege)
|vpiName:privilege
|vpiDirection:1
|vpiExpr:
\_logic_net: (privilege), line:185
|vpiIODecl:
\_io_decl: (write_entry)
|vpiName:write_entry
|vpiDirection:2
|vpiExpr:
\_logic_net: (write_entry), line:178
|vpiName:write_entry
|vpiNetType:36
|vpiIODecl:
\_io_decl: (new_phys_addr)
|vpiName:new_phys_addr
|vpiDirection:2
|vpiExpr:
\_logic_net: (new_phys_addr), line:179
|vpiName:new_phys_addr
|vpiNetType:36
|vpiRange:
\_range: , line:179
|vpiLeftRange:
\_constant: , line:179
|vpiConstType:7
|vpiDecompile:19
|vpiSize:32
|INT:19
|vpiRightRange:
\_constant: , line:179
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiInterface:
\_interface: work@mmu_interface (immu), file:third_party/cores/taiga/core/gc_unit.sv, line:260
|vpiModport:
\_modport: (tlb)
|vpiName:tlb
|vpiIODecl:
\_io_decl: (write_entry)
|vpiName:write_entry
|vpiDirection:1
|vpiExpr:
\_logic_net: (write_entry), line:178
|vpiIODecl:
\_io_decl: (new_phys_addr)
|vpiName:new_phys_addr
|vpiDirection:1
|vpiExpr:
\_logic_net: (new_phys_addr), line:179
|vpiIODecl:
\_io_decl: (new_request)
|vpiName:new_request
|vpiDirection:2
|vpiExpr:
\_logic_net: (new_request), line:172
|vpiIODecl:
\_io_decl: (virtual_address)
|vpiName:virtual_address
|vpiDirection:2
|vpiExpr:
\_logic_net: (virtual_address), line:175
|vpiIODecl:
\_io_decl: (execute)
|vpiName:execute
|vpiDirection:2
|vpiExpr:
\_logic_net: (execute), line:173
|vpiIODecl:
\_io_decl: (rnw)
|vpiName:rnw
|vpiDirection:2
|vpiExpr:
\_logic_net: (rnw), line:174
|vpiInterface:
\_interface: work@mmu_interface (immu), file:third_party/cores/taiga/core/gc_unit.sv, line:260
|vpiPort:
\_port: (dmmu), line:53, parent:csr_registers
|vpiName:dmmu
|vpiDirection:5
|vpiHighConn:
\_ref_obj: (dmmu), line:260
|vpiName:dmmu
|vpiActual:
\_interface: work@mmu_interface (dmmu), file:third_party/cores/taiga/core/taiga.sv, line:193
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_modport: (csr)
|vpiName:csr
|vpiIODecl:
\_io_decl: (ppn)
|vpiName:ppn
|vpiDirection:2
|vpiExpr:
\_logic_net: (ppn), line:182
|vpiIODecl:
\_io_decl: (mxr)
|vpiName:mxr
|vpiDirection:2
|vpiExpr:
\_logic_net: (mxr), line:183
|vpiIODecl:
\_io_decl: (pum)
|vpiName:pum
|vpiDirection:2
|vpiExpr:
\_logic_net: (pum), line:184
|vpiIODecl:
\_io_decl: (privilege)
|vpiName:privilege
|vpiDirection:2
|vpiExpr:
\_logic_net: (privilege), line:185
|vpiInterface:
\_interface: work@mmu_interface (dmmu), file:third_party/cores/taiga/core/gc_unit.sv, line:260
|vpiDefName:work@mmu_interface
|vpiName:dmmu
|vpiModport:
\_modport: (csr)
|vpiModport:
\_modport: (mmu)
|vpiName:mmu
|vpiIODecl:
\_io_decl: (virtual_address)
|vpiName:virtual_address
|vpiDirection:1
|vpiExpr:
\_logic_net: (virtual_address), line:175
|vpiIODecl:
\_io_decl: (new_request)
|vpiName:new_request
|vpiDirection:1
|vpiExpr:
\_logic_net: (new_request), line:172
|vpiIODecl:
\_io_decl: (execute)
|vpiName:execute
|vpiDirection:1
|vpiExpr:
\_logic_net: (execute), line:173
|vpiIODecl:
\_io_decl: (rnw)
|vpiName:rnw
|vpiDirection:1
|vpiExpr:
\_logic_net: (rnw), line:174
|vpiIODecl:
\_io_decl: (ppn)
|vpiName:ppn
|vpiDirection:1
|vpiExpr:
\_logic_net: (ppn), line:182
|vpiIODecl:
\_io_decl: (mxr)
|vpiName:mxr
|vpiDirection:1
|vpiExpr:
\_logic_net: (mxr), line:183
|vpiIODecl:
\_io_decl: (pum)
|vpiName:pum
|vpiDirection:1
|vpiExpr:
\_logic_net: (pum), line:184
|vpiIODecl:
\_io_decl: (privilege)
|vpiName:privilege
|vpiDirection:1
|vpiExpr:
\_logic_net: (privilege), line:185
|vpiIODecl:
\_io_decl: (write_entry)
|vpiName:write_entry
|vpiDirection:2
|vpiExpr:
\_logic_net: (write_entry), line:178
|vpiIODecl:
\_io_decl: (new_phys_addr)
|vpiName:new_phys_addr
|vpiDirection:2
|vpiExpr:
\_logic_net: (new_phys_addr), line:179
|vpiInterface:
\_interface: work@mmu_interface (dmmu), file:third_party/cores/taiga/core/gc_unit.sv, line:260
|vpiModport:
\_modport: (tlb)
|vpiName:tlb
|vpiIODecl:
\_io_decl: (write_entry)
|vpiName:write_entry
|vpiDirection:1
|vpiExpr:
\_logic_net: (write_entry), line:178
|vpiIODecl:
\_io_decl: (new_phys_addr)
|vpiName:new_phys_addr
|vpiDirection:1
|vpiExpr:
\_logic_net: (new_phys_addr), line:179
|vpiIODecl:
\_io_decl: (new_request)
|vpiName:new_request
|vpiDirection:2
|vpiExpr:
\_logic_net: (new_request), line:172
|vpiIODecl:
\_io_decl: (virtual_address)
|vpiName:virtual_address
|vpiDirection:2
|vpiExpr:
\_logic_net: (virtual_address), line:175
|vpiIODecl:
\_io_decl: (execute)
|vpiName:execute
|vpiDirection:2
|vpiExpr:
\_logic_net: (execute), line:173
|vpiIODecl:
\_io_decl: (rnw)
|vpiName:rnw
|vpiDirection:2
|vpiExpr:
\_logic_net: (rnw), line:174
|vpiInterface:
\_interface: work@mmu_interface (dmmu), file:third_party/cores/taiga/core/gc_unit.sv, line:260
|vpiPort:
\_port: (instruction_complete), line:56, parent:csr_registers
|vpiName:instruction_complete
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (instruction_complete), line:260
|vpiName:instruction_complete
|vpiActual:
\_logic_net: (instruction_complete), line:53, parent:gc_unit_block
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (instruction_complete), line:56, parent:csr_registers
|vpiName:instruction_complete
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.instruction_complete
|vpiNetType:36
|vpiPort:
\_port: (interrupt), line:60, parent:csr_registers
|vpiName:interrupt
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (interrupt), line:260
|vpiName:interrupt
|vpiActual:
\_logic_net: (interrupt), line:59, parent:gc_unit_block
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (interrupt), line:60, parent:csr_registers
|vpiName:interrupt
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.interrupt
|vpiNetType:36
|vpiPort:
\_port: (timer_interrupt), line:61, parent:csr_registers
|vpiName:timer_interrupt
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (timer_interrupt), line:260
|vpiName:timer_interrupt
|vpiActual:
\_logic_net: (timer_interrupt), line:60, parent:gc_unit_block
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (timer_interrupt), line:61, parent:csr_registers
|vpiName:timer_interrupt
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.timer_interrupt
|vpiNetType:36
|vpiPort:
\_port: (wb_csr), line:63, parent:csr_registers
|vpiName:wb_csr
|vpiDirection:2
|vpiHighConn:
\_ref_obj: (wb_csr), line:260
|vpiName:wb_csr
|vpiActual:
\_logic_net: (wb_csr), line:142, parent:gc_unit_block
|vpiName:wb_csr
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.wb_csr
|vpiNetType:36
|vpiRange:
\_range: , line:142
|vpiLeftRange:
\_constant: , line:142
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiRightRange:
\_constant: , line:142
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (wb_csr), line:63, parent:csr_registers
|vpiName:wb_csr
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.wb_csr
|vpiNetType:36
|vpiRange:
\_range: , line:63
|vpiLeftRange:
\_constant: , line:63
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiRightRange:
\_constant: , line:63
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiPort:
\_port: (trap_pc), line:64, parent:csr_registers
|vpiName:trap_pc
|vpiDirection:2
|vpiHighConn:
\_ref_obj: (trap_pc), line:260
|vpiName:trap_pc
|vpiActual:
\_logic_net: (trap_pc), line:147, parent:gc_unit_block
|vpiName:trap_pc
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.trap_pc
|vpiNetType:36
|vpiRange:
\_range: , line:147
|vpiLeftRange:
\_constant: , line:147
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:147
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (trap_pc), line:64, parent:csr_registers
|vpiName:trap_pc
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.trap_pc
|vpiNetType:36
|vpiRange:
\_range: , line:64
|vpiLeftRange:
\_constant: , line:64
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:64
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiPort:
\_port: (csr_mepc), line:65, parent:csr_registers
|vpiName:csr_mepc
|vpiDirection:2
|vpiHighConn:
\_ref_obj: (csr_mepc), line:260
|vpiName:csr_mepc
|vpiActual:
\_logic_net: (csr_mepc), line:148, parent:gc_unit_block
|vpiName:csr_mepc
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_mepc
|vpiNetType:36
|vpiRange:
\_range: , line:148
|vpiLeftRange:
\_constant: , line:148
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:148
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (csr_mepc), line:65, parent:csr_registers
|vpiName:csr_mepc
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.csr_mepc
|vpiNetType:36
|vpiRange:
\_range: , line:65
|vpiLeftRange:
\_constant: , line:65
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:65
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiPort:
\_port: (csr_sepc), line:66, parent:csr_registers
|vpiName:csr_sepc
|vpiDirection:2
|vpiHighConn:
\_ref_obj: (csr_sepc), line:260
|vpiName:csr_sepc
|vpiActual:
\_logic_net: (csr_sepc), line:149, parent:gc_unit_block
|vpiName:csr_sepc
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_sepc
|vpiNetType:36
|vpiRange:
\_range: , line:149
|vpiLeftRange:
\_constant: , line:149
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:149
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (csr_sepc), line:66, parent:csr_registers
|vpiName:csr_sepc
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.csr_sepc
|vpiNetType:36
|vpiRange:
\_range: , line:66
|vpiLeftRange:
\_constant: , line:66
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:66
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiGenScopeArray:
\_gen_scope_array: (genblk1), line:191, parent:csr_registers
|vpiName:genblk1
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1
|vpiGenScope:
\_gen_scope: , parent:genblk1
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1
|vpiNet:
\_logic_net: (trap_return_privilege_level), line:200
|vpiName:trap_return_privilege_level
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1.trap_return_privilege_level
|vpiNetType:36
|vpiRange:
\_range: , line:200
|vpiLeftRange:
\_constant: , line:200
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:200
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (exception_privilege_level), line:200
|vpiName:exception_privilege_level
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1.exception_privilege_level
|vpiNetType:36
|vpiRange:
\_range: , line:200
|vpiLeftRange:
\_constant: , line:200
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:200
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (interrupt_privilege_level), line:200
|vpiName:interrupt_privilege_level
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1.interrupt_privilege_level
|vpiNetType:36
|vpiRange:
\_range: , line:200
|vpiLeftRange:
\_constant: , line:200
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:200
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (mstatus_exception), line:201
|vpiName:mstatus_exception
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1.mstatus_exception
|vpiNet:
\_logic_net: (mstatus_return), line:201
|vpiName:mstatus_return
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1.mstatus_return
|vpiNet:
\_logic_net: (mstatus_rst), line:201
|vpiName:mstatus_rst
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1.mstatus_rst
|vpiNet:
\_logic_net: (mstatus_new), line:201
|vpiName:mstatus_new
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1.mstatus_new
|vpiNet:
\_logic_net: (mstatus_mmask), line:202
|vpiName:mstatus_mmask
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1.mstatus_mmask
|vpiNet:
\_logic_net: (mstatus_mask), line:202
|vpiName:mstatus_mask
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1.mstatus_mask
|vpiNet:
\_logic_net: (exception_delegated), line:203
|vpiName:exception_delegated
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1.exception_delegated
|vpiNetType:36
|vpiNet:
\_logic_net: (interrupt_delegated), line:204
|vpiName:interrupt_delegated
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1.interrupt_delegated
|vpiNetType:36
|vpiNet:
\_logic_net: (medeleg_mask), line:289
|vpiName:medeleg_mask
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1.medeleg_mask
|vpiNetType:36
|vpiRange:
\_range: , line:289
|vpiLeftRange:
\_constant: , line:289
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:289
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (mideleg_mask), line:311
|vpiName:mideleg_mask
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1.mideleg_mask
|vpiNetType:36
|vpiRange:
\_range: , line:311
|vpiLeftRange:
\_constant: , line:311
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:311
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (mcause_mask), line:370
|vpiName:mcause_mask
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1.mcause_mask
|vpiNetType:36
|vpiRange:
\_range: , line:370
|vpiLeftRange:
\_constant: , line:370
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiRightRange:
\_constant: , line:370
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (scratch_reg_write), line:389
|vpiName:scratch_reg_write
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1.scratch_reg_write
|vpiNetType:36
|vpiProcess:
\_always: , line:213
|vpiAlwaysType:2
|vpiStmt:
\_begin: , line:213
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1
|vpiStmt:
\_if_else: , line:214
|vpiCondition:
\_operation: , line:214
|vpiOpType:29
|vpiOperand:
\_ref_obj: (mret), line:214
|vpiName:mret
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1.mret
|vpiOperand:
\_ref_obj: (sret), line:214
|vpiName:sret
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1.sret
|vpiStmt:
\_assignment: , line:215
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (next_privilege_level), line:215
|vpiName:next_privilege_level
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1.next_privilege_level
|vpiRhs:
\_ref_obj: (trap_return_privilege_level), line:215
|vpiName:trap_return_privilege_level
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1.trap_return_privilege_level
|vpiElseStmt:
\_if_else: , line:216
|vpiCondition:
\_ref_obj: (interrupt), line:216
|vpiName:interrupt
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1.interrupt
|vpiStmt:
\_assignment: , line:217
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (next_privilege_level), line:217
|vpiName:next_privilege_level
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1.next_privilege_level
|vpiRhs:
\_ref_obj: (interrupt_privilege_level), line:217
|vpiName:interrupt_privilege_level
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1.interrupt_privilege_level
|vpiElseStmt:
\_if_else: , line:218
|vpiCondition:
\_ref_obj: (gc_exception.valid), line:218
|vpiName:gc_exception.valid
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1.gc_exception.valid
|vpiStmt:
\_assignment: , line:219
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (next_privilege_level), line:219
|vpiName:next_privilege_level
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1.next_privilege_level
|vpiRhs:
\_ref_obj: (exception_privilege_level), line:219
|vpiName:exception_privilege_level
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1.exception_privilege_level
|vpiElseStmt:
\_assignment: , line:221
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (next_privilege_level), line:221
|vpiName:next_privilege_level
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1.next_privilege_level
|vpiRhs:
\_ref_obj: (privilege_level), line:221
|vpiName:privilege_level
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1.privilege_level
|vpiProcess:
\_always: , line:225
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:225
|vpiCondition:
\_operation: , line:225
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:225
|vpiName:clk
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1.clk
|vpiStmt:
\_begin: , line:225
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1
|vpiStmt:
\_if_else: , line:226
|vpiCondition:
\_ref_obj: (rst), line:226
|vpiName:rst
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1.rst
|vpiStmt:
\_assignment: , line:227
|vpiOpType:82
|vpiLhs:
\_ref_obj: (privilege_level), line:227
|vpiName:privilege_level
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1.privilege_level
|vpiRhs:
\_ref_obj: (MACHINE_PRIVILEGE), line:227
|vpiName:MACHINE_PRIVILEGE
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1.MACHINE_PRIVILEGE
|vpiElseStmt:
\_assignment: , line:229
|vpiOpType:82
|vpiLhs:
\_ref_obj: (privilege_level), line:229
|vpiName:privilege_level
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1.privilege_level
|vpiRhs:
\_ref_obj: (next_privilege_level), line:229
|vpiName:next_privilege_level
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1.next_privilege_level
|vpiProcess:
\_always: , line:233
|vpiAlwaysType:2
|vpiStmt:
\_begin: , line:233
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1
|vpiStmt:
\_assignment: , line:234
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (mstatus_exception), line:234
|vpiName:mstatus_exception
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1.mstatus_exception
|vpiRhs:
\_ref_obj: (mstatus), line:234
|vpiName:mstatus
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1.mstatus
|vpiStmt:
\_case_stmt: , line:235
|vpiCaseType:1
|vpiCondition:
\_ref_obj: (next_privilege_level), line:235
|vpiName:next_privilege_level
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1.next_privilege_level
|vpiCaseItem:
\_case_item: , line:236
|vpiExpr:
\_ref_obj: (SUPERVISOR_PRIVILEGE), line:236
|vpiName:SUPERVISOR_PRIVILEGE
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1.SUPERVISOR_PRIVILEGE
|vpiStmt:
\_begin: , line:236
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1
|vpiStmt:
\_assignment: , line:237
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (mstatus_exception.spie), line:237
|vpiName:mstatus_exception.spie
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1.mstatus_exception.spie
|vpiRhs:
\_operation: , line:237
|vpiOpType:32
|vpiOperand:
\_operation: , line:237
|vpiOpType:14
|vpiOperand:
\_ref_obj: (privilege_level), line:237
|vpiName:privilege_level
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1.privilege_level
|vpiOperand:
\_ref_obj: (SUPERVISOR_PRIVILEGE), line:237
|vpiName:SUPERVISOR_PRIVILEGE
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1.SUPERVISOR_PRIVILEGE
|vpiOperand:
\_ref_obj: (mstatus.sie), line:237
|vpiName:mstatus.sie
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1.mstatus.sie
|vpiOperand:
\_ref_obj: (mstatus.uie), line:237
|vpiName:mstatus.uie
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1.mstatus.uie
|vpiStmt:
\_assignment: , line:238
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (mstatus_exception.sie), line:238
|vpiName:mstatus_exception.sie
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1.mstatus_exception.sie
|vpiRhs:
\_constant: , line:238
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiStmt:
\_assignment: , line:239
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (mstatus_exception.spp), line:239
|vpiName:mstatus_exception.spp
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1.mstatus_exception.spp
|vpiRhs:
\_bit_select: (privilege_level), line:239
|vpiName:privilege_level
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1.privilege_level
|vpiIndex:
\_constant: , line:239
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiCaseItem:
\_case_item: , line:241
|vpiStmt:
\_begin: , line:241
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1
|vpiStmt:
\_assignment: , line:242
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (mstatus_exception.mpie), line:242
|vpiName:mstatus_exception.mpie
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1.mstatus_exception.mpie
|vpiRhs:
\_operation: , line:242
|vpiOpType:32
|vpiOperand:
\_operation: , line:242
|vpiOpType:14
|vpiOperand:
\_ref_obj: (privilege_level), line:242
|vpiName:privilege_level
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1.privilege_level
|vpiOperand:
\_ref_obj: (MACHINE_PRIVILEGE), line:242
|vpiName:MACHINE_PRIVILEGE
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1.MACHINE_PRIVILEGE
|vpiOperand:
\_ref_obj: (mstatus.mie), line:242
|vpiName:mstatus.mie
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1.mstatus.mie
|vpiOperand:
\_operation: , line:242
|vpiOpType:32
|vpiOperand:
\_operation: , line:242
|vpiOpType:14
|vpiOperand:
\_ref_obj: (privilege_level), line:242
|vpiName:privilege_level
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1.privilege_level
|vpiOperand:
\_ref_obj: (SUPERVISOR_PRIVILEGE), line:242
|vpiName:SUPERVISOR_PRIVILEGE
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1.SUPERVISOR_PRIVILEGE
|vpiOperand:
\_ref_obj: (mstatus.sie), line:242
|vpiName:mstatus.sie
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1.mstatus.sie
|vpiOperand:
\_ref_obj: (mstatus.uie), line:242
|vpiName:mstatus.uie
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1.mstatus.uie
|vpiStmt:
\_assignment: , line:243
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (mstatus_exception.mie), line:243
|vpiName:mstatus_exception.mie
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1.mstatus_exception.mie
|vpiRhs:
\_constant: , line:243
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiStmt:
\_assignment: , line:244
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (mstatus_exception.mpp), line:244
|vpiName:mstatus_exception.mpp
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1.mstatus_exception.mpp
|vpiRhs:
\_ref_obj: (privilege_level), line:244
|vpiName:privilege_level
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1.privilege_level
|vpiProcess:
\_always: , line:250
|vpiAlwaysType:2
|vpiStmt:
\_begin: , line:250
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1
|vpiStmt:
\_assignment: , line:251
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (mstatus_return), line:251
|vpiName:mstatus_return
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1.mstatus_return
|vpiRhs:
\_ref_obj: (mstatus), line:251
|vpiName:mstatus
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1.mstatus
|vpiStmt:
\_if_else: , line:252
|vpiCondition:
\_ref_obj: (sret), line:252
|vpiName:sret
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1.sret
|vpiStmt:
\_begin: , line:252
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1
|vpiStmt:
\_assignment: , line:253
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (mstatus_return.sie), line:253
|vpiName:mstatus_return.sie
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1.mstatus_return.sie
|vpiRhs:
\_ref_obj: (mstatus_return.spie), line:253
|vpiName:mstatus_return.spie
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1.mstatus_return.spie
|vpiStmt:
\_assignment: , line:254
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (mstatus_return.spie), line:254
|vpiName:mstatus_return.spie
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1.mstatus_return.spie
|vpiRhs:
\_constant: , line:254
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiStmt:
\_assignment: , line:255
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (mstatus_return.spp), line:255
|vpiName:mstatus_return.spp
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1.mstatus_return.spp
|vpiRhs:
\_constant: , line:255
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiElseStmt:
\_if_stmt: , line:256
|vpiCondition:
\_ref_obj: (mret), line:256
|vpiName:mret
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1.mret
|vpiStmt:
\_begin: , line:256
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1
|vpiStmt:
\_assignment: , line:257
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (mstatus_return.mie), line:257
|vpiName:mstatus_return.mie
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1.mstatus_return.mie
|vpiRhs:
\_ref_obj: (mstatus.mpie), line:257
|vpiName:mstatus.mpie
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1.mstatus.mpie
|vpiStmt:
\_assignment: , line:258
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (mstatus_return.mpie), line:258
|vpiName:mstatus_return.mpie
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1.mstatus_return.mpie
|vpiRhs:
\_constant: , line:258
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiStmt:
\_assignment: , line:259
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (mstatus_return.mpp), line:259
|vpiName:mstatus_return.mpp
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1.mstatus_return.mpp
|vpiRhs:
\_ref_obj: (USER_PRIVILEGE), line:259
|vpiName:USER_PRIVILEGE
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1.USER_PRIVILEGE
|vpiProcess:
\_always: , line:267
|vpiAlwaysType:2
|vpiStmt:
\_begin: , line:267
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1
|vpiStmt:
\_if_else: , line:268
|vpiCondition:
\_operation: , line:268
|vpiOpType:29
|vpiOperand:
\_bit_select: (mwrite_decoder), line:268
|vpiName:mwrite_decoder
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1.mwrite_decoder
|vpiIndex:
\_part_select: , line:268, parent:MSTATUS
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (MSTATUS)
|vpiLeftRange:
\_constant: , line:268
|vpiConstType:7
|vpiDecompile:5
|vpiSize:32
|INT:5
|vpiRightRange:
\_constant: , line:268
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiOperand:
\_bit_select: (swrite_decoder), line:268
|vpiName:swrite_decoder
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1.swrite_decoder
|vpiIndex:
\_part_select: , line:268, parent:SSTATUS
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (SSTATUS)
|vpiLeftRange:
\_constant: , line:268
|vpiConstType:7
|vpiDecompile:5
|vpiSize:32
|INT:5
|vpiRightRange:
\_constant: , line:268
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiStmt:
\_assignment: , line:269
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (mstatus_new), line:269
|vpiName:mstatus_new
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1.mstatus_new
|vpiRhs:
\_operation: , line:269
|vpiOpType:28
|vpiOperand:
\_ref_obj: (updated_csr), line:269
|vpiName:updated_csr
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1.updated_csr
|vpiOperand:
\_ref_obj: (mstatus_mask), line:269
|vpiName:mstatus_mask
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1.mstatus_mask
|vpiElseStmt:
\_if_else: , line:270
|vpiCondition:
\_operation: , line:270
|vpiOpType:29
|vpiOperand:
\_ref_obj: (interrupt), line:270
|vpiName:interrupt
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1.interrupt
|vpiOperand:
\_ref_obj: (gc_exception.valid), line:270
|vpiName:gc_exception.valid
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1.gc_exception.valid
|vpiStmt:
\_assignment: , line:271
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (mstatus_new), line:271
|vpiName:mstatus_new
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1.mstatus_new
|vpiRhs:
\_ref_obj: (mstatus_exception), line:271
|vpiName:mstatus_exception
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1.mstatus_exception
|vpiElseStmt:
\_if_else: , line:272
|vpiCondition:
\_operation: , line:272
|vpiOpType:29
|vpiOperand:
\_ref_obj: (mret), line:272
|vpiName:mret
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1.mret
|vpiOperand:
\_ref_obj: (sret), line:272
|vpiName:sret
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1.sret
|vpiStmt:
\_assignment: , line:273
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (mstatus_new), line:273
|vpiName:mstatus_new
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1.mstatus_new
|vpiRhs:
\_ref_obj: (mstatus_return), line:273
|vpiName:mstatus_return
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1.mstatus_return
|vpiElseStmt:
\_assignment: , line:275
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (mstatus_new), line:275
|vpiName:mstatus_new
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1.mstatus_new
|vpiRhs:
\_ref_obj: (mstatus), line:275
|vpiName:mstatus
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1.mstatus
|vpiProcess:
\_always: , line:279
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:279
|vpiCondition:
\_operation: , line:279
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:279
|vpiName:clk
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1.clk
|vpiStmt:
\_begin: , line:279
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1
|vpiStmt:
\_if_else: , line:280
|vpiCondition:
\_ref_obj: (rst), line:280
|vpiName:rst
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1.rst
|vpiStmt:
\_assignment: , line:281
|vpiOpType:82
|vpiLhs:
\_ref_obj: (mstatus), line:281
|vpiName:mstatus
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1.mstatus
|vpiRhs:
\_ref_obj: (mstatus_rst), line:281
|vpiName:mstatus_rst
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1.mstatus_rst
|vpiElseStmt:
\_assignment: , line:283
|vpiOpType:82
|vpiLhs:
\_ref_obj: (mstatus), line:283
|vpiName:mstatus
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1.mstatus
|vpiRhs:
\_ref_obj: (mstatus_new), line:283
|vpiName:mstatus_new
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1.mstatus_new
|vpiProcess:
\_always: , line:290
|vpiAlwaysType:2
|vpiStmt:
\_begin: , line:290
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1
|vpiStmt:
\_assignment: , line:291
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (medeleg_mask), line:291
|vpiName:medeleg_mask
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1.medeleg_mask
|vpiRhs:
\_constant: , line:291
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiStmt:
\_assignment: , line:292
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_bit_select: (medeleg_mask), line:292
|vpiName:medeleg_mask
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1.medeleg_mask
|vpiIndex:
\_ref_obj: (INST_ADDR_MISSALIGNED), line:292
|vpiName:INST_ADDR_MISSALIGNED
|vpiRhs:
\_constant: , line:292
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiStmt:
\_assignment: , line:293
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_bit_select: (medeleg_mask), line:293
|vpiName:medeleg_mask
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1.medeleg_mask
|vpiIndex:
\_ref_obj: (INST_ACCESS_FAULT), line:293
|vpiName:INST_ACCESS_FAULT
|vpiRhs:
\_constant: , line:293
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiStmt:
\_assignment: , line:294
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_bit_select: (medeleg_mask), line:294
|vpiName:medeleg_mask
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1.medeleg_mask
|vpiIndex:
\_ref_obj: (ILLEGAL_INST), line:294
|vpiName:ILLEGAL_INST
|vpiRhs:
\_constant: , line:294
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiStmt:
\_assignment: , line:295
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_bit_select: (medeleg_mask), line:295
|vpiName:medeleg_mask
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1.medeleg_mask
|vpiIndex:
\_ref_obj: (BREAK), line:295
|vpiName:BREAK
|vpiRhs:
\_constant: , line:295
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiStmt:
\_assignment: , line:296
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_bit_select: (medeleg_mask), line:296
|vpiName:medeleg_mask
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1.medeleg_mask
|vpiIndex:
\_ref_obj: (LOAD_FAULT), line:296
|vpiName:LOAD_FAULT
|vpiRhs:
\_constant: , line:296
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiStmt:
\_assignment: , line:297
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_bit_select: (medeleg_mask), line:297
|vpiName:medeleg_mask
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1.medeleg_mask
|vpiIndex:
\_ref_obj: (STORE_AMO_FAULT), line:297
|vpiName:STORE_AMO_FAULT
|vpiRhs:
\_constant: , line:297
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiStmt:
\_assignment: , line:298
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_bit_select: (medeleg_mask), line:298
|vpiName:medeleg_mask
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1.medeleg_mask
|vpiIndex:
\_ref_obj: (ECALL_U), line:298
|vpiName:ECALL_U
|vpiRhs:
\_constant: , line:298
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiStmt:
\_assignment: , line:299
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_bit_select: (medeleg_mask), line:299
|vpiName:medeleg_mask
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1.medeleg_mask
|vpiIndex:
\_ref_obj: (INST_PAGE_FAULT), line:299
|vpiName:INST_PAGE_FAULT
|vpiRhs:
\_constant: , line:299
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiStmt:
\_assignment: , line:300
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_bit_select: (medeleg_mask), line:300
|vpiName:medeleg_mask
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1.medeleg_mask
|vpiIndex:
\_ref_obj: (LOAD_PAGE_FAULT), line:300
|vpiName:LOAD_PAGE_FAULT
|vpiRhs:
\_constant: , line:300
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiStmt:
\_assignment: , line:301
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_bit_select: (medeleg_mask), line:301
|vpiName:medeleg_mask
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1.medeleg_mask
|vpiIndex:
\_ref_obj: (STORE_OR_AMO_PAGE_FAULT), line:301
|vpiName:STORE_OR_AMO_PAGE_FAULT
|vpiRhs:
\_constant: , line:301
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiProcess:
\_always: , line:303
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:303
|vpiCondition:
\_operation: , line:303
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:303
|vpiName:clk
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1.clk
|vpiStmt:
\_begin: , line:303
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1
|vpiStmt:
\_if_else: , line:304
|vpiCondition:
\_ref_obj: (rst), line:304
|vpiName:rst
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1.rst
|vpiStmt:
\_assignment: , line:305
|vpiOpType:82
|vpiLhs:
\_ref_obj: (medeleg), line:305
|vpiName:medeleg
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1.medeleg
|vpiRhs:
\_constant: , line:305
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiElseStmt:
\_if_stmt: , line:306
|vpiCondition:
\_bit_select: (mwrite_decoder), line:306
|vpiName:mwrite_decoder
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1.mwrite_decoder
|vpiIndex:
\_part_select: , line:306, parent:MEDELEG
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (MEDELEG)
|vpiLeftRange:
\_constant: , line:306
|vpiConstType:7
|vpiDecompile:5
|vpiSize:32
|INT:5
|vpiRightRange:
\_constant: , line:306
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiStmt:
\_assignment: , line:307
|vpiOpType:82
|vpiLhs:
\_ref_obj: (medeleg), line:307
|vpiName:medeleg
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1.medeleg
|vpiRhs:
\_operation: , line:307
|vpiOpType:28
|vpiOperand:
\_ref_obj: (updated_csr), line:307
|vpiName:updated_csr
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1.updated_csr
|vpiOperand:
\_ref_obj: (medeleg_mask), line:307
|vpiName:medeleg_mask
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1.medeleg_mask
|vpiProcess:
\_always: , line:312
|vpiAlwaysType:2
|vpiStmt:
\_begin: , line:312
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1
|vpiStmt:
\_assignment: , line:313
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (mideleg_mask), line:313
|vpiName:mideleg_mask
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1.mideleg_mask
|vpiRhs:
\_constant: , line:313
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiStmt:
\_assignment: , line:314
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_bit_select: (mideleg_mask), line:314
|vpiName:mideleg_mask
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1.mideleg_mask
|vpiIndex:
\_ref_obj: (S_SOFTWARE_INTERRUPT), line:314
|vpiName:S_SOFTWARE_INTERRUPT
|vpiRhs:
\_constant: , line:314
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiStmt:
\_assignment: , line:315
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_bit_select: (mideleg_mask), line:315
|vpiName:mideleg_mask
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1.mideleg_mask
|vpiIndex:
\_ref_obj: (S_TIMER_INTERRUPT), line:315
|vpiName:S_TIMER_INTERRUPT
|vpiRhs:
\_constant: , line:315
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiStmt:
\_assignment: , line:316
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_bit_select: (mideleg_mask), line:316
|vpiName:mideleg_mask
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1.mideleg_mask
|vpiIndex:
\_ref_obj: (S_EXTERNAL_INTERRUPT), line:316
|vpiName:S_EXTERNAL_INTERRUPT
|vpiRhs:
\_constant: , line:316
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiProcess:
\_always: , line:318
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:318
|vpiCondition:
\_operation: , line:318
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:318
|vpiName:clk
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1.clk
|vpiStmt:
\_begin: , line:318
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1
|vpiStmt:
\_if_else: , line:319
|vpiCondition:
\_ref_obj: (rst), line:319
|vpiName:rst
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1.rst
|vpiStmt:
\_assignment: , line:320
|vpiOpType:82
|vpiLhs:
\_ref_obj: (mideleg), line:320
|vpiName:mideleg
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1.mideleg
|vpiRhs:
\_constant: , line:320
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiElseStmt:
\_if_stmt: , line:321
|vpiCondition:
\_bit_select: (mwrite_decoder), line:321
|vpiName:mwrite_decoder
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1.mwrite_decoder
|vpiIndex:
\_part_select: , line:321, parent:MIDELEG
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (MIDELEG)
|vpiLeftRange:
\_constant: , line:321
|vpiConstType:7
|vpiDecompile:5
|vpiSize:32
|INT:5
|vpiRightRange:
\_constant: , line:321
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiStmt:
\_assignment: , line:322
|vpiOpType:82
|vpiLhs:
\_ref_obj: (mideleg), line:322
|vpiName:mideleg
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1.mideleg
|vpiRhs:
\_operation: , line:322
|vpiOpType:28
|vpiOperand:
\_ref_obj: (updated_csr), line:322
|vpiName:updated_csr
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1.updated_csr
|vpiOperand:
\_ref_obj: (mideleg_mask), line:322
|vpiName:mideleg_mask
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1.mideleg_mask
|vpiProcess:
\_always: , line:327
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:327
|vpiCondition:
\_operation: , line:327
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:327
|vpiName:clk
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1.clk
|vpiStmt:
\_begin: , line:327
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1
|vpiStmt:
\_if_else: , line:328
|vpiCondition:
\_ref_obj: (rst), line:328
|vpiName:rst
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1.rst
|vpiStmt:
\_assignment: , line:329
|vpiOpType:82
|vpiLhs:
\_ref_obj: (mip), line:329
|vpiName:mip
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1.mip
|vpiRhs:
\_constant: , line:329
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiElseStmt:
\_if_stmt: , line:330
|vpiCondition:
\_bit_select: (mwrite_decoder), line:330
|vpiName:mwrite_decoder
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1.mwrite_decoder
|vpiIndex:
\_part_select: , line:330, parent:MIP
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (MIP)
|vpiLeftRange:
\_constant: , line:330
|vpiConstType:7
|vpiDecompile:5
|vpiSize:32
|INT:5
|vpiRightRange:
\_constant: , line:330
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiStmt:
\_assignment: , line:331
|vpiOpType:82
|vpiLhs:
\_ref_obj: (mip), line:331
|vpiName:mip
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1.mip
|vpiRhs:
\_operation: , line:331
|vpiOpType:28
|vpiOperand:
\_ref_obj: (updated_csr), line:331
|vpiName:updated_csr
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1.updated_csr
|vpiOperand:
\_ref_obj: (mip_mask), line:331
|vpiName:mip_mask
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1.mip_mask
|vpiProcess:
\_always: , line:338
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:338
|vpiCondition:
\_operation: , line:338
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:338
|vpiName:clk
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1.clk
|vpiStmt:
\_begin: , line:338
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1
|vpiStmt:
\_if_else: , line:339
|vpiCondition:
\_ref_obj: (rst), line:339
|vpiName:rst
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1.rst
|vpiStmt:
\_assignment: , line:340
|vpiOpType:82
|vpiLhs:
\_ref_obj: (mie_reg), line:340
|vpiName:mie_reg
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1.mie_reg
|vpiRhs:
\_constant: , line:340
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiElseStmt:
\_if_else: , line:341
|vpiCondition:
\_bit_select: (mwrite_decoder), line:341
|vpiName:mwrite_decoder
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1.mwrite_decoder
|vpiIndex:
\_part_select: , line:341, parent:MIE
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (MIE)
|vpiLeftRange:
\_constant: , line:341
|vpiConstType:7
|vpiDecompile:5
|vpiSize:32
|INT:5
|vpiRightRange:
\_constant: , line:341
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiStmt:
\_assignment: , line:342
|vpiOpType:82
|vpiLhs:
\_ref_obj: (mie_reg), line:342
|vpiName:mie_reg
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1.mie_reg
|vpiRhs:
\_operation: , line:342
|vpiOpType:28
|vpiOperand:
\_ref_obj: (updated_csr), line:342
|vpiName:updated_csr
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1.updated_csr
|vpiOperand:
\_ref_obj: (mie_mask), line:342
|vpiName:mie_mask
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1.mie_mask
|vpiElseStmt:
\_if_stmt: , line:343
|vpiCondition:
\_bit_select: (swrite_decoder), line:343
|vpiName:swrite_decoder
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1.swrite_decoder
|vpiIndex:
\_part_select: , line:343, parent:SIE
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (SIE)
|vpiLeftRange:
\_constant: , line:343
|vpiConstType:7
|vpiDecompile:5
|vpiSize:32
|INT:5
|vpiRightRange:
\_constant: , line:343
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiStmt:
\_assignment: , line:344
|vpiOpType:82
|vpiLhs:
\_ref_obj: (mie_reg), line:344
|vpiName:mie_reg
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1.mie_reg
|vpiRhs:
\_operation: , line:344
|vpiOpType:28
|vpiOperand:
\_ref_obj: (updated_csr), line:344
|vpiName:updated_csr
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1.updated_csr
|vpiOperand:
\_ref_obj: (sie_mask), line:344
|vpiName:sie_mask
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1.sie_mask
|vpiProcess:
\_always: , line:351
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:351
|vpiCondition:
\_operation: , line:351
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:351
|vpiName:clk
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1.clk
|vpiStmt:
\_begin: , line:351
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1
|vpiStmt:
\_assignment: , line:352
|vpiOpType:82
|vpiLhs:
\_part_select: , line:352, parent:mepc
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (mepc)
|vpiLeftRange:
\_constant: , line:352
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:352
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiRhs:
\_constant: , line:352
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiStmt:
\_if_stmt: , line:353
|vpiCondition:
\_operation: , line:353
|vpiOpType:29
|vpiOperand:
\_bit_select: (mwrite_decoder), line:353
|vpiName:mwrite_decoder
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1.mwrite_decoder
|vpiIndex:
\_part_select: , line:353, parent:MEPC
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (MEPC)
|vpiLeftRange:
\_constant: , line:353
|vpiConstType:7
|vpiDecompile:5
|vpiSize:32
|INT:5
|vpiRightRange:
\_constant: , line:353
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiOperand:
\_ref_obj: (gc_exception.valid), line:353
|vpiName:gc_exception.valid
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1.gc_exception.valid
|vpiStmt:
\_assignment: , line:354
|vpiOpType:82
|vpiLhs:
\_part_select: , line:354, parent:mepc
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (mepc)
|vpiLeftRange:
\_operation: , line:354
|vpiOpType:11
|vpiOperand:
\_ref_obj: (XLEN), line:354
|vpiName:XLEN
|vpiOperand:
\_constant: , line:354
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:354
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiRhs:
\_operation: , line:354
|vpiOpType:32
|vpiOperand:
\_ref_obj: (gc_exception.valid), line:354
|vpiName:gc_exception.valid
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1.gc_exception.valid
|vpiOperand:
\_ref_obj: (gc_exception.pc), line:354
|vpiName:gc_exception.pc
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1.gc_exception.pc
|vpiOperand:
\_part_select: , line:354, parent:updated_csr
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (updated_csr)
|vpiLeftRange:
\_operation: , line:354
|vpiOpType:11
|vpiOperand:
\_ref_obj: (XLEN), line:354
|vpiName:XLEN
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1.XLEN
|vpiOperand:
\_constant: , line:354
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:354
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiProcess:
\_always: , line:361
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:361
|vpiCondition:
\_operation: , line:361
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:361
|vpiName:clk
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1.clk
|vpiStmt:
\_begin: , line:361
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1
|vpiStmt:
\_assignment: , line:362
|vpiOpType:82
|vpiLhs:
\_part_select: , line:362, parent:mtvec
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (mtvec)
|vpiLeftRange:
\_constant: , line:362
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:362
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiRhs:
\_constant: , line:362
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiStmt:
\_if_stmt: , line:363
|vpiCondition:
\_bit_select: (mwrite_decoder), line:363
|vpiName:mwrite_decoder
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1.mwrite_decoder
|vpiIndex:
\_part_select: , line:363, parent:MTVEC
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (MTVEC)
|vpiLeftRange:
\_constant: , line:363
|vpiConstType:7
|vpiDecompile:5
|vpiSize:32
|INT:5
|vpiRightRange:
\_constant: , line:363
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiStmt:
\_assignment: , line:364
|vpiOpType:82
|vpiLhs:
\_part_select: , line:364, parent:mtvec
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (mtvec)
|vpiLeftRange:
\_operation: , line:364
|vpiOpType:11
|vpiOperand:
\_ref_obj: (XLEN), line:364
|vpiName:XLEN
|vpiOperand:
\_constant: , line:364
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:364
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiRhs:
\_part_select: , line:364, parent:updated_csr
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (updated_csr)
|vpiLeftRange:
\_operation: , line:364
|vpiOpType:11
|vpiOperand:
\_ref_obj: (XLEN), line:364
|vpiName:XLEN
|vpiOperand:
\_constant: , line:364
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:364
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiProcess:
\_always: , line:371
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:371
|vpiCondition:
\_operation: , line:371
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:371
|vpiName:clk
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1.clk
|vpiStmt:
\_begin: , line:371
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1
|vpiStmt:
\_assignment: , line:372
|vpiOpType:82
|vpiLhs:
\_ref_obj: (mcause.zeroes), line:372
|vpiName:mcause.zeroes
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1.mcause.zeroes
|vpiRhs:
\_constant: , line:372
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiStmt:
\_if_stmt: , line:373
|vpiCondition:
\_operation: , line:373
|vpiOpType:29
|vpiOperand:
\_bit_select: (mwrite_decoder), line:373
|vpiName:mwrite_decoder
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1.mwrite_decoder
|vpiIndex:
\_part_select: , line:373, parent:MCAUSE
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (MCAUSE)
|vpiLeftRange:
\_constant: , line:373
|vpiConstType:7
|vpiDecompile:5
|vpiSize:32
|INT:5
|vpiRightRange:
\_constant: , line:373
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiOperand:
\_ref_obj: (gc_exception.valid), line:373
|vpiName:gc_exception.valid
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1.gc_exception.valid
|vpiStmt:
\_begin: , line:373
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1
|vpiStmt:
\_assignment: , line:374
|vpiOpType:82
|vpiLhs:
\_ref_obj: (mcause.interrupt), line:374
|vpiName:mcause.interrupt
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1.mcause.interrupt
|vpiRhs:
\_operation: , line:374
|vpiOpType:32
|vpiOperand:
\_ref_obj: (gc_exception.valid), line:374
|vpiName:gc_exception.valid
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1.gc_exception.valid
|vpiOperand:
\_constant: , line:374
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiOperand:
\_bit_select: (updated_csr), line:374
|vpiName:updated_csr
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1.updated_csr
|vpiIndex:
\_operation: , line:374
|vpiOpType:11
|vpiOperand:
\_ref_obj: (XLEN), line:374
|vpiName:XLEN
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1.XLEN
|vpiOperand:
\_constant: , line:374
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiStmt:
\_assignment: , line:375
|vpiOpType:82
|vpiLhs:
\_ref_obj: (mcause.code), line:375
|vpiName:mcause.code
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1.mcause.code
|vpiRhs:
\_operation: , line:375
|vpiOpType:32
|vpiOperand:
\_ref_obj: (gc_exception.valid), line:375
|vpiName:gc_exception.valid
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1.gc_exception.valid
|vpiOperand:
\_ref_obj: (gc_exception.code), line:375
|vpiName:gc_exception.code
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1.gc_exception.code
|vpiOperand:
\_part_select: , line:375, parent:updated_csr
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (updated_csr)
|vpiLeftRange:
\_operation: , line:375
|vpiOpType:11
|vpiOperand:
\_ref_obj: (ECODE_W), line:375
|vpiName:ECODE_W
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1.ECODE_W
|vpiOperand:
\_constant: , line:375
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:375
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiProcess:
\_always: , line:381
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:381
|vpiCondition:
\_operation: , line:381
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:381
|vpiName:clk
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1.clk
|vpiStmt:
\_begin: , line:381
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1
|vpiStmt:
\_if_stmt: , line:382
|vpiCondition:
\_operation: , line:382
|vpiOpType:29
|vpiOperand:
\_bit_select: (mwrite_decoder), line:382
|vpiName:mwrite_decoder
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1.mwrite_decoder
|vpiIndex:
\_part_select: , line:382, parent:MTVAL
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (MTVAL)
|vpiLeftRange:
\_constant: , line:382
|vpiConstType:7
|vpiDecompile:5
|vpiSize:32
|INT:5
|vpiRightRange:
\_constant: , line:382
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiOperand:
\_ref_obj: (gc_exception.valid), line:382
|vpiName:gc_exception.valid
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1.gc_exception.valid
|vpiStmt:
\_assignment: , line:383
|vpiOpType:82
|vpiLhs:
\_ref_obj: (mtval), line:383
|vpiName:mtval
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1.mtval
|vpiRhs:
\_operation: , line:383
|vpiOpType:32
|vpiOperand:
\_ref_obj: (gc_exception.valid), line:383
|vpiName:gc_exception.valid
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1.gc_exception.valid
|vpiOperand:
\_ref_obj: (gc_exception.tval), line:383
|vpiName:gc_exception.tval
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1.gc_exception.tval
|vpiOperand:
\_ref_obj: (updated_csr), line:383
|vpiName:updated_csr
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1.updated_csr
|vpiProcess:
\_always: , line:392
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:392
|vpiCondition:
\_operation: , line:392
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:392
|vpiName:clk
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1.clk
|vpiStmt:
\_begin: , line:392
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1
|vpiStmt:
\_if_stmt: , line:393
|vpiCondition:
\_ref_obj: (scratch_reg_write), line:393
|vpiName:scratch_reg_write
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1.scratch_reg_write
|vpiStmt:
\_assignment: , line:394
|vpiOpType:82
|vpiLhs:
\_bit_select: (scratch_regs), line:394
|vpiName:scratch_regs
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1.scratch_regs
|vpiIndex:
\_operation: , line:394
|vpiOpType:33
|vpiOperand:
\_ref_obj: (csr_addr.privilege), line:394
|vpiName:csr_addr.privilege
|vpiOperand:
\_ref_obj: (csr_addr.sub_addr), line:394
|vpiName:csr_addr.sub_addr
|vpiRhs:
\_ref_obj: (updated_csr), line:394
|vpiName:updated_csr
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1.updated_csr
|vpiContAssign:
\_cont_assign: , line:195
|vpiRhs:
\_operation: , line:195
|vpiOpType:75
|vpiOperand:
\_constant: , line:195
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiOperand:
\_constant: , line:195
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiOperand:
\_constant: , line:195
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiOperand:
\_constant: , line:195
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiOperand:
\_constant: , line:195
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiOperand:
\_constant: , line:195
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiOperand:
\_constant: , line:195
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiOperand:
\_constant: , line:195
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiOperand:
\_constant: , line:195
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiOperand:
\_constant: , line:195
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiOperand:
\_constant: , line:195
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiOperand:
\_constant: , line:195
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiLhs:
\_ref_obj: (misa), line:195
|vpiName:misa
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1.misa
|vpiContAssign:
\_cont_assign: , line:206
|vpiRhs:
\_bit_select: (medeleg), line:206
|vpiName:medeleg
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1.medeleg
|vpiIndex:
\_ref_obj: (gc_exception.code), line:206
|vpiName:gc_exception.code
|vpiLhs:
\_ref_obj: (exception_delegated), line:206
|vpiName:exception_delegated
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1.exception_delegated
|vpiContAssign:
\_cont_assign: , line:207
|vpiRhs:
\_bit_select: (mideleg), line:207
|vpiName:mideleg
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1.mideleg
|vpiIndex:
\_ref_obj: (gc_exception.code), line:207
|vpiName:gc_exception.code
|vpiLhs:
\_ref_obj: (interrupt_delegated), line:207
|vpiName:interrupt_delegated
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1.interrupt_delegated
|vpiContAssign:
\_cont_assign: , line:209
|vpiRhs:
\_operation: , line:209
|vpiOpType:32
|vpiOperand:
\_ref_obj: (mret), line:209
|vpiName:mret
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1.mret
|vpiOperand:
\_ref_obj: (mstatus.mpp), line:209
|vpiName:mstatus.mpp
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1.mstatus.mpp
|vpiOperand:
\_operation: , line:209
|vpiOpType:33
|vpiOperand:
\_constant: , line:209
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiOperand:
\_ref_obj: (mstatus.spp), line:209
|vpiName:mstatus.spp
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1.mstatus.spp
|vpiLhs:
\_ref_obj: (trap_return_privilege_level), line:209
|vpiName:trap_return_privilege_level
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1.trap_return_privilege_level
|vpiContAssign:
\_cont_assign: , line:210
|vpiRhs:
\_operation: , line:210
|vpiOpType:32
|vpiOperand:
\_ref_obj: (exception_delegated), line:210
|vpiName:exception_delegated
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1.exception_delegated
|vpiOperand:
\_ref_obj: (SUPERVISOR_PRIVILEGE), line:210
|vpiName:SUPERVISOR_PRIVILEGE
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1.SUPERVISOR_PRIVILEGE
|vpiOperand:
\_ref_obj: (MACHINE_PRIVILEGE), line:210
|vpiName:MACHINE_PRIVILEGE
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1.MACHINE_PRIVILEGE
|vpiLhs:
\_ref_obj: (exception_privilege_level), line:210
|vpiName:exception_privilege_level
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1.exception_privilege_level
|vpiContAssign:
\_cont_assign: , line:211
|vpiRhs:
\_operation: , line:211
|vpiOpType:32
|vpiOperand:
\_ref_obj: (interrupt_delegated), line:211
|vpiName:interrupt_delegated
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1.interrupt_delegated
|vpiOperand:
\_ref_obj: (SUPERVISOR_PRIVILEGE), line:211
|vpiName:SUPERVISOR_PRIVILEGE
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1.SUPERVISOR_PRIVILEGE
|vpiOperand:
\_ref_obj: (MACHINE_PRIVILEGE), line:211
|vpiName:MACHINE_PRIVILEGE
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1.MACHINE_PRIVILEGE
|vpiLhs:
\_ref_obj: (interrupt_privilege_level), line:211
|vpiName:interrupt_privilege_level
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1.interrupt_privilege_level
|vpiContAssign:
\_cont_assign: , line:231
|vpiRhs:
\_ref_obj: (privilege_level), line:231
|vpiName:privilege_level
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1.privilege_level
|vpiLhs:
\_ref_obj: (current_privilege), line:231
|vpiName:current_privilege
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1.current_privilege
|vpiContAssign:
\_cont_assign: , line:263
|vpiRhs:
\_operation: , line:263
|vpiOpType:75
|vpiOperand:
\_constant: , line:263
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiOperand:
\_constant: , line:263
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiOperand:
\_constant: , line:263
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiOperand:
\_constant: , line:263
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiOperand:
\_constant: , line:263
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiOperand:
\_constant: , line:263
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiOperand:
\_constant: , line:263
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiOperand:
\_constant: , line:263
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiOperand:
\_constant: , line:263
|vpiConstType:3
|vpiDecompile:'b1
|vpiSize:1
|BIN:1
|vpiOperand:
\_constant: , line:263
|vpiConstType:3
|vpiDecompile:'b1
|vpiSize:1
|BIN:1
|vpiOperand:
\_constant: , line:263
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiOperand:
\_constant: , line:263
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiOperand:
\_constant: , line:263
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiOperand:
\_constant: , line:263
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiOperand:
\_constant: , line:263
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiOperand:
\_constant: , line:263
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiOperand:
\_constant: , line:263
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiOperand:
\_constant: , line:263
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiOperand:
\_constant: , line:263
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiOperand:
\_constant: , line:263
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiLhs:
\_ref_obj: (mstatus_mmask), line:263
|vpiName:mstatus_mmask
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1.mstatus_mmask
|vpiContAssign:
\_cont_assign: , line:264
|vpiRhs:
\_operation: , line:264
|vpiOpType:75
|vpiOperand:
\_constant: , line:264
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiOperand:
\_constant: , line:264
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiOperand:
\_constant: , line:264
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiOperand:
\_constant: , line:264
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiOperand:
\_constant: , line:264
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiOperand:
\_constant: , line:264
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiOperand:
\_constant: , line:264
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiOperand:
\_constant: , line:264
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiOperand:
\_constant: , line:264
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiOperand:
\_constant: , line:264
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiOperand:
\_constant: , line:264
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiOperand:
\_constant: , line:264
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiLhs:
\_ref_obj: (mstatus_smask), line:264
|vpiName:mstatus_smask
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1.mstatus_smask
|vpiContAssign:
\_cont_assign: , line:265
|vpiRhs:
\_operation: , line:265
|vpiOpType:32
|vpiOperand:
\_bit_select: (mwrite_decoder), line:265
|vpiName:mwrite_decoder
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1.mwrite_decoder
|vpiIndex:
\_part_select: , line:265, parent:MSTATUS
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (MSTATUS)
|vpiLeftRange:
\_constant: , line:265
|vpiConstType:7
|vpiDecompile:5
|vpiSize:32
|INT:5
|vpiRightRange:
\_constant: , line:265
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiOperand:
\_ref_obj: (mstatus_mmask), line:265
|vpiName:mstatus_mmask
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1.mstatus_mmask
|vpiOperand:
\_ref_obj: (mstatus_smask), line:265
|vpiName:mstatus_smask
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1.mstatus_smask
|vpiLhs:
\_ref_obj: (mstatus_mask), line:265
|vpiName:mstatus_mask
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1.mstatus_mask
|vpiContAssign:
\_cont_assign: , line:278
|vpiRhs:
\_operation: , line:278
|vpiOpType:75
|vpiOperand:
\_constant: , line:278
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiOperand:
\_constant: , line:278
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiOperand:
\_ref_obj: (MACHINE_PRIVILEGE), line:278
|vpiName:MACHINE_PRIVILEGE
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1.MACHINE_PRIVILEGE
|vpiOperand:
\_ref_obj: (MACHINE_PRIVILEGE), line:278
|vpiName:MACHINE_PRIVILEGE
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1.MACHINE_PRIVILEGE
|vpiLhs:
\_ref_obj: (mstatus_rst), line:278
|vpiName:mstatus_rst
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1.mstatus_rst
|vpiContAssign:
\_cont_assign: , line:326
|vpiRhs:
\_operation: , line:326
|vpiOpType:75
|vpiOperand:
\_constant: , line:326
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiOperand:
\_constant: , line:326
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiOperand:
\_constant: , line:326
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiOperand:
\_constant: , line:326
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiOperand:
\_constant: , line:326
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiOperand:
\_constant: , line:326
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiLhs:
\_ref_obj: (mip_mask), line:326
|vpiName:mip_mask
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1.mip_mask
|vpiContAssign:
\_cont_assign: , line:335
|vpiRhs:
\_operation: , line:335
|vpiOpType:75
|vpiOperand:
\_constant: , line:335
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiOperand:
\_constant: , line:335
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiOperand:
\_constant: , line:335
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiOperand:
\_constant: , line:335
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiOperand:
\_constant: , line:335
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiOperand:
\_constant: , line:335
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiOperand:
\_constant: , line:335
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiOperand:
\_constant: , line:335
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiOperand:
\_constant: , line:335
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiOperand:
\_constant: , line:335
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiOperand:
\_constant: , line:335
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiOperand:
\_constant: , line:335
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiOperand:
\_constant: , line:335
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiOperand:
\_constant: , line:335
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiLhs:
\_ref_obj: (mie_mask), line:335
|vpiName:mie_mask
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1.mie_mask
|vpiContAssign:
\_cont_assign: , line:336
|vpiRhs:
\_operation: , line:336
|vpiOpType:75
|vpiOperand:
\_constant: , line:336
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiOperand:
\_constant: , line:336
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiOperand:
\_constant: , line:336
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiOperand:
\_constant: , line:336
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiOperand:
\_constant: , line:336
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiOperand:
\_constant: , line:336
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiOperand:
\_constant: , line:336
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiOperand:
\_constant: , line:336
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiLhs:
\_ref_obj: (sie_mask), line:336
|vpiName:sie_mask
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1.sie_mask
|vpiContAssign:
\_cont_assign: , line:356
|vpiRhs:
\_ref_obj: (mepc), line:356
|vpiName:mepc
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1.mepc
|vpiLhs:
\_ref_obj: (csr_mepc), line:356
|vpiName:csr_mepc
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1.csr_mepc
|vpiContAssign:
\_cont_assign: , line:366
|vpiRhs:
\_ref_obj: (mtvec), line:366
|vpiName:mtvec
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1.mtvec
|vpiLhs:
\_ref_obj: (trap_pc), line:366
|vpiName:trap_pc
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1.trap_pc
|vpiContAssign:
\_cont_assign: , line:390
|vpiRhs:
\_operation: , line:390
|vpiOpType:29
|vpiOperand:
\_bit_select: (mwrite_decoder), line:390
|vpiName:mwrite_decoder
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1.mwrite_decoder
|vpiIndex:
\_part_select: , line:390, parent:MSCRATCH
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (MSCRATCH)
|vpiLeftRange:
\_constant: , line:390
|vpiConstType:7
|vpiDecompile:5
|vpiSize:32
|INT:5
|vpiRightRange:
\_constant: , line:390
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiOperand:
\_bit_select: (swrite_decoder), line:390
|vpiName:swrite_decoder
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1.swrite_decoder
|vpiIndex:
\_part_select: , line:390, parent:SSCRATCH
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (SSCRATCH)
|vpiLeftRange:
\_constant: , line:390
|vpiConstType:7
|vpiDecompile:5
|vpiSize:32
|INT:5
|vpiRightRange:
\_constant: , line:390
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiLhs:
\_ref_obj: (scratch_reg_write), line:390
|vpiName:scratch_reg_write
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1.scratch_reg_write
|vpiContAssign:
\_cont_assign: , line:396
|vpiRhs:
\_bit_select: (scratch_regs), line:396
|vpiName:scratch_regs
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1.scratch_regs
|vpiIndex:
\_operation: , line:396
|vpiOpType:33
|vpiOperand:
\_ref_obj: (csr_addr.privilege), line:396
|vpiName:csr_addr.privilege
|vpiOperand:
\_ref_obj: (csr_addr.sub_addr), line:396
|vpiName:csr_addr.sub_addr
|vpiLhs:
\_ref_obj: (scratch_out), line:396
|vpiName:scratch_out
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk1.scratch_out
|vpiParameter:
\_parameter: (ALU_UNIT_WB_ID), line:190
|vpiName:ALU_UNIT_WB_ID
|INT:32
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (BRANCH_PREDICTOR_WAYS), line:159
|vpiName:BRANCH_PREDICTOR_WAYS
|INT:9
|vpiParameter:
\_parameter: (BRANCH_TABLE_ENTRIES), line:160
|vpiName:BRANCH_TABLE_ENTRIES
|INT:4
|vpiParameter:
\_parameter: (BRANCH_UNIT_ID), line:195
|vpiName:BRANCH_UNIT_ID
|INT:8
|vpiParameter:
\_parameter: (BUS_ADDR_H), line:107
|vpiName:BUS_ADDR_H
|INT:1
|vpiParameter:
\_parameter: (BUS_ADDR_L), line:106
|vpiName:BUS_ADDR_L
|INT:0
|vpiParameter:
\_parameter: (BUS_BIT_CHECK), line:108
|vpiName:BUS_BIT_CHECK
|INT:1
|vpiParameter:
\_parameter: (BUS_TYPE), line:89
|vpiName:BUS_TYPE
|INT:5
|vpiParameter:
\_parameter: (COUNTER_W), line:42
|vpiName:COUNTER_W
|INT:33
|vpiParameter:
\_parameter: (CPU_ID), line:38
|vpiName:CPU_ID
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_ADDR_WIDTH), line:113
|vpiName:C_M_AXI_ADDR_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_DATA_WIDTH), line:114
|vpiName:C_M_AXI_DATA_WIDTH
|INT:1
|vpiParameter:
\_parameter: (DCACHE_LINES), line:133
|vpiName:DCACHE_LINES
|INT:-2146435073
|vpiParameter:
\_parameter: (DCACHE_LINE_ADDR_W), line:135
|vpiName:DCACHE_LINE_ADDR_W
|INT:1073741824
|vpiParameter:
\_parameter: (DCACHE_LINE_W), line:136
|vpiName:DCACHE_LINE_W
|INT:1342177279
|vpiParameter:
\_parameter: (DCACHE_SUB_LINE_ADDR_W), line:137
|vpiName:DCACHE_SUB_LINE_ADDR_W
|INT:4
|vpiParameter:
\_parameter: (DCACHE_TAG_W), line:138
|vpiName:DCACHE_TAG_W
|INT:1610612736
|vpiParameter:
\_parameter: (DCACHE_WAYS), line:134
|vpiName:DCACHE_WAYS
|INT:4
|vpiParameter:
\_parameter: (DIV_ALGORITHM), line:67
|vpiName:DIV_ALGORITHM
|INT:0
|vpiParameter:
\_parameter: (DIV_UNIT_WB_ID), line:192
|vpiName:DIV_UNIT_WB_ID
|INT:2
|vpiParameter:
\_parameter: (DTLB_DEPTH), line:152
|vpiName:DTLB_DEPTH
|INT:512
|vpiParameter:
\_parameter: (DTLB_WAYS), line:151
|vpiName:DTLB_WAYS
|INT:32
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (ENABLE_M_MODE), line:34
|vpiName:ENABLE_M_MODE
|INT:1
|vpiParameter:
\_parameter: (ENABLE_S_MODE), line:36
|vpiName:ENABLE_S_MODE
|INT:0
|vpiParameter:
\_parameter: (ENABLE_TRACE_INTERFACE), line:172
|vpiName:ENABLE_TRACE_INTERFACE
|INT:2
|vpiParameter:
\_parameter: (FETCH_BUFFER_DEPTH), line:168
|vpiName:FETCH_BUFFER_DEPTH
|INT:512
|vpiParameter:
\_parameter: (FPGA_VENDOR), line:27
|vpiName:FPGA_VENDOR
|STRING:"xilinx"
|vpiParameter:
\_parameter: (GC_UNIT_ID), line:196
|vpiName:GC_UNIT_ID
|INT:4
|vpiParameter:
\_parameter: (ICACHE_LINES), line:121
|vpiName:ICACHE_LINES
|INT:2
|vpiParameter:
\_parameter: (ICACHE_LINE_ADDR_W), line:123
|vpiName:ICACHE_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_LINE_W), line:124
|vpiName:ICACHE_LINE_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_SUB_LINE_ADDR_W), line:125
|vpiName:ICACHE_SUB_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_TAG_W), line:126
|vpiName:ICACHE_TAG_W
|INT:-2147483648
|vpiParameter:
\_parameter: (ICACHE_WAYS), line:122
|vpiName:ICACHE_WAYS
|INT:1
|vpiParameter:
\_parameter: (ITLB_DEPTH), line:146
|vpiName:ITLB_DEPTH
|INT:32
|vpiParameter:
\_parameter: (ITLB_WAYS), line:145
|vpiName:ITLB_WAYS
|INT:4
|vpiParameter:
\_parameter: (L1_CONNECTIONS), line:177
|vpiName:L1_CONNECTIONS
|INT:9
|vpiParameter:
\_parameter: (L1_DCACHE_ID), line:178
|vpiName:L1_DCACHE_ID
|INT:4
|vpiParameter:
\_parameter: (L1_DMMU_ID), line:179
|vpiName:L1_DMMU_ID
|INT:2
|vpiParameter:
\_parameter: (L1_ICACHE_ID), line:180
|vpiName:L1_ICACHE_ID
|INT:19
|vpiParameter:
\_parameter: (L1_IMMU_ID), line:181
|vpiName:L1_IMMU_ID
|INT:0
|vpiParameter:
\_parameter: (LS_UNIT_WB_ID), line:191
|vpiName:LS_UNIT_WB_ID
|INT:1
|vpiParameter:
\_parameter: (MAX_INFLIGHT_COUNT), line:167
|vpiName:MAX_INFLIGHT_COUNT
|INT:19
|vpiParameter:
\_parameter: (MEMORY_ADDR_H), line:103
|vpiName:MEMORY_ADDR_H
|INT:12
|vpiParameter:
\_parameter: (MEMORY_ADDR_L), line:102
|vpiName:MEMORY_ADDR_L
|INT:11
|vpiParameter:
\_parameter: (MEMORY_BIT_CHECK), line:104
|vpiName:MEMORY_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (MUL_UNIT_WB_ID), line:193
|vpiName:MUL_UNIT_WB_ID
|INT:512
|vpiParameter:
\_parameter: (NUM_UNITS), line:188
|vpiName:NUM_UNITS
|INT:2
|vpiParameter:
\_parameter: (NUM_WB_UNITS), line:186
|vpiName:NUM_WB_UNITS
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (RAS_DEPTH), line:161
|vpiName:RAS_DEPTH
|INT:2
|vpiParameter:
\_parameter: (RESET_VEC), line:39
|vpiName:RESET_VEC
|INT:-2147483648
|vpiParameter:
\_parameter: (SCRATCH_ADDR_H), line:99
|vpiName:SCRATCH_ADDR_H
|INT:9
|vpiParameter:
\_parameter: (SCRATCH_ADDR_L), line:98
|vpiName:SCRATCH_ADDR_L
|INT:8
|vpiParameter:
\_parameter: (SCRATCH_BIT_CHECK), line:100
|vpiName:SCRATCH_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (USE_AMO), line:70
|vpiName:USE_AMO
|INT:1
|vpiParameter:
\_parameter: (USE_BRANCH_PREDICTOR), line:158
|vpiName:USE_BRANCH_PREDICTOR
|INT:2
|vpiParameter:
\_parameter: (USE_BUS), line:88
|vpiName:USE_BUS
|INT:4
|vpiParameter:
\_parameter: (USE_DCACHE), line:92
|vpiName:USE_DCACHE
|INT:6
|vpiParameter:
\_parameter: (USE_DIV), line:49
|vpiName:USE_DIV
|INT:1
|vpiParameter:
\_parameter: (USE_DTAG_INVALIDATIONS), line:140
|vpiName:USE_DTAG_INVALIDATIONS
|INT:1879048191
|vpiParameter:
\_parameter: (USE_D_SCRATCH_MEM), line:79
|vpiName:USE_D_SCRATCH_MEM
|INT:3
|vpiParameter:
\_parameter: (USE_ICACHE), line:93
|vpiName:USE_ICACHE
|INT:7
|vpiParameter:
\_parameter: (USE_I_SCRATCH_MEM), line:78
|vpiName:USE_I_SCRATCH_MEM
|INT:2
|vpiParameter:
\_parameter: (USE_MUL), line:48
|vpiName:USE_MUL
|INT:1
|vpiParameter:
\_parameter: (WB_UNITS_WIDTH), line:187
|vpiName:WB_UNITS_WIDTH
|INT:32
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiGenScopeArray:
\_gen_scope_array: (genblk2), line:420, parent:csr_registers
|vpiName:genblk2
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk2
|vpiGenScope:
\_gen_scope: , parent:genblk2
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk2
|vpiNet:
\_logic_net: (stvec_mask), line:425
|vpiName:stvec_mask
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk2.stvec_mask
|vpiNetType:36
|vpiRange:
\_range: , line:425
|vpiLeftRange:
\_constant: , line:425
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:425
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (satp_mask), line:434
|vpiName:satp_mask
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk2.satp_mask
|vpiNetType:36
|vpiRange:
\_range: , line:434
|vpiLeftRange:
\_constant: , line:434
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiRightRange:
\_constant: , line:434
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiProcess:
\_always: , line:426
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:426
|vpiCondition:
\_operation: , line:426
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:426
|vpiName:clk
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk2.clk
|vpiStmt:
\_begin: , line:426
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk2
|vpiStmt:
\_if_else: , line:427
|vpiCondition:
\_ref_obj: (rst), line:427
|vpiName:rst
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk2.rst
|vpiStmt:
\_assignment: , line:428
|vpiOpType:82
|vpiLhs:
\_ref_obj: (stvec), line:428
|vpiName:stvec
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk2.stvec
|vpiRhs:
\_operation: , line:428
|vpiOpType:33
|vpiOperand:
\_part_select: , line:428, parent:RESET_VEC
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (RESET_VEC)
|vpiLeftRange:
\_operation: , line:428
|vpiOpType:11
|vpiOperand:
\_ref_obj: (XLEN), line:428
|vpiName:XLEN
|vpiOperand:
\_constant: , line:428
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:428
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiOperand:
\_constant: , line:428
|vpiConstType:3
|vpiDecompile:2'b00
|vpiSize:2
|BIN:2'b00
|vpiElseStmt:
\_if_stmt: , line:429
|vpiCondition:
\_bit_select: (swrite_decoder), line:429
|vpiName:swrite_decoder
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk2.swrite_decoder
|vpiIndex:
\_part_select: , line:429, parent:STVEC
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (STVEC)
|vpiLeftRange:
\_constant: , line:429
|vpiConstType:7
|vpiDecompile:5
|vpiSize:32
|INT:5
|vpiRightRange:
\_constant: , line:429
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiStmt:
\_assignment: , line:430
|vpiOpType:82
|vpiLhs:
\_ref_obj: (stvec), line:430
|vpiName:stvec
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk2.stvec
|vpiRhs:
\_operation: , line:430
|vpiOpType:28
|vpiOperand:
\_ref_obj: (updated_csr), line:430
|vpiName:updated_csr
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk2.updated_csr
|vpiOperand:
\_ref_obj: (stvec_mask), line:430
|vpiName:stvec_mask
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk2.stvec_mask
|vpiProcess:
\_always: , line:436
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:436
|vpiCondition:
\_operation: , line:436
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:436
|vpiName:clk
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk2.clk
|vpiStmt:
\_begin: , line:436
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk2
|vpiStmt:
\_if_else: , line:437
|vpiCondition:
\_ref_obj: (rst), line:437
|vpiName:rst
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk2.rst
|vpiStmt:
\_assignment: , line:438
|vpiOpType:82
|vpiLhs:
\_ref_obj: (satp), line:438
|vpiName:satp
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk2.satp
|vpiRhs:
\_constant: , line:438
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiElseStmt:
\_if_stmt: , line:439
|vpiCondition:
\_bit_select: (swrite_decoder), line:439
|vpiName:swrite_decoder
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk2.swrite_decoder
|vpiIndex:
\_part_select: , line:439, parent:SATP
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (SATP)
|vpiLeftRange:
\_constant: , line:439
|vpiConstType:7
|vpiDecompile:5
|vpiSize:32
|INT:5
|vpiRightRange:
\_constant: , line:439
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiStmt:
\_assignment: , line:440
|vpiOpType:82
|vpiLhs:
\_ref_obj: (satp), line:440
|vpiName:satp
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk2.satp
|vpiRhs:
\_operation: , line:440
|vpiOpType:28
|vpiOperand:
\_ref_obj: (updated_csr), line:440
|vpiName:updated_csr
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk2.updated_csr
|vpiOperand:
\_ref_obj: (satp_mask), line:440
|vpiName:satp_mask
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk2.satp_mask
|vpiContAssign:
\_cont_assign: , line:422
|vpiRhs:
\_operation: , line:422
|vpiOpType:75
|vpiOperand:
\_constant: , line:422
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiOperand:
\_constant: , line:422
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiOperand:
\_constant: , line:422
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiOperand:
\_constant: , line:422
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiOperand:
\_constant: , line:422
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiOperand:
\_constant: , line:422
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiOperand:
\_constant: , line:422
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiOperand:
\_constant: , line:422
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiLhs:
\_ref_obj: (sip_mask), line:422
|vpiName:sip_mask
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk2.sip_mask
|vpiContAssign:
\_cont_assign: , line:435
|vpiRhs:
\_constant: , line:435
|vpiConstType:3
|vpiDecompile:'b1
|vpiSize:1
|BIN:1
|vpiLhs:
\_ref_obj: (satp_mask), line:435
|vpiName:satp_mask
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.genblk2.satp_mask
|vpiParameter:
\_parameter: (ALU_UNIT_WB_ID), line:190
|vpiName:ALU_UNIT_WB_ID
|INT:32
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (BRANCH_PREDICTOR_WAYS), line:159
|vpiName:BRANCH_PREDICTOR_WAYS
|INT:9
|vpiParameter:
\_parameter: (BRANCH_TABLE_ENTRIES), line:160
|vpiName:BRANCH_TABLE_ENTRIES
|INT:4
|vpiParameter:
\_parameter: (BRANCH_UNIT_ID), line:195
|vpiName:BRANCH_UNIT_ID
|INT:8
|vpiParameter:
\_parameter: (BUS_ADDR_H), line:107
|vpiName:BUS_ADDR_H
|INT:1
|vpiParameter:
\_parameter: (BUS_ADDR_L), line:106
|vpiName:BUS_ADDR_L
|INT:0
|vpiParameter:
\_parameter: (BUS_BIT_CHECK), line:108
|vpiName:BUS_BIT_CHECK
|INT:1
|vpiParameter:
\_parameter: (BUS_TYPE), line:89
|vpiName:BUS_TYPE
|INT:5
|vpiParameter:
\_parameter: (COUNTER_W), line:42
|vpiName:COUNTER_W
|INT:33
|vpiParameter:
\_parameter: (CPU_ID), line:38
|vpiName:CPU_ID
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_ADDR_WIDTH), line:113
|vpiName:C_M_AXI_ADDR_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_DATA_WIDTH), line:114
|vpiName:C_M_AXI_DATA_WIDTH
|INT:1
|vpiParameter:
\_parameter: (DCACHE_LINES), line:133
|vpiName:DCACHE_LINES
|INT:-2146435073
|vpiParameter:
\_parameter: (DCACHE_LINE_ADDR_W), line:135
|vpiName:DCACHE_LINE_ADDR_W
|INT:1073741824
|vpiParameter:
\_parameter: (DCACHE_LINE_W), line:136
|vpiName:DCACHE_LINE_W
|INT:1342177279
|vpiParameter:
\_parameter: (DCACHE_SUB_LINE_ADDR_W), line:137
|vpiName:DCACHE_SUB_LINE_ADDR_W
|INT:4
|vpiParameter:
\_parameter: (DCACHE_TAG_W), line:138
|vpiName:DCACHE_TAG_W
|INT:1610612736
|vpiParameter:
\_parameter: (DCACHE_WAYS), line:134
|vpiName:DCACHE_WAYS
|INT:4
|vpiParameter:
\_parameter: (DIV_ALGORITHM), line:67
|vpiName:DIV_ALGORITHM
|INT:0
|vpiParameter:
\_parameter: (DIV_UNIT_WB_ID), line:192
|vpiName:DIV_UNIT_WB_ID
|INT:2
|vpiParameter:
\_parameter: (DTLB_DEPTH), line:152
|vpiName:DTLB_DEPTH
|INT:512
|vpiParameter:
\_parameter: (DTLB_WAYS), line:151
|vpiName:DTLB_WAYS
|INT:32
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (ENABLE_M_MODE), line:34
|vpiName:ENABLE_M_MODE
|INT:1
|vpiParameter:
\_parameter: (ENABLE_S_MODE), line:36
|vpiName:ENABLE_S_MODE
|INT:0
|vpiParameter:
\_parameter: (ENABLE_TRACE_INTERFACE), line:172
|vpiName:ENABLE_TRACE_INTERFACE
|INT:2
|vpiParameter:
\_parameter: (FETCH_BUFFER_DEPTH), line:168
|vpiName:FETCH_BUFFER_DEPTH
|INT:512
|vpiParameter:
\_parameter: (FPGA_VENDOR), line:27
|vpiName:FPGA_VENDOR
|STRING:"xilinx"
|vpiParameter:
\_parameter: (GC_UNIT_ID), line:196
|vpiName:GC_UNIT_ID
|INT:4
|vpiParameter:
\_parameter: (ICACHE_LINES), line:121
|vpiName:ICACHE_LINES
|INT:2
|vpiParameter:
\_parameter: (ICACHE_LINE_ADDR_W), line:123
|vpiName:ICACHE_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_LINE_W), line:124
|vpiName:ICACHE_LINE_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_SUB_LINE_ADDR_W), line:125
|vpiName:ICACHE_SUB_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_TAG_W), line:126
|vpiName:ICACHE_TAG_W
|INT:-2147483648
|vpiParameter:
\_parameter: (ICACHE_WAYS), line:122
|vpiName:ICACHE_WAYS
|INT:1
|vpiParameter:
\_parameter: (ITLB_DEPTH), line:146
|vpiName:ITLB_DEPTH
|INT:32
|vpiParameter:
\_parameter: (ITLB_WAYS), line:145
|vpiName:ITLB_WAYS
|INT:4
|vpiParameter:
\_parameter: (L1_CONNECTIONS), line:177
|vpiName:L1_CONNECTIONS
|INT:9
|vpiParameter:
\_parameter: (L1_DCACHE_ID), line:178
|vpiName:L1_DCACHE_ID
|INT:4
|vpiParameter:
\_parameter: (L1_DMMU_ID), line:179
|vpiName:L1_DMMU_ID
|INT:2
|vpiParameter:
\_parameter: (L1_ICACHE_ID), line:180
|vpiName:L1_ICACHE_ID
|INT:19
|vpiParameter:
\_parameter: (L1_IMMU_ID), line:181
|vpiName:L1_IMMU_ID
|INT:0
|vpiParameter:
\_parameter: (LS_UNIT_WB_ID), line:191
|vpiName:LS_UNIT_WB_ID
|INT:1
|vpiParameter:
\_parameter: (MAX_INFLIGHT_COUNT), line:167
|vpiName:MAX_INFLIGHT_COUNT
|INT:19
|vpiParameter:
\_parameter: (MEMORY_ADDR_H), line:103
|vpiName:MEMORY_ADDR_H
|INT:12
|vpiParameter:
\_parameter: (MEMORY_ADDR_L), line:102
|vpiName:MEMORY_ADDR_L
|INT:11
|vpiParameter:
\_parameter: (MEMORY_BIT_CHECK), line:104
|vpiName:MEMORY_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (MUL_UNIT_WB_ID), line:193
|vpiName:MUL_UNIT_WB_ID
|INT:512
|vpiParameter:
\_parameter: (NUM_UNITS), line:188
|vpiName:NUM_UNITS
|INT:2
|vpiParameter:
\_parameter: (NUM_WB_UNITS), line:186
|vpiName:NUM_WB_UNITS
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (RAS_DEPTH), line:161
|vpiName:RAS_DEPTH
|INT:2
|vpiParameter:
\_parameter: (RESET_VEC), line:39
|vpiName:RESET_VEC
|INT:-2147483648
|vpiParameter:
\_parameter: (SCRATCH_ADDR_H), line:99
|vpiName:SCRATCH_ADDR_H
|INT:9
|vpiParameter:
\_parameter: (SCRATCH_ADDR_L), line:98
|vpiName:SCRATCH_ADDR_L
|INT:8
|vpiParameter:
\_parameter: (SCRATCH_BIT_CHECK), line:100
|vpiName:SCRATCH_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (USE_AMO), line:70
|vpiName:USE_AMO
|INT:1
|vpiParameter:
\_parameter: (USE_BRANCH_PREDICTOR), line:158
|vpiName:USE_BRANCH_PREDICTOR
|INT:2
|vpiParameter:
\_parameter: (USE_BUS), line:88
|vpiName:USE_BUS
|INT:4
|vpiParameter:
\_parameter: (USE_DCACHE), line:92
|vpiName:USE_DCACHE
|INT:6
|vpiParameter:
\_parameter: (USE_DIV), line:49
|vpiName:USE_DIV
|INT:1
|vpiParameter:
\_parameter: (USE_DTAG_INVALIDATIONS), line:140
|vpiName:USE_DTAG_INVALIDATIONS
|INT:1879048191
|vpiParameter:
\_parameter: (USE_D_SCRATCH_MEM), line:79
|vpiName:USE_D_SCRATCH_MEM
|INT:3
|vpiParameter:
\_parameter: (USE_ICACHE), line:93
|vpiName:USE_ICACHE
|INT:7
|vpiParameter:
\_parameter: (USE_I_SCRATCH_MEM), line:78
|vpiName:USE_I_SCRATCH_MEM
|INT:2
|vpiParameter:
\_parameter: (USE_MUL), line:48
|vpiName:USE_MUL
|INT:1
|vpiParameter:
\_parameter: (WB_UNITS_WIDTH), line:187
|vpiName:WB_UNITS_WIDTH
|INT:32
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiNet:
\_logic_net: (clk), line:28, parent:csr_registers
|vpiNet:
\_logic_net: (rst), line:29, parent:csr_registers
|vpiNet:
\_logic_net: (csr_inputs), line:32, parent:csr_registers
|vpiNet:
\_logic_net: (new_request), line:33, parent:csr_registers
|vpiName:new_request
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.new_request
|vpiNet:
\_logic_net: (read_regs), line:34, parent:csr_registers
|vpiNet:
\_logic_net: (commit), line:35, parent:csr_registers
|vpiNet:
\_logic_net: (gc_exception), line:36, parent:csr_registers
|vpiNet:
\_logic_net: (csr_exception), line:37, parent:csr_registers
|vpiNet:
\_logic_net: (current_privilege), line:38, parent:csr_registers
|vpiNet:
\_logic_net: (instruction_issued_no_rd), line:41, parent:csr_registers
|vpiNet:
\_logic_net: (mret), line:44, parent:csr_registers
|vpiNet:
\_logic_net: (sret), line:45, parent:csr_registers
|vpiNet:
\_logic_net: (tlb_on), line:48, parent:csr_registers
|vpiNet:
\_logic_net: (asid), line:49, parent:csr_registers
|vpiNet:
\_logic_net: (instruction_complete), line:56, parent:csr_registers
|vpiNet:
\_logic_net: (interrupt), line:60, parent:csr_registers
|vpiNet:
\_logic_net: (timer_interrupt), line:61, parent:csr_registers
|vpiNet:
\_logic_net: (wb_csr), line:63, parent:csr_registers
|vpiNet:
\_logic_net: (trap_pc), line:64, parent:csr_registers
|vpiNet:
\_logic_net: (csr_mepc), line:65, parent:csr_registers
|vpiNet:
\_logic_net: (csr_sepc), line:66, parent:csr_registers
|vpiNet:
\_logic_net: (mvendorid), line:71, parent:csr_registers
|vpiName:mvendorid
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.mvendorid
|vpiRange:
\_range: , line:71
|vpiLeftRange:
\_constant: , line:71
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiRightRange:
\_constant: , line:71
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (marchid), line:72, parent:csr_registers
|vpiName:marchid
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.marchid
|vpiRange:
\_range: , line:72
|vpiLeftRange:
\_constant: , line:72
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiRightRange:
\_constant: , line:72
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (mimpid), line:73, parent:csr_registers
|vpiName:mimpid
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.mimpid
|vpiRange:
\_range: , line:73
|vpiLeftRange:
\_constant: , line:73
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiRightRange:
\_constant: , line:73
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (mhartid), line:74, parent:csr_registers
|vpiName:mhartid
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.mhartid
|vpiRange:
\_range: , line:74
|vpiLeftRange:
\_constant: , line:74
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiRightRange:
\_constant: , line:74
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (privilege_level), line:80, parent:csr_registers
|vpiName:privilege_level
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.privilege_level
|vpiNetType:36
|vpiRange:
\_range: , line:80
|vpiLeftRange:
\_constant: , line:80
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:80
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (next_privilege_level), line:80, parent:csr_registers
|vpiName:next_privilege_level
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.next_privilege_level
|vpiNetType:36
|vpiRange:
\_range: , line:80
|vpiLeftRange:
\_constant: , line:80
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:80
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (scratch_out), line:84, parent:csr_registers
|vpiName:scratch_out
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.scratch_out
|vpiNetType:36
|vpiRange:
\_range: , line:84
|vpiLeftRange:
\_constant: , line:84
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiRightRange:
\_constant: , line:84
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (mtvec), line:87, parent:csr_registers
|vpiName:mtvec
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.mtvec
|vpiNetType:36
|vpiRange:
\_range: , line:87
|vpiLeftRange:
\_constant: , line:87
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiRightRange:
\_constant: , line:87
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (medeleg), line:88, parent:csr_registers
|vpiName:medeleg
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.medeleg
|vpiNetType:36
|vpiRange:
\_range: , line:88
|vpiLeftRange:
\_constant: , line:88
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiRightRange:
\_constant: , line:88
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (mideleg), line:89, parent:csr_registers
|vpiName:mideleg
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.mideleg
|vpiNetType:36
|vpiRange:
\_range: , line:89
|vpiLeftRange:
\_constant: , line:89
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiRightRange:
\_constant: , line:89
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (mepc), line:93, parent:csr_registers
|vpiName:mepc
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.mepc
|vpiNetType:36
|vpiRange:
\_range: , line:93
|vpiLeftRange:
\_constant: , line:93
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiRightRange:
\_constant: , line:93
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (mtimecmp), line:95, parent:csr_registers
|vpiName:mtimecmp
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.mtimecmp
|vpiNetType:36
|vpiRange:
\_range: , line:95
|vpiLeftRange:
\_constant: , line:95
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiRightRange:
\_constant: , line:95
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (mtval), line:98, parent:csr_registers
|vpiName:mtval
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.mtval
|vpiNetType:36
|vpiRange:
\_range: , line:98
|vpiLeftRange:
\_constant: , line:98
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiRightRange:
\_constant: , line:98
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (sepc), line:102, parent:csr_registers
|vpiName:sepc
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.sepc
|vpiNetType:36
|vpiRange:
\_range: , line:102
|vpiLeftRange:
\_constant: , line:102
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiRightRange:
\_constant: , line:102
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (stime), line:104, parent:csr_registers
|vpiName:stime
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.stime
|vpiNetType:36
|vpiRange:
\_range: , line:104
|vpiLeftRange:
\_constant: , line:104
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiRightRange:
\_constant: , line:104
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (stimecmp), line:105, parent:csr_registers
|vpiName:stimecmp
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.stimecmp
|vpiNetType:36
|vpiRange:
\_range: , line:105
|vpiLeftRange:
\_constant: , line:105
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiRightRange:
\_constant: , line:105
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (scause), line:107, parent:csr_registers
|vpiName:scause
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.scause
|vpiNetType:36
|vpiRange:
\_range: , line:107
|vpiLeftRange:
\_constant: , line:107
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiRightRange:
\_constant: , line:107
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (stval), line:108, parent:csr_registers
|vpiName:stval
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.stval
|vpiNetType:36
|vpiRange:
\_range: , line:108
|vpiLeftRange:
\_constant: , line:108
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiRightRange:
\_constant: , line:108
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (sstatus), line:110, parent:csr_registers
|vpiName:sstatus
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.sstatus
|vpiNetType:36
|vpiRange:
\_range: , line:110
|vpiLeftRange:
\_constant: , line:110
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiRightRange:
\_constant: , line:110
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (stvec), line:111, parent:csr_registers
|vpiName:stvec
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.stvec
|vpiNetType:36
|vpiRange:
\_range: , line:111
|vpiLeftRange:
\_constant: , line:111
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiRightRange:
\_constant: , line:111
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (mcycle), line:115, parent:csr_registers
|vpiName:mcycle
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.mcycle
|vpiNetType:36
|vpiRange:
\_range: , line:115
|vpiLeftRange:
\_constant: , line:115
|vpiConstType:7
|vpiDecompile:32
|vpiSize:32
|INT:32
|vpiRightRange:
\_constant: , line:115
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (mtime), line:116, parent:csr_registers
|vpiName:mtime
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.mtime
|vpiNetType:36
|vpiRange:
\_range: , line:116
|vpiLeftRange:
\_constant: , line:116
|vpiConstType:7
|vpiDecompile:32
|vpiSize:32
|INT:32
|vpiRightRange:
\_constant: , line:116
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (minst_ret), line:117, parent:csr_registers
|vpiName:minst_ret
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.minst_ret
|vpiNetType:36
|vpiRange:
\_range: , line:117
|vpiLeftRange:
\_constant: , line:117
|vpiConstType:7
|vpiDecompile:32
|vpiSize:32
|INT:32
|vpiRightRange:
\_constant: , line:117
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (inst_ret_inc), line:118, parent:csr_registers
|vpiName:inst_ret_inc
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.inst_ret_inc
|vpiNetType:36
|vpiRange:
\_range: , line:118
|vpiLeftRange:
\_constant: , line:118
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:118
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (supervisor_write), line:121, parent:csr_registers
|vpiName:supervisor_write
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.supervisor_write
|vpiNetType:36
|vpiNet:
\_logic_net: (machine_write), line:122, parent:csr_registers
|vpiName:machine_write
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.machine_write
|vpiNetType:36
|vpiNet:
\_logic_net: (privilege_exception), line:126, parent:csr_registers
|vpiName:privilege_exception
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.privilege_exception
|vpiNetType:36
|vpiNet:
\_logic_net: (selected_csr), line:128, parent:csr_registers
|vpiName:selected_csr
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.selected_csr
|vpiNetType:36
|vpiRange:
\_range: , line:128
|vpiLeftRange:
\_constant: , line:128
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiRightRange:
\_constant: , line:128
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (selected_csr_r), line:129, parent:csr_registers
|vpiName:selected_csr_r
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.selected_csr_r
|vpiNetType:36
|vpiRange:
\_range: , line:129
|vpiLeftRange:
\_constant: , line:129
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiRightRange:
\_constant: , line:129
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (updated_csr), line:131, parent:csr_registers
|vpiName:updated_csr
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.updated_csr
|vpiNetType:36
|vpiRange:
\_range: , line:131
|vpiLeftRange:
\_constant: , line:131
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:131
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (invalid_addr), line:133, parent:csr_registers
|vpiName:invalid_addr
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.invalid_addr
|vpiNetType:36
|vpiNet:
\_logic_net: (machine_trap), line:135, parent:csr_registers
|vpiName:machine_trap
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.machine_trap
|vpiNetType:36
|vpiNet:
\_logic_net: (supervisor_trap), line:136, parent:csr_registers
|vpiName:supervisor_trap
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.supervisor_trap
|vpiNetType:36
|vpiNet:
\_logic_net: (done), line:138, parent:csr_registers
|vpiName:done
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.done
|vpiNetType:36
|vpiNet:
\_logic_net: (swrite_decoder), line:140, parent:csr_registers
|vpiName:swrite_decoder
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.swrite_decoder
|vpiNetType:36
|vpiRange:
\_range: , line:140
|vpiLeftRange:
\_constant: , line:140
|vpiConstType:7
|vpiDecompile:63
|vpiSize:32
|INT:63
|vpiRightRange:
\_constant: , line:140
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (mwrite_decoder), line:141, parent:csr_registers
|vpiName:mwrite_decoder
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.mwrite_decoder
|vpiNetType:36
|vpiRange:
\_range: , line:141
|vpiLeftRange:
\_constant: , line:141
|vpiConstType:7
|vpiDecompile:63
|vpiSize:32
|INT:63
|vpiRightRange:
\_constant: , line:141
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (illegal_instruction), line:175, parent:csr_registers
|vpiName:illegal_instruction
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.illegal_instruction
|vpiNetType:36
|vpiNet:
\_logic_net: (immu), line:52, parent:csr_registers
|vpiName:immu
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.immu
|vpiNet:
\_logic_net: (dmmu), line:53, parent:csr_registers
|vpiName:dmmu
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.dmmu
|vpiInstance:
\_module: work@gc_unit (gc_unit_block), file:third_party/cores/taiga/core/taiga.sv, line:193, parent:cpu
|vpiArrayNet:
\_array_net: (scratch_regs), line:83, parent:csr_registers
|vpiName:scratch_regs
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.scratch_regs
|vpiSize:32
|vpiNet:
\_logic_net: , parent:scratch_regs
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.scratch_regs
|vpiNetType:36
|vpiRange:
\_range: , line:83
|vpiLeftRange:
\_constant: , line:83
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiRightRange:
\_constant: , line:83
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiRange:
\_range: , line:83
|vpiLeftRange:
\_constant: , line:83
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:83
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiVariables:
\_struct_var: (misa), line:69, parent:csr_registers
|vpiName:misa
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.misa
|vpiTypespec:
\_struct_typespec: (misa_t), line:45
|vpiVariables:
\_struct_var: (mstatus), line:78, parent:csr_registers
|vpiName:mstatus
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.mstatus
|vpiTypespec:
\_struct_typespec: (mstatus_t), line:78
|vpiVariables:
\_struct_var: (mstatus_smask), line:79, parent:csr_registers
|vpiName:mstatus_smask
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.mstatus_smask
|vpiTypespec:
\_struct_typespec: (mstatus_t), line:78
|vpiVariables:
\_struct_var: (mip), line:90, parent:csr_registers
|vpiName:mip
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.mip
|vpiTypespec:
\_struct_typespec: (mip_t), line:103
|vpiVariables:
\_struct_var: (mip_mask), line:90, parent:csr_registers
|vpiName:mip_mask
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.mip_mask
|vpiTypespec:
\_struct_typespec: (mip_t), line:103
|vpiVariables:
\_struct_var: (mie_reg), line:91, parent:csr_registers
|vpiName:mie_reg
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.mie_reg
|vpiTypespec:
\_struct_typespec: (mie_t), line:119
|vpiVariables:
\_struct_var: (mie_mask), line:91, parent:csr_registers
|vpiName:mie_mask
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.mie_mask
|vpiTypespec:
\_struct_typespec: (mie_t), line:119
|vpiVariables:
\_struct_var: (mcause), line:97, parent:csr_registers
|vpiName:mcause
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.mcause
|vpiTypespec:
\_struct_typespec: (mcause_t), line:135
|vpiVariables:
\_struct_var: (sip_mask), line:100, parent:csr_registers
|vpiName:sip_mask
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.sip_mask
|vpiTypespec:
\_struct_typespec: (mip_t), line:103
|vpiVariables:
\_struct_var: (sie_mask), line:101, parent:csr_registers
|vpiName:sie_mask
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.sie_mask
|vpiTypespec:
\_struct_typespec: (mie_t), line:119
|vpiVariables:
\_struct_var: (satp), line:113, parent:csr_registers
|vpiName:satp
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.satp
|vpiTypespec:
\_struct_typespec: (satp_t), line:142
|vpiVariables:
\_struct_var: (csr_addr), line:125, parent:csr_registers
|vpiName:csr_addr
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_registers.csr_addr
|vpiTypespec:
\_struct_typespec: (csr_addr_t), line:37
|vpiParameter:
\_parameter: (ALU_UNIT_WB_ID), line:190
|vpiName:ALU_UNIT_WB_ID
|INT:32
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (BRANCH_PREDICTOR_WAYS), line:159
|vpiName:BRANCH_PREDICTOR_WAYS
|INT:9
|vpiParameter:
\_parameter: (BRANCH_TABLE_ENTRIES), line:160
|vpiName:BRANCH_TABLE_ENTRIES
|INT:4
|vpiParameter:
\_parameter: (BRANCH_UNIT_ID), line:195
|vpiName:BRANCH_UNIT_ID
|INT:8
|vpiParameter:
\_parameter: (BUS_ADDR_H), line:107
|vpiName:BUS_ADDR_H
|INT:1
|vpiParameter:
\_parameter: (BUS_ADDR_L), line:106
|vpiName:BUS_ADDR_L
|INT:0
|vpiParameter:
\_parameter: (BUS_BIT_CHECK), line:108
|vpiName:BUS_BIT_CHECK
|INT:1
|vpiParameter:
\_parameter: (BUS_TYPE), line:89
|vpiName:BUS_TYPE
|INT:5
|vpiParameter:
\_parameter: (COUNTER_W), line:42
|vpiName:COUNTER_W
|INT:33
|vpiParameter:
\_parameter: (CPU_ID), line:38
|vpiName:CPU_ID
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_ADDR_WIDTH), line:113
|vpiName:C_M_AXI_ADDR_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_DATA_WIDTH), line:114
|vpiName:C_M_AXI_DATA_WIDTH
|INT:1
|vpiParameter:
\_parameter: (DCACHE_LINES), line:133
|vpiName:DCACHE_LINES
|INT:-2146435073
|vpiParameter:
\_parameter: (DCACHE_LINE_ADDR_W), line:135
|vpiName:DCACHE_LINE_ADDR_W
|INT:1073741824
|vpiParameter:
\_parameter: (DCACHE_LINE_W), line:136
|vpiName:DCACHE_LINE_W
|INT:1342177279
|vpiParameter:
\_parameter: (DCACHE_SUB_LINE_ADDR_W), line:137
|vpiName:DCACHE_SUB_LINE_ADDR_W
|INT:4
|vpiParameter:
\_parameter: (DCACHE_TAG_W), line:138
|vpiName:DCACHE_TAG_W
|INT:1610612736
|vpiParameter:
\_parameter: (DCACHE_WAYS), line:134
|vpiName:DCACHE_WAYS
|INT:4
|vpiParameter:
\_parameter: (DIV_ALGORITHM), line:67
|vpiName:DIV_ALGORITHM
|INT:0
|vpiParameter:
\_parameter: (DIV_UNIT_WB_ID), line:192
|vpiName:DIV_UNIT_WB_ID
|INT:2
|vpiParameter:
\_parameter: (DTLB_DEPTH), line:152
|vpiName:DTLB_DEPTH
|INT:512
|vpiParameter:
\_parameter: (DTLB_WAYS), line:151
|vpiName:DTLB_WAYS
|INT:32
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (ENABLE_M_MODE), line:34
|vpiName:ENABLE_M_MODE
|INT:1
|vpiParameter:
\_parameter: (ENABLE_S_MODE), line:36
|vpiName:ENABLE_S_MODE
|INT:0
|vpiParameter:
\_parameter: (ENABLE_TRACE_INTERFACE), line:172
|vpiName:ENABLE_TRACE_INTERFACE
|INT:2
|vpiParameter:
\_parameter: (FETCH_BUFFER_DEPTH), line:168
|vpiName:FETCH_BUFFER_DEPTH
|INT:512
|vpiParameter:
\_parameter: (FPGA_VENDOR), line:27
|vpiName:FPGA_VENDOR
|STRING:"xilinx"
|vpiParameter:
\_parameter: (GC_UNIT_ID), line:196
|vpiName:GC_UNIT_ID
|INT:4
|vpiParameter:
\_parameter: (ICACHE_LINES), line:121
|vpiName:ICACHE_LINES
|INT:2
|vpiParameter:
\_parameter: (ICACHE_LINE_ADDR_W), line:123
|vpiName:ICACHE_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_LINE_W), line:124
|vpiName:ICACHE_LINE_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_SUB_LINE_ADDR_W), line:125
|vpiName:ICACHE_SUB_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_TAG_W), line:126
|vpiName:ICACHE_TAG_W
|INT:-2147483648
|vpiParameter:
\_parameter: (ICACHE_WAYS), line:122
|vpiName:ICACHE_WAYS
|INT:1
|vpiParameter:
\_parameter: (ITLB_DEPTH), line:146
|vpiName:ITLB_DEPTH
|INT:32
|vpiParameter:
\_parameter: (ITLB_WAYS), line:145
|vpiName:ITLB_WAYS
|INT:4
|vpiParameter:
\_parameter: (L1_CONNECTIONS), line:177
|vpiName:L1_CONNECTIONS
|INT:9
|vpiParameter:
\_parameter: (L1_DCACHE_ID), line:178
|vpiName:L1_DCACHE_ID
|INT:4
|vpiParameter:
\_parameter: (L1_DMMU_ID), line:179
|vpiName:L1_DMMU_ID
|INT:2
|vpiParameter:
\_parameter: (L1_ICACHE_ID), line:180
|vpiName:L1_ICACHE_ID
|INT:19
|vpiParameter:
\_parameter: (L1_IMMU_ID), line:181
|vpiName:L1_IMMU_ID
|INT:0
|vpiParameter:
\_parameter: (LS_UNIT_WB_ID), line:191
|vpiName:LS_UNIT_WB_ID
|INT:1
|vpiParameter:
\_parameter: (MAX_INFLIGHT_COUNT), line:167
|vpiName:MAX_INFLIGHT_COUNT
|INT:19
|vpiParameter:
\_parameter: (MEMORY_ADDR_H), line:103
|vpiName:MEMORY_ADDR_H
|INT:12
|vpiParameter:
\_parameter: (MEMORY_ADDR_L), line:102
|vpiName:MEMORY_ADDR_L
|INT:11
|vpiParameter:
\_parameter: (MEMORY_BIT_CHECK), line:104
|vpiName:MEMORY_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (MUL_UNIT_WB_ID), line:193
|vpiName:MUL_UNIT_WB_ID
|INT:512
|vpiParameter:
\_parameter: (NUM_UNITS), line:188
|vpiName:NUM_UNITS
|INT:2
|vpiParameter:
\_parameter: (NUM_WB_UNITS), line:186
|vpiName:NUM_WB_UNITS
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (RAS_DEPTH), line:161
|vpiName:RAS_DEPTH
|INT:2
|vpiParameter:
\_parameter: (RESET_VEC), line:39
|vpiName:RESET_VEC
|INT:-2147483648
|vpiParameter:
\_parameter: (SCRATCH_ADDR_H), line:99
|vpiName:SCRATCH_ADDR_H
|INT:9
|vpiParameter:
\_parameter: (SCRATCH_ADDR_L), line:98
|vpiName:SCRATCH_ADDR_L
|INT:8
|vpiParameter:
\_parameter: (SCRATCH_BIT_CHECK), line:100
|vpiName:SCRATCH_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (USE_AMO), line:70
|vpiName:USE_AMO
|INT:1
|vpiParameter:
\_parameter: (USE_BRANCH_PREDICTOR), line:158
|vpiName:USE_BRANCH_PREDICTOR
|INT:2
|vpiParameter:
\_parameter: (USE_BUS), line:88
|vpiName:USE_BUS
|INT:4
|vpiParameter:
\_parameter: (USE_DCACHE), line:92
|vpiName:USE_DCACHE
|INT:6
|vpiParameter:
\_parameter: (USE_DIV), line:49
|vpiName:USE_DIV
|INT:1
|vpiParameter:
\_parameter: (USE_DTAG_INVALIDATIONS), line:140
|vpiName:USE_DTAG_INVALIDATIONS
|INT:1879048191
|vpiParameter:
\_parameter: (USE_D_SCRATCH_MEM), line:79
|vpiName:USE_D_SCRATCH_MEM
|INT:3
|vpiParameter:
\_parameter: (USE_ICACHE), line:93
|vpiName:USE_ICACHE
|INT:7
|vpiParameter:
\_parameter: (USE_I_SCRATCH_MEM), line:78
|vpiName:USE_I_SCRATCH_MEM
|INT:2
|vpiParameter:
\_parameter: (USE_MUL), line:48
|vpiName:USE_MUL
|INT:1
|vpiParameter:
\_parameter: (WB_UNITS_WIDTH), line:187
|vpiName:WB_UNITS_WIDTH
|INT:32
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiNet:
\_logic_net: (clk), line:28, parent:gc_unit_block
|vpiNet:
\_logic_net: (rst), line:29, parent:gc_unit_block
|vpiNet:
\_logic_net: (gc_inputs), line:34, parent:gc_unit_block
|vpiNet:
\_logic_net: (instruction_issued_no_rd), line:35, parent:gc_unit_block
|vpiNet:
\_logic_net: (gc_flush_required), line:36, parent:gc_unit_block
|vpiNet:
\_logic_net: (branch_flush), line:38, parent:gc_unit_block
|vpiNet:
\_logic_net: (ls_exception), line:41, parent:gc_unit_block
|vpiNet:
\_logic_net: (ls_exception_valid), line:42, parent:gc_unit_block
|vpiNet:
\_logic_net: (tlb_on), line:45, parent:gc_unit_block
|vpiNet:
\_logic_net: (asid), line:46, parent:gc_unit_block
|vpiNet:
\_logic_net: (instruction_complete), line:53, parent:gc_unit_block
|vpiNet:
\_logic_net: (instruction_queue_empty), line:54, parent:gc_unit_block
|vpiNet:
\_logic_net: (oldest_id), line:55, parent:gc_unit_block
|vpiNet:
\_logic_net: (interrupt), line:59, parent:gc_unit_block
|vpiNet:
\_logic_net: (timer_interrupt), line:60, parent:gc_unit_block
|vpiNet:
\_logic_net: (gc_issue_hold), line:63, parent:gc_unit_block
|vpiNet:
\_logic_net: (gc_issue_flush), line:64, parent:gc_unit_block
|vpiNet:
\_logic_net: (gc_fetch_flush), line:65, parent:gc_unit_block
|vpiNet:
\_logic_net: (gc_fetch_pc_override), line:66, parent:gc_unit_block
|vpiNet:
\_logic_net: (gc_supress_writeback), line:67, parent:gc_unit_block
|vpiNet:
\_logic_net: (gc_fetch_pc), line:69, parent:gc_unit_block
|vpiNet:
\_logic_net: (csr_rd), line:72, parent:gc_unit_block
|vpiNet:
\_logic_net: (csr_id), line:73, parent:gc_unit_block
|vpiNet:
\_logic_net: (csr_done), line:74, parent:gc_unit_block
|vpiNet:
\_logic_net: (tlb_clear_done), line:133, parent:gc_unit_block
|vpiName:tlb_clear_done
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.tlb_clear_done
|vpiNetType:36
|vpiNet:
\_logic_net: (i_fence_flush), line:135, parent:gc_unit_block
|vpiName:i_fence_flush
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.i_fence_flush
|vpiNetType:36
|vpiNet:
\_logic_net: (second_cycle_flush), line:137, parent:gc_unit_block
|vpiName:second_cycle_flush
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.second_cycle_flush
|vpiNetType:36
|vpiNet:
\_logic_net: (mret), line:140, parent:gc_unit_block
|vpiNet:
\_logic_net: (sret), line:141, parent:gc_unit_block
|vpiNet:
\_logic_net: (wb_csr), line:142, parent:gc_unit_block
|vpiNet:
\_logic_net: (current_privilege), line:146, parent:gc_unit_block
|vpiNet:
\_logic_net: (trap_pc), line:147, parent:gc_unit_block
|vpiNet:
\_logic_net: (csr_mepc), line:148, parent:gc_unit_block
|vpiNet:
\_logic_net: (csr_sepc), line:149, parent:gc_unit_block
|vpiNet:
\_logic_net: (fn3), line:152, parent:gc_unit_block
|vpiName:fn3
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.fn3
|vpiNetType:36
|vpiRange:
\_range: , line:152
|vpiLeftRange:
\_constant: , line:152
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiRightRange:
\_constant: , line:152
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (opcode), line:153, parent:gc_unit_block
|vpiName:opcode
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.opcode
|vpiNetType:36
|vpiRange:
\_range: , line:153
|vpiLeftRange:
\_constant: , line:153
|vpiConstType:7
|vpiDecompile:6
|vpiSize:32
|INT:6
|vpiRightRange:
\_constant: , line:153
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (opcode_trim), line:154, parent:gc_unit_block
|vpiName:opcode_trim
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.opcode_trim
|vpiNetType:36
|vpiRange:
\_range: , line:154
|vpiLeftRange:
\_constant: , line:154
|vpiConstType:7
|vpiDecompile:4
|vpiSize:32
|INT:4
|vpiRightRange:
\_constant: , line:154
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (rs1_addr), line:156, parent:gc_unit_block
|vpiName:rs1_addr
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.rs1_addr
|vpiNetType:36
|vpiRange:
\_range: , line:156
|vpiLeftRange:
\_constant: , line:156
|vpiConstType:7
|vpiDecompile:4
|vpiSize:32
|INT:4
|vpiRightRange:
\_constant: , line:156
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (rs2_addr), line:157, parent:gc_unit_block
|vpiName:rs2_addr
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.rs2_addr
|vpiNetType:36
|vpiRange:
\_range: , line:157
|vpiLeftRange:
\_constant: , line:157
|vpiConstType:7
|vpiDecompile:4
|vpiSize:32
|INT:4
|vpiRightRange:
\_constant: , line:157
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (future_rd_addr), line:158, parent:gc_unit_block
|vpiName:future_rd_addr
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.future_rd_addr
|vpiNetType:36
|vpiRange:
\_range: , line:158
|vpiLeftRange:
\_constant: , line:158
|vpiConstType:7
|vpiDecompile:4
|vpiSize:32
|INT:4
|vpiRightRange:
\_constant: , line:158
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (is_csr), line:160, parent:gc_unit_block
|vpiName:is_csr
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.is_csr
|vpiNetType:36
|vpiNet:
\_logic_net: (processing_csr), line:161, parent:gc_unit_block
|vpiName:processing_csr
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.processing_csr
|vpiNetType:36
|vpiNet:
\_logic_net: (csr_ready_to_complete), line:162, parent:gc_unit_block
|vpiName:csr_ready_to_complete
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_ready_to_complete
|vpiNetType:36
|vpiNet:
\_logic_net: (csr_ready_to_complete_r), line:163, parent:gc_unit_block
|vpiName:csr_ready_to_complete_r
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_ready_to_complete_r
|vpiNetType:36
|vpiNet:
\_logic_net: (ls_exception_first_cycle), line:219, parent:gc_unit_block
|vpiName:ls_exception_first_cycle
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.ls_exception_first_cycle
|vpiNetType:36
|vpiNet:
\_logic_net: (ls_exception_second_cycle), line:220, parent:gc_unit_block
|vpiName:ls_exception_second_cycle
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.ls_exception_second_cycle
|vpiNetType:36
|vpiNet:
\_logic_net: (issue), line:33, parent:gc_unit_block
|vpiName:issue
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.issue
|vpiNet:
\_logic_net: (immu), line:49, parent:gc_unit_block
|vpiName:immu
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.immu
|vpiNet:
\_logic_net: (dmmu), line:50, parent:gc_unit_block
|vpiName:dmmu
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.dmmu
|vpiInstance:
\_module: work@taiga (cpu), file:third_party/cores/taiga/examples/zedboard/taiga_wrapper.sv, line:233, parent:work@taiga_wrapper
|vpiVariables:
\_enum_var: (state), line:130, parent:gc_unit_block
|vpiName:state
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.state
|vpiTypespec:
\_enum_typespec: (gc_state), line:129
|vpiVariables:
\_enum_var: (next_state), line:131, parent:gc_unit_block
|vpiName:next_state
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.next_state
|vpiTypespec:
\_enum_typespec: (gc_state), line:129
|vpiVariables:
\_enum_var: (ecall_code), line:136, parent:gc_unit_block
|vpiName:ecall_code
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.ecall_code
|vpiTypespec:
\_enum_typespec: (exception_code_t), line:245
|vpiVariables:
\_struct_var: (csr_inputs), line:143, parent:gc_unit_block
|vpiName:csr_inputs
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_inputs
|vpiTypespec:
\_struct_typespec: (csr_inputs_t), line:396
|vpiVariables:
\_struct_var: (gc_exception), line:144, parent:gc_unit_block
|vpiName:gc_exception
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.gc_exception
|vpiTypespec:
\_struct_typespec: (exception_packet_t), line:263
|vpiVariables:
\_struct_var: (csr_exception), line:145, parent:gc_unit_block
|vpiName:csr_exception
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.csr_exception
|vpiTypespec:
\_struct_typespec: (exception_packet_t), line:263
|vpiVariables:
\_logic_var: (instruction_id), line:164, parent:gc_unit_block
|vpiName:instruction_id
|vpiFullName:work@taiga_wrapper.cpu.gc_unit_block.instruction_id
|vpiParameter:
\_parameter: (ALU_UNIT_WB_ID), line:190
|vpiName:ALU_UNIT_WB_ID
|INT:32
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (BRANCH_PREDICTOR_WAYS), line:159
|vpiName:BRANCH_PREDICTOR_WAYS
|INT:9
|vpiParameter:
\_parameter: (BRANCH_TABLE_ENTRIES), line:160
|vpiName:BRANCH_TABLE_ENTRIES
|INT:4
|vpiParameter:
\_parameter: (BRANCH_UNIT_ID), line:195
|vpiName:BRANCH_UNIT_ID
|INT:8
|vpiParameter:
\_parameter: (BUS_ADDR_H), line:107
|vpiName:BUS_ADDR_H
|INT:1
|vpiParameter:
\_parameter: (BUS_ADDR_L), line:106
|vpiName:BUS_ADDR_L
|INT:0
|vpiParameter:
\_parameter: (BUS_BIT_CHECK), line:108
|vpiName:BUS_BIT_CHECK
|INT:1
|vpiParameter:
\_parameter: (BUS_TYPE), line:89
|vpiName:BUS_TYPE
|INT:5
|vpiParameter:
\_parameter: (CLEAR_DEPTH), line:80
|vpiName:CLEAR_DEPTH
|INT:0
|vpiParameter:
\_parameter: (COUNTER_W), line:42
|vpiName:COUNTER_W
|INT:33
|vpiParameter:
\_parameter: (CPU_ID), line:38
|vpiName:CPU_ID
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_ADDR_WIDTH), line:113
|vpiName:C_M_AXI_ADDR_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_DATA_WIDTH), line:114
|vpiName:C_M_AXI_DATA_WIDTH
|INT:1
|vpiParameter:
\_parameter: (DCACHE_LINES), line:133
|vpiName:DCACHE_LINES
|INT:-2146435073
|vpiParameter:
\_parameter: (DCACHE_LINE_ADDR_W), line:135
|vpiName:DCACHE_LINE_ADDR_W
|INT:1073741824
|vpiParameter:
\_parameter: (DCACHE_LINE_W), line:136
|vpiName:DCACHE_LINE_W
|INT:1342177279
|vpiParameter:
\_parameter: (DCACHE_SUB_LINE_ADDR_W), line:137
|vpiName:DCACHE_SUB_LINE_ADDR_W
|INT:4
|vpiParameter:
\_parameter: (DCACHE_TAG_W), line:138
|vpiName:DCACHE_TAG_W
|INT:1610612736
|vpiParameter:
\_parameter: (DCACHE_WAYS), line:134
|vpiName:DCACHE_WAYS
|INT:4
|vpiParameter:
\_parameter: (DIV_ALGORITHM), line:67
|vpiName:DIV_ALGORITHM
|INT:0
|vpiParameter:
\_parameter: (DIV_UNIT_WB_ID), line:192
|vpiName:DIV_UNIT_WB_ID
|INT:2
|vpiParameter:
\_parameter: (DTLB_DEPTH), line:152
|vpiName:DTLB_DEPTH
|INT:512
|vpiParameter:
\_parameter: (DTLB_WAYS), line:151
|vpiName:DTLB_WAYS
|INT:32
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (ENABLE_M_MODE), line:34
|vpiName:ENABLE_M_MODE
|INT:1
|vpiParameter:
\_parameter: (ENABLE_S_MODE), line:36
|vpiName:ENABLE_S_MODE
|INT:0
|vpiParameter:
\_parameter: (ENABLE_TRACE_INTERFACE), line:172
|vpiName:ENABLE_TRACE_INTERFACE
|INT:2
|vpiParameter:
\_parameter: (FETCH_BUFFER_DEPTH), line:168
|vpiName:FETCH_BUFFER_DEPTH
|INT:512
|vpiParameter:
\_parameter: (FPGA_VENDOR), line:27
|vpiName:FPGA_VENDOR
|STRING:"xilinx"
|vpiParameter:
\_parameter: (GC_UNIT_ID), line:196
|vpiName:GC_UNIT_ID
|INT:4
|vpiParameter:
\_parameter: (ICACHE_LINES), line:121
|vpiName:ICACHE_LINES
|INT:2
|vpiParameter:
\_parameter: (ICACHE_LINE_ADDR_W), line:123
|vpiName:ICACHE_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_LINE_W), line:124
|vpiName:ICACHE_LINE_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_SUB_LINE_ADDR_W), line:125
|vpiName:ICACHE_SUB_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_TAG_W), line:126
|vpiName:ICACHE_TAG_W
|INT:-2147483648
|vpiParameter:
\_parameter: (ICACHE_WAYS), line:122
|vpiName:ICACHE_WAYS
|INT:1
|vpiParameter:
\_parameter: (ITLB_DEPTH), line:146
|vpiName:ITLB_DEPTH
|INT:32
|vpiParameter:
\_parameter: (ITLB_WAYS), line:145
|vpiName:ITLB_WAYS
|INT:4
|vpiParameter:
\_parameter: (L1_CONNECTIONS), line:177
|vpiName:L1_CONNECTIONS
|INT:9
|vpiParameter:
\_parameter: (L1_DCACHE_ID), line:178
|vpiName:L1_DCACHE_ID
|INT:4
|vpiParameter:
\_parameter: (L1_DMMU_ID), line:179
|vpiName:L1_DMMU_ID
|INT:2
|vpiParameter:
\_parameter: (L1_ICACHE_ID), line:180
|vpiName:L1_ICACHE_ID
|INT:19
|vpiParameter:
\_parameter: (L1_IMMU_ID), line:181
|vpiName:L1_IMMU_ID
|INT:0
|vpiParameter:
\_parameter: (LS_UNIT_WB_ID), line:191
|vpiName:LS_UNIT_WB_ID
|INT:1
|vpiParameter:
\_parameter: (MAX_INFLIGHT_COUNT), line:167
|vpiName:MAX_INFLIGHT_COUNT
|INT:19
|vpiParameter:
\_parameter: (MEMORY_ADDR_H), line:103
|vpiName:MEMORY_ADDR_H
|INT:12
|vpiParameter:
\_parameter: (MEMORY_ADDR_L), line:102
|vpiName:MEMORY_ADDR_L
|INT:11
|vpiParameter:
\_parameter: (MEMORY_BIT_CHECK), line:104
|vpiName:MEMORY_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (MUL_UNIT_WB_ID), line:193
|vpiName:MUL_UNIT_WB_ID
|INT:512
|vpiParameter:
\_parameter: (NUM_UNITS), line:188
|vpiName:NUM_UNITS
|INT:2
|vpiParameter:
\_parameter: (NUM_WB_UNITS), line:186
|vpiName:NUM_WB_UNITS
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (RAS_DEPTH), line:161
|vpiName:RAS_DEPTH
|INT:2
|vpiParameter:
\_parameter: (RESET_VEC), line:39
|vpiName:RESET_VEC
|INT:-2147483648
|vpiParameter:
\_parameter: (SCRATCH_ADDR_H), line:99
|vpiName:SCRATCH_ADDR_H
|INT:9
|vpiParameter:
\_parameter: (SCRATCH_ADDR_L), line:98
|vpiName:SCRATCH_ADDR_L
|INT:8
|vpiParameter:
\_parameter: (SCRATCH_BIT_CHECK), line:100
|vpiName:SCRATCH_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (TLB_CLEAR_DEPTH), line:78
|vpiName:TLB_CLEAR_DEPTH
|INT:1
|vpiParameter:
\_parameter: (USE_AMO), line:70
|vpiName:USE_AMO
|INT:1
|vpiParameter:
\_parameter: (USE_BRANCH_PREDICTOR), line:158
|vpiName:USE_BRANCH_PREDICTOR
|INT:2
|vpiParameter:
\_parameter: (USE_BUS), line:88
|vpiName:USE_BUS
|INT:4
|vpiParameter:
\_parameter: (USE_DCACHE), line:92
|vpiName:USE_DCACHE
|INT:6
|vpiParameter:
\_parameter: (USE_DIV), line:49
|vpiName:USE_DIV
|INT:1
|vpiParameter:
\_parameter: (USE_DTAG_INVALIDATIONS), line:140
|vpiName:USE_DTAG_INVALIDATIONS
|INT:1879048191
|vpiParameter:
\_parameter: (USE_D_SCRATCH_MEM), line:79
|vpiName:USE_D_SCRATCH_MEM
|INT:3
|vpiParameter:
\_parameter: (USE_ICACHE), line:93
|vpiName:USE_ICACHE
|INT:7
|vpiParameter:
\_parameter: (USE_I_SCRATCH_MEM), line:78
|vpiName:USE_I_SCRATCH_MEM
|INT:2
|vpiParameter:
\_parameter: (USE_MUL), line:48
|vpiName:USE_MUL
|INT:1
|vpiParameter:
\_parameter: (WB_UNITS_WIDTH), line:187
|vpiName:WB_UNITS_WIDTH
|INT:32
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiModule:
\_module: work@write_back (write_back_mux), file:third_party/cores/taiga/core/taiga.sv, line:204, parent:cpu
|vpiDefName:work@write_back
|vpiName:write_back_mux
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux
|vpiPort:
\_port: (clk), line:27, parent:write_back_mux
|vpiName:clk
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (clk), line:204
|vpiName:clk
|vpiActual:
\_logic_net: (clk), line:27, parent:cpu
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (clk), line:27, parent:write_back_mux
|vpiName:clk
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.clk
|vpiNetType:36
|vpiPort:
\_port: (rst), line:28, parent:write_back_mux
|vpiName:rst
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (rst), line:204
|vpiName:rst
|vpiActual:
\_logic_net: (rst), line:28, parent:cpu
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (rst), line:28, parent:write_back_mux
|vpiName:rst
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.rst
|vpiNetType:36
|vpiPort:
\_port: (gc_fetch_flush), line:30, parent:write_back_mux
|vpiName:gc_fetch_flush
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (gc_fetch_flush), line:204
|vpiName:gc_fetch_flush
|vpiActual:
\_logic_net: (gc_fetch_flush), line:95, parent:cpu
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (gc_fetch_flush), line:30, parent:write_back_mux
|vpiName:gc_fetch_flush
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.gc_fetch_flush
|vpiNetType:36
|vpiPort:
\_port: (instruction_issued_with_rd), line:31, parent:write_back_mux
|vpiName:instruction_issued_with_rd
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (instruction_issued_with_rd), line:204
|vpiName:instruction_issued_with_rd
|vpiActual:
\_logic_net: (instruction_issued_with_rd), line:113, parent:cpu
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (instruction_issued_with_rd), line:31, parent:write_back_mux
|vpiName:instruction_issued_with_rd
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.instruction_issued_with_rd
|vpiNetType:36
|vpiPort:
\_port: (unit_wb), line:33, parent:write_back_mux
|vpiName:unit_wb
|vpiDirection:1
|vpiTypedef:
\_struct_typespec: (unit_writeback_t), line:295
|vpiHighConn:
\_ref_obj: (unit_wb), line:204
|vpiName:unit_wb
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (unit_wb), line:33, parent:write_back_mux
|vpiName:unit_wb
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.unit_wb
|vpiPort:
\_port: (rf_wb), line:34, parent:write_back_mux
|vpiName:rf_wb
|vpiDirection:5
|vpiHighConn:
\_ref_obj: (rf_wb), line:204
|vpiName:rf_wb
|vpiActual:
\_interface: work@register_file_writeback_interface (rf_wb), file:third_party/cores/taiga/core/taiga.sv, line:71
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_modport: (writeback)
|vpiName:writeback
|vpiIODecl:
\_io_decl: (rd_addr)
|vpiName:rd_addr
|vpiDirection:2
|vpiExpr:
\_logic_net: (rd_addr), line:124
|vpiName:rd_addr
|vpiNetType:36
|vpiRange:
\_range: , line:124
|vpiLeftRange:
\_constant: , line:124
|vpiConstType:7
|vpiDecompile:4
|vpiSize:32
|INT:4
|vpiRightRange:
\_constant: , line:124
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (retiring)
|vpiName:retiring
|vpiDirection:2
|vpiExpr:
\_logic_net: (retiring), line:125
|vpiName:retiring
|vpiNetType:36
|vpiIODecl:
\_io_decl: (rd_nzero)
|vpiName:rd_nzero
|vpiDirection:2
|vpiExpr:
\_logic_net: (rd_nzero), line:126
|vpiName:rd_nzero
|vpiNetType:36
|vpiIODecl:
\_io_decl: (rd_data)
|vpiName:rd_data
|vpiDirection:2
|vpiExpr:
\_logic_net: (rd_data), line:128
|vpiName:rd_data
|vpiNetType:36
|vpiRange:
\_range: , line:128
|vpiLeftRange:
\_constant: , line:128
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiRightRange:
\_constant: , line:128
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (id)
|vpiName:id
|vpiDirection:2
|vpiIODecl:
\_io_decl: (rs1_data)
|vpiName:rs1_data
|vpiDirection:2
|vpiExpr:
\_logic_net: (rs1_data), line:134
|vpiName:rs1_data
|vpiNetType:36
|vpiRange:
\_range: , line:134
|vpiLeftRange:
\_constant: , line:134
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiRightRange:
\_constant: , line:134
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (rs2_data)
|vpiName:rs2_data
|vpiDirection:2
|vpiExpr:
\_logic_net: (rs2_data), line:135
|vpiName:rs2_data
|vpiNetType:36
|vpiRange:
\_range: , line:135
|vpiLeftRange:
\_constant: , line:135
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiRightRange:
\_constant: , line:135
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (rs1_valid)
|vpiName:rs1_valid
|vpiDirection:2
|vpiExpr:
\_logic_net: (rs1_valid), line:136
|vpiName:rs1_valid
|vpiNetType:36
|vpiIODecl:
\_io_decl: (rs2_valid)
|vpiName:rs2_valid
|vpiDirection:2
|vpiExpr:
\_logic_net: (rs2_valid), line:137
|vpiName:rs2_valid
|vpiNetType:36
|vpiIODecl:
\_io_decl: (rs1_id)
|vpiName:rs1_id
|vpiDirection:1
|vpiIODecl:
\_io_decl: (rs2_id)
|vpiName:rs2_id
|vpiDirection:1
|vpiInterface:
\_interface: work@register_file_writeback_interface (rf_wb), file:third_party/cores/taiga/core/taiga.sv, line:204
|vpiDefName:work@register_file_writeback_interface
|vpiName:rf_wb
|vpiModport:
\_modport: (unit)
|vpiName:unit
|vpiIODecl:
\_io_decl: (rd_addr)
|vpiName:rd_addr
|vpiDirection:1
|vpiExpr:
\_logic_net: (rd_addr), line:124
|vpiIODecl:
\_io_decl: (retiring)
|vpiName:retiring
|vpiDirection:1
|vpiExpr:
\_logic_net: (retiring), line:125
|vpiIODecl:
\_io_decl: (rd_nzero)
|vpiName:rd_nzero
|vpiDirection:1
|vpiExpr:
\_logic_net: (rd_nzero), line:126
|vpiIODecl:
\_io_decl: (rd_data)
|vpiName:rd_data
|vpiDirection:1
|vpiExpr:
\_logic_net: (rd_data), line:128
|vpiIODecl:
\_io_decl: (id)
|vpiName:id
|vpiDirection:1
|vpiIODecl:
\_io_decl: (rs1_data)
|vpiName:rs1_data
|vpiDirection:1
|vpiExpr:
\_logic_net: (rs1_data), line:134
|vpiIODecl:
\_io_decl: (rs2_data)
|vpiName:rs2_data
|vpiDirection:1
|vpiExpr:
\_logic_net: (rs2_data), line:135
|vpiIODecl:
\_io_decl: (rs1_valid)
|vpiName:rs1_valid
|vpiDirection:1
|vpiExpr:
\_logic_net: (rs1_valid), line:136
|vpiIODecl:
\_io_decl: (rs2_valid)
|vpiName:rs2_valid
|vpiDirection:1
|vpiExpr:
\_logic_net: (rs2_valid), line:137
|vpiIODecl:
\_io_decl: (rs1_id)
|vpiName:rs1_id
|vpiDirection:2
|vpiIODecl:
\_io_decl: (rs2_id)
|vpiName:rs2_id
|vpiDirection:2
|vpiInterface:
\_interface: work@register_file_writeback_interface (rf_wb), file:third_party/cores/taiga/core/taiga.sv, line:204
|vpiModport:
\_modport: (writeback)
|vpiPort:
\_port: (ti), line:35, parent:write_back_mux
|vpiName:ti
|vpiDirection:5
|vpiHighConn:
\_ref_obj: (ti), line:204
|vpiName:ti
|vpiActual:
\_interface: work@tracking_interface (ti), file:third_party/cores/taiga/core/taiga.sv, line:69
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_modport: (wb)
|vpiName:wb
|vpiIODecl:
\_io_decl: (issue_id)
|vpiName:issue_id
|vpiDirection:2
|vpiIODecl:
\_io_decl: (id_available)
|vpiName:id_available
|vpiDirection:2
|vpiExpr:
\_logic_net: (id_available), line:147
|vpiName:id_available
|vpiNetType:36
|vpiIODecl:
\_io_decl: (inflight_packet)
|vpiName:inflight_packet
|vpiDirection:1
|vpiIODecl:
\_io_decl: (issued)
|vpiName:issued
|vpiDirection:1
|vpiExpr:
\_logic_net: (issued), line:150
|vpiName:issued
|vpiNetType:36
|vpiIODecl:
\_io_decl: (issue_unit_id)
|vpiName:issue_unit_id
|vpiDirection:1
|vpiExpr:
\_logic_net: (issue_unit_id), line:151
|vpiName:issue_unit_id
|vpiNetType:36
|vpiRange:
\_range: , line:151
|vpiLeftRange:
\_constant: , line:151
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:151
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiInterface:
\_interface: work@tracking_interface (ti), file:third_party/cores/taiga/core/taiga.sv, line:204
|vpiDefName:work@tracking_interface
|vpiName:ti
|vpiModport:
\_modport: (decode)
|vpiName:decode
|vpiIODecl:
\_io_decl: (issue_id)
|vpiName:issue_id
|vpiDirection:1
|vpiIODecl:
\_io_decl: (id_available)
|vpiName:id_available
|vpiDirection:1
|vpiExpr:
\_logic_net: (id_available), line:147
|vpiIODecl:
\_io_decl: (inflight_packet)
|vpiName:inflight_packet
|vpiDirection:2
|vpiIODecl:
\_io_decl: (issued)
|vpiName:issued
|vpiDirection:2
|vpiExpr:
\_logic_net: (issued), line:150
|vpiIODecl:
\_io_decl: (issue_unit_id)
|vpiName:issue_unit_id
|vpiDirection:2
|vpiExpr:
\_logic_net: (issue_unit_id), line:151
|vpiInterface:
\_interface: work@tracking_interface (ti), file:third_party/cores/taiga/core/taiga.sv, line:204
|vpiModport:
\_modport: (wb)
|vpiPort:
\_port: (instruction_complete), line:36, parent:write_back_mux
|vpiName:instruction_complete
|vpiDirection:2
|vpiHighConn:
\_ref_obj: (instruction_complete), line:204
|vpiName:instruction_complete
|vpiActual:
\_logic_net: (instruction_complete), line:114, parent:cpu
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (instruction_complete), line:36, parent:write_back_mux
|vpiName:instruction_complete
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.instruction_complete
|vpiNetType:36
|vpiPort:
\_port: (instruction_queue_empty), line:37, parent:write_back_mux
|vpiName:instruction_queue_empty
|vpiDirection:2
|vpiHighConn:
\_ref_obj: (instruction_queue_empty), line:204
|vpiName:instruction_queue_empty
|vpiActual:
\_logic_net: (instruction_queue_empty), line:109, parent:cpu
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (instruction_queue_empty), line:37, parent:write_back_mux
|vpiName:instruction_queue_empty
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.instruction_queue_empty
|vpiNetType:36
|vpiPort:
\_port: (oldest_id), line:38, parent:write_back_mux
|vpiName:oldest_id
|vpiDirection:2
|vpiTypedef:
\_logic_typespec: (instruction_id_t), line:30
|vpiHighConn:
\_ref_obj: (oldest_id), line:204
|vpiName:oldest_id
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (oldest_id), line:38, parent:write_back_mux
|vpiName:oldest_id
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.oldest_id
|vpiPort:
\_port: (store_done_id), line:40, parent:write_back_mux
|vpiName:store_done_id
|vpiDirection:1
|vpiTypedef:
\_logic_typespec: (instruction_id_t), line:30
|vpiHighConn:
\_ref_obj: (store_done_id), line:204
|vpiName:store_done_id
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (store_done_id), line:40, parent:write_back_mux
|vpiName:store_done_id
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.store_done_id
|vpiPort:
\_port: (store_complete), line:41, parent:write_back_mux
|vpiName:store_complete
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (store_complete), line:204
|vpiName:store_complete
|vpiActual:
\_logic_net: (store_complete), line:119, parent:cpu
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (store_complete), line:41, parent:write_back_mux
|vpiName:store_complete
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.store_complete
|vpiNetType:36
|vpiPort:
\_port: (store_forwarding), line:42, parent:write_back_mux
|vpiName:store_forwarding
|vpiDirection:5
|vpiHighConn:
\_ref_obj: (store_forwarding), line:204
|vpiName:store_forwarding
|vpiActual:
\_interface: work@post_issue_forwarding_interface (store_forwarding), file:third_party/cores/taiga/core/taiga.sv, line:120
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_modport: (wb)
|vpiName:wb
|vpiIODecl:
\_io_decl: (data)
|vpiName:data
|vpiDirection:2
|vpiExpr:
\_logic_net: (data), line:260
|vpiName:data
|vpiNetType:36
|vpiRange:
\_range: , line:260
|vpiLeftRange:
\_constant: , line:260
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:260
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (data_valid)
|vpiName:data_valid
|vpiDirection:2
|vpiExpr:
\_logic_net: (data_valid), line:261
|vpiName:data_valid
|vpiNetType:36
|vpiIODecl:
\_io_decl: (id)
|vpiName:id
|vpiDirection:1
|vpiInterface:
\_interface: work@post_issue_forwarding_interface (store_forwarding), file:third_party/cores/taiga/core/taiga.sv, line:204
|vpiDefName:work@post_issue_forwarding_interface
|vpiName:store_forwarding
|vpiModport:
\_modport: (unit)
|vpiName:unit
|vpiIODecl:
\_io_decl: (data)
|vpiName:data
|vpiDirection:1
|vpiExpr:
\_logic_net: (data), line:260
|vpiIODecl:
\_io_decl: (data_valid)
|vpiName:data_valid
|vpiDirection:1
|vpiExpr:
\_logic_net: (data_valid), line:261
|vpiIODecl:
\_io_decl: (id)
|vpiName:id
|vpiDirection:2
|vpiInterface:
\_interface: work@post_issue_forwarding_interface (store_forwarding), file:third_party/cores/taiga/core/taiga.sv, line:204
|vpiModport:
\_modport: (wb)
|vpiPort:
\_port: (store_issued_with_data), line:44, parent:write_back_mux
|vpiName:store_issued_with_data
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (store_issued_with_data), line:204
|vpiName:store_issued_with_data
|vpiActual:
\_logic_net: (store_issued_with_data), line:122, parent:cpu
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (store_issued_with_data), line:44, parent:write_back_mux
|vpiName:store_issued_with_data
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.store_issued_with_data
|vpiNetType:36
|vpiPort:
\_port: (store_data), line:45, parent:write_back_mux
|vpiName:store_data
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (store_data), line:204
|vpiName:store_data
|vpiActual:
\_logic_net: (store_data), line:123, parent:cpu
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (store_data), line:45, parent:write_back_mux
|vpiName:store_data
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.store_data
|vpiNetType:36
|vpiRange:
\_range: , line:45
|vpiLeftRange:
\_constant: , line:45
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:45
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiPort:
\_port: (tr_wb_mux_contention), line:48, parent:write_back_mux
|vpiName:tr_wb_mux_contention
|vpiDirection:2
|vpiHighConn:
\_ref_obj: (tr_wb_mux_contention), line:204
|vpiName:tr_wb_mux_contention
|vpiActual:
\_logic_net: (tr_wb_mux_contention), line:143, parent:cpu
|vpiName:tr_wb_mux_contention
|vpiFullName:work@taiga_wrapper.cpu.tr_wb_mux_contention
|vpiNetType:36
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (tr_wb_mux_contention), line:48, parent:write_back_mux
|vpiName:tr_wb_mux_contention
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.tr_wb_mux_contention
|vpiNetType:36
|vpiModule:
\_module: work@id_tracking (id_fifos), file:third_party/cores/taiga/core/write_back.sv, line:165, parent:write_back_mux
|vpiDefName:work@id_tracking
|vpiName:id_fifos
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.id_fifos
|vpiPort:
\_port: (clk), line:28, parent:id_fifos
|vpiName:clk
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (clk), line:165
|vpiName:clk
|vpiActual:
\_logic_net: (clk), line:27, parent:write_back_mux
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (clk), line:28, parent:id_fifos
|vpiName:clk
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.id_fifos.clk
|vpiNetType:36
|vpiPort:
\_port: (rst), line:29, parent:id_fifos
|vpiName:rst
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (rst), line:165
|vpiName:rst
|vpiActual:
\_logic_net: (rst), line:28, parent:write_back_mux
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (rst), line:29, parent:id_fifos
|vpiName:rst
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.id_fifos.rst
|vpiNetType:36
|vpiPort:
\_port: (issued), line:30, parent:id_fifos
|vpiName:issued
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (issued), line:165
|vpiName:issued
|vpiActual:
\_logic_net: (issued), line:150
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (issued), line:30, parent:id_fifos
|vpiName:issued
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.id_fifos.issued
|vpiNetType:36
|vpiPort:
\_port: (retired), line:31, parent:id_fifos
|vpiName:retired
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (retired), line:165
|vpiName:retired
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (retired), line:31, parent:id_fifos
|vpiName:retired
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.id_fifos.retired
|vpiNetType:36
|vpiPort:
\_port: (id_available), line:32, parent:id_fifos
|vpiName:id_available
|vpiDirection:2
|vpiHighConn:
\_ref_obj: (id_available), line:165
|vpiName:id_available
|vpiActual:
\_logic_net: (id_available), line:147
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (id_available), line:32, parent:id_fifos
|vpiName:id_available
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.id_fifos.id_available
|vpiNetType:36
|vpiPort:
\_port: (oldest_id), line:33, parent:id_fifos
|vpiName:oldest_id
|vpiDirection:2
|vpiTypedef:
\_logic_typespec: (instruction_id_t), line:30
|vpiHighConn:
\_ref_obj: (oldest_id), line:165
|vpiName:oldest_id
|vpiActual:
\_logic_net: (oldest_id), line:38, parent:write_back_mux
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (oldest_id), line:33, parent:id_fifos
|vpiName:oldest_id
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.id_fifos.oldest_id
|vpiPort:
\_port: (next_id), line:34, parent:id_fifos
|vpiName:next_id
|vpiDirection:2
|vpiTypedef:
\_logic_typespec: (instruction_id_t), line:30
|vpiHighConn:
\_ref_obj: (next_id), line:165
|vpiName:next_id
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (next_id), line:34, parent:id_fifos
|vpiName:next_id
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.id_fifos.next_id
|vpiPort:
\_port: (empty), line:35, parent:id_fifos
|vpiName:empty
|vpiDirection:2
|vpiHighConn:
\_ref_obj: (empty), line:165
|vpiName:empty
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (empty), line:35, parent:id_fifos
|vpiName:empty
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.id_fifos.empty
|vpiNetType:36
|vpiNet:
\_logic_net: (clk), line:28, parent:id_fifos
|vpiNet:
\_logic_net: (rst), line:29, parent:id_fifos
|vpiNet:
\_logic_net: (issued), line:30, parent:id_fifos
|vpiNet:
\_logic_net: (retired), line:31, parent:id_fifos
|vpiNet:
\_logic_net: (id_available), line:32, parent:id_fifos
|vpiNet:
\_logic_net: (oldest_id), line:33, parent:id_fifos
|vpiNet:
\_logic_net: (next_id), line:34, parent:id_fifos
|vpiNet:
\_logic_net: (empty), line:35, parent:id_fifos
|vpiNet:
\_logic_net: (inflight_count), line:39, parent:id_fifos
|vpiName:inflight_count
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.id_fifos.inflight_count
|vpiNetType:36
|vpiRange:
\_range: , line:39
|vpiLeftRange:
\_constant: , line:39
|vpiConstType:7
|vpiDecompile:5
|vpiSize:32
|INT:5
|vpiRightRange:
\_constant: , line:39
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiInstance:
\_module: work@write_back (write_back_mux), file:third_party/cores/taiga/core/taiga.sv, line:204, parent:cpu
|vpiParameter:
\_parameter: (ALU_UNIT_WB_ID), line:190
|vpiName:ALU_UNIT_WB_ID
|INT:32
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (BRANCH_PREDICTOR_WAYS), line:159
|vpiName:BRANCH_PREDICTOR_WAYS
|INT:9
|vpiParameter:
\_parameter: (BRANCH_TABLE_ENTRIES), line:160
|vpiName:BRANCH_TABLE_ENTRIES
|INT:4
|vpiParameter:
\_parameter: (BRANCH_UNIT_ID), line:195
|vpiName:BRANCH_UNIT_ID
|INT:8
|vpiParameter:
\_parameter: (BUS_ADDR_H), line:107
|vpiName:BUS_ADDR_H
|INT:1
|vpiParameter:
\_parameter: (BUS_ADDR_L), line:106
|vpiName:BUS_ADDR_L
|INT:0
|vpiParameter:
\_parameter: (BUS_BIT_CHECK), line:108
|vpiName:BUS_BIT_CHECK
|INT:1
|vpiParameter:
\_parameter: (BUS_TYPE), line:89
|vpiName:BUS_TYPE
|INT:5
|vpiParameter:
\_parameter: (COUNTER_W), line:42
|vpiName:COUNTER_W
|INT:33
|vpiParameter:
\_parameter: (CPU_ID), line:38
|vpiName:CPU_ID
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_ADDR_WIDTH), line:113
|vpiName:C_M_AXI_ADDR_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_DATA_WIDTH), line:114
|vpiName:C_M_AXI_DATA_WIDTH
|INT:1
|vpiParameter:
\_parameter: (DCACHE_LINES), line:133
|vpiName:DCACHE_LINES
|INT:-2146435073
|vpiParameter:
\_parameter: (DCACHE_LINE_ADDR_W), line:135
|vpiName:DCACHE_LINE_ADDR_W
|INT:1073741824
|vpiParameter:
\_parameter: (DCACHE_LINE_W), line:136
|vpiName:DCACHE_LINE_W
|INT:1342177279
|vpiParameter:
\_parameter: (DCACHE_SUB_LINE_ADDR_W), line:137
|vpiName:DCACHE_SUB_LINE_ADDR_W
|INT:4
|vpiParameter:
\_parameter: (DCACHE_TAG_W), line:138
|vpiName:DCACHE_TAG_W
|INT:1610612736
|vpiParameter:
\_parameter: (DCACHE_WAYS), line:134
|vpiName:DCACHE_WAYS
|INT:4
|vpiParameter:
\_parameter: (DIV_ALGORITHM), line:67
|vpiName:DIV_ALGORITHM
|INT:0
|vpiParameter:
\_parameter: (DIV_UNIT_WB_ID), line:192
|vpiName:DIV_UNIT_WB_ID
|INT:2
|vpiParameter:
\_parameter: (DTLB_DEPTH), line:152
|vpiName:DTLB_DEPTH
|INT:512
|vpiParameter:
\_parameter: (DTLB_WAYS), line:151
|vpiName:DTLB_WAYS
|INT:32
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (ENABLE_M_MODE), line:34
|vpiName:ENABLE_M_MODE
|INT:1
|vpiParameter:
\_parameter: (ENABLE_S_MODE), line:36
|vpiName:ENABLE_S_MODE
|INT:0
|vpiParameter:
\_parameter: (ENABLE_TRACE_INTERFACE), line:172
|vpiName:ENABLE_TRACE_INTERFACE
|INT:2
|vpiParameter:
\_parameter: (FETCH_BUFFER_DEPTH), line:168
|vpiName:FETCH_BUFFER_DEPTH
|INT:512
|vpiParameter:
\_parameter: (FPGA_VENDOR), line:27
|vpiName:FPGA_VENDOR
|STRING:"xilinx"
|vpiParameter:
\_parameter: (GC_UNIT_ID), line:196
|vpiName:GC_UNIT_ID
|INT:4
|vpiParameter:
\_parameter: (ICACHE_LINES), line:121
|vpiName:ICACHE_LINES
|INT:2
|vpiParameter:
\_parameter: (ICACHE_LINE_ADDR_W), line:123
|vpiName:ICACHE_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_LINE_W), line:124
|vpiName:ICACHE_LINE_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_SUB_LINE_ADDR_W), line:125
|vpiName:ICACHE_SUB_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_TAG_W), line:126
|vpiName:ICACHE_TAG_W
|INT:-2147483648
|vpiParameter:
\_parameter: (ICACHE_WAYS), line:122
|vpiName:ICACHE_WAYS
|INT:1
|vpiParameter:
\_parameter: (ITLB_DEPTH), line:146
|vpiName:ITLB_DEPTH
|INT:32
|vpiParameter:
\_parameter: (ITLB_WAYS), line:145
|vpiName:ITLB_WAYS
|INT:4
|vpiParameter:
\_parameter: (L1_CONNECTIONS), line:177
|vpiName:L1_CONNECTIONS
|INT:9
|vpiParameter:
\_parameter: (L1_DCACHE_ID), line:178
|vpiName:L1_DCACHE_ID
|INT:4
|vpiParameter:
\_parameter: (L1_DMMU_ID), line:179
|vpiName:L1_DMMU_ID
|INT:2
|vpiParameter:
\_parameter: (L1_ICACHE_ID), line:180
|vpiName:L1_ICACHE_ID
|INT:19
|vpiParameter:
\_parameter: (L1_IMMU_ID), line:181
|vpiName:L1_IMMU_ID
|INT:0
|vpiParameter:
\_parameter: (LOG2_MAX_INFLIGHT_COUNT), line:38
|vpiName:LOG2_MAX_INFLIGHT_COUNT
|INT:5
|vpiParameter:
\_parameter: (LS_UNIT_WB_ID), line:191
|vpiName:LS_UNIT_WB_ID
|INT:1
|vpiParameter:
\_parameter: (MAX_INFLIGHT_COUNT), line:167
|vpiName:MAX_INFLIGHT_COUNT
|INT:19
|vpiParameter:
\_parameter: (MEMORY_ADDR_H), line:103
|vpiName:MEMORY_ADDR_H
|INT:12
|vpiParameter:
\_parameter: (MEMORY_ADDR_L), line:102
|vpiName:MEMORY_ADDR_L
|INT:11
|vpiParameter:
\_parameter: (MEMORY_BIT_CHECK), line:104
|vpiName:MEMORY_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (MUL_UNIT_WB_ID), line:193
|vpiName:MUL_UNIT_WB_ID
|INT:512
|vpiParameter:
\_parameter: (NUM_UNITS), line:188
|vpiName:NUM_UNITS
|INT:2
|vpiParameter:
\_parameter: (NUM_WB_UNITS), line:186
|vpiName:NUM_WB_UNITS
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (RAS_DEPTH), line:161
|vpiName:RAS_DEPTH
|INT:2
|vpiParameter:
\_parameter: (RESET_VEC), line:39
|vpiName:RESET_VEC
|INT:-2147483648
|vpiParameter:
\_parameter: (SCRATCH_ADDR_H), line:99
|vpiName:SCRATCH_ADDR_H
|INT:9
|vpiParameter:
\_parameter: (SCRATCH_ADDR_L), line:98
|vpiName:SCRATCH_ADDR_L
|INT:8
|vpiParameter:
\_parameter: (SCRATCH_BIT_CHECK), line:100
|vpiName:SCRATCH_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (USE_AMO), line:70
|vpiName:USE_AMO
|INT:1
|vpiParameter:
\_parameter: (USE_BRANCH_PREDICTOR), line:158
|vpiName:USE_BRANCH_PREDICTOR
|INT:2
|vpiParameter:
\_parameter: (USE_BUS), line:88
|vpiName:USE_BUS
|INT:4
|vpiParameter:
\_parameter: (USE_DCACHE), line:92
|vpiName:USE_DCACHE
|INT:6
|vpiParameter:
\_parameter: (USE_DIV), line:49
|vpiName:USE_DIV
|INT:1
|vpiParameter:
\_parameter: (USE_DTAG_INVALIDATIONS), line:140
|vpiName:USE_DTAG_INVALIDATIONS
|INT:1879048191
|vpiParameter:
\_parameter: (USE_D_SCRATCH_MEM), line:79
|vpiName:USE_D_SCRATCH_MEM
|INT:3
|vpiParameter:
\_parameter: (USE_ICACHE), line:93
|vpiName:USE_ICACHE
|INT:7
|vpiParameter:
\_parameter: (USE_I_SCRATCH_MEM), line:78
|vpiName:USE_I_SCRATCH_MEM
|INT:2
|vpiParameter:
\_parameter: (USE_MUL), line:48
|vpiName:USE_MUL
|INT:1
|vpiParameter:
\_parameter: (WB_UNITS_WIDTH), line:187
|vpiName:WB_UNITS_WIDTH
|INT:32
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiGenScopeArray:
\_gen_scope_array: (interface_to_array_g[0]), line:85, parent:write_back_mux
|vpiName:interface_to_array_g[0]
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.interface_to_array_g[0]
|vpiGenScope:
\_gen_scope: , parent:interface_to_array_g[0]
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.interface_to_array_g[0]
|vpiContAssign:
\_cont_assign: , line:86
|vpiRhs:
\_bit_select: (unit_wb.id), line:86
|vpiName:unit_wb.id
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.interface_to_array_g[0].unit_wb.id
|vpiIndex:
\_ref_obj: (i), line:86
|vpiName:i
|vpiLhs:
\_bit_select: (unit_instruction_id), line:86
|vpiName:unit_instruction_id
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.interface_to_array_g[0].unit_instruction_id
|vpiIndex:
\_ref_obj: (i), line:86
|vpiName:i
|vpiContAssign:
\_cont_assign: , line:87
|vpiRhs:
\_bit_select: (unit_wb.done), line:87
|vpiName:unit_wb.done
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.interface_to_array_g[0].unit_wb.done
|vpiIndex:
\_ref_obj: (i), line:87
|vpiName:i
|vpiLhs:
\_bit_select: (unit_done), line:87
|vpiName:unit_done
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.interface_to_array_g[0].unit_done
|vpiIndex:
\_ref_obj: (i), line:87
|vpiName:i
|vpiContAssign:
\_cont_assign: , line:88
|vpiRhs:
\_bit_select: (unit_wb.rd), line:88
|vpiName:unit_wb.rd
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.interface_to_array_g[0].unit_wb.rd
|vpiIndex:
\_ref_obj: (i), line:88
|vpiName:i
|vpiLhs:
\_bit_select: (unit_rd), line:88
|vpiName:unit_rd
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.interface_to_array_g[0].unit_rd
|vpiIndex:
\_ref_obj: (i), line:88
|vpiName:i
|vpiParameter:
\_parameter: (ALU_UNIT_WB_ID), line:190
|vpiName:ALU_UNIT_WB_ID
|INT:32
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (BRANCH_PREDICTOR_WAYS), line:159
|vpiName:BRANCH_PREDICTOR_WAYS
|INT:9
|vpiParameter:
\_parameter: (BRANCH_TABLE_ENTRIES), line:160
|vpiName:BRANCH_TABLE_ENTRIES
|INT:4
|vpiParameter:
\_parameter: (BRANCH_UNIT_ID), line:195
|vpiName:BRANCH_UNIT_ID
|INT:8
|vpiParameter:
\_parameter: (BUS_ADDR_H), line:107
|vpiName:BUS_ADDR_H
|INT:1
|vpiParameter:
\_parameter: (BUS_ADDR_L), line:106
|vpiName:BUS_ADDR_L
|INT:0
|vpiParameter:
\_parameter: (BUS_BIT_CHECK), line:108
|vpiName:BUS_BIT_CHECK
|INT:1
|vpiParameter:
\_parameter: (BUS_TYPE), line:89
|vpiName:BUS_TYPE
|INT:5
|vpiParameter:
\_parameter: (COUNTER_W), line:42
|vpiName:COUNTER_W
|INT:33
|vpiParameter:
\_parameter: (CPU_ID), line:38
|vpiName:CPU_ID
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_ADDR_WIDTH), line:113
|vpiName:C_M_AXI_ADDR_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_DATA_WIDTH), line:114
|vpiName:C_M_AXI_DATA_WIDTH
|INT:1
|vpiParameter:
\_parameter: (DCACHE_LINES), line:133
|vpiName:DCACHE_LINES
|INT:-2146435073
|vpiParameter:
\_parameter: (DCACHE_LINE_ADDR_W), line:135
|vpiName:DCACHE_LINE_ADDR_W
|INT:1073741824
|vpiParameter:
\_parameter: (DCACHE_LINE_W), line:136
|vpiName:DCACHE_LINE_W
|INT:1342177279
|vpiParameter:
\_parameter: (DCACHE_SUB_LINE_ADDR_W), line:137
|vpiName:DCACHE_SUB_LINE_ADDR_W
|INT:4
|vpiParameter:
\_parameter: (DCACHE_TAG_W), line:138
|vpiName:DCACHE_TAG_W
|INT:1610612736
|vpiParameter:
\_parameter: (DCACHE_WAYS), line:134
|vpiName:DCACHE_WAYS
|INT:4
|vpiParameter:
\_parameter: (DIV_ALGORITHM), line:67
|vpiName:DIV_ALGORITHM
|INT:0
|vpiParameter:
\_parameter: (DIV_UNIT_WB_ID), line:192
|vpiName:DIV_UNIT_WB_ID
|INT:2
|vpiParameter:
\_parameter: (DTLB_DEPTH), line:152
|vpiName:DTLB_DEPTH
|INT:512
|vpiParameter:
\_parameter: (DTLB_WAYS), line:151
|vpiName:DTLB_WAYS
|INT:32
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (ENABLE_M_MODE), line:34
|vpiName:ENABLE_M_MODE
|INT:1
|vpiParameter:
\_parameter: (ENABLE_S_MODE), line:36
|vpiName:ENABLE_S_MODE
|INT:0
|vpiParameter:
\_parameter: (ENABLE_TRACE_INTERFACE), line:172
|vpiName:ENABLE_TRACE_INTERFACE
|INT:2
|vpiParameter:
\_parameter: (FETCH_BUFFER_DEPTH), line:168
|vpiName:FETCH_BUFFER_DEPTH
|INT:512
|vpiParameter:
\_parameter: (FPGA_VENDOR), line:27
|vpiName:FPGA_VENDOR
|STRING:"xilinx"
|vpiParameter:
\_parameter: (GC_UNIT_ID), line:196
|vpiName:GC_UNIT_ID
|INT:4
|vpiParameter:
\_parameter: (ICACHE_LINES), line:121
|vpiName:ICACHE_LINES
|INT:2
|vpiParameter:
\_parameter: (ICACHE_LINE_ADDR_W), line:123
|vpiName:ICACHE_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_LINE_W), line:124
|vpiName:ICACHE_LINE_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_SUB_LINE_ADDR_W), line:125
|vpiName:ICACHE_SUB_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_TAG_W), line:126
|vpiName:ICACHE_TAG_W
|INT:-2147483648
|vpiParameter:
\_parameter: (ICACHE_WAYS), line:122
|vpiName:ICACHE_WAYS
|INT:1
|vpiParameter:
\_parameter: (ITLB_DEPTH), line:146
|vpiName:ITLB_DEPTH
|INT:32
|vpiParameter:
\_parameter: (ITLB_WAYS), line:145
|vpiName:ITLB_WAYS
|INT:4
|vpiParameter:
\_parameter: (L1_CONNECTIONS), line:177
|vpiName:L1_CONNECTIONS
|INT:9
|vpiParameter:
\_parameter: (L1_DCACHE_ID), line:178
|vpiName:L1_DCACHE_ID
|INT:4
|vpiParameter:
\_parameter: (L1_DMMU_ID), line:179
|vpiName:L1_DMMU_ID
|INT:2
|vpiParameter:
\_parameter: (L1_ICACHE_ID), line:180
|vpiName:L1_ICACHE_ID
|INT:19
|vpiParameter:
\_parameter: (L1_IMMU_ID), line:181
|vpiName:L1_IMMU_ID
|INT:0
|vpiParameter:
\_parameter: (LS_UNIT_WB_ID), line:191
|vpiName:LS_UNIT_WB_ID
|INT:1
|vpiParameter:
\_parameter: (MAX_INFLIGHT_COUNT), line:167
|vpiName:MAX_INFLIGHT_COUNT
|INT:19
|vpiParameter:
\_parameter: (MEMORY_ADDR_H), line:103
|vpiName:MEMORY_ADDR_H
|INT:12
|vpiParameter:
\_parameter: (MEMORY_ADDR_L), line:102
|vpiName:MEMORY_ADDR_L
|INT:11
|vpiParameter:
\_parameter: (MEMORY_BIT_CHECK), line:104
|vpiName:MEMORY_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (MUL_UNIT_WB_ID), line:193
|vpiName:MUL_UNIT_WB_ID
|INT:512
|vpiParameter:
\_parameter: (NUM_UNITS), line:188
|vpiName:NUM_UNITS
|INT:2
|vpiParameter:
\_parameter: (NUM_WB_UNITS), line:186
|vpiName:NUM_WB_UNITS
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (RAS_DEPTH), line:161
|vpiName:RAS_DEPTH
|INT:2
|vpiParameter:
\_parameter: (RESET_VEC), line:39
|vpiName:RESET_VEC
|INT:-2147483648
|vpiParameter:
\_parameter: (SCRATCH_ADDR_H), line:99
|vpiName:SCRATCH_ADDR_H
|INT:9
|vpiParameter:
\_parameter: (SCRATCH_ADDR_L), line:98
|vpiName:SCRATCH_ADDR_L
|INT:8
|vpiParameter:
\_parameter: (SCRATCH_BIT_CHECK), line:100
|vpiName:SCRATCH_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (USE_AMO), line:70
|vpiName:USE_AMO
|INT:1
|vpiParameter:
\_parameter: (USE_BRANCH_PREDICTOR), line:158
|vpiName:USE_BRANCH_PREDICTOR
|INT:2
|vpiParameter:
\_parameter: (USE_BUS), line:88
|vpiName:USE_BUS
|INT:4
|vpiParameter:
\_parameter: (USE_DCACHE), line:92
|vpiName:USE_DCACHE
|INT:6
|vpiParameter:
\_parameter: (USE_DIV), line:49
|vpiName:USE_DIV
|INT:1
|vpiParameter:
\_parameter: (USE_DTAG_INVALIDATIONS), line:140
|vpiName:USE_DTAG_INVALIDATIONS
|INT:1879048191
|vpiParameter:
\_parameter: (USE_D_SCRATCH_MEM), line:79
|vpiName:USE_D_SCRATCH_MEM
|INT:3
|vpiParameter:
\_parameter: (USE_ICACHE), line:93
|vpiName:USE_ICACHE
|INT:7
|vpiParameter:
\_parameter: (USE_I_SCRATCH_MEM), line:78
|vpiName:USE_I_SCRATCH_MEM
|INT:2
|vpiParameter:
\_parameter: (USE_MUL), line:48
|vpiName:USE_MUL
|INT:1
|vpiParameter:
\_parameter: (WB_UNITS_WIDTH), line:187
|vpiName:WB_UNITS_WIDTH
|INT:32
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiParameter:
\_parameter: (i), line:85
|vpiName:i
|INT:0
|vpiGenScopeArray:
\_gen_scope_array: (interface_to_array_g[1]), line:85, parent:write_back_mux
|vpiName:interface_to_array_g[1]
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.interface_to_array_g[1]
|vpiGenScope:
\_gen_scope: , parent:interface_to_array_g[1]
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.interface_to_array_g[1]
|vpiContAssign:
\_cont_assign: , line:86
|vpiRhs:
\_bit_select: (unit_wb.id), line:86
|vpiName:unit_wb.id
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.interface_to_array_g[1].unit_wb.id
|vpiIndex:
\_ref_obj: (i), line:86
|vpiName:i
|vpiLhs:
\_bit_select: (unit_instruction_id), line:86
|vpiName:unit_instruction_id
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.interface_to_array_g[1].unit_instruction_id
|vpiIndex:
\_ref_obj: (i), line:86
|vpiName:i
|vpiContAssign:
\_cont_assign: , line:87
|vpiRhs:
\_bit_select: (unit_wb.done), line:87
|vpiName:unit_wb.done
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.interface_to_array_g[1].unit_wb.done
|vpiIndex:
\_ref_obj: (i), line:87
|vpiName:i
|vpiLhs:
\_bit_select: (unit_done), line:87
|vpiName:unit_done
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.interface_to_array_g[1].unit_done
|vpiIndex:
\_ref_obj: (i), line:87
|vpiName:i
|vpiContAssign:
\_cont_assign: , line:88
|vpiRhs:
\_bit_select: (unit_wb.rd), line:88
|vpiName:unit_wb.rd
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.interface_to_array_g[1].unit_wb.rd
|vpiIndex:
\_ref_obj: (i), line:88
|vpiName:i
|vpiLhs:
\_bit_select: (unit_rd), line:88
|vpiName:unit_rd
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.interface_to_array_g[1].unit_rd
|vpiIndex:
\_ref_obj: (i), line:88
|vpiName:i
|vpiParameter:
\_parameter: (ALU_UNIT_WB_ID), line:190
|vpiName:ALU_UNIT_WB_ID
|INT:32
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (BRANCH_PREDICTOR_WAYS), line:159
|vpiName:BRANCH_PREDICTOR_WAYS
|INT:9
|vpiParameter:
\_parameter: (BRANCH_TABLE_ENTRIES), line:160
|vpiName:BRANCH_TABLE_ENTRIES
|INT:4
|vpiParameter:
\_parameter: (BRANCH_UNIT_ID), line:195
|vpiName:BRANCH_UNIT_ID
|INT:8
|vpiParameter:
\_parameter: (BUS_ADDR_H), line:107
|vpiName:BUS_ADDR_H
|INT:1
|vpiParameter:
\_parameter: (BUS_ADDR_L), line:106
|vpiName:BUS_ADDR_L
|INT:0
|vpiParameter:
\_parameter: (BUS_BIT_CHECK), line:108
|vpiName:BUS_BIT_CHECK
|INT:1
|vpiParameter:
\_parameter: (BUS_TYPE), line:89
|vpiName:BUS_TYPE
|INT:5
|vpiParameter:
\_parameter: (COUNTER_W), line:42
|vpiName:COUNTER_W
|INT:33
|vpiParameter:
\_parameter: (CPU_ID), line:38
|vpiName:CPU_ID
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_ADDR_WIDTH), line:113
|vpiName:C_M_AXI_ADDR_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_DATA_WIDTH), line:114
|vpiName:C_M_AXI_DATA_WIDTH
|INT:1
|vpiParameter:
\_parameter: (DCACHE_LINES), line:133
|vpiName:DCACHE_LINES
|INT:-2146435073
|vpiParameter:
\_parameter: (DCACHE_LINE_ADDR_W), line:135
|vpiName:DCACHE_LINE_ADDR_W
|INT:1073741824
|vpiParameter:
\_parameter: (DCACHE_LINE_W), line:136
|vpiName:DCACHE_LINE_W
|INT:1342177279
|vpiParameter:
\_parameter: (DCACHE_SUB_LINE_ADDR_W), line:137
|vpiName:DCACHE_SUB_LINE_ADDR_W
|INT:4
|vpiParameter:
\_parameter: (DCACHE_TAG_W), line:138
|vpiName:DCACHE_TAG_W
|INT:1610612736
|vpiParameter:
\_parameter: (DCACHE_WAYS), line:134
|vpiName:DCACHE_WAYS
|INT:4
|vpiParameter:
\_parameter: (DIV_ALGORITHM), line:67
|vpiName:DIV_ALGORITHM
|INT:0
|vpiParameter:
\_parameter: (DIV_UNIT_WB_ID), line:192
|vpiName:DIV_UNIT_WB_ID
|INT:2
|vpiParameter:
\_parameter: (DTLB_DEPTH), line:152
|vpiName:DTLB_DEPTH
|INT:512
|vpiParameter:
\_parameter: (DTLB_WAYS), line:151
|vpiName:DTLB_WAYS
|INT:32
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (ENABLE_M_MODE), line:34
|vpiName:ENABLE_M_MODE
|INT:1
|vpiParameter:
\_parameter: (ENABLE_S_MODE), line:36
|vpiName:ENABLE_S_MODE
|INT:0
|vpiParameter:
\_parameter: (ENABLE_TRACE_INTERFACE), line:172
|vpiName:ENABLE_TRACE_INTERFACE
|INT:2
|vpiParameter:
\_parameter: (FETCH_BUFFER_DEPTH), line:168
|vpiName:FETCH_BUFFER_DEPTH
|INT:512
|vpiParameter:
\_parameter: (FPGA_VENDOR), line:27
|vpiName:FPGA_VENDOR
|STRING:"xilinx"
|vpiParameter:
\_parameter: (GC_UNIT_ID), line:196
|vpiName:GC_UNIT_ID
|INT:4
|vpiParameter:
\_parameter: (ICACHE_LINES), line:121
|vpiName:ICACHE_LINES
|INT:2
|vpiParameter:
\_parameter: (ICACHE_LINE_ADDR_W), line:123
|vpiName:ICACHE_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_LINE_W), line:124
|vpiName:ICACHE_LINE_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_SUB_LINE_ADDR_W), line:125
|vpiName:ICACHE_SUB_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_TAG_W), line:126
|vpiName:ICACHE_TAG_W
|INT:-2147483648
|vpiParameter:
\_parameter: (ICACHE_WAYS), line:122
|vpiName:ICACHE_WAYS
|INT:1
|vpiParameter:
\_parameter: (ITLB_DEPTH), line:146
|vpiName:ITLB_DEPTH
|INT:32
|vpiParameter:
\_parameter: (ITLB_WAYS), line:145
|vpiName:ITLB_WAYS
|INT:4
|vpiParameter:
\_parameter: (L1_CONNECTIONS), line:177
|vpiName:L1_CONNECTIONS
|INT:9
|vpiParameter:
\_parameter: (L1_DCACHE_ID), line:178
|vpiName:L1_DCACHE_ID
|INT:4
|vpiParameter:
\_parameter: (L1_DMMU_ID), line:179
|vpiName:L1_DMMU_ID
|INT:2
|vpiParameter:
\_parameter: (L1_ICACHE_ID), line:180
|vpiName:L1_ICACHE_ID
|INT:19
|vpiParameter:
\_parameter: (L1_IMMU_ID), line:181
|vpiName:L1_IMMU_ID
|INT:0
|vpiParameter:
\_parameter: (LS_UNIT_WB_ID), line:191
|vpiName:LS_UNIT_WB_ID
|INT:1
|vpiParameter:
\_parameter: (MAX_INFLIGHT_COUNT), line:167
|vpiName:MAX_INFLIGHT_COUNT
|INT:19
|vpiParameter:
\_parameter: (MEMORY_ADDR_H), line:103
|vpiName:MEMORY_ADDR_H
|INT:12
|vpiParameter:
\_parameter: (MEMORY_ADDR_L), line:102
|vpiName:MEMORY_ADDR_L
|INT:11
|vpiParameter:
\_parameter: (MEMORY_BIT_CHECK), line:104
|vpiName:MEMORY_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (MUL_UNIT_WB_ID), line:193
|vpiName:MUL_UNIT_WB_ID
|INT:512
|vpiParameter:
\_parameter: (NUM_UNITS), line:188
|vpiName:NUM_UNITS
|INT:2
|vpiParameter:
\_parameter: (NUM_WB_UNITS), line:186
|vpiName:NUM_WB_UNITS
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (RAS_DEPTH), line:161
|vpiName:RAS_DEPTH
|INT:2
|vpiParameter:
\_parameter: (RESET_VEC), line:39
|vpiName:RESET_VEC
|INT:-2147483648
|vpiParameter:
\_parameter: (SCRATCH_ADDR_H), line:99
|vpiName:SCRATCH_ADDR_H
|INT:9
|vpiParameter:
\_parameter: (SCRATCH_ADDR_L), line:98
|vpiName:SCRATCH_ADDR_L
|INT:8
|vpiParameter:
\_parameter: (SCRATCH_BIT_CHECK), line:100
|vpiName:SCRATCH_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (USE_AMO), line:70
|vpiName:USE_AMO
|INT:1
|vpiParameter:
\_parameter: (USE_BRANCH_PREDICTOR), line:158
|vpiName:USE_BRANCH_PREDICTOR
|INT:2
|vpiParameter:
\_parameter: (USE_BUS), line:88
|vpiName:USE_BUS
|INT:4
|vpiParameter:
\_parameter: (USE_DCACHE), line:92
|vpiName:USE_DCACHE
|INT:6
|vpiParameter:
\_parameter: (USE_DIV), line:49
|vpiName:USE_DIV
|INT:1
|vpiParameter:
\_parameter: (USE_DTAG_INVALIDATIONS), line:140
|vpiName:USE_DTAG_INVALIDATIONS
|INT:1879048191
|vpiParameter:
\_parameter: (USE_D_SCRATCH_MEM), line:79
|vpiName:USE_D_SCRATCH_MEM
|INT:3
|vpiParameter:
\_parameter: (USE_ICACHE), line:93
|vpiName:USE_ICACHE
|INT:7
|vpiParameter:
\_parameter: (USE_I_SCRATCH_MEM), line:78
|vpiName:USE_I_SCRATCH_MEM
|INT:2
|vpiParameter:
\_parameter: (USE_MUL), line:48
|vpiName:USE_MUL
|INT:1
|vpiParameter:
\_parameter: (WB_UNITS_WIDTH), line:187
|vpiName:WB_UNITS_WIDTH
|INT:32
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiParameter:
\_parameter: (i), line:85
|vpiName:i
|INT:1
|vpiGenScopeArray:
\_gen_scope_array: (genblk1[2]), line:90, parent:write_back_mux
|vpiName:genblk1[2]
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk1[2]
|vpiGenScope:
\_gen_scope: , parent:genblk1[2]
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk1[2]
|vpiContAssign:
\_cont_assign: , line:91
|vpiRhs:
\_ref_obj: (store_data), line:91
|vpiName:store_data
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk1[2].store_data
|vpiLhs:
\_bit_select: (unit_rd), line:91
|vpiName:unit_rd
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk1[2].unit_rd
|vpiIndex:
\_ref_obj: (i), line:91
|vpiName:i
|vpiParameter:
\_parameter: (ALU_UNIT_WB_ID), line:190
|vpiName:ALU_UNIT_WB_ID
|INT:32
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (BRANCH_PREDICTOR_WAYS), line:159
|vpiName:BRANCH_PREDICTOR_WAYS
|INT:9
|vpiParameter:
\_parameter: (BRANCH_TABLE_ENTRIES), line:160
|vpiName:BRANCH_TABLE_ENTRIES
|INT:4
|vpiParameter:
\_parameter: (BRANCH_UNIT_ID), line:195
|vpiName:BRANCH_UNIT_ID
|INT:8
|vpiParameter:
\_parameter: (BUS_ADDR_H), line:107
|vpiName:BUS_ADDR_H
|INT:1
|vpiParameter:
\_parameter: (BUS_ADDR_L), line:106
|vpiName:BUS_ADDR_L
|INT:0
|vpiParameter:
\_parameter: (BUS_BIT_CHECK), line:108
|vpiName:BUS_BIT_CHECK
|INT:1
|vpiParameter:
\_parameter: (BUS_TYPE), line:89
|vpiName:BUS_TYPE
|INT:5
|vpiParameter:
\_parameter: (COUNTER_W), line:42
|vpiName:COUNTER_W
|INT:33
|vpiParameter:
\_parameter: (CPU_ID), line:38
|vpiName:CPU_ID
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_ADDR_WIDTH), line:113
|vpiName:C_M_AXI_ADDR_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_DATA_WIDTH), line:114
|vpiName:C_M_AXI_DATA_WIDTH
|INT:1
|vpiParameter:
\_parameter: (DCACHE_LINES), line:133
|vpiName:DCACHE_LINES
|INT:-2146435073
|vpiParameter:
\_parameter: (DCACHE_LINE_ADDR_W), line:135
|vpiName:DCACHE_LINE_ADDR_W
|INT:1073741824
|vpiParameter:
\_parameter: (DCACHE_LINE_W), line:136
|vpiName:DCACHE_LINE_W
|INT:1342177279
|vpiParameter:
\_parameter: (DCACHE_SUB_LINE_ADDR_W), line:137
|vpiName:DCACHE_SUB_LINE_ADDR_W
|INT:4
|vpiParameter:
\_parameter: (DCACHE_TAG_W), line:138
|vpiName:DCACHE_TAG_W
|INT:1610612736
|vpiParameter:
\_parameter: (DCACHE_WAYS), line:134
|vpiName:DCACHE_WAYS
|INT:4
|vpiParameter:
\_parameter: (DIV_ALGORITHM), line:67
|vpiName:DIV_ALGORITHM
|INT:0
|vpiParameter:
\_parameter: (DIV_UNIT_WB_ID), line:192
|vpiName:DIV_UNIT_WB_ID
|INT:2
|vpiParameter:
\_parameter: (DTLB_DEPTH), line:152
|vpiName:DTLB_DEPTH
|INT:512
|vpiParameter:
\_parameter: (DTLB_WAYS), line:151
|vpiName:DTLB_WAYS
|INT:32
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (ENABLE_M_MODE), line:34
|vpiName:ENABLE_M_MODE
|INT:1
|vpiParameter:
\_parameter: (ENABLE_S_MODE), line:36
|vpiName:ENABLE_S_MODE
|INT:0
|vpiParameter:
\_parameter: (ENABLE_TRACE_INTERFACE), line:172
|vpiName:ENABLE_TRACE_INTERFACE
|INT:2
|vpiParameter:
\_parameter: (FETCH_BUFFER_DEPTH), line:168
|vpiName:FETCH_BUFFER_DEPTH
|INT:512
|vpiParameter:
\_parameter: (FPGA_VENDOR), line:27
|vpiName:FPGA_VENDOR
|STRING:"xilinx"
|vpiParameter:
\_parameter: (GC_UNIT_ID), line:196
|vpiName:GC_UNIT_ID
|INT:4
|vpiParameter:
\_parameter: (ICACHE_LINES), line:121
|vpiName:ICACHE_LINES
|INT:2
|vpiParameter:
\_parameter: (ICACHE_LINE_ADDR_W), line:123
|vpiName:ICACHE_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_LINE_W), line:124
|vpiName:ICACHE_LINE_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_SUB_LINE_ADDR_W), line:125
|vpiName:ICACHE_SUB_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_TAG_W), line:126
|vpiName:ICACHE_TAG_W
|INT:-2147483648
|vpiParameter:
\_parameter: (ICACHE_WAYS), line:122
|vpiName:ICACHE_WAYS
|INT:1
|vpiParameter:
\_parameter: (ITLB_DEPTH), line:146
|vpiName:ITLB_DEPTH
|INT:32
|vpiParameter:
\_parameter: (ITLB_WAYS), line:145
|vpiName:ITLB_WAYS
|INT:4
|vpiParameter:
\_parameter: (L1_CONNECTIONS), line:177
|vpiName:L1_CONNECTIONS
|INT:9
|vpiParameter:
\_parameter: (L1_DCACHE_ID), line:178
|vpiName:L1_DCACHE_ID
|INT:4
|vpiParameter:
\_parameter: (L1_DMMU_ID), line:179
|vpiName:L1_DMMU_ID
|INT:2
|vpiParameter:
\_parameter: (L1_ICACHE_ID), line:180
|vpiName:L1_ICACHE_ID
|INT:19
|vpiParameter:
\_parameter: (L1_IMMU_ID), line:181
|vpiName:L1_IMMU_ID
|INT:0
|vpiParameter:
\_parameter: (LS_UNIT_WB_ID), line:191
|vpiName:LS_UNIT_WB_ID
|INT:1
|vpiParameter:
\_parameter: (MAX_INFLIGHT_COUNT), line:167
|vpiName:MAX_INFLIGHT_COUNT
|INT:19
|vpiParameter:
\_parameter: (MEMORY_ADDR_H), line:103
|vpiName:MEMORY_ADDR_H
|INT:12
|vpiParameter:
\_parameter: (MEMORY_ADDR_L), line:102
|vpiName:MEMORY_ADDR_L
|INT:11
|vpiParameter:
\_parameter: (MEMORY_BIT_CHECK), line:104
|vpiName:MEMORY_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (MUL_UNIT_WB_ID), line:193
|vpiName:MUL_UNIT_WB_ID
|INT:512
|vpiParameter:
\_parameter: (NUM_UNITS), line:188
|vpiName:NUM_UNITS
|INT:2
|vpiParameter:
\_parameter: (NUM_WB_UNITS), line:186
|vpiName:NUM_WB_UNITS
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (RAS_DEPTH), line:161
|vpiName:RAS_DEPTH
|INT:2
|vpiParameter:
\_parameter: (RESET_VEC), line:39
|vpiName:RESET_VEC
|INT:-2147483648
|vpiParameter:
\_parameter: (SCRATCH_ADDR_H), line:99
|vpiName:SCRATCH_ADDR_H
|INT:9
|vpiParameter:
\_parameter: (SCRATCH_ADDR_L), line:98
|vpiName:SCRATCH_ADDR_L
|INT:8
|vpiParameter:
\_parameter: (SCRATCH_BIT_CHECK), line:100
|vpiName:SCRATCH_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (USE_AMO), line:70
|vpiName:USE_AMO
|INT:1
|vpiParameter:
\_parameter: (USE_BRANCH_PREDICTOR), line:158
|vpiName:USE_BRANCH_PREDICTOR
|INT:2
|vpiParameter:
\_parameter: (USE_BUS), line:88
|vpiName:USE_BUS
|INT:4
|vpiParameter:
\_parameter: (USE_DCACHE), line:92
|vpiName:USE_DCACHE
|INT:6
|vpiParameter:
\_parameter: (USE_DIV), line:49
|vpiName:USE_DIV
|INT:1
|vpiParameter:
\_parameter: (USE_DTAG_INVALIDATIONS), line:140
|vpiName:USE_DTAG_INVALIDATIONS
|INT:1879048191
|vpiParameter:
\_parameter: (USE_D_SCRATCH_MEM), line:79
|vpiName:USE_D_SCRATCH_MEM
|INT:3
|vpiParameter:
\_parameter: (USE_ICACHE), line:93
|vpiName:USE_ICACHE
|INT:7
|vpiParameter:
\_parameter: (USE_I_SCRATCH_MEM), line:78
|vpiName:USE_I_SCRATCH_MEM
|INT:2
|vpiParameter:
\_parameter: (USE_MUL), line:48
|vpiName:USE_MUL
|INT:1
|vpiParameter:
\_parameter: (WB_UNITS_WIDTH), line:187
|vpiName:WB_UNITS_WIDTH
|INT:32
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiParameter:
\_parameter: (i), line:90
|vpiName:i
|INT:2
|vpiGenScopeArray:
\_gen_scope_array: (genblk1[3]), line:90, parent:write_back_mux
|vpiName:genblk1[3]
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk1[3]
|vpiGenScope:
\_gen_scope: , parent:genblk1[3]
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk1[3]
|vpiContAssign:
\_cont_assign: , line:91
|vpiRhs:
\_ref_obj: (store_data), line:91
|vpiName:store_data
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk1[3].store_data
|vpiLhs:
\_bit_select: (unit_rd), line:91
|vpiName:unit_rd
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk1[3].unit_rd
|vpiIndex:
\_ref_obj: (i), line:91
|vpiName:i
|vpiParameter:
\_parameter: (ALU_UNIT_WB_ID), line:190
|vpiName:ALU_UNIT_WB_ID
|INT:32
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (BRANCH_PREDICTOR_WAYS), line:159
|vpiName:BRANCH_PREDICTOR_WAYS
|INT:9
|vpiParameter:
\_parameter: (BRANCH_TABLE_ENTRIES), line:160
|vpiName:BRANCH_TABLE_ENTRIES
|INT:4
|vpiParameter:
\_parameter: (BRANCH_UNIT_ID), line:195
|vpiName:BRANCH_UNIT_ID
|INT:8
|vpiParameter:
\_parameter: (BUS_ADDR_H), line:107
|vpiName:BUS_ADDR_H
|INT:1
|vpiParameter:
\_parameter: (BUS_ADDR_L), line:106
|vpiName:BUS_ADDR_L
|INT:0
|vpiParameter:
\_parameter: (BUS_BIT_CHECK), line:108
|vpiName:BUS_BIT_CHECK
|INT:1
|vpiParameter:
\_parameter: (BUS_TYPE), line:89
|vpiName:BUS_TYPE
|INT:5
|vpiParameter:
\_parameter: (COUNTER_W), line:42
|vpiName:COUNTER_W
|INT:33
|vpiParameter:
\_parameter: (CPU_ID), line:38
|vpiName:CPU_ID
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_ADDR_WIDTH), line:113
|vpiName:C_M_AXI_ADDR_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_DATA_WIDTH), line:114
|vpiName:C_M_AXI_DATA_WIDTH
|INT:1
|vpiParameter:
\_parameter: (DCACHE_LINES), line:133
|vpiName:DCACHE_LINES
|INT:-2146435073
|vpiParameter:
\_parameter: (DCACHE_LINE_ADDR_W), line:135
|vpiName:DCACHE_LINE_ADDR_W
|INT:1073741824
|vpiParameter:
\_parameter: (DCACHE_LINE_W), line:136
|vpiName:DCACHE_LINE_W
|INT:1342177279
|vpiParameter:
\_parameter: (DCACHE_SUB_LINE_ADDR_W), line:137
|vpiName:DCACHE_SUB_LINE_ADDR_W
|INT:4
|vpiParameter:
\_parameter: (DCACHE_TAG_W), line:138
|vpiName:DCACHE_TAG_W
|INT:1610612736
|vpiParameter:
\_parameter: (DCACHE_WAYS), line:134
|vpiName:DCACHE_WAYS
|INT:4
|vpiParameter:
\_parameter: (DIV_ALGORITHM), line:67
|vpiName:DIV_ALGORITHM
|INT:0
|vpiParameter:
\_parameter: (DIV_UNIT_WB_ID), line:192
|vpiName:DIV_UNIT_WB_ID
|INT:2
|vpiParameter:
\_parameter: (DTLB_DEPTH), line:152
|vpiName:DTLB_DEPTH
|INT:512
|vpiParameter:
\_parameter: (DTLB_WAYS), line:151
|vpiName:DTLB_WAYS
|INT:32
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (ENABLE_M_MODE), line:34
|vpiName:ENABLE_M_MODE
|INT:1
|vpiParameter:
\_parameter: (ENABLE_S_MODE), line:36
|vpiName:ENABLE_S_MODE
|INT:0
|vpiParameter:
\_parameter: (ENABLE_TRACE_INTERFACE), line:172
|vpiName:ENABLE_TRACE_INTERFACE
|INT:2
|vpiParameter:
\_parameter: (FETCH_BUFFER_DEPTH), line:168
|vpiName:FETCH_BUFFER_DEPTH
|INT:512
|vpiParameter:
\_parameter: (FPGA_VENDOR), line:27
|vpiName:FPGA_VENDOR
|STRING:"xilinx"
|vpiParameter:
\_parameter: (GC_UNIT_ID), line:196
|vpiName:GC_UNIT_ID
|INT:4
|vpiParameter:
\_parameter: (ICACHE_LINES), line:121
|vpiName:ICACHE_LINES
|INT:2
|vpiParameter:
\_parameter: (ICACHE_LINE_ADDR_W), line:123
|vpiName:ICACHE_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_LINE_W), line:124
|vpiName:ICACHE_LINE_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_SUB_LINE_ADDR_W), line:125
|vpiName:ICACHE_SUB_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_TAG_W), line:126
|vpiName:ICACHE_TAG_W
|INT:-2147483648
|vpiParameter:
\_parameter: (ICACHE_WAYS), line:122
|vpiName:ICACHE_WAYS
|INT:1
|vpiParameter:
\_parameter: (ITLB_DEPTH), line:146
|vpiName:ITLB_DEPTH
|INT:32
|vpiParameter:
\_parameter: (ITLB_WAYS), line:145
|vpiName:ITLB_WAYS
|INT:4
|vpiParameter:
\_parameter: (L1_CONNECTIONS), line:177
|vpiName:L1_CONNECTIONS
|INT:9
|vpiParameter:
\_parameter: (L1_DCACHE_ID), line:178
|vpiName:L1_DCACHE_ID
|INT:4
|vpiParameter:
\_parameter: (L1_DMMU_ID), line:179
|vpiName:L1_DMMU_ID
|INT:2
|vpiParameter:
\_parameter: (L1_ICACHE_ID), line:180
|vpiName:L1_ICACHE_ID
|INT:19
|vpiParameter:
\_parameter: (L1_IMMU_ID), line:181
|vpiName:L1_IMMU_ID
|INT:0
|vpiParameter:
\_parameter: (LS_UNIT_WB_ID), line:191
|vpiName:LS_UNIT_WB_ID
|INT:1
|vpiParameter:
\_parameter: (MAX_INFLIGHT_COUNT), line:167
|vpiName:MAX_INFLIGHT_COUNT
|INT:19
|vpiParameter:
\_parameter: (MEMORY_ADDR_H), line:103
|vpiName:MEMORY_ADDR_H
|INT:12
|vpiParameter:
\_parameter: (MEMORY_ADDR_L), line:102
|vpiName:MEMORY_ADDR_L
|INT:11
|vpiParameter:
\_parameter: (MEMORY_BIT_CHECK), line:104
|vpiName:MEMORY_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (MUL_UNIT_WB_ID), line:193
|vpiName:MUL_UNIT_WB_ID
|INT:512
|vpiParameter:
\_parameter: (NUM_UNITS), line:188
|vpiName:NUM_UNITS
|INT:2
|vpiParameter:
\_parameter: (NUM_WB_UNITS), line:186
|vpiName:NUM_WB_UNITS
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (RAS_DEPTH), line:161
|vpiName:RAS_DEPTH
|INT:2
|vpiParameter:
\_parameter: (RESET_VEC), line:39
|vpiName:RESET_VEC
|INT:-2147483648
|vpiParameter:
\_parameter: (SCRATCH_ADDR_H), line:99
|vpiName:SCRATCH_ADDR_H
|INT:9
|vpiParameter:
\_parameter: (SCRATCH_ADDR_L), line:98
|vpiName:SCRATCH_ADDR_L
|INT:8
|vpiParameter:
\_parameter: (SCRATCH_BIT_CHECK), line:100
|vpiName:SCRATCH_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (USE_AMO), line:70
|vpiName:USE_AMO
|INT:1
|vpiParameter:
\_parameter: (USE_BRANCH_PREDICTOR), line:158
|vpiName:USE_BRANCH_PREDICTOR
|INT:2
|vpiParameter:
\_parameter: (USE_BUS), line:88
|vpiName:USE_BUS
|INT:4
|vpiParameter:
\_parameter: (USE_DCACHE), line:92
|vpiName:USE_DCACHE
|INT:6
|vpiParameter:
\_parameter: (USE_DIV), line:49
|vpiName:USE_DIV
|INT:1
|vpiParameter:
\_parameter: (USE_DTAG_INVALIDATIONS), line:140
|vpiName:USE_DTAG_INVALIDATIONS
|INT:1879048191
|vpiParameter:
\_parameter: (USE_D_SCRATCH_MEM), line:79
|vpiName:USE_D_SCRATCH_MEM
|INT:3
|vpiParameter:
\_parameter: (USE_ICACHE), line:93
|vpiName:USE_ICACHE
|INT:7
|vpiParameter:
\_parameter: (USE_I_SCRATCH_MEM), line:78
|vpiName:USE_I_SCRATCH_MEM
|INT:2
|vpiParameter:
\_parameter: (USE_MUL), line:48
|vpiName:USE_MUL
|INT:1
|vpiParameter:
\_parameter: (WB_UNITS_WIDTH), line:187
|vpiName:WB_UNITS_WIDTH
|INT:32
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiParameter:
\_parameter: (i), line:90
|vpiName:i
|INT:3
|vpiGenScopeArray:
\_gen_scope_array: (genblk2[0]), line:122, parent:write_back_mux
|vpiName:genblk2[0]
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[0]
|vpiGenScope:
\_gen_scope: , parent:genblk2[0]
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[0]
|vpiProcess:
\_always: , line:123
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:123
|vpiCondition:
\_operation: , line:123
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:123
|vpiName:clk
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[0].clk
|vpiStmt:
\_begin: , line:123
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[0]
|vpiStmt:
\_if_stmt: , line:124
|vpiCondition:
\_bit_select: (id_issued_one_hot), line:124
|vpiName:id_issued_one_hot
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[0].id_issued_one_hot
|vpiIndex:
\_ref_obj: (i), line:124
|vpiName:i
|vpiStmt:
\_assignment: , line:125
|vpiOpType:82
|vpiLhs:
\_bit_select: (id_unit_select_r), line:125
|vpiName:id_unit_select_r
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[0].id_unit_select_r
|vpiIndex:
\_ref_obj: (i), line:125
|vpiName:i
|vpiRhs:
\_ref_obj: (ti.issue_unit_id), line:125
|vpiName:ti.issue_unit_id
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[0].ti.issue_unit_id
|vpiContAssign:
\_cont_assign: , line:127
|vpiRhs:
\_operation: , line:127
|vpiOpType:32
|vpiOperand:
\_bit_select: (id_inuse), line:127
|vpiName:id_inuse
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[0].id_inuse
|vpiIndex:
\_ref_obj: (i), line:127
|vpiName:i
|vpiOperand:
\_bit_select: (id_unit_select_r), line:127
|vpiName:id_unit_select_r
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[0].id_unit_select_r
|vpiIndex:
\_ref_obj: (i), line:127
|vpiName:i
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[0].i
|vpiOperand:
\_ref_obj: (ti.issue_unit_id), line:127
|vpiName:ti.issue_unit_id
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[0].ti.issue_unit_id
|vpiLhs:
\_bit_select: (id_unit_select), line:127
|vpiName:id_unit_select
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[0].id_unit_select
|vpiIndex:
\_ref_obj: (i), line:127
|vpiName:i
|vpiParameter:
\_parameter: (ALU_UNIT_WB_ID), line:190
|vpiName:ALU_UNIT_WB_ID
|INT:32
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (BRANCH_PREDICTOR_WAYS), line:159
|vpiName:BRANCH_PREDICTOR_WAYS
|INT:9
|vpiParameter:
\_parameter: (BRANCH_TABLE_ENTRIES), line:160
|vpiName:BRANCH_TABLE_ENTRIES
|INT:4
|vpiParameter:
\_parameter: (BRANCH_UNIT_ID), line:195
|vpiName:BRANCH_UNIT_ID
|INT:8
|vpiParameter:
\_parameter: (BUS_ADDR_H), line:107
|vpiName:BUS_ADDR_H
|INT:1
|vpiParameter:
\_parameter: (BUS_ADDR_L), line:106
|vpiName:BUS_ADDR_L
|INT:0
|vpiParameter:
\_parameter: (BUS_BIT_CHECK), line:108
|vpiName:BUS_BIT_CHECK
|INT:1
|vpiParameter:
\_parameter: (BUS_TYPE), line:89
|vpiName:BUS_TYPE
|INT:5
|vpiParameter:
\_parameter: (COUNTER_W), line:42
|vpiName:COUNTER_W
|INT:33
|vpiParameter:
\_parameter: (CPU_ID), line:38
|vpiName:CPU_ID
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_ADDR_WIDTH), line:113
|vpiName:C_M_AXI_ADDR_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_DATA_WIDTH), line:114
|vpiName:C_M_AXI_DATA_WIDTH
|INT:1
|vpiParameter:
\_parameter: (DCACHE_LINES), line:133
|vpiName:DCACHE_LINES
|INT:-2146435073
|vpiParameter:
\_parameter: (DCACHE_LINE_ADDR_W), line:135
|vpiName:DCACHE_LINE_ADDR_W
|INT:1073741824
|vpiParameter:
\_parameter: (DCACHE_LINE_W), line:136
|vpiName:DCACHE_LINE_W
|INT:1342177279
|vpiParameter:
\_parameter: (DCACHE_SUB_LINE_ADDR_W), line:137
|vpiName:DCACHE_SUB_LINE_ADDR_W
|INT:4
|vpiParameter:
\_parameter: (DCACHE_TAG_W), line:138
|vpiName:DCACHE_TAG_W
|INT:1610612736
|vpiParameter:
\_parameter: (DCACHE_WAYS), line:134
|vpiName:DCACHE_WAYS
|INT:4
|vpiParameter:
\_parameter: (DIV_ALGORITHM), line:67
|vpiName:DIV_ALGORITHM
|INT:0
|vpiParameter:
\_parameter: (DIV_UNIT_WB_ID), line:192
|vpiName:DIV_UNIT_WB_ID
|INT:2
|vpiParameter:
\_parameter: (DTLB_DEPTH), line:152
|vpiName:DTLB_DEPTH
|INT:512
|vpiParameter:
\_parameter: (DTLB_WAYS), line:151
|vpiName:DTLB_WAYS
|INT:32
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (ENABLE_M_MODE), line:34
|vpiName:ENABLE_M_MODE
|INT:1
|vpiParameter:
\_parameter: (ENABLE_S_MODE), line:36
|vpiName:ENABLE_S_MODE
|INT:0
|vpiParameter:
\_parameter: (ENABLE_TRACE_INTERFACE), line:172
|vpiName:ENABLE_TRACE_INTERFACE
|INT:2
|vpiParameter:
\_parameter: (FETCH_BUFFER_DEPTH), line:168
|vpiName:FETCH_BUFFER_DEPTH
|INT:512
|vpiParameter:
\_parameter: (FPGA_VENDOR), line:27
|vpiName:FPGA_VENDOR
|STRING:"xilinx"
|vpiParameter:
\_parameter: (GC_UNIT_ID), line:196
|vpiName:GC_UNIT_ID
|INT:4
|vpiParameter:
\_parameter: (ICACHE_LINES), line:121
|vpiName:ICACHE_LINES
|INT:2
|vpiParameter:
\_parameter: (ICACHE_LINE_ADDR_W), line:123
|vpiName:ICACHE_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_LINE_W), line:124
|vpiName:ICACHE_LINE_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_SUB_LINE_ADDR_W), line:125
|vpiName:ICACHE_SUB_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_TAG_W), line:126
|vpiName:ICACHE_TAG_W
|INT:-2147483648
|vpiParameter:
\_parameter: (ICACHE_WAYS), line:122
|vpiName:ICACHE_WAYS
|INT:1
|vpiParameter:
\_parameter: (ITLB_DEPTH), line:146
|vpiName:ITLB_DEPTH
|INT:32
|vpiParameter:
\_parameter: (ITLB_WAYS), line:145
|vpiName:ITLB_WAYS
|INT:4
|vpiParameter:
\_parameter: (L1_CONNECTIONS), line:177
|vpiName:L1_CONNECTIONS
|INT:9
|vpiParameter:
\_parameter: (L1_DCACHE_ID), line:178
|vpiName:L1_DCACHE_ID
|INT:4
|vpiParameter:
\_parameter: (L1_DMMU_ID), line:179
|vpiName:L1_DMMU_ID
|INT:2
|vpiParameter:
\_parameter: (L1_ICACHE_ID), line:180
|vpiName:L1_ICACHE_ID
|INT:19
|vpiParameter:
\_parameter: (L1_IMMU_ID), line:181
|vpiName:L1_IMMU_ID
|INT:0
|vpiParameter:
\_parameter: (LS_UNIT_WB_ID), line:191
|vpiName:LS_UNIT_WB_ID
|INT:1
|vpiParameter:
\_parameter: (MAX_INFLIGHT_COUNT), line:167
|vpiName:MAX_INFLIGHT_COUNT
|INT:19
|vpiParameter:
\_parameter: (MEMORY_ADDR_H), line:103
|vpiName:MEMORY_ADDR_H
|INT:12
|vpiParameter:
\_parameter: (MEMORY_ADDR_L), line:102
|vpiName:MEMORY_ADDR_L
|INT:11
|vpiParameter:
\_parameter: (MEMORY_BIT_CHECK), line:104
|vpiName:MEMORY_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (MUL_UNIT_WB_ID), line:193
|vpiName:MUL_UNIT_WB_ID
|INT:512
|vpiParameter:
\_parameter: (NUM_UNITS), line:188
|vpiName:NUM_UNITS
|INT:2
|vpiParameter:
\_parameter: (NUM_WB_UNITS), line:186
|vpiName:NUM_WB_UNITS
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (RAS_DEPTH), line:161
|vpiName:RAS_DEPTH
|INT:2
|vpiParameter:
\_parameter: (RESET_VEC), line:39
|vpiName:RESET_VEC
|INT:-2147483648
|vpiParameter:
\_parameter: (SCRATCH_ADDR_H), line:99
|vpiName:SCRATCH_ADDR_H
|INT:9
|vpiParameter:
\_parameter: (SCRATCH_ADDR_L), line:98
|vpiName:SCRATCH_ADDR_L
|INT:8
|vpiParameter:
\_parameter: (SCRATCH_BIT_CHECK), line:100
|vpiName:SCRATCH_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (USE_AMO), line:70
|vpiName:USE_AMO
|INT:1
|vpiParameter:
\_parameter: (USE_BRANCH_PREDICTOR), line:158
|vpiName:USE_BRANCH_PREDICTOR
|INT:2
|vpiParameter:
\_parameter: (USE_BUS), line:88
|vpiName:USE_BUS
|INT:4
|vpiParameter:
\_parameter: (USE_DCACHE), line:92
|vpiName:USE_DCACHE
|INT:6
|vpiParameter:
\_parameter: (USE_DIV), line:49
|vpiName:USE_DIV
|INT:1
|vpiParameter:
\_parameter: (USE_DTAG_INVALIDATIONS), line:140
|vpiName:USE_DTAG_INVALIDATIONS
|INT:1879048191
|vpiParameter:
\_parameter: (USE_D_SCRATCH_MEM), line:79
|vpiName:USE_D_SCRATCH_MEM
|INT:3
|vpiParameter:
\_parameter: (USE_ICACHE), line:93
|vpiName:USE_ICACHE
|INT:7
|vpiParameter:
\_parameter: (USE_I_SCRATCH_MEM), line:78
|vpiName:USE_I_SCRATCH_MEM
|INT:2
|vpiParameter:
\_parameter: (USE_MUL), line:48
|vpiName:USE_MUL
|INT:1
|vpiParameter:
\_parameter: (WB_UNITS_WIDTH), line:187
|vpiName:WB_UNITS_WIDTH
|INT:32
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiParameter:
\_parameter: (i), line:122
|vpiName:i
|INT:0
|vpiGenScopeArray:
\_gen_scope_array: (genblk2[1]), line:122, parent:write_back_mux
|vpiName:genblk2[1]
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[1]
|vpiGenScope:
\_gen_scope: , parent:genblk2[1]
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[1]
|vpiProcess:
\_always: , line:123
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:123
|vpiCondition:
\_operation: , line:123
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:123
|vpiName:clk
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[1].clk
|vpiStmt:
\_begin: , line:123
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[1]
|vpiStmt:
\_if_stmt: , line:124
|vpiCondition:
\_bit_select: (id_issued_one_hot), line:124
|vpiName:id_issued_one_hot
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[1].id_issued_one_hot
|vpiIndex:
\_ref_obj: (i), line:124
|vpiName:i
|vpiStmt:
\_assignment: , line:125
|vpiOpType:82
|vpiLhs:
\_bit_select: (id_unit_select_r), line:125
|vpiName:id_unit_select_r
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[1].id_unit_select_r
|vpiIndex:
\_ref_obj: (i), line:125
|vpiName:i
|vpiRhs:
\_ref_obj: (ti.issue_unit_id), line:125
|vpiName:ti.issue_unit_id
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[1].ti.issue_unit_id
|vpiContAssign:
\_cont_assign: , line:127
|vpiRhs:
\_operation: , line:127
|vpiOpType:32
|vpiOperand:
\_bit_select: (id_inuse), line:127
|vpiName:id_inuse
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[1].id_inuse
|vpiIndex:
\_ref_obj: (i), line:127
|vpiName:i
|vpiOperand:
\_bit_select: (id_unit_select_r), line:127
|vpiName:id_unit_select_r
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[1].id_unit_select_r
|vpiIndex:
\_ref_obj: (i), line:127
|vpiName:i
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[1].i
|vpiOperand:
\_ref_obj: (ti.issue_unit_id), line:127
|vpiName:ti.issue_unit_id
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[1].ti.issue_unit_id
|vpiLhs:
\_bit_select: (id_unit_select), line:127
|vpiName:id_unit_select
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[1].id_unit_select
|vpiIndex:
\_ref_obj: (i), line:127
|vpiName:i
|vpiParameter:
\_parameter: (ALU_UNIT_WB_ID), line:190
|vpiName:ALU_UNIT_WB_ID
|INT:32
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (BRANCH_PREDICTOR_WAYS), line:159
|vpiName:BRANCH_PREDICTOR_WAYS
|INT:9
|vpiParameter:
\_parameter: (BRANCH_TABLE_ENTRIES), line:160
|vpiName:BRANCH_TABLE_ENTRIES
|INT:4
|vpiParameter:
\_parameter: (BRANCH_UNIT_ID), line:195
|vpiName:BRANCH_UNIT_ID
|INT:8
|vpiParameter:
\_parameter: (BUS_ADDR_H), line:107
|vpiName:BUS_ADDR_H
|INT:1
|vpiParameter:
\_parameter: (BUS_ADDR_L), line:106
|vpiName:BUS_ADDR_L
|INT:0
|vpiParameter:
\_parameter: (BUS_BIT_CHECK), line:108
|vpiName:BUS_BIT_CHECK
|INT:1
|vpiParameter:
\_parameter: (BUS_TYPE), line:89
|vpiName:BUS_TYPE
|INT:5
|vpiParameter:
\_parameter: (COUNTER_W), line:42
|vpiName:COUNTER_W
|INT:33
|vpiParameter:
\_parameter: (CPU_ID), line:38
|vpiName:CPU_ID
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_ADDR_WIDTH), line:113
|vpiName:C_M_AXI_ADDR_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_DATA_WIDTH), line:114
|vpiName:C_M_AXI_DATA_WIDTH
|INT:1
|vpiParameter:
\_parameter: (DCACHE_LINES), line:133
|vpiName:DCACHE_LINES
|INT:-2146435073
|vpiParameter:
\_parameter: (DCACHE_LINE_ADDR_W), line:135
|vpiName:DCACHE_LINE_ADDR_W
|INT:1073741824
|vpiParameter:
\_parameter: (DCACHE_LINE_W), line:136
|vpiName:DCACHE_LINE_W
|INT:1342177279
|vpiParameter:
\_parameter: (DCACHE_SUB_LINE_ADDR_W), line:137
|vpiName:DCACHE_SUB_LINE_ADDR_W
|INT:4
|vpiParameter:
\_parameter: (DCACHE_TAG_W), line:138
|vpiName:DCACHE_TAG_W
|INT:1610612736
|vpiParameter:
\_parameter: (DCACHE_WAYS), line:134
|vpiName:DCACHE_WAYS
|INT:4
|vpiParameter:
\_parameter: (DIV_ALGORITHM), line:67
|vpiName:DIV_ALGORITHM
|INT:0
|vpiParameter:
\_parameter: (DIV_UNIT_WB_ID), line:192
|vpiName:DIV_UNIT_WB_ID
|INT:2
|vpiParameter:
\_parameter: (DTLB_DEPTH), line:152
|vpiName:DTLB_DEPTH
|INT:512
|vpiParameter:
\_parameter: (DTLB_WAYS), line:151
|vpiName:DTLB_WAYS
|INT:32
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (ENABLE_M_MODE), line:34
|vpiName:ENABLE_M_MODE
|INT:1
|vpiParameter:
\_parameter: (ENABLE_S_MODE), line:36
|vpiName:ENABLE_S_MODE
|INT:0
|vpiParameter:
\_parameter: (ENABLE_TRACE_INTERFACE), line:172
|vpiName:ENABLE_TRACE_INTERFACE
|INT:2
|vpiParameter:
\_parameter: (FETCH_BUFFER_DEPTH), line:168
|vpiName:FETCH_BUFFER_DEPTH
|INT:512
|vpiParameter:
\_parameter: (FPGA_VENDOR), line:27
|vpiName:FPGA_VENDOR
|STRING:"xilinx"
|vpiParameter:
\_parameter: (GC_UNIT_ID), line:196
|vpiName:GC_UNIT_ID
|INT:4
|vpiParameter:
\_parameter: (ICACHE_LINES), line:121
|vpiName:ICACHE_LINES
|INT:2
|vpiParameter:
\_parameter: (ICACHE_LINE_ADDR_W), line:123
|vpiName:ICACHE_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_LINE_W), line:124
|vpiName:ICACHE_LINE_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_SUB_LINE_ADDR_W), line:125
|vpiName:ICACHE_SUB_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_TAG_W), line:126
|vpiName:ICACHE_TAG_W
|INT:-2147483648
|vpiParameter:
\_parameter: (ICACHE_WAYS), line:122
|vpiName:ICACHE_WAYS
|INT:1
|vpiParameter:
\_parameter: (ITLB_DEPTH), line:146
|vpiName:ITLB_DEPTH
|INT:32
|vpiParameter:
\_parameter: (ITLB_WAYS), line:145
|vpiName:ITLB_WAYS
|INT:4
|vpiParameter:
\_parameter: (L1_CONNECTIONS), line:177
|vpiName:L1_CONNECTIONS
|INT:9
|vpiParameter:
\_parameter: (L1_DCACHE_ID), line:178
|vpiName:L1_DCACHE_ID
|INT:4
|vpiParameter:
\_parameter: (L1_DMMU_ID), line:179
|vpiName:L1_DMMU_ID
|INT:2
|vpiParameter:
\_parameter: (L1_ICACHE_ID), line:180
|vpiName:L1_ICACHE_ID
|INT:19
|vpiParameter:
\_parameter: (L1_IMMU_ID), line:181
|vpiName:L1_IMMU_ID
|INT:0
|vpiParameter:
\_parameter: (LS_UNIT_WB_ID), line:191
|vpiName:LS_UNIT_WB_ID
|INT:1
|vpiParameter:
\_parameter: (MAX_INFLIGHT_COUNT), line:167
|vpiName:MAX_INFLIGHT_COUNT
|INT:19
|vpiParameter:
\_parameter: (MEMORY_ADDR_H), line:103
|vpiName:MEMORY_ADDR_H
|INT:12
|vpiParameter:
\_parameter: (MEMORY_ADDR_L), line:102
|vpiName:MEMORY_ADDR_L
|INT:11
|vpiParameter:
\_parameter: (MEMORY_BIT_CHECK), line:104
|vpiName:MEMORY_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (MUL_UNIT_WB_ID), line:193
|vpiName:MUL_UNIT_WB_ID
|INT:512
|vpiParameter:
\_parameter: (NUM_UNITS), line:188
|vpiName:NUM_UNITS
|INT:2
|vpiParameter:
\_parameter: (NUM_WB_UNITS), line:186
|vpiName:NUM_WB_UNITS
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (RAS_DEPTH), line:161
|vpiName:RAS_DEPTH
|INT:2
|vpiParameter:
\_parameter: (RESET_VEC), line:39
|vpiName:RESET_VEC
|INT:-2147483648
|vpiParameter:
\_parameter: (SCRATCH_ADDR_H), line:99
|vpiName:SCRATCH_ADDR_H
|INT:9
|vpiParameter:
\_parameter: (SCRATCH_ADDR_L), line:98
|vpiName:SCRATCH_ADDR_L
|INT:8
|vpiParameter:
\_parameter: (SCRATCH_BIT_CHECK), line:100
|vpiName:SCRATCH_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (USE_AMO), line:70
|vpiName:USE_AMO
|INT:1
|vpiParameter:
\_parameter: (USE_BRANCH_PREDICTOR), line:158
|vpiName:USE_BRANCH_PREDICTOR
|INT:2
|vpiParameter:
\_parameter: (USE_BUS), line:88
|vpiName:USE_BUS
|INT:4
|vpiParameter:
\_parameter: (USE_DCACHE), line:92
|vpiName:USE_DCACHE
|INT:6
|vpiParameter:
\_parameter: (USE_DIV), line:49
|vpiName:USE_DIV
|INT:1
|vpiParameter:
\_parameter: (USE_DTAG_INVALIDATIONS), line:140
|vpiName:USE_DTAG_INVALIDATIONS
|INT:1879048191
|vpiParameter:
\_parameter: (USE_D_SCRATCH_MEM), line:79
|vpiName:USE_D_SCRATCH_MEM
|INT:3
|vpiParameter:
\_parameter: (USE_ICACHE), line:93
|vpiName:USE_ICACHE
|INT:7
|vpiParameter:
\_parameter: (USE_I_SCRATCH_MEM), line:78
|vpiName:USE_I_SCRATCH_MEM
|INT:2
|vpiParameter:
\_parameter: (USE_MUL), line:48
|vpiName:USE_MUL
|INT:1
|vpiParameter:
\_parameter: (WB_UNITS_WIDTH), line:187
|vpiName:WB_UNITS_WIDTH
|INT:32
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiParameter:
\_parameter: (i), line:122
|vpiName:i
|INT:1
|vpiGenScopeArray:
\_gen_scope_array: (genblk2[2]), line:122, parent:write_back_mux
|vpiName:genblk2[2]
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[2]
|vpiGenScope:
\_gen_scope: , parent:genblk2[2]
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[2]
|vpiProcess:
\_always: , line:123
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:123
|vpiCondition:
\_operation: , line:123
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:123
|vpiName:clk
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[2].clk
|vpiStmt:
\_begin: , line:123
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[2]
|vpiStmt:
\_if_stmt: , line:124
|vpiCondition:
\_bit_select: (id_issued_one_hot), line:124
|vpiName:id_issued_one_hot
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[2].id_issued_one_hot
|vpiIndex:
\_ref_obj: (i), line:124
|vpiName:i
|vpiStmt:
\_assignment: , line:125
|vpiOpType:82
|vpiLhs:
\_bit_select: (id_unit_select_r), line:125
|vpiName:id_unit_select_r
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[2].id_unit_select_r
|vpiIndex:
\_ref_obj: (i), line:125
|vpiName:i
|vpiRhs:
\_ref_obj: (ti.issue_unit_id), line:125
|vpiName:ti.issue_unit_id
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[2].ti.issue_unit_id
|vpiContAssign:
\_cont_assign: , line:127
|vpiRhs:
\_operation: , line:127
|vpiOpType:32
|vpiOperand:
\_bit_select: (id_inuse), line:127
|vpiName:id_inuse
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[2].id_inuse
|vpiIndex:
\_ref_obj: (i), line:127
|vpiName:i
|vpiOperand:
\_bit_select: (id_unit_select_r), line:127
|vpiName:id_unit_select_r
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[2].id_unit_select_r
|vpiIndex:
\_ref_obj: (i), line:127
|vpiName:i
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[2].i
|vpiOperand:
\_ref_obj: (ti.issue_unit_id), line:127
|vpiName:ti.issue_unit_id
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[2].ti.issue_unit_id
|vpiLhs:
\_bit_select: (id_unit_select), line:127
|vpiName:id_unit_select
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[2].id_unit_select
|vpiIndex:
\_ref_obj: (i), line:127
|vpiName:i
|vpiParameter:
\_parameter: (ALU_UNIT_WB_ID), line:190
|vpiName:ALU_UNIT_WB_ID
|INT:32
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (BRANCH_PREDICTOR_WAYS), line:159
|vpiName:BRANCH_PREDICTOR_WAYS
|INT:9
|vpiParameter:
\_parameter: (BRANCH_TABLE_ENTRIES), line:160
|vpiName:BRANCH_TABLE_ENTRIES
|INT:4
|vpiParameter:
\_parameter: (BRANCH_UNIT_ID), line:195
|vpiName:BRANCH_UNIT_ID
|INT:8
|vpiParameter:
\_parameter: (BUS_ADDR_H), line:107
|vpiName:BUS_ADDR_H
|INT:1
|vpiParameter:
\_parameter: (BUS_ADDR_L), line:106
|vpiName:BUS_ADDR_L
|INT:0
|vpiParameter:
\_parameter: (BUS_BIT_CHECK), line:108
|vpiName:BUS_BIT_CHECK
|INT:1
|vpiParameter:
\_parameter: (BUS_TYPE), line:89
|vpiName:BUS_TYPE
|INT:5
|vpiParameter:
\_parameter: (COUNTER_W), line:42
|vpiName:COUNTER_W
|INT:33
|vpiParameter:
\_parameter: (CPU_ID), line:38
|vpiName:CPU_ID
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_ADDR_WIDTH), line:113
|vpiName:C_M_AXI_ADDR_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_DATA_WIDTH), line:114
|vpiName:C_M_AXI_DATA_WIDTH
|INT:1
|vpiParameter:
\_parameter: (DCACHE_LINES), line:133
|vpiName:DCACHE_LINES
|INT:-2146435073
|vpiParameter:
\_parameter: (DCACHE_LINE_ADDR_W), line:135
|vpiName:DCACHE_LINE_ADDR_W
|INT:1073741824
|vpiParameter:
\_parameter: (DCACHE_LINE_W), line:136
|vpiName:DCACHE_LINE_W
|INT:1342177279
|vpiParameter:
\_parameter: (DCACHE_SUB_LINE_ADDR_W), line:137
|vpiName:DCACHE_SUB_LINE_ADDR_W
|INT:4
|vpiParameter:
\_parameter: (DCACHE_TAG_W), line:138
|vpiName:DCACHE_TAG_W
|INT:1610612736
|vpiParameter:
\_parameter: (DCACHE_WAYS), line:134
|vpiName:DCACHE_WAYS
|INT:4
|vpiParameter:
\_parameter: (DIV_ALGORITHM), line:67
|vpiName:DIV_ALGORITHM
|INT:0
|vpiParameter:
\_parameter: (DIV_UNIT_WB_ID), line:192
|vpiName:DIV_UNIT_WB_ID
|INT:2
|vpiParameter:
\_parameter: (DTLB_DEPTH), line:152
|vpiName:DTLB_DEPTH
|INT:512
|vpiParameter:
\_parameter: (DTLB_WAYS), line:151
|vpiName:DTLB_WAYS
|INT:32
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (ENABLE_M_MODE), line:34
|vpiName:ENABLE_M_MODE
|INT:1
|vpiParameter:
\_parameter: (ENABLE_S_MODE), line:36
|vpiName:ENABLE_S_MODE
|INT:0
|vpiParameter:
\_parameter: (ENABLE_TRACE_INTERFACE), line:172
|vpiName:ENABLE_TRACE_INTERFACE
|INT:2
|vpiParameter:
\_parameter: (FETCH_BUFFER_DEPTH), line:168
|vpiName:FETCH_BUFFER_DEPTH
|INT:512
|vpiParameter:
\_parameter: (FPGA_VENDOR), line:27
|vpiName:FPGA_VENDOR
|STRING:"xilinx"
|vpiParameter:
\_parameter: (GC_UNIT_ID), line:196
|vpiName:GC_UNIT_ID
|INT:4
|vpiParameter:
\_parameter: (ICACHE_LINES), line:121
|vpiName:ICACHE_LINES
|INT:2
|vpiParameter:
\_parameter: (ICACHE_LINE_ADDR_W), line:123
|vpiName:ICACHE_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_LINE_W), line:124
|vpiName:ICACHE_LINE_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_SUB_LINE_ADDR_W), line:125
|vpiName:ICACHE_SUB_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_TAG_W), line:126
|vpiName:ICACHE_TAG_W
|INT:-2147483648
|vpiParameter:
\_parameter: (ICACHE_WAYS), line:122
|vpiName:ICACHE_WAYS
|INT:1
|vpiParameter:
\_parameter: (ITLB_DEPTH), line:146
|vpiName:ITLB_DEPTH
|INT:32
|vpiParameter:
\_parameter: (ITLB_WAYS), line:145
|vpiName:ITLB_WAYS
|INT:4
|vpiParameter:
\_parameter: (L1_CONNECTIONS), line:177
|vpiName:L1_CONNECTIONS
|INT:9
|vpiParameter:
\_parameter: (L1_DCACHE_ID), line:178
|vpiName:L1_DCACHE_ID
|INT:4
|vpiParameter:
\_parameter: (L1_DMMU_ID), line:179
|vpiName:L1_DMMU_ID
|INT:2
|vpiParameter:
\_parameter: (L1_ICACHE_ID), line:180
|vpiName:L1_ICACHE_ID
|INT:19
|vpiParameter:
\_parameter: (L1_IMMU_ID), line:181
|vpiName:L1_IMMU_ID
|INT:0
|vpiParameter:
\_parameter: (LS_UNIT_WB_ID), line:191
|vpiName:LS_UNIT_WB_ID
|INT:1
|vpiParameter:
\_parameter: (MAX_INFLIGHT_COUNT), line:167
|vpiName:MAX_INFLIGHT_COUNT
|INT:19
|vpiParameter:
\_parameter: (MEMORY_ADDR_H), line:103
|vpiName:MEMORY_ADDR_H
|INT:12
|vpiParameter:
\_parameter: (MEMORY_ADDR_L), line:102
|vpiName:MEMORY_ADDR_L
|INT:11
|vpiParameter:
\_parameter: (MEMORY_BIT_CHECK), line:104
|vpiName:MEMORY_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (MUL_UNIT_WB_ID), line:193
|vpiName:MUL_UNIT_WB_ID
|INT:512
|vpiParameter:
\_parameter: (NUM_UNITS), line:188
|vpiName:NUM_UNITS
|INT:2
|vpiParameter:
\_parameter: (NUM_WB_UNITS), line:186
|vpiName:NUM_WB_UNITS
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (RAS_DEPTH), line:161
|vpiName:RAS_DEPTH
|INT:2
|vpiParameter:
\_parameter: (RESET_VEC), line:39
|vpiName:RESET_VEC
|INT:-2147483648
|vpiParameter:
\_parameter: (SCRATCH_ADDR_H), line:99
|vpiName:SCRATCH_ADDR_H
|INT:9
|vpiParameter:
\_parameter: (SCRATCH_ADDR_L), line:98
|vpiName:SCRATCH_ADDR_L
|INT:8
|vpiParameter:
\_parameter: (SCRATCH_BIT_CHECK), line:100
|vpiName:SCRATCH_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (USE_AMO), line:70
|vpiName:USE_AMO
|INT:1
|vpiParameter:
\_parameter: (USE_BRANCH_PREDICTOR), line:158
|vpiName:USE_BRANCH_PREDICTOR
|INT:2
|vpiParameter:
\_parameter: (USE_BUS), line:88
|vpiName:USE_BUS
|INT:4
|vpiParameter:
\_parameter: (USE_DCACHE), line:92
|vpiName:USE_DCACHE
|INT:6
|vpiParameter:
\_parameter: (USE_DIV), line:49
|vpiName:USE_DIV
|INT:1
|vpiParameter:
\_parameter: (USE_DTAG_INVALIDATIONS), line:140
|vpiName:USE_DTAG_INVALIDATIONS
|INT:1879048191
|vpiParameter:
\_parameter: (USE_D_SCRATCH_MEM), line:79
|vpiName:USE_D_SCRATCH_MEM
|INT:3
|vpiParameter:
\_parameter: (USE_ICACHE), line:93
|vpiName:USE_ICACHE
|INT:7
|vpiParameter:
\_parameter: (USE_I_SCRATCH_MEM), line:78
|vpiName:USE_I_SCRATCH_MEM
|INT:2
|vpiParameter:
\_parameter: (USE_MUL), line:48
|vpiName:USE_MUL
|INT:1
|vpiParameter:
\_parameter: (WB_UNITS_WIDTH), line:187
|vpiName:WB_UNITS_WIDTH
|INT:32
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiParameter:
\_parameter: (i), line:122
|vpiName:i
|INT:2
|vpiGenScopeArray:
\_gen_scope_array: (genblk2[3]), line:122, parent:write_back_mux
|vpiName:genblk2[3]
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[3]
|vpiGenScope:
\_gen_scope: , parent:genblk2[3]
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[3]
|vpiProcess:
\_always: , line:123
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:123
|vpiCondition:
\_operation: , line:123
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:123
|vpiName:clk
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[3].clk
|vpiStmt:
\_begin: , line:123
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[3]
|vpiStmt:
\_if_stmt: , line:124
|vpiCondition:
\_bit_select: (id_issued_one_hot), line:124
|vpiName:id_issued_one_hot
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[3].id_issued_one_hot
|vpiIndex:
\_ref_obj: (i), line:124
|vpiName:i
|vpiStmt:
\_assignment: , line:125
|vpiOpType:82
|vpiLhs:
\_bit_select: (id_unit_select_r), line:125
|vpiName:id_unit_select_r
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[3].id_unit_select_r
|vpiIndex:
\_ref_obj: (i), line:125
|vpiName:i
|vpiRhs:
\_ref_obj: (ti.issue_unit_id), line:125
|vpiName:ti.issue_unit_id
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[3].ti.issue_unit_id
|vpiContAssign:
\_cont_assign: , line:127
|vpiRhs:
\_operation: , line:127
|vpiOpType:32
|vpiOperand:
\_bit_select: (id_inuse), line:127
|vpiName:id_inuse
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[3].id_inuse
|vpiIndex:
\_ref_obj: (i), line:127
|vpiName:i
|vpiOperand:
\_bit_select: (id_unit_select_r), line:127
|vpiName:id_unit_select_r
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[3].id_unit_select_r
|vpiIndex:
\_ref_obj: (i), line:127
|vpiName:i
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[3].i
|vpiOperand:
\_ref_obj: (ti.issue_unit_id), line:127
|vpiName:ti.issue_unit_id
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[3].ti.issue_unit_id
|vpiLhs:
\_bit_select: (id_unit_select), line:127
|vpiName:id_unit_select
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[3].id_unit_select
|vpiIndex:
\_ref_obj: (i), line:127
|vpiName:i
|vpiParameter:
\_parameter: (ALU_UNIT_WB_ID), line:190
|vpiName:ALU_UNIT_WB_ID
|INT:32
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (BRANCH_PREDICTOR_WAYS), line:159
|vpiName:BRANCH_PREDICTOR_WAYS
|INT:9
|vpiParameter:
\_parameter: (BRANCH_TABLE_ENTRIES), line:160
|vpiName:BRANCH_TABLE_ENTRIES
|INT:4
|vpiParameter:
\_parameter: (BRANCH_UNIT_ID), line:195
|vpiName:BRANCH_UNIT_ID
|INT:8
|vpiParameter:
\_parameter: (BUS_ADDR_H), line:107
|vpiName:BUS_ADDR_H
|INT:1
|vpiParameter:
\_parameter: (BUS_ADDR_L), line:106
|vpiName:BUS_ADDR_L
|INT:0
|vpiParameter:
\_parameter: (BUS_BIT_CHECK), line:108
|vpiName:BUS_BIT_CHECK
|INT:1
|vpiParameter:
\_parameter: (BUS_TYPE), line:89
|vpiName:BUS_TYPE
|INT:5
|vpiParameter:
\_parameter: (COUNTER_W), line:42
|vpiName:COUNTER_W
|INT:33
|vpiParameter:
\_parameter: (CPU_ID), line:38
|vpiName:CPU_ID
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_ADDR_WIDTH), line:113
|vpiName:C_M_AXI_ADDR_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_DATA_WIDTH), line:114
|vpiName:C_M_AXI_DATA_WIDTH
|INT:1
|vpiParameter:
\_parameter: (DCACHE_LINES), line:133
|vpiName:DCACHE_LINES
|INT:-2146435073
|vpiParameter:
\_parameter: (DCACHE_LINE_ADDR_W), line:135
|vpiName:DCACHE_LINE_ADDR_W
|INT:1073741824
|vpiParameter:
\_parameter: (DCACHE_LINE_W), line:136
|vpiName:DCACHE_LINE_W
|INT:1342177279
|vpiParameter:
\_parameter: (DCACHE_SUB_LINE_ADDR_W), line:137
|vpiName:DCACHE_SUB_LINE_ADDR_W
|INT:4
|vpiParameter:
\_parameter: (DCACHE_TAG_W), line:138
|vpiName:DCACHE_TAG_W
|INT:1610612736
|vpiParameter:
\_parameter: (DCACHE_WAYS), line:134
|vpiName:DCACHE_WAYS
|INT:4
|vpiParameter:
\_parameter: (DIV_ALGORITHM), line:67
|vpiName:DIV_ALGORITHM
|INT:0
|vpiParameter:
\_parameter: (DIV_UNIT_WB_ID), line:192
|vpiName:DIV_UNIT_WB_ID
|INT:2
|vpiParameter:
\_parameter: (DTLB_DEPTH), line:152
|vpiName:DTLB_DEPTH
|INT:512
|vpiParameter:
\_parameter: (DTLB_WAYS), line:151
|vpiName:DTLB_WAYS
|INT:32
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (ENABLE_M_MODE), line:34
|vpiName:ENABLE_M_MODE
|INT:1
|vpiParameter:
\_parameter: (ENABLE_S_MODE), line:36
|vpiName:ENABLE_S_MODE
|INT:0
|vpiParameter:
\_parameter: (ENABLE_TRACE_INTERFACE), line:172
|vpiName:ENABLE_TRACE_INTERFACE
|INT:2
|vpiParameter:
\_parameter: (FETCH_BUFFER_DEPTH), line:168
|vpiName:FETCH_BUFFER_DEPTH
|INT:512
|vpiParameter:
\_parameter: (FPGA_VENDOR), line:27
|vpiName:FPGA_VENDOR
|STRING:"xilinx"
|vpiParameter:
\_parameter: (GC_UNIT_ID), line:196
|vpiName:GC_UNIT_ID
|INT:4
|vpiParameter:
\_parameter: (ICACHE_LINES), line:121
|vpiName:ICACHE_LINES
|INT:2
|vpiParameter:
\_parameter: (ICACHE_LINE_ADDR_W), line:123
|vpiName:ICACHE_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_LINE_W), line:124
|vpiName:ICACHE_LINE_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_SUB_LINE_ADDR_W), line:125
|vpiName:ICACHE_SUB_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_TAG_W), line:126
|vpiName:ICACHE_TAG_W
|INT:-2147483648
|vpiParameter:
\_parameter: (ICACHE_WAYS), line:122
|vpiName:ICACHE_WAYS
|INT:1
|vpiParameter:
\_parameter: (ITLB_DEPTH), line:146
|vpiName:ITLB_DEPTH
|INT:32
|vpiParameter:
\_parameter: (ITLB_WAYS), line:145
|vpiName:ITLB_WAYS
|INT:4
|vpiParameter:
\_parameter: (L1_CONNECTIONS), line:177
|vpiName:L1_CONNECTIONS
|INT:9
|vpiParameter:
\_parameter: (L1_DCACHE_ID), line:178
|vpiName:L1_DCACHE_ID
|INT:4
|vpiParameter:
\_parameter: (L1_DMMU_ID), line:179
|vpiName:L1_DMMU_ID
|INT:2
|vpiParameter:
\_parameter: (L1_ICACHE_ID), line:180
|vpiName:L1_ICACHE_ID
|INT:19
|vpiParameter:
\_parameter: (L1_IMMU_ID), line:181
|vpiName:L1_IMMU_ID
|INT:0
|vpiParameter:
\_parameter: (LS_UNIT_WB_ID), line:191
|vpiName:LS_UNIT_WB_ID
|INT:1
|vpiParameter:
\_parameter: (MAX_INFLIGHT_COUNT), line:167
|vpiName:MAX_INFLIGHT_COUNT
|INT:19
|vpiParameter:
\_parameter: (MEMORY_ADDR_H), line:103
|vpiName:MEMORY_ADDR_H
|INT:12
|vpiParameter:
\_parameter: (MEMORY_ADDR_L), line:102
|vpiName:MEMORY_ADDR_L
|INT:11
|vpiParameter:
\_parameter: (MEMORY_BIT_CHECK), line:104
|vpiName:MEMORY_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (MUL_UNIT_WB_ID), line:193
|vpiName:MUL_UNIT_WB_ID
|INT:512
|vpiParameter:
\_parameter: (NUM_UNITS), line:188
|vpiName:NUM_UNITS
|INT:2
|vpiParameter:
\_parameter: (NUM_WB_UNITS), line:186
|vpiName:NUM_WB_UNITS
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (RAS_DEPTH), line:161
|vpiName:RAS_DEPTH
|INT:2
|vpiParameter:
\_parameter: (RESET_VEC), line:39
|vpiName:RESET_VEC
|INT:-2147483648
|vpiParameter:
\_parameter: (SCRATCH_ADDR_H), line:99
|vpiName:SCRATCH_ADDR_H
|INT:9
|vpiParameter:
\_parameter: (SCRATCH_ADDR_L), line:98
|vpiName:SCRATCH_ADDR_L
|INT:8
|vpiParameter:
\_parameter: (SCRATCH_BIT_CHECK), line:100
|vpiName:SCRATCH_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (USE_AMO), line:70
|vpiName:USE_AMO
|INT:1
|vpiParameter:
\_parameter: (USE_BRANCH_PREDICTOR), line:158
|vpiName:USE_BRANCH_PREDICTOR
|INT:2
|vpiParameter:
\_parameter: (USE_BUS), line:88
|vpiName:USE_BUS
|INT:4
|vpiParameter:
\_parameter: (USE_DCACHE), line:92
|vpiName:USE_DCACHE
|INT:6
|vpiParameter:
\_parameter: (USE_DIV), line:49
|vpiName:USE_DIV
|INT:1
|vpiParameter:
\_parameter: (USE_DTAG_INVALIDATIONS), line:140
|vpiName:USE_DTAG_INVALIDATIONS
|INT:1879048191
|vpiParameter:
\_parameter: (USE_D_SCRATCH_MEM), line:79
|vpiName:USE_D_SCRATCH_MEM
|INT:3
|vpiParameter:
\_parameter: (USE_ICACHE), line:93
|vpiName:USE_ICACHE
|INT:7
|vpiParameter:
\_parameter: (USE_I_SCRATCH_MEM), line:78
|vpiName:USE_I_SCRATCH_MEM
|INT:2
|vpiParameter:
\_parameter: (USE_MUL), line:48
|vpiName:USE_MUL
|INT:1
|vpiParameter:
\_parameter: (WB_UNITS_WIDTH), line:187
|vpiName:WB_UNITS_WIDTH
|INT:32
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiParameter:
\_parameter: (i), line:122
|vpiName:i
|INT:3
|vpiGenScopeArray:
\_gen_scope_array: (genblk2[4]), line:122, parent:write_back_mux
|vpiName:genblk2[4]
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[4]
|vpiGenScope:
\_gen_scope: , parent:genblk2[4]
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[4]
|vpiProcess:
\_always: , line:123
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:123
|vpiCondition:
\_operation: , line:123
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:123
|vpiName:clk
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[4].clk
|vpiStmt:
\_begin: , line:123
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[4]
|vpiStmt:
\_if_stmt: , line:124
|vpiCondition:
\_bit_select: (id_issued_one_hot), line:124
|vpiName:id_issued_one_hot
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[4].id_issued_one_hot
|vpiIndex:
\_ref_obj: (i), line:124
|vpiName:i
|vpiStmt:
\_assignment: , line:125
|vpiOpType:82
|vpiLhs:
\_bit_select: (id_unit_select_r), line:125
|vpiName:id_unit_select_r
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[4].id_unit_select_r
|vpiIndex:
\_ref_obj: (i), line:125
|vpiName:i
|vpiRhs:
\_ref_obj: (ti.issue_unit_id), line:125
|vpiName:ti.issue_unit_id
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[4].ti.issue_unit_id
|vpiContAssign:
\_cont_assign: , line:127
|vpiRhs:
\_operation: , line:127
|vpiOpType:32
|vpiOperand:
\_bit_select: (id_inuse), line:127
|vpiName:id_inuse
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[4].id_inuse
|vpiIndex:
\_ref_obj: (i), line:127
|vpiName:i
|vpiOperand:
\_bit_select: (id_unit_select_r), line:127
|vpiName:id_unit_select_r
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[4].id_unit_select_r
|vpiIndex:
\_ref_obj: (i), line:127
|vpiName:i
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[4].i
|vpiOperand:
\_ref_obj: (ti.issue_unit_id), line:127
|vpiName:ti.issue_unit_id
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[4].ti.issue_unit_id
|vpiLhs:
\_bit_select: (id_unit_select), line:127
|vpiName:id_unit_select
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[4].id_unit_select
|vpiIndex:
\_ref_obj: (i), line:127
|vpiName:i
|vpiParameter:
\_parameter: (ALU_UNIT_WB_ID), line:190
|vpiName:ALU_UNIT_WB_ID
|INT:32
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (BRANCH_PREDICTOR_WAYS), line:159
|vpiName:BRANCH_PREDICTOR_WAYS
|INT:9
|vpiParameter:
\_parameter: (BRANCH_TABLE_ENTRIES), line:160
|vpiName:BRANCH_TABLE_ENTRIES
|INT:4
|vpiParameter:
\_parameter: (BRANCH_UNIT_ID), line:195
|vpiName:BRANCH_UNIT_ID
|INT:8
|vpiParameter:
\_parameter: (BUS_ADDR_H), line:107
|vpiName:BUS_ADDR_H
|INT:1
|vpiParameter:
\_parameter: (BUS_ADDR_L), line:106
|vpiName:BUS_ADDR_L
|INT:0
|vpiParameter:
\_parameter: (BUS_BIT_CHECK), line:108
|vpiName:BUS_BIT_CHECK
|INT:1
|vpiParameter:
\_parameter: (BUS_TYPE), line:89
|vpiName:BUS_TYPE
|INT:5
|vpiParameter:
\_parameter: (COUNTER_W), line:42
|vpiName:COUNTER_W
|INT:33
|vpiParameter:
\_parameter: (CPU_ID), line:38
|vpiName:CPU_ID
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_ADDR_WIDTH), line:113
|vpiName:C_M_AXI_ADDR_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_DATA_WIDTH), line:114
|vpiName:C_M_AXI_DATA_WIDTH
|INT:1
|vpiParameter:
\_parameter: (DCACHE_LINES), line:133
|vpiName:DCACHE_LINES
|INT:-2146435073
|vpiParameter:
\_parameter: (DCACHE_LINE_ADDR_W), line:135
|vpiName:DCACHE_LINE_ADDR_W
|INT:1073741824
|vpiParameter:
\_parameter: (DCACHE_LINE_W), line:136
|vpiName:DCACHE_LINE_W
|INT:1342177279
|vpiParameter:
\_parameter: (DCACHE_SUB_LINE_ADDR_W), line:137
|vpiName:DCACHE_SUB_LINE_ADDR_W
|INT:4
|vpiParameter:
\_parameter: (DCACHE_TAG_W), line:138
|vpiName:DCACHE_TAG_W
|INT:1610612736
|vpiParameter:
\_parameter: (DCACHE_WAYS), line:134
|vpiName:DCACHE_WAYS
|INT:4
|vpiParameter:
\_parameter: (DIV_ALGORITHM), line:67
|vpiName:DIV_ALGORITHM
|INT:0
|vpiParameter:
\_parameter: (DIV_UNIT_WB_ID), line:192
|vpiName:DIV_UNIT_WB_ID
|INT:2
|vpiParameter:
\_parameter: (DTLB_DEPTH), line:152
|vpiName:DTLB_DEPTH
|INT:512
|vpiParameter:
\_parameter: (DTLB_WAYS), line:151
|vpiName:DTLB_WAYS
|INT:32
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (ENABLE_M_MODE), line:34
|vpiName:ENABLE_M_MODE
|INT:1
|vpiParameter:
\_parameter: (ENABLE_S_MODE), line:36
|vpiName:ENABLE_S_MODE
|INT:0
|vpiParameter:
\_parameter: (ENABLE_TRACE_INTERFACE), line:172
|vpiName:ENABLE_TRACE_INTERFACE
|INT:2
|vpiParameter:
\_parameter: (FETCH_BUFFER_DEPTH), line:168
|vpiName:FETCH_BUFFER_DEPTH
|INT:512
|vpiParameter:
\_parameter: (FPGA_VENDOR), line:27
|vpiName:FPGA_VENDOR
|STRING:"xilinx"
|vpiParameter:
\_parameter: (GC_UNIT_ID), line:196
|vpiName:GC_UNIT_ID
|INT:4
|vpiParameter:
\_parameter: (ICACHE_LINES), line:121
|vpiName:ICACHE_LINES
|INT:2
|vpiParameter:
\_parameter: (ICACHE_LINE_ADDR_W), line:123
|vpiName:ICACHE_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_LINE_W), line:124
|vpiName:ICACHE_LINE_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_SUB_LINE_ADDR_W), line:125
|vpiName:ICACHE_SUB_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_TAG_W), line:126
|vpiName:ICACHE_TAG_W
|INT:-2147483648
|vpiParameter:
\_parameter: (ICACHE_WAYS), line:122
|vpiName:ICACHE_WAYS
|INT:1
|vpiParameter:
\_parameter: (ITLB_DEPTH), line:146
|vpiName:ITLB_DEPTH
|INT:32
|vpiParameter:
\_parameter: (ITLB_WAYS), line:145
|vpiName:ITLB_WAYS
|INT:4
|vpiParameter:
\_parameter: (L1_CONNECTIONS), line:177
|vpiName:L1_CONNECTIONS
|INT:9
|vpiParameter:
\_parameter: (L1_DCACHE_ID), line:178
|vpiName:L1_DCACHE_ID
|INT:4
|vpiParameter:
\_parameter: (L1_DMMU_ID), line:179
|vpiName:L1_DMMU_ID
|INT:2
|vpiParameter:
\_parameter: (L1_ICACHE_ID), line:180
|vpiName:L1_ICACHE_ID
|INT:19
|vpiParameter:
\_parameter: (L1_IMMU_ID), line:181
|vpiName:L1_IMMU_ID
|INT:0
|vpiParameter:
\_parameter: (LS_UNIT_WB_ID), line:191
|vpiName:LS_UNIT_WB_ID
|INT:1
|vpiParameter:
\_parameter: (MAX_INFLIGHT_COUNT), line:167
|vpiName:MAX_INFLIGHT_COUNT
|INT:19
|vpiParameter:
\_parameter: (MEMORY_ADDR_H), line:103
|vpiName:MEMORY_ADDR_H
|INT:12
|vpiParameter:
\_parameter: (MEMORY_ADDR_L), line:102
|vpiName:MEMORY_ADDR_L
|INT:11
|vpiParameter:
\_parameter: (MEMORY_BIT_CHECK), line:104
|vpiName:MEMORY_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (MUL_UNIT_WB_ID), line:193
|vpiName:MUL_UNIT_WB_ID
|INT:512
|vpiParameter:
\_parameter: (NUM_UNITS), line:188
|vpiName:NUM_UNITS
|INT:2
|vpiParameter:
\_parameter: (NUM_WB_UNITS), line:186
|vpiName:NUM_WB_UNITS
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (RAS_DEPTH), line:161
|vpiName:RAS_DEPTH
|INT:2
|vpiParameter:
\_parameter: (RESET_VEC), line:39
|vpiName:RESET_VEC
|INT:-2147483648
|vpiParameter:
\_parameter: (SCRATCH_ADDR_H), line:99
|vpiName:SCRATCH_ADDR_H
|INT:9
|vpiParameter:
\_parameter: (SCRATCH_ADDR_L), line:98
|vpiName:SCRATCH_ADDR_L
|INT:8
|vpiParameter:
\_parameter: (SCRATCH_BIT_CHECK), line:100
|vpiName:SCRATCH_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (USE_AMO), line:70
|vpiName:USE_AMO
|INT:1
|vpiParameter:
\_parameter: (USE_BRANCH_PREDICTOR), line:158
|vpiName:USE_BRANCH_PREDICTOR
|INT:2
|vpiParameter:
\_parameter: (USE_BUS), line:88
|vpiName:USE_BUS
|INT:4
|vpiParameter:
\_parameter: (USE_DCACHE), line:92
|vpiName:USE_DCACHE
|INT:6
|vpiParameter:
\_parameter: (USE_DIV), line:49
|vpiName:USE_DIV
|INT:1
|vpiParameter:
\_parameter: (USE_DTAG_INVALIDATIONS), line:140
|vpiName:USE_DTAG_INVALIDATIONS
|INT:1879048191
|vpiParameter:
\_parameter: (USE_D_SCRATCH_MEM), line:79
|vpiName:USE_D_SCRATCH_MEM
|INT:3
|vpiParameter:
\_parameter: (USE_ICACHE), line:93
|vpiName:USE_ICACHE
|INT:7
|vpiParameter:
\_parameter: (USE_I_SCRATCH_MEM), line:78
|vpiName:USE_I_SCRATCH_MEM
|INT:2
|vpiParameter:
\_parameter: (USE_MUL), line:48
|vpiName:USE_MUL
|INT:1
|vpiParameter:
\_parameter: (WB_UNITS_WIDTH), line:187
|vpiName:WB_UNITS_WIDTH
|INT:32
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiParameter:
\_parameter: (i), line:122
|vpiName:i
|INT:4
|vpiGenScopeArray:
\_gen_scope_array: (genblk2[5]), line:122, parent:write_back_mux
|vpiName:genblk2[5]
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[5]
|vpiGenScope:
\_gen_scope: , parent:genblk2[5]
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[5]
|vpiProcess:
\_always: , line:123
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:123
|vpiCondition:
\_operation: , line:123
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:123
|vpiName:clk
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[5].clk
|vpiStmt:
\_begin: , line:123
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[5]
|vpiStmt:
\_if_stmt: , line:124
|vpiCondition:
\_bit_select: (id_issued_one_hot), line:124
|vpiName:id_issued_one_hot
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[5].id_issued_one_hot
|vpiIndex:
\_ref_obj: (i), line:124
|vpiName:i
|vpiStmt:
\_assignment: , line:125
|vpiOpType:82
|vpiLhs:
\_bit_select: (id_unit_select_r), line:125
|vpiName:id_unit_select_r
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[5].id_unit_select_r
|vpiIndex:
\_ref_obj: (i), line:125
|vpiName:i
|vpiRhs:
\_ref_obj: (ti.issue_unit_id), line:125
|vpiName:ti.issue_unit_id
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[5].ti.issue_unit_id
|vpiContAssign:
\_cont_assign: , line:127
|vpiRhs:
\_operation: , line:127
|vpiOpType:32
|vpiOperand:
\_bit_select: (id_inuse), line:127
|vpiName:id_inuse
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[5].id_inuse
|vpiIndex:
\_ref_obj: (i), line:127
|vpiName:i
|vpiOperand:
\_bit_select: (id_unit_select_r), line:127
|vpiName:id_unit_select_r
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[5].id_unit_select_r
|vpiIndex:
\_ref_obj: (i), line:127
|vpiName:i
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[5].i
|vpiOperand:
\_ref_obj: (ti.issue_unit_id), line:127
|vpiName:ti.issue_unit_id
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[5].ti.issue_unit_id
|vpiLhs:
\_bit_select: (id_unit_select), line:127
|vpiName:id_unit_select
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[5].id_unit_select
|vpiIndex:
\_ref_obj: (i), line:127
|vpiName:i
|vpiParameter:
\_parameter: (ALU_UNIT_WB_ID), line:190
|vpiName:ALU_UNIT_WB_ID
|INT:32
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (BRANCH_PREDICTOR_WAYS), line:159
|vpiName:BRANCH_PREDICTOR_WAYS
|INT:9
|vpiParameter:
\_parameter: (BRANCH_TABLE_ENTRIES), line:160
|vpiName:BRANCH_TABLE_ENTRIES
|INT:4
|vpiParameter:
\_parameter: (BRANCH_UNIT_ID), line:195
|vpiName:BRANCH_UNIT_ID
|INT:8
|vpiParameter:
\_parameter: (BUS_ADDR_H), line:107
|vpiName:BUS_ADDR_H
|INT:1
|vpiParameter:
\_parameter: (BUS_ADDR_L), line:106
|vpiName:BUS_ADDR_L
|INT:0
|vpiParameter:
\_parameter: (BUS_BIT_CHECK), line:108
|vpiName:BUS_BIT_CHECK
|INT:1
|vpiParameter:
\_parameter: (BUS_TYPE), line:89
|vpiName:BUS_TYPE
|INT:5
|vpiParameter:
\_parameter: (COUNTER_W), line:42
|vpiName:COUNTER_W
|INT:33
|vpiParameter:
\_parameter: (CPU_ID), line:38
|vpiName:CPU_ID
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_ADDR_WIDTH), line:113
|vpiName:C_M_AXI_ADDR_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_DATA_WIDTH), line:114
|vpiName:C_M_AXI_DATA_WIDTH
|INT:1
|vpiParameter:
\_parameter: (DCACHE_LINES), line:133
|vpiName:DCACHE_LINES
|INT:-2146435073
|vpiParameter:
\_parameter: (DCACHE_LINE_ADDR_W), line:135
|vpiName:DCACHE_LINE_ADDR_W
|INT:1073741824
|vpiParameter:
\_parameter: (DCACHE_LINE_W), line:136
|vpiName:DCACHE_LINE_W
|INT:1342177279
|vpiParameter:
\_parameter: (DCACHE_SUB_LINE_ADDR_W), line:137
|vpiName:DCACHE_SUB_LINE_ADDR_W
|INT:4
|vpiParameter:
\_parameter: (DCACHE_TAG_W), line:138
|vpiName:DCACHE_TAG_W
|INT:1610612736
|vpiParameter:
\_parameter: (DCACHE_WAYS), line:134
|vpiName:DCACHE_WAYS
|INT:4
|vpiParameter:
\_parameter: (DIV_ALGORITHM), line:67
|vpiName:DIV_ALGORITHM
|INT:0
|vpiParameter:
\_parameter: (DIV_UNIT_WB_ID), line:192
|vpiName:DIV_UNIT_WB_ID
|INT:2
|vpiParameter:
\_parameter: (DTLB_DEPTH), line:152
|vpiName:DTLB_DEPTH
|INT:512
|vpiParameter:
\_parameter: (DTLB_WAYS), line:151
|vpiName:DTLB_WAYS
|INT:32
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (ENABLE_M_MODE), line:34
|vpiName:ENABLE_M_MODE
|INT:1
|vpiParameter:
\_parameter: (ENABLE_S_MODE), line:36
|vpiName:ENABLE_S_MODE
|INT:0
|vpiParameter:
\_parameter: (ENABLE_TRACE_INTERFACE), line:172
|vpiName:ENABLE_TRACE_INTERFACE
|INT:2
|vpiParameter:
\_parameter: (FETCH_BUFFER_DEPTH), line:168
|vpiName:FETCH_BUFFER_DEPTH
|INT:512
|vpiParameter:
\_parameter: (FPGA_VENDOR), line:27
|vpiName:FPGA_VENDOR
|STRING:"xilinx"
|vpiParameter:
\_parameter: (GC_UNIT_ID), line:196
|vpiName:GC_UNIT_ID
|INT:4
|vpiParameter:
\_parameter: (ICACHE_LINES), line:121
|vpiName:ICACHE_LINES
|INT:2
|vpiParameter:
\_parameter: (ICACHE_LINE_ADDR_W), line:123
|vpiName:ICACHE_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_LINE_W), line:124
|vpiName:ICACHE_LINE_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_SUB_LINE_ADDR_W), line:125
|vpiName:ICACHE_SUB_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_TAG_W), line:126
|vpiName:ICACHE_TAG_W
|INT:-2147483648
|vpiParameter:
\_parameter: (ICACHE_WAYS), line:122
|vpiName:ICACHE_WAYS
|INT:1
|vpiParameter:
\_parameter: (ITLB_DEPTH), line:146
|vpiName:ITLB_DEPTH
|INT:32
|vpiParameter:
\_parameter: (ITLB_WAYS), line:145
|vpiName:ITLB_WAYS
|INT:4
|vpiParameter:
\_parameter: (L1_CONNECTIONS), line:177
|vpiName:L1_CONNECTIONS
|INT:9
|vpiParameter:
\_parameter: (L1_DCACHE_ID), line:178
|vpiName:L1_DCACHE_ID
|INT:4
|vpiParameter:
\_parameter: (L1_DMMU_ID), line:179
|vpiName:L1_DMMU_ID
|INT:2
|vpiParameter:
\_parameter: (L1_ICACHE_ID), line:180
|vpiName:L1_ICACHE_ID
|INT:19
|vpiParameter:
\_parameter: (L1_IMMU_ID), line:181
|vpiName:L1_IMMU_ID
|INT:0
|vpiParameter:
\_parameter: (LS_UNIT_WB_ID), line:191
|vpiName:LS_UNIT_WB_ID
|INT:1
|vpiParameter:
\_parameter: (MAX_INFLIGHT_COUNT), line:167
|vpiName:MAX_INFLIGHT_COUNT
|INT:19
|vpiParameter:
\_parameter: (MEMORY_ADDR_H), line:103
|vpiName:MEMORY_ADDR_H
|INT:12
|vpiParameter:
\_parameter: (MEMORY_ADDR_L), line:102
|vpiName:MEMORY_ADDR_L
|INT:11
|vpiParameter:
\_parameter: (MEMORY_BIT_CHECK), line:104
|vpiName:MEMORY_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (MUL_UNIT_WB_ID), line:193
|vpiName:MUL_UNIT_WB_ID
|INT:512
|vpiParameter:
\_parameter: (NUM_UNITS), line:188
|vpiName:NUM_UNITS
|INT:2
|vpiParameter:
\_parameter: (NUM_WB_UNITS), line:186
|vpiName:NUM_WB_UNITS
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (RAS_DEPTH), line:161
|vpiName:RAS_DEPTH
|INT:2
|vpiParameter:
\_parameter: (RESET_VEC), line:39
|vpiName:RESET_VEC
|INT:-2147483648
|vpiParameter:
\_parameter: (SCRATCH_ADDR_H), line:99
|vpiName:SCRATCH_ADDR_H
|INT:9
|vpiParameter:
\_parameter: (SCRATCH_ADDR_L), line:98
|vpiName:SCRATCH_ADDR_L
|INT:8
|vpiParameter:
\_parameter: (SCRATCH_BIT_CHECK), line:100
|vpiName:SCRATCH_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (USE_AMO), line:70
|vpiName:USE_AMO
|INT:1
|vpiParameter:
\_parameter: (USE_BRANCH_PREDICTOR), line:158
|vpiName:USE_BRANCH_PREDICTOR
|INT:2
|vpiParameter:
\_parameter: (USE_BUS), line:88
|vpiName:USE_BUS
|INT:4
|vpiParameter:
\_parameter: (USE_DCACHE), line:92
|vpiName:USE_DCACHE
|INT:6
|vpiParameter:
\_parameter: (USE_DIV), line:49
|vpiName:USE_DIV
|INT:1
|vpiParameter:
\_parameter: (USE_DTAG_INVALIDATIONS), line:140
|vpiName:USE_DTAG_INVALIDATIONS
|INT:1879048191
|vpiParameter:
\_parameter: (USE_D_SCRATCH_MEM), line:79
|vpiName:USE_D_SCRATCH_MEM
|INT:3
|vpiParameter:
\_parameter: (USE_ICACHE), line:93
|vpiName:USE_ICACHE
|INT:7
|vpiParameter:
\_parameter: (USE_I_SCRATCH_MEM), line:78
|vpiName:USE_I_SCRATCH_MEM
|INT:2
|vpiParameter:
\_parameter: (USE_MUL), line:48
|vpiName:USE_MUL
|INT:1
|vpiParameter:
\_parameter: (WB_UNITS_WIDTH), line:187
|vpiName:WB_UNITS_WIDTH
|INT:32
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiParameter:
\_parameter: (i), line:122
|vpiName:i
|INT:5
|vpiGenScopeArray:
\_gen_scope_array: (genblk2[6]), line:122, parent:write_back_mux
|vpiName:genblk2[6]
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[6]
|vpiGenScope:
\_gen_scope: , parent:genblk2[6]
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[6]
|vpiProcess:
\_always: , line:123
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:123
|vpiCondition:
\_operation: , line:123
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:123
|vpiName:clk
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[6].clk
|vpiStmt:
\_begin: , line:123
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[6]
|vpiStmt:
\_if_stmt: , line:124
|vpiCondition:
\_bit_select: (id_issued_one_hot), line:124
|vpiName:id_issued_one_hot
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[6].id_issued_one_hot
|vpiIndex:
\_ref_obj: (i), line:124
|vpiName:i
|vpiStmt:
\_assignment: , line:125
|vpiOpType:82
|vpiLhs:
\_bit_select: (id_unit_select_r), line:125
|vpiName:id_unit_select_r
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[6].id_unit_select_r
|vpiIndex:
\_ref_obj: (i), line:125
|vpiName:i
|vpiRhs:
\_ref_obj: (ti.issue_unit_id), line:125
|vpiName:ti.issue_unit_id
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[6].ti.issue_unit_id
|vpiContAssign:
\_cont_assign: , line:127
|vpiRhs:
\_operation: , line:127
|vpiOpType:32
|vpiOperand:
\_bit_select: (id_inuse), line:127
|vpiName:id_inuse
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[6].id_inuse
|vpiIndex:
\_ref_obj: (i), line:127
|vpiName:i
|vpiOperand:
\_bit_select: (id_unit_select_r), line:127
|vpiName:id_unit_select_r
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[6].id_unit_select_r
|vpiIndex:
\_ref_obj: (i), line:127
|vpiName:i
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[6].i
|vpiOperand:
\_ref_obj: (ti.issue_unit_id), line:127
|vpiName:ti.issue_unit_id
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[6].ti.issue_unit_id
|vpiLhs:
\_bit_select: (id_unit_select), line:127
|vpiName:id_unit_select
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[6].id_unit_select
|vpiIndex:
\_ref_obj: (i), line:127
|vpiName:i
|vpiParameter:
\_parameter: (ALU_UNIT_WB_ID), line:190
|vpiName:ALU_UNIT_WB_ID
|INT:32
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (BRANCH_PREDICTOR_WAYS), line:159
|vpiName:BRANCH_PREDICTOR_WAYS
|INT:9
|vpiParameter:
\_parameter: (BRANCH_TABLE_ENTRIES), line:160
|vpiName:BRANCH_TABLE_ENTRIES
|INT:4
|vpiParameter:
\_parameter: (BRANCH_UNIT_ID), line:195
|vpiName:BRANCH_UNIT_ID
|INT:8
|vpiParameter:
\_parameter: (BUS_ADDR_H), line:107
|vpiName:BUS_ADDR_H
|INT:1
|vpiParameter:
\_parameter: (BUS_ADDR_L), line:106
|vpiName:BUS_ADDR_L
|INT:0
|vpiParameter:
\_parameter: (BUS_BIT_CHECK), line:108
|vpiName:BUS_BIT_CHECK
|INT:1
|vpiParameter:
\_parameter: (BUS_TYPE), line:89
|vpiName:BUS_TYPE
|INT:5
|vpiParameter:
\_parameter: (COUNTER_W), line:42
|vpiName:COUNTER_W
|INT:33
|vpiParameter:
\_parameter: (CPU_ID), line:38
|vpiName:CPU_ID
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_ADDR_WIDTH), line:113
|vpiName:C_M_AXI_ADDR_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_DATA_WIDTH), line:114
|vpiName:C_M_AXI_DATA_WIDTH
|INT:1
|vpiParameter:
\_parameter: (DCACHE_LINES), line:133
|vpiName:DCACHE_LINES
|INT:-2146435073
|vpiParameter:
\_parameter: (DCACHE_LINE_ADDR_W), line:135
|vpiName:DCACHE_LINE_ADDR_W
|INT:1073741824
|vpiParameter:
\_parameter: (DCACHE_LINE_W), line:136
|vpiName:DCACHE_LINE_W
|INT:1342177279
|vpiParameter:
\_parameter: (DCACHE_SUB_LINE_ADDR_W), line:137
|vpiName:DCACHE_SUB_LINE_ADDR_W
|INT:4
|vpiParameter:
\_parameter: (DCACHE_TAG_W), line:138
|vpiName:DCACHE_TAG_W
|INT:1610612736
|vpiParameter:
\_parameter: (DCACHE_WAYS), line:134
|vpiName:DCACHE_WAYS
|INT:4
|vpiParameter:
\_parameter: (DIV_ALGORITHM), line:67
|vpiName:DIV_ALGORITHM
|INT:0
|vpiParameter:
\_parameter: (DIV_UNIT_WB_ID), line:192
|vpiName:DIV_UNIT_WB_ID
|INT:2
|vpiParameter:
\_parameter: (DTLB_DEPTH), line:152
|vpiName:DTLB_DEPTH
|INT:512
|vpiParameter:
\_parameter: (DTLB_WAYS), line:151
|vpiName:DTLB_WAYS
|INT:32
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (ENABLE_M_MODE), line:34
|vpiName:ENABLE_M_MODE
|INT:1
|vpiParameter:
\_parameter: (ENABLE_S_MODE), line:36
|vpiName:ENABLE_S_MODE
|INT:0
|vpiParameter:
\_parameter: (ENABLE_TRACE_INTERFACE), line:172
|vpiName:ENABLE_TRACE_INTERFACE
|INT:2
|vpiParameter:
\_parameter: (FETCH_BUFFER_DEPTH), line:168
|vpiName:FETCH_BUFFER_DEPTH
|INT:512
|vpiParameter:
\_parameter: (FPGA_VENDOR), line:27
|vpiName:FPGA_VENDOR
|STRING:"xilinx"
|vpiParameter:
\_parameter: (GC_UNIT_ID), line:196
|vpiName:GC_UNIT_ID
|INT:4
|vpiParameter:
\_parameter: (ICACHE_LINES), line:121
|vpiName:ICACHE_LINES
|INT:2
|vpiParameter:
\_parameter: (ICACHE_LINE_ADDR_W), line:123
|vpiName:ICACHE_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_LINE_W), line:124
|vpiName:ICACHE_LINE_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_SUB_LINE_ADDR_W), line:125
|vpiName:ICACHE_SUB_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_TAG_W), line:126
|vpiName:ICACHE_TAG_W
|INT:-2147483648
|vpiParameter:
\_parameter: (ICACHE_WAYS), line:122
|vpiName:ICACHE_WAYS
|INT:1
|vpiParameter:
\_parameter: (ITLB_DEPTH), line:146
|vpiName:ITLB_DEPTH
|INT:32
|vpiParameter:
\_parameter: (ITLB_WAYS), line:145
|vpiName:ITLB_WAYS
|INT:4
|vpiParameter:
\_parameter: (L1_CONNECTIONS), line:177
|vpiName:L1_CONNECTIONS
|INT:9
|vpiParameter:
\_parameter: (L1_DCACHE_ID), line:178
|vpiName:L1_DCACHE_ID
|INT:4
|vpiParameter:
\_parameter: (L1_DMMU_ID), line:179
|vpiName:L1_DMMU_ID
|INT:2
|vpiParameter:
\_parameter: (L1_ICACHE_ID), line:180
|vpiName:L1_ICACHE_ID
|INT:19
|vpiParameter:
\_parameter: (L1_IMMU_ID), line:181
|vpiName:L1_IMMU_ID
|INT:0
|vpiParameter:
\_parameter: (LS_UNIT_WB_ID), line:191
|vpiName:LS_UNIT_WB_ID
|INT:1
|vpiParameter:
\_parameter: (MAX_INFLIGHT_COUNT), line:167
|vpiName:MAX_INFLIGHT_COUNT
|INT:19
|vpiParameter:
\_parameter: (MEMORY_ADDR_H), line:103
|vpiName:MEMORY_ADDR_H
|INT:12
|vpiParameter:
\_parameter: (MEMORY_ADDR_L), line:102
|vpiName:MEMORY_ADDR_L
|INT:11
|vpiParameter:
\_parameter: (MEMORY_BIT_CHECK), line:104
|vpiName:MEMORY_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (MUL_UNIT_WB_ID), line:193
|vpiName:MUL_UNIT_WB_ID
|INT:512
|vpiParameter:
\_parameter: (NUM_UNITS), line:188
|vpiName:NUM_UNITS
|INT:2
|vpiParameter:
\_parameter: (NUM_WB_UNITS), line:186
|vpiName:NUM_WB_UNITS
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (RAS_DEPTH), line:161
|vpiName:RAS_DEPTH
|INT:2
|vpiParameter:
\_parameter: (RESET_VEC), line:39
|vpiName:RESET_VEC
|INT:-2147483648
|vpiParameter:
\_parameter: (SCRATCH_ADDR_H), line:99
|vpiName:SCRATCH_ADDR_H
|INT:9
|vpiParameter:
\_parameter: (SCRATCH_ADDR_L), line:98
|vpiName:SCRATCH_ADDR_L
|INT:8
|vpiParameter:
\_parameter: (SCRATCH_BIT_CHECK), line:100
|vpiName:SCRATCH_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (USE_AMO), line:70
|vpiName:USE_AMO
|INT:1
|vpiParameter:
\_parameter: (USE_BRANCH_PREDICTOR), line:158
|vpiName:USE_BRANCH_PREDICTOR
|INT:2
|vpiParameter:
\_parameter: (USE_BUS), line:88
|vpiName:USE_BUS
|INT:4
|vpiParameter:
\_parameter: (USE_DCACHE), line:92
|vpiName:USE_DCACHE
|INT:6
|vpiParameter:
\_parameter: (USE_DIV), line:49
|vpiName:USE_DIV
|INT:1
|vpiParameter:
\_parameter: (USE_DTAG_INVALIDATIONS), line:140
|vpiName:USE_DTAG_INVALIDATIONS
|INT:1879048191
|vpiParameter:
\_parameter: (USE_D_SCRATCH_MEM), line:79
|vpiName:USE_D_SCRATCH_MEM
|INT:3
|vpiParameter:
\_parameter: (USE_ICACHE), line:93
|vpiName:USE_ICACHE
|INT:7
|vpiParameter:
\_parameter: (USE_I_SCRATCH_MEM), line:78
|vpiName:USE_I_SCRATCH_MEM
|INT:2
|vpiParameter:
\_parameter: (USE_MUL), line:48
|vpiName:USE_MUL
|INT:1
|vpiParameter:
\_parameter: (WB_UNITS_WIDTH), line:187
|vpiName:WB_UNITS_WIDTH
|INT:32
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiParameter:
\_parameter: (i), line:122
|vpiName:i
|INT:6
|vpiGenScopeArray:
\_gen_scope_array: (genblk2[7]), line:122, parent:write_back_mux
|vpiName:genblk2[7]
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[7]
|vpiGenScope:
\_gen_scope: , parent:genblk2[7]
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[7]
|vpiProcess:
\_always: , line:123
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:123
|vpiCondition:
\_operation: , line:123
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:123
|vpiName:clk
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[7].clk
|vpiStmt:
\_begin: , line:123
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[7]
|vpiStmt:
\_if_stmt: , line:124
|vpiCondition:
\_bit_select: (id_issued_one_hot), line:124
|vpiName:id_issued_one_hot
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[7].id_issued_one_hot
|vpiIndex:
\_ref_obj: (i), line:124
|vpiName:i
|vpiStmt:
\_assignment: , line:125
|vpiOpType:82
|vpiLhs:
\_bit_select: (id_unit_select_r), line:125
|vpiName:id_unit_select_r
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[7].id_unit_select_r
|vpiIndex:
\_ref_obj: (i), line:125
|vpiName:i
|vpiRhs:
\_ref_obj: (ti.issue_unit_id), line:125
|vpiName:ti.issue_unit_id
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[7].ti.issue_unit_id
|vpiContAssign:
\_cont_assign: , line:127
|vpiRhs:
\_operation: , line:127
|vpiOpType:32
|vpiOperand:
\_bit_select: (id_inuse), line:127
|vpiName:id_inuse
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[7].id_inuse
|vpiIndex:
\_ref_obj: (i), line:127
|vpiName:i
|vpiOperand:
\_bit_select: (id_unit_select_r), line:127
|vpiName:id_unit_select_r
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[7].id_unit_select_r
|vpiIndex:
\_ref_obj: (i), line:127
|vpiName:i
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[7].i
|vpiOperand:
\_ref_obj: (ti.issue_unit_id), line:127
|vpiName:ti.issue_unit_id
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[7].ti.issue_unit_id
|vpiLhs:
\_bit_select: (id_unit_select), line:127
|vpiName:id_unit_select
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[7].id_unit_select
|vpiIndex:
\_ref_obj: (i), line:127
|vpiName:i
|vpiParameter:
\_parameter: (ALU_UNIT_WB_ID), line:190
|vpiName:ALU_UNIT_WB_ID
|INT:32
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (BRANCH_PREDICTOR_WAYS), line:159
|vpiName:BRANCH_PREDICTOR_WAYS
|INT:9
|vpiParameter:
\_parameter: (BRANCH_TABLE_ENTRIES), line:160
|vpiName:BRANCH_TABLE_ENTRIES
|INT:4
|vpiParameter:
\_parameter: (BRANCH_UNIT_ID), line:195
|vpiName:BRANCH_UNIT_ID
|INT:8
|vpiParameter:
\_parameter: (BUS_ADDR_H), line:107
|vpiName:BUS_ADDR_H
|INT:1
|vpiParameter:
\_parameter: (BUS_ADDR_L), line:106
|vpiName:BUS_ADDR_L
|INT:0
|vpiParameter:
\_parameter: (BUS_BIT_CHECK), line:108
|vpiName:BUS_BIT_CHECK
|INT:1
|vpiParameter:
\_parameter: (BUS_TYPE), line:89
|vpiName:BUS_TYPE
|INT:5
|vpiParameter:
\_parameter: (COUNTER_W), line:42
|vpiName:COUNTER_W
|INT:33
|vpiParameter:
\_parameter: (CPU_ID), line:38
|vpiName:CPU_ID
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_ADDR_WIDTH), line:113
|vpiName:C_M_AXI_ADDR_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_DATA_WIDTH), line:114
|vpiName:C_M_AXI_DATA_WIDTH
|INT:1
|vpiParameter:
\_parameter: (DCACHE_LINES), line:133
|vpiName:DCACHE_LINES
|INT:-2146435073
|vpiParameter:
\_parameter: (DCACHE_LINE_ADDR_W), line:135
|vpiName:DCACHE_LINE_ADDR_W
|INT:1073741824
|vpiParameter:
\_parameter: (DCACHE_LINE_W), line:136
|vpiName:DCACHE_LINE_W
|INT:1342177279
|vpiParameter:
\_parameter: (DCACHE_SUB_LINE_ADDR_W), line:137
|vpiName:DCACHE_SUB_LINE_ADDR_W
|INT:4
|vpiParameter:
\_parameter: (DCACHE_TAG_W), line:138
|vpiName:DCACHE_TAG_W
|INT:1610612736
|vpiParameter:
\_parameter: (DCACHE_WAYS), line:134
|vpiName:DCACHE_WAYS
|INT:4
|vpiParameter:
\_parameter: (DIV_ALGORITHM), line:67
|vpiName:DIV_ALGORITHM
|INT:0
|vpiParameter:
\_parameter: (DIV_UNIT_WB_ID), line:192
|vpiName:DIV_UNIT_WB_ID
|INT:2
|vpiParameter:
\_parameter: (DTLB_DEPTH), line:152
|vpiName:DTLB_DEPTH
|INT:512
|vpiParameter:
\_parameter: (DTLB_WAYS), line:151
|vpiName:DTLB_WAYS
|INT:32
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (ENABLE_M_MODE), line:34
|vpiName:ENABLE_M_MODE
|INT:1
|vpiParameter:
\_parameter: (ENABLE_S_MODE), line:36
|vpiName:ENABLE_S_MODE
|INT:0
|vpiParameter:
\_parameter: (ENABLE_TRACE_INTERFACE), line:172
|vpiName:ENABLE_TRACE_INTERFACE
|INT:2
|vpiParameter:
\_parameter: (FETCH_BUFFER_DEPTH), line:168
|vpiName:FETCH_BUFFER_DEPTH
|INT:512
|vpiParameter:
\_parameter: (FPGA_VENDOR), line:27
|vpiName:FPGA_VENDOR
|STRING:"xilinx"
|vpiParameter:
\_parameter: (GC_UNIT_ID), line:196
|vpiName:GC_UNIT_ID
|INT:4
|vpiParameter:
\_parameter: (ICACHE_LINES), line:121
|vpiName:ICACHE_LINES
|INT:2
|vpiParameter:
\_parameter: (ICACHE_LINE_ADDR_W), line:123
|vpiName:ICACHE_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_LINE_W), line:124
|vpiName:ICACHE_LINE_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_SUB_LINE_ADDR_W), line:125
|vpiName:ICACHE_SUB_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_TAG_W), line:126
|vpiName:ICACHE_TAG_W
|INT:-2147483648
|vpiParameter:
\_parameter: (ICACHE_WAYS), line:122
|vpiName:ICACHE_WAYS
|INT:1
|vpiParameter:
\_parameter: (ITLB_DEPTH), line:146
|vpiName:ITLB_DEPTH
|INT:32
|vpiParameter:
\_parameter: (ITLB_WAYS), line:145
|vpiName:ITLB_WAYS
|INT:4
|vpiParameter:
\_parameter: (L1_CONNECTIONS), line:177
|vpiName:L1_CONNECTIONS
|INT:9
|vpiParameter:
\_parameter: (L1_DCACHE_ID), line:178
|vpiName:L1_DCACHE_ID
|INT:4
|vpiParameter:
\_parameter: (L1_DMMU_ID), line:179
|vpiName:L1_DMMU_ID
|INT:2
|vpiParameter:
\_parameter: (L1_ICACHE_ID), line:180
|vpiName:L1_ICACHE_ID
|INT:19
|vpiParameter:
\_parameter: (L1_IMMU_ID), line:181
|vpiName:L1_IMMU_ID
|INT:0
|vpiParameter:
\_parameter: (LS_UNIT_WB_ID), line:191
|vpiName:LS_UNIT_WB_ID
|INT:1
|vpiParameter:
\_parameter: (MAX_INFLIGHT_COUNT), line:167
|vpiName:MAX_INFLIGHT_COUNT
|INT:19
|vpiParameter:
\_parameter: (MEMORY_ADDR_H), line:103
|vpiName:MEMORY_ADDR_H
|INT:12
|vpiParameter:
\_parameter: (MEMORY_ADDR_L), line:102
|vpiName:MEMORY_ADDR_L
|INT:11
|vpiParameter:
\_parameter: (MEMORY_BIT_CHECK), line:104
|vpiName:MEMORY_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (MUL_UNIT_WB_ID), line:193
|vpiName:MUL_UNIT_WB_ID
|INT:512
|vpiParameter:
\_parameter: (NUM_UNITS), line:188
|vpiName:NUM_UNITS
|INT:2
|vpiParameter:
\_parameter: (NUM_WB_UNITS), line:186
|vpiName:NUM_WB_UNITS
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (RAS_DEPTH), line:161
|vpiName:RAS_DEPTH
|INT:2
|vpiParameter:
\_parameter: (RESET_VEC), line:39
|vpiName:RESET_VEC
|INT:-2147483648
|vpiParameter:
\_parameter: (SCRATCH_ADDR_H), line:99
|vpiName:SCRATCH_ADDR_H
|INT:9
|vpiParameter:
\_parameter: (SCRATCH_ADDR_L), line:98
|vpiName:SCRATCH_ADDR_L
|INT:8
|vpiParameter:
\_parameter: (SCRATCH_BIT_CHECK), line:100
|vpiName:SCRATCH_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (USE_AMO), line:70
|vpiName:USE_AMO
|INT:1
|vpiParameter:
\_parameter: (USE_BRANCH_PREDICTOR), line:158
|vpiName:USE_BRANCH_PREDICTOR
|INT:2
|vpiParameter:
\_parameter: (USE_BUS), line:88
|vpiName:USE_BUS
|INT:4
|vpiParameter:
\_parameter: (USE_DCACHE), line:92
|vpiName:USE_DCACHE
|INT:6
|vpiParameter:
\_parameter: (USE_DIV), line:49
|vpiName:USE_DIV
|INT:1
|vpiParameter:
\_parameter: (USE_DTAG_INVALIDATIONS), line:140
|vpiName:USE_DTAG_INVALIDATIONS
|INT:1879048191
|vpiParameter:
\_parameter: (USE_D_SCRATCH_MEM), line:79
|vpiName:USE_D_SCRATCH_MEM
|INT:3
|vpiParameter:
\_parameter: (USE_ICACHE), line:93
|vpiName:USE_ICACHE
|INT:7
|vpiParameter:
\_parameter: (USE_I_SCRATCH_MEM), line:78
|vpiName:USE_I_SCRATCH_MEM
|INT:2
|vpiParameter:
\_parameter: (USE_MUL), line:48
|vpiName:USE_MUL
|INT:1
|vpiParameter:
\_parameter: (WB_UNITS_WIDTH), line:187
|vpiName:WB_UNITS_WIDTH
|INT:32
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiParameter:
\_parameter: (i), line:122
|vpiName:i
|INT:7
|vpiGenScopeArray:
\_gen_scope_array: (genblk2[8]), line:122, parent:write_back_mux
|vpiName:genblk2[8]
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[8]
|vpiGenScope:
\_gen_scope: , parent:genblk2[8]
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[8]
|vpiProcess:
\_always: , line:123
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:123
|vpiCondition:
\_operation: , line:123
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:123
|vpiName:clk
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[8].clk
|vpiStmt:
\_begin: , line:123
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[8]
|vpiStmt:
\_if_stmt: , line:124
|vpiCondition:
\_bit_select: (id_issued_one_hot), line:124
|vpiName:id_issued_one_hot
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[8].id_issued_one_hot
|vpiIndex:
\_ref_obj: (i), line:124
|vpiName:i
|vpiStmt:
\_assignment: , line:125
|vpiOpType:82
|vpiLhs:
\_bit_select: (id_unit_select_r), line:125
|vpiName:id_unit_select_r
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[8].id_unit_select_r
|vpiIndex:
\_ref_obj: (i), line:125
|vpiName:i
|vpiRhs:
\_ref_obj: (ti.issue_unit_id), line:125
|vpiName:ti.issue_unit_id
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[8].ti.issue_unit_id
|vpiContAssign:
\_cont_assign: , line:127
|vpiRhs:
\_operation: , line:127
|vpiOpType:32
|vpiOperand:
\_bit_select: (id_inuse), line:127
|vpiName:id_inuse
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[8].id_inuse
|vpiIndex:
\_ref_obj: (i), line:127
|vpiName:i
|vpiOperand:
\_bit_select: (id_unit_select_r), line:127
|vpiName:id_unit_select_r
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[8].id_unit_select_r
|vpiIndex:
\_ref_obj: (i), line:127
|vpiName:i
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[8].i
|vpiOperand:
\_ref_obj: (ti.issue_unit_id), line:127
|vpiName:ti.issue_unit_id
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[8].ti.issue_unit_id
|vpiLhs:
\_bit_select: (id_unit_select), line:127
|vpiName:id_unit_select
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[8].id_unit_select
|vpiIndex:
\_ref_obj: (i), line:127
|vpiName:i
|vpiParameter:
\_parameter: (ALU_UNIT_WB_ID), line:190
|vpiName:ALU_UNIT_WB_ID
|INT:32
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (BRANCH_PREDICTOR_WAYS), line:159
|vpiName:BRANCH_PREDICTOR_WAYS
|INT:9
|vpiParameter:
\_parameter: (BRANCH_TABLE_ENTRIES), line:160
|vpiName:BRANCH_TABLE_ENTRIES
|INT:4
|vpiParameter:
\_parameter: (BRANCH_UNIT_ID), line:195
|vpiName:BRANCH_UNIT_ID
|INT:8
|vpiParameter:
\_parameter: (BUS_ADDR_H), line:107
|vpiName:BUS_ADDR_H
|INT:1
|vpiParameter:
\_parameter: (BUS_ADDR_L), line:106
|vpiName:BUS_ADDR_L
|INT:0
|vpiParameter:
\_parameter: (BUS_BIT_CHECK), line:108
|vpiName:BUS_BIT_CHECK
|INT:1
|vpiParameter:
\_parameter: (BUS_TYPE), line:89
|vpiName:BUS_TYPE
|INT:5
|vpiParameter:
\_parameter: (COUNTER_W), line:42
|vpiName:COUNTER_W
|INT:33
|vpiParameter:
\_parameter: (CPU_ID), line:38
|vpiName:CPU_ID
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_ADDR_WIDTH), line:113
|vpiName:C_M_AXI_ADDR_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_DATA_WIDTH), line:114
|vpiName:C_M_AXI_DATA_WIDTH
|INT:1
|vpiParameter:
\_parameter: (DCACHE_LINES), line:133
|vpiName:DCACHE_LINES
|INT:-2146435073
|vpiParameter:
\_parameter: (DCACHE_LINE_ADDR_W), line:135
|vpiName:DCACHE_LINE_ADDR_W
|INT:1073741824
|vpiParameter:
\_parameter: (DCACHE_LINE_W), line:136
|vpiName:DCACHE_LINE_W
|INT:1342177279
|vpiParameter:
\_parameter: (DCACHE_SUB_LINE_ADDR_W), line:137
|vpiName:DCACHE_SUB_LINE_ADDR_W
|INT:4
|vpiParameter:
\_parameter: (DCACHE_TAG_W), line:138
|vpiName:DCACHE_TAG_W
|INT:1610612736
|vpiParameter:
\_parameter: (DCACHE_WAYS), line:134
|vpiName:DCACHE_WAYS
|INT:4
|vpiParameter:
\_parameter: (DIV_ALGORITHM), line:67
|vpiName:DIV_ALGORITHM
|INT:0
|vpiParameter:
\_parameter: (DIV_UNIT_WB_ID), line:192
|vpiName:DIV_UNIT_WB_ID
|INT:2
|vpiParameter:
\_parameter: (DTLB_DEPTH), line:152
|vpiName:DTLB_DEPTH
|INT:512
|vpiParameter:
\_parameter: (DTLB_WAYS), line:151
|vpiName:DTLB_WAYS
|INT:32
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (ENABLE_M_MODE), line:34
|vpiName:ENABLE_M_MODE
|INT:1
|vpiParameter:
\_parameter: (ENABLE_S_MODE), line:36
|vpiName:ENABLE_S_MODE
|INT:0
|vpiParameter:
\_parameter: (ENABLE_TRACE_INTERFACE), line:172
|vpiName:ENABLE_TRACE_INTERFACE
|INT:2
|vpiParameter:
\_parameter: (FETCH_BUFFER_DEPTH), line:168
|vpiName:FETCH_BUFFER_DEPTH
|INT:512
|vpiParameter:
\_parameter: (FPGA_VENDOR), line:27
|vpiName:FPGA_VENDOR
|STRING:"xilinx"
|vpiParameter:
\_parameter: (GC_UNIT_ID), line:196
|vpiName:GC_UNIT_ID
|INT:4
|vpiParameter:
\_parameter: (ICACHE_LINES), line:121
|vpiName:ICACHE_LINES
|INT:2
|vpiParameter:
\_parameter: (ICACHE_LINE_ADDR_W), line:123
|vpiName:ICACHE_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_LINE_W), line:124
|vpiName:ICACHE_LINE_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_SUB_LINE_ADDR_W), line:125
|vpiName:ICACHE_SUB_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_TAG_W), line:126
|vpiName:ICACHE_TAG_W
|INT:-2147483648
|vpiParameter:
\_parameter: (ICACHE_WAYS), line:122
|vpiName:ICACHE_WAYS
|INT:1
|vpiParameter:
\_parameter: (ITLB_DEPTH), line:146
|vpiName:ITLB_DEPTH
|INT:32
|vpiParameter:
\_parameter: (ITLB_WAYS), line:145
|vpiName:ITLB_WAYS
|INT:4
|vpiParameter:
\_parameter: (L1_CONNECTIONS), line:177
|vpiName:L1_CONNECTIONS
|INT:9
|vpiParameter:
\_parameter: (L1_DCACHE_ID), line:178
|vpiName:L1_DCACHE_ID
|INT:4
|vpiParameter:
\_parameter: (L1_DMMU_ID), line:179
|vpiName:L1_DMMU_ID
|INT:2
|vpiParameter:
\_parameter: (L1_ICACHE_ID), line:180
|vpiName:L1_ICACHE_ID
|INT:19
|vpiParameter:
\_parameter: (L1_IMMU_ID), line:181
|vpiName:L1_IMMU_ID
|INT:0
|vpiParameter:
\_parameter: (LS_UNIT_WB_ID), line:191
|vpiName:LS_UNIT_WB_ID
|INT:1
|vpiParameter:
\_parameter: (MAX_INFLIGHT_COUNT), line:167
|vpiName:MAX_INFLIGHT_COUNT
|INT:19
|vpiParameter:
\_parameter: (MEMORY_ADDR_H), line:103
|vpiName:MEMORY_ADDR_H
|INT:12
|vpiParameter:
\_parameter: (MEMORY_ADDR_L), line:102
|vpiName:MEMORY_ADDR_L
|INT:11
|vpiParameter:
\_parameter: (MEMORY_BIT_CHECK), line:104
|vpiName:MEMORY_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (MUL_UNIT_WB_ID), line:193
|vpiName:MUL_UNIT_WB_ID
|INT:512
|vpiParameter:
\_parameter: (NUM_UNITS), line:188
|vpiName:NUM_UNITS
|INT:2
|vpiParameter:
\_parameter: (NUM_WB_UNITS), line:186
|vpiName:NUM_WB_UNITS
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (RAS_DEPTH), line:161
|vpiName:RAS_DEPTH
|INT:2
|vpiParameter:
\_parameter: (RESET_VEC), line:39
|vpiName:RESET_VEC
|INT:-2147483648
|vpiParameter:
\_parameter: (SCRATCH_ADDR_H), line:99
|vpiName:SCRATCH_ADDR_H
|INT:9
|vpiParameter:
\_parameter: (SCRATCH_ADDR_L), line:98
|vpiName:SCRATCH_ADDR_L
|INT:8
|vpiParameter:
\_parameter: (SCRATCH_BIT_CHECK), line:100
|vpiName:SCRATCH_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (USE_AMO), line:70
|vpiName:USE_AMO
|INT:1
|vpiParameter:
\_parameter: (USE_BRANCH_PREDICTOR), line:158
|vpiName:USE_BRANCH_PREDICTOR
|INT:2
|vpiParameter:
\_parameter: (USE_BUS), line:88
|vpiName:USE_BUS
|INT:4
|vpiParameter:
\_parameter: (USE_DCACHE), line:92
|vpiName:USE_DCACHE
|INT:6
|vpiParameter:
\_parameter: (USE_DIV), line:49
|vpiName:USE_DIV
|INT:1
|vpiParameter:
\_parameter: (USE_DTAG_INVALIDATIONS), line:140
|vpiName:USE_DTAG_INVALIDATIONS
|INT:1879048191
|vpiParameter:
\_parameter: (USE_D_SCRATCH_MEM), line:79
|vpiName:USE_D_SCRATCH_MEM
|INT:3
|vpiParameter:
\_parameter: (USE_ICACHE), line:93
|vpiName:USE_ICACHE
|INT:7
|vpiParameter:
\_parameter: (USE_I_SCRATCH_MEM), line:78
|vpiName:USE_I_SCRATCH_MEM
|INT:2
|vpiParameter:
\_parameter: (USE_MUL), line:48
|vpiName:USE_MUL
|INT:1
|vpiParameter:
\_parameter: (WB_UNITS_WIDTH), line:187
|vpiName:WB_UNITS_WIDTH
|INT:32
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiParameter:
\_parameter: (i), line:122
|vpiName:i
|INT:8
|vpiGenScopeArray:
\_gen_scope_array: (genblk2[9]), line:122, parent:write_back_mux
|vpiName:genblk2[9]
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[9]
|vpiGenScope:
\_gen_scope: , parent:genblk2[9]
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[9]
|vpiProcess:
\_always: , line:123
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:123
|vpiCondition:
\_operation: , line:123
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:123
|vpiName:clk
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[9].clk
|vpiStmt:
\_begin: , line:123
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[9]
|vpiStmt:
\_if_stmt: , line:124
|vpiCondition:
\_bit_select: (id_issued_one_hot), line:124
|vpiName:id_issued_one_hot
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[9].id_issued_one_hot
|vpiIndex:
\_ref_obj: (i), line:124
|vpiName:i
|vpiStmt:
\_assignment: , line:125
|vpiOpType:82
|vpiLhs:
\_bit_select: (id_unit_select_r), line:125
|vpiName:id_unit_select_r
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[9].id_unit_select_r
|vpiIndex:
\_ref_obj: (i), line:125
|vpiName:i
|vpiRhs:
\_ref_obj: (ti.issue_unit_id), line:125
|vpiName:ti.issue_unit_id
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[9].ti.issue_unit_id
|vpiContAssign:
\_cont_assign: , line:127
|vpiRhs:
\_operation: , line:127
|vpiOpType:32
|vpiOperand:
\_bit_select: (id_inuse), line:127
|vpiName:id_inuse
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[9].id_inuse
|vpiIndex:
\_ref_obj: (i), line:127
|vpiName:i
|vpiOperand:
\_bit_select: (id_unit_select_r), line:127
|vpiName:id_unit_select_r
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[9].id_unit_select_r
|vpiIndex:
\_ref_obj: (i), line:127
|vpiName:i
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[9].i
|vpiOperand:
\_ref_obj: (ti.issue_unit_id), line:127
|vpiName:ti.issue_unit_id
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[9].ti.issue_unit_id
|vpiLhs:
\_bit_select: (id_unit_select), line:127
|vpiName:id_unit_select
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[9].id_unit_select
|vpiIndex:
\_ref_obj: (i), line:127
|vpiName:i
|vpiParameter:
\_parameter: (ALU_UNIT_WB_ID), line:190
|vpiName:ALU_UNIT_WB_ID
|INT:32
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (BRANCH_PREDICTOR_WAYS), line:159
|vpiName:BRANCH_PREDICTOR_WAYS
|INT:9
|vpiParameter:
\_parameter: (BRANCH_TABLE_ENTRIES), line:160
|vpiName:BRANCH_TABLE_ENTRIES
|INT:4
|vpiParameter:
\_parameter: (BRANCH_UNIT_ID), line:195
|vpiName:BRANCH_UNIT_ID
|INT:8
|vpiParameter:
\_parameter: (BUS_ADDR_H), line:107
|vpiName:BUS_ADDR_H
|INT:1
|vpiParameter:
\_parameter: (BUS_ADDR_L), line:106
|vpiName:BUS_ADDR_L
|INT:0
|vpiParameter:
\_parameter: (BUS_BIT_CHECK), line:108
|vpiName:BUS_BIT_CHECK
|INT:1
|vpiParameter:
\_parameter: (BUS_TYPE), line:89
|vpiName:BUS_TYPE
|INT:5
|vpiParameter:
\_parameter: (COUNTER_W), line:42
|vpiName:COUNTER_W
|INT:33
|vpiParameter:
\_parameter: (CPU_ID), line:38
|vpiName:CPU_ID
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_ADDR_WIDTH), line:113
|vpiName:C_M_AXI_ADDR_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_DATA_WIDTH), line:114
|vpiName:C_M_AXI_DATA_WIDTH
|INT:1
|vpiParameter:
\_parameter: (DCACHE_LINES), line:133
|vpiName:DCACHE_LINES
|INT:-2146435073
|vpiParameter:
\_parameter: (DCACHE_LINE_ADDR_W), line:135
|vpiName:DCACHE_LINE_ADDR_W
|INT:1073741824
|vpiParameter:
\_parameter: (DCACHE_LINE_W), line:136
|vpiName:DCACHE_LINE_W
|INT:1342177279
|vpiParameter:
\_parameter: (DCACHE_SUB_LINE_ADDR_W), line:137
|vpiName:DCACHE_SUB_LINE_ADDR_W
|INT:4
|vpiParameter:
\_parameter: (DCACHE_TAG_W), line:138
|vpiName:DCACHE_TAG_W
|INT:1610612736
|vpiParameter:
\_parameter: (DCACHE_WAYS), line:134
|vpiName:DCACHE_WAYS
|INT:4
|vpiParameter:
\_parameter: (DIV_ALGORITHM), line:67
|vpiName:DIV_ALGORITHM
|INT:0
|vpiParameter:
\_parameter: (DIV_UNIT_WB_ID), line:192
|vpiName:DIV_UNIT_WB_ID
|INT:2
|vpiParameter:
\_parameter: (DTLB_DEPTH), line:152
|vpiName:DTLB_DEPTH
|INT:512
|vpiParameter:
\_parameter: (DTLB_WAYS), line:151
|vpiName:DTLB_WAYS
|INT:32
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (ENABLE_M_MODE), line:34
|vpiName:ENABLE_M_MODE
|INT:1
|vpiParameter:
\_parameter: (ENABLE_S_MODE), line:36
|vpiName:ENABLE_S_MODE
|INT:0
|vpiParameter:
\_parameter: (ENABLE_TRACE_INTERFACE), line:172
|vpiName:ENABLE_TRACE_INTERFACE
|INT:2
|vpiParameter:
\_parameter: (FETCH_BUFFER_DEPTH), line:168
|vpiName:FETCH_BUFFER_DEPTH
|INT:512
|vpiParameter:
\_parameter: (FPGA_VENDOR), line:27
|vpiName:FPGA_VENDOR
|STRING:"xilinx"
|vpiParameter:
\_parameter: (GC_UNIT_ID), line:196
|vpiName:GC_UNIT_ID
|INT:4
|vpiParameter:
\_parameter: (ICACHE_LINES), line:121
|vpiName:ICACHE_LINES
|INT:2
|vpiParameter:
\_parameter: (ICACHE_LINE_ADDR_W), line:123
|vpiName:ICACHE_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_LINE_W), line:124
|vpiName:ICACHE_LINE_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_SUB_LINE_ADDR_W), line:125
|vpiName:ICACHE_SUB_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_TAG_W), line:126
|vpiName:ICACHE_TAG_W
|INT:-2147483648
|vpiParameter:
\_parameter: (ICACHE_WAYS), line:122
|vpiName:ICACHE_WAYS
|INT:1
|vpiParameter:
\_parameter: (ITLB_DEPTH), line:146
|vpiName:ITLB_DEPTH
|INT:32
|vpiParameter:
\_parameter: (ITLB_WAYS), line:145
|vpiName:ITLB_WAYS
|INT:4
|vpiParameter:
\_parameter: (L1_CONNECTIONS), line:177
|vpiName:L1_CONNECTIONS
|INT:9
|vpiParameter:
\_parameter: (L1_DCACHE_ID), line:178
|vpiName:L1_DCACHE_ID
|INT:4
|vpiParameter:
\_parameter: (L1_DMMU_ID), line:179
|vpiName:L1_DMMU_ID
|INT:2
|vpiParameter:
\_parameter: (L1_ICACHE_ID), line:180
|vpiName:L1_ICACHE_ID
|INT:19
|vpiParameter:
\_parameter: (L1_IMMU_ID), line:181
|vpiName:L1_IMMU_ID
|INT:0
|vpiParameter:
\_parameter: (LS_UNIT_WB_ID), line:191
|vpiName:LS_UNIT_WB_ID
|INT:1
|vpiParameter:
\_parameter: (MAX_INFLIGHT_COUNT), line:167
|vpiName:MAX_INFLIGHT_COUNT
|INT:19
|vpiParameter:
\_parameter: (MEMORY_ADDR_H), line:103
|vpiName:MEMORY_ADDR_H
|INT:12
|vpiParameter:
\_parameter: (MEMORY_ADDR_L), line:102
|vpiName:MEMORY_ADDR_L
|INT:11
|vpiParameter:
\_parameter: (MEMORY_BIT_CHECK), line:104
|vpiName:MEMORY_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (MUL_UNIT_WB_ID), line:193
|vpiName:MUL_UNIT_WB_ID
|INT:512
|vpiParameter:
\_parameter: (NUM_UNITS), line:188
|vpiName:NUM_UNITS
|INT:2
|vpiParameter:
\_parameter: (NUM_WB_UNITS), line:186
|vpiName:NUM_WB_UNITS
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (RAS_DEPTH), line:161
|vpiName:RAS_DEPTH
|INT:2
|vpiParameter:
\_parameter: (RESET_VEC), line:39
|vpiName:RESET_VEC
|INT:-2147483648
|vpiParameter:
\_parameter: (SCRATCH_ADDR_H), line:99
|vpiName:SCRATCH_ADDR_H
|INT:9
|vpiParameter:
\_parameter: (SCRATCH_ADDR_L), line:98
|vpiName:SCRATCH_ADDR_L
|INT:8
|vpiParameter:
\_parameter: (SCRATCH_BIT_CHECK), line:100
|vpiName:SCRATCH_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (USE_AMO), line:70
|vpiName:USE_AMO
|INT:1
|vpiParameter:
\_parameter: (USE_BRANCH_PREDICTOR), line:158
|vpiName:USE_BRANCH_PREDICTOR
|INT:2
|vpiParameter:
\_parameter: (USE_BUS), line:88
|vpiName:USE_BUS
|INT:4
|vpiParameter:
\_parameter: (USE_DCACHE), line:92
|vpiName:USE_DCACHE
|INT:6
|vpiParameter:
\_parameter: (USE_DIV), line:49
|vpiName:USE_DIV
|INT:1
|vpiParameter:
\_parameter: (USE_DTAG_INVALIDATIONS), line:140
|vpiName:USE_DTAG_INVALIDATIONS
|INT:1879048191
|vpiParameter:
\_parameter: (USE_D_SCRATCH_MEM), line:79
|vpiName:USE_D_SCRATCH_MEM
|INT:3
|vpiParameter:
\_parameter: (USE_ICACHE), line:93
|vpiName:USE_ICACHE
|INT:7
|vpiParameter:
\_parameter: (USE_I_SCRATCH_MEM), line:78
|vpiName:USE_I_SCRATCH_MEM
|INT:2
|vpiParameter:
\_parameter: (USE_MUL), line:48
|vpiName:USE_MUL
|INT:1
|vpiParameter:
\_parameter: (WB_UNITS_WIDTH), line:187
|vpiName:WB_UNITS_WIDTH
|INT:32
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiParameter:
\_parameter: (i), line:122
|vpiName:i
|INT:9
|vpiGenScopeArray:
\_gen_scope_array: (genblk2[10]), line:122, parent:write_back_mux
|vpiName:genblk2[10]
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[10]
|vpiGenScope:
\_gen_scope: , parent:genblk2[10]
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[10]
|vpiProcess:
\_always: , line:123
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:123
|vpiCondition:
\_operation: , line:123
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:123
|vpiName:clk
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[10].clk
|vpiStmt:
\_begin: , line:123
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[10]
|vpiStmt:
\_if_stmt: , line:124
|vpiCondition:
\_bit_select: (id_issued_one_hot), line:124
|vpiName:id_issued_one_hot
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[10].id_issued_one_hot
|vpiIndex:
\_ref_obj: (i), line:124
|vpiName:i
|vpiStmt:
\_assignment: , line:125
|vpiOpType:82
|vpiLhs:
\_bit_select: (id_unit_select_r), line:125
|vpiName:id_unit_select_r
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[10].id_unit_select_r
|vpiIndex:
\_ref_obj: (i), line:125
|vpiName:i
|vpiRhs:
\_ref_obj: (ti.issue_unit_id), line:125
|vpiName:ti.issue_unit_id
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[10].ti.issue_unit_id
|vpiContAssign:
\_cont_assign: , line:127
|vpiRhs:
\_operation: , line:127
|vpiOpType:32
|vpiOperand:
\_bit_select: (id_inuse), line:127
|vpiName:id_inuse
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[10].id_inuse
|vpiIndex:
\_ref_obj: (i), line:127
|vpiName:i
|vpiOperand:
\_bit_select: (id_unit_select_r), line:127
|vpiName:id_unit_select_r
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[10].id_unit_select_r
|vpiIndex:
\_ref_obj: (i), line:127
|vpiName:i
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[10].i
|vpiOperand:
\_ref_obj: (ti.issue_unit_id), line:127
|vpiName:ti.issue_unit_id
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[10].ti.issue_unit_id
|vpiLhs:
\_bit_select: (id_unit_select), line:127
|vpiName:id_unit_select
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[10].id_unit_select
|vpiIndex:
\_ref_obj: (i), line:127
|vpiName:i
|vpiParameter:
\_parameter: (ALU_UNIT_WB_ID), line:190
|vpiName:ALU_UNIT_WB_ID
|INT:32
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (BRANCH_PREDICTOR_WAYS), line:159
|vpiName:BRANCH_PREDICTOR_WAYS
|INT:9
|vpiParameter:
\_parameter: (BRANCH_TABLE_ENTRIES), line:160
|vpiName:BRANCH_TABLE_ENTRIES
|INT:4
|vpiParameter:
\_parameter: (BRANCH_UNIT_ID), line:195
|vpiName:BRANCH_UNIT_ID
|INT:8
|vpiParameter:
\_parameter: (BUS_ADDR_H), line:107
|vpiName:BUS_ADDR_H
|INT:1
|vpiParameter:
\_parameter: (BUS_ADDR_L), line:106
|vpiName:BUS_ADDR_L
|INT:0
|vpiParameter:
\_parameter: (BUS_BIT_CHECK), line:108
|vpiName:BUS_BIT_CHECK
|INT:1
|vpiParameter:
\_parameter: (BUS_TYPE), line:89
|vpiName:BUS_TYPE
|INT:5
|vpiParameter:
\_parameter: (COUNTER_W), line:42
|vpiName:COUNTER_W
|INT:33
|vpiParameter:
\_parameter: (CPU_ID), line:38
|vpiName:CPU_ID
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_ADDR_WIDTH), line:113
|vpiName:C_M_AXI_ADDR_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_DATA_WIDTH), line:114
|vpiName:C_M_AXI_DATA_WIDTH
|INT:1
|vpiParameter:
\_parameter: (DCACHE_LINES), line:133
|vpiName:DCACHE_LINES
|INT:-2146435073
|vpiParameter:
\_parameter: (DCACHE_LINE_ADDR_W), line:135
|vpiName:DCACHE_LINE_ADDR_W
|INT:1073741824
|vpiParameter:
\_parameter: (DCACHE_LINE_W), line:136
|vpiName:DCACHE_LINE_W
|INT:1342177279
|vpiParameter:
\_parameter: (DCACHE_SUB_LINE_ADDR_W), line:137
|vpiName:DCACHE_SUB_LINE_ADDR_W
|INT:4
|vpiParameter:
\_parameter: (DCACHE_TAG_W), line:138
|vpiName:DCACHE_TAG_W
|INT:1610612736
|vpiParameter:
\_parameter: (DCACHE_WAYS), line:134
|vpiName:DCACHE_WAYS
|INT:4
|vpiParameter:
\_parameter: (DIV_ALGORITHM), line:67
|vpiName:DIV_ALGORITHM
|INT:0
|vpiParameter:
\_parameter: (DIV_UNIT_WB_ID), line:192
|vpiName:DIV_UNIT_WB_ID
|INT:2
|vpiParameter:
\_parameter: (DTLB_DEPTH), line:152
|vpiName:DTLB_DEPTH
|INT:512
|vpiParameter:
\_parameter: (DTLB_WAYS), line:151
|vpiName:DTLB_WAYS
|INT:32
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (ENABLE_M_MODE), line:34
|vpiName:ENABLE_M_MODE
|INT:1
|vpiParameter:
\_parameter: (ENABLE_S_MODE), line:36
|vpiName:ENABLE_S_MODE
|INT:0
|vpiParameter:
\_parameter: (ENABLE_TRACE_INTERFACE), line:172
|vpiName:ENABLE_TRACE_INTERFACE
|INT:2
|vpiParameter:
\_parameter: (FETCH_BUFFER_DEPTH), line:168
|vpiName:FETCH_BUFFER_DEPTH
|INT:512
|vpiParameter:
\_parameter: (FPGA_VENDOR), line:27
|vpiName:FPGA_VENDOR
|STRING:"xilinx"
|vpiParameter:
\_parameter: (GC_UNIT_ID), line:196
|vpiName:GC_UNIT_ID
|INT:4
|vpiParameter:
\_parameter: (ICACHE_LINES), line:121
|vpiName:ICACHE_LINES
|INT:2
|vpiParameter:
\_parameter: (ICACHE_LINE_ADDR_W), line:123
|vpiName:ICACHE_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_LINE_W), line:124
|vpiName:ICACHE_LINE_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_SUB_LINE_ADDR_W), line:125
|vpiName:ICACHE_SUB_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_TAG_W), line:126
|vpiName:ICACHE_TAG_W
|INT:-2147483648
|vpiParameter:
\_parameter: (ICACHE_WAYS), line:122
|vpiName:ICACHE_WAYS
|INT:1
|vpiParameter:
\_parameter: (ITLB_DEPTH), line:146
|vpiName:ITLB_DEPTH
|INT:32
|vpiParameter:
\_parameter: (ITLB_WAYS), line:145
|vpiName:ITLB_WAYS
|INT:4
|vpiParameter:
\_parameter: (L1_CONNECTIONS), line:177
|vpiName:L1_CONNECTIONS
|INT:9
|vpiParameter:
\_parameter: (L1_DCACHE_ID), line:178
|vpiName:L1_DCACHE_ID
|INT:4
|vpiParameter:
\_parameter: (L1_DMMU_ID), line:179
|vpiName:L1_DMMU_ID
|INT:2
|vpiParameter:
\_parameter: (L1_ICACHE_ID), line:180
|vpiName:L1_ICACHE_ID
|INT:19
|vpiParameter:
\_parameter: (L1_IMMU_ID), line:181
|vpiName:L1_IMMU_ID
|INT:0
|vpiParameter:
\_parameter: (LS_UNIT_WB_ID), line:191
|vpiName:LS_UNIT_WB_ID
|INT:1
|vpiParameter:
\_parameter: (MAX_INFLIGHT_COUNT), line:167
|vpiName:MAX_INFLIGHT_COUNT
|INT:19
|vpiParameter:
\_parameter: (MEMORY_ADDR_H), line:103
|vpiName:MEMORY_ADDR_H
|INT:12
|vpiParameter:
\_parameter: (MEMORY_ADDR_L), line:102
|vpiName:MEMORY_ADDR_L
|INT:11
|vpiParameter:
\_parameter: (MEMORY_BIT_CHECK), line:104
|vpiName:MEMORY_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (MUL_UNIT_WB_ID), line:193
|vpiName:MUL_UNIT_WB_ID
|INT:512
|vpiParameter:
\_parameter: (NUM_UNITS), line:188
|vpiName:NUM_UNITS
|INT:2
|vpiParameter:
\_parameter: (NUM_WB_UNITS), line:186
|vpiName:NUM_WB_UNITS
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (RAS_DEPTH), line:161
|vpiName:RAS_DEPTH
|INT:2
|vpiParameter:
\_parameter: (RESET_VEC), line:39
|vpiName:RESET_VEC
|INT:-2147483648
|vpiParameter:
\_parameter: (SCRATCH_ADDR_H), line:99
|vpiName:SCRATCH_ADDR_H
|INT:9
|vpiParameter:
\_parameter: (SCRATCH_ADDR_L), line:98
|vpiName:SCRATCH_ADDR_L
|INT:8
|vpiParameter:
\_parameter: (SCRATCH_BIT_CHECK), line:100
|vpiName:SCRATCH_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (USE_AMO), line:70
|vpiName:USE_AMO
|INT:1
|vpiParameter:
\_parameter: (USE_BRANCH_PREDICTOR), line:158
|vpiName:USE_BRANCH_PREDICTOR
|INT:2
|vpiParameter:
\_parameter: (USE_BUS), line:88
|vpiName:USE_BUS
|INT:4
|vpiParameter:
\_parameter: (USE_DCACHE), line:92
|vpiName:USE_DCACHE
|INT:6
|vpiParameter:
\_parameter: (USE_DIV), line:49
|vpiName:USE_DIV
|INT:1
|vpiParameter:
\_parameter: (USE_DTAG_INVALIDATIONS), line:140
|vpiName:USE_DTAG_INVALIDATIONS
|INT:1879048191
|vpiParameter:
\_parameter: (USE_D_SCRATCH_MEM), line:79
|vpiName:USE_D_SCRATCH_MEM
|INT:3
|vpiParameter:
\_parameter: (USE_ICACHE), line:93
|vpiName:USE_ICACHE
|INT:7
|vpiParameter:
\_parameter: (USE_I_SCRATCH_MEM), line:78
|vpiName:USE_I_SCRATCH_MEM
|INT:2
|vpiParameter:
\_parameter: (USE_MUL), line:48
|vpiName:USE_MUL
|INT:1
|vpiParameter:
\_parameter: (WB_UNITS_WIDTH), line:187
|vpiName:WB_UNITS_WIDTH
|INT:32
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiParameter:
\_parameter: (i), line:122
|vpiName:i
|INT:10
|vpiGenScopeArray:
\_gen_scope_array: (genblk2[11]), line:122, parent:write_back_mux
|vpiName:genblk2[11]
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[11]
|vpiGenScope:
\_gen_scope: , parent:genblk2[11]
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[11]
|vpiProcess:
\_always: , line:123
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:123
|vpiCondition:
\_operation: , line:123
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:123
|vpiName:clk
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[11].clk
|vpiStmt:
\_begin: , line:123
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[11]
|vpiStmt:
\_if_stmt: , line:124
|vpiCondition:
\_bit_select: (id_issued_one_hot), line:124
|vpiName:id_issued_one_hot
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[11].id_issued_one_hot
|vpiIndex:
\_ref_obj: (i), line:124
|vpiName:i
|vpiStmt:
\_assignment: , line:125
|vpiOpType:82
|vpiLhs:
\_bit_select: (id_unit_select_r), line:125
|vpiName:id_unit_select_r
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[11].id_unit_select_r
|vpiIndex:
\_ref_obj: (i), line:125
|vpiName:i
|vpiRhs:
\_ref_obj: (ti.issue_unit_id), line:125
|vpiName:ti.issue_unit_id
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[11].ti.issue_unit_id
|vpiContAssign:
\_cont_assign: , line:127
|vpiRhs:
\_operation: , line:127
|vpiOpType:32
|vpiOperand:
\_bit_select: (id_inuse), line:127
|vpiName:id_inuse
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[11].id_inuse
|vpiIndex:
\_ref_obj: (i), line:127
|vpiName:i
|vpiOperand:
\_bit_select: (id_unit_select_r), line:127
|vpiName:id_unit_select_r
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[11].id_unit_select_r
|vpiIndex:
\_ref_obj: (i), line:127
|vpiName:i
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[11].i
|vpiOperand:
\_ref_obj: (ti.issue_unit_id), line:127
|vpiName:ti.issue_unit_id
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[11].ti.issue_unit_id
|vpiLhs:
\_bit_select: (id_unit_select), line:127
|vpiName:id_unit_select
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[11].id_unit_select
|vpiIndex:
\_ref_obj: (i), line:127
|vpiName:i
|vpiParameter:
\_parameter: (ALU_UNIT_WB_ID), line:190
|vpiName:ALU_UNIT_WB_ID
|INT:32
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (BRANCH_PREDICTOR_WAYS), line:159
|vpiName:BRANCH_PREDICTOR_WAYS
|INT:9
|vpiParameter:
\_parameter: (BRANCH_TABLE_ENTRIES), line:160
|vpiName:BRANCH_TABLE_ENTRIES
|INT:4
|vpiParameter:
\_parameter: (BRANCH_UNIT_ID), line:195
|vpiName:BRANCH_UNIT_ID
|INT:8
|vpiParameter:
\_parameter: (BUS_ADDR_H), line:107
|vpiName:BUS_ADDR_H
|INT:1
|vpiParameter:
\_parameter: (BUS_ADDR_L), line:106
|vpiName:BUS_ADDR_L
|INT:0
|vpiParameter:
\_parameter: (BUS_BIT_CHECK), line:108
|vpiName:BUS_BIT_CHECK
|INT:1
|vpiParameter:
\_parameter: (BUS_TYPE), line:89
|vpiName:BUS_TYPE
|INT:5
|vpiParameter:
\_parameter: (COUNTER_W), line:42
|vpiName:COUNTER_W
|INT:33
|vpiParameter:
\_parameter: (CPU_ID), line:38
|vpiName:CPU_ID
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_ADDR_WIDTH), line:113
|vpiName:C_M_AXI_ADDR_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_DATA_WIDTH), line:114
|vpiName:C_M_AXI_DATA_WIDTH
|INT:1
|vpiParameter:
\_parameter: (DCACHE_LINES), line:133
|vpiName:DCACHE_LINES
|INT:-2146435073
|vpiParameter:
\_parameter: (DCACHE_LINE_ADDR_W), line:135
|vpiName:DCACHE_LINE_ADDR_W
|INT:1073741824
|vpiParameter:
\_parameter: (DCACHE_LINE_W), line:136
|vpiName:DCACHE_LINE_W
|INT:1342177279
|vpiParameter:
\_parameter: (DCACHE_SUB_LINE_ADDR_W), line:137
|vpiName:DCACHE_SUB_LINE_ADDR_W
|INT:4
|vpiParameter:
\_parameter: (DCACHE_TAG_W), line:138
|vpiName:DCACHE_TAG_W
|INT:1610612736
|vpiParameter:
\_parameter: (DCACHE_WAYS), line:134
|vpiName:DCACHE_WAYS
|INT:4
|vpiParameter:
\_parameter: (DIV_ALGORITHM), line:67
|vpiName:DIV_ALGORITHM
|INT:0
|vpiParameter:
\_parameter: (DIV_UNIT_WB_ID), line:192
|vpiName:DIV_UNIT_WB_ID
|INT:2
|vpiParameter:
\_parameter: (DTLB_DEPTH), line:152
|vpiName:DTLB_DEPTH
|INT:512
|vpiParameter:
\_parameter: (DTLB_WAYS), line:151
|vpiName:DTLB_WAYS
|INT:32
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (ENABLE_M_MODE), line:34
|vpiName:ENABLE_M_MODE
|INT:1
|vpiParameter:
\_parameter: (ENABLE_S_MODE), line:36
|vpiName:ENABLE_S_MODE
|INT:0
|vpiParameter:
\_parameter: (ENABLE_TRACE_INTERFACE), line:172
|vpiName:ENABLE_TRACE_INTERFACE
|INT:2
|vpiParameter:
\_parameter: (FETCH_BUFFER_DEPTH), line:168
|vpiName:FETCH_BUFFER_DEPTH
|INT:512
|vpiParameter:
\_parameter: (FPGA_VENDOR), line:27
|vpiName:FPGA_VENDOR
|STRING:"xilinx"
|vpiParameter:
\_parameter: (GC_UNIT_ID), line:196
|vpiName:GC_UNIT_ID
|INT:4
|vpiParameter:
\_parameter: (ICACHE_LINES), line:121
|vpiName:ICACHE_LINES
|INT:2
|vpiParameter:
\_parameter: (ICACHE_LINE_ADDR_W), line:123
|vpiName:ICACHE_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_LINE_W), line:124
|vpiName:ICACHE_LINE_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_SUB_LINE_ADDR_W), line:125
|vpiName:ICACHE_SUB_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_TAG_W), line:126
|vpiName:ICACHE_TAG_W
|INT:-2147483648
|vpiParameter:
\_parameter: (ICACHE_WAYS), line:122
|vpiName:ICACHE_WAYS
|INT:1
|vpiParameter:
\_parameter: (ITLB_DEPTH), line:146
|vpiName:ITLB_DEPTH
|INT:32
|vpiParameter:
\_parameter: (ITLB_WAYS), line:145
|vpiName:ITLB_WAYS
|INT:4
|vpiParameter:
\_parameter: (L1_CONNECTIONS), line:177
|vpiName:L1_CONNECTIONS
|INT:9
|vpiParameter:
\_parameter: (L1_DCACHE_ID), line:178
|vpiName:L1_DCACHE_ID
|INT:4
|vpiParameter:
\_parameter: (L1_DMMU_ID), line:179
|vpiName:L1_DMMU_ID
|INT:2
|vpiParameter:
\_parameter: (L1_ICACHE_ID), line:180
|vpiName:L1_ICACHE_ID
|INT:19
|vpiParameter:
\_parameter: (L1_IMMU_ID), line:181
|vpiName:L1_IMMU_ID
|INT:0
|vpiParameter:
\_parameter: (LS_UNIT_WB_ID), line:191
|vpiName:LS_UNIT_WB_ID
|INT:1
|vpiParameter:
\_parameter: (MAX_INFLIGHT_COUNT), line:167
|vpiName:MAX_INFLIGHT_COUNT
|INT:19
|vpiParameter:
\_parameter: (MEMORY_ADDR_H), line:103
|vpiName:MEMORY_ADDR_H
|INT:12
|vpiParameter:
\_parameter: (MEMORY_ADDR_L), line:102
|vpiName:MEMORY_ADDR_L
|INT:11
|vpiParameter:
\_parameter: (MEMORY_BIT_CHECK), line:104
|vpiName:MEMORY_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (MUL_UNIT_WB_ID), line:193
|vpiName:MUL_UNIT_WB_ID
|INT:512
|vpiParameter:
\_parameter: (NUM_UNITS), line:188
|vpiName:NUM_UNITS
|INT:2
|vpiParameter:
\_parameter: (NUM_WB_UNITS), line:186
|vpiName:NUM_WB_UNITS
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (RAS_DEPTH), line:161
|vpiName:RAS_DEPTH
|INT:2
|vpiParameter:
\_parameter: (RESET_VEC), line:39
|vpiName:RESET_VEC
|INT:-2147483648
|vpiParameter:
\_parameter: (SCRATCH_ADDR_H), line:99
|vpiName:SCRATCH_ADDR_H
|INT:9
|vpiParameter:
\_parameter: (SCRATCH_ADDR_L), line:98
|vpiName:SCRATCH_ADDR_L
|INT:8
|vpiParameter:
\_parameter: (SCRATCH_BIT_CHECK), line:100
|vpiName:SCRATCH_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (USE_AMO), line:70
|vpiName:USE_AMO
|INT:1
|vpiParameter:
\_parameter: (USE_BRANCH_PREDICTOR), line:158
|vpiName:USE_BRANCH_PREDICTOR
|INT:2
|vpiParameter:
\_parameter: (USE_BUS), line:88
|vpiName:USE_BUS
|INT:4
|vpiParameter:
\_parameter: (USE_DCACHE), line:92
|vpiName:USE_DCACHE
|INT:6
|vpiParameter:
\_parameter: (USE_DIV), line:49
|vpiName:USE_DIV
|INT:1
|vpiParameter:
\_parameter: (USE_DTAG_INVALIDATIONS), line:140
|vpiName:USE_DTAG_INVALIDATIONS
|INT:1879048191
|vpiParameter:
\_parameter: (USE_D_SCRATCH_MEM), line:79
|vpiName:USE_D_SCRATCH_MEM
|INT:3
|vpiParameter:
\_parameter: (USE_ICACHE), line:93
|vpiName:USE_ICACHE
|INT:7
|vpiParameter:
\_parameter: (USE_I_SCRATCH_MEM), line:78
|vpiName:USE_I_SCRATCH_MEM
|INT:2
|vpiParameter:
\_parameter: (USE_MUL), line:48
|vpiName:USE_MUL
|INT:1
|vpiParameter:
\_parameter: (WB_UNITS_WIDTH), line:187
|vpiName:WB_UNITS_WIDTH
|INT:32
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiParameter:
\_parameter: (i), line:122
|vpiName:i
|INT:11
|vpiGenScopeArray:
\_gen_scope_array: (genblk2[12]), line:122, parent:write_back_mux
|vpiName:genblk2[12]
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[12]
|vpiGenScope:
\_gen_scope: , parent:genblk2[12]
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[12]
|vpiProcess:
\_always: , line:123
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:123
|vpiCondition:
\_operation: , line:123
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:123
|vpiName:clk
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[12].clk
|vpiStmt:
\_begin: , line:123
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[12]
|vpiStmt:
\_if_stmt: , line:124
|vpiCondition:
\_bit_select: (id_issued_one_hot), line:124
|vpiName:id_issued_one_hot
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[12].id_issued_one_hot
|vpiIndex:
\_ref_obj: (i), line:124
|vpiName:i
|vpiStmt:
\_assignment: , line:125
|vpiOpType:82
|vpiLhs:
\_bit_select: (id_unit_select_r), line:125
|vpiName:id_unit_select_r
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[12].id_unit_select_r
|vpiIndex:
\_ref_obj: (i), line:125
|vpiName:i
|vpiRhs:
\_ref_obj: (ti.issue_unit_id), line:125
|vpiName:ti.issue_unit_id
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[12].ti.issue_unit_id
|vpiContAssign:
\_cont_assign: , line:127
|vpiRhs:
\_operation: , line:127
|vpiOpType:32
|vpiOperand:
\_bit_select: (id_inuse), line:127
|vpiName:id_inuse
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[12].id_inuse
|vpiIndex:
\_ref_obj: (i), line:127
|vpiName:i
|vpiOperand:
\_bit_select: (id_unit_select_r), line:127
|vpiName:id_unit_select_r
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[12].id_unit_select_r
|vpiIndex:
\_ref_obj: (i), line:127
|vpiName:i
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[12].i
|vpiOperand:
\_ref_obj: (ti.issue_unit_id), line:127
|vpiName:ti.issue_unit_id
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[12].ti.issue_unit_id
|vpiLhs:
\_bit_select: (id_unit_select), line:127
|vpiName:id_unit_select
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[12].id_unit_select
|vpiIndex:
\_ref_obj: (i), line:127
|vpiName:i
|vpiParameter:
\_parameter: (ALU_UNIT_WB_ID), line:190
|vpiName:ALU_UNIT_WB_ID
|INT:32
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (BRANCH_PREDICTOR_WAYS), line:159
|vpiName:BRANCH_PREDICTOR_WAYS
|INT:9
|vpiParameter:
\_parameter: (BRANCH_TABLE_ENTRIES), line:160
|vpiName:BRANCH_TABLE_ENTRIES
|INT:4
|vpiParameter:
\_parameter: (BRANCH_UNIT_ID), line:195
|vpiName:BRANCH_UNIT_ID
|INT:8
|vpiParameter:
\_parameter: (BUS_ADDR_H), line:107
|vpiName:BUS_ADDR_H
|INT:1
|vpiParameter:
\_parameter: (BUS_ADDR_L), line:106
|vpiName:BUS_ADDR_L
|INT:0
|vpiParameter:
\_parameter: (BUS_BIT_CHECK), line:108
|vpiName:BUS_BIT_CHECK
|INT:1
|vpiParameter:
\_parameter: (BUS_TYPE), line:89
|vpiName:BUS_TYPE
|INT:5
|vpiParameter:
\_parameter: (COUNTER_W), line:42
|vpiName:COUNTER_W
|INT:33
|vpiParameter:
\_parameter: (CPU_ID), line:38
|vpiName:CPU_ID
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_ADDR_WIDTH), line:113
|vpiName:C_M_AXI_ADDR_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_DATA_WIDTH), line:114
|vpiName:C_M_AXI_DATA_WIDTH
|INT:1
|vpiParameter:
\_parameter: (DCACHE_LINES), line:133
|vpiName:DCACHE_LINES
|INT:-2146435073
|vpiParameter:
\_parameter: (DCACHE_LINE_ADDR_W), line:135
|vpiName:DCACHE_LINE_ADDR_W
|INT:1073741824
|vpiParameter:
\_parameter: (DCACHE_LINE_W), line:136
|vpiName:DCACHE_LINE_W
|INT:1342177279
|vpiParameter:
\_parameter: (DCACHE_SUB_LINE_ADDR_W), line:137
|vpiName:DCACHE_SUB_LINE_ADDR_W
|INT:4
|vpiParameter:
\_parameter: (DCACHE_TAG_W), line:138
|vpiName:DCACHE_TAG_W
|INT:1610612736
|vpiParameter:
\_parameter: (DCACHE_WAYS), line:134
|vpiName:DCACHE_WAYS
|INT:4
|vpiParameter:
\_parameter: (DIV_ALGORITHM), line:67
|vpiName:DIV_ALGORITHM
|INT:0
|vpiParameter:
\_parameter: (DIV_UNIT_WB_ID), line:192
|vpiName:DIV_UNIT_WB_ID
|INT:2
|vpiParameter:
\_parameter: (DTLB_DEPTH), line:152
|vpiName:DTLB_DEPTH
|INT:512
|vpiParameter:
\_parameter: (DTLB_WAYS), line:151
|vpiName:DTLB_WAYS
|INT:32
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (ENABLE_M_MODE), line:34
|vpiName:ENABLE_M_MODE
|INT:1
|vpiParameter:
\_parameter: (ENABLE_S_MODE), line:36
|vpiName:ENABLE_S_MODE
|INT:0
|vpiParameter:
\_parameter: (ENABLE_TRACE_INTERFACE), line:172
|vpiName:ENABLE_TRACE_INTERFACE
|INT:2
|vpiParameter:
\_parameter: (FETCH_BUFFER_DEPTH), line:168
|vpiName:FETCH_BUFFER_DEPTH
|INT:512
|vpiParameter:
\_parameter: (FPGA_VENDOR), line:27
|vpiName:FPGA_VENDOR
|STRING:"xilinx"
|vpiParameter:
\_parameter: (GC_UNIT_ID), line:196
|vpiName:GC_UNIT_ID
|INT:4
|vpiParameter:
\_parameter: (ICACHE_LINES), line:121
|vpiName:ICACHE_LINES
|INT:2
|vpiParameter:
\_parameter: (ICACHE_LINE_ADDR_W), line:123
|vpiName:ICACHE_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_LINE_W), line:124
|vpiName:ICACHE_LINE_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_SUB_LINE_ADDR_W), line:125
|vpiName:ICACHE_SUB_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_TAG_W), line:126
|vpiName:ICACHE_TAG_W
|INT:-2147483648
|vpiParameter:
\_parameter: (ICACHE_WAYS), line:122
|vpiName:ICACHE_WAYS
|INT:1
|vpiParameter:
\_parameter: (ITLB_DEPTH), line:146
|vpiName:ITLB_DEPTH
|INT:32
|vpiParameter:
\_parameter: (ITLB_WAYS), line:145
|vpiName:ITLB_WAYS
|INT:4
|vpiParameter:
\_parameter: (L1_CONNECTIONS), line:177
|vpiName:L1_CONNECTIONS
|INT:9
|vpiParameter:
\_parameter: (L1_DCACHE_ID), line:178
|vpiName:L1_DCACHE_ID
|INT:4
|vpiParameter:
\_parameter: (L1_DMMU_ID), line:179
|vpiName:L1_DMMU_ID
|INT:2
|vpiParameter:
\_parameter: (L1_ICACHE_ID), line:180
|vpiName:L1_ICACHE_ID
|INT:19
|vpiParameter:
\_parameter: (L1_IMMU_ID), line:181
|vpiName:L1_IMMU_ID
|INT:0
|vpiParameter:
\_parameter: (LS_UNIT_WB_ID), line:191
|vpiName:LS_UNIT_WB_ID
|INT:1
|vpiParameter:
\_parameter: (MAX_INFLIGHT_COUNT), line:167
|vpiName:MAX_INFLIGHT_COUNT
|INT:19
|vpiParameter:
\_parameter: (MEMORY_ADDR_H), line:103
|vpiName:MEMORY_ADDR_H
|INT:12
|vpiParameter:
\_parameter: (MEMORY_ADDR_L), line:102
|vpiName:MEMORY_ADDR_L
|INT:11
|vpiParameter:
\_parameter: (MEMORY_BIT_CHECK), line:104
|vpiName:MEMORY_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (MUL_UNIT_WB_ID), line:193
|vpiName:MUL_UNIT_WB_ID
|INT:512
|vpiParameter:
\_parameter: (NUM_UNITS), line:188
|vpiName:NUM_UNITS
|INT:2
|vpiParameter:
\_parameter: (NUM_WB_UNITS), line:186
|vpiName:NUM_WB_UNITS
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (RAS_DEPTH), line:161
|vpiName:RAS_DEPTH
|INT:2
|vpiParameter:
\_parameter: (RESET_VEC), line:39
|vpiName:RESET_VEC
|INT:-2147483648
|vpiParameter:
\_parameter: (SCRATCH_ADDR_H), line:99
|vpiName:SCRATCH_ADDR_H
|INT:9
|vpiParameter:
\_parameter: (SCRATCH_ADDR_L), line:98
|vpiName:SCRATCH_ADDR_L
|INT:8
|vpiParameter:
\_parameter: (SCRATCH_BIT_CHECK), line:100
|vpiName:SCRATCH_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (USE_AMO), line:70
|vpiName:USE_AMO
|INT:1
|vpiParameter:
\_parameter: (USE_BRANCH_PREDICTOR), line:158
|vpiName:USE_BRANCH_PREDICTOR
|INT:2
|vpiParameter:
\_parameter: (USE_BUS), line:88
|vpiName:USE_BUS
|INT:4
|vpiParameter:
\_parameter: (USE_DCACHE), line:92
|vpiName:USE_DCACHE
|INT:6
|vpiParameter:
\_parameter: (USE_DIV), line:49
|vpiName:USE_DIV
|INT:1
|vpiParameter:
\_parameter: (USE_DTAG_INVALIDATIONS), line:140
|vpiName:USE_DTAG_INVALIDATIONS
|INT:1879048191
|vpiParameter:
\_parameter: (USE_D_SCRATCH_MEM), line:79
|vpiName:USE_D_SCRATCH_MEM
|INT:3
|vpiParameter:
\_parameter: (USE_ICACHE), line:93
|vpiName:USE_ICACHE
|INT:7
|vpiParameter:
\_parameter: (USE_I_SCRATCH_MEM), line:78
|vpiName:USE_I_SCRATCH_MEM
|INT:2
|vpiParameter:
\_parameter: (USE_MUL), line:48
|vpiName:USE_MUL
|INT:1
|vpiParameter:
\_parameter: (WB_UNITS_WIDTH), line:187
|vpiName:WB_UNITS_WIDTH
|INT:32
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiParameter:
\_parameter: (i), line:122
|vpiName:i
|INT:12
|vpiGenScopeArray:
\_gen_scope_array: (genblk2[13]), line:122, parent:write_back_mux
|vpiName:genblk2[13]
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[13]
|vpiGenScope:
\_gen_scope: , parent:genblk2[13]
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[13]
|vpiProcess:
\_always: , line:123
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:123
|vpiCondition:
\_operation: , line:123
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:123
|vpiName:clk
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[13].clk
|vpiStmt:
\_begin: , line:123
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[13]
|vpiStmt:
\_if_stmt: , line:124
|vpiCondition:
\_bit_select: (id_issued_one_hot), line:124
|vpiName:id_issued_one_hot
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[13].id_issued_one_hot
|vpiIndex:
\_ref_obj: (i), line:124
|vpiName:i
|vpiStmt:
\_assignment: , line:125
|vpiOpType:82
|vpiLhs:
\_bit_select: (id_unit_select_r), line:125
|vpiName:id_unit_select_r
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[13].id_unit_select_r
|vpiIndex:
\_ref_obj: (i), line:125
|vpiName:i
|vpiRhs:
\_ref_obj: (ti.issue_unit_id), line:125
|vpiName:ti.issue_unit_id
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[13].ti.issue_unit_id
|vpiContAssign:
\_cont_assign: , line:127
|vpiRhs:
\_operation: , line:127
|vpiOpType:32
|vpiOperand:
\_bit_select: (id_inuse), line:127
|vpiName:id_inuse
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[13].id_inuse
|vpiIndex:
\_ref_obj: (i), line:127
|vpiName:i
|vpiOperand:
\_bit_select: (id_unit_select_r), line:127
|vpiName:id_unit_select_r
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[13].id_unit_select_r
|vpiIndex:
\_ref_obj: (i), line:127
|vpiName:i
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[13].i
|vpiOperand:
\_ref_obj: (ti.issue_unit_id), line:127
|vpiName:ti.issue_unit_id
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[13].ti.issue_unit_id
|vpiLhs:
\_bit_select: (id_unit_select), line:127
|vpiName:id_unit_select
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[13].id_unit_select
|vpiIndex:
\_ref_obj: (i), line:127
|vpiName:i
|vpiParameter:
\_parameter: (ALU_UNIT_WB_ID), line:190
|vpiName:ALU_UNIT_WB_ID
|INT:32
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (BRANCH_PREDICTOR_WAYS), line:159
|vpiName:BRANCH_PREDICTOR_WAYS
|INT:9
|vpiParameter:
\_parameter: (BRANCH_TABLE_ENTRIES), line:160
|vpiName:BRANCH_TABLE_ENTRIES
|INT:4
|vpiParameter:
\_parameter: (BRANCH_UNIT_ID), line:195
|vpiName:BRANCH_UNIT_ID
|INT:8
|vpiParameter:
\_parameter: (BUS_ADDR_H), line:107
|vpiName:BUS_ADDR_H
|INT:1
|vpiParameter:
\_parameter: (BUS_ADDR_L), line:106
|vpiName:BUS_ADDR_L
|INT:0
|vpiParameter:
\_parameter: (BUS_BIT_CHECK), line:108
|vpiName:BUS_BIT_CHECK
|INT:1
|vpiParameter:
\_parameter: (BUS_TYPE), line:89
|vpiName:BUS_TYPE
|INT:5
|vpiParameter:
\_parameter: (COUNTER_W), line:42
|vpiName:COUNTER_W
|INT:33
|vpiParameter:
\_parameter: (CPU_ID), line:38
|vpiName:CPU_ID
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_ADDR_WIDTH), line:113
|vpiName:C_M_AXI_ADDR_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_DATA_WIDTH), line:114
|vpiName:C_M_AXI_DATA_WIDTH
|INT:1
|vpiParameter:
\_parameter: (DCACHE_LINES), line:133
|vpiName:DCACHE_LINES
|INT:-2146435073
|vpiParameter:
\_parameter: (DCACHE_LINE_ADDR_W), line:135
|vpiName:DCACHE_LINE_ADDR_W
|INT:1073741824
|vpiParameter:
\_parameter: (DCACHE_LINE_W), line:136
|vpiName:DCACHE_LINE_W
|INT:1342177279
|vpiParameter:
\_parameter: (DCACHE_SUB_LINE_ADDR_W), line:137
|vpiName:DCACHE_SUB_LINE_ADDR_W
|INT:4
|vpiParameter:
\_parameter: (DCACHE_TAG_W), line:138
|vpiName:DCACHE_TAG_W
|INT:1610612736
|vpiParameter:
\_parameter: (DCACHE_WAYS), line:134
|vpiName:DCACHE_WAYS
|INT:4
|vpiParameter:
\_parameter: (DIV_ALGORITHM), line:67
|vpiName:DIV_ALGORITHM
|INT:0
|vpiParameter:
\_parameter: (DIV_UNIT_WB_ID), line:192
|vpiName:DIV_UNIT_WB_ID
|INT:2
|vpiParameter:
\_parameter: (DTLB_DEPTH), line:152
|vpiName:DTLB_DEPTH
|INT:512
|vpiParameter:
\_parameter: (DTLB_WAYS), line:151
|vpiName:DTLB_WAYS
|INT:32
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (ENABLE_M_MODE), line:34
|vpiName:ENABLE_M_MODE
|INT:1
|vpiParameter:
\_parameter: (ENABLE_S_MODE), line:36
|vpiName:ENABLE_S_MODE
|INT:0
|vpiParameter:
\_parameter: (ENABLE_TRACE_INTERFACE), line:172
|vpiName:ENABLE_TRACE_INTERFACE
|INT:2
|vpiParameter:
\_parameter: (FETCH_BUFFER_DEPTH), line:168
|vpiName:FETCH_BUFFER_DEPTH
|INT:512
|vpiParameter:
\_parameter: (FPGA_VENDOR), line:27
|vpiName:FPGA_VENDOR
|STRING:"xilinx"
|vpiParameter:
\_parameter: (GC_UNIT_ID), line:196
|vpiName:GC_UNIT_ID
|INT:4
|vpiParameter:
\_parameter: (ICACHE_LINES), line:121
|vpiName:ICACHE_LINES
|INT:2
|vpiParameter:
\_parameter: (ICACHE_LINE_ADDR_W), line:123
|vpiName:ICACHE_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_LINE_W), line:124
|vpiName:ICACHE_LINE_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_SUB_LINE_ADDR_W), line:125
|vpiName:ICACHE_SUB_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_TAG_W), line:126
|vpiName:ICACHE_TAG_W
|INT:-2147483648
|vpiParameter:
\_parameter: (ICACHE_WAYS), line:122
|vpiName:ICACHE_WAYS
|INT:1
|vpiParameter:
\_parameter: (ITLB_DEPTH), line:146
|vpiName:ITLB_DEPTH
|INT:32
|vpiParameter:
\_parameter: (ITLB_WAYS), line:145
|vpiName:ITLB_WAYS
|INT:4
|vpiParameter:
\_parameter: (L1_CONNECTIONS), line:177
|vpiName:L1_CONNECTIONS
|INT:9
|vpiParameter:
\_parameter: (L1_DCACHE_ID), line:178
|vpiName:L1_DCACHE_ID
|INT:4
|vpiParameter:
\_parameter: (L1_DMMU_ID), line:179
|vpiName:L1_DMMU_ID
|INT:2
|vpiParameter:
\_parameter: (L1_ICACHE_ID), line:180
|vpiName:L1_ICACHE_ID
|INT:19
|vpiParameter:
\_parameter: (L1_IMMU_ID), line:181
|vpiName:L1_IMMU_ID
|INT:0
|vpiParameter:
\_parameter: (LS_UNIT_WB_ID), line:191
|vpiName:LS_UNIT_WB_ID
|INT:1
|vpiParameter:
\_parameter: (MAX_INFLIGHT_COUNT), line:167
|vpiName:MAX_INFLIGHT_COUNT
|INT:19
|vpiParameter:
\_parameter: (MEMORY_ADDR_H), line:103
|vpiName:MEMORY_ADDR_H
|INT:12
|vpiParameter:
\_parameter: (MEMORY_ADDR_L), line:102
|vpiName:MEMORY_ADDR_L
|INT:11
|vpiParameter:
\_parameter: (MEMORY_BIT_CHECK), line:104
|vpiName:MEMORY_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (MUL_UNIT_WB_ID), line:193
|vpiName:MUL_UNIT_WB_ID
|INT:512
|vpiParameter:
\_parameter: (NUM_UNITS), line:188
|vpiName:NUM_UNITS
|INT:2
|vpiParameter:
\_parameter: (NUM_WB_UNITS), line:186
|vpiName:NUM_WB_UNITS
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (RAS_DEPTH), line:161
|vpiName:RAS_DEPTH
|INT:2
|vpiParameter:
\_parameter: (RESET_VEC), line:39
|vpiName:RESET_VEC
|INT:-2147483648
|vpiParameter:
\_parameter: (SCRATCH_ADDR_H), line:99
|vpiName:SCRATCH_ADDR_H
|INT:9
|vpiParameter:
\_parameter: (SCRATCH_ADDR_L), line:98
|vpiName:SCRATCH_ADDR_L
|INT:8
|vpiParameter:
\_parameter: (SCRATCH_BIT_CHECK), line:100
|vpiName:SCRATCH_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (USE_AMO), line:70
|vpiName:USE_AMO
|INT:1
|vpiParameter:
\_parameter: (USE_BRANCH_PREDICTOR), line:158
|vpiName:USE_BRANCH_PREDICTOR
|INT:2
|vpiParameter:
\_parameter: (USE_BUS), line:88
|vpiName:USE_BUS
|INT:4
|vpiParameter:
\_parameter: (USE_DCACHE), line:92
|vpiName:USE_DCACHE
|INT:6
|vpiParameter:
\_parameter: (USE_DIV), line:49
|vpiName:USE_DIV
|INT:1
|vpiParameter:
\_parameter: (USE_DTAG_INVALIDATIONS), line:140
|vpiName:USE_DTAG_INVALIDATIONS
|INT:1879048191
|vpiParameter:
\_parameter: (USE_D_SCRATCH_MEM), line:79
|vpiName:USE_D_SCRATCH_MEM
|INT:3
|vpiParameter:
\_parameter: (USE_ICACHE), line:93
|vpiName:USE_ICACHE
|INT:7
|vpiParameter:
\_parameter: (USE_I_SCRATCH_MEM), line:78
|vpiName:USE_I_SCRATCH_MEM
|INT:2
|vpiParameter:
\_parameter: (USE_MUL), line:48
|vpiName:USE_MUL
|INT:1
|vpiParameter:
\_parameter: (WB_UNITS_WIDTH), line:187
|vpiName:WB_UNITS_WIDTH
|INT:32
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiParameter:
\_parameter: (i), line:122
|vpiName:i
|INT:13
|vpiGenScopeArray:
\_gen_scope_array: (genblk2[14]), line:122, parent:write_back_mux
|vpiName:genblk2[14]
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[14]
|vpiGenScope:
\_gen_scope: , parent:genblk2[14]
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[14]
|vpiProcess:
\_always: , line:123
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:123
|vpiCondition:
\_operation: , line:123
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:123
|vpiName:clk
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[14].clk
|vpiStmt:
\_begin: , line:123
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[14]
|vpiStmt:
\_if_stmt: , line:124
|vpiCondition:
\_bit_select: (id_issued_one_hot), line:124
|vpiName:id_issued_one_hot
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[14].id_issued_one_hot
|vpiIndex:
\_ref_obj: (i), line:124
|vpiName:i
|vpiStmt:
\_assignment: , line:125
|vpiOpType:82
|vpiLhs:
\_bit_select: (id_unit_select_r), line:125
|vpiName:id_unit_select_r
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[14].id_unit_select_r
|vpiIndex:
\_ref_obj: (i), line:125
|vpiName:i
|vpiRhs:
\_ref_obj: (ti.issue_unit_id), line:125
|vpiName:ti.issue_unit_id
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[14].ti.issue_unit_id
|vpiContAssign:
\_cont_assign: , line:127
|vpiRhs:
\_operation: , line:127
|vpiOpType:32
|vpiOperand:
\_bit_select: (id_inuse), line:127
|vpiName:id_inuse
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[14].id_inuse
|vpiIndex:
\_ref_obj: (i), line:127
|vpiName:i
|vpiOperand:
\_bit_select: (id_unit_select_r), line:127
|vpiName:id_unit_select_r
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[14].id_unit_select_r
|vpiIndex:
\_ref_obj: (i), line:127
|vpiName:i
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[14].i
|vpiOperand:
\_ref_obj: (ti.issue_unit_id), line:127
|vpiName:ti.issue_unit_id
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[14].ti.issue_unit_id
|vpiLhs:
\_bit_select: (id_unit_select), line:127
|vpiName:id_unit_select
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[14].id_unit_select
|vpiIndex:
\_ref_obj: (i), line:127
|vpiName:i
|vpiParameter:
\_parameter: (ALU_UNIT_WB_ID), line:190
|vpiName:ALU_UNIT_WB_ID
|INT:32
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (BRANCH_PREDICTOR_WAYS), line:159
|vpiName:BRANCH_PREDICTOR_WAYS
|INT:9
|vpiParameter:
\_parameter: (BRANCH_TABLE_ENTRIES), line:160
|vpiName:BRANCH_TABLE_ENTRIES
|INT:4
|vpiParameter:
\_parameter: (BRANCH_UNIT_ID), line:195
|vpiName:BRANCH_UNIT_ID
|INT:8
|vpiParameter:
\_parameter: (BUS_ADDR_H), line:107
|vpiName:BUS_ADDR_H
|INT:1
|vpiParameter:
\_parameter: (BUS_ADDR_L), line:106
|vpiName:BUS_ADDR_L
|INT:0
|vpiParameter:
\_parameter: (BUS_BIT_CHECK), line:108
|vpiName:BUS_BIT_CHECK
|INT:1
|vpiParameter:
\_parameter: (BUS_TYPE), line:89
|vpiName:BUS_TYPE
|INT:5
|vpiParameter:
\_parameter: (COUNTER_W), line:42
|vpiName:COUNTER_W
|INT:33
|vpiParameter:
\_parameter: (CPU_ID), line:38
|vpiName:CPU_ID
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_ADDR_WIDTH), line:113
|vpiName:C_M_AXI_ADDR_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_DATA_WIDTH), line:114
|vpiName:C_M_AXI_DATA_WIDTH
|INT:1
|vpiParameter:
\_parameter: (DCACHE_LINES), line:133
|vpiName:DCACHE_LINES
|INT:-2146435073
|vpiParameter:
\_parameter: (DCACHE_LINE_ADDR_W), line:135
|vpiName:DCACHE_LINE_ADDR_W
|INT:1073741824
|vpiParameter:
\_parameter: (DCACHE_LINE_W), line:136
|vpiName:DCACHE_LINE_W
|INT:1342177279
|vpiParameter:
\_parameter: (DCACHE_SUB_LINE_ADDR_W), line:137
|vpiName:DCACHE_SUB_LINE_ADDR_W
|INT:4
|vpiParameter:
\_parameter: (DCACHE_TAG_W), line:138
|vpiName:DCACHE_TAG_W
|INT:1610612736
|vpiParameter:
\_parameter: (DCACHE_WAYS), line:134
|vpiName:DCACHE_WAYS
|INT:4
|vpiParameter:
\_parameter: (DIV_ALGORITHM), line:67
|vpiName:DIV_ALGORITHM
|INT:0
|vpiParameter:
\_parameter: (DIV_UNIT_WB_ID), line:192
|vpiName:DIV_UNIT_WB_ID
|INT:2
|vpiParameter:
\_parameter: (DTLB_DEPTH), line:152
|vpiName:DTLB_DEPTH
|INT:512
|vpiParameter:
\_parameter: (DTLB_WAYS), line:151
|vpiName:DTLB_WAYS
|INT:32
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (ENABLE_M_MODE), line:34
|vpiName:ENABLE_M_MODE
|INT:1
|vpiParameter:
\_parameter: (ENABLE_S_MODE), line:36
|vpiName:ENABLE_S_MODE
|INT:0
|vpiParameter:
\_parameter: (ENABLE_TRACE_INTERFACE), line:172
|vpiName:ENABLE_TRACE_INTERFACE
|INT:2
|vpiParameter:
\_parameter: (FETCH_BUFFER_DEPTH), line:168
|vpiName:FETCH_BUFFER_DEPTH
|INT:512
|vpiParameter:
\_parameter: (FPGA_VENDOR), line:27
|vpiName:FPGA_VENDOR
|STRING:"xilinx"
|vpiParameter:
\_parameter: (GC_UNIT_ID), line:196
|vpiName:GC_UNIT_ID
|INT:4
|vpiParameter:
\_parameter: (ICACHE_LINES), line:121
|vpiName:ICACHE_LINES
|INT:2
|vpiParameter:
\_parameter: (ICACHE_LINE_ADDR_W), line:123
|vpiName:ICACHE_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_LINE_W), line:124
|vpiName:ICACHE_LINE_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_SUB_LINE_ADDR_W), line:125
|vpiName:ICACHE_SUB_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_TAG_W), line:126
|vpiName:ICACHE_TAG_W
|INT:-2147483648
|vpiParameter:
\_parameter: (ICACHE_WAYS), line:122
|vpiName:ICACHE_WAYS
|INT:1
|vpiParameter:
\_parameter: (ITLB_DEPTH), line:146
|vpiName:ITLB_DEPTH
|INT:32
|vpiParameter:
\_parameter: (ITLB_WAYS), line:145
|vpiName:ITLB_WAYS
|INT:4
|vpiParameter:
\_parameter: (L1_CONNECTIONS), line:177
|vpiName:L1_CONNECTIONS
|INT:9
|vpiParameter:
\_parameter: (L1_DCACHE_ID), line:178
|vpiName:L1_DCACHE_ID
|INT:4
|vpiParameter:
\_parameter: (L1_DMMU_ID), line:179
|vpiName:L1_DMMU_ID
|INT:2
|vpiParameter:
\_parameter: (L1_ICACHE_ID), line:180
|vpiName:L1_ICACHE_ID
|INT:19
|vpiParameter:
\_parameter: (L1_IMMU_ID), line:181
|vpiName:L1_IMMU_ID
|INT:0
|vpiParameter:
\_parameter: (LS_UNIT_WB_ID), line:191
|vpiName:LS_UNIT_WB_ID
|INT:1
|vpiParameter:
\_parameter: (MAX_INFLIGHT_COUNT), line:167
|vpiName:MAX_INFLIGHT_COUNT
|INT:19
|vpiParameter:
\_parameter: (MEMORY_ADDR_H), line:103
|vpiName:MEMORY_ADDR_H
|INT:12
|vpiParameter:
\_parameter: (MEMORY_ADDR_L), line:102
|vpiName:MEMORY_ADDR_L
|INT:11
|vpiParameter:
\_parameter: (MEMORY_BIT_CHECK), line:104
|vpiName:MEMORY_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (MUL_UNIT_WB_ID), line:193
|vpiName:MUL_UNIT_WB_ID
|INT:512
|vpiParameter:
\_parameter: (NUM_UNITS), line:188
|vpiName:NUM_UNITS
|INT:2
|vpiParameter:
\_parameter: (NUM_WB_UNITS), line:186
|vpiName:NUM_WB_UNITS
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (RAS_DEPTH), line:161
|vpiName:RAS_DEPTH
|INT:2
|vpiParameter:
\_parameter: (RESET_VEC), line:39
|vpiName:RESET_VEC
|INT:-2147483648
|vpiParameter:
\_parameter: (SCRATCH_ADDR_H), line:99
|vpiName:SCRATCH_ADDR_H
|INT:9
|vpiParameter:
\_parameter: (SCRATCH_ADDR_L), line:98
|vpiName:SCRATCH_ADDR_L
|INT:8
|vpiParameter:
\_parameter: (SCRATCH_BIT_CHECK), line:100
|vpiName:SCRATCH_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (USE_AMO), line:70
|vpiName:USE_AMO
|INT:1
|vpiParameter:
\_parameter: (USE_BRANCH_PREDICTOR), line:158
|vpiName:USE_BRANCH_PREDICTOR
|INT:2
|vpiParameter:
\_parameter: (USE_BUS), line:88
|vpiName:USE_BUS
|INT:4
|vpiParameter:
\_parameter: (USE_DCACHE), line:92
|vpiName:USE_DCACHE
|INT:6
|vpiParameter:
\_parameter: (USE_DIV), line:49
|vpiName:USE_DIV
|INT:1
|vpiParameter:
\_parameter: (USE_DTAG_INVALIDATIONS), line:140
|vpiName:USE_DTAG_INVALIDATIONS
|INT:1879048191
|vpiParameter:
\_parameter: (USE_D_SCRATCH_MEM), line:79
|vpiName:USE_D_SCRATCH_MEM
|INT:3
|vpiParameter:
\_parameter: (USE_ICACHE), line:93
|vpiName:USE_ICACHE
|INT:7
|vpiParameter:
\_parameter: (USE_I_SCRATCH_MEM), line:78
|vpiName:USE_I_SCRATCH_MEM
|INT:2
|vpiParameter:
\_parameter: (USE_MUL), line:48
|vpiName:USE_MUL
|INT:1
|vpiParameter:
\_parameter: (WB_UNITS_WIDTH), line:187
|vpiName:WB_UNITS_WIDTH
|INT:32
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiParameter:
\_parameter: (i), line:122
|vpiName:i
|INT:14
|vpiGenScopeArray:
\_gen_scope_array: (genblk2[15]), line:122, parent:write_back_mux
|vpiName:genblk2[15]
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[15]
|vpiGenScope:
\_gen_scope: , parent:genblk2[15]
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[15]
|vpiProcess:
\_always: , line:123
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:123
|vpiCondition:
\_operation: , line:123
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:123
|vpiName:clk
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[15].clk
|vpiStmt:
\_begin: , line:123
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[15]
|vpiStmt:
\_if_stmt: , line:124
|vpiCondition:
\_bit_select: (id_issued_one_hot), line:124
|vpiName:id_issued_one_hot
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[15].id_issued_one_hot
|vpiIndex:
\_ref_obj: (i), line:124
|vpiName:i
|vpiStmt:
\_assignment: , line:125
|vpiOpType:82
|vpiLhs:
\_bit_select: (id_unit_select_r), line:125
|vpiName:id_unit_select_r
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[15].id_unit_select_r
|vpiIndex:
\_ref_obj: (i), line:125
|vpiName:i
|vpiRhs:
\_ref_obj: (ti.issue_unit_id), line:125
|vpiName:ti.issue_unit_id
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[15].ti.issue_unit_id
|vpiContAssign:
\_cont_assign: , line:127
|vpiRhs:
\_operation: , line:127
|vpiOpType:32
|vpiOperand:
\_bit_select: (id_inuse), line:127
|vpiName:id_inuse
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[15].id_inuse
|vpiIndex:
\_ref_obj: (i), line:127
|vpiName:i
|vpiOperand:
\_bit_select: (id_unit_select_r), line:127
|vpiName:id_unit_select_r
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[15].id_unit_select_r
|vpiIndex:
\_ref_obj: (i), line:127
|vpiName:i
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[15].i
|vpiOperand:
\_ref_obj: (ti.issue_unit_id), line:127
|vpiName:ti.issue_unit_id
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[15].ti.issue_unit_id
|vpiLhs:
\_bit_select: (id_unit_select), line:127
|vpiName:id_unit_select
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[15].id_unit_select
|vpiIndex:
\_ref_obj: (i), line:127
|vpiName:i
|vpiParameter:
\_parameter: (ALU_UNIT_WB_ID), line:190
|vpiName:ALU_UNIT_WB_ID
|INT:32
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (BRANCH_PREDICTOR_WAYS), line:159
|vpiName:BRANCH_PREDICTOR_WAYS
|INT:9
|vpiParameter:
\_parameter: (BRANCH_TABLE_ENTRIES), line:160
|vpiName:BRANCH_TABLE_ENTRIES
|INT:4
|vpiParameter:
\_parameter: (BRANCH_UNIT_ID), line:195
|vpiName:BRANCH_UNIT_ID
|INT:8
|vpiParameter:
\_parameter: (BUS_ADDR_H), line:107
|vpiName:BUS_ADDR_H
|INT:1
|vpiParameter:
\_parameter: (BUS_ADDR_L), line:106
|vpiName:BUS_ADDR_L
|INT:0
|vpiParameter:
\_parameter: (BUS_BIT_CHECK), line:108
|vpiName:BUS_BIT_CHECK
|INT:1
|vpiParameter:
\_parameter: (BUS_TYPE), line:89
|vpiName:BUS_TYPE
|INT:5
|vpiParameter:
\_parameter: (COUNTER_W), line:42
|vpiName:COUNTER_W
|INT:33
|vpiParameter:
\_parameter: (CPU_ID), line:38
|vpiName:CPU_ID
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_ADDR_WIDTH), line:113
|vpiName:C_M_AXI_ADDR_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_DATA_WIDTH), line:114
|vpiName:C_M_AXI_DATA_WIDTH
|INT:1
|vpiParameter:
\_parameter: (DCACHE_LINES), line:133
|vpiName:DCACHE_LINES
|INT:-2146435073
|vpiParameter:
\_parameter: (DCACHE_LINE_ADDR_W), line:135
|vpiName:DCACHE_LINE_ADDR_W
|INT:1073741824
|vpiParameter:
\_parameter: (DCACHE_LINE_W), line:136
|vpiName:DCACHE_LINE_W
|INT:1342177279
|vpiParameter:
\_parameter: (DCACHE_SUB_LINE_ADDR_W), line:137
|vpiName:DCACHE_SUB_LINE_ADDR_W
|INT:4
|vpiParameter:
\_parameter: (DCACHE_TAG_W), line:138
|vpiName:DCACHE_TAG_W
|INT:1610612736
|vpiParameter:
\_parameter: (DCACHE_WAYS), line:134
|vpiName:DCACHE_WAYS
|INT:4
|vpiParameter:
\_parameter: (DIV_ALGORITHM), line:67
|vpiName:DIV_ALGORITHM
|INT:0
|vpiParameter:
\_parameter: (DIV_UNIT_WB_ID), line:192
|vpiName:DIV_UNIT_WB_ID
|INT:2
|vpiParameter:
\_parameter: (DTLB_DEPTH), line:152
|vpiName:DTLB_DEPTH
|INT:512
|vpiParameter:
\_parameter: (DTLB_WAYS), line:151
|vpiName:DTLB_WAYS
|INT:32
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (ENABLE_M_MODE), line:34
|vpiName:ENABLE_M_MODE
|INT:1
|vpiParameter:
\_parameter: (ENABLE_S_MODE), line:36
|vpiName:ENABLE_S_MODE
|INT:0
|vpiParameter:
\_parameter: (ENABLE_TRACE_INTERFACE), line:172
|vpiName:ENABLE_TRACE_INTERFACE
|INT:2
|vpiParameter:
\_parameter: (FETCH_BUFFER_DEPTH), line:168
|vpiName:FETCH_BUFFER_DEPTH
|INT:512
|vpiParameter:
\_parameter: (FPGA_VENDOR), line:27
|vpiName:FPGA_VENDOR
|STRING:"xilinx"
|vpiParameter:
\_parameter: (GC_UNIT_ID), line:196
|vpiName:GC_UNIT_ID
|INT:4
|vpiParameter:
\_parameter: (ICACHE_LINES), line:121
|vpiName:ICACHE_LINES
|INT:2
|vpiParameter:
\_parameter: (ICACHE_LINE_ADDR_W), line:123
|vpiName:ICACHE_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_LINE_W), line:124
|vpiName:ICACHE_LINE_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_SUB_LINE_ADDR_W), line:125
|vpiName:ICACHE_SUB_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_TAG_W), line:126
|vpiName:ICACHE_TAG_W
|INT:-2147483648
|vpiParameter:
\_parameter: (ICACHE_WAYS), line:122
|vpiName:ICACHE_WAYS
|INT:1
|vpiParameter:
\_parameter: (ITLB_DEPTH), line:146
|vpiName:ITLB_DEPTH
|INT:32
|vpiParameter:
\_parameter: (ITLB_WAYS), line:145
|vpiName:ITLB_WAYS
|INT:4
|vpiParameter:
\_parameter: (L1_CONNECTIONS), line:177
|vpiName:L1_CONNECTIONS
|INT:9
|vpiParameter:
\_parameter: (L1_DCACHE_ID), line:178
|vpiName:L1_DCACHE_ID
|INT:4
|vpiParameter:
\_parameter: (L1_DMMU_ID), line:179
|vpiName:L1_DMMU_ID
|INT:2
|vpiParameter:
\_parameter: (L1_ICACHE_ID), line:180
|vpiName:L1_ICACHE_ID
|INT:19
|vpiParameter:
\_parameter: (L1_IMMU_ID), line:181
|vpiName:L1_IMMU_ID
|INT:0
|vpiParameter:
\_parameter: (LS_UNIT_WB_ID), line:191
|vpiName:LS_UNIT_WB_ID
|INT:1
|vpiParameter:
\_parameter: (MAX_INFLIGHT_COUNT), line:167
|vpiName:MAX_INFLIGHT_COUNT
|INT:19
|vpiParameter:
\_parameter: (MEMORY_ADDR_H), line:103
|vpiName:MEMORY_ADDR_H
|INT:12
|vpiParameter:
\_parameter: (MEMORY_ADDR_L), line:102
|vpiName:MEMORY_ADDR_L
|INT:11
|vpiParameter:
\_parameter: (MEMORY_BIT_CHECK), line:104
|vpiName:MEMORY_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (MUL_UNIT_WB_ID), line:193
|vpiName:MUL_UNIT_WB_ID
|INT:512
|vpiParameter:
\_parameter: (NUM_UNITS), line:188
|vpiName:NUM_UNITS
|INT:2
|vpiParameter:
\_parameter: (NUM_WB_UNITS), line:186
|vpiName:NUM_WB_UNITS
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (RAS_DEPTH), line:161
|vpiName:RAS_DEPTH
|INT:2
|vpiParameter:
\_parameter: (RESET_VEC), line:39
|vpiName:RESET_VEC
|INT:-2147483648
|vpiParameter:
\_parameter: (SCRATCH_ADDR_H), line:99
|vpiName:SCRATCH_ADDR_H
|INT:9
|vpiParameter:
\_parameter: (SCRATCH_ADDR_L), line:98
|vpiName:SCRATCH_ADDR_L
|INT:8
|vpiParameter:
\_parameter: (SCRATCH_BIT_CHECK), line:100
|vpiName:SCRATCH_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (USE_AMO), line:70
|vpiName:USE_AMO
|INT:1
|vpiParameter:
\_parameter: (USE_BRANCH_PREDICTOR), line:158
|vpiName:USE_BRANCH_PREDICTOR
|INT:2
|vpiParameter:
\_parameter: (USE_BUS), line:88
|vpiName:USE_BUS
|INT:4
|vpiParameter:
\_parameter: (USE_DCACHE), line:92
|vpiName:USE_DCACHE
|INT:6
|vpiParameter:
\_parameter: (USE_DIV), line:49
|vpiName:USE_DIV
|INT:1
|vpiParameter:
\_parameter: (USE_DTAG_INVALIDATIONS), line:140
|vpiName:USE_DTAG_INVALIDATIONS
|INT:1879048191
|vpiParameter:
\_parameter: (USE_D_SCRATCH_MEM), line:79
|vpiName:USE_D_SCRATCH_MEM
|INT:3
|vpiParameter:
\_parameter: (USE_ICACHE), line:93
|vpiName:USE_ICACHE
|INT:7
|vpiParameter:
\_parameter: (USE_I_SCRATCH_MEM), line:78
|vpiName:USE_I_SCRATCH_MEM
|INT:2
|vpiParameter:
\_parameter: (USE_MUL), line:48
|vpiName:USE_MUL
|INT:1
|vpiParameter:
\_parameter: (WB_UNITS_WIDTH), line:187
|vpiName:WB_UNITS_WIDTH
|INT:32
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiParameter:
\_parameter: (i), line:122
|vpiName:i
|INT:15
|vpiGenScopeArray:
\_gen_scope_array: (genblk2[16]), line:122, parent:write_back_mux
|vpiName:genblk2[16]
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[16]
|vpiGenScope:
\_gen_scope: , parent:genblk2[16]
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[16]
|vpiProcess:
\_always: , line:123
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:123
|vpiCondition:
\_operation: , line:123
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:123
|vpiName:clk
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[16].clk
|vpiStmt:
\_begin: , line:123
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[16]
|vpiStmt:
\_if_stmt: , line:124
|vpiCondition:
\_bit_select: (id_issued_one_hot), line:124
|vpiName:id_issued_one_hot
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[16].id_issued_one_hot
|vpiIndex:
\_ref_obj: (i), line:124
|vpiName:i
|vpiStmt:
\_assignment: , line:125
|vpiOpType:82
|vpiLhs:
\_bit_select: (id_unit_select_r), line:125
|vpiName:id_unit_select_r
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[16].id_unit_select_r
|vpiIndex:
\_ref_obj: (i), line:125
|vpiName:i
|vpiRhs:
\_ref_obj: (ti.issue_unit_id), line:125
|vpiName:ti.issue_unit_id
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[16].ti.issue_unit_id
|vpiContAssign:
\_cont_assign: , line:127
|vpiRhs:
\_operation: , line:127
|vpiOpType:32
|vpiOperand:
\_bit_select: (id_inuse), line:127
|vpiName:id_inuse
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[16].id_inuse
|vpiIndex:
\_ref_obj: (i), line:127
|vpiName:i
|vpiOperand:
\_bit_select: (id_unit_select_r), line:127
|vpiName:id_unit_select_r
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[16].id_unit_select_r
|vpiIndex:
\_ref_obj: (i), line:127
|vpiName:i
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[16].i
|vpiOperand:
\_ref_obj: (ti.issue_unit_id), line:127
|vpiName:ti.issue_unit_id
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[16].ti.issue_unit_id
|vpiLhs:
\_bit_select: (id_unit_select), line:127
|vpiName:id_unit_select
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[16].id_unit_select
|vpiIndex:
\_ref_obj: (i), line:127
|vpiName:i
|vpiParameter:
\_parameter: (ALU_UNIT_WB_ID), line:190
|vpiName:ALU_UNIT_WB_ID
|INT:32
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (BRANCH_PREDICTOR_WAYS), line:159
|vpiName:BRANCH_PREDICTOR_WAYS
|INT:9
|vpiParameter:
\_parameter: (BRANCH_TABLE_ENTRIES), line:160
|vpiName:BRANCH_TABLE_ENTRIES
|INT:4
|vpiParameter:
\_parameter: (BRANCH_UNIT_ID), line:195
|vpiName:BRANCH_UNIT_ID
|INT:8
|vpiParameter:
\_parameter: (BUS_ADDR_H), line:107
|vpiName:BUS_ADDR_H
|INT:1
|vpiParameter:
\_parameter: (BUS_ADDR_L), line:106
|vpiName:BUS_ADDR_L
|INT:0
|vpiParameter:
\_parameter: (BUS_BIT_CHECK), line:108
|vpiName:BUS_BIT_CHECK
|INT:1
|vpiParameter:
\_parameter: (BUS_TYPE), line:89
|vpiName:BUS_TYPE
|INT:5
|vpiParameter:
\_parameter: (COUNTER_W), line:42
|vpiName:COUNTER_W
|INT:33
|vpiParameter:
\_parameter: (CPU_ID), line:38
|vpiName:CPU_ID
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_ADDR_WIDTH), line:113
|vpiName:C_M_AXI_ADDR_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_DATA_WIDTH), line:114
|vpiName:C_M_AXI_DATA_WIDTH
|INT:1
|vpiParameter:
\_parameter: (DCACHE_LINES), line:133
|vpiName:DCACHE_LINES
|INT:-2146435073
|vpiParameter:
\_parameter: (DCACHE_LINE_ADDR_W), line:135
|vpiName:DCACHE_LINE_ADDR_W
|INT:1073741824
|vpiParameter:
\_parameter: (DCACHE_LINE_W), line:136
|vpiName:DCACHE_LINE_W
|INT:1342177279
|vpiParameter:
\_parameter: (DCACHE_SUB_LINE_ADDR_W), line:137
|vpiName:DCACHE_SUB_LINE_ADDR_W
|INT:4
|vpiParameter:
\_parameter: (DCACHE_TAG_W), line:138
|vpiName:DCACHE_TAG_W
|INT:1610612736
|vpiParameter:
\_parameter: (DCACHE_WAYS), line:134
|vpiName:DCACHE_WAYS
|INT:4
|vpiParameter:
\_parameter: (DIV_ALGORITHM), line:67
|vpiName:DIV_ALGORITHM
|INT:0
|vpiParameter:
\_parameter: (DIV_UNIT_WB_ID), line:192
|vpiName:DIV_UNIT_WB_ID
|INT:2
|vpiParameter:
\_parameter: (DTLB_DEPTH), line:152
|vpiName:DTLB_DEPTH
|INT:512
|vpiParameter:
\_parameter: (DTLB_WAYS), line:151
|vpiName:DTLB_WAYS
|INT:32
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (ENABLE_M_MODE), line:34
|vpiName:ENABLE_M_MODE
|INT:1
|vpiParameter:
\_parameter: (ENABLE_S_MODE), line:36
|vpiName:ENABLE_S_MODE
|INT:0
|vpiParameter:
\_parameter: (ENABLE_TRACE_INTERFACE), line:172
|vpiName:ENABLE_TRACE_INTERFACE
|INT:2
|vpiParameter:
\_parameter: (FETCH_BUFFER_DEPTH), line:168
|vpiName:FETCH_BUFFER_DEPTH
|INT:512
|vpiParameter:
\_parameter: (FPGA_VENDOR), line:27
|vpiName:FPGA_VENDOR
|STRING:"xilinx"
|vpiParameter:
\_parameter: (GC_UNIT_ID), line:196
|vpiName:GC_UNIT_ID
|INT:4
|vpiParameter:
\_parameter: (ICACHE_LINES), line:121
|vpiName:ICACHE_LINES
|INT:2
|vpiParameter:
\_parameter: (ICACHE_LINE_ADDR_W), line:123
|vpiName:ICACHE_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_LINE_W), line:124
|vpiName:ICACHE_LINE_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_SUB_LINE_ADDR_W), line:125
|vpiName:ICACHE_SUB_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_TAG_W), line:126
|vpiName:ICACHE_TAG_W
|INT:-2147483648
|vpiParameter:
\_parameter: (ICACHE_WAYS), line:122
|vpiName:ICACHE_WAYS
|INT:1
|vpiParameter:
\_parameter: (ITLB_DEPTH), line:146
|vpiName:ITLB_DEPTH
|INT:32
|vpiParameter:
\_parameter: (ITLB_WAYS), line:145
|vpiName:ITLB_WAYS
|INT:4
|vpiParameter:
\_parameter: (L1_CONNECTIONS), line:177
|vpiName:L1_CONNECTIONS
|INT:9
|vpiParameter:
\_parameter: (L1_DCACHE_ID), line:178
|vpiName:L1_DCACHE_ID
|INT:4
|vpiParameter:
\_parameter: (L1_DMMU_ID), line:179
|vpiName:L1_DMMU_ID
|INT:2
|vpiParameter:
\_parameter: (L1_ICACHE_ID), line:180
|vpiName:L1_ICACHE_ID
|INT:19
|vpiParameter:
\_parameter: (L1_IMMU_ID), line:181
|vpiName:L1_IMMU_ID
|INT:0
|vpiParameter:
\_parameter: (LS_UNIT_WB_ID), line:191
|vpiName:LS_UNIT_WB_ID
|INT:1
|vpiParameter:
\_parameter: (MAX_INFLIGHT_COUNT), line:167
|vpiName:MAX_INFLIGHT_COUNT
|INT:19
|vpiParameter:
\_parameter: (MEMORY_ADDR_H), line:103
|vpiName:MEMORY_ADDR_H
|INT:12
|vpiParameter:
\_parameter: (MEMORY_ADDR_L), line:102
|vpiName:MEMORY_ADDR_L
|INT:11
|vpiParameter:
\_parameter: (MEMORY_BIT_CHECK), line:104
|vpiName:MEMORY_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (MUL_UNIT_WB_ID), line:193
|vpiName:MUL_UNIT_WB_ID
|INT:512
|vpiParameter:
\_parameter: (NUM_UNITS), line:188
|vpiName:NUM_UNITS
|INT:2
|vpiParameter:
\_parameter: (NUM_WB_UNITS), line:186
|vpiName:NUM_WB_UNITS
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (RAS_DEPTH), line:161
|vpiName:RAS_DEPTH
|INT:2
|vpiParameter:
\_parameter: (RESET_VEC), line:39
|vpiName:RESET_VEC
|INT:-2147483648
|vpiParameter:
\_parameter: (SCRATCH_ADDR_H), line:99
|vpiName:SCRATCH_ADDR_H
|INT:9
|vpiParameter:
\_parameter: (SCRATCH_ADDR_L), line:98
|vpiName:SCRATCH_ADDR_L
|INT:8
|vpiParameter:
\_parameter: (SCRATCH_BIT_CHECK), line:100
|vpiName:SCRATCH_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (USE_AMO), line:70
|vpiName:USE_AMO
|INT:1
|vpiParameter:
\_parameter: (USE_BRANCH_PREDICTOR), line:158
|vpiName:USE_BRANCH_PREDICTOR
|INT:2
|vpiParameter:
\_parameter: (USE_BUS), line:88
|vpiName:USE_BUS
|INT:4
|vpiParameter:
\_parameter: (USE_DCACHE), line:92
|vpiName:USE_DCACHE
|INT:6
|vpiParameter:
\_parameter: (USE_DIV), line:49
|vpiName:USE_DIV
|INT:1
|vpiParameter:
\_parameter: (USE_DTAG_INVALIDATIONS), line:140
|vpiName:USE_DTAG_INVALIDATIONS
|INT:1879048191
|vpiParameter:
\_parameter: (USE_D_SCRATCH_MEM), line:79
|vpiName:USE_D_SCRATCH_MEM
|INT:3
|vpiParameter:
\_parameter: (USE_ICACHE), line:93
|vpiName:USE_ICACHE
|INT:7
|vpiParameter:
\_parameter: (USE_I_SCRATCH_MEM), line:78
|vpiName:USE_I_SCRATCH_MEM
|INT:2
|vpiParameter:
\_parameter: (USE_MUL), line:48
|vpiName:USE_MUL
|INT:1
|vpiParameter:
\_parameter: (WB_UNITS_WIDTH), line:187
|vpiName:WB_UNITS_WIDTH
|INT:32
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiParameter:
\_parameter: (i), line:122
|vpiName:i
|INT:16
|vpiGenScopeArray:
\_gen_scope_array: (genblk2[17]), line:122, parent:write_back_mux
|vpiName:genblk2[17]
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[17]
|vpiGenScope:
\_gen_scope: , parent:genblk2[17]
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[17]
|vpiProcess:
\_always: , line:123
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:123
|vpiCondition:
\_operation: , line:123
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:123
|vpiName:clk
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[17].clk
|vpiStmt:
\_begin: , line:123
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[17]
|vpiStmt:
\_if_stmt: , line:124
|vpiCondition:
\_bit_select: (id_issued_one_hot), line:124
|vpiName:id_issued_one_hot
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[17].id_issued_one_hot
|vpiIndex:
\_ref_obj: (i), line:124
|vpiName:i
|vpiStmt:
\_assignment: , line:125
|vpiOpType:82
|vpiLhs:
\_bit_select: (id_unit_select_r), line:125
|vpiName:id_unit_select_r
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[17].id_unit_select_r
|vpiIndex:
\_ref_obj: (i), line:125
|vpiName:i
|vpiRhs:
\_ref_obj: (ti.issue_unit_id), line:125
|vpiName:ti.issue_unit_id
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[17].ti.issue_unit_id
|vpiContAssign:
\_cont_assign: , line:127
|vpiRhs:
\_operation: , line:127
|vpiOpType:32
|vpiOperand:
\_bit_select: (id_inuse), line:127
|vpiName:id_inuse
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[17].id_inuse
|vpiIndex:
\_ref_obj: (i), line:127
|vpiName:i
|vpiOperand:
\_bit_select: (id_unit_select_r), line:127
|vpiName:id_unit_select_r
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[17].id_unit_select_r
|vpiIndex:
\_ref_obj: (i), line:127
|vpiName:i
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[17].i
|vpiOperand:
\_ref_obj: (ti.issue_unit_id), line:127
|vpiName:ti.issue_unit_id
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[17].ti.issue_unit_id
|vpiLhs:
\_bit_select: (id_unit_select), line:127
|vpiName:id_unit_select
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[17].id_unit_select
|vpiIndex:
\_ref_obj: (i), line:127
|vpiName:i
|vpiParameter:
\_parameter: (ALU_UNIT_WB_ID), line:190
|vpiName:ALU_UNIT_WB_ID
|INT:32
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (BRANCH_PREDICTOR_WAYS), line:159
|vpiName:BRANCH_PREDICTOR_WAYS
|INT:9
|vpiParameter:
\_parameter: (BRANCH_TABLE_ENTRIES), line:160
|vpiName:BRANCH_TABLE_ENTRIES
|INT:4
|vpiParameter:
\_parameter: (BRANCH_UNIT_ID), line:195
|vpiName:BRANCH_UNIT_ID
|INT:8
|vpiParameter:
\_parameter: (BUS_ADDR_H), line:107
|vpiName:BUS_ADDR_H
|INT:1
|vpiParameter:
\_parameter: (BUS_ADDR_L), line:106
|vpiName:BUS_ADDR_L
|INT:0
|vpiParameter:
\_parameter: (BUS_BIT_CHECK), line:108
|vpiName:BUS_BIT_CHECK
|INT:1
|vpiParameter:
\_parameter: (BUS_TYPE), line:89
|vpiName:BUS_TYPE
|INT:5
|vpiParameter:
\_parameter: (COUNTER_W), line:42
|vpiName:COUNTER_W
|INT:33
|vpiParameter:
\_parameter: (CPU_ID), line:38
|vpiName:CPU_ID
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_ADDR_WIDTH), line:113
|vpiName:C_M_AXI_ADDR_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_DATA_WIDTH), line:114
|vpiName:C_M_AXI_DATA_WIDTH
|INT:1
|vpiParameter:
\_parameter: (DCACHE_LINES), line:133
|vpiName:DCACHE_LINES
|INT:-2146435073
|vpiParameter:
\_parameter: (DCACHE_LINE_ADDR_W), line:135
|vpiName:DCACHE_LINE_ADDR_W
|INT:1073741824
|vpiParameter:
\_parameter: (DCACHE_LINE_W), line:136
|vpiName:DCACHE_LINE_W
|INT:1342177279
|vpiParameter:
\_parameter: (DCACHE_SUB_LINE_ADDR_W), line:137
|vpiName:DCACHE_SUB_LINE_ADDR_W
|INT:4
|vpiParameter:
\_parameter: (DCACHE_TAG_W), line:138
|vpiName:DCACHE_TAG_W
|INT:1610612736
|vpiParameter:
\_parameter: (DCACHE_WAYS), line:134
|vpiName:DCACHE_WAYS
|INT:4
|vpiParameter:
\_parameter: (DIV_ALGORITHM), line:67
|vpiName:DIV_ALGORITHM
|INT:0
|vpiParameter:
\_parameter: (DIV_UNIT_WB_ID), line:192
|vpiName:DIV_UNIT_WB_ID
|INT:2
|vpiParameter:
\_parameter: (DTLB_DEPTH), line:152
|vpiName:DTLB_DEPTH
|INT:512
|vpiParameter:
\_parameter: (DTLB_WAYS), line:151
|vpiName:DTLB_WAYS
|INT:32
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (ENABLE_M_MODE), line:34
|vpiName:ENABLE_M_MODE
|INT:1
|vpiParameter:
\_parameter: (ENABLE_S_MODE), line:36
|vpiName:ENABLE_S_MODE
|INT:0
|vpiParameter:
\_parameter: (ENABLE_TRACE_INTERFACE), line:172
|vpiName:ENABLE_TRACE_INTERFACE
|INT:2
|vpiParameter:
\_parameter: (FETCH_BUFFER_DEPTH), line:168
|vpiName:FETCH_BUFFER_DEPTH
|INT:512
|vpiParameter:
\_parameter: (FPGA_VENDOR), line:27
|vpiName:FPGA_VENDOR
|STRING:"xilinx"
|vpiParameter:
\_parameter: (GC_UNIT_ID), line:196
|vpiName:GC_UNIT_ID
|INT:4
|vpiParameter:
\_parameter: (ICACHE_LINES), line:121
|vpiName:ICACHE_LINES
|INT:2
|vpiParameter:
\_parameter: (ICACHE_LINE_ADDR_W), line:123
|vpiName:ICACHE_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_LINE_W), line:124
|vpiName:ICACHE_LINE_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_SUB_LINE_ADDR_W), line:125
|vpiName:ICACHE_SUB_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_TAG_W), line:126
|vpiName:ICACHE_TAG_W
|INT:-2147483648
|vpiParameter:
\_parameter: (ICACHE_WAYS), line:122
|vpiName:ICACHE_WAYS
|INT:1
|vpiParameter:
\_parameter: (ITLB_DEPTH), line:146
|vpiName:ITLB_DEPTH
|INT:32
|vpiParameter:
\_parameter: (ITLB_WAYS), line:145
|vpiName:ITLB_WAYS
|INT:4
|vpiParameter:
\_parameter: (L1_CONNECTIONS), line:177
|vpiName:L1_CONNECTIONS
|INT:9
|vpiParameter:
\_parameter: (L1_DCACHE_ID), line:178
|vpiName:L1_DCACHE_ID
|INT:4
|vpiParameter:
\_parameter: (L1_DMMU_ID), line:179
|vpiName:L1_DMMU_ID
|INT:2
|vpiParameter:
\_parameter: (L1_ICACHE_ID), line:180
|vpiName:L1_ICACHE_ID
|INT:19
|vpiParameter:
\_parameter: (L1_IMMU_ID), line:181
|vpiName:L1_IMMU_ID
|INT:0
|vpiParameter:
\_parameter: (LS_UNIT_WB_ID), line:191
|vpiName:LS_UNIT_WB_ID
|INT:1
|vpiParameter:
\_parameter: (MAX_INFLIGHT_COUNT), line:167
|vpiName:MAX_INFLIGHT_COUNT
|INT:19
|vpiParameter:
\_parameter: (MEMORY_ADDR_H), line:103
|vpiName:MEMORY_ADDR_H
|INT:12
|vpiParameter:
\_parameter: (MEMORY_ADDR_L), line:102
|vpiName:MEMORY_ADDR_L
|INT:11
|vpiParameter:
\_parameter: (MEMORY_BIT_CHECK), line:104
|vpiName:MEMORY_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (MUL_UNIT_WB_ID), line:193
|vpiName:MUL_UNIT_WB_ID
|INT:512
|vpiParameter:
\_parameter: (NUM_UNITS), line:188
|vpiName:NUM_UNITS
|INT:2
|vpiParameter:
\_parameter: (NUM_WB_UNITS), line:186
|vpiName:NUM_WB_UNITS
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (RAS_DEPTH), line:161
|vpiName:RAS_DEPTH
|INT:2
|vpiParameter:
\_parameter: (RESET_VEC), line:39
|vpiName:RESET_VEC
|INT:-2147483648
|vpiParameter:
\_parameter: (SCRATCH_ADDR_H), line:99
|vpiName:SCRATCH_ADDR_H
|INT:9
|vpiParameter:
\_parameter: (SCRATCH_ADDR_L), line:98
|vpiName:SCRATCH_ADDR_L
|INT:8
|vpiParameter:
\_parameter: (SCRATCH_BIT_CHECK), line:100
|vpiName:SCRATCH_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (USE_AMO), line:70
|vpiName:USE_AMO
|INT:1
|vpiParameter:
\_parameter: (USE_BRANCH_PREDICTOR), line:158
|vpiName:USE_BRANCH_PREDICTOR
|INT:2
|vpiParameter:
\_parameter: (USE_BUS), line:88
|vpiName:USE_BUS
|INT:4
|vpiParameter:
\_parameter: (USE_DCACHE), line:92
|vpiName:USE_DCACHE
|INT:6
|vpiParameter:
\_parameter: (USE_DIV), line:49
|vpiName:USE_DIV
|INT:1
|vpiParameter:
\_parameter: (USE_DTAG_INVALIDATIONS), line:140
|vpiName:USE_DTAG_INVALIDATIONS
|INT:1879048191
|vpiParameter:
\_parameter: (USE_D_SCRATCH_MEM), line:79
|vpiName:USE_D_SCRATCH_MEM
|INT:3
|vpiParameter:
\_parameter: (USE_ICACHE), line:93
|vpiName:USE_ICACHE
|INT:7
|vpiParameter:
\_parameter: (USE_I_SCRATCH_MEM), line:78
|vpiName:USE_I_SCRATCH_MEM
|INT:2
|vpiParameter:
\_parameter: (USE_MUL), line:48
|vpiName:USE_MUL
|INT:1
|vpiParameter:
\_parameter: (WB_UNITS_WIDTH), line:187
|vpiName:WB_UNITS_WIDTH
|INT:32
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiParameter:
\_parameter: (i), line:122
|vpiName:i
|INT:17
|vpiGenScopeArray:
\_gen_scope_array: (genblk2[18]), line:122, parent:write_back_mux
|vpiName:genblk2[18]
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[18]
|vpiGenScope:
\_gen_scope: , parent:genblk2[18]
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[18]
|vpiProcess:
\_always: , line:123
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:123
|vpiCondition:
\_operation: , line:123
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:123
|vpiName:clk
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[18].clk
|vpiStmt:
\_begin: , line:123
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[18]
|vpiStmt:
\_if_stmt: , line:124
|vpiCondition:
\_bit_select: (id_issued_one_hot), line:124
|vpiName:id_issued_one_hot
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[18].id_issued_one_hot
|vpiIndex:
\_ref_obj: (i), line:124
|vpiName:i
|vpiStmt:
\_assignment: , line:125
|vpiOpType:82
|vpiLhs:
\_bit_select: (id_unit_select_r), line:125
|vpiName:id_unit_select_r
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[18].id_unit_select_r
|vpiIndex:
\_ref_obj: (i), line:125
|vpiName:i
|vpiRhs:
\_ref_obj: (ti.issue_unit_id), line:125
|vpiName:ti.issue_unit_id
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[18].ti.issue_unit_id
|vpiContAssign:
\_cont_assign: , line:127
|vpiRhs:
\_operation: , line:127
|vpiOpType:32
|vpiOperand:
\_bit_select: (id_inuse), line:127
|vpiName:id_inuse
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[18].id_inuse
|vpiIndex:
\_ref_obj: (i), line:127
|vpiName:i
|vpiOperand:
\_bit_select: (id_unit_select_r), line:127
|vpiName:id_unit_select_r
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[18].id_unit_select_r
|vpiIndex:
\_ref_obj: (i), line:127
|vpiName:i
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[18].i
|vpiOperand:
\_ref_obj: (ti.issue_unit_id), line:127
|vpiName:ti.issue_unit_id
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[18].ti.issue_unit_id
|vpiLhs:
\_bit_select: (id_unit_select), line:127
|vpiName:id_unit_select
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk2[18].id_unit_select
|vpiIndex:
\_ref_obj: (i), line:127
|vpiName:i
|vpiParameter:
\_parameter: (ALU_UNIT_WB_ID), line:190
|vpiName:ALU_UNIT_WB_ID
|INT:32
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (BRANCH_PREDICTOR_WAYS), line:159
|vpiName:BRANCH_PREDICTOR_WAYS
|INT:9
|vpiParameter:
\_parameter: (BRANCH_TABLE_ENTRIES), line:160
|vpiName:BRANCH_TABLE_ENTRIES
|INT:4
|vpiParameter:
\_parameter: (BRANCH_UNIT_ID), line:195
|vpiName:BRANCH_UNIT_ID
|INT:8
|vpiParameter:
\_parameter: (BUS_ADDR_H), line:107
|vpiName:BUS_ADDR_H
|INT:1
|vpiParameter:
\_parameter: (BUS_ADDR_L), line:106
|vpiName:BUS_ADDR_L
|INT:0
|vpiParameter:
\_parameter: (BUS_BIT_CHECK), line:108
|vpiName:BUS_BIT_CHECK
|INT:1
|vpiParameter:
\_parameter: (BUS_TYPE), line:89
|vpiName:BUS_TYPE
|INT:5
|vpiParameter:
\_parameter: (COUNTER_W), line:42
|vpiName:COUNTER_W
|INT:33
|vpiParameter:
\_parameter: (CPU_ID), line:38
|vpiName:CPU_ID
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_ADDR_WIDTH), line:113
|vpiName:C_M_AXI_ADDR_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_DATA_WIDTH), line:114
|vpiName:C_M_AXI_DATA_WIDTH
|INT:1
|vpiParameter:
\_parameter: (DCACHE_LINES), line:133
|vpiName:DCACHE_LINES
|INT:-2146435073
|vpiParameter:
\_parameter: (DCACHE_LINE_ADDR_W), line:135
|vpiName:DCACHE_LINE_ADDR_W
|INT:1073741824
|vpiParameter:
\_parameter: (DCACHE_LINE_W), line:136
|vpiName:DCACHE_LINE_W
|INT:1342177279
|vpiParameter:
\_parameter: (DCACHE_SUB_LINE_ADDR_W), line:137
|vpiName:DCACHE_SUB_LINE_ADDR_W
|INT:4
|vpiParameter:
\_parameter: (DCACHE_TAG_W), line:138
|vpiName:DCACHE_TAG_W
|INT:1610612736
|vpiParameter:
\_parameter: (DCACHE_WAYS), line:134
|vpiName:DCACHE_WAYS
|INT:4
|vpiParameter:
\_parameter: (DIV_ALGORITHM), line:67
|vpiName:DIV_ALGORITHM
|INT:0
|vpiParameter:
\_parameter: (DIV_UNIT_WB_ID), line:192
|vpiName:DIV_UNIT_WB_ID
|INT:2
|vpiParameter:
\_parameter: (DTLB_DEPTH), line:152
|vpiName:DTLB_DEPTH
|INT:512
|vpiParameter:
\_parameter: (DTLB_WAYS), line:151
|vpiName:DTLB_WAYS
|INT:32
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (ENABLE_M_MODE), line:34
|vpiName:ENABLE_M_MODE
|INT:1
|vpiParameter:
\_parameter: (ENABLE_S_MODE), line:36
|vpiName:ENABLE_S_MODE
|INT:0
|vpiParameter:
\_parameter: (ENABLE_TRACE_INTERFACE), line:172
|vpiName:ENABLE_TRACE_INTERFACE
|INT:2
|vpiParameter:
\_parameter: (FETCH_BUFFER_DEPTH), line:168
|vpiName:FETCH_BUFFER_DEPTH
|INT:512
|vpiParameter:
\_parameter: (FPGA_VENDOR), line:27
|vpiName:FPGA_VENDOR
|STRING:"xilinx"
|vpiParameter:
\_parameter: (GC_UNIT_ID), line:196
|vpiName:GC_UNIT_ID
|INT:4
|vpiParameter:
\_parameter: (ICACHE_LINES), line:121
|vpiName:ICACHE_LINES
|INT:2
|vpiParameter:
\_parameter: (ICACHE_LINE_ADDR_W), line:123
|vpiName:ICACHE_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_LINE_W), line:124
|vpiName:ICACHE_LINE_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_SUB_LINE_ADDR_W), line:125
|vpiName:ICACHE_SUB_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_TAG_W), line:126
|vpiName:ICACHE_TAG_W
|INT:-2147483648
|vpiParameter:
\_parameter: (ICACHE_WAYS), line:122
|vpiName:ICACHE_WAYS
|INT:1
|vpiParameter:
\_parameter: (ITLB_DEPTH), line:146
|vpiName:ITLB_DEPTH
|INT:32
|vpiParameter:
\_parameter: (ITLB_WAYS), line:145
|vpiName:ITLB_WAYS
|INT:4
|vpiParameter:
\_parameter: (L1_CONNECTIONS), line:177
|vpiName:L1_CONNECTIONS
|INT:9
|vpiParameter:
\_parameter: (L1_DCACHE_ID), line:178
|vpiName:L1_DCACHE_ID
|INT:4
|vpiParameter:
\_parameter: (L1_DMMU_ID), line:179
|vpiName:L1_DMMU_ID
|INT:2
|vpiParameter:
\_parameter: (L1_ICACHE_ID), line:180
|vpiName:L1_ICACHE_ID
|INT:19
|vpiParameter:
\_parameter: (L1_IMMU_ID), line:181
|vpiName:L1_IMMU_ID
|INT:0
|vpiParameter:
\_parameter: (LS_UNIT_WB_ID), line:191
|vpiName:LS_UNIT_WB_ID
|INT:1
|vpiParameter:
\_parameter: (MAX_INFLIGHT_COUNT), line:167
|vpiName:MAX_INFLIGHT_COUNT
|INT:19
|vpiParameter:
\_parameter: (MEMORY_ADDR_H), line:103
|vpiName:MEMORY_ADDR_H
|INT:12
|vpiParameter:
\_parameter: (MEMORY_ADDR_L), line:102
|vpiName:MEMORY_ADDR_L
|INT:11
|vpiParameter:
\_parameter: (MEMORY_BIT_CHECK), line:104
|vpiName:MEMORY_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (MUL_UNIT_WB_ID), line:193
|vpiName:MUL_UNIT_WB_ID
|INT:512
|vpiParameter:
\_parameter: (NUM_UNITS), line:188
|vpiName:NUM_UNITS
|INT:2
|vpiParameter:
\_parameter: (NUM_WB_UNITS), line:186
|vpiName:NUM_WB_UNITS
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (RAS_DEPTH), line:161
|vpiName:RAS_DEPTH
|INT:2
|vpiParameter:
\_parameter: (RESET_VEC), line:39
|vpiName:RESET_VEC
|INT:-2147483648
|vpiParameter:
\_parameter: (SCRATCH_ADDR_H), line:99
|vpiName:SCRATCH_ADDR_H
|INT:9
|vpiParameter:
\_parameter: (SCRATCH_ADDR_L), line:98
|vpiName:SCRATCH_ADDR_L
|INT:8
|vpiParameter:
\_parameter: (SCRATCH_BIT_CHECK), line:100
|vpiName:SCRATCH_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (USE_AMO), line:70
|vpiName:USE_AMO
|INT:1
|vpiParameter:
\_parameter: (USE_BRANCH_PREDICTOR), line:158
|vpiName:USE_BRANCH_PREDICTOR
|INT:2
|vpiParameter:
\_parameter: (USE_BUS), line:88
|vpiName:USE_BUS
|INT:4
|vpiParameter:
\_parameter: (USE_DCACHE), line:92
|vpiName:USE_DCACHE
|INT:6
|vpiParameter:
\_parameter: (USE_DIV), line:49
|vpiName:USE_DIV
|INT:1
|vpiParameter:
\_parameter: (USE_DTAG_INVALIDATIONS), line:140
|vpiName:USE_DTAG_INVALIDATIONS
|INT:1879048191
|vpiParameter:
\_parameter: (USE_D_SCRATCH_MEM), line:79
|vpiName:USE_D_SCRATCH_MEM
|INT:3
|vpiParameter:
\_parameter: (USE_ICACHE), line:93
|vpiName:USE_ICACHE
|INT:7
|vpiParameter:
\_parameter: (USE_I_SCRATCH_MEM), line:78
|vpiName:USE_I_SCRATCH_MEM
|INT:2
|vpiParameter:
\_parameter: (USE_MUL), line:48
|vpiName:USE_MUL
|INT:1
|vpiParameter:
\_parameter: (WB_UNITS_WIDTH), line:187
|vpiName:WB_UNITS_WIDTH
|INT:32
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiParameter:
\_parameter: (i), line:122
|vpiName:i
|INT:18
|vpiGenScopeArray:
\_gen_scope_array: (genblk3[0]), line:140, parent:write_back_mux
|vpiName:genblk3[0]
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk3[0]
|vpiGenScope:
\_gen_scope: , parent:genblk3[0]
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk3[0]
|vpiProcess:
\_always: , line:141
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:141
|vpiCondition:
\_operation: , line:141
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:141
|vpiName:clk
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk3[0].clk
|vpiStmt:
\_begin: , line:141
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk3[0]
|vpiStmt:
\_if_stmt: , line:142
|vpiCondition:
\_operation: , line:142
|vpiOpType:29
|vpiOperand:
\_bit_select: (id_writing_to_buffer), line:142
|vpiName:id_writing_to_buffer
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk3[0].id_writing_to_buffer
|vpiIndex:
\_ref_obj: (i), line:142
|vpiName:i
|vpiOperand:
\_bit_select: (store_mux), line:142
|vpiName:store_mux
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk3[0].store_mux
|vpiIndex:
\_ref_obj: (i), line:142
|vpiName:i
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk3[0].i
|vpiStmt:
\_assignment: , line:143
|vpiOpType:82
|vpiLhs:
\_bit_select: (results_by_id), line:143
|vpiName:results_by_id
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk3[0].results_by_id
|vpiIndex:
\_ref_obj: (i), line:143
|vpiName:i
|vpiRhs:
\_bit_select: (unit_rd), line:143
|vpiName:unit_rd
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk3[0].unit_rd
|vpiIndex:
\_operation: , line:143
|vpiOpType:33
|vpiOperand:
\_bit_select: (store_mux), line:143
|vpiName:store_mux
|vpiIndex:
\_ref_obj: (i), line:143
|vpiName:i
|vpiOperand:
\_bit_select: (id_unit_select), line:143
|vpiName:id_unit_select
|vpiIndex:
\_ref_obj: (i), line:143
|vpiName:i
|vpiParameter:
\_parameter: (ALU_UNIT_WB_ID), line:190
|vpiName:ALU_UNIT_WB_ID
|INT:32
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (BRANCH_PREDICTOR_WAYS), line:159
|vpiName:BRANCH_PREDICTOR_WAYS
|INT:9
|vpiParameter:
\_parameter: (BRANCH_TABLE_ENTRIES), line:160
|vpiName:BRANCH_TABLE_ENTRIES
|INT:4
|vpiParameter:
\_parameter: (BRANCH_UNIT_ID), line:195
|vpiName:BRANCH_UNIT_ID
|INT:8
|vpiParameter:
\_parameter: (BUS_ADDR_H), line:107
|vpiName:BUS_ADDR_H
|INT:1
|vpiParameter:
\_parameter: (BUS_ADDR_L), line:106
|vpiName:BUS_ADDR_L
|INT:0
|vpiParameter:
\_parameter: (BUS_BIT_CHECK), line:108
|vpiName:BUS_BIT_CHECK
|INT:1
|vpiParameter:
\_parameter: (BUS_TYPE), line:89
|vpiName:BUS_TYPE
|INT:5
|vpiParameter:
\_parameter: (COUNTER_W), line:42
|vpiName:COUNTER_W
|INT:33
|vpiParameter:
\_parameter: (CPU_ID), line:38
|vpiName:CPU_ID
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_ADDR_WIDTH), line:113
|vpiName:C_M_AXI_ADDR_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_DATA_WIDTH), line:114
|vpiName:C_M_AXI_DATA_WIDTH
|INT:1
|vpiParameter:
\_parameter: (DCACHE_LINES), line:133
|vpiName:DCACHE_LINES
|INT:-2146435073
|vpiParameter:
\_parameter: (DCACHE_LINE_ADDR_W), line:135
|vpiName:DCACHE_LINE_ADDR_W
|INT:1073741824
|vpiParameter:
\_parameter: (DCACHE_LINE_W), line:136
|vpiName:DCACHE_LINE_W
|INT:1342177279
|vpiParameter:
\_parameter: (DCACHE_SUB_LINE_ADDR_W), line:137
|vpiName:DCACHE_SUB_LINE_ADDR_W
|INT:4
|vpiParameter:
\_parameter: (DCACHE_TAG_W), line:138
|vpiName:DCACHE_TAG_W
|INT:1610612736
|vpiParameter:
\_parameter: (DCACHE_WAYS), line:134
|vpiName:DCACHE_WAYS
|INT:4
|vpiParameter:
\_parameter: (DIV_ALGORITHM), line:67
|vpiName:DIV_ALGORITHM
|INT:0
|vpiParameter:
\_parameter: (DIV_UNIT_WB_ID), line:192
|vpiName:DIV_UNIT_WB_ID
|INT:2
|vpiParameter:
\_parameter: (DTLB_DEPTH), line:152
|vpiName:DTLB_DEPTH
|INT:512
|vpiParameter:
\_parameter: (DTLB_WAYS), line:151
|vpiName:DTLB_WAYS
|INT:32
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (ENABLE_M_MODE), line:34
|vpiName:ENABLE_M_MODE
|INT:1
|vpiParameter:
\_parameter: (ENABLE_S_MODE), line:36
|vpiName:ENABLE_S_MODE
|INT:0
|vpiParameter:
\_parameter: (ENABLE_TRACE_INTERFACE), line:172
|vpiName:ENABLE_TRACE_INTERFACE
|INT:2
|vpiParameter:
\_parameter: (FETCH_BUFFER_DEPTH), line:168
|vpiName:FETCH_BUFFER_DEPTH
|INT:512
|vpiParameter:
\_parameter: (FPGA_VENDOR), line:27
|vpiName:FPGA_VENDOR
|STRING:"xilinx"
|vpiParameter:
\_parameter: (GC_UNIT_ID), line:196
|vpiName:GC_UNIT_ID
|INT:4
|vpiParameter:
\_parameter: (ICACHE_LINES), line:121
|vpiName:ICACHE_LINES
|INT:2
|vpiParameter:
\_parameter: (ICACHE_LINE_ADDR_W), line:123
|vpiName:ICACHE_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_LINE_W), line:124
|vpiName:ICACHE_LINE_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_SUB_LINE_ADDR_W), line:125
|vpiName:ICACHE_SUB_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_TAG_W), line:126
|vpiName:ICACHE_TAG_W
|INT:-2147483648
|vpiParameter:
\_parameter: (ICACHE_WAYS), line:122
|vpiName:ICACHE_WAYS
|INT:1
|vpiParameter:
\_parameter: (ITLB_DEPTH), line:146
|vpiName:ITLB_DEPTH
|INT:32
|vpiParameter:
\_parameter: (ITLB_WAYS), line:145
|vpiName:ITLB_WAYS
|INT:4
|vpiParameter:
\_parameter: (L1_CONNECTIONS), line:177
|vpiName:L1_CONNECTIONS
|INT:9
|vpiParameter:
\_parameter: (L1_DCACHE_ID), line:178
|vpiName:L1_DCACHE_ID
|INT:4
|vpiParameter:
\_parameter: (L1_DMMU_ID), line:179
|vpiName:L1_DMMU_ID
|INT:2
|vpiParameter:
\_parameter: (L1_ICACHE_ID), line:180
|vpiName:L1_ICACHE_ID
|INT:19
|vpiParameter:
\_parameter: (L1_IMMU_ID), line:181
|vpiName:L1_IMMU_ID
|INT:0
|vpiParameter:
\_parameter: (LS_UNIT_WB_ID), line:191
|vpiName:LS_UNIT_WB_ID
|INT:1
|vpiParameter:
\_parameter: (MAX_INFLIGHT_COUNT), line:167
|vpiName:MAX_INFLIGHT_COUNT
|INT:19
|vpiParameter:
\_parameter: (MEMORY_ADDR_H), line:103
|vpiName:MEMORY_ADDR_H
|INT:12
|vpiParameter:
\_parameter: (MEMORY_ADDR_L), line:102
|vpiName:MEMORY_ADDR_L
|INT:11
|vpiParameter:
\_parameter: (MEMORY_BIT_CHECK), line:104
|vpiName:MEMORY_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (MUL_UNIT_WB_ID), line:193
|vpiName:MUL_UNIT_WB_ID
|INT:512
|vpiParameter:
\_parameter: (NUM_UNITS), line:188
|vpiName:NUM_UNITS
|INT:2
|vpiParameter:
\_parameter: (NUM_WB_UNITS), line:186
|vpiName:NUM_WB_UNITS
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (RAS_DEPTH), line:161
|vpiName:RAS_DEPTH
|INT:2
|vpiParameter:
\_parameter: (RESET_VEC), line:39
|vpiName:RESET_VEC
|INT:-2147483648
|vpiParameter:
\_parameter: (SCRATCH_ADDR_H), line:99
|vpiName:SCRATCH_ADDR_H
|INT:9
|vpiParameter:
\_parameter: (SCRATCH_ADDR_L), line:98
|vpiName:SCRATCH_ADDR_L
|INT:8
|vpiParameter:
\_parameter: (SCRATCH_BIT_CHECK), line:100
|vpiName:SCRATCH_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (USE_AMO), line:70
|vpiName:USE_AMO
|INT:1
|vpiParameter:
\_parameter: (USE_BRANCH_PREDICTOR), line:158
|vpiName:USE_BRANCH_PREDICTOR
|INT:2
|vpiParameter:
\_parameter: (USE_BUS), line:88
|vpiName:USE_BUS
|INT:4
|vpiParameter:
\_parameter: (USE_DCACHE), line:92
|vpiName:USE_DCACHE
|INT:6
|vpiParameter:
\_parameter: (USE_DIV), line:49
|vpiName:USE_DIV
|INT:1
|vpiParameter:
\_parameter: (USE_DTAG_INVALIDATIONS), line:140
|vpiName:USE_DTAG_INVALIDATIONS
|INT:1879048191
|vpiParameter:
\_parameter: (USE_D_SCRATCH_MEM), line:79
|vpiName:USE_D_SCRATCH_MEM
|INT:3
|vpiParameter:
\_parameter: (USE_ICACHE), line:93
|vpiName:USE_ICACHE
|INT:7
|vpiParameter:
\_parameter: (USE_I_SCRATCH_MEM), line:78
|vpiName:USE_I_SCRATCH_MEM
|INT:2
|vpiParameter:
\_parameter: (USE_MUL), line:48
|vpiName:USE_MUL
|INT:1
|vpiParameter:
\_parameter: (WB_UNITS_WIDTH), line:187
|vpiName:WB_UNITS_WIDTH
|INT:32
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiParameter:
\_parameter: (i), line:140
|vpiName:i
|INT:0
|vpiGenScopeArray:
\_gen_scope_array: (genblk3[1]), line:140, parent:write_back_mux
|vpiName:genblk3[1]
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk3[1]
|vpiGenScope:
\_gen_scope: , parent:genblk3[1]
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk3[1]
|vpiProcess:
\_always: , line:141
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:141
|vpiCondition:
\_operation: , line:141
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:141
|vpiName:clk
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk3[1].clk
|vpiStmt:
\_begin: , line:141
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk3[1]
|vpiStmt:
\_if_stmt: , line:142
|vpiCondition:
\_operation: , line:142
|vpiOpType:29
|vpiOperand:
\_bit_select: (id_writing_to_buffer), line:142
|vpiName:id_writing_to_buffer
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk3[1].id_writing_to_buffer
|vpiIndex:
\_ref_obj: (i), line:142
|vpiName:i
|vpiOperand:
\_bit_select: (store_mux), line:142
|vpiName:store_mux
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk3[1].store_mux
|vpiIndex:
\_ref_obj: (i), line:142
|vpiName:i
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk3[1].i
|vpiStmt:
\_assignment: , line:143
|vpiOpType:82
|vpiLhs:
\_bit_select: (results_by_id), line:143
|vpiName:results_by_id
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk3[1].results_by_id
|vpiIndex:
\_ref_obj: (i), line:143
|vpiName:i
|vpiRhs:
\_bit_select: (unit_rd), line:143
|vpiName:unit_rd
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk3[1].unit_rd
|vpiIndex:
\_operation: , line:143
|vpiOpType:33
|vpiOperand:
\_bit_select: (store_mux), line:143
|vpiName:store_mux
|vpiIndex:
\_ref_obj: (i), line:143
|vpiName:i
|vpiOperand:
\_bit_select: (id_unit_select), line:143
|vpiName:id_unit_select
|vpiIndex:
\_ref_obj: (i), line:143
|vpiName:i
|vpiParameter:
\_parameter: (ALU_UNIT_WB_ID), line:190
|vpiName:ALU_UNIT_WB_ID
|INT:32
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (BRANCH_PREDICTOR_WAYS), line:159
|vpiName:BRANCH_PREDICTOR_WAYS
|INT:9
|vpiParameter:
\_parameter: (BRANCH_TABLE_ENTRIES), line:160
|vpiName:BRANCH_TABLE_ENTRIES
|INT:4
|vpiParameter:
\_parameter: (BRANCH_UNIT_ID), line:195
|vpiName:BRANCH_UNIT_ID
|INT:8
|vpiParameter:
\_parameter: (BUS_ADDR_H), line:107
|vpiName:BUS_ADDR_H
|INT:1
|vpiParameter:
\_parameter: (BUS_ADDR_L), line:106
|vpiName:BUS_ADDR_L
|INT:0
|vpiParameter:
\_parameter: (BUS_BIT_CHECK), line:108
|vpiName:BUS_BIT_CHECK
|INT:1
|vpiParameter:
\_parameter: (BUS_TYPE), line:89
|vpiName:BUS_TYPE
|INT:5
|vpiParameter:
\_parameter: (COUNTER_W), line:42
|vpiName:COUNTER_W
|INT:33
|vpiParameter:
\_parameter: (CPU_ID), line:38
|vpiName:CPU_ID
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_ADDR_WIDTH), line:113
|vpiName:C_M_AXI_ADDR_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_DATA_WIDTH), line:114
|vpiName:C_M_AXI_DATA_WIDTH
|INT:1
|vpiParameter:
\_parameter: (DCACHE_LINES), line:133
|vpiName:DCACHE_LINES
|INT:-2146435073
|vpiParameter:
\_parameter: (DCACHE_LINE_ADDR_W), line:135
|vpiName:DCACHE_LINE_ADDR_W
|INT:1073741824
|vpiParameter:
\_parameter: (DCACHE_LINE_W), line:136
|vpiName:DCACHE_LINE_W
|INT:1342177279
|vpiParameter:
\_parameter: (DCACHE_SUB_LINE_ADDR_W), line:137
|vpiName:DCACHE_SUB_LINE_ADDR_W
|INT:4
|vpiParameter:
\_parameter: (DCACHE_TAG_W), line:138
|vpiName:DCACHE_TAG_W
|INT:1610612736
|vpiParameter:
\_parameter: (DCACHE_WAYS), line:134
|vpiName:DCACHE_WAYS
|INT:4
|vpiParameter:
\_parameter: (DIV_ALGORITHM), line:67
|vpiName:DIV_ALGORITHM
|INT:0
|vpiParameter:
\_parameter: (DIV_UNIT_WB_ID), line:192
|vpiName:DIV_UNIT_WB_ID
|INT:2
|vpiParameter:
\_parameter: (DTLB_DEPTH), line:152
|vpiName:DTLB_DEPTH
|INT:512
|vpiParameter:
\_parameter: (DTLB_WAYS), line:151
|vpiName:DTLB_WAYS
|INT:32
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (ENABLE_M_MODE), line:34
|vpiName:ENABLE_M_MODE
|INT:1
|vpiParameter:
\_parameter: (ENABLE_S_MODE), line:36
|vpiName:ENABLE_S_MODE
|INT:0
|vpiParameter:
\_parameter: (ENABLE_TRACE_INTERFACE), line:172
|vpiName:ENABLE_TRACE_INTERFACE
|INT:2
|vpiParameter:
\_parameter: (FETCH_BUFFER_DEPTH), line:168
|vpiName:FETCH_BUFFER_DEPTH
|INT:512
|vpiParameter:
\_parameter: (FPGA_VENDOR), line:27
|vpiName:FPGA_VENDOR
|STRING:"xilinx"
|vpiParameter:
\_parameter: (GC_UNIT_ID), line:196
|vpiName:GC_UNIT_ID
|INT:4
|vpiParameter:
\_parameter: (ICACHE_LINES), line:121
|vpiName:ICACHE_LINES
|INT:2
|vpiParameter:
\_parameter: (ICACHE_LINE_ADDR_W), line:123
|vpiName:ICACHE_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_LINE_W), line:124
|vpiName:ICACHE_LINE_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_SUB_LINE_ADDR_W), line:125
|vpiName:ICACHE_SUB_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_TAG_W), line:126
|vpiName:ICACHE_TAG_W
|INT:-2147483648
|vpiParameter:
\_parameter: (ICACHE_WAYS), line:122
|vpiName:ICACHE_WAYS
|INT:1
|vpiParameter:
\_parameter: (ITLB_DEPTH), line:146
|vpiName:ITLB_DEPTH
|INT:32
|vpiParameter:
\_parameter: (ITLB_WAYS), line:145
|vpiName:ITLB_WAYS
|INT:4
|vpiParameter:
\_parameter: (L1_CONNECTIONS), line:177
|vpiName:L1_CONNECTIONS
|INT:9
|vpiParameter:
\_parameter: (L1_DCACHE_ID), line:178
|vpiName:L1_DCACHE_ID
|INT:4
|vpiParameter:
\_parameter: (L1_DMMU_ID), line:179
|vpiName:L1_DMMU_ID
|INT:2
|vpiParameter:
\_parameter: (L1_ICACHE_ID), line:180
|vpiName:L1_ICACHE_ID
|INT:19
|vpiParameter:
\_parameter: (L1_IMMU_ID), line:181
|vpiName:L1_IMMU_ID
|INT:0
|vpiParameter:
\_parameter: (LS_UNIT_WB_ID), line:191
|vpiName:LS_UNIT_WB_ID
|INT:1
|vpiParameter:
\_parameter: (MAX_INFLIGHT_COUNT), line:167
|vpiName:MAX_INFLIGHT_COUNT
|INT:19
|vpiParameter:
\_parameter: (MEMORY_ADDR_H), line:103
|vpiName:MEMORY_ADDR_H
|INT:12
|vpiParameter:
\_parameter: (MEMORY_ADDR_L), line:102
|vpiName:MEMORY_ADDR_L
|INT:11
|vpiParameter:
\_parameter: (MEMORY_BIT_CHECK), line:104
|vpiName:MEMORY_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (MUL_UNIT_WB_ID), line:193
|vpiName:MUL_UNIT_WB_ID
|INT:512
|vpiParameter:
\_parameter: (NUM_UNITS), line:188
|vpiName:NUM_UNITS
|INT:2
|vpiParameter:
\_parameter: (NUM_WB_UNITS), line:186
|vpiName:NUM_WB_UNITS
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (RAS_DEPTH), line:161
|vpiName:RAS_DEPTH
|INT:2
|vpiParameter:
\_parameter: (RESET_VEC), line:39
|vpiName:RESET_VEC
|INT:-2147483648
|vpiParameter:
\_parameter: (SCRATCH_ADDR_H), line:99
|vpiName:SCRATCH_ADDR_H
|INT:9
|vpiParameter:
\_parameter: (SCRATCH_ADDR_L), line:98
|vpiName:SCRATCH_ADDR_L
|INT:8
|vpiParameter:
\_parameter: (SCRATCH_BIT_CHECK), line:100
|vpiName:SCRATCH_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (USE_AMO), line:70
|vpiName:USE_AMO
|INT:1
|vpiParameter:
\_parameter: (USE_BRANCH_PREDICTOR), line:158
|vpiName:USE_BRANCH_PREDICTOR
|INT:2
|vpiParameter:
\_parameter: (USE_BUS), line:88
|vpiName:USE_BUS
|INT:4
|vpiParameter:
\_parameter: (USE_DCACHE), line:92
|vpiName:USE_DCACHE
|INT:6
|vpiParameter:
\_parameter: (USE_DIV), line:49
|vpiName:USE_DIV
|INT:1
|vpiParameter:
\_parameter: (USE_DTAG_INVALIDATIONS), line:140
|vpiName:USE_DTAG_INVALIDATIONS
|INT:1879048191
|vpiParameter:
\_parameter: (USE_D_SCRATCH_MEM), line:79
|vpiName:USE_D_SCRATCH_MEM
|INT:3
|vpiParameter:
\_parameter: (USE_ICACHE), line:93
|vpiName:USE_ICACHE
|INT:7
|vpiParameter:
\_parameter: (USE_I_SCRATCH_MEM), line:78
|vpiName:USE_I_SCRATCH_MEM
|INT:2
|vpiParameter:
\_parameter: (USE_MUL), line:48
|vpiName:USE_MUL
|INT:1
|vpiParameter:
\_parameter: (WB_UNITS_WIDTH), line:187
|vpiName:WB_UNITS_WIDTH
|INT:32
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiParameter:
\_parameter: (i), line:140
|vpiName:i
|INT:1
|vpiGenScopeArray:
\_gen_scope_array: (genblk3[2]), line:140, parent:write_back_mux
|vpiName:genblk3[2]
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk3[2]
|vpiGenScope:
\_gen_scope: , parent:genblk3[2]
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk3[2]
|vpiProcess:
\_always: , line:141
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:141
|vpiCondition:
\_operation: , line:141
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:141
|vpiName:clk
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk3[2].clk
|vpiStmt:
\_begin: , line:141
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk3[2]
|vpiStmt:
\_if_stmt: , line:142
|vpiCondition:
\_operation: , line:142
|vpiOpType:29
|vpiOperand:
\_bit_select: (id_writing_to_buffer), line:142
|vpiName:id_writing_to_buffer
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk3[2].id_writing_to_buffer
|vpiIndex:
\_ref_obj: (i), line:142
|vpiName:i
|vpiOperand:
\_bit_select: (store_mux), line:142
|vpiName:store_mux
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk3[2].store_mux
|vpiIndex:
\_ref_obj: (i), line:142
|vpiName:i
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk3[2].i
|vpiStmt:
\_assignment: , line:143
|vpiOpType:82
|vpiLhs:
\_bit_select: (results_by_id), line:143
|vpiName:results_by_id
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk3[2].results_by_id
|vpiIndex:
\_ref_obj: (i), line:143
|vpiName:i
|vpiRhs:
\_bit_select: (unit_rd), line:143
|vpiName:unit_rd
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk3[2].unit_rd
|vpiIndex:
\_operation: , line:143
|vpiOpType:33
|vpiOperand:
\_bit_select: (store_mux), line:143
|vpiName:store_mux
|vpiIndex:
\_ref_obj: (i), line:143
|vpiName:i
|vpiOperand:
\_bit_select: (id_unit_select), line:143
|vpiName:id_unit_select
|vpiIndex:
\_ref_obj: (i), line:143
|vpiName:i
|vpiParameter:
\_parameter: (ALU_UNIT_WB_ID), line:190
|vpiName:ALU_UNIT_WB_ID
|INT:32
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (BRANCH_PREDICTOR_WAYS), line:159
|vpiName:BRANCH_PREDICTOR_WAYS
|INT:9
|vpiParameter:
\_parameter: (BRANCH_TABLE_ENTRIES), line:160
|vpiName:BRANCH_TABLE_ENTRIES
|INT:4
|vpiParameter:
\_parameter: (BRANCH_UNIT_ID), line:195
|vpiName:BRANCH_UNIT_ID
|INT:8
|vpiParameter:
\_parameter: (BUS_ADDR_H), line:107
|vpiName:BUS_ADDR_H
|INT:1
|vpiParameter:
\_parameter: (BUS_ADDR_L), line:106
|vpiName:BUS_ADDR_L
|INT:0
|vpiParameter:
\_parameter: (BUS_BIT_CHECK), line:108
|vpiName:BUS_BIT_CHECK
|INT:1
|vpiParameter:
\_parameter: (BUS_TYPE), line:89
|vpiName:BUS_TYPE
|INT:5
|vpiParameter:
\_parameter: (COUNTER_W), line:42
|vpiName:COUNTER_W
|INT:33
|vpiParameter:
\_parameter: (CPU_ID), line:38
|vpiName:CPU_ID
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_ADDR_WIDTH), line:113
|vpiName:C_M_AXI_ADDR_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_DATA_WIDTH), line:114
|vpiName:C_M_AXI_DATA_WIDTH
|INT:1
|vpiParameter:
\_parameter: (DCACHE_LINES), line:133
|vpiName:DCACHE_LINES
|INT:-2146435073
|vpiParameter:
\_parameter: (DCACHE_LINE_ADDR_W), line:135
|vpiName:DCACHE_LINE_ADDR_W
|INT:1073741824
|vpiParameter:
\_parameter: (DCACHE_LINE_W), line:136
|vpiName:DCACHE_LINE_W
|INT:1342177279
|vpiParameter:
\_parameter: (DCACHE_SUB_LINE_ADDR_W), line:137
|vpiName:DCACHE_SUB_LINE_ADDR_W
|INT:4
|vpiParameter:
\_parameter: (DCACHE_TAG_W), line:138
|vpiName:DCACHE_TAG_W
|INT:1610612736
|vpiParameter:
\_parameter: (DCACHE_WAYS), line:134
|vpiName:DCACHE_WAYS
|INT:4
|vpiParameter:
\_parameter: (DIV_ALGORITHM), line:67
|vpiName:DIV_ALGORITHM
|INT:0
|vpiParameter:
\_parameter: (DIV_UNIT_WB_ID), line:192
|vpiName:DIV_UNIT_WB_ID
|INT:2
|vpiParameter:
\_parameter: (DTLB_DEPTH), line:152
|vpiName:DTLB_DEPTH
|INT:512
|vpiParameter:
\_parameter: (DTLB_WAYS), line:151
|vpiName:DTLB_WAYS
|INT:32
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (ENABLE_M_MODE), line:34
|vpiName:ENABLE_M_MODE
|INT:1
|vpiParameter:
\_parameter: (ENABLE_S_MODE), line:36
|vpiName:ENABLE_S_MODE
|INT:0
|vpiParameter:
\_parameter: (ENABLE_TRACE_INTERFACE), line:172
|vpiName:ENABLE_TRACE_INTERFACE
|INT:2
|vpiParameter:
\_parameter: (FETCH_BUFFER_DEPTH), line:168
|vpiName:FETCH_BUFFER_DEPTH
|INT:512
|vpiParameter:
\_parameter: (FPGA_VENDOR), line:27
|vpiName:FPGA_VENDOR
|STRING:"xilinx"
|vpiParameter:
\_parameter: (GC_UNIT_ID), line:196
|vpiName:GC_UNIT_ID
|INT:4
|vpiParameter:
\_parameter: (ICACHE_LINES), line:121
|vpiName:ICACHE_LINES
|INT:2
|vpiParameter:
\_parameter: (ICACHE_LINE_ADDR_W), line:123
|vpiName:ICACHE_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_LINE_W), line:124
|vpiName:ICACHE_LINE_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_SUB_LINE_ADDR_W), line:125
|vpiName:ICACHE_SUB_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_TAG_W), line:126
|vpiName:ICACHE_TAG_W
|INT:-2147483648
|vpiParameter:
\_parameter: (ICACHE_WAYS), line:122
|vpiName:ICACHE_WAYS
|INT:1
|vpiParameter:
\_parameter: (ITLB_DEPTH), line:146
|vpiName:ITLB_DEPTH
|INT:32
|vpiParameter:
\_parameter: (ITLB_WAYS), line:145
|vpiName:ITLB_WAYS
|INT:4
|vpiParameter:
\_parameter: (L1_CONNECTIONS), line:177
|vpiName:L1_CONNECTIONS
|INT:9
|vpiParameter:
\_parameter: (L1_DCACHE_ID), line:178
|vpiName:L1_DCACHE_ID
|INT:4
|vpiParameter:
\_parameter: (L1_DMMU_ID), line:179
|vpiName:L1_DMMU_ID
|INT:2
|vpiParameter:
\_parameter: (L1_ICACHE_ID), line:180
|vpiName:L1_ICACHE_ID
|INT:19
|vpiParameter:
\_parameter: (L1_IMMU_ID), line:181
|vpiName:L1_IMMU_ID
|INT:0
|vpiParameter:
\_parameter: (LS_UNIT_WB_ID), line:191
|vpiName:LS_UNIT_WB_ID
|INT:1
|vpiParameter:
\_parameter: (MAX_INFLIGHT_COUNT), line:167
|vpiName:MAX_INFLIGHT_COUNT
|INT:19
|vpiParameter:
\_parameter: (MEMORY_ADDR_H), line:103
|vpiName:MEMORY_ADDR_H
|INT:12
|vpiParameter:
\_parameter: (MEMORY_ADDR_L), line:102
|vpiName:MEMORY_ADDR_L
|INT:11
|vpiParameter:
\_parameter: (MEMORY_BIT_CHECK), line:104
|vpiName:MEMORY_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (MUL_UNIT_WB_ID), line:193
|vpiName:MUL_UNIT_WB_ID
|INT:512
|vpiParameter:
\_parameter: (NUM_UNITS), line:188
|vpiName:NUM_UNITS
|INT:2
|vpiParameter:
\_parameter: (NUM_WB_UNITS), line:186
|vpiName:NUM_WB_UNITS
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (RAS_DEPTH), line:161
|vpiName:RAS_DEPTH
|INT:2
|vpiParameter:
\_parameter: (RESET_VEC), line:39
|vpiName:RESET_VEC
|INT:-2147483648
|vpiParameter:
\_parameter: (SCRATCH_ADDR_H), line:99
|vpiName:SCRATCH_ADDR_H
|INT:9
|vpiParameter:
\_parameter: (SCRATCH_ADDR_L), line:98
|vpiName:SCRATCH_ADDR_L
|INT:8
|vpiParameter:
\_parameter: (SCRATCH_BIT_CHECK), line:100
|vpiName:SCRATCH_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (USE_AMO), line:70
|vpiName:USE_AMO
|INT:1
|vpiParameter:
\_parameter: (USE_BRANCH_PREDICTOR), line:158
|vpiName:USE_BRANCH_PREDICTOR
|INT:2
|vpiParameter:
\_parameter: (USE_BUS), line:88
|vpiName:USE_BUS
|INT:4
|vpiParameter:
\_parameter: (USE_DCACHE), line:92
|vpiName:USE_DCACHE
|INT:6
|vpiParameter:
\_parameter: (USE_DIV), line:49
|vpiName:USE_DIV
|INT:1
|vpiParameter:
\_parameter: (USE_DTAG_INVALIDATIONS), line:140
|vpiName:USE_DTAG_INVALIDATIONS
|INT:1879048191
|vpiParameter:
\_parameter: (USE_D_SCRATCH_MEM), line:79
|vpiName:USE_D_SCRATCH_MEM
|INT:3
|vpiParameter:
\_parameter: (USE_ICACHE), line:93
|vpiName:USE_ICACHE
|INT:7
|vpiParameter:
\_parameter: (USE_I_SCRATCH_MEM), line:78
|vpiName:USE_I_SCRATCH_MEM
|INT:2
|vpiParameter:
\_parameter: (USE_MUL), line:48
|vpiName:USE_MUL
|INT:1
|vpiParameter:
\_parameter: (WB_UNITS_WIDTH), line:187
|vpiName:WB_UNITS_WIDTH
|INT:32
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiParameter:
\_parameter: (i), line:140
|vpiName:i
|INT:2
|vpiGenScopeArray:
\_gen_scope_array: (genblk3[3]), line:140, parent:write_back_mux
|vpiName:genblk3[3]
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk3[3]
|vpiGenScope:
\_gen_scope: , parent:genblk3[3]
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk3[3]
|vpiProcess:
\_always: , line:141
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:141
|vpiCondition:
\_operation: , line:141
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:141
|vpiName:clk
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk3[3].clk
|vpiStmt:
\_begin: , line:141
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk3[3]
|vpiStmt:
\_if_stmt: , line:142
|vpiCondition:
\_operation: , line:142
|vpiOpType:29
|vpiOperand:
\_bit_select: (id_writing_to_buffer), line:142
|vpiName:id_writing_to_buffer
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk3[3].id_writing_to_buffer
|vpiIndex:
\_ref_obj: (i), line:142
|vpiName:i
|vpiOperand:
\_bit_select: (store_mux), line:142
|vpiName:store_mux
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk3[3].store_mux
|vpiIndex:
\_ref_obj: (i), line:142
|vpiName:i
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk3[3].i
|vpiStmt:
\_assignment: , line:143
|vpiOpType:82
|vpiLhs:
\_bit_select: (results_by_id), line:143
|vpiName:results_by_id
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk3[3].results_by_id
|vpiIndex:
\_ref_obj: (i), line:143
|vpiName:i
|vpiRhs:
\_bit_select: (unit_rd), line:143
|vpiName:unit_rd
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk3[3].unit_rd
|vpiIndex:
\_operation: , line:143
|vpiOpType:33
|vpiOperand:
\_bit_select: (store_mux), line:143
|vpiName:store_mux
|vpiIndex:
\_ref_obj: (i), line:143
|vpiName:i
|vpiOperand:
\_bit_select: (id_unit_select), line:143
|vpiName:id_unit_select
|vpiIndex:
\_ref_obj: (i), line:143
|vpiName:i
|vpiParameter:
\_parameter: (ALU_UNIT_WB_ID), line:190
|vpiName:ALU_UNIT_WB_ID
|INT:32
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (BRANCH_PREDICTOR_WAYS), line:159
|vpiName:BRANCH_PREDICTOR_WAYS
|INT:9
|vpiParameter:
\_parameter: (BRANCH_TABLE_ENTRIES), line:160
|vpiName:BRANCH_TABLE_ENTRIES
|INT:4
|vpiParameter:
\_parameter: (BRANCH_UNIT_ID), line:195
|vpiName:BRANCH_UNIT_ID
|INT:8
|vpiParameter:
\_parameter: (BUS_ADDR_H), line:107
|vpiName:BUS_ADDR_H
|INT:1
|vpiParameter:
\_parameter: (BUS_ADDR_L), line:106
|vpiName:BUS_ADDR_L
|INT:0
|vpiParameter:
\_parameter: (BUS_BIT_CHECK), line:108
|vpiName:BUS_BIT_CHECK
|INT:1
|vpiParameter:
\_parameter: (BUS_TYPE), line:89
|vpiName:BUS_TYPE
|INT:5
|vpiParameter:
\_parameter: (COUNTER_W), line:42
|vpiName:COUNTER_W
|INT:33
|vpiParameter:
\_parameter: (CPU_ID), line:38
|vpiName:CPU_ID
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_ADDR_WIDTH), line:113
|vpiName:C_M_AXI_ADDR_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_DATA_WIDTH), line:114
|vpiName:C_M_AXI_DATA_WIDTH
|INT:1
|vpiParameter:
\_parameter: (DCACHE_LINES), line:133
|vpiName:DCACHE_LINES
|INT:-2146435073
|vpiParameter:
\_parameter: (DCACHE_LINE_ADDR_W), line:135
|vpiName:DCACHE_LINE_ADDR_W
|INT:1073741824
|vpiParameter:
\_parameter: (DCACHE_LINE_W), line:136
|vpiName:DCACHE_LINE_W
|INT:1342177279
|vpiParameter:
\_parameter: (DCACHE_SUB_LINE_ADDR_W), line:137
|vpiName:DCACHE_SUB_LINE_ADDR_W
|INT:4
|vpiParameter:
\_parameter: (DCACHE_TAG_W), line:138
|vpiName:DCACHE_TAG_W
|INT:1610612736
|vpiParameter:
\_parameter: (DCACHE_WAYS), line:134
|vpiName:DCACHE_WAYS
|INT:4
|vpiParameter:
\_parameter: (DIV_ALGORITHM), line:67
|vpiName:DIV_ALGORITHM
|INT:0
|vpiParameter:
\_parameter: (DIV_UNIT_WB_ID), line:192
|vpiName:DIV_UNIT_WB_ID
|INT:2
|vpiParameter:
\_parameter: (DTLB_DEPTH), line:152
|vpiName:DTLB_DEPTH
|INT:512
|vpiParameter:
\_parameter: (DTLB_WAYS), line:151
|vpiName:DTLB_WAYS
|INT:32
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (ENABLE_M_MODE), line:34
|vpiName:ENABLE_M_MODE
|INT:1
|vpiParameter:
\_parameter: (ENABLE_S_MODE), line:36
|vpiName:ENABLE_S_MODE
|INT:0
|vpiParameter:
\_parameter: (ENABLE_TRACE_INTERFACE), line:172
|vpiName:ENABLE_TRACE_INTERFACE
|INT:2
|vpiParameter:
\_parameter: (FETCH_BUFFER_DEPTH), line:168
|vpiName:FETCH_BUFFER_DEPTH
|INT:512
|vpiParameter:
\_parameter: (FPGA_VENDOR), line:27
|vpiName:FPGA_VENDOR
|STRING:"xilinx"
|vpiParameter:
\_parameter: (GC_UNIT_ID), line:196
|vpiName:GC_UNIT_ID
|INT:4
|vpiParameter:
\_parameter: (ICACHE_LINES), line:121
|vpiName:ICACHE_LINES
|INT:2
|vpiParameter:
\_parameter: (ICACHE_LINE_ADDR_W), line:123
|vpiName:ICACHE_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_LINE_W), line:124
|vpiName:ICACHE_LINE_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_SUB_LINE_ADDR_W), line:125
|vpiName:ICACHE_SUB_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_TAG_W), line:126
|vpiName:ICACHE_TAG_W
|INT:-2147483648
|vpiParameter:
\_parameter: (ICACHE_WAYS), line:122
|vpiName:ICACHE_WAYS
|INT:1
|vpiParameter:
\_parameter: (ITLB_DEPTH), line:146
|vpiName:ITLB_DEPTH
|INT:32
|vpiParameter:
\_parameter: (ITLB_WAYS), line:145
|vpiName:ITLB_WAYS
|INT:4
|vpiParameter:
\_parameter: (L1_CONNECTIONS), line:177
|vpiName:L1_CONNECTIONS
|INT:9
|vpiParameter:
\_parameter: (L1_DCACHE_ID), line:178
|vpiName:L1_DCACHE_ID
|INT:4
|vpiParameter:
\_parameter: (L1_DMMU_ID), line:179
|vpiName:L1_DMMU_ID
|INT:2
|vpiParameter:
\_parameter: (L1_ICACHE_ID), line:180
|vpiName:L1_ICACHE_ID
|INT:19
|vpiParameter:
\_parameter: (L1_IMMU_ID), line:181
|vpiName:L1_IMMU_ID
|INT:0
|vpiParameter:
\_parameter: (LS_UNIT_WB_ID), line:191
|vpiName:LS_UNIT_WB_ID
|INT:1
|vpiParameter:
\_parameter: (MAX_INFLIGHT_COUNT), line:167
|vpiName:MAX_INFLIGHT_COUNT
|INT:19
|vpiParameter:
\_parameter: (MEMORY_ADDR_H), line:103
|vpiName:MEMORY_ADDR_H
|INT:12
|vpiParameter:
\_parameter: (MEMORY_ADDR_L), line:102
|vpiName:MEMORY_ADDR_L
|INT:11
|vpiParameter:
\_parameter: (MEMORY_BIT_CHECK), line:104
|vpiName:MEMORY_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (MUL_UNIT_WB_ID), line:193
|vpiName:MUL_UNIT_WB_ID
|INT:512
|vpiParameter:
\_parameter: (NUM_UNITS), line:188
|vpiName:NUM_UNITS
|INT:2
|vpiParameter:
\_parameter: (NUM_WB_UNITS), line:186
|vpiName:NUM_WB_UNITS
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (RAS_DEPTH), line:161
|vpiName:RAS_DEPTH
|INT:2
|vpiParameter:
\_parameter: (RESET_VEC), line:39
|vpiName:RESET_VEC
|INT:-2147483648
|vpiParameter:
\_parameter: (SCRATCH_ADDR_H), line:99
|vpiName:SCRATCH_ADDR_H
|INT:9
|vpiParameter:
\_parameter: (SCRATCH_ADDR_L), line:98
|vpiName:SCRATCH_ADDR_L
|INT:8
|vpiParameter:
\_parameter: (SCRATCH_BIT_CHECK), line:100
|vpiName:SCRATCH_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (USE_AMO), line:70
|vpiName:USE_AMO
|INT:1
|vpiParameter:
\_parameter: (USE_BRANCH_PREDICTOR), line:158
|vpiName:USE_BRANCH_PREDICTOR
|INT:2
|vpiParameter:
\_parameter: (USE_BUS), line:88
|vpiName:USE_BUS
|INT:4
|vpiParameter:
\_parameter: (USE_DCACHE), line:92
|vpiName:USE_DCACHE
|INT:6
|vpiParameter:
\_parameter: (USE_DIV), line:49
|vpiName:USE_DIV
|INT:1
|vpiParameter:
\_parameter: (USE_DTAG_INVALIDATIONS), line:140
|vpiName:USE_DTAG_INVALIDATIONS
|INT:1879048191
|vpiParameter:
\_parameter: (USE_D_SCRATCH_MEM), line:79
|vpiName:USE_D_SCRATCH_MEM
|INT:3
|vpiParameter:
\_parameter: (USE_ICACHE), line:93
|vpiName:USE_ICACHE
|INT:7
|vpiParameter:
\_parameter: (USE_I_SCRATCH_MEM), line:78
|vpiName:USE_I_SCRATCH_MEM
|INT:2
|vpiParameter:
\_parameter: (USE_MUL), line:48
|vpiName:USE_MUL
|INT:1
|vpiParameter:
\_parameter: (WB_UNITS_WIDTH), line:187
|vpiName:WB_UNITS_WIDTH
|INT:32
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiParameter:
\_parameter: (i), line:140
|vpiName:i
|INT:3
|vpiGenScopeArray:
\_gen_scope_array: (genblk3[4]), line:140, parent:write_back_mux
|vpiName:genblk3[4]
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk3[4]
|vpiGenScope:
\_gen_scope: , parent:genblk3[4]
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk3[4]
|vpiProcess:
\_always: , line:141
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:141
|vpiCondition:
\_operation: , line:141
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:141
|vpiName:clk
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk3[4].clk
|vpiStmt:
\_begin: , line:141
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk3[4]
|vpiStmt:
\_if_stmt: , line:142
|vpiCondition:
\_operation: , line:142
|vpiOpType:29
|vpiOperand:
\_bit_select: (id_writing_to_buffer), line:142
|vpiName:id_writing_to_buffer
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk3[4].id_writing_to_buffer
|vpiIndex:
\_ref_obj: (i), line:142
|vpiName:i
|vpiOperand:
\_bit_select: (store_mux), line:142
|vpiName:store_mux
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk3[4].store_mux
|vpiIndex:
\_ref_obj: (i), line:142
|vpiName:i
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk3[4].i
|vpiStmt:
\_assignment: , line:143
|vpiOpType:82
|vpiLhs:
\_bit_select: (results_by_id), line:143
|vpiName:results_by_id
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk3[4].results_by_id
|vpiIndex:
\_ref_obj: (i), line:143
|vpiName:i
|vpiRhs:
\_bit_select: (unit_rd), line:143
|vpiName:unit_rd
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk3[4].unit_rd
|vpiIndex:
\_operation: , line:143
|vpiOpType:33
|vpiOperand:
\_bit_select: (store_mux), line:143
|vpiName:store_mux
|vpiIndex:
\_ref_obj: (i), line:143
|vpiName:i
|vpiOperand:
\_bit_select: (id_unit_select), line:143
|vpiName:id_unit_select
|vpiIndex:
\_ref_obj: (i), line:143
|vpiName:i
|vpiParameter:
\_parameter: (ALU_UNIT_WB_ID), line:190
|vpiName:ALU_UNIT_WB_ID
|INT:32
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (BRANCH_PREDICTOR_WAYS), line:159
|vpiName:BRANCH_PREDICTOR_WAYS
|INT:9
|vpiParameter:
\_parameter: (BRANCH_TABLE_ENTRIES), line:160
|vpiName:BRANCH_TABLE_ENTRIES
|INT:4
|vpiParameter:
\_parameter: (BRANCH_UNIT_ID), line:195
|vpiName:BRANCH_UNIT_ID
|INT:8
|vpiParameter:
\_parameter: (BUS_ADDR_H), line:107
|vpiName:BUS_ADDR_H
|INT:1
|vpiParameter:
\_parameter: (BUS_ADDR_L), line:106
|vpiName:BUS_ADDR_L
|INT:0
|vpiParameter:
\_parameter: (BUS_BIT_CHECK), line:108
|vpiName:BUS_BIT_CHECK
|INT:1
|vpiParameter:
\_parameter: (BUS_TYPE), line:89
|vpiName:BUS_TYPE
|INT:5
|vpiParameter:
\_parameter: (COUNTER_W), line:42
|vpiName:COUNTER_W
|INT:33
|vpiParameter:
\_parameter: (CPU_ID), line:38
|vpiName:CPU_ID
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_ADDR_WIDTH), line:113
|vpiName:C_M_AXI_ADDR_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_DATA_WIDTH), line:114
|vpiName:C_M_AXI_DATA_WIDTH
|INT:1
|vpiParameter:
\_parameter: (DCACHE_LINES), line:133
|vpiName:DCACHE_LINES
|INT:-2146435073
|vpiParameter:
\_parameter: (DCACHE_LINE_ADDR_W), line:135
|vpiName:DCACHE_LINE_ADDR_W
|INT:1073741824
|vpiParameter:
\_parameter: (DCACHE_LINE_W), line:136
|vpiName:DCACHE_LINE_W
|INT:1342177279
|vpiParameter:
\_parameter: (DCACHE_SUB_LINE_ADDR_W), line:137
|vpiName:DCACHE_SUB_LINE_ADDR_W
|INT:4
|vpiParameter:
\_parameter: (DCACHE_TAG_W), line:138
|vpiName:DCACHE_TAG_W
|INT:1610612736
|vpiParameter:
\_parameter: (DCACHE_WAYS), line:134
|vpiName:DCACHE_WAYS
|INT:4
|vpiParameter:
\_parameter: (DIV_ALGORITHM), line:67
|vpiName:DIV_ALGORITHM
|INT:0
|vpiParameter:
\_parameter: (DIV_UNIT_WB_ID), line:192
|vpiName:DIV_UNIT_WB_ID
|INT:2
|vpiParameter:
\_parameter: (DTLB_DEPTH), line:152
|vpiName:DTLB_DEPTH
|INT:512
|vpiParameter:
\_parameter: (DTLB_WAYS), line:151
|vpiName:DTLB_WAYS
|INT:32
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (ENABLE_M_MODE), line:34
|vpiName:ENABLE_M_MODE
|INT:1
|vpiParameter:
\_parameter: (ENABLE_S_MODE), line:36
|vpiName:ENABLE_S_MODE
|INT:0
|vpiParameter:
\_parameter: (ENABLE_TRACE_INTERFACE), line:172
|vpiName:ENABLE_TRACE_INTERFACE
|INT:2
|vpiParameter:
\_parameter: (FETCH_BUFFER_DEPTH), line:168
|vpiName:FETCH_BUFFER_DEPTH
|INT:512
|vpiParameter:
\_parameter: (FPGA_VENDOR), line:27
|vpiName:FPGA_VENDOR
|STRING:"xilinx"
|vpiParameter:
\_parameter: (GC_UNIT_ID), line:196
|vpiName:GC_UNIT_ID
|INT:4
|vpiParameter:
\_parameter: (ICACHE_LINES), line:121
|vpiName:ICACHE_LINES
|INT:2
|vpiParameter:
\_parameter: (ICACHE_LINE_ADDR_W), line:123
|vpiName:ICACHE_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_LINE_W), line:124
|vpiName:ICACHE_LINE_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_SUB_LINE_ADDR_W), line:125
|vpiName:ICACHE_SUB_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_TAG_W), line:126
|vpiName:ICACHE_TAG_W
|INT:-2147483648
|vpiParameter:
\_parameter: (ICACHE_WAYS), line:122
|vpiName:ICACHE_WAYS
|INT:1
|vpiParameter:
\_parameter: (ITLB_DEPTH), line:146
|vpiName:ITLB_DEPTH
|INT:32
|vpiParameter:
\_parameter: (ITLB_WAYS), line:145
|vpiName:ITLB_WAYS
|INT:4
|vpiParameter:
\_parameter: (L1_CONNECTIONS), line:177
|vpiName:L1_CONNECTIONS
|INT:9
|vpiParameter:
\_parameter: (L1_DCACHE_ID), line:178
|vpiName:L1_DCACHE_ID
|INT:4
|vpiParameter:
\_parameter: (L1_DMMU_ID), line:179
|vpiName:L1_DMMU_ID
|INT:2
|vpiParameter:
\_parameter: (L1_ICACHE_ID), line:180
|vpiName:L1_ICACHE_ID
|INT:19
|vpiParameter:
\_parameter: (L1_IMMU_ID), line:181
|vpiName:L1_IMMU_ID
|INT:0
|vpiParameter:
\_parameter: (LS_UNIT_WB_ID), line:191
|vpiName:LS_UNIT_WB_ID
|INT:1
|vpiParameter:
\_parameter: (MAX_INFLIGHT_COUNT), line:167
|vpiName:MAX_INFLIGHT_COUNT
|INT:19
|vpiParameter:
\_parameter: (MEMORY_ADDR_H), line:103
|vpiName:MEMORY_ADDR_H
|INT:12
|vpiParameter:
\_parameter: (MEMORY_ADDR_L), line:102
|vpiName:MEMORY_ADDR_L
|INT:11
|vpiParameter:
\_parameter: (MEMORY_BIT_CHECK), line:104
|vpiName:MEMORY_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (MUL_UNIT_WB_ID), line:193
|vpiName:MUL_UNIT_WB_ID
|INT:512
|vpiParameter:
\_parameter: (NUM_UNITS), line:188
|vpiName:NUM_UNITS
|INT:2
|vpiParameter:
\_parameter: (NUM_WB_UNITS), line:186
|vpiName:NUM_WB_UNITS
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (RAS_DEPTH), line:161
|vpiName:RAS_DEPTH
|INT:2
|vpiParameter:
\_parameter: (RESET_VEC), line:39
|vpiName:RESET_VEC
|INT:-2147483648
|vpiParameter:
\_parameter: (SCRATCH_ADDR_H), line:99
|vpiName:SCRATCH_ADDR_H
|INT:9
|vpiParameter:
\_parameter: (SCRATCH_ADDR_L), line:98
|vpiName:SCRATCH_ADDR_L
|INT:8
|vpiParameter:
\_parameter: (SCRATCH_BIT_CHECK), line:100
|vpiName:SCRATCH_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (USE_AMO), line:70
|vpiName:USE_AMO
|INT:1
|vpiParameter:
\_parameter: (USE_BRANCH_PREDICTOR), line:158
|vpiName:USE_BRANCH_PREDICTOR
|INT:2
|vpiParameter:
\_parameter: (USE_BUS), line:88
|vpiName:USE_BUS
|INT:4
|vpiParameter:
\_parameter: (USE_DCACHE), line:92
|vpiName:USE_DCACHE
|INT:6
|vpiParameter:
\_parameter: (USE_DIV), line:49
|vpiName:USE_DIV
|INT:1
|vpiParameter:
\_parameter: (USE_DTAG_INVALIDATIONS), line:140
|vpiName:USE_DTAG_INVALIDATIONS
|INT:1879048191
|vpiParameter:
\_parameter: (USE_D_SCRATCH_MEM), line:79
|vpiName:USE_D_SCRATCH_MEM
|INT:3
|vpiParameter:
\_parameter: (USE_ICACHE), line:93
|vpiName:USE_ICACHE
|INT:7
|vpiParameter:
\_parameter: (USE_I_SCRATCH_MEM), line:78
|vpiName:USE_I_SCRATCH_MEM
|INT:2
|vpiParameter:
\_parameter: (USE_MUL), line:48
|vpiName:USE_MUL
|INT:1
|vpiParameter:
\_parameter: (WB_UNITS_WIDTH), line:187
|vpiName:WB_UNITS_WIDTH
|INT:32
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiParameter:
\_parameter: (i), line:140
|vpiName:i
|INT:4
|vpiGenScopeArray:
\_gen_scope_array: (genblk3[5]), line:140, parent:write_back_mux
|vpiName:genblk3[5]
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk3[5]
|vpiGenScope:
\_gen_scope: , parent:genblk3[5]
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk3[5]
|vpiProcess:
\_always: , line:141
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:141
|vpiCondition:
\_operation: , line:141
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:141
|vpiName:clk
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk3[5].clk
|vpiStmt:
\_begin: , line:141
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk3[5]
|vpiStmt:
\_if_stmt: , line:142
|vpiCondition:
\_operation: , line:142
|vpiOpType:29
|vpiOperand:
\_bit_select: (id_writing_to_buffer), line:142
|vpiName:id_writing_to_buffer
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk3[5].id_writing_to_buffer
|vpiIndex:
\_ref_obj: (i), line:142
|vpiName:i
|vpiOperand:
\_bit_select: (store_mux), line:142
|vpiName:store_mux
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk3[5].store_mux
|vpiIndex:
\_ref_obj: (i), line:142
|vpiName:i
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk3[5].i
|vpiStmt:
\_assignment: , line:143
|vpiOpType:82
|vpiLhs:
\_bit_select: (results_by_id), line:143
|vpiName:results_by_id
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk3[5].results_by_id
|vpiIndex:
\_ref_obj: (i), line:143
|vpiName:i
|vpiRhs:
\_bit_select: (unit_rd), line:143
|vpiName:unit_rd
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk3[5].unit_rd
|vpiIndex:
\_operation: , line:143
|vpiOpType:33
|vpiOperand:
\_bit_select: (store_mux), line:143
|vpiName:store_mux
|vpiIndex:
\_ref_obj: (i), line:143
|vpiName:i
|vpiOperand:
\_bit_select: (id_unit_select), line:143
|vpiName:id_unit_select
|vpiIndex:
\_ref_obj: (i), line:143
|vpiName:i
|vpiParameter:
\_parameter: (ALU_UNIT_WB_ID), line:190
|vpiName:ALU_UNIT_WB_ID
|INT:32
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (BRANCH_PREDICTOR_WAYS), line:159
|vpiName:BRANCH_PREDICTOR_WAYS
|INT:9
|vpiParameter:
\_parameter: (BRANCH_TABLE_ENTRIES), line:160
|vpiName:BRANCH_TABLE_ENTRIES
|INT:4
|vpiParameter:
\_parameter: (BRANCH_UNIT_ID), line:195
|vpiName:BRANCH_UNIT_ID
|INT:8
|vpiParameter:
\_parameter: (BUS_ADDR_H), line:107
|vpiName:BUS_ADDR_H
|INT:1
|vpiParameter:
\_parameter: (BUS_ADDR_L), line:106
|vpiName:BUS_ADDR_L
|INT:0
|vpiParameter:
\_parameter: (BUS_BIT_CHECK), line:108
|vpiName:BUS_BIT_CHECK
|INT:1
|vpiParameter:
\_parameter: (BUS_TYPE), line:89
|vpiName:BUS_TYPE
|INT:5
|vpiParameter:
\_parameter: (COUNTER_W), line:42
|vpiName:COUNTER_W
|INT:33
|vpiParameter:
\_parameter: (CPU_ID), line:38
|vpiName:CPU_ID
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_ADDR_WIDTH), line:113
|vpiName:C_M_AXI_ADDR_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_DATA_WIDTH), line:114
|vpiName:C_M_AXI_DATA_WIDTH
|INT:1
|vpiParameter:
\_parameter: (DCACHE_LINES), line:133
|vpiName:DCACHE_LINES
|INT:-2146435073
|vpiParameter:
\_parameter: (DCACHE_LINE_ADDR_W), line:135
|vpiName:DCACHE_LINE_ADDR_W
|INT:1073741824
|vpiParameter:
\_parameter: (DCACHE_LINE_W), line:136
|vpiName:DCACHE_LINE_W
|INT:1342177279
|vpiParameter:
\_parameter: (DCACHE_SUB_LINE_ADDR_W), line:137
|vpiName:DCACHE_SUB_LINE_ADDR_W
|INT:4
|vpiParameter:
\_parameter: (DCACHE_TAG_W), line:138
|vpiName:DCACHE_TAG_W
|INT:1610612736
|vpiParameter:
\_parameter: (DCACHE_WAYS), line:134
|vpiName:DCACHE_WAYS
|INT:4
|vpiParameter:
\_parameter: (DIV_ALGORITHM), line:67
|vpiName:DIV_ALGORITHM
|INT:0
|vpiParameter:
\_parameter: (DIV_UNIT_WB_ID), line:192
|vpiName:DIV_UNIT_WB_ID
|INT:2
|vpiParameter:
\_parameter: (DTLB_DEPTH), line:152
|vpiName:DTLB_DEPTH
|INT:512
|vpiParameter:
\_parameter: (DTLB_WAYS), line:151
|vpiName:DTLB_WAYS
|INT:32
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (ENABLE_M_MODE), line:34
|vpiName:ENABLE_M_MODE
|INT:1
|vpiParameter:
\_parameter: (ENABLE_S_MODE), line:36
|vpiName:ENABLE_S_MODE
|INT:0
|vpiParameter:
\_parameter: (ENABLE_TRACE_INTERFACE), line:172
|vpiName:ENABLE_TRACE_INTERFACE
|INT:2
|vpiParameter:
\_parameter: (FETCH_BUFFER_DEPTH), line:168
|vpiName:FETCH_BUFFER_DEPTH
|INT:512
|vpiParameter:
\_parameter: (FPGA_VENDOR), line:27
|vpiName:FPGA_VENDOR
|STRING:"xilinx"
|vpiParameter:
\_parameter: (GC_UNIT_ID), line:196
|vpiName:GC_UNIT_ID
|INT:4
|vpiParameter:
\_parameter: (ICACHE_LINES), line:121
|vpiName:ICACHE_LINES
|INT:2
|vpiParameter:
\_parameter: (ICACHE_LINE_ADDR_W), line:123
|vpiName:ICACHE_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_LINE_W), line:124
|vpiName:ICACHE_LINE_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_SUB_LINE_ADDR_W), line:125
|vpiName:ICACHE_SUB_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_TAG_W), line:126
|vpiName:ICACHE_TAG_W
|INT:-2147483648
|vpiParameter:
\_parameter: (ICACHE_WAYS), line:122
|vpiName:ICACHE_WAYS
|INT:1
|vpiParameter:
\_parameter: (ITLB_DEPTH), line:146
|vpiName:ITLB_DEPTH
|INT:32
|vpiParameter:
\_parameter: (ITLB_WAYS), line:145
|vpiName:ITLB_WAYS
|INT:4
|vpiParameter:
\_parameter: (L1_CONNECTIONS), line:177
|vpiName:L1_CONNECTIONS
|INT:9
|vpiParameter:
\_parameter: (L1_DCACHE_ID), line:178
|vpiName:L1_DCACHE_ID
|INT:4
|vpiParameter:
\_parameter: (L1_DMMU_ID), line:179
|vpiName:L1_DMMU_ID
|INT:2
|vpiParameter:
\_parameter: (L1_ICACHE_ID), line:180
|vpiName:L1_ICACHE_ID
|INT:19
|vpiParameter:
\_parameter: (L1_IMMU_ID), line:181
|vpiName:L1_IMMU_ID
|INT:0
|vpiParameter:
\_parameter: (LS_UNIT_WB_ID), line:191
|vpiName:LS_UNIT_WB_ID
|INT:1
|vpiParameter:
\_parameter: (MAX_INFLIGHT_COUNT), line:167
|vpiName:MAX_INFLIGHT_COUNT
|INT:19
|vpiParameter:
\_parameter: (MEMORY_ADDR_H), line:103
|vpiName:MEMORY_ADDR_H
|INT:12
|vpiParameter:
\_parameter: (MEMORY_ADDR_L), line:102
|vpiName:MEMORY_ADDR_L
|INT:11
|vpiParameter:
\_parameter: (MEMORY_BIT_CHECK), line:104
|vpiName:MEMORY_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (MUL_UNIT_WB_ID), line:193
|vpiName:MUL_UNIT_WB_ID
|INT:512
|vpiParameter:
\_parameter: (NUM_UNITS), line:188
|vpiName:NUM_UNITS
|INT:2
|vpiParameter:
\_parameter: (NUM_WB_UNITS), line:186
|vpiName:NUM_WB_UNITS
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (RAS_DEPTH), line:161
|vpiName:RAS_DEPTH
|INT:2
|vpiParameter:
\_parameter: (RESET_VEC), line:39
|vpiName:RESET_VEC
|INT:-2147483648
|vpiParameter:
\_parameter: (SCRATCH_ADDR_H), line:99
|vpiName:SCRATCH_ADDR_H
|INT:9
|vpiParameter:
\_parameter: (SCRATCH_ADDR_L), line:98
|vpiName:SCRATCH_ADDR_L
|INT:8
|vpiParameter:
\_parameter: (SCRATCH_BIT_CHECK), line:100
|vpiName:SCRATCH_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (USE_AMO), line:70
|vpiName:USE_AMO
|INT:1
|vpiParameter:
\_parameter: (USE_BRANCH_PREDICTOR), line:158
|vpiName:USE_BRANCH_PREDICTOR
|INT:2
|vpiParameter:
\_parameter: (USE_BUS), line:88
|vpiName:USE_BUS
|INT:4
|vpiParameter:
\_parameter: (USE_DCACHE), line:92
|vpiName:USE_DCACHE
|INT:6
|vpiParameter:
\_parameter: (USE_DIV), line:49
|vpiName:USE_DIV
|INT:1
|vpiParameter:
\_parameter: (USE_DTAG_INVALIDATIONS), line:140
|vpiName:USE_DTAG_INVALIDATIONS
|INT:1879048191
|vpiParameter:
\_parameter: (USE_D_SCRATCH_MEM), line:79
|vpiName:USE_D_SCRATCH_MEM
|INT:3
|vpiParameter:
\_parameter: (USE_ICACHE), line:93
|vpiName:USE_ICACHE
|INT:7
|vpiParameter:
\_parameter: (USE_I_SCRATCH_MEM), line:78
|vpiName:USE_I_SCRATCH_MEM
|INT:2
|vpiParameter:
\_parameter: (USE_MUL), line:48
|vpiName:USE_MUL
|INT:1
|vpiParameter:
\_parameter: (WB_UNITS_WIDTH), line:187
|vpiName:WB_UNITS_WIDTH
|INT:32
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiParameter:
\_parameter: (i), line:140
|vpiName:i
|INT:5
|vpiGenScopeArray:
\_gen_scope_array: (genblk3[6]), line:140, parent:write_back_mux
|vpiName:genblk3[6]
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk3[6]
|vpiGenScope:
\_gen_scope: , parent:genblk3[6]
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk3[6]
|vpiProcess:
\_always: , line:141
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:141
|vpiCondition:
\_operation: , line:141
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:141
|vpiName:clk
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk3[6].clk
|vpiStmt:
\_begin: , line:141
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk3[6]
|vpiStmt:
\_if_stmt: , line:142
|vpiCondition:
\_operation: , line:142
|vpiOpType:29
|vpiOperand:
\_bit_select: (id_writing_to_buffer), line:142
|vpiName:id_writing_to_buffer
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk3[6].id_writing_to_buffer
|vpiIndex:
\_ref_obj: (i), line:142
|vpiName:i
|vpiOperand:
\_bit_select: (store_mux), line:142
|vpiName:store_mux
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk3[6].store_mux
|vpiIndex:
\_ref_obj: (i), line:142
|vpiName:i
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk3[6].i
|vpiStmt:
\_assignment: , line:143
|vpiOpType:82
|vpiLhs:
\_bit_select: (results_by_id), line:143
|vpiName:results_by_id
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk3[6].results_by_id
|vpiIndex:
\_ref_obj: (i), line:143
|vpiName:i
|vpiRhs:
\_bit_select: (unit_rd), line:143
|vpiName:unit_rd
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk3[6].unit_rd
|vpiIndex:
\_operation: , line:143
|vpiOpType:33
|vpiOperand:
\_bit_select: (store_mux), line:143
|vpiName:store_mux
|vpiIndex:
\_ref_obj: (i), line:143
|vpiName:i
|vpiOperand:
\_bit_select: (id_unit_select), line:143
|vpiName:id_unit_select
|vpiIndex:
\_ref_obj: (i), line:143
|vpiName:i
|vpiParameter:
\_parameter: (ALU_UNIT_WB_ID), line:190
|vpiName:ALU_UNIT_WB_ID
|INT:32
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (BRANCH_PREDICTOR_WAYS), line:159
|vpiName:BRANCH_PREDICTOR_WAYS
|INT:9
|vpiParameter:
\_parameter: (BRANCH_TABLE_ENTRIES), line:160
|vpiName:BRANCH_TABLE_ENTRIES
|INT:4
|vpiParameter:
\_parameter: (BRANCH_UNIT_ID), line:195
|vpiName:BRANCH_UNIT_ID
|INT:8
|vpiParameter:
\_parameter: (BUS_ADDR_H), line:107
|vpiName:BUS_ADDR_H
|INT:1
|vpiParameter:
\_parameter: (BUS_ADDR_L), line:106
|vpiName:BUS_ADDR_L
|INT:0
|vpiParameter:
\_parameter: (BUS_BIT_CHECK), line:108
|vpiName:BUS_BIT_CHECK
|INT:1
|vpiParameter:
\_parameter: (BUS_TYPE), line:89
|vpiName:BUS_TYPE
|INT:5
|vpiParameter:
\_parameter: (COUNTER_W), line:42
|vpiName:COUNTER_W
|INT:33
|vpiParameter:
\_parameter: (CPU_ID), line:38
|vpiName:CPU_ID
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_ADDR_WIDTH), line:113
|vpiName:C_M_AXI_ADDR_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_DATA_WIDTH), line:114
|vpiName:C_M_AXI_DATA_WIDTH
|INT:1
|vpiParameter:
\_parameter: (DCACHE_LINES), line:133
|vpiName:DCACHE_LINES
|INT:-2146435073
|vpiParameter:
\_parameter: (DCACHE_LINE_ADDR_W), line:135
|vpiName:DCACHE_LINE_ADDR_W
|INT:1073741824
|vpiParameter:
\_parameter: (DCACHE_LINE_W), line:136
|vpiName:DCACHE_LINE_W
|INT:1342177279
|vpiParameter:
\_parameter: (DCACHE_SUB_LINE_ADDR_W), line:137
|vpiName:DCACHE_SUB_LINE_ADDR_W
|INT:4
|vpiParameter:
\_parameter: (DCACHE_TAG_W), line:138
|vpiName:DCACHE_TAG_W
|INT:1610612736
|vpiParameter:
\_parameter: (DCACHE_WAYS), line:134
|vpiName:DCACHE_WAYS
|INT:4
|vpiParameter:
\_parameter: (DIV_ALGORITHM), line:67
|vpiName:DIV_ALGORITHM
|INT:0
|vpiParameter:
\_parameter: (DIV_UNIT_WB_ID), line:192
|vpiName:DIV_UNIT_WB_ID
|INT:2
|vpiParameter:
\_parameter: (DTLB_DEPTH), line:152
|vpiName:DTLB_DEPTH
|INT:512
|vpiParameter:
\_parameter: (DTLB_WAYS), line:151
|vpiName:DTLB_WAYS
|INT:32
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (ENABLE_M_MODE), line:34
|vpiName:ENABLE_M_MODE
|INT:1
|vpiParameter:
\_parameter: (ENABLE_S_MODE), line:36
|vpiName:ENABLE_S_MODE
|INT:0
|vpiParameter:
\_parameter: (ENABLE_TRACE_INTERFACE), line:172
|vpiName:ENABLE_TRACE_INTERFACE
|INT:2
|vpiParameter:
\_parameter: (FETCH_BUFFER_DEPTH), line:168
|vpiName:FETCH_BUFFER_DEPTH
|INT:512
|vpiParameter:
\_parameter: (FPGA_VENDOR), line:27
|vpiName:FPGA_VENDOR
|STRING:"xilinx"
|vpiParameter:
\_parameter: (GC_UNIT_ID), line:196
|vpiName:GC_UNIT_ID
|INT:4
|vpiParameter:
\_parameter: (ICACHE_LINES), line:121
|vpiName:ICACHE_LINES
|INT:2
|vpiParameter:
\_parameter: (ICACHE_LINE_ADDR_W), line:123
|vpiName:ICACHE_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_LINE_W), line:124
|vpiName:ICACHE_LINE_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_SUB_LINE_ADDR_W), line:125
|vpiName:ICACHE_SUB_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_TAG_W), line:126
|vpiName:ICACHE_TAG_W
|INT:-2147483648
|vpiParameter:
\_parameter: (ICACHE_WAYS), line:122
|vpiName:ICACHE_WAYS
|INT:1
|vpiParameter:
\_parameter: (ITLB_DEPTH), line:146
|vpiName:ITLB_DEPTH
|INT:32
|vpiParameter:
\_parameter: (ITLB_WAYS), line:145
|vpiName:ITLB_WAYS
|INT:4
|vpiParameter:
\_parameter: (L1_CONNECTIONS), line:177
|vpiName:L1_CONNECTIONS
|INT:9
|vpiParameter:
\_parameter: (L1_DCACHE_ID), line:178
|vpiName:L1_DCACHE_ID
|INT:4
|vpiParameter:
\_parameter: (L1_DMMU_ID), line:179
|vpiName:L1_DMMU_ID
|INT:2
|vpiParameter:
\_parameter: (L1_ICACHE_ID), line:180
|vpiName:L1_ICACHE_ID
|INT:19
|vpiParameter:
\_parameter: (L1_IMMU_ID), line:181
|vpiName:L1_IMMU_ID
|INT:0
|vpiParameter:
\_parameter: (LS_UNIT_WB_ID), line:191
|vpiName:LS_UNIT_WB_ID
|INT:1
|vpiParameter:
\_parameter: (MAX_INFLIGHT_COUNT), line:167
|vpiName:MAX_INFLIGHT_COUNT
|INT:19
|vpiParameter:
\_parameter: (MEMORY_ADDR_H), line:103
|vpiName:MEMORY_ADDR_H
|INT:12
|vpiParameter:
\_parameter: (MEMORY_ADDR_L), line:102
|vpiName:MEMORY_ADDR_L
|INT:11
|vpiParameter:
\_parameter: (MEMORY_BIT_CHECK), line:104
|vpiName:MEMORY_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (MUL_UNIT_WB_ID), line:193
|vpiName:MUL_UNIT_WB_ID
|INT:512
|vpiParameter:
\_parameter: (NUM_UNITS), line:188
|vpiName:NUM_UNITS
|INT:2
|vpiParameter:
\_parameter: (NUM_WB_UNITS), line:186
|vpiName:NUM_WB_UNITS
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (RAS_DEPTH), line:161
|vpiName:RAS_DEPTH
|INT:2
|vpiParameter:
\_parameter: (RESET_VEC), line:39
|vpiName:RESET_VEC
|INT:-2147483648
|vpiParameter:
\_parameter: (SCRATCH_ADDR_H), line:99
|vpiName:SCRATCH_ADDR_H
|INT:9
|vpiParameter:
\_parameter: (SCRATCH_ADDR_L), line:98
|vpiName:SCRATCH_ADDR_L
|INT:8
|vpiParameter:
\_parameter: (SCRATCH_BIT_CHECK), line:100
|vpiName:SCRATCH_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (USE_AMO), line:70
|vpiName:USE_AMO
|INT:1
|vpiParameter:
\_parameter: (USE_BRANCH_PREDICTOR), line:158
|vpiName:USE_BRANCH_PREDICTOR
|INT:2
|vpiParameter:
\_parameter: (USE_BUS), line:88
|vpiName:USE_BUS
|INT:4
|vpiParameter:
\_parameter: (USE_DCACHE), line:92
|vpiName:USE_DCACHE
|INT:6
|vpiParameter:
\_parameter: (USE_DIV), line:49
|vpiName:USE_DIV
|INT:1
|vpiParameter:
\_parameter: (USE_DTAG_INVALIDATIONS), line:140
|vpiName:USE_DTAG_INVALIDATIONS
|INT:1879048191
|vpiParameter:
\_parameter: (USE_D_SCRATCH_MEM), line:79
|vpiName:USE_D_SCRATCH_MEM
|INT:3
|vpiParameter:
\_parameter: (USE_ICACHE), line:93
|vpiName:USE_ICACHE
|INT:7
|vpiParameter:
\_parameter: (USE_I_SCRATCH_MEM), line:78
|vpiName:USE_I_SCRATCH_MEM
|INT:2
|vpiParameter:
\_parameter: (USE_MUL), line:48
|vpiName:USE_MUL
|INT:1
|vpiParameter:
\_parameter: (WB_UNITS_WIDTH), line:187
|vpiName:WB_UNITS_WIDTH
|INT:32
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiParameter:
\_parameter: (i), line:140
|vpiName:i
|INT:6
|vpiGenScopeArray:
\_gen_scope_array: (genblk3[7]), line:140, parent:write_back_mux
|vpiName:genblk3[7]
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk3[7]
|vpiGenScope:
\_gen_scope: , parent:genblk3[7]
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk3[7]
|vpiProcess:
\_always: , line:141
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:141
|vpiCondition:
\_operation: , line:141
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:141
|vpiName:clk
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk3[7].clk
|vpiStmt:
\_begin: , line:141
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk3[7]
|vpiStmt:
\_if_stmt: , line:142
|vpiCondition:
\_operation: , line:142
|vpiOpType:29
|vpiOperand:
\_bit_select: (id_writing_to_buffer), line:142
|vpiName:id_writing_to_buffer
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk3[7].id_writing_to_buffer
|vpiIndex:
\_ref_obj: (i), line:142
|vpiName:i
|vpiOperand:
\_bit_select: (store_mux), line:142
|vpiName:store_mux
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk3[7].store_mux
|vpiIndex:
\_ref_obj: (i), line:142
|vpiName:i
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk3[7].i
|vpiStmt:
\_assignment: , line:143
|vpiOpType:82
|vpiLhs:
\_bit_select: (results_by_id), line:143
|vpiName:results_by_id
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk3[7].results_by_id
|vpiIndex:
\_ref_obj: (i), line:143
|vpiName:i
|vpiRhs:
\_bit_select: (unit_rd), line:143
|vpiName:unit_rd
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk3[7].unit_rd
|vpiIndex:
\_operation: , line:143
|vpiOpType:33
|vpiOperand:
\_bit_select: (store_mux), line:143
|vpiName:store_mux
|vpiIndex:
\_ref_obj: (i), line:143
|vpiName:i
|vpiOperand:
\_bit_select: (id_unit_select), line:143
|vpiName:id_unit_select
|vpiIndex:
\_ref_obj: (i), line:143
|vpiName:i
|vpiParameter:
\_parameter: (ALU_UNIT_WB_ID), line:190
|vpiName:ALU_UNIT_WB_ID
|INT:32
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (BRANCH_PREDICTOR_WAYS), line:159
|vpiName:BRANCH_PREDICTOR_WAYS
|INT:9
|vpiParameter:
\_parameter: (BRANCH_TABLE_ENTRIES), line:160
|vpiName:BRANCH_TABLE_ENTRIES
|INT:4
|vpiParameter:
\_parameter: (BRANCH_UNIT_ID), line:195
|vpiName:BRANCH_UNIT_ID
|INT:8
|vpiParameter:
\_parameter: (BUS_ADDR_H), line:107
|vpiName:BUS_ADDR_H
|INT:1
|vpiParameter:
\_parameter: (BUS_ADDR_L), line:106
|vpiName:BUS_ADDR_L
|INT:0
|vpiParameter:
\_parameter: (BUS_BIT_CHECK), line:108
|vpiName:BUS_BIT_CHECK
|INT:1
|vpiParameter:
\_parameter: (BUS_TYPE), line:89
|vpiName:BUS_TYPE
|INT:5
|vpiParameter:
\_parameter: (COUNTER_W), line:42
|vpiName:COUNTER_W
|INT:33
|vpiParameter:
\_parameter: (CPU_ID), line:38
|vpiName:CPU_ID
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_ADDR_WIDTH), line:113
|vpiName:C_M_AXI_ADDR_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_DATA_WIDTH), line:114
|vpiName:C_M_AXI_DATA_WIDTH
|INT:1
|vpiParameter:
\_parameter: (DCACHE_LINES), line:133
|vpiName:DCACHE_LINES
|INT:-2146435073
|vpiParameter:
\_parameter: (DCACHE_LINE_ADDR_W), line:135
|vpiName:DCACHE_LINE_ADDR_W
|INT:1073741824
|vpiParameter:
\_parameter: (DCACHE_LINE_W), line:136
|vpiName:DCACHE_LINE_W
|INT:1342177279
|vpiParameter:
\_parameter: (DCACHE_SUB_LINE_ADDR_W), line:137
|vpiName:DCACHE_SUB_LINE_ADDR_W
|INT:4
|vpiParameter:
\_parameter: (DCACHE_TAG_W), line:138
|vpiName:DCACHE_TAG_W
|INT:1610612736
|vpiParameter:
\_parameter: (DCACHE_WAYS), line:134
|vpiName:DCACHE_WAYS
|INT:4
|vpiParameter:
\_parameter: (DIV_ALGORITHM), line:67
|vpiName:DIV_ALGORITHM
|INT:0
|vpiParameter:
\_parameter: (DIV_UNIT_WB_ID), line:192
|vpiName:DIV_UNIT_WB_ID
|INT:2
|vpiParameter:
\_parameter: (DTLB_DEPTH), line:152
|vpiName:DTLB_DEPTH
|INT:512
|vpiParameter:
\_parameter: (DTLB_WAYS), line:151
|vpiName:DTLB_WAYS
|INT:32
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (ENABLE_M_MODE), line:34
|vpiName:ENABLE_M_MODE
|INT:1
|vpiParameter:
\_parameter: (ENABLE_S_MODE), line:36
|vpiName:ENABLE_S_MODE
|INT:0
|vpiParameter:
\_parameter: (ENABLE_TRACE_INTERFACE), line:172
|vpiName:ENABLE_TRACE_INTERFACE
|INT:2
|vpiParameter:
\_parameter: (FETCH_BUFFER_DEPTH), line:168
|vpiName:FETCH_BUFFER_DEPTH
|INT:512
|vpiParameter:
\_parameter: (FPGA_VENDOR), line:27
|vpiName:FPGA_VENDOR
|STRING:"xilinx"
|vpiParameter:
\_parameter: (GC_UNIT_ID), line:196
|vpiName:GC_UNIT_ID
|INT:4
|vpiParameter:
\_parameter: (ICACHE_LINES), line:121
|vpiName:ICACHE_LINES
|INT:2
|vpiParameter:
\_parameter: (ICACHE_LINE_ADDR_W), line:123
|vpiName:ICACHE_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_LINE_W), line:124
|vpiName:ICACHE_LINE_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_SUB_LINE_ADDR_W), line:125
|vpiName:ICACHE_SUB_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_TAG_W), line:126
|vpiName:ICACHE_TAG_W
|INT:-2147483648
|vpiParameter:
\_parameter: (ICACHE_WAYS), line:122
|vpiName:ICACHE_WAYS
|INT:1
|vpiParameter:
\_parameter: (ITLB_DEPTH), line:146
|vpiName:ITLB_DEPTH
|INT:32
|vpiParameter:
\_parameter: (ITLB_WAYS), line:145
|vpiName:ITLB_WAYS
|INT:4
|vpiParameter:
\_parameter: (L1_CONNECTIONS), line:177
|vpiName:L1_CONNECTIONS
|INT:9
|vpiParameter:
\_parameter: (L1_DCACHE_ID), line:178
|vpiName:L1_DCACHE_ID
|INT:4
|vpiParameter:
\_parameter: (L1_DMMU_ID), line:179
|vpiName:L1_DMMU_ID
|INT:2
|vpiParameter:
\_parameter: (L1_ICACHE_ID), line:180
|vpiName:L1_ICACHE_ID
|INT:19
|vpiParameter:
\_parameter: (L1_IMMU_ID), line:181
|vpiName:L1_IMMU_ID
|INT:0
|vpiParameter:
\_parameter: (LS_UNIT_WB_ID), line:191
|vpiName:LS_UNIT_WB_ID
|INT:1
|vpiParameter:
\_parameter: (MAX_INFLIGHT_COUNT), line:167
|vpiName:MAX_INFLIGHT_COUNT
|INT:19
|vpiParameter:
\_parameter: (MEMORY_ADDR_H), line:103
|vpiName:MEMORY_ADDR_H
|INT:12
|vpiParameter:
\_parameter: (MEMORY_ADDR_L), line:102
|vpiName:MEMORY_ADDR_L
|INT:11
|vpiParameter:
\_parameter: (MEMORY_BIT_CHECK), line:104
|vpiName:MEMORY_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (MUL_UNIT_WB_ID), line:193
|vpiName:MUL_UNIT_WB_ID
|INT:512
|vpiParameter:
\_parameter: (NUM_UNITS), line:188
|vpiName:NUM_UNITS
|INT:2
|vpiParameter:
\_parameter: (NUM_WB_UNITS), line:186
|vpiName:NUM_WB_UNITS
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (RAS_DEPTH), line:161
|vpiName:RAS_DEPTH
|INT:2
|vpiParameter:
\_parameter: (RESET_VEC), line:39
|vpiName:RESET_VEC
|INT:-2147483648
|vpiParameter:
\_parameter: (SCRATCH_ADDR_H), line:99
|vpiName:SCRATCH_ADDR_H
|INT:9
|vpiParameter:
\_parameter: (SCRATCH_ADDR_L), line:98
|vpiName:SCRATCH_ADDR_L
|INT:8
|vpiParameter:
\_parameter: (SCRATCH_BIT_CHECK), line:100
|vpiName:SCRATCH_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (USE_AMO), line:70
|vpiName:USE_AMO
|INT:1
|vpiParameter:
\_parameter: (USE_BRANCH_PREDICTOR), line:158
|vpiName:USE_BRANCH_PREDICTOR
|INT:2
|vpiParameter:
\_parameter: (USE_BUS), line:88
|vpiName:USE_BUS
|INT:4
|vpiParameter:
\_parameter: (USE_DCACHE), line:92
|vpiName:USE_DCACHE
|INT:6
|vpiParameter:
\_parameter: (USE_DIV), line:49
|vpiName:USE_DIV
|INT:1
|vpiParameter:
\_parameter: (USE_DTAG_INVALIDATIONS), line:140
|vpiName:USE_DTAG_INVALIDATIONS
|INT:1879048191
|vpiParameter:
\_parameter: (USE_D_SCRATCH_MEM), line:79
|vpiName:USE_D_SCRATCH_MEM
|INT:3
|vpiParameter:
\_parameter: (USE_ICACHE), line:93
|vpiName:USE_ICACHE
|INT:7
|vpiParameter:
\_parameter: (USE_I_SCRATCH_MEM), line:78
|vpiName:USE_I_SCRATCH_MEM
|INT:2
|vpiParameter:
\_parameter: (USE_MUL), line:48
|vpiName:USE_MUL
|INT:1
|vpiParameter:
\_parameter: (WB_UNITS_WIDTH), line:187
|vpiName:WB_UNITS_WIDTH
|INT:32
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiParameter:
\_parameter: (i), line:140
|vpiName:i
|INT:7
|vpiGenScopeArray:
\_gen_scope_array: (genblk3[8]), line:140, parent:write_back_mux
|vpiName:genblk3[8]
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk3[8]
|vpiGenScope:
\_gen_scope: , parent:genblk3[8]
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk3[8]
|vpiProcess:
\_always: , line:141
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:141
|vpiCondition:
\_operation: , line:141
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:141
|vpiName:clk
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk3[8].clk
|vpiStmt:
\_begin: , line:141
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk3[8]
|vpiStmt:
\_if_stmt: , line:142
|vpiCondition:
\_operation: , line:142
|vpiOpType:29
|vpiOperand:
\_bit_select: (id_writing_to_buffer), line:142
|vpiName:id_writing_to_buffer
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk3[8].id_writing_to_buffer
|vpiIndex:
\_ref_obj: (i), line:142
|vpiName:i
|vpiOperand:
\_bit_select: (store_mux), line:142
|vpiName:store_mux
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk3[8].store_mux
|vpiIndex:
\_ref_obj: (i), line:142
|vpiName:i
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk3[8].i
|vpiStmt:
\_assignment: , line:143
|vpiOpType:82
|vpiLhs:
\_bit_select: (results_by_id), line:143
|vpiName:results_by_id
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk3[8].results_by_id
|vpiIndex:
\_ref_obj: (i), line:143
|vpiName:i
|vpiRhs:
\_bit_select: (unit_rd), line:143
|vpiName:unit_rd
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk3[8].unit_rd
|vpiIndex:
\_operation: , line:143
|vpiOpType:33
|vpiOperand:
\_bit_select: (store_mux), line:143
|vpiName:store_mux
|vpiIndex:
\_ref_obj: (i), line:143
|vpiName:i
|vpiOperand:
\_bit_select: (id_unit_select), line:143
|vpiName:id_unit_select
|vpiIndex:
\_ref_obj: (i), line:143
|vpiName:i
|vpiParameter:
\_parameter: (ALU_UNIT_WB_ID), line:190
|vpiName:ALU_UNIT_WB_ID
|INT:32
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (BRANCH_PREDICTOR_WAYS), line:159
|vpiName:BRANCH_PREDICTOR_WAYS
|INT:9
|vpiParameter:
\_parameter: (BRANCH_TABLE_ENTRIES), line:160
|vpiName:BRANCH_TABLE_ENTRIES
|INT:4
|vpiParameter:
\_parameter: (BRANCH_UNIT_ID), line:195
|vpiName:BRANCH_UNIT_ID
|INT:8
|vpiParameter:
\_parameter: (BUS_ADDR_H), line:107
|vpiName:BUS_ADDR_H
|INT:1
|vpiParameter:
\_parameter: (BUS_ADDR_L), line:106
|vpiName:BUS_ADDR_L
|INT:0
|vpiParameter:
\_parameter: (BUS_BIT_CHECK), line:108
|vpiName:BUS_BIT_CHECK
|INT:1
|vpiParameter:
\_parameter: (BUS_TYPE), line:89
|vpiName:BUS_TYPE
|INT:5
|vpiParameter:
\_parameter: (COUNTER_W), line:42
|vpiName:COUNTER_W
|INT:33
|vpiParameter:
\_parameter: (CPU_ID), line:38
|vpiName:CPU_ID
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_ADDR_WIDTH), line:113
|vpiName:C_M_AXI_ADDR_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_DATA_WIDTH), line:114
|vpiName:C_M_AXI_DATA_WIDTH
|INT:1
|vpiParameter:
\_parameter: (DCACHE_LINES), line:133
|vpiName:DCACHE_LINES
|INT:-2146435073
|vpiParameter:
\_parameter: (DCACHE_LINE_ADDR_W), line:135
|vpiName:DCACHE_LINE_ADDR_W
|INT:1073741824
|vpiParameter:
\_parameter: (DCACHE_LINE_W), line:136
|vpiName:DCACHE_LINE_W
|INT:1342177279
|vpiParameter:
\_parameter: (DCACHE_SUB_LINE_ADDR_W), line:137
|vpiName:DCACHE_SUB_LINE_ADDR_W
|INT:4
|vpiParameter:
\_parameter: (DCACHE_TAG_W), line:138
|vpiName:DCACHE_TAG_W
|INT:1610612736
|vpiParameter:
\_parameter: (DCACHE_WAYS), line:134
|vpiName:DCACHE_WAYS
|INT:4
|vpiParameter:
\_parameter: (DIV_ALGORITHM), line:67
|vpiName:DIV_ALGORITHM
|INT:0
|vpiParameter:
\_parameter: (DIV_UNIT_WB_ID), line:192
|vpiName:DIV_UNIT_WB_ID
|INT:2
|vpiParameter:
\_parameter: (DTLB_DEPTH), line:152
|vpiName:DTLB_DEPTH
|INT:512
|vpiParameter:
\_parameter: (DTLB_WAYS), line:151
|vpiName:DTLB_WAYS
|INT:32
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (ENABLE_M_MODE), line:34
|vpiName:ENABLE_M_MODE
|INT:1
|vpiParameter:
\_parameter: (ENABLE_S_MODE), line:36
|vpiName:ENABLE_S_MODE
|INT:0
|vpiParameter:
\_parameter: (ENABLE_TRACE_INTERFACE), line:172
|vpiName:ENABLE_TRACE_INTERFACE
|INT:2
|vpiParameter:
\_parameter: (FETCH_BUFFER_DEPTH), line:168
|vpiName:FETCH_BUFFER_DEPTH
|INT:512
|vpiParameter:
\_parameter: (FPGA_VENDOR), line:27
|vpiName:FPGA_VENDOR
|STRING:"xilinx"
|vpiParameter:
\_parameter: (GC_UNIT_ID), line:196
|vpiName:GC_UNIT_ID
|INT:4
|vpiParameter:
\_parameter: (ICACHE_LINES), line:121
|vpiName:ICACHE_LINES
|INT:2
|vpiParameter:
\_parameter: (ICACHE_LINE_ADDR_W), line:123
|vpiName:ICACHE_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_LINE_W), line:124
|vpiName:ICACHE_LINE_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_SUB_LINE_ADDR_W), line:125
|vpiName:ICACHE_SUB_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_TAG_W), line:126
|vpiName:ICACHE_TAG_W
|INT:-2147483648
|vpiParameter:
\_parameter: (ICACHE_WAYS), line:122
|vpiName:ICACHE_WAYS
|INT:1
|vpiParameter:
\_parameter: (ITLB_DEPTH), line:146
|vpiName:ITLB_DEPTH
|INT:32
|vpiParameter:
\_parameter: (ITLB_WAYS), line:145
|vpiName:ITLB_WAYS
|INT:4
|vpiParameter:
\_parameter: (L1_CONNECTIONS), line:177
|vpiName:L1_CONNECTIONS
|INT:9
|vpiParameter:
\_parameter: (L1_DCACHE_ID), line:178
|vpiName:L1_DCACHE_ID
|INT:4
|vpiParameter:
\_parameter: (L1_DMMU_ID), line:179
|vpiName:L1_DMMU_ID
|INT:2
|vpiParameter:
\_parameter: (L1_ICACHE_ID), line:180
|vpiName:L1_ICACHE_ID
|INT:19
|vpiParameter:
\_parameter: (L1_IMMU_ID), line:181
|vpiName:L1_IMMU_ID
|INT:0
|vpiParameter:
\_parameter: (LS_UNIT_WB_ID), line:191
|vpiName:LS_UNIT_WB_ID
|INT:1
|vpiParameter:
\_parameter: (MAX_INFLIGHT_COUNT), line:167
|vpiName:MAX_INFLIGHT_COUNT
|INT:19
|vpiParameter:
\_parameter: (MEMORY_ADDR_H), line:103
|vpiName:MEMORY_ADDR_H
|INT:12
|vpiParameter:
\_parameter: (MEMORY_ADDR_L), line:102
|vpiName:MEMORY_ADDR_L
|INT:11
|vpiParameter:
\_parameter: (MEMORY_BIT_CHECK), line:104
|vpiName:MEMORY_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (MUL_UNIT_WB_ID), line:193
|vpiName:MUL_UNIT_WB_ID
|INT:512
|vpiParameter:
\_parameter: (NUM_UNITS), line:188
|vpiName:NUM_UNITS
|INT:2
|vpiParameter:
\_parameter: (NUM_WB_UNITS), line:186
|vpiName:NUM_WB_UNITS
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (RAS_DEPTH), line:161
|vpiName:RAS_DEPTH
|INT:2
|vpiParameter:
\_parameter: (RESET_VEC), line:39
|vpiName:RESET_VEC
|INT:-2147483648
|vpiParameter:
\_parameter: (SCRATCH_ADDR_H), line:99
|vpiName:SCRATCH_ADDR_H
|INT:9
|vpiParameter:
\_parameter: (SCRATCH_ADDR_L), line:98
|vpiName:SCRATCH_ADDR_L
|INT:8
|vpiParameter:
\_parameter: (SCRATCH_BIT_CHECK), line:100
|vpiName:SCRATCH_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (USE_AMO), line:70
|vpiName:USE_AMO
|INT:1
|vpiParameter:
\_parameter: (USE_BRANCH_PREDICTOR), line:158
|vpiName:USE_BRANCH_PREDICTOR
|INT:2
|vpiParameter:
\_parameter: (USE_BUS), line:88
|vpiName:USE_BUS
|INT:4
|vpiParameter:
\_parameter: (USE_DCACHE), line:92
|vpiName:USE_DCACHE
|INT:6
|vpiParameter:
\_parameter: (USE_DIV), line:49
|vpiName:USE_DIV
|INT:1
|vpiParameter:
\_parameter: (USE_DTAG_INVALIDATIONS), line:140
|vpiName:USE_DTAG_INVALIDATIONS
|INT:1879048191
|vpiParameter:
\_parameter: (USE_D_SCRATCH_MEM), line:79
|vpiName:USE_D_SCRATCH_MEM
|INT:3
|vpiParameter:
\_parameter: (USE_ICACHE), line:93
|vpiName:USE_ICACHE
|INT:7
|vpiParameter:
\_parameter: (USE_I_SCRATCH_MEM), line:78
|vpiName:USE_I_SCRATCH_MEM
|INT:2
|vpiParameter:
\_parameter: (USE_MUL), line:48
|vpiName:USE_MUL
|INT:1
|vpiParameter:
\_parameter: (WB_UNITS_WIDTH), line:187
|vpiName:WB_UNITS_WIDTH
|INT:32
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiParameter:
\_parameter: (i), line:140
|vpiName:i
|INT:8
|vpiGenScopeArray:
\_gen_scope_array: (genblk3[9]), line:140, parent:write_back_mux
|vpiName:genblk3[9]
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk3[9]
|vpiGenScope:
\_gen_scope: , parent:genblk3[9]
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk3[9]
|vpiProcess:
\_always: , line:141
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:141
|vpiCondition:
\_operation: , line:141
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:141
|vpiName:clk
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk3[9].clk
|vpiStmt:
\_begin: , line:141
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk3[9]
|vpiStmt:
\_if_stmt: , line:142
|vpiCondition:
\_operation: , line:142
|vpiOpType:29
|vpiOperand:
\_bit_select: (id_writing_to_buffer), line:142
|vpiName:id_writing_to_buffer
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk3[9].id_writing_to_buffer
|vpiIndex:
\_ref_obj: (i), line:142
|vpiName:i
|vpiOperand:
\_bit_select: (store_mux), line:142
|vpiName:store_mux
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk3[9].store_mux
|vpiIndex:
\_ref_obj: (i), line:142
|vpiName:i
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk3[9].i
|vpiStmt:
\_assignment: , line:143
|vpiOpType:82
|vpiLhs:
\_bit_select: (results_by_id), line:143
|vpiName:results_by_id
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk3[9].results_by_id
|vpiIndex:
\_ref_obj: (i), line:143
|vpiName:i
|vpiRhs:
\_bit_select: (unit_rd), line:143
|vpiName:unit_rd
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk3[9].unit_rd
|vpiIndex:
\_operation: , line:143
|vpiOpType:33
|vpiOperand:
\_bit_select: (store_mux), line:143
|vpiName:store_mux
|vpiIndex:
\_ref_obj: (i), line:143
|vpiName:i
|vpiOperand:
\_bit_select: (id_unit_select), line:143
|vpiName:id_unit_select
|vpiIndex:
\_ref_obj: (i), line:143
|vpiName:i
|vpiParameter:
\_parameter: (ALU_UNIT_WB_ID), line:190
|vpiName:ALU_UNIT_WB_ID
|INT:32
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (BRANCH_PREDICTOR_WAYS), line:159
|vpiName:BRANCH_PREDICTOR_WAYS
|INT:9
|vpiParameter:
\_parameter: (BRANCH_TABLE_ENTRIES), line:160
|vpiName:BRANCH_TABLE_ENTRIES
|INT:4
|vpiParameter:
\_parameter: (BRANCH_UNIT_ID), line:195
|vpiName:BRANCH_UNIT_ID
|INT:8
|vpiParameter:
\_parameter: (BUS_ADDR_H), line:107
|vpiName:BUS_ADDR_H
|INT:1
|vpiParameter:
\_parameter: (BUS_ADDR_L), line:106
|vpiName:BUS_ADDR_L
|INT:0
|vpiParameter:
\_parameter: (BUS_BIT_CHECK), line:108
|vpiName:BUS_BIT_CHECK
|INT:1
|vpiParameter:
\_parameter: (BUS_TYPE), line:89
|vpiName:BUS_TYPE
|INT:5
|vpiParameter:
\_parameter: (COUNTER_W), line:42
|vpiName:COUNTER_W
|INT:33
|vpiParameter:
\_parameter: (CPU_ID), line:38
|vpiName:CPU_ID
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_ADDR_WIDTH), line:113
|vpiName:C_M_AXI_ADDR_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_DATA_WIDTH), line:114
|vpiName:C_M_AXI_DATA_WIDTH
|INT:1
|vpiParameter:
\_parameter: (DCACHE_LINES), line:133
|vpiName:DCACHE_LINES
|INT:-2146435073
|vpiParameter:
\_parameter: (DCACHE_LINE_ADDR_W), line:135
|vpiName:DCACHE_LINE_ADDR_W
|INT:1073741824
|vpiParameter:
\_parameter: (DCACHE_LINE_W), line:136
|vpiName:DCACHE_LINE_W
|INT:1342177279
|vpiParameter:
\_parameter: (DCACHE_SUB_LINE_ADDR_W), line:137
|vpiName:DCACHE_SUB_LINE_ADDR_W
|INT:4
|vpiParameter:
\_parameter: (DCACHE_TAG_W), line:138
|vpiName:DCACHE_TAG_W
|INT:1610612736
|vpiParameter:
\_parameter: (DCACHE_WAYS), line:134
|vpiName:DCACHE_WAYS
|INT:4
|vpiParameter:
\_parameter: (DIV_ALGORITHM), line:67
|vpiName:DIV_ALGORITHM
|INT:0
|vpiParameter:
\_parameter: (DIV_UNIT_WB_ID), line:192
|vpiName:DIV_UNIT_WB_ID
|INT:2
|vpiParameter:
\_parameter: (DTLB_DEPTH), line:152
|vpiName:DTLB_DEPTH
|INT:512
|vpiParameter:
\_parameter: (DTLB_WAYS), line:151
|vpiName:DTLB_WAYS
|INT:32
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (ENABLE_M_MODE), line:34
|vpiName:ENABLE_M_MODE
|INT:1
|vpiParameter:
\_parameter: (ENABLE_S_MODE), line:36
|vpiName:ENABLE_S_MODE
|INT:0
|vpiParameter:
\_parameter: (ENABLE_TRACE_INTERFACE), line:172
|vpiName:ENABLE_TRACE_INTERFACE
|INT:2
|vpiParameter:
\_parameter: (FETCH_BUFFER_DEPTH), line:168
|vpiName:FETCH_BUFFER_DEPTH
|INT:512
|vpiParameter:
\_parameter: (FPGA_VENDOR), line:27
|vpiName:FPGA_VENDOR
|STRING:"xilinx"
|vpiParameter:
\_parameter: (GC_UNIT_ID), line:196
|vpiName:GC_UNIT_ID
|INT:4
|vpiParameter:
\_parameter: (ICACHE_LINES), line:121
|vpiName:ICACHE_LINES
|INT:2
|vpiParameter:
\_parameter: (ICACHE_LINE_ADDR_W), line:123
|vpiName:ICACHE_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_LINE_W), line:124
|vpiName:ICACHE_LINE_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_SUB_LINE_ADDR_W), line:125
|vpiName:ICACHE_SUB_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_TAG_W), line:126
|vpiName:ICACHE_TAG_W
|INT:-2147483648
|vpiParameter:
\_parameter: (ICACHE_WAYS), line:122
|vpiName:ICACHE_WAYS
|INT:1
|vpiParameter:
\_parameter: (ITLB_DEPTH), line:146
|vpiName:ITLB_DEPTH
|INT:32
|vpiParameter:
\_parameter: (ITLB_WAYS), line:145
|vpiName:ITLB_WAYS
|INT:4
|vpiParameter:
\_parameter: (L1_CONNECTIONS), line:177
|vpiName:L1_CONNECTIONS
|INT:9
|vpiParameter:
\_parameter: (L1_DCACHE_ID), line:178
|vpiName:L1_DCACHE_ID
|INT:4
|vpiParameter:
\_parameter: (L1_DMMU_ID), line:179
|vpiName:L1_DMMU_ID
|INT:2
|vpiParameter:
\_parameter: (L1_ICACHE_ID), line:180
|vpiName:L1_ICACHE_ID
|INT:19
|vpiParameter:
\_parameter: (L1_IMMU_ID), line:181
|vpiName:L1_IMMU_ID
|INT:0
|vpiParameter:
\_parameter: (LS_UNIT_WB_ID), line:191
|vpiName:LS_UNIT_WB_ID
|INT:1
|vpiParameter:
\_parameter: (MAX_INFLIGHT_COUNT), line:167
|vpiName:MAX_INFLIGHT_COUNT
|INT:19
|vpiParameter:
\_parameter: (MEMORY_ADDR_H), line:103
|vpiName:MEMORY_ADDR_H
|INT:12
|vpiParameter:
\_parameter: (MEMORY_ADDR_L), line:102
|vpiName:MEMORY_ADDR_L
|INT:11
|vpiParameter:
\_parameter: (MEMORY_BIT_CHECK), line:104
|vpiName:MEMORY_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (MUL_UNIT_WB_ID), line:193
|vpiName:MUL_UNIT_WB_ID
|INT:512
|vpiParameter:
\_parameter: (NUM_UNITS), line:188
|vpiName:NUM_UNITS
|INT:2
|vpiParameter:
\_parameter: (NUM_WB_UNITS), line:186
|vpiName:NUM_WB_UNITS
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (RAS_DEPTH), line:161
|vpiName:RAS_DEPTH
|INT:2
|vpiParameter:
\_parameter: (RESET_VEC), line:39
|vpiName:RESET_VEC
|INT:-2147483648
|vpiParameter:
\_parameter: (SCRATCH_ADDR_H), line:99
|vpiName:SCRATCH_ADDR_H
|INT:9
|vpiParameter:
\_parameter: (SCRATCH_ADDR_L), line:98
|vpiName:SCRATCH_ADDR_L
|INT:8
|vpiParameter:
\_parameter: (SCRATCH_BIT_CHECK), line:100
|vpiName:SCRATCH_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (USE_AMO), line:70
|vpiName:USE_AMO
|INT:1
|vpiParameter:
\_parameter: (USE_BRANCH_PREDICTOR), line:158
|vpiName:USE_BRANCH_PREDICTOR
|INT:2
|vpiParameter:
\_parameter: (USE_BUS), line:88
|vpiName:USE_BUS
|INT:4
|vpiParameter:
\_parameter: (USE_DCACHE), line:92
|vpiName:USE_DCACHE
|INT:6
|vpiParameter:
\_parameter: (USE_DIV), line:49
|vpiName:USE_DIV
|INT:1
|vpiParameter:
\_parameter: (USE_DTAG_INVALIDATIONS), line:140
|vpiName:USE_DTAG_INVALIDATIONS
|INT:1879048191
|vpiParameter:
\_parameter: (USE_D_SCRATCH_MEM), line:79
|vpiName:USE_D_SCRATCH_MEM
|INT:3
|vpiParameter:
\_parameter: (USE_ICACHE), line:93
|vpiName:USE_ICACHE
|INT:7
|vpiParameter:
\_parameter: (USE_I_SCRATCH_MEM), line:78
|vpiName:USE_I_SCRATCH_MEM
|INT:2
|vpiParameter:
\_parameter: (USE_MUL), line:48
|vpiName:USE_MUL
|INT:1
|vpiParameter:
\_parameter: (WB_UNITS_WIDTH), line:187
|vpiName:WB_UNITS_WIDTH
|INT:32
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiParameter:
\_parameter: (i), line:140
|vpiName:i
|INT:9
|vpiGenScopeArray:
\_gen_scope_array: (genblk3[10]), line:140, parent:write_back_mux
|vpiName:genblk3[10]
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk3[10]
|vpiGenScope:
\_gen_scope: , parent:genblk3[10]
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk3[10]
|vpiProcess:
\_always: , line:141
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:141
|vpiCondition:
\_operation: , line:141
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:141
|vpiName:clk
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk3[10].clk
|vpiStmt:
\_begin: , line:141
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk3[10]
|vpiStmt:
\_if_stmt: , line:142
|vpiCondition:
\_operation: , line:142
|vpiOpType:29
|vpiOperand:
\_bit_select: (id_writing_to_buffer), line:142
|vpiName:id_writing_to_buffer
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk3[10].id_writing_to_buffer
|vpiIndex:
\_ref_obj: (i), line:142
|vpiName:i
|vpiOperand:
\_bit_select: (store_mux), line:142
|vpiName:store_mux
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk3[10].store_mux
|vpiIndex:
\_ref_obj: (i), line:142
|vpiName:i
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk3[10].i
|vpiStmt:
\_assignment: , line:143
|vpiOpType:82
|vpiLhs:
\_bit_select: (results_by_id), line:143
|vpiName:results_by_id
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk3[10].results_by_id
|vpiIndex:
\_ref_obj: (i), line:143
|vpiName:i
|vpiRhs:
\_bit_select: (unit_rd), line:143
|vpiName:unit_rd
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk3[10].unit_rd
|vpiIndex:
\_operation: , line:143
|vpiOpType:33
|vpiOperand:
\_bit_select: (store_mux), line:143
|vpiName:store_mux
|vpiIndex:
\_ref_obj: (i), line:143
|vpiName:i
|vpiOperand:
\_bit_select: (id_unit_select), line:143
|vpiName:id_unit_select
|vpiIndex:
\_ref_obj: (i), line:143
|vpiName:i
|vpiParameter:
\_parameter: (ALU_UNIT_WB_ID), line:190
|vpiName:ALU_UNIT_WB_ID
|INT:32
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (BRANCH_PREDICTOR_WAYS), line:159
|vpiName:BRANCH_PREDICTOR_WAYS
|INT:9
|vpiParameter:
\_parameter: (BRANCH_TABLE_ENTRIES), line:160
|vpiName:BRANCH_TABLE_ENTRIES
|INT:4
|vpiParameter:
\_parameter: (BRANCH_UNIT_ID), line:195
|vpiName:BRANCH_UNIT_ID
|INT:8
|vpiParameter:
\_parameter: (BUS_ADDR_H), line:107
|vpiName:BUS_ADDR_H
|INT:1
|vpiParameter:
\_parameter: (BUS_ADDR_L), line:106
|vpiName:BUS_ADDR_L
|INT:0
|vpiParameter:
\_parameter: (BUS_BIT_CHECK), line:108
|vpiName:BUS_BIT_CHECK
|INT:1
|vpiParameter:
\_parameter: (BUS_TYPE), line:89
|vpiName:BUS_TYPE
|INT:5
|vpiParameter:
\_parameter: (COUNTER_W), line:42
|vpiName:COUNTER_W
|INT:33
|vpiParameter:
\_parameter: (CPU_ID), line:38
|vpiName:CPU_ID
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_ADDR_WIDTH), line:113
|vpiName:C_M_AXI_ADDR_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_DATA_WIDTH), line:114
|vpiName:C_M_AXI_DATA_WIDTH
|INT:1
|vpiParameter:
\_parameter: (DCACHE_LINES), line:133
|vpiName:DCACHE_LINES
|INT:-2146435073
|vpiParameter:
\_parameter: (DCACHE_LINE_ADDR_W), line:135
|vpiName:DCACHE_LINE_ADDR_W
|INT:1073741824
|vpiParameter:
\_parameter: (DCACHE_LINE_W), line:136
|vpiName:DCACHE_LINE_W
|INT:1342177279
|vpiParameter:
\_parameter: (DCACHE_SUB_LINE_ADDR_W), line:137
|vpiName:DCACHE_SUB_LINE_ADDR_W
|INT:4
|vpiParameter:
\_parameter: (DCACHE_TAG_W), line:138
|vpiName:DCACHE_TAG_W
|INT:1610612736
|vpiParameter:
\_parameter: (DCACHE_WAYS), line:134
|vpiName:DCACHE_WAYS
|INT:4
|vpiParameter:
\_parameter: (DIV_ALGORITHM), line:67
|vpiName:DIV_ALGORITHM
|INT:0
|vpiParameter:
\_parameter: (DIV_UNIT_WB_ID), line:192
|vpiName:DIV_UNIT_WB_ID
|INT:2
|vpiParameter:
\_parameter: (DTLB_DEPTH), line:152
|vpiName:DTLB_DEPTH
|INT:512
|vpiParameter:
\_parameter: (DTLB_WAYS), line:151
|vpiName:DTLB_WAYS
|INT:32
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (ENABLE_M_MODE), line:34
|vpiName:ENABLE_M_MODE
|INT:1
|vpiParameter:
\_parameter: (ENABLE_S_MODE), line:36
|vpiName:ENABLE_S_MODE
|INT:0
|vpiParameter:
\_parameter: (ENABLE_TRACE_INTERFACE), line:172
|vpiName:ENABLE_TRACE_INTERFACE
|INT:2
|vpiParameter:
\_parameter: (FETCH_BUFFER_DEPTH), line:168
|vpiName:FETCH_BUFFER_DEPTH
|INT:512
|vpiParameter:
\_parameter: (FPGA_VENDOR), line:27
|vpiName:FPGA_VENDOR
|STRING:"xilinx"
|vpiParameter:
\_parameter: (GC_UNIT_ID), line:196
|vpiName:GC_UNIT_ID
|INT:4
|vpiParameter:
\_parameter: (ICACHE_LINES), line:121
|vpiName:ICACHE_LINES
|INT:2
|vpiParameter:
\_parameter: (ICACHE_LINE_ADDR_W), line:123
|vpiName:ICACHE_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_LINE_W), line:124
|vpiName:ICACHE_LINE_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_SUB_LINE_ADDR_W), line:125
|vpiName:ICACHE_SUB_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_TAG_W), line:126
|vpiName:ICACHE_TAG_W
|INT:-2147483648
|vpiParameter:
\_parameter: (ICACHE_WAYS), line:122
|vpiName:ICACHE_WAYS
|INT:1
|vpiParameter:
\_parameter: (ITLB_DEPTH), line:146
|vpiName:ITLB_DEPTH
|INT:32
|vpiParameter:
\_parameter: (ITLB_WAYS), line:145
|vpiName:ITLB_WAYS
|INT:4
|vpiParameter:
\_parameter: (L1_CONNECTIONS), line:177
|vpiName:L1_CONNECTIONS
|INT:9
|vpiParameter:
\_parameter: (L1_DCACHE_ID), line:178
|vpiName:L1_DCACHE_ID
|INT:4
|vpiParameter:
\_parameter: (L1_DMMU_ID), line:179
|vpiName:L1_DMMU_ID
|INT:2
|vpiParameter:
\_parameter: (L1_ICACHE_ID), line:180
|vpiName:L1_ICACHE_ID
|INT:19
|vpiParameter:
\_parameter: (L1_IMMU_ID), line:181
|vpiName:L1_IMMU_ID
|INT:0
|vpiParameter:
\_parameter: (LS_UNIT_WB_ID), line:191
|vpiName:LS_UNIT_WB_ID
|INT:1
|vpiParameter:
\_parameter: (MAX_INFLIGHT_COUNT), line:167
|vpiName:MAX_INFLIGHT_COUNT
|INT:19
|vpiParameter:
\_parameter: (MEMORY_ADDR_H), line:103
|vpiName:MEMORY_ADDR_H
|INT:12
|vpiParameter:
\_parameter: (MEMORY_ADDR_L), line:102
|vpiName:MEMORY_ADDR_L
|INT:11
|vpiParameter:
\_parameter: (MEMORY_BIT_CHECK), line:104
|vpiName:MEMORY_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (MUL_UNIT_WB_ID), line:193
|vpiName:MUL_UNIT_WB_ID
|INT:512
|vpiParameter:
\_parameter: (NUM_UNITS), line:188
|vpiName:NUM_UNITS
|INT:2
|vpiParameter:
\_parameter: (NUM_WB_UNITS), line:186
|vpiName:NUM_WB_UNITS
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (RAS_DEPTH), line:161
|vpiName:RAS_DEPTH
|INT:2
|vpiParameter:
\_parameter: (RESET_VEC), line:39
|vpiName:RESET_VEC
|INT:-2147483648
|vpiParameter:
\_parameter: (SCRATCH_ADDR_H), line:99
|vpiName:SCRATCH_ADDR_H
|INT:9
|vpiParameter:
\_parameter: (SCRATCH_ADDR_L), line:98
|vpiName:SCRATCH_ADDR_L
|INT:8
|vpiParameter:
\_parameter: (SCRATCH_BIT_CHECK), line:100
|vpiName:SCRATCH_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (USE_AMO), line:70
|vpiName:USE_AMO
|INT:1
|vpiParameter:
\_parameter: (USE_BRANCH_PREDICTOR), line:158
|vpiName:USE_BRANCH_PREDICTOR
|INT:2
|vpiParameter:
\_parameter: (USE_BUS), line:88
|vpiName:USE_BUS
|INT:4
|vpiParameter:
\_parameter: (USE_DCACHE), line:92
|vpiName:USE_DCACHE
|INT:6
|vpiParameter:
\_parameter: (USE_DIV), line:49
|vpiName:USE_DIV
|INT:1
|vpiParameter:
\_parameter: (USE_DTAG_INVALIDATIONS), line:140
|vpiName:USE_DTAG_INVALIDATIONS
|INT:1879048191
|vpiParameter:
\_parameter: (USE_D_SCRATCH_MEM), line:79
|vpiName:USE_D_SCRATCH_MEM
|INT:3
|vpiParameter:
\_parameter: (USE_ICACHE), line:93
|vpiName:USE_ICACHE
|INT:7
|vpiParameter:
\_parameter: (USE_I_SCRATCH_MEM), line:78
|vpiName:USE_I_SCRATCH_MEM
|INT:2
|vpiParameter:
\_parameter: (USE_MUL), line:48
|vpiName:USE_MUL
|INT:1
|vpiParameter:
\_parameter: (WB_UNITS_WIDTH), line:187
|vpiName:WB_UNITS_WIDTH
|INT:32
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiParameter:
\_parameter: (i), line:140
|vpiName:i
|INT:10
|vpiGenScopeArray:
\_gen_scope_array: (genblk3[11]), line:140, parent:write_back_mux
|vpiName:genblk3[11]
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk3[11]
|vpiGenScope:
\_gen_scope: , parent:genblk3[11]
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk3[11]
|vpiProcess:
\_always: , line:141
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:141
|vpiCondition:
\_operation: , line:141
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:141
|vpiName:clk
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk3[11].clk
|vpiStmt:
\_begin: , line:141
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk3[11]
|vpiStmt:
\_if_stmt: , line:142
|vpiCondition:
\_operation: , line:142
|vpiOpType:29
|vpiOperand:
\_bit_select: (id_writing_to_buffer), line:142
|vpiName:id_writing_to_buffer
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk3[11].id_writing_to_buffer
|vpiIndex:
\_ref_obj: (i), line:142
|vpiName:i
|vpiOperand:
\_bit_select: (store_mux), line:142
|vpiName:store_mux
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk3[11].store_mux
|vpiIndex:
\_ref_obj: (i), line:142
|vpiName:i
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk3[11].i
|vpiStmt:
\_assignment: , line:143
|vpiOpType:82
|vpiLhs:
\_bit_select: (results_by_id), line:143
|vpiName:results_by_id
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk3[11].results_by_id
|vpiIndex:
\_ref_obj: (i), line:143
|vpiName:i
|vpiRhs:
\_bit_select: (unit_rd), line:143
|vpiName:unit_rd
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk3[11].unit_rd
|vpiIndex:
\_operation: , line:143
|vpiOpType:33
|vpiOperand:
\_bit_select: (store_mux), line:143
|vpiName:store_mux
|vpiIndex:
\_ref_obj: (i), line:143
|vpiName:i
|vpiOperand:
\_bit_select: (id_unit_select), line:143
|vpiName:id_unit_select
|vpiIndex:
\_ref_obj: (i), line:143
|vpiName:i
|vpiParameter:
\_parameter: (ALU_UNIT_WB_ID), line:190
|vpiName:ALU_UNIT_WB_ID
|INT:32
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (BRANCH_PREDICTOR_WAYS), line:159
|vpiName:BRANCH_PREDICTOR_WAYS
|INT:9
|vpiParameter:
\_parameter: (BRANCH_TABLE_ENTRIES), line:160
|vpiName:BRANCH_TABLE_ENTRIES
|INT:4
|vpiParameter:
\_parameter: (BRANCH_UNIT_ID), line:195
|vpiName:BRANCH_UNIT_ID
|INT:8
|vpiParameter:
\_parameter: (BUS_ADDR_H), line:107
|vpiName:BUS_ADDR_H
|INT:1
|vpiParameter:
\_parameter: (BUS_ADDR_L), line:106
|vpiName:BUS_ADDR_L
|INT:0
|vpiParameter:
\_parameter: (BUS_BIT_CHECK), line:108
|vpiName:BUS_BIT_CHECK
|INT:1
|vpiParameter:
\_parameter: (BUS_TYPE), line:89
|vpiName:BUS_TYPE
|INT:5
|vpiParameter:
\_parameter: (COUNTER_W), line:42
|vpiName:COUNTER_W
|INT:33
|vpiParameter:
\_parameter: (CPU_ID), line:38
|vpiName:CPU_ID
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_ADDR_WIDTH), line:113
|vpiName:C_M_AXI_ADDR_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_DATA_WIDTH), line:114
|vpiName:C_M_AXI_DATA_WIDTH
|INT:1
|vpiParameter:
\_parameter: (DCACHE_LINES), line:133
|vpiName:DCACHE_LINES
|INT:-2146435073
|vpiParameter:
\_parameter: (DCACHE_LINE_ADDR_W), line:135
|vpiName:DCACHE_LINE_ADDR_W
|INT:1073741824
|vpiParameter:
\_parameter: (DCACHE_LINE_W), line:136
|vpiName:DCACHE_LINE_W
|INT:1342177279
|vpiParameter:
\_parameter: (DCACHE_SUB_LINE_ADDR_W), line:137
|vpiName:DCACHE_SUB_LINE_ADDR_W
|INT:4
|vpiParameter:
\_parameter: (DCACHE_TAG_W), line:138
|vpiName:DCACHE_TAG_W
|INT:1610612736
|vpiParameter:
\_parameter: (DCACHE_WAYS), line:134
|vpiName:DCACHE_WAYS
|INT:4
|vpiParameter:
\_parameter: (DIV_ALGORITHM), line:67
|vpiName:DIV_ALGORITHM
|INT:0
|vpiParameter:
\_parameter: (DIV_UNIT_WB_ID), line:192
|vpiName:DIV_UNIT_WB_ID
|INT:2
|vpiParameter:
\_parameter: (DTLB_DEPTH), line:152
|vpiName:DTLB_DEPTH
|INT:512
|vpiParameter:
\_parameter: (DTLB_WAYS), line:151
|vpiName:DTLB_WAYS
|INT:32
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (ENABLE_M_MODE), line:34
|vpiName:ENABLE_M_MODE
|INT:1
|vpiParameter:
\_parameter: (ENABLE_S_MODE), line:36
|vpiName:ENABLE_S_MODE
|INT:0
|vpiParameter:
\_parameter: (ENABLE_TRACE_INTERFACE), line:172
|vpiName:ENABLE_TRACE_INTERFACE
|INT:2
|vpiParameter:
\_parameter: (FETCH_BUFFER_DEPTH), line:168
|vpiName:FETCH_BUFFER_DEPTH
|INT:512
|vpiParameter:
\_parameter: (FPGA_VENDOR), line:27
|vpiName:FPGA_VENDOR
|STRING:"xilinx"
|vpiParameter:
\_parameter: (GC_UNIT_ID), line:196
|vpiName:GC_UNIT_ID
|INT:4
|vpiParameter:
\_parameter: (ICACHE_LINES), line:121
|vpiName:ICACHE_LINES
|INT:2
|vpiParameter:
\_parameter: (ICACHE_LINE_ADDR_W), line:123
|vpiName:ICACHE_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_LINE_W), line:124
|vpiName:ICACHE_LINE_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_SUB_LINE_ADDR_W), line:125
|vpiName:ICACHE_SUB_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_TAG_W), line:126
|vpiName:ICACHE_TAG_W
|INT:-2147483648
|vpiParameter:
\_parameter: (ICACHE_WAYS), line:122
|vpiName:ICACHE_WAYS
|INT:1
|vpiParameter:
\_parameter: (ITLB_DEPTH), line:146
|vpiName:ITLB_DEPTH
|INT:32
|vpiParameter:
\_parameter: (ITLB_WAYS), line:145
|vpiName:ITLB_WAYS
|INT:4
|vpiParameter:
\_parameter: (L1_CONNECTIONS), line:177
|vpiName:L1_CONNECTIONS
|INT:9
|vpiParameter:
\_parameter: (L1_DCACHE_ID), line:178
|vpiName:L1_DCACHE_ID
|INT:4
|vpiParameter:
\_parameter: (L1_DMMU_ID), line:179
|vpiName:L1_DMMU_ID
|INT:2
|vpiParameter:
\_parameter: (L1_ICACHE_ID), line:180
|vpiName:L1_ICACHE_ID
|INT:19
|vpiParameter:
\_parameter: (L1_IMMU_ID), line:181
|vpiName:L1_IMMU_ID
|INT:0
|vpiParameter:
\_parameter: (LS_UNIT_WB_ID), line:191
|vpiName:LS_UNIT_WB_ID
|INT:1
|vpiParameter:
\_parameter: (MAX_INFLIGHT_COUNT), line:167
|vpiName:MAX_INFLIGHT_COUNT
|INT:19
|vpiParameter:
\_parameter: (MEMORY_ADDR_H), line:103
|vpiName:MEMORY_ADDR_H
|INT:12
|vpiParameter:
\_parameter: (MEMORY_ADDR_L), line:102
|vpiName:MEMORY_ADDR_L
|INT:11
|vpiParameter:
\_parameter: (MEMORY_BIT_CHECK), line:104
|vpiName:MEMORY_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (MUL_UNIT_WB_ID), line:193
|vpiName:MUL_UNIT_WB_ID
|INT:512
|vpiParameter:
\_parameter: (NUM_UNITS), line:188
|vpiName:NUM_UNITS
|INT:2
|vpiParameter:
\_parameter: (NUM_WB_UNITS), line:186
|vpiName:NUM_WB_UNITS
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (RAS_DEPTH), line:161
|vpiName:RAS_DEPTH
|INT:2
|vpiParameter:
\_parameter: (RESET_VEC), line:39
|vpiName:RESET_VEC
|INT:-2147483648
|vpiParameter:
\_parameter: (SCRATCH_ADDR_H), line:99
|vpiName:SCRATCH_ADDR_H
|INT:9
|vpiParameter:
\_parameter: (SCRATCH_ADDR_L), line:98
|vpiName:SCRATCH_ADDR_L
|INT:8
|vpiParameter:
\_parameter: (SCRATCH_BIT_CHECK), line:100
|vpiName:SCRATCH_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (USE_AMO), line:70
|vpiName:USE_AMO
|INT:1
|vpiParameter:
\_parameter: (USE_BRANCH_PREDICTOR), line:158
|vpiName:USE_BRANCH_PREDICTOR
|INT:2
|vpiParameter:
\_parameter: (USE_BUS), line:88
|vpiName:USE_BUS
|INT:4
|vpiParameter:
\_parameter: (USE_DCACHE), line:92
|vpiName:USE_DCACHE
|INT:6
|vpiParameter:
\_parameter: (USE_DIV), line:49
|vpiName:USE_DIV
|INT:1
|vpiParameter:
\_parameter: (USE_DTAG_INVALIDATIONS), line:140
|vpiName:USE_DTAG_INVALIDATIONS
|INT:1879048191
|vpiParameter:
\_parameter: (USE_D_SCRATCH_MEM), line:79
|vpiName:USE_D_SCRATCH_MEM
|INT:3
|vpiParameter:
\_parameter: (USE_ICACHE), line:93
|vpiName:USE_ICACHE
|INT:7
|vpiParameter:
\_parameter: (USE_I_SCRATCH_MEM), line:78
|vpiName:USE_I_SCRATCH_MEM
|INT:2
|vpiParameter:
\_parameter: (USE_MUL), line:48
|vpiName:USE_MUL
|INT:1
|vpiParameter:
\_parameter: (WB_UNITS_WIDTH), line:187
|vpiName:WB_UNITS_WIDTH
|INT:32
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiParameter:
\_parameter: (i), line:140
|vpiName:i
|INT:11
|vpiGenScopeArray:
\_gen_scope_array: (genblk3[12]), line:140, parent:write_back_mux
|vpiName:genblk3[12]
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk3[12]
|vpiGenScope:
\_gen_scope: , parent:genblk3[12]
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk3[12]
|vpiProcess:
\_always: , line:141
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:141
|vpiCondition:
\_operation: , line:141
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:141
|vpiName:clk
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk3[12].clk
|vpiStmt:
\_begin: , line:141
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk3[12]
|vpiStmt:
\_if_stmt: , line:142
|vpiCondition:
\_operation: , line:142
|vpiOpType:29
|vpiOperand:
\_bit_select: (id_writing_to_buffer), line:142
|vpiName:id_writing_to_buffer
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk3[12].id_writing_to_buffer
|vpiIndex:
\_ref_obj: (i), line:142
|vpiName:i
|vpiOperand:
\_bit_select: (store_mux), line:142
|vpiName:store_mux
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk3[12].store_mux
|vpiIndex:
\_ref_obj: (i), line:142
|vpiName:i
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk3[12].i
|vpiStmt:
\_assignment: , line:143
|vpiOpType:82
|vpiLhs:
\_bit_select: (results_by_id), line:143
|vpiName:results_by_id
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk3[12].results_by_id
|vpiIndex:
\_ref_obj: (i), line:143
|vpiName:i
|vpiRhs:
\_bit_select: (unit_rd), line:143
|vpiName:unit_rd
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk3[12].unit_rd
|vpiIndex:
\_operation: , line:143
|vpiOpType:33
|vpiOperand:
\_bit_select: (store_mux), line:143
|vpiName:store_mux
|vpiIndex:
\_ref_obj: (i), line:143
|vpiName:i
|vpiOperand:
\_bit_select: (id_unit_select), line:143
|vpiName:id_unit_select
|vpiIndex:
\_ref_obj: (i), line:143
|vpiName:i
|vpiParameter:
\_parameter: (ALU_UNIT_WB_ID), line:190
|vpiName:ALU_UNIT_WB_ID
|INT:32
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (BRANCH_PREDICTOR_WAYS), line:159
|vpiName:BRANCH_PREDICTOR_WAYS
|INT:9
|vpiParameter:
\_parameter: (BRANCH_TABLE_ENTRIES), line:160
|vpiName:BRANCH_TABLE_ENTRIES
|INT:4
|vpiParameter:
\_parameter: (BRANCH_UNIT_ID), line:195
|vpiName:BRANCH_UNIT_ID
|INT:8
|vpiParameter:
\_parameter: (BUS_ADDR_H), line:107
|vpiName:BUS_ADDR_H
|INT:1
|vpiParameter:
\_parameter: (BUS_ADDR_L), line:106
|vpiName:BUS_ADDR_L
|INT:0
|vpiParameter:
\_parameter: (BUS_BIT_CHECK), line:108
|vpiName:BUS_BIT_CHECK
|INT:1
|vpiParameter:
\_parameter: (BUS_TYPE), line:89
|vpiName:BUS_TYPE
|INT:5
|vpiParameter:
\_parameter: (COUNTER_W), line:42
|vpiName:COUNTER_W
|INT:33
|vpiParameter:
\_parameter: (CPU_ID), line:38
|vpiName:CPU_ID
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_ADDR_WIDTH), line:113
|vpiName:C_M_AXI_ADDR_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_DATA_WIDTH), line:114
|vpiName:C_M_AXI_DATA_WIDTH
|INT:1
|vpiParameter:
\_parameter: (DCACHE_LINES), line:133
|vpiName:DCACHE_LINES
|INT:-2146435073
|vpiParameter:
\_parameter: (DCACHE_LINE_ADDR_W), line:135
|vpiName:DCACHE_LINE_ADDR_W
|INT:1073741824
|vpiParameter:
\_parameter: (DCACHE_LINE_W), line:136
|vpiName:DCACHE_LINE_W
|INT:1342177279
|vpiParameter:
\_parameter: (DCACHE_SUB_LINE_ADDR_W), line:137
|vpiName:DCACHE_SUB_LINE_ADDR_W
|INT:4
|vpiParameter:
\_parameter: (DCACHE_TAG_W), line:138
|vpiName:DCACHE_TAG_W
|INT:1610612736
|vpiParameter:
\_parameter: (DCACHE_WAYS), line:134
|vpiName:DCACHE_WAYS
|INT:4
|vpiParameter:
\_parameter: (DIV_ALGORITHM), line:67
|vpiName:DIV_ALGORITHM
|INT:0
|vpiParameter:
\_parameter: (DIV_UNIT_WB_ID), line:192
|vpiName:DIV_UNIT_WB_ID
|INT:2
|vpiParameter:
\_parameter: (DTLB_DEPTH), line:152
|vpiName:DTLB_DEPTH
|INT:512
|vpiParameter:
\_parameter: (DTLB_WAYS), line:151
|vpiName:DTLB_WAYS
|INT:32
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (ENABLE_M_MODE), line:34
|vpiName:ENABLE_M_MODE
|INT:1
|vpiParameter:
\_parameter: (ENABLE_S_MODE), line:36
|vpiName:ENABLE_S_MODE
|INT:0
|vpiParameter:
\_parameter: (ENABLE_TRACE_INTERFACE), line:172
|vpiName:ENABLE_TRACE_INTERFACE
|INT:2
|vpiParameter:
\_parameter: (FETCH_BUFFER_DEPTH), line:168
|vpiName:FETCH_BUFFER_DEPTH
|INT:512
|vpiParameter:
\_parameter: (FPGA_VENDOR), line:27
|vpiName:FPGA_VENDOR
|STRING:"xilinx"
|vpiParameter:
\_parameter: (GC_UNIT_ID), line:196
|vpiName:GC_UNIT_ID
|INT:4
|vpiParameter:
\_parameter: (ICACHE_LINES), line:121
|vpiName:ICACHE_LINES
|INT:2
|vpiParameter:
\_parameter: (ICACHE_LINE_ADDR_W), line:123
|vpiName:ICACHE_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_LINE_W), line:124
|vpiName:ICACHE_LINE_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_SUB_LINE_ADDR_W), line:125
|vpiName:ICACHE_SUB_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_TAG_W), line:126
|vpiName:ICACHE_TAG_W
|INT:-2147483648
|vpiParameter:
\_parameter: (ICACHE_WAYS), line:122
|vpiName:ICACHE_WAYS
|INT:1
|vpiParameter:
\_parameter: (ITLB_DEPTH), line:146
|vpiName:ITLB_DEPTH
|INT:32
|vpiParameter:
\_parameter: (ITLB_WAYS), line:145
|vpiName:ITLB_WAYS
|INT:4
|vpiParameter:
\_parameter: (L1_CONNECTIONS), line:177
|vpiName:L1_CONNECTIONS
|INT:9
|vpiParameter:
\_parameter: (L1_DCACHE_ID), line:178
|vpiName:L1_DCACHE_ID
|INT:4
|vpiParameter:
\_parameter: (L1_DMMU_ID), line:179
|vpiName:L1_DMMU_ID
|INT:2
|vpiParameter:
\_parameter: (L1_ICACHE_ID), line:180
|vpiName:L1_ICACHE_ID
|INT:19
|vpiParameter:
\_parameter: (L1_IMMU_ID), line:181
|vpiName:L1_IMMU_ID
|INT:0
|vpiParameter:
\_parameter: (LS_UNIT_WB_ID), line:191
|vpiName:LS_UNIT_WB_ID
|INT:1
|vpiParameter:
\_parameter: (MAX_INFLIGHT_COUNT), line:167
|vpiName:MAX_INFLIGHT_COUNT
|INT:19
|vpiParameter:
\_parameter: (MEMORY_ADDR_H), line:103
|vpiName:MEMORY_ADDR_H
|INT:12
|vpiParameter:
\_parameter: (MEMORY_ADDR_L), line:102
|vpiName:MEMORY_ADDR_L
|INT:11
|vpiParameter:
\_parameter: (MEMORY_BIT_CHECK), line:104
|vpiName:MEMORY_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (MUL_UNIT_WB_ID), line:193
|vpiName:MUL_UNIT_WB_ID
|INT:512
|vpiParameter:
\_parameter: (NUM_UNITS), line:188
|vpiName:NUM_UNITS
|INT:2
|vpiParameter:
\_parameter: (NUM_WB_UNITS), line:186
|vpiName:NUM_WB_UNITS
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (RAS_DEPTH), line:161
|vpiName:RAS_DEPTH
|INT:2
|vpiParameter:
\_parameter: (RESET_VEC), line:39
|vpiName:RESET_VEC
|INT:-2147483648
|vpiParameter:
\_parameter: (SCRATCH_ADDR_H), line:99
|vpiName:SCRATCH_ADDR_H
|INT:9
|vpiParameter:
\_parameter: (SCRATCH_ADDR_L), line:98
|vpiName:SCRATCH_ADDR_L
|INT:8
|vpiParameter:
\_parameter: (SCRATCH_BIT_CHECK), line:100
|vpiName:SCRATCH_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (USE_AMO), line:70
|vpiName:USE_AMO
|INT:1
|vpiParameter:
\_parameter: (USE_BRANCH_PREDICTOR), line:158
|vpiName:USE_BRANCH_PREDICTOR
|INT:2
|vpiParameter:
\_parameter: (USE_BUS), line:88
|vpiName:USE_BUS
|INT:4
|vpiParameter:
\_parameter: (USE_DCACHE), line:92
|vpiName:USE_DCACHE
|INT:6
|vpiParameter:
\_parameter: (USE_DIV), line:49
|vpiName:USE_DIV
|INT:1
|vpiParameter:
\_parameter: (USE_DTAG_INVALIDATIONS), line:140
|vpiName:USE_DTAG_INVALIDATIONS
|INT:1879048191
|vpiParameter:
\_parameter: (USE_D_SCRATCH_MEM), line:79
|vpiName:USE_D_SCRATCH_MEM
|INT:3
|vpiParameter:
\_parameter: (USE_ICACHE), line:93
|vpiName:USE_ICACHE
|INT:7
|vpiParameter:
\_parameter: (USE_I_SCRATCH_MEM), line:78
|vpiName:USE_I_SCRATCH_MEM
|INT:2
|vpiParameter:
\_parameter: (USE_MUL), line:48
|vpiName:USE_MUL
|INT:1
|vpiParameter:
\_parameter: (WB_UNITS_WIDTH), line:187
|vpiName:WB_UNITS_WIDTH
|INT:32
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiParameter:
\_parameter: (i), line:140
|vpiName:i
|INT:12
|vpiGenScopeArray:
\_gen_scope_array: (genblk3[13]), line:140, parent:write_back_mux
|vpiName:genblk3[13]
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk3[13]
|vpiGenScope:
\_gen_scope: , parent:genblk3[13]
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk3[13]
|vpiProcess:
\_always: , line:141
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:141
|vpiCondition:
\_operation: , line:141
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:141
|vpiName:clk
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk3[13].clk
|vpiStmt:
\_begin: , line:141
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk3[13]
|vpiStmt:
\_if_stmt: , line:142
|vpiCondition:
\_operation: , line:142
|vpiOpType:29
|vpiOperand:
\_bit_select: (id_writing_to_buffer), line:142
|vpiName:id_writing_to_buffer
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk3[13].id_writing_to_buffer
|vpiIndex:
\_ref_obj: (i), line:142
|vpiName:i
|vpiOperand:
\_bit_select: (store_mux), line:142
|vpiName:store_mux
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk3[13].store_mux
|vpiIndex:
\_ref_obj: (i), line:142
|vpiName:i
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk3[13].i
|vpiStmt:
\_assignment: , line:143
|vpiOpType:82
|vpiLhs:
\_bit_select: (results_by_id), line:143
|vpiName:results_by_id
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk3[13].results_by_id
|vpiIndex:
\_ref_obj: (i), line:143
|vpiName:i
|vpiRhs:
\_bit_select: (unit_rd), line:143
|vpiName:unit_rd
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk3[13].unit_rd
|vpiIndex:
\_operation: , line:143
|vpiOpType:33
|vpiOperand:
\_bit_select: (store_mux), line:143
|vpiName:store_mux
|vpiIndex:
\_ref_obj: (i), line:143
|vpiName:i
|vpiOperand:
\_bit_select: (id_unit_select), line:143
|vpiName:id_unit_select
|vpiIndex:
\_ref_obj: (i), line:143
|vpiName:i
|vpiParameter:
\_parameter: (ALU_UNIT_WB_ID), line:190
|vpiName:ALU_UNIT_WB_ID
|INT:32
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (BRANCH_PREDICTOR_WAYS), line:159
|vpiName:BRANCH_PREDICTOR_WAYS
|INT:9
|vpiParameter:
\_parameter: (BRANCH_TABLE_ENTRIES), line:160
|vpiName:BRANCH_TABLE_ENTRIES
|INT:4
|vpiParameter:
\_parameter: (BRANCH_UNIT_ID), line:195
|vpiName:BRANCH_UNIT_ID
|INT:8
|vpiParameter:
\_parameter: (BUS_ADDR_H), line:107
|vpiName:BUS_ADDR_H
|INT:1
|vpiParameter:
\_parameter: (BUS_ADDR_L), line:106
|vpiName:BUS_ADDR_L
|INT:0
|vpiParameter:
\_parameter: (BUS_BIT_CHECK), line:108
|vpiName:BUS_BIT_CHECK
|INT:1
|vpiParameter:
\_parameter: (BUS_TYPE), line:89
|vpiName:BUS_TYPE
|INT:5
|vpiParameter:
\_parameter: (COUNTER_W), line:42
|vpiName:COUNTER_W
|INT:33
|vpiParameter:
\_parameter: (CPU_ID), line:38
|vpiName:CPU_ID
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_ADDR_WIDTH), line:113
|vpiName:C_M_AXI_ADDR_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_DATA_WIDTH), line:114
|vpiName:C_M_AXI_DATA_WIDTH
|INT:1
|vpiParameter:
\_parameter: (DCACHE_LINES), line:133
|vpiName:DCACHE_LINES
|INT:-2146435073
|vpiParameter:
\_parameter: (DCACHE_LINE_ADDR_W), line:135
|vpiName:DCACHE_LINE_ADDR_W
|INT:1073741824
|vpiParameter:
\_parameter: (DCACHE_LINE_W), line:136
|vpiName:DCACHE_LINE_W
|INT:1342177279
|vpiParameter:
\_parameter: (DCACHE_SUB_LINE_ADDR_W), line:137
|vpiName:DCACHE_SUB_LINE_ADDR_W
|INT:4
|vpiParameter:
\_parameter: (DCACHE_TAG_W), line:138
|vpiName:DCACHE_TAG_W
|INT:1610612736
|vpiParameter:
\_parameter: (DCACHE_WAYS), line:134
|vpiName:DCACHE_WAYS
|INT:4
|vpiParameter:
\_parameter: (DIV_ALGORITHM), line:67
|vpiName:DIV_ALGORITHM
|INT:0
|vpiParameter:
\_parameter: (DIV_UNIT_WB_ID), line:192
|vpiName:DIV_UNIT_WB_ID
|INT:2
|vpiParameter:
\_parameter: (DTLB_DEPTH), line:152
|vpiName:DTLB_DEPTH
|INT:512
|vpiParameter:
\_parameter: (DTLB_WAYS), line:151
|vpiName:DTLB_WAYS
|INT:32
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (ENABLE_M_MODE), line:34
|vpiName:ENABLE_M_MODE
|INT:1
|vpiParameter:
\_parameter: (ENABLE_S_MODE), line:36
|vpiName:ENABLE_S_MODE
|INT:0
|vpiParameter:
\_parameter: (ENABLE_TRACE_INTERFACE), line:172
|vpiName:ENABLE_TRACE_INTERFACE
|INT:2
|vpiParameter:
\_parameter: (FETCH_BUFFER_DEPTH), line:168
|vpiName:FETCH_BUFFER_DEPTH
|INT:512
|vpiParameter:
\_parameter: (FPGA_VENDOR), line:27
|vpiName:FPGA_VENDOR
|STRING:"xilinx"
|vpiParameter:
\_parameter: (GC_UNIT_ID), line:196
|vpiName:GC_UNIT_ID
|INT:4
|vpiParameter:
\_parameter: (ICACHE_LINES), line:121
|vpiName:ICACHE_LINES
|INT:2
|vpiParameter:
\_parameter: (ICACHE_LINE_ADDR_W), line:123
|vpiName:ICACHE_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_LINE_W), line:124
|vpiName:ICACHE_LINE_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_SUB_LINE_ADDR_W), line:125
|vpiName:ICACHE_SUB_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_TAG_W), line:126
|vpiName:ICACHE_TAG_W
|INT:-2147483648
|vpiParameter:
\_parameter: (ICACHE_WAYS), line:122
|vpiName:ICACHE_WAYS
|INT:1
|vpiParameter:
\_parameter: (ITLB_DEPTH), line:146
|vpiName:ITLB_DEPTH
|INT:32
|vpiParameter:
\_parameter: (ITLB_WAYS), line:145
|vpiName:ITLB_WAYS
|INT:4
|vpiParameter:
\_parameter: (L1_CONNECTIONS), line:177
|vpiName:L1_CONNECTIONS
|INT:9
|vpiParameter:
\_parameter: (L1_DCACHE_ID), line:178
|vpiName:L1_DCACHE_ID
|INT:4
|vpiParameter:
\_parameter: (L1_DMMU_ID), line:179
|vpiName:L1_DMMU_ID
|INT:2
|vpiParameter:
\_parameter: (L1_ICACHE_ID), line:180
|vpiName:L1_ICACHE_ID
|INT:19
|vpiParameter:
\_parameter: (L1_IMMU_ID), line:181
|vpiName:L1_IMMU_ID
|INT:0
|vpiParameter:
\_parameter: (LS_UNIT_WB_ID), line:191
|vpiName:LS_UNIT_WB_ID
|INT:1
|vpiParameter:
\_parameter: (MAX_INFLIGHT_COUNT), line:167
|vpiName:MAX_INFLIGHT_COUNT
|INT:19
|vpiParameter:
\_parameter: (MEMORY_ADDR_H), line:103
|vpiName:MEMORY_ADDR_H
|INT:12
|vpiParameter:
\_parameter: (MEMORY_ADDR_L), line:102
|vpiName:MEMORY_ADDR_L
|INT:11
|vpiParameter:
\_parameter: (MEMORY_BIT_CHECK), line:104
|vpiName:MEMORY_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (MUL_UNIT_WB_ID), line:193
|vpiName:MUL_UNIT_WB_ID
|INT:512
|vpiParameter:
\_parameter: (NUM_UNITS), line:188
|vpiName:NUM_UNITS
|INT:2
|vpiParameter:
\_parameter: (NUM_WB_UNITS), line:186
|vpiName:NUM_WB_UNITS
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (RAS_DEPTH), line:161
|vpiName:RAS_DEPTH
|INT:2
|vpiParameter:
\_parameter: (RESET_VEC), line:39
|vpiName:RESET_VEC
|INT:-2147483648
|vpiParameter:
\_parameter: (SCRATCH_ADDR_H), line:99
|vpiName:SCRATCH_ADDR_H
|INT:9
|vpiParameter:
\_parameter: (SCRATCH_ADDR_L), line:98
|vpiName:SCRATCH_ADDR_L
|INT:8
|vpiParameter:
\_parameter: (SCRATCH_BIT_CHECK), line:100
|vpiName:SCRATCH_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (USE_AMO), line:70
|vpiName:USE_AMO
|INT:1
|vpiParameter:
\_parameter: (USE_BRANCH_PREDICTOR), line:158
|vpiName:USE_BRANCH_PREDICTOR
|INT:2
|vpiParameter:
\_parameter: (USE_BUS), line:88
|vpiName:USE_BUS
|INT:4
|vpiParameter:
\_parameter: (USE_DCACHE), line:92
|vpiName:USE_DCACHE
|INT:6
|vpiParameter:
\_parameter: (USE_DIV), line:49
|vpiName:USE_DIV
|INT:1
|vpiParameter:
\_parameter: (USE_DTAG_INVALIDATIONS), line:140
|vpiName:USE_DTAG_INVALIDATIONS
|INT:1879048191
|vpiParameter:
\_parameter: (USE_D_SCRATCH_MEM), line:79
|vpiName:USE_D_SCRATCH_MEM
|INT:3
|vpiParameter:
\_parameter: (USE_ICACHE), line:93
|vpiName:USE_ICACHE
|INT:7
|vpiParameter:
\_parameter: (USE_I_SCRATCH_MEM), line:78
|vpiName:USE_I_SCRATCH_MEM
|INT:2
|vpiParameter:
\_parameter: (USE_MUL), line:48
|vpiName:USE_MUL
|INT:1
|vpiParameter:
\_parameter: (WB_UNITS_WIDTH), line:187
|vpiName:WB_UNITS_WIDTH
|INT:32
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiParameter:
\_parameter: (i), line:140
|vpiName:i
|INT:13
|vpiGenScopeArray:
\_gen_scope_array: (genblk3[14]), line:140, parent:write_back_mux
|vpiName:genblk3[14]
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk3[14]
|vpiGenScope:
\_gen_scope: , parent:genblk3[14]
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk3[14]
|vpiProcess:
\_always: , line:141
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:141
|vpiCondition:
\_operation: , line:141
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:141
|vpiName:clk
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk3[14].clk
|vpiStmt:
\_begin: , line:141
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk3[14]
|vpiStmt:
\_if_stmt: , line:142
|vpiCondition:
\_operation: , line:142
|vpiOpType:29
|vpiOperand:
\_bit_select: (id_writing_to_buffer), line:142
|vpiName:id_writing_to_buffer
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk3[14].id_writing_to_buffer
|vpiIndex:
\_ref_obj: (i), line:142
|vpiName:i
|vpiOperand:
\_bit_select: (store_mux), line:142
|vpiName:store_mux
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk3[14].store_mux
|vpiIndex:
\_ref_obj: (i), line:142
|vpiName:i
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk3[14].i
|vpiStmt:
\_assignment: , line:143
|vpiOpType:82
|vpiLhs:
\_bit_select: (results_by_id), line:143
|vpiName:results_by_id
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk3[14].results_by_id
|vpiIndex:
\_ref_obj: (i), line:143
|vpiName:i
|vpiRhs:
\_bit_select: (unit_rd), line:143
|vpiName:unit_rd
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk3[14].unit_rd
|vpiIndex:
\_operation: , line:143
|vpiOpType:33
|vpiOperand:
\_bit_select: (store_mux), line:143
|vpiName:store_mux
|vpiIndex:
\_ref_obj: (i), line:143
|vpiName:i
|vpiOperand:
\_bit_select: (id_unit_select), line:143
|vpiName:id_unit_select
|vpiIndex:
\_ref_obj: (i), line:143
|vpiName:i
|vpiParameter:
\_parameter: (ALU_UNIT_WB_ID), line:190
|vpiName:ALU_UNIT_WB_ID
|INT:32
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (BRANCH_PREDICTOR_WAYS), line:159
|vpiName:BRANCH_PREDICTOR_WAYS
|INT:9
|vpiParameter:
\_parameter: (BRANCH_TABLE_ENTRIES), line:160
|vpiName:BRANCH_TABLE_ENTRIES
|INT:4
|vpiParameter:
\_parameter: (BRANCH_UNIT_ID), line:195
|vpiName:BRANCH_UNIT_ID
|INT:8
|vpiParameter:
\_parameter: (BUS_ADDR_H), line:107
|vpiName:BUS_ADDR_H
|INT:1
|vpiParameter:
\_parameter: (BUS_ADDR_L), line:106
|vpiName:BUS_ADDR_L
|INT:0
|vpiParameter:
\_parameter: (BUS_BIT_CHECK), line:108
|vpiName:BUS_BIT_CHECK
|INT:1
|vpiParameter:
\_parameter: (BUS_TYPE), line:89
|vpiName:BUS_TYPE
|INT:5
|vpiParameter:
\_parameter: (COUNTER_W), line:42
|vpiName:COUNTER_W
|INT:33
|vpiParameter:
\_parameter: (CPU_ID), line:38
|vpiName:CPU_ID
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_ADDR_WIDTH), line:113
|vpiName:C_M_AXI_ADDR_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_DATA_WIDTH), line:114
|vpiName:C_M_AXI_DATA_WIDTH
|INT:1
|vpiParameter:
\_parameter: (DCACHE_LINES), line:133
|vpiName:DCACHE_LINES
|INT:-2146435073
|vpiParameter:
\_parameter: (DCACHE_LINE_ADDR_W), line:135
|vpiName:DCACHE_LINE_ADDR_W
|INT:1073741824
|vpiParameter:
\_parameter: (DCACHE_LINE_W), line:136
|vpiName:DCACHE_LINE_W
|INT:1342177279
|vpiParameter:
\_parameter: (DCACHE_SUB_LINE_ADDR_W), line:137
|vpiName:DCACHE_SUB_LINE_ADDR_W
|INT:4
|vpiParameter:
\_parameter: (DCACHE_TAG_W), line:138
|vpiName:DCACHE_TAG_W
|INT:1610612736
|vpiParameter:
\_parameter: (DCACHE_WAYS), line:134
|vpiName:DCACHE_WAYS
|INT:4
|vpiParameter:
\_parameter: (DIV_ALGORITHM), line:67
|vpiName:DIV_ALGORITHM
|INT:0
|vpiParameter:
\_parameter: (DIV_UNIT_WB_ID), line:192
|vpiName:DIV_UNIT_WB_ID
|INT:2
|vpiParameter:
\_parameter: (DTLB_DEPTH), line:152
|vpiName:DTLB_DEPTH
|INT:512
|vpiParameter:
\_parameter: (DTLB_WAYS), line:151
|vpiName:DTLB_WAYS
|INT:32
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (ENABLE_M_MODE), line:34
|vpiName:ENABLE_M_MODE
|INT:1
|vpiParameter:
\_parameter: (ENABLE_S_MODE), line:36
|vpiName:ENABLE_S_MODE
|INT:0
|vpiParameter:
\_parameter: (ENABLE_TRACE_INTERFACE), line:172
|vpiName:ENABLE_TRACE_INTERFACE
|INT:2
|vpiParameter:
\_parameter: (FETCH_BUFFER_DEPTH), line:168
|vpiName:FETCH_BUFFER_DEPTH
|INT:512
|vpiParameter:
\_parameter: (FPGA_VENDOR), line:27
|vpiName:FPGA_VENDOR
|STRING:"xilinx"
|vpiParameter:
\_parameter: (GC_UNIT_ID), line:196
|vpiName:GC_UNIT_ID
|INT:4
|vpiParameter:
\_parameter: (ICACHE_LINES), line:121
|vpiName:ICACHE_LINES
|INT:2
|vpiParameter:
\_parameter: (ICACHE_LINE_ADDR_W), line:123
|vpiName:ICACHE_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_LINE_W), line:124
|vpiName:ICACHE_LINE_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_SUB_LINE_ADDR_W), line:125
|vpiName:ICACHE_SUB_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_TAG_W), line:126
|vpiName:ICACHE_TAG_W
|INT:-2147483648
|vpiParameter:
\_parameter: (ICACHE_WAYS), line:122
|vpiName:ICACHE_WAYS
|INT:1
|vpiParameter:
\_parameter: (ITLB_DEPTH), line:146
|vpiName:ITLB_DEPTH
|INT:32
|vpiParameter:
\_parameter: (ITLB_WAYS), line:145
|vpiName:ITLB_WAYS
|INT:4
|vpiParameter:
\_parameter: (L1_CONNECTIONS), line:177
|vpiName:L1_CONNECTIONS
|INT:9
|vpiParameter:
\_parameter: (L1_DCACHE_ID), line:178
|vpiName:L1_DCACHE_ID
|INT:4
|vpiParameter:
\_parameter: (L1_DMMU_ID), line:179
|vpiName:L1_DMMU_ID
|INT:2
|vpiParameter:
\_parameter: (L1_ICACHE_ID), line:180
|vpiName:L1_ICACHE_ID
|INT:19
|vpiParameter:
\_parameter: (L1_IMMU_ID), line:181
|vpiName:L1_IMMU_ID
|INT:0
|vpiParameter:
\_parameter: (LS_UNIT_WB_ID), line:191
|vpiName:LS_UNIT_WB_ID
|INT:1
|vpiParameter:
\_parameter: (MAX_INFLIGHT_COUNT), line:167
|vpiName:MAX_INFLIGHT_COUNT
|INT:19
|vpiParameter:
\_parameter: (MEMORY_ADDR_H), line:103
|vpiName:MEMORY_ADDR_H
|INT:12
|vpiParameter:
\_parameter: (MEMORY_ADDR_L), line:102
|vpiName:MEMORY_ADDR_L
|INT:11
|vpiParameter:
\_parameter: (MEMORY_BIT_CHECK), line:104
|vpiName:MEMORY_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (MUL_UNIT_WB_ID), line:193
|vpiName:MUL_UNIT_WB_ID
|INT:512
|vpiParameter:
\_parameter: (NUM_UNITS), line:188
|vpiName:NUM_UNITS
|INT:2
|vpiParameter:
\_parameter: (NUM_WB_UNITS), line:186
|vpiName:NUM_WB_UNITS
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (RAS_DEPTH), line:161
|vpiName:RAS_DEPTH
|INT:2
|vpiParameter:
\_parameter: (RESET_VEC), line:39
|vpiName:RESET_VEC
|INT:-2147483648
|vpiParameter:
\_parameter: (SCRATCH_ADDR_H), line:99
|vpiName:SCRATCH_ADDR_H
|INT:9
|vpiParameter:
\_parameter: (SCRATCH_ADDR_L), line:98
|vpiName:SCRATCH_ADDR_L
|INT:8
|vpiParameter:
\_parameter: (SCRATCH_BIT_CHECK), line:100
|vpiName:SCRATCH_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (USE_AMO), line:70
|vpiName:USE_AMO
|INT:1
|vpiParameter:
\_parameter: (USE_BRANCH_PREDICTOR), line:158
|vpiName:USE_BRANCH_PREDICTOR
|INT:2
|vpiParameter:
\_parameter: (USE_BUS), line:88
|vpiName:USE_BUS
|INT:4
|vpiParameter:
\_parameter: (USE_DCACHE), line:92
|vpiName:USE_DCACHE
|INT:6
|vpiParameter:
\_parameter: (USE_DIV), line:49
|vpiName:USE_DIV
|INT:1
|vpiParameter:
\_parameter: (USE_DTAG_INVALIDATIONS), line:140
|vpiName:USE_DTAG_INVALIDATIONS
|INT:1879048191
|vpiParameter:
\_parameter: (USE_D_SCRATCH_MEM), line:79
|vpiName:USE_D_SCRATCH_MEM
|INT:3
|vpiParameter:
\_parameter: (USE_ICACHE), line:93
|vpiName:USE_ICACHE
|INT:7
|vpiParameter:
\_parameter: (USE_I_SCRATCH_MEM), line:78
|vpiName:USE_I_SCRATCH_MEM
|INT:2
|vpiParameter:
\_parameter: (USE_MUL), line:48
|vpiName:USE_MUL
|INT:1
|vpiParameter:
\_parameter: (WB_UNITS_WIDTH), line:187
|vpiName:WB_UNITS_WIDTH
|INT:32
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiParameter:
\_parameter: (i), line:140
|vpiName:i
|INT:14
|vpiGenScopeArray:
\_gen_scope_array: (genblk3[15]), line:140, parent:write_back_mux
|vpiName:genblk3[15]
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk3[15]
|vpiGenScope:
\_gen_scope: , parent:genblk3[15]
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk3[15]
|vpiProcess:
\_always: , line:141
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:141
|vpiCondition:
\_operation: , line:141
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:141
|vpiName:clk
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk3[15].clk
|vpiStmt:
\_begin: , line:141
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk3[15]
|vpiStmt:
\_if_stmt: , line:142
|vpiCondition:
\_operation: , line:142
|vpiOpType:29
|vpiOperand:
\_bit_select: (id_writing_to_buffer), line:142
|vpiName:id_writing_to_buffer
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk3[15].id_writing_to_buffer
|vpiIndex:
\_ref_obj: (i), line:142
|vpiName:i
|vpiOperand:
\_bit_select: (store_mux), line:142
|vpiName:store_mux
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk3[15].store_mux
|vpiIndex:
\_ref_obj: (i), line:142
|vpiName:i
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk3[15].i
|vpiStmt:
\_assignment: , line:143
|vpiOpType:82
|vpiLhs:
\_bit_select: (results_by_id), line:143
|vpiName:results_by_id
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk3[15].results_by_id
|vpiIndex:
\_ref_obj: (i), line:143
|vpiName:i
|vpiRhs:
\_bit_select: (unit_rd), line:143
|vpiName:unit_rd
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk3[15].unit_rd
|vpiIndex:
\_operation: , line:143
|vpiOpType:33
|vpiOperand:
\_bit_select: (store_mux), line:143
|vpiName:store_mux
|vpiIndex:
\_ref_obj: (i), line:143
|vpiName:i
|vpiOperand:
\_bit_select: (id_unit_select), line:143
|vpiName:id_unit_select
|vpiIndex:
\_ref_obj: (i), line:143
|vpiName:i
|vpiParameter:
\_parameter: (ALU_UNIT_WB_ID), line:190
|vpiName:ALU_UNIT_WB_ID
|INT:32
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (BRANCH_PREDICTOR_WAYS), line:159
|vpiName:BRANCH_PREDICTOR_WAYS
|INT:9
|vpiParameter:
\_parameter: (BRANCH_TABLE_ENTRIES), line:160
|vpiName:BRANCH_TABLE_ENTRIES
|INT:4
|vpiParameter:
\_parameter: (BRANCH_UNIT_ID), line:195
|vpiName:BRANCH_UNIT_ID
|INT:8
|vpiParameter:
\_parameter: (BUS_ADDR_H), line:107
|vpiName:BUS_ADDR_H
|INT:1
|vpiParameter:
\_parameter: (BUS_ADDR_L), line:106
|vpiName:BUS_ADDR_L
|INT:0
|vpiParameter:
\_parameter: (BUS_BIT_CHECK), line:108
|vpiName:BUS_BIT_CHECK
|INT:1
|vpiParameter:
\_parameter: (BUS_TYPE), line:89
|vpiName:BUS_TYPE
|INT:5
|vpiParameter:
\_parameter: (COUNTER_W), line:42
|vpiName:COUNTER_W
|INT:33
|vpiParameter:
\_parameter: (CPU_ID), line:38
|vpiName:CPU_ID
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_ADDR_WIDTH), line:113
|vpiName:C_M_AXI_ADDR_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_DATA_WIDTH), line:114
|vpiName:C_M_AXI_DATA_WIDTH
|INT:1
|vpiParameter:
\_parameter: (DCACHE_LINES), line:133
|vpiName:DCACHE_LINES
|INT:-2146435073
|vpiParameter:
\_parameter: (DCACHE_LINE_ADDR_W), line:135
|vpiName:DCACHE_LINE_ADDR_W
|INT:1073741824
|vpiParameter:
\_parameter: (DCACHE_LINE_W), line:136
|vpiName:DCACHE_LINE_W
|INT:1342177279
|vpiParameter:
\_parameter: (DCACHE_SUB_LINE_ADDR_W), line:137
|vpiName:DCACHE_SUB_LINE_ADDR_W
|INT:4
|vpiParameter:
\_parameter: (DCACHE_TAG_W), line:138
|vpiName:DCACHE_TAG_W
|INT:1610612736
|vpiParameter:
\_parameter: (DCACHE_WAYS), line:134
|vpiName:DCACHE_WAYS
|INT:4
|vpiParameter:
\_parameter: (DIV_ALGORITHM), line:67
|vpiName:DIV_ALGORITHM
|INT:0
|vpiParameter:
\_parameter: (DIV_UNIT_WB_ID), line:192
|vpiName:DIV_UNIT_WB_ID
|INT:2
|vpiParameter:
\_parameter: (DTLB_DEPTH), line:152
|vpiName:DTLB_DEPTH
|INT:512
|vpiParameter:
\_parameter: (DTLB_WAYS), line:151
|vpiName:DTLB_WAYS
|INT:32
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (ENABLE_M_MODE), line:34
|vpiName:ENABLE_M_MODE
|INT:1
|vpiParameter:
\_parameter: (ENABLE_S_MODE), line:36
|vpiName:ENABLE_S_MODE
|INT:0
|vpiParameter:
\_parameter: (ENABLE_TRACE_INTERFACE), line:172
|vpiName:ENABLE_TRACE_INTERFACE
|INT:2
|vpiParameter:
\_parameter: (FETCH_BUFFER_DEPTH), line:168
|vpiName:FETCH_BUFFER_DEPTH
|INT:512
|vpiParameter:
\_parameter: (FPGA_VENDOR), line:27
|vpiName:FPGA_VENDOR
|STRING:"xilinx"
|vpiParameter:
\_parameter: (GC_UNIT_ID), line:196
|vpiName:GC_UNIT_ID
|INT:4
|vpiParameter:
\_parameter: (ICACHE_LINES), line:121
|vpiName:ICACHE_LINES
|INT:2
|vpiParameter:
\_parameter: (ICACHE_LINE_ADDR_W), line:123
|vpiName:ICACHE_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_LINE_W), line:124
|vpiName:ICACHE_LINE_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_SUB_LINE_ADDR_W), line:125
|vpiName:ICACHE_SUB_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_TAG_W), line:126
|vpiName:ICACHE_TAG_W
|INT:-2147483648
|vpiParameter:
\_parameter: (ICACHE_WAYS), line:122
|vpiName:ICACHE_WAYS
|INT:1
|vpiParameter:
\_parameter: (ITLB_DEPTH), line:146
|vpiName:ITLB_DEPTH
|INT:32
|vpiParameter:
\_parameter: (ITLB_WAYS), line:145
|vpiName:ITLB_WAYS
|INT:4
|vpiParameter:
\_parameter: (L1_CONNECTIONS), line:177
|vpiName:L1_CONNECTIONS
|INT:9
|vpiParameter:
\_parameter: (L1_DCACHE_ID), line:178
|vpiName:L1_DCACHE_ID
|INT:4
|vpiParameter:
\_parameter: (L1_DMMU_ID), line:179
|vpiName:L1_DMMU_ID
|INT:2
|vpiParameter:
\_parameter: (L1_ICACHE_ID), line:180
|vpiName:L1_ICACHE_ID
|INT:19
|vpiParameter:
\_parameter: (L1_IMMU_ID), line:181
|vpiName:L1_IMMU_ID
|INT:0
|vpiParameter:
\_parameter: (LS_UNIT_WB_ID), line:191
|vpiName:LS_UNIT_WB_ID
|INT:1
|vpiParameter:
\_parameter: (MAX_INFLIGHT_COUNT), line:167
|vpiName:MAX_INFLIGHT_COUNT
|INT:19
|vpiParameter:
\_parameter: (MEMORY_ADDR_H), line:103
|vpiName:MEMORY_ADDR_H
|INT:12
|vpiParameter:
\_parameter: (MEMORY_ADDR_L), line:102
|vpiName:MEMORY_ADDR_L
|INT:11
|vpiParameter:
\_parameter: (MEMORY_BIT_CHECK), line:104
|vpiName:MEMORY_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (MUL_UNIT_WB_ID), line:193
|vpiName:MUL_UNIT_WB_ID
|INT:512
|vpiParameter:
\_parameter: (NUM_UNITS), line:188
|vpiName:NUM_UNITS
|INT:2
|vpiParameter:
\_parameter: (NUM_WB_UNITS), line:186
|vpiName:NUM_WB_UNITS
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (RAS_DEPTH), line:161
|vpiName:RAS_DEPTH
|INT:2
|vpiParameter:
\_parameter: (RESET_VEC), line:39
|vpiName:RESET_VEC
|INT:-2147483648
|vpiParameter:
\_parameter: (SCRATCH_ADDR_H), line:99
|vpiName:SCRATCH_ADDR_H
|INT:9
|vpiParameter:
\_parameter: (SCRATCH_ADDR_L), line:98
|vpiName:SCRATCH_ADDR_L
|INT:8
|vpiParameter:
\_parameter: (SCRATCH_BIT_CHECK), line:100
|vpiName:SCRATCH_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (USE_AMO), line:70
|vpiName:USE_AMO
|INT:1
|vpiParameter:
\_parameter: (USE_BRANCH_PREDICTOR), line:158
|vpiName:USE_BRANCH_PREDICTOR
|INT:2
|vpiParameter:
\_parameter: (USE_BUS), line:88
|vpiName:USE_BUS
|INT:4
|vpiParameter:
\_parameter: (USE_DCACHE), line:92
|vpiName:USE_DCACHE
|INT:6
|vpiParameter:
\_parameter: (USE_DIV), line:49
|vpiName:USE_DIV
|INT:1
|vpiParameter:
\_parameter: (USE_DTAG_INVALIDATIONS), line:140
|vpiName:USE_DTAG_INVALIDATIONS
|INT:1879048191
|vpiParameter:
\_parameter: (USE_D_SCRATCH_MEM), line:79
|vpiName:USE_D_SCRATCH_MEM
|INT:3
|vpiParameter:
\_parameter: (USE_ICACHE), line:93
|vpiName:USE_ICACHE
|INT:7
|vpiParameter:
\_parameter: (USE_I_SCRATCH_MEM), line:78
|vpiName:USE_I_SCRATCH_MEM
|INT:2
|vpiParameter:
\_parameter: (USE_MUL), line:48
|vpiName:USE_MUL
|INT:1
|vpiParameter:
\_parameter: (WB_UNITS_WIDTH), line:187
|vpiName:WB_UNITS_WIDTH
|INT:32
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiParameter:
\_parameter: (i), line:140
|vpiName:i
|INT:15
|vpiGenScopeArray:
\_gen_scope_array: (genblk3[16]), line:140, parent:write_back_mux
|vpiName:genblk3[16]
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk3[16]
|vpiGenScope:
\_gen_scope: , parent:genblk3[16]
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk3[16]
|vpiProcess:
\_always: , line:141
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:141
|vpiCondition:
\_operation: , line:141
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:141
|vpiName:clk
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk3[16].clk
|vpiStmt:
\_begin: , line:141
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk3[16]
|vpiStmt:
\_if_stmt: , line:142
|vpiCondition:
\_operation: , line:142
|vpiOpType:29
|vpiOperand:
\_bit_select: (id_writing_to_buffer), line:142
|vpiName:id_writing_to_buffer
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk3[16].id_writing_to_buffer
|vpiIndex:
\_ref_obj: (i), line:142
|vpiName:i
|vpiOperand:
\_bit_select: (store_mux), line:142
|vpiName:store_mux
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk3[16].store_mux
|vpiIndex:
\_ref_obj: (i), line:142
|vpiName:i
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk3[16].i
|vpiStmt:
\_assignment: , line:143
|vpiOpType:82
|vpiLhs:
\_bit_select: (results_by_id), line:143
|vpiName:results_by_id
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk3[16].results_by_id
|vpiIndex:
\_ref_obj: (i), line:143
|vpiName:i
|vpiRhs:
\_bit_select: (unit_rd), line:143
|vpiName:unit_rd
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk3[16].unit_rd
|vpiIndex:
\_operation: , line:143
|vpiOpType:33
|vpiOperand:
\_bit_select: (store_mux), line:143
|vpiName:store_mux
|vpiIndex:
\_ref_obj: (i), line:143
|vpiName:i
|vpiOperand:
\_bit_select: (id_unit_select), line:143
|vpiName:id_unit_select
|vpiIndex:
\_ref_obj: (i), line:143
|vpiName:i
|vpiParameter:
\_parameter: (ALU_UNIT_WB_ID), line:190
|vpiName:ALU_UNIT_WB_ID
|INT:32
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (BRANCH_PREDICTOR_WAYS), line:159
|vpiName:BRANCH_PREDICTOR_WAYS
|INT:9
|vpiParameter:
\_parameter: (BRANCH_TABLE_ENTRIES), line:160
|vpiName:BRANCH_TABLE_ENTRIES
|INT:4
|vpiParameter:
\_parameter: (BRANCH_UNIT_ID), line:195
|vpiName:BRANCH_UNIT_ID
|INT:8
|vpiParameter:
\_parameter: (BUS_ADDR_H), line:107
|vpiName:BUS_ADDR_H
|INT:1
|vpiParameter:
\_parameter: (BUS_ADDR_L), line:106
|vpiName:BUS_ADDR_L
|INT:0
|vpiParameter:
\_parameter: (BUS_BIT_CHECK), line:108
|vpiName:BUS_BIT_CHECK
|INT:1
|vpiParameter:
\_parameter: (BUS_TYPE), line:89
|vpiName:BUS_TYPE
|INT:5
|vpiParameter:
\_parameter: (COUNTER_W), line:42
|vpiName:COUNTER_W
|INT:33
|vpiParameter:
\_parameter: (CPU_ID), line:38
|vpiName:CPU_ID
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_ADDR_WIDTH), line:113
|vpiName:C_M_AXI_ADDR_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_DATA_WIDTH), line:114
|vpiName:C_M_AXI_DATA_WIDTH
|INT:1
|vpiParameter:
\_parameter: (DCACHE_LINES), line:133
|vpiName:DCACHE_LINES
|INT:-2146435073
|vpiParameter:
\_parameter: (DCACHE_LINE_ADDR_W), line:135
|vpiName:DCACHE_LINE_ADDR_W
|INT:1073741824
|vpiParameter:
\_parameter: (DCACHE_LINE_W), line:136
|vpiName:DCACHE_LINE_W
|INT:1342177279
|vpiParameter:
\_parameter: (DCACHE_SUB_LINE_ADDR_W), line:137
|vpiName:DCACHE_SUB_LINE_ADDR_W
|INT:4
|vpiParameter:
\_parameter: (DCACHE_TAG_W), line:138
|vpiName:DCACHE_TAG_W
|INT:1610612736
|vpiParameter:
\_parameter: (DCACHE_WAYS), line:134
|vpiName:DCACHE_WAYS
|INT:4
|vpiParameter:
\_parameter: (DIV_ALGORITHM), line:67
|vpiName:DIV_ALGORITHM
|INT:0
|vpiParameter:
\_parameter: (DIV_UNIT_WB_ID), line:192
|vpiName:DIV_UNIT_WB_ID
|INT:2
|vpiParameter:
\_parameter: (DTLB_DEPTH), line:152
|vpiName:DTLB_DEPTH
|INT:512
|vpiParameter:
\_parameter: (DTLB_WAYS), line:151
|vpiName:DTLB_WAYS
|INT:32
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (ENABLE_M_MODE), line:34
|vpiName:ENABLE_M_MODE
|INT:1
|vpiParameter:
\_parameter: (ENABLE_S_MODE), line:36
|vpiName:ENABLE_S_MODE
|INT:0
|vpiParameter:
\_parameter: (ENABLE_TRACE_INTERFACE), line:172
|vpiName:ENABLE_TRACE_INTERFACE
|INT:2
|vpiParameter:
\_parameter: (FETCH_BUFFER_DEPTH), line:168
|vpiName:FETCH_BUFFER_DEPTH
|INT:512
|vpiParameter:
\_parameter: (FPGA_VENDOR), line:27
|vpiName:FPGA_VENDOR
|STRING:"xilinx"
|vpiParameter:
\_parameter: (GC_UNIT_ID), line:196
|vpiName:GC_UNIT_ID
|INT:4
|vpiParameter:
\_parameter: (ICACHE_LINES), line:121
|vpiName:ICACHE_LINES
|INT:2
|vpiParameter:
\_parameter: (ICACHE_LINE_ADDR_W), line:123
|vpiName:ICACHE_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_LINE_W), line:124
|vpiName:ICACHE_LINE_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_SUB_LINE_ADDR_W), line:125
|vpiName:ICACHE_SUB_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_TAG_W), line:126
|vpiName:ICACHE_TAG_W
|INT:-2147483648
|vpiParameter:
\_parameter: (ICACHE_WAYS), line:122
|vpiName:ICACHE_WAYS
|INT:1
|vpiParameter:
\_parameter: (ITLB_DEPTH), line:146
|vpiName:ITLB_DEPTH
|INT:32
|vpiParameter:
\_parameter: (ITLB_WAYS), line:145
|vpiName:ITLB_WAYS
|INT:4
|vpiParameter:
\_parameter: (L1_CONNECTIONS), line:177
|vpiName:L1_CONNECTIONS
|INT:9
|vpiParameter:
\_parameter: (L1_DCACHE_ID), line:178
|vpiName:L1_DCACHE_ID
|INT:4
|vpiParameter:
\_parameter: (L1_DMMU_ID), line:179
|vpiName:L1_DMMU_ID
|INT:2
|vpiParameter:
\_parameter: (L1_ICACHE_ID), line:180
|vpiName:L1_ICACHE_ID
|INT:19
|vpiParameter:
\_parameter: (L1_IMMU_ID), line:181
|vpiName:L1_IMMU_ID
|INT:0
|vpiParameter:
\_parameter: (LS_UNIT_WB_ID), line:191
|vpiName:LS_UNIT_WB_ID
|INT:1
|vpiParameter:
\_parameter: (MAX_INFLIGHT_COUNT), line:167
|vpiName:MAX_INFLIGHT_COUNT
|INT:19
|vpiParameter:
\_parameter: (MEMORY_ADDR_H), line:103
|vpiName:MEMORY_ADDR_H
|INT:12
|vpiParameter:
\_parameter: (MEMORY_ADDR_L), line:102
|vpiName:MEMORY_ADDR_L
|INT:11
|vpiParameter:
\_parameter: (MEMORY_BIT_CHECK), line:104
|vpiName:MEMORY_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (MUL_UNIT_WB_ID), line:193
|vpiName:MUL_UNIT_WB_ID
|INT:512
|vpiParameter:
\_parameter: (NUM_UNITS), line:188
|vpiName:NUM_UNITS
|INT:2
|vpiParameter:
\_parameter: (NUM_WB_UNITS), line:186
|vpiName:NUM_WB_UNITS
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (RAS_DEPTH), line:161
|vpiName:RAS_DEPTH
|INT:2
|vpiParameter:
\_parameter: (RESET_VEC), line:39
|vpiName:RESET_VEC
|INT:-2147483648
|vpiParameter:
\_parameter: (SCRATCH_ADDR_H), line:99
|vpiName:SCRATCH_ADDR_H
|INT:9
|vpiParameter:
\_parameter: (SCRATCH_ADDR_L), line:98
|vpiName:SCRATCH_ADDR_L
|INT:8
|vpiParameter:
\_parameter: (SCRATCH_BIT_CHECK), line:100
|vpiName:SCRATCH_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (USE_AMO), line:70
|vpiName:USE_AMO
|INT:1
|vpiParameter:
\_parameter: (USE_BRANCH_PREDICTOR), line:158
|vpiName:USE_BRANCH_PREDICTOR
|INT:2
|vpiParameter:
\_parameter: (USE_BUS), line:88
|vpiName:USE_BUS
|INT:4
|vpiParameter:
\_parameter: (USE_DCACHE), line:92
|vpiName:USE_DCACHE
|INT:6
|vpiParameter:
\_parameter: (USE_DIV), line:49
|vpiName:USE_DIV
|INT:1
|vpiParameter:
\_parameter: (USE_DTAG_INVALIDATIONS), line:140
|vpiName:USE_DTAG_INVALIDATIONS
|INT:1879048191
|vpiParameter:
\_parameter: (USE_D_SCRATCH_MEM), line:79
|vpiName:USE_D_SCRATCH_MEM
|INT:3
|vpiParameter:
\_parameter: (USE_ICACHE), line:93
|vpiName:USE_ICACHE
|INT:7
|vpiParameter:
\_parameter: (USE_I_SCRATCH_MEM), line:78
|vpiName:USE_I_SCRATCH_MEM
|INT:2
|vpiParameter:
\_parameter: (USE_MUL), line:48
|vpiName:USE_MUL
|INT:1
|vpiParameter:
\_parameter: (WB_UNITS_WIDTH), line:187
|vpiName:WB_UNITS_WIDTH
|INT:32
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiParameter:
\_parameter: (i), line:140
|vpiName:i
|INT:16
|vpiGenScopeArray:
\_gen_scope_array: (genblk3[17]), line:140, parent:write_back_mux
|vpiName:genblk3[17]
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk3[17]
|vpiGenScope:
\_gen_scope: , parent:genblk3[17]
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk3[17]
|vpiProcess:
\_always: , line:141
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:141
|vpiCondition:
\_operation: , line:141
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:141
|vpiName:clk
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk3[17].clk
|vpiStmt:
\_begin: , line:141
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk3[17]
|vpiStmt:
\_if_stmt: , line:142
|vpiCondition:
\_operation: , line:142
|vpiOpType:29
|vpiOperand:
\_bit_select: (id_writing_to_buffer), line:142
|vpiName:id_writing_to_buffer
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk3[17].id_writing_to_buffer
|vpiIndex:
\_ref_obj: (i), line:142
|vpiName:i
|vpiOperand:
\_bit_select: (store_mux), line:142
|vpiName:store_mux
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk3[17].store_mux
|vpiIndex:
\_ref_obj: (i), line:142
|vpiName:i
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk3[17].i
|vpiStmt:
\_assignment: , line:143
|vpiOpType:82
|vpiLhs:
\_bit_select: (results_by_id), line:143
|vpiName:results_by_id
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk3[17].results_by_id
|vpiIndex:
\_ref_obj: (i), line:143
|vpiName:i
|vpiRhs:
\_bit_select: (unit_rd), line:143
|vpiName:unit_rd
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk3[17].unit_rd
|vpiIndex:
\_operation: , line:143
|vpiOpType:33
|vpiOperand:
\_bit_select: (store_mux), line:143
|vpiName:store_mux
|vpiIndex:
\_ref_obj: (i), line:143
|vpiName:i
|vpiOperand:
\_bit_select: (id_unit_select), line:143
|vpiName:id_unit_select
|vpiIndex:
\_ref_obj: (i), line:143
|vpiName:i
|vpiParameter:
\_parameter: (ALU_UNIT_WB_ID), line:190
|vpiName:ALU_UNIT_WB_ID
|INT:32
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (BRANCH_PREDICTOR_WAYS), line:159
|vpiName:BRANCH_PREDICTOR_WAYS
|INT:9
|vpiParameter:
\_parameter: (BRANCH_TABLE_ENTRIES), line:160
|vpiName:BRANCH_TABLE_ENTRIES
|INT:4
|vpiParameter:
\_parameter: (BRANCH_UNIT_ID), line:195
|vpiName:BRANCH_UNIT_ID
|INT:8
|vpiParameter:
\_parameter: (BUS_ADDR_H), line:107
|vpiName:BUS_ADDR_H
|INT:1
|vpiParameter:
\_parameter: (BUS_ADDR_L), line:106
|vpiName:BUS_ADDR_L
|INT:0
|vpiParameter:
\_parameter: (BUS_BIT_CHECK), line:108
|vpiName:BUS_BIT_CHECK
|INT:1
|vpiParameter:
\_parameter: (BUS_TYPE), line:89
|vpiName:BUS_TYPE
|INT:5
|vpiParameter:
\_parameter: (COUNTER_W), line:42
|vpiName:COUNTER_W
|INT:33
|vpiParameter:
\_parameter: (CPU_ID), line:38
|vpiName:CPU_ID
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_ADDR_WIDTH), line:113
|vpiName:C_M_AXI_ADDR_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_DATA_WIDTH), line:114
|vpiName:C_M_AXI_DATA_WIDTH
|INT:1
|vpiParameter:
\_parameter: (DCACHE_LINES), line:133
|vpiName:DCACHE_LINES
|INT:-2146435073
|vpiParameter:
\_parameter: (DCACHE_LINE_ADDR_W), line:135
|vpiName:DCACHE_LINE_ADDR_W
|INT:1073741824
|vpiParameter:
\_parameter: (DCACHE_LINE_W), line:136
|vpiName:DCACHE_LINE_W
|INT:1342177279
|vpiParameter:
\_parameter: (DCACHE_SUB_LINE_ADDR_W), line:137
|vpiName:DCACHE_SUB_LINE_ADDR_W
|INT:4
|vpiParameter:
\_parameter: (DCACHE_TAG_W), line:138
|vpiName:DCACHE_TAG_W
|INT:1610612736
|vpiParameter:
\_parameter: (DCACHE_WAYS), line:134
|vpiName:DCACHE_WAYS
|INT:4
|vpiParameter:
\_parameter: (DIV_ALGORITHM), line:67
|vpiName:DIV_ALGORITHM
|INT:0
|vpiParameter:
\_parameter: (DIV_UNIT_WB_ID), line:192
|vpiName:DIV_UNIT_WB_ID
|INT:2
|vpiParameter:
\_parameter: (DTLB_DEPTH), line:152
|vpiName:DTLB_DEPTH
|INT:512
|vpiParameter:
\_parameter: (DTLB_WAYS), line:151
|vpiName:DTLB_WAYS
|INT:32
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (ENABLE_M_MODE), line:34
|vpiName:ENABLE_M_MODE
|INT:1
|vpiParameter:
\_parameter: (ENABLE_S_MODE), line:36
|vpiName:ENABLE_S_MODE
|INT:0
|vpiParameter:
\_parameter: (ENABLE_TRACE_INTERFACE), line:172
|vpiName:ENABLE_TRACE_INTERFACE
|INT:2
|vpiParameter:
\_parameter: (FETCH_BUFFER_DEPTH), line:168
|vpiName:FETCH_BUFFER_DEPTH
|INT:512
|vpiParameter:
\_parameter: (FPGA_VENDOR), line:27
|vpiName:FPGA_VENDOR
|STRING:"xilinx"
|vpiParameter:
\_parameter: (GC_UNIT_ID), line:196
|vpiName:GC_UNIT_ID
|INT:4
|vpiParameter:
\_parameter: (ICACHE_LINES), line:121
|vpiName:ICACHE_LINES
|INT:2
|vpiParameter:
\_parameter: (ICACHE_LINE_ADDR_W), line:123
|vpiName:ICACHE_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_LINE_W), line:124
|vpiName:ICACHE_LINE_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_SUB_LINE_ADDR_W), line:125
|vpiName:ICACHE_SUB_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_TAG_W), line:126
|vpiName:ICACHE_TAG_W
|INT:-2147483648
|vpiParameter:
\_parameter: (ICACHE_WAYS), line:122
|vpiName:ICACHE_WAYS
|INT:1
|vpiParameter:
\_parameter: (ITLB_DEPTH), line:146
|vpiName:ITLB_DEPTH
|INT:32
|vpiParameter:
\_parameter: (ITLB_WAYS), line:145
|vpiName:ITLB_WAYS
|INT:4
|vpiParameter:
\_parameter: (L1_CONNECTIONS), line:177
|vpiName:L1_CONNECTIONS
|INT:9
|vpiParameter:
\_parameter: (L1_DCACHE_ID), line:178
|vpiName:L1_DCACHE_ID
|INT:4
|vpiParameter:
\_parameter: (L1_DMMU_ID), line:179
|vpiName:L1_DMMU_ID
|INT:2
|vpiParameter:
\_parameter: (L1_ICACHE_ID), line:180
|vpiName:L1_ICACHE_ID
|INT:19
|vpiParameter:
\_parameter: (L1_IMMU_ID), line:181
|vpiName:L1_IMMU_ID
|INT:0
|vpiParameter:
\_parameter: (LS_UNIT_WB_ID), line:191
|vpiName:LS_UNIT_WB_ID
|INT:1
|vpiParameter:
\_parameter: (MAX_INFLIGHT_COUNT), line:167
|vpiName:MAX_INFLIGHT_COUNT
|INT:19
|vpiParameter:
\_parameter: (MEMORY_ADDR_H), line:103
|vpiName:MEMORY_ADDR_H
|INT:12
|vpiParameter:
\_parameter: (MEMORY_ADDR_L), line:102
|vpiName:MEMORY_ADDR_L
|INT:11
|vpiParameter:
\_parameter: (MEMORY_BIT_CHECK), line:104
|vpiName:MEMORY_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (MUL_UNIT_WB_ID), line:193
|vpiName:MUL_UNIT_WB_ID
|INT:512
|vpiParameter:
\_parameter: (NUM_UNITS), line:188
|vpiName:NUM_UNITS
|INT:2
|vpiParameter:
\_parameter: (NUM_WB_UNITS), line:186
|vpiName:NUM_WB_UNITS
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (RAS_DEPTH), line:161
|vpiName:RAS_DEPTH
|INT:2
|vpiParameter:
\_parameter: (RESET_VEC), line:39
|vpiName:RESET_VEC
|INT:-2147483648
|vpiParameter:
\_parameter: (SCRATCH_ADDR_H), line:99
|vpiName:SCRATCH_ADDR_H
|INT:9
|vpiParameter:
\_parameter: (SCRATCH_ADDR_L), line:98
|vpiName:SCRATCH_ADDR_L
|INT:8
|vpiParameter:
\_parameter: (SCRATCH_BIT_CHECK), line:100
|vpiName:SCRATCH_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (USE_AMO), line:70
|vpiName:USE_AMO
|INT:1
|vpiParameter:
\_parameter: (USE_BRANCH_PREDICTOR), line:158
|vpiName:USE_BRANCH_PREDICTOR
|INT:2
|vpiParameter:
\_parameter: (USE_BUS), line:88
|vpiName:USE_BUS
|INT:4
|vpiParameter:
\_parameter: (USE_DCACHE), line:92
|vpiName:USE_DCACHE
|INT:6
|vpiParameter:
\_parameter: (USE_DIV), line:49
|vpiName:USE_DIV
|INT:1
|vpiParameter:
\_parameter: (USE_DTAG_INVALIDATIONS), line:140
|vpiName:USE_DTAG_INVALIDATIONS
|INT:1879048191
|vpiParameter:
\_parameter: (USE_D_SCRATCH_MEM), line:79
|vpiName:USE_D_SCRATCH_MEM
|INT:3
|vpiParameter:
\_parameter: (USE_ICACHE), line:93
|vpiName:USE_ICACHE
|INT:7
|vpiParameter:
\_parameter: (USE_I_SCRATCH_MEM), line:78
|vpiName:USE_I_SCRATCH_MEM
|INT:2
|vpiParameter:
\_parameter: (USE_MUL), line:48
|vpiName:USE_MUL
|INT:1
|vpiParameter:
\_parameter: (WB_UNITS_WIDTH), line:187
|vpiName:WB_UNITS_WIDTH
|INT:32
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiParameter:
\_parameter: (i), line:140
|vpiName:i
|INT:17
|vpiGenScopeArray:
\_gen_scope_array: (genblk3[18]), line:140, parent:write_back_mux
|vpiName:genblk3[18]
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk3[18]
|vpiGenScope:
\_gen_scope: , parent:genblk3[18]
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk3[18]
|vpiProcess:
\_always: , line:141
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:141
|vpiCondition:
\_operation: , line:141
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:141
|vpiName:clk
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk3[18].clk
|vpiStmt:
\_begin: , line:141
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk3[18]
|vpiStmt:
\_if_stmt: , line:142
|vpiCondition:
\_operation: , line:142
|vpiOpType:29
|vpiOperand:
\_bit_select: (id_writing_to_buffer), line:142
|vpiName:id_writing_to_buffer
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk3[18].id_writing_to_buffer
|vpiIndex:
\_ref_obj: (i), line:142
|vpiName:i
|vpiOperand:
\_bit_select: (store_mux), line:142
|vpiName:store_mux
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk3[18].store_mux
|vpiIndex:
\_ref_obj: (i), line:142
|vpiName:i
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk3[18].i
|vpiStmt:
\_assignment: , line:143
|vpiOpType:82
|vpiLhs:
\_bit_select: (results_by_id), line:143
|vpiName:results_by_id
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk3[18].results_by_id
|vpiIndex:
\_ref_obj: (i), line:143
|vpiName:i
|vpiRhs:
\_bit_select: (unit_rd), line:143
|vpiName:unit_rd
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk3[18].unit_rd
|vpiIndex:
\_operation: , line:143
|vpiOpType:33
|vpiOperand:
\_bit_select: (store_mux), line:143
|vpiName:store_mux
|vpiIndex:
\_ref_obj: (i), line:143
|vpiName:i
|vpiOperand:
\_bit_select: (id_unit_select), line:143
|vpiName:id_unit_select
|vpiIndex:
\_ref_obj: (i), line:143
|vpiName:i
|vpiParameter:
\_parameter: (ALU_UNIT_WB_ID), line:190
|vpiName:ALU_UNIT_WB_ID
|INT:32
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (BRANCH_PREDICTOR_WAYS), line:159
|vpiName:BRANCH_PREDICTOR_WAYS
|INT:9
|vpiParameter:
\_parameter: (BRANCH_TABLE_ENTRIES), line:160
|vpiName:BRANCH_TABLE_ENTRIES
|INT:4
|vpiParameter:
\_parameter: (BRANCH_UNIT_ID), line:195
|vpiName:BRANCH_UNIT_ID
|INT:8
|vpiParameter:
\_parameter: (BUS_ADDR_H), line:107
|vpiName:BUS_ADDR_H
|INT:1
|vpiParameter:
\_parameter: (BUS_ADDR_L), line:106
|vpiName:BUS_ADDR_L
|INT:0
|vpiParameter:
\_parameter: (BUS_BIT_CHECK), line:108
|vpiName:BUS_BIT_CHECK
|INT:1
|vpiParameter:
\_parameter: (BUS_TYPE), line:89
|vpiName:BUS_TYPE
|INT:5
|vpiParameter:
\_parameter: (COUNTER_W), line:42
|vpiName:COUNTER_W
|INT:33
|vpiParameter:
\_parameter: (CPU_ID), line:38
|vpiName:CPU_ID
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_ADDR_WIDTH), line:113
|vpiName:C_M_AXI_ADDR_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_DATA_WIDTH), line:114
|vpiName:C_M_AXI_DATA_WIDTH
|INT:1
|vpiParameter:
\_parameter: (DCACHE_LINES), line:133
|vpiName:DCACHE_LINES
|INT:-2146435073
|vpiParameter:
\_parameter: (DCACHE_LINE_ADDR_W), line:135
|vpiName:DCACHE_LINE_ADDR_W
|INT:1073741824
|vpiParameter:
\_parameter: (DCACHE_LINE_W), line:136
|vpiName:DCACHE_LINE_W
|INT:1342177279
|vpiParameter:
\_parameter: (DCACHE_SUB_LINE_ADDR_W), line:137
|vpiName:DCACHE_SUB_LINE_ADDR_W
|INT:4
|vpiParameter:
\_parameter: (DCACHE_TAG_W), line:138
|vpiName:DCACHE_TAG_W
|INT:1610612736
|vpiParameter:
\_parameter: (DCACHE_WAYS), line:134
|vpiName:DCACHE_WAYS
|INT:4
|vpiParameter:
\_parameter: (DIV_ALGORITHM), line:67
|vpiName:DIV_ALGORITHM
|INT:0
|vpiParameter:
\_parameter: (DIV_UNIT_WB_ID), line:192
|vpiName:DIV_UNIT_WB_ID
|INT:2
|vpiParameter:
\_parameter: (DTLB_DEPTH), line:152
|vpiName:DTLB_DEPTH
|INT:512
|vpiParameter:
\_parameter: (DTLB_WAYS), line:151
|vpiName:DTLB_WAYS
|INT:32
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (ENABLE_M_MODE), line:34
|vpiName:ENABLE_M_MODE
|INT:1
|vpiParameter:
\_parameter: (ENABLE_S_MODE), line:36
|vpiName:ENABLE_S_MODE
|INT:0
|vpiParameter:
\_parameter: (ENABLE_TRACE_INTERFACE), line:172
|vpiName:ENABLE_TRACE_INTERFACE
|INT:2
|vpiParameter:
\_parameter: (FETCH_BUFFER_DEPTH), line:168
|vpiName:FETCH_BUFFER_DEPTH
|INT:512
|vpiParameter:
\_parameter: (FPGA_VENDOR), line:27
|vpiName:FPGA_VENDOR
|STRING:"xilinx"
|vpiParameter:
\_parameter: (GC_UNIT_ID), line:196
|vpiName:GC_UNIT_ID
|INT:4
|vpiParameter:
\_parameter: (ICACHE_LINES), line:121
|vpiName:ICACHE_LINES
|INT:2
|vpiParameter:
\_parameter: (ICACHE_LINE_ADDR_W), line:123
|vpiName:ICACHE_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_LINE_W), line:124
|vpiName:ICACHE_LINE_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_SUB_LINE_ADDR_W), line:125
|vpiName:ICACHE_SUB_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_TAG_W), line:126
|vpiName:ICACHE_TAG_W
|INT:-2147483648
|vpiParameter:
\_parameter: (ICACHE_WAYS), line:122
|vpiName:ICACHE_WAYS
|INT:1
|vpiParameter:
\_parameter: (ITLB_DEPTH), line:146
|vpiName:ITLB_DEPTH
|INT:32
|vpiParameter:
\_parameter: (ITLB_WAYS), line:145
|vpiName:ITLB_WAYS
|INT:4
|vpiParameter:
\_parameter: (L1_CONNECTIONS), line:177
|vpiName:L1_CONNECTIONS
|INT:9
|vpiParameter:
\_parameter: (L1_DCACHE_ID), line:178
|vpiName:L1_DCACHE_ID
|INT:4
|vpiParameter:
\_parameter: (L1_DMMU_ID), line:179
|vpiName:L1_DMMU_ID
|INT:2
|vpiParameter:
\_parameter: (L1_ICACHE_ID), line:180
|vpiName:L1_ICACHE_ID
|INT:19
|vpiParameter:
\_parameter: (L1_IMMU_ID), line:181
|vpiName:L1_IMMU_ID
|INT:0
|vpiParameter:
\_parameter: (LS_UNIT_WB_ID), line:191
|vpiName:LS_UNIT_WB_ID
|INT:1
|vpiParameter:
\_parameter: (MAX_INFLIGHT_COUNT), line:167
|vpiName:MAX_INFLIGHT_COUNT
|INT:19
|vpiParameter:
\_parameter: (MEMORY_ADDR_H), line:103
|vpiName:MEMORY_ADDR_H
|INT:12
|vpiParameter:
\_parameter: (MEMORY_ADDR_L), line:102
|vpiName:MEMORY_ADDR_L
|INT:11
|vpiParameter:
\_parameter: (MEMORY_BIT_CHECK), line:104
|vpiName:MEMORY_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (MUL_UNIT_WB_ID), line:193
|vpiName:MUL_UNIT_WB_ID
|INT:512
|vpiParameter:
\_parameter: (NUM_UNITS), line:188
|vpiName:NUM_UNITS
|INT:2
|vpiParameter:
\_parameter: (NUM_WB_UNITS), line:186
|vpiName:NUM_WB_UNITS
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (RAS_DEPTH), line:161
|vpiName:RAS_DEPTH
|INT:2
|vpiParameter:
\_parameter: (RESET_VEC), line:39
|vpiName:RESET_VEC
|INT:-2147483648
|vpiParameter:
\_parameter: (SCRATCH_ADDR_H), line:99
|vpiName:SCRATCH_ADDR_H
|INT:9
|vpiParameter:
\_parameter: (SCRATCH_ADDR_L), line:98
|vpiName:SCRATCH_ADDR_L
|INT:8
|vpiParameter:
\_parameter: (SCRATCH_BIT_CHECK), line:100
|vpiName:SCRATCH_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (USE_AMO), line:70
|vpiName:USE_AMO
|INT:1
|vpiParameter:
\_parameter: (USE_BRANCH_PREDICTOR), line:158
|vpiName:USE_BRANCH_PREDICTOR
|INT:2
|vpiParameter:
\_parameter: (USE_BUS), line:88
|vpiName:USE_BUS
|INT:4
|vpiParameter:
\_parameter: (USE_DCACHE), line:92
|vpiName:USE_DCACHE
|INT:6
|vpiParameter:
\_parameter: (USE_DIV), line:49
|vpiName:USE_DIV
|INT:1
|vpiParameter:
\_parameter: (USE_DTAG_INVALIDATIONS), line:140
|vpiName:USE_DTAG_INVALIDATIONS
|INT:1879048191
|vpiParameter:
\_parameter: (USE_D_SCRATCH_MEM), line:79
|vpiName:USE_D_SCRATCH_MEM
|INT:3
|vpiParameter:
\_parameter: (USE_ICACHE), line:93
|vpiName:USE_ICACHE
|INT:7
|vpiParameter:
\_parameter: (USE_I_SCRATCH_MEM), line:78
|vpiName:USE_I_SCRATCH_MEM
|INT:2
|vpiParameter:
\_parameter: (USE_MUL), line:48
|vpiName:USE_MUL
|INT:1
|vpiParameter:
\_parameter: (WB_UNITS_WIDTH), line:187
|vpiName:WB_UNITS_WIDTH
|INT:32
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiParameter:
\_parameter: (i), line:140
|vpiName:i
|INT:18
|vpiGenScopeArray:
\_gen_scope_array: (genblk4), line:231, parent:write_back_mux
|vpiName:genblk4
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk4
|vpiGenScope:
\_gen_scope: , parent:genblk4
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk4
|vpiProcess:
\_always: , line:233
|vpiAlwaysType:2
|vpiStmt:
\_begin: , line:233
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk4
|vpiStmt:
\_assignment: , line:234
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (tr_wb_mux_contention), line:234
|vpiName:tr_wb_mux_contention
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk4.tr_wb_mux_contention
|vpiRhs:
\_constant: , line:234
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiStmt:
\_for_stmt: , line:235
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk4
|vpiCondition:
\_operation: , line:235
|vpiOpType:20
|vpiOperand:
\_ref_obj: (i), line:235
|vpiName:i
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk4.i
|vpiOperand:
\_operation: , line:235
|vpiOpType:11
|vpiOperand:
\_ref_obj: (MAX_INFLIGHT_COUNT), line:235
|vpiName:MAX_INFLIGHT_COUNT
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk4.MAX_INFLIGHT_COUNT
|vpiOperand:
\_constant: , line:235
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiForInitStmt:
\_assign_stmt:
|vpiRhs:
\_constant: , line:235
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiLhs:
\_int_var: (i), line:235
|vpiName:i
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk4.i
|vpiForIncStmt:
\_operation: , line:235
|vpiOpType:62
|vpiOperand:
\_ref_obj: (i), line:235
|vpiName:i
|vpiStmt:
\_begin: , line:235
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk4
|vpiStmt:
\_for_stmt: , line:236
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk4
|vpiCondition:
\_operation: , line:236
|vpiOpType:20
|vpiOperand:
\_ref_obj: (j), line:236
|vpiName:j
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk4.j
|vpiOperand:
\_ref_obj: (MAX_INFLIGHT_COUNT), line:236
|vpiName:MAX_INFLIGHT_COUNT
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk4.MAX_INFLIGHT_COUNT
|vpiForInitStmt:
\_assign_stmt:
|vpiRhs:
\_operation: , line:236
|vpiOpType:24
|vpiOperand:
\_ref_obj: (i), line:236
|vpiName:i
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk4.i
|vpiOperand:
\_constant: , line:236
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiLhs:
\_int_var: (j), line:236
|vpiName:j
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk4.j
|vpiForIncStmt:
\_operation: , line:236
|vpiOpType:62
|vpiOperand:
\_ref_obj: (j), line:236
|vpiName:j
|vpiStmt:
\_begin: , line:236
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk4
|vpiStmt:
\_assignment: , line:237
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (tr_wb_mux_contention), line:237
|vpiName:tr_wb_mux_contention
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk4.tr_wb_mux_contention
|vpiRhs:
\_operation: , line:237
|vpiOpType:28
|vpiOperand:
\_bit_select: (id_writeback_pending), line:237
|vpiName:id_writeback_pending
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk4.id_writeback_pending
|vpiIndex:
\_ref_obj: (i), line:237
|vpiName:i
|vpiOperand:
\_bit_select: (id_writeback_pending), line:237
|vpiName:id_writeback_pending
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk4.id_writeback_pending
|vpiIndex:
\_ref_obj: (j), line:237
|vpiName:j
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.genblk4.j
|vpiParameter:
\_parameter: (ALU_UNIT_WB_ID), line:190
|vpiName:ALU_UNIT_WB_ID
|INT:32
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (BRANCH_PREDICTOR_WAYS), line:159
|vpiName:BRANCH_PREDICTOR_WAYS
|INT:9
|vpiParameter:
\_parameter: (BRANCH_TABLE_ENTRIES), line:160
|vpiName:BRANCH_TABLE_ENTRIES
|INT:4
|vpiParameter:
\_parameter: (BRANCH_UNIT_ID), line:195
|vpiName:BRANCH_UNIT_ID
|INT:8
|vpiParameter:
\_parameter: (BUS_ADDR_H), line:107
|vpiName:BUS_ADDR_H
|INT:1
|vpiParameter:
\_parameter: (BUS_ADDR_L), line:106
|vpiName:BUS_ADDR_L
|INT:0
|vpiParameter:
\_parameter: (BUS_BIT_CHECK), line:108
|vpiName:BUS_BIT_CHECK
|INT:1
|vpiParameter:
\_parameter: (BUS_TYPE), line:89
|vpiName:BUS_TYPE
|INT:5
|vpiParameter:
\_parameter: (COUNTER_W), line:42
|vpiName:COUNTER_W
|INT:33
|vpiParameter:
\_parameter: (CPU_ID), line:38
|vpiName:CPU_ID
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_ADDR_WIDTH), line:113
|vpiName:C_M_AXI_ADDR_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_DATA_WIDTH), line:114
|vpiName:C_M_AXI_DATA_WIDTH
|INT:1
|vpiParameter:
\_parameter: (DCACHE_LINES), line:133
|vpiName:DCACHE_LINES
|INT:-2146435073
|vpiParameter:
\_parameter: (DCACHE_LINE_ADDR_W), line:135
|vpiName:DCACHE_LINE_ADDR_W
|INT:1073741824
|vpiParameter:
\_parameter: (DCACHE_LINE_W), line:136
|vpiName:DCACHE_LINE_W
|INT:1342177279
|vpiParameter:
\_parameter: (DCACHE_SUB_LINE_ADDR_W), line:137
|vpiName:DCACHE_SUB_LINE_ADDR_W
|INT:4
|vpiParameter:
\_parameter: (DCACHE_TAG_W), line:138
|vpiName:DCACHE_TAG_W
|INT:1610612736
|vpiParameter:
\_parameter: (DCACHE_WAYS), line:134
|vpiName:DCACHE_WAYS
|INT:4
|vpiParameter:
\_parameter: (DIV_ALGORITHM), line:67
|vpiName:DIV_ALGORITHM
|INT:0
|vpiParameter:
\_parameter: (DIV_UNIT_WB_ID), line:192
|vpiName:DIV_UNIT_WB_ID
|INT:2
|vpiParameter:
\_parameter: (DTLB_DEPTH), line:152
|vpiName:DTLB_DEPTH
|INT:512
|vpiParameter:
\_parameter: (DTLB_WAYS), line:151
|vpiName:DTLB_WAYS
|INT:32
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (ENABLE_M_MODE), line:34
|vpiName:ENABLE_M_MODE
|INT:1
|vpiParameter:
\_parameter: (ENABLE_S_MODE), line:36
|vpiName:ENABLE_S_MODE
|INT:0
|vpiParameter:
\_parameter: (ENABLE_TRACE_INTERFACE), line:172
|vpiName:ENABLE_TRACE_INTERFACE
|INT:2
|vpiParameter:
\_parameter: (FETCH_BUFFER_DEPTH), line:168
|vpiName:FETCH_BUFFER_DEPTH
|INT:512
|vpiParameter:
\_parameter: (FPGA_VENDOR), line:27
|vpiName:FPGA_VENDOR
|STRING:"xilinx"
|vpiParameter:
\_parameter: (GC_UNIT_ID), line:196
|vpiName:GC_UNIT_ID
|INT:4
|vpiParameter:
\_parameter: (ICACHE_LINES), line:121
|vpiName:ICACHE_LINES
|INT:2
|vpiParameter:
\_parameter: (ICACHE_LINE_ADDR_W), line:123
|vpiName:ICACHE_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_LINE_W), line:124
|vpiName:ICACHE_LINE_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_SUB_LINE_ADDR_W), line:125
|vpiName:ICACHE_SUB_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_TAG_W), line:126
|vpiName:ICACHE_TAG_W
|INT:-2147483648
|vpiParameter:
\_parameter: (ICACHE_WAYS), line:122
|vpiName:ICACHE_WAYS
|INT:1
|vpiParameter:
\_parameter: (ITLB_DEPTH), line:146
|vpiName:ITLB_DEPTH
|INT:32
|vpiParameter:
\_parameter: (ITLB_WAYS), line:145
|vpiName:ITLB_WAYS
|INT:4
|vpiParameter:
\_parameter: (L1_CONNECTIONS), line:177
|vpiName:L1_CONNECTIONS
|INT:9
|vpiParameter:
\_parameter: (L1_DCACHE_ID), line:178
|vpiName:L1_DCACHE_ID
|INT:4
|vpiParameter:
\_parameter: (L1_DMMU_ID), line:179
|vpiName:L1_DMMU_ID
|INT:2
|vpiParameter:
\_parameter: (L1_ICACHE_ID), line:180
|vpiName:L1_ICACHE_ID
|INT:19
|vpiParameter:
\_parameter: (L1_IMMU_ID), line:181
|vpiName:L1_IMMU_ID
|INT:0
|vpiParameter:
\_parameter: (LS_UNIT_WB_ID), line:191
|vpiName:LS_UNIT_WB_ID
|INT:1
|vpiParameter:
\_parameter: (MAX_INFLIGHT_COUNT), line:167
|vpiName:MAX_INFLIGHT_COUNT
|INT:19
|vpiParameter:
\_parameter: (MEMORY_ADDR_H), line:103
|vpiName:MEMORY_ADDR_H
|INT:12
|vpiParameter:
\_parameter: (MEMORY_ADDR_L), line:102
|vpiName:MEMORY_ADDR_L
|INT:11
|vpiParameter:
\_parameter: (MEMORY_BIT_CHECK), line:104
|vpiName:MEMORY_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (MUL_UNIT_WB_ID), line:193
|vpiName:MUL_UNIT_WB_ID
|INT:512
|vpiParameter:
\_parameter: (NUM_UNITS), line:188
|vpiName:NUM_UNITS
|INT:2
|vpiParameter:
\_parameter: (NUM_WB_UNITS), line:186
|vpiName:NUM_WB_UNITS
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (RAS_DEPTH), line:161
|vpiName:RAS_DEPTH
|INT:2
|vpiParameter:
\_parameter: (RESET_VEC), line:39
|vpiName:RESET_VEC
|INT:-2147483648
|vpiParameter:
\_parameter: (SCRATCH_ADDR_H), line:99
|vpiName:SCRATCH_ADDR_H
|INT:9
|vpiParameter:
\_parameter: (SCRATCH_ADDR_L), line:98
|vpiName:SCRATCH_ADDR_L
|INT:8
|vpiParameter:
\_parameter: (SCRATCH_BIT_CHECK), line:100
|vpiName:SCRATCH_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (USE_AMO), line:70
|vpiName:USE_AMO
|INT:1
|vpiParameter:
\_parameter: (USE_BRANCH_PREDICTOR), line:158
|vpiName:USE_BRANCH_PREDICTOR
|INT:2
|vpiParameter:
\_parameter: (USE_BUS), line:88
|vpiName:USE_BUS
|INT:4
|vpiParameter:
\_parameter: (USE_DCACHE), line:92
|vpiName:USE_DCACHE
|INT:6
|vpiParameter:
\_parameter: (USE_DIV), line:49
|vpiName:USE_DIV
|INT:1
|vpiParameter:
\_parameter: (USE_DTAG_INVALIDATIONS), line:140
|vpiName:USE_DTAG_INVALIDATIONS
|INT:1879048191
|vpiParameter:
\_parameter: (USE_D_SCRATCH_MEM), line:79
|vpiName:USE_D_SCRATCH_MEM
|INT:3
|vpiParameter:
\_parameter: (USE_ICACHE), line:93
|vpiName:USE_ICACHE
|INT:7
|vpiParameter:
\_parameter: (USE_I_SCRATCH_MEM), line:78
|vpiName:USE_I_SCRATCH_MEM
|INT:2
|vpiParameter:
\_parameter: (USE_MUL), line:48
|vpiName:USE_MUL
|INT:1
|vpiParameter:
\_parameter: (WB_UNITS_WIDTH), line:187
|vpiName:WB_UNITS_WIDTH
|INT:32
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiNet:
\_logic_net: (clk), line:27, parent:write_back_mux
|vpiNet:
\_logic_net: (rst), line:28, parent:write_back_mux
|vpiNet:
\_logic_net: (gc_fetch_flush), line:30, parent:write_back_mux
|vpiNet:
\_logic_net: (instruction_issued_with_rd), line:31, parent:write_back_mux
|vpiNet:
\_logic_net: (unit_wb), line:33, parent:write_back_mux
|vpiNet:
\_logic_net: (instruction_complete), line:36, parent:write_back_mux
|vpiNet:
\_logic_net: (instruction_queue_empty), line:37, parent:write_back_mux
|vpiNet:
\_logic_net: (oldest_id), line:38, parent:write_back_mux
|vpiNet:
\_logic_net: (store_done_id), line:40, parent:write_back_mux
|vpiNet:
\_logic_net: (store_complete), line:41, parent:write_back_mux
|vpiNet:
\_logic_net: (store_issued_with_data), line:44, parent:write_back_mux
|vpiNet:
\_logic_net: (store_data), line:45, parent:write_back_mux
|vpiNet:
\_logic_net: (tr_wb_mux_contention), line:48, parent:write_back_mux
|vpiNet:
\_logic_net: (unit_done), line:57, parent:write_back_mux
|vpiName:unit_done
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.unit_done
|vpiNetType:36
|vpiRange:
\_range: , line:57
|vpiLeftRange:
\_constant: , line:57
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:57
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (id_inuse), line:69, parent:write_back_mux
|vpiName:id_inuse
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.id_inuse
|vpiNetType:36
|vpiRange:
\_range: , line:69
|vpiLeftRange:
\_constant: , line:69
|vpiConstType:7
|vpiDecompile:18
|vpiSize:32
|INT:18
|vpiRightRange:
\_constant: , line:69
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (id_writeback_pending), line:71, parent:write_back_mux
|vpiName:id_writeback_pending
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.id_writeback_pending
|vpiNetType:36
|vpiRange:
\_range: , line:71
|vpiLeftRange:
\_constant: , line:71
|vpiConstType:7
|vpiDecompile:18
|vpiSize:32
|INT:18
|vpiRightRange:
\_constant: , line:71
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (id_writeback_pending_r), line:72, parent:write_back_mux
|vpiName:id_writeback_pending_r
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.id_writeback_pending_r
|vpiNetType:36
|vpiRange:
\_range: , line:72
|vpiLeftRange:
\_constant: , line:72
|vpiConstType:7
|vpiDecompile:18
|vpiSize:32
|INT:18
|vpiRightRange:
\_constant: , line:72
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (id_writing_to_buffer), line:74, parent:write_back_mux
|vpiName:id_writing_to_buffer
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.id_writing_to_buffer
|vpiNetType:36
|vpiRange:
\_range: , line:74
|vpiLeftRange:
\_constant: , line:74
|vpiConstType:7
|vpiDecompile:18
|vpiSize:32
|INT:18
|vpiRightRange:
\_constant: , line:74
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (id_retiring_one_hot), line:76, parent:write_back_mux
|vpiName:id_retiring_one_hot
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.id_retiring_one_hot
|vpiNetType:36
|vpiRange:
\_range: , line:76
|vpiLeftRange:
\_constant: , line:76
|vpiConstType:7
|vpiDecompile:18
|vpiSize:32
|INT:18
|vpiRightRange:
\_constant: , line:76
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (id_issued_one_hot), line:77, parent:write_back_mux
|vpiName:id_issued_one_hot
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.id_issued_one_hot
|vpiNetType:36
|vpiRange:
\_range: , line:77
|vpiLeftRange:
\_constant: , line:77
|vpiConstType:7
|vpiDecompile:18
|vpiSize:32
|INT:18
|vpiRightRange:
\_constant: , line:77
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (retiring_next_cycle), line:79, parent:write_back_mux
|vpiName:retiring_next_cycle
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.retiring_next_cycle
|vpiNetType:36
|vpiNet:
\_logic_net: (retiring), line:79, parent:write_back_mux
|vpiName:retiring
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.retiring
|vpiNetType:36
|vpiNet:
\_logic_net: (store_mux), line:134, parent:write_back_mux
|vpiName:store_mux
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.store_mux
|vpiNetType:36
|vpiRange:
\_range: , line:134
|vpiLeftRange:
\_constant: , line:134
|vpiConstType:7
|vpiDecompile:18
|vpiSize:32
|INT:18
|vpiRightRange:
\_constant: , line:134
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (rf_wb), line:34, parent:write_back_mux
|vpiName:rf_wb
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.rf_wb
|vpiNet:
\_logic_net: (ti), line:35, parent:write_back_mux
|vpiName:ti
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.ti
|vpiNet:
\_logic_net: (store_forwarding), line:42, parent:write_back_mux
|vpiName:store_forwarding
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.store_forwarding
|vpiInstance:
\_module: work@taiga (cpu), file:third_party/cores/taiga/examples/zedboard/taiga_wrapper.sv, line:233, parent:work@taiga_wrapper
|vpiArrayNet:
\_array_net: (id_metadata), line:53, parent:write_back_mux
|vpiName:id_metadata
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.id_metadata
|vpiSize:19
|vpiNet:
\_logic_net: , parent:id_metadata
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.id_metadata
|vpiNetType:36
|vpiRange:
\_range: , line:53
|vpiLeftRange:
\_constant: , line:53
|vpiDecompile:5
|INT:5
|vpiRightRange:
\_constant: , line:53
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiRange:
\_range: , line:53
|vpiLeftRange:
\_constant: , line:53
|vpiConstType:7
|vpiDecompile:18
|vpiSize:32
|INT:18
|vpiRightRange:
\_constant: , line:53
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiArrayNet:
\_array_net: (unit_rd), line:59, parent:write_back_mux
|vpiName:unit_rd
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.unit_rd
|vpiSize:4
|vpiNet:
\_logic_net: , parent:unit_rd
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.unit_rd
|vpiNetType:36
|vpiRange:
\_range: , line:59
|vpiLeftRange:
\_constant: , line:59
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiRightRange:
\_constant: , line:59
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiRange:
\_range: , line:59
|vpiLeftRange:
\_constant: , line:59
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiRightRange:
\_constant: , line:59
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiArrayNet:
\_array_net: (id_unit_select), line:61, parent:write_back_mux
|vpiName:id_unit_select
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.id_unit_select
|vpiSize:19
|vpiNet:
\_logic_net: , parent:id_unit_select
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.id_unit_select
|vpiNetType:36
|vpiRange:
\_range: , line:61
|vpiLeftRange:
\_constant: , line:61
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiRightRange:
\_constant: , line:61
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiRange:
\_range: , line:61
|vpiLeftRange:
\_constant: , line:61
|vpiConstType:7
|vpiDecompile:18
|vpiSize:32
|INT:18
|vpiRightRange:
\_constant: , line:61
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiArrayNet:
\_array_net: (id_unit_select_r), line:62, parent:write_back_mux
|vpiName:id_unit_select_r
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.id_unit_select_r
|vpiSize:19
|vpiNet:
\_logic_net: , parent:id_unit_select_r
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.id_unit_select_r
|vpiNetType:36
|vpiRange:
\_range: , line:62
|vpiLeftRange:
\_constant: , line:62
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiRightRange:
\_constant: , line:62
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiRange:
\_range: , line:62
|vpiLeftRange:
\_constant: , line:62
|vpiConstType:7
|vpiDecompile:18
|vpiSize:32
|INT:18
|vpiRightRange:
\_constant: , line:62
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiArrayNet:
\_array_net: (results_by_id), line:64, parent:write_back_mux
|vpiName:results_by_id
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.results_by_id
|vpiSize:19
|vpiNet:
\_logic_net: , parent:results_by_id
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.results_by_id
|vpiNetType:36
|vpiRange:
\_range: , line:64
|vpiLeftRange:
\_constant: , line:64
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiRightRange:
\_constant: , line:64
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiRange:
\_range: , line:64
|vpiLeftRange:
\_constant: , line:64
|vpiConstType:7
|vpiDecompile:18
|vpiSize:32
|INT:18
|vpiRightRange:
\_constant: , line:64
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiArrayNet:
\_array_net: (results_by_id_new), line:65, parent:write_back_mux
|vpiName:results_by_id_new
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.results_by_id_new
|vpiSize:19
|vpiNet:
\_logic_net: , parent:results_by_id_new
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.results_by_id_new
|vpiNetType:36
|vpiRange:
\_range: , line:65
|vpiLeftRange:
\_constant: , line:65
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiRightRange:
\_constant: , line:65
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiRange:
\_range: , line:65
|vpiLeftRange:
\_constant: , line:65
|vpiConstType:7
|vpiDecompile:18
|vpiSize:32
|INT:18
|vpiRightRange:
\_constant: , line:65
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiVariables:
\_array_var: (unit_instruction_id), parent:write_back_mux
|vpiArrayType:1
|vpiName:unit_instruction_id
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.unit_instruction_id
|vpiRandType:1
|vpiVisibility:1
|vpiSize:2
|vpiReg:
\_logic_var: (unit_instruction_id), line:56, parent:unit_instruction_id
|vpiName:unit_instruction_id
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.unit_instruction_id.unit_instruction_id
|vpiRange:
\_range: , line:56
|vpiLeftRange:
\_constant: , line:56
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:56
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiVariables:
\_logic_var: (id_retiring), line:66, parent:write_back_mux
|vpiName:id_retiring
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.id_retiring
|vpiVariables:
\_struct_var: (retiring_instruction_packet), line:67, parent:write_back_mux
|vpiName:retiring_instruction_packet
|vpiFullName:work@taiga_wrapper.cpu.write_back_mux.retiring_instruction_packet
|vpiTypespec:
\_struct_typespec: (inflight_instruction_packet), line:271
|vpiParameter:
\_parameter: (ALU_UNIT_WB_ID), line:190
|vpiName:ALU_UNIT_WB_ID
|INT:32
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (BRANCH_PREDICTOR_WAYS), line:159
|vpiName:BRANCH_PREDICTOR_WAYS
|INT:9
|vpiParameter:
\_parameter: (BRANCH_TABLE_ENTRIES), line:160
|vpiName:BRANCH_TABLE_ENTRIES
|INT:4
|vpiParameter:
\_parameter: (BRANCH_UNIT_ID), line:195
|vpiName:BRANCH_UNIT_ID
|INT:8
|vpiParameter:
\_parameter: (BUS_ADDR_H), line:107
|vpiName:BUS_ADDR_H
|INT:1
|vpiParameter:
\_parameter: (BUS_ADDR_L), line:106
|vpiName:BUS_ADDR_L
|INT:0
|vpiParameter:
\_parameter: (BUS_BIT_CHECK), line:108
|vpiName:BUS_BIT_CHECK
|INT:1
|vpiParameter:
\_parameter: (BUS_TYPE), line:89
|vpiName:BUS_TYPE
|INT:5
|vpiParameter:
\_parameter: (COUNTER_W), line:42
|vpiName:COUNTER_W
|INT:33
|vpiParameter:
\_parameter: (CPU_ID), line:38
|vpiName:CPU_ID
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_ADDR_WIDTH), line:113
|vpiName:C_M_AXI_ADDR_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_DATA_WIDTH), line:114
|vpiName:C_M_AXI_DATA_WIDTH
|INT:1
|vpiParameter:
\_parameter: (DCACHE_LINES), line:133
|vpiName:DCACHE_LINES
|INT:-2146435073
|vpiParameter:
\_parameter: (DCACHE_LINE_ADDR_W), line:135
|vpiName:DCACHE_LINE_ADDR_W
|INT:1073741824
|vpiParameter:
\_parameter: (DCACHE_LINE_W), line:136
|vpiName:DCACHE_LINE_W
|INT:1342177279
|vpiParameter:
\_parameter: (DCACHE_SUB_LINE_ADDR_W), line:137
|vpiName:DCACHE_SUB_LINE_ADDR_W
|INT:4
|vpiParameter:
\_parameter: (DCACHE_TAG_W), line:138
|vpiName:DCACHE_TAG_W
|INT:1610612736
|vpiParameter:
\_parameter: (DCACHE_WAYS), line:134
|vpiName:DCACHE_WAYS
|INT:4
|vpiParameter:
\_parameter: (DIV_ALGORITHM), line:67
|vpiName:DIV_ALGORITHM
|INT:0
|vpiParameter:
\_parameter: (DIV_UNIT_WB_ID), line:192
|vpiName:DIV_UNIT_WB_ID
|INT:2
|vpiParameter:
\_parameter: (DTLB_DEPTH), line:152
|vpiName:DTLB_DEPTH
|INT:512
|vpiParameter:
\_parameter: (DTLB_WAYS), line:151
|vpiName:DTLB_WAYS
|INT:32
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (ENABLE_M_MODE), line:34
|vpiName:ENABLE_M_MODE
|INT:1
|vpiParameter:
\_parameter: (ENABLE_S_MODE), line:36
|vpiName:ENABLE_S_MODE
|INT:0
|vpiParameter:
\_parameter: (ENABLE_TRACE_INTERFACE), line:172
|vpiName:ENABLE_TRACE_INTERFACE
|INT:2
|vpiParameter:
\_parameter: (FETCH_BUFFER_DEPTH), line:168
|vpiName:FETCH_BUFFER_DEPTH
|INT:512
|vpiParameter:
\_parameter: (FPGA_VENDOR), line:27
|vpiName:FPGA_VENDOR
|STRING:"xilinx"
|vpiParameter:
\_parameter: (GC_UNIT_ID), line:196
|vpiName:GC_UNIT_ID
|INT:4
|vpiParameter:
\_parameter: (ICACHE_LINES), line:121
|vpiName:ICACHE_LINES
|INT:2
|vpiParameter:
\_parameter: (ICACHE_LINE_ADDR_W), line:123
|vpiName:ICACHE_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_LINE_W), line:124
|vpiName:ICACHE_LINE_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_SUB_LINE_ADDR_W), line:125
|vpiName:ICACHE_SUB_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_TAG_W), line:126
|vpiName:ICACHE_TAG_W
|INT:-2147483648
|vpiParameter:
\_parameter: (ICACHE_WAYS), line:122
|vpiName:ICACHE_WAYS
|INT:1
|vpiParameter:
\_parameter: (ITLB_DEPTH), line:146
|vpiName:ITLB_DEPTH
|INT:32
|vpiParameter:
\_parameter: (ITLB_WAYS), line:145
|vpiName:ITLB_WAYS
|INT:4
|vpiParameter:
\_parameter: (L1_CONNECTIONS), line:177
|vpiName:L1_CONNECTIONS
|INT:9
|vpiParameter:
\_parameter: (L1_DCACHE_ID), line:178
|vpiName:L1_DCACHE_ID
|INT:4
|vpiParameter:
\_parameter: (L1_DMMU_ID), line:179
|vpiName:L1_DMMU_ID
|INT:2
|vpiParameter:
\_parameter: (L1_ICACHE_ID), line:180
|vpiName:L1_ICACHE_ID
|INT:19
|vpiParameter:
\_parameter: (L1_IMMU_ID), line:181
|vpiName:L1_IMMU_ID
|INT:0
|vpiParameter:
\_parameter: (LS_UNIT_WB_ID), line:191
|vpiName:LS_UNIT_WB_ID
|INT:1
|vpiParameter:
\_parameter: (MAX_INFLIGHT_COUNT), line:167
|vpiName:MAX_INFLIGHT_COUNT
|INT:19
|vpiParameter:
\_parameter: (MEMORY_ADDR_H), line:103
|vpiName:MEMORY_ADDR_H
|INT:12
|vpiParameter:
\_parameter: (MEMORY_ADDR_L), line:102
|vpiName:MEMORY_ADDR_L
|INT:11
|vpiParameter:
\_parameter: (MEMORY_BIT_CHECK), line:104
|vpiName:MEMORY_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (MUL_UNIT_WB_ID), line:193
|vpiName:MUL_UNIT_WB_ID
|INT:512
|vpiParameter:
\_parameter: (NUM_UNITS), line:188
|vpiName:NUM_UNITS
|INT:2
|vpiParameter:
\_parameter: (NUM_WB_UNITS), line:186
|vpiName:NUM_WB_UNITS
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (RAS_DEPTH), line:161
|vpiName:RAS_DEPTH
|INT:2
|vpiParameter:
\_parameter: (RESET_VEC), line:39
|vpiName:RESET_VEC
|INT:-2147483648
|vpiParameter:
\_parameter: (SCRATCH_ADDR_H), line:99
|vpiName:SCRATCH_ADDR_H
|INT:9
|vpiParameter:
\_parameter: (SCRATCH_ADDR_L), line:98
|vpiName:SCRATCH_ADDR_L
|INT:8
|vpiParameter:
\_parameter: (SCRATCH_BIT_CHECK), line:100
|vpiName:SCRATCH_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (USE_AMO), line:70
|vpiName:USE_AMO
|INT:1
|vpiParameter:
\_parameter: (USE_BRANCH_PREDICTOR), line:158
|vpiName:USE_BRANCH_PREDICTOR
|INT:2
|vpiParameter:
\_parameter: (USE_BUS), line:88
|vpiName:USE_BUS
|INT:4
|vpiParameter:
\_parameter: (USE_DCACHE), line:92
|vpiName:USE_DCACHE
|INT:6
|vpiParameter:
\_parameter: (USE_DIV), line:49
|vpiName:USE_DIV
|INT:1
|vpiParameter:
\_parameter: (USE_DTAG_INVALIDATIONS), line:140
|vpiName:USE_DTAG_INVALIDATIONS
|INT:1879048191
|vpiParameter:
\_parameter: (USE_D_SCRATCH_MEM), line:79
|vpiName:USE_D_SCRATCH_MEM
|INT:3
|vpiParameter:
\_parameter: (USE_ICACHE), line:93
|vpiName:USE_ICACHE
|INT:7
|vpiParameter:
\_parameter: (USE_I_SCRATCH_MEM), line:78
|vpiName:USE_I_SCRATCH_MEM
|INT:2
|vpiParameter:
\_parameter: (USE_MUL), line:48
|vpiName:USE_MUL
|INT:1
|vpiParameter:
\_parameter: (WB_UNITS_WIDTH), line:187
|vpiName:WB_UNITS_WIDTH
|INT:32
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiGenScopeArray:
\_gen_scope_array: (genblk1), line:154, parent:cpu
|vpiName:genblk1
|vpiFullName:work@taiga_wrapper.cpu.genblk1
|vpiGenScope:
\_gen_scope: , parent:genblk1
|vpiFullName:work@taiga_wrapper.cpu.genblk1
|vpiModule:
\_module: work@l1_arbiter (arb), file:third_party/cores/taiga/core/taiga.sv, line:155
|vpiDefName:work@l1_arbiter
|vpiName:arb
|vpiFullName:work@taiga_wrapper.cpu.genblk1.arb
|vpiPort:
\_port: (clk), line:29, parent:arb
|vpiName:clk
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (clk), line:155
|vpiName:clk
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (clk), line:29, parent:arb
|vpiName:clk
|vpiFullName:work@taiga_wrapper.cpu.genblk1.arb.clk
|vpiNetType:36
|vpiPort:
\_port: (rst), line:30, parent:arb
|vpiName:rst
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (rst), line:155
|vpiName:rst
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (rst), line:30, parent:arb
|vpiName:rst
|vpiFullName:work@taiga_wrapper.cpu.genblk1.arb.rst
|vpiNetType:36
|vpiPort:
\_port: (l2), line:32, parent:arb
|vpiName:l2
|vpiDirection:5
|vpiHighConn:
\_ref_obj: (l2), line:155
|vpiName:l2
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_modport: (master)
|vpiName:master
|vpiIODecl:
\_io_decl: (addr)
|vpiName:addr
|vpiDirection:2
|vpiExpr:
\_logic_net: (addr), line:27
|vpiName:addr
|vpiNetType:36
|vpiRange:
\_range: , line:27
|vpiLeftRange:
\_constant: , line:27
|vpiConstType:7
|vpiDecompile:29
|vpiSize:32
|INT:29
|vpiRightRange:
\_constant: , line:27
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (be)
|vpiName:be
|vpiDirection:2
|vpiExpr:
\_logic_net: (be), line:28
|vpiName:be
|vpiNetType:36
|vpiRange:
\_range: , line:28
|vpiLeftRange:
\_constant: , line:28
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiRightRange:
\_constant: , line:28
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (rnw)
|vpiName:rnw
|vpiDirection:2
|vpiExpr:
\_logic_net: (rnw), line:29
|vpiName:rnw
|vpiNetType:36
|vpiIODecl:
\_io_decl: (is_amo)
|vpiName:is_amo
|vpiDirection:2
|vpiExpr:
\_logic_net: (is_amo), line:30
|vpiName:is_amo
|vpiNetType:36
|vpiIODecl:
\_io_decl: (amo_type_or_burst_size)
|vpiName:amo_type_or_burst_size
|vpiDirection:2
|vpiExpr:
\_logic_net: (amo_type_or_burst_size), line:31
|vpiName:amo_type_or_burst_size
|vpiNetType:36
|vpiRange:
\_range: , line:31
|vpiLeftRange:
\_constant: , line:31
|vpiConstType:7
|vpiDecompile:4
|vpiSize:32
|INT:4
|vpiRightRange:
\_constant: , line:31
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (sub_id)
|vpiName:sub_id
|vpiDirection:2
|vpiExpr:
\_logic_net: (sub_id), line:32
|vpiName:sub_id
|vpiNetType:36
|vpiRange:
\_range: , line:32
|vpiLeftRange:
\_constant: , line:32
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:32
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (request_push)
|vpiName:request_push
|vpiDirection:2
|vpiExpr:
\_logic_net: (request_push), line:34
|vpiName:request_push
|vpiNetType:36
|vpiIODecl:
\_io_decl: (request_full)
|vpiName:request_full
|vpiDirection:1
|vpiExpr:
\_logic_net: (request_full), line:35
|vpiName:request_full
|vpiNetType:36
|vpiIODecl:
\_io_decl: (inv_addr)
|vpiName:inv_addr
|vpiDirection:1
|vpiExpr:
\_logic_net: (inv_addr), line:37
|vpiName:inv_addr
|vpiNetType:36
|vpiRange:
\_range: , line:37
|vpiLeftRange:
\_constant: , line:37
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:37
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiIODecl:
\_io_decl: (inv_valid)
|vpiName:inv_valid
|vpiDirection:1
|vpiExpr:
\_logic_net: (inv_valid), line:38
|vpiName:inv_valid
|vpiNetType:36
|vpiIODecl:
\_io_decl: (inv_ack)
|vpiName:inv_ack
|vpiDirection:2
|vpiExpr:
\_logic_net: (inv_ack), line:39
|vpiName:inv_ack
|vpiNetType:36
|vpiIODecl:
\_io_decl: (con_result)
|vpiName:con_result
|vpiDirection:1
|vpiExpr:
\_logic_net: (con_result), line:41
|vpiName:con_result
|vpiNetType:36
|vpiIODecl:
\_io_decl: (con_valid)
|vpiName:con_valid
|vpiDirection:1
|vpiExpr:
\_logic_net: (con_valid), line:42
|vpiName:con_valid
|vpiNetType:36
|vpiIODecl:
\_io_decl: (wr_data)
|vpiName:wr_data
|vpiDirection:2
|vpiExpr:
\_logic_net: (wr_data), line:44
|vpiName:wr_data
|vpiNetType:36
|vpiRange:
\_range: , line:44
|vpiLeftRange:
\_constant: , line:44
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:44
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (wr_data_push)
|vpiName:wr_data_push
|vpiDirection:2
|vpiExpr:
\_logic_net: (wr_data_push), line:45
|vpiName:wr_data_push
|vpiNetType:36
|vpiIODecl:
\_io_decl: (data_full)
|vpiName:data_full
|vpiDirection:1
|vpiExpr:
\_logic_net: (data_full), line:46
|vpiName:data_full
|vpiNetType:36
|vpiIODecl:
\_io_decl: (rd_data)
|vpiName:rd_data
|vpiDirection:1
|vpiExpr:
\_logic_net: (rd_data), line:48
|vpiName:rd_data
|vpiNetType:36
|vpiRange:
\_range: , line:48
|vpiLeftRange:
\_constant: , line:48
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:48
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (rd_sub_id)
|vpiName:rd_sub_id
|vpiDirection:1
|vpiExpr:
\_logic_net: (rd_sub_id), line:49
|vpiName:rd_sub_id
|vpiNetType:36
|vpiRange:
\_range: , line:49
|vpiLeftRange:
\_constant: , line:49
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:49
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (rd_data_valid)
|vpiName:rd_data_valid
|vpiDirection:1
|vpiExpr:
\_logic_net: (rd_data_valid), line:50
|vpiName:rd_data_valid
|vpiNetType:36
|vpiIODecl:
\_io_decl: (rd_data_ack)
|vpiName:rd_data_ack
|vpiDirection:2
|vpiExpr:
\_logic_net: (rd_data_ack), line:51
|vpiName:rd_data_ack
|vpiNetType:36
|vpiInterface:
\_interface: work@l2_requester_interface (l2), file:third_party/cores/taiga/core/taiga.sv, line:155
|vpiDefName:work@l2_requester_interface
|vpiName:l2
|vpiModport:
\_modport: (master)
|vpiModport:
\_modport: (slave)
|vpiName:slave
|vpiIODecl:
\_io_decl: (addr)
|vpiName:addr
|vpiDirection:1
|vpiExpr:
\_logic_net: (addr), line:27
|vpiIODecl:
\_io_decl: (be)
|vpiName:be
|vpiDirection:1
|vpiExpr:
\_logic_net: (be), line:28
|vpiIODecl:
\_io_decl: (rnw)
|vpiName:rnw
|vpiDirection:1
|vpiExpr:
\_logic_net: (rnw), line:29
|vpiIODecl:
\_io_decl: (is_amo)
|vpiName:is_amo
|vpiDirection:1
|vpiExpr:
\_logic_net: (is_amo), line:30
|vpiIODecl:
\_io_decl: (amo_type_or_burst_size)
|vpiName:amo_type_or_burst_size
|vpiDirection:1
|vpiExpr:
\_logic_net: (amo_type_or_burst_size), line:31
|vpiIODecl:
\_io_decl: (sub_id)
|vpiName:sub_id
|vpiDirection:1
|vpiExpr:
\_logic_net: (sub_id), line:32
|vpiIODecl:
\_io_decl: (request_push)
|vpiName:request_push
|vpiDirection:1
|vpiExpr:
\_logic_net: (request_push), line:34
|vpiIODecl:
\_io_decl: (request_full)
|vpiName:request_full
|vpiDirection:2
|vpiExpr:
\_logic_net: (request_full), line:35
|vpiIODecl:
\_io_decl: (inv_addr)
|vpiName:inv_addr
|vpiDirection:2
|vpiExpr:
\_logic_net: (inv_addr), line:37
|vpiIODecl:
\_io_decl: (inv_valid)
|vpiName:inv_valid
|vpiDirection:2
|vpiExpr:
\_logic_net: (inv_valid), line:38
|vpiIODecl:
\_io_decl: (inv_ack)
|vpiName:inv_ack
|vpiDirection:1
|vpiExpr:
\_logic_net: (inv_ack), line:39
|vpiIODecl:
\_io_decl: (con_result)
|vpiName:con_result
|vpiDirection:2
|vpiExpr:
\_logic_net: (con_result), line:41
|vpiIODecl:
\_io_decl: (con_valid)
|vpiName:con_valid
|vpiDirection:2
|vpiExpr:
\_logic_net: (con_valid), line:42
|vpiIODecl:
\_io_decl: (wr_data)
|vpiName:wr_data
|vpiDirection:1
|vpiExpr:
\_logic_net: (wr_data), line:44
|vpiIODecl:
\_io_decl: (wr_data_push)
|vpiName:wr_data_push
|vpiDirection:1
|vpiExpr:
\_logic_net: (wr_data_push), line:45
|vpiIODecl:
\_io_decl: (data_full)
|vpiName:data_full
|vpiDirection:2
|vpiExpr:
\_logic_net: (data_full), line:46
|vpiIODecl:
\_io_decl: (rd_data)
|vpiName:rd_data
|vpiDirection:2
|vpiExpr:
\_logic_net: (rd_data), line:48
|vpiIODecl:
\_io_decl: (rd_sub_id)
|vpiName:rd_sub_id
|vpiDirection:2
|vpiExpr:
\_logic_net: (rd_sub_id), line:49
|vpiIODecl:
\_io_decl: (rd_data_valid)
|vpiName:rd_data_valid
|vpiDirection:2
|vpiExpr:
\_logic_net: (rd_data_valid), line:50
|vpiIODecl:
\_io_decl: (rd_data_ack)
|vpiName:rd_data_ack
|vpiDirection:1
|vpiExpr:
\_logic_net: (rd_data_ack), line:51
|vpiInterface:
\_interface: work@l2_requester_interface (l2), file:third_party/cores/taiga/core/taiga.sv, line:155
|vpiPort:
\_port: (sc_complete), line:34, parent:arb
|vpiName:sc_complete
|vpiDirection:2
|vpiHighConn:
\_ref_obj: (sc_complete), line:155
|vpiName:sc_complete
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (sc_complete), line:34, parent:arb
|vpiName:sc_complete
|vpiFullName:work@taiga_wrapper.cpu.genblk1.arb.sc_complete
|vpiPort:
\_port: (sc_success), line:35, parent:arb
|vpiName:sc_success
|vpiDirection:2
|vpiHighConn:
\_ref_obj: (sc_success), line:155
|vpiName:sc_success
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (sc_success), line:35, parent:arb
|vpiName:sc_success
|vpiFullName:work@taiga_wrapper.cpu.genblk1.arb.sc_success
|vpiPort:
\_port: (l1_request), line:37, parent:arb
|vpiName:l1_request
|vpiDirection:5
|vpiHighConn:
\_ref_obj: (l1_request), line:155
|vpiName:l1_request
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_modport: (slave)
|vpiName:slave
|vpiIODecl:
\_io_decl: (addr)
|vpiName:addr
|vpiDirection:1
|vpiExpr:
\_logic_net: (addr), line:27
|vpiIODecl:
\_io_decl: (data)
|vpiName:data
|vpiDirection:1
|vpiExpr:
\_logic_net: (data), line:124
|vpiName:data
|vpiNetType:36
|vpiRange:
\_range: , line:124
|vpiLeftRange:
\_constant: , line:124
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:124
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (rnw)
|vpiName:rnw
|vpiDirection:1
|vpiExpr:
\_logic_net: (rnw), line:29
|vpiIODecl:
\_io_decl: (be)
|vpiName:be
|vpiDirection:1
|vpiExpr:
\_logic_net: (be), line:28
|vpiIODecl:
\_io_decl: (size)
|vpiName:size
|vpiDirection:1
|vpiExpr:
\_logic_net: (size), line:127
|vpiName:size
|vpiNetType:36
|vpiRange:
\_range: , line:127
|vpiLeftRange:
\_constant: , line:127
|vpiConstType:7
|vpiDecompile:4
|vpiSize:32
|INT:4
|vpiRightRange:
\_constant: , line:127
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (is_amo)
|vpiName:is_amo
|vpiDirection:1
|vpiExpr:
\_logic_net: (is_amo), line:30
|vpiIODecl:
\_io_decl: (amo)
|vpiName:amo
|vpiDirection:1
|vpiExpr:
\_logic_net: (amo), line:129
|vpiName:amo
|vpiNetType:36
|vpiRange:
\_range: , line:129
|vpiLeftRange:
\_constant: , line:129
|vpiConstType:7
|vpiDecompile:4
|vpiSize:32
|INT:4
|vpiRightRange:
\_constant: , line:129
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (request)
|vpiName:request
|vpiDirection:1
|vpiExpr:
\_logic_net: (request), line:131
|vpiName:request
|vpiNetType:36
|vpiIODecl:
\_io_decl: (ack)
|vpiName:ack
|vpiDirection:2
|vpiExpr:
\_logic_net: (ack), line:132
|vpiName:ack
|vpiNetType:36
|vpiInterface:
\_interface: work@l1_arbiter_request_interface (l1_request), file:third_party/cores/taiga/core/taiga.sv, line:155
|vpiDefName:work@l1_arbiter_request_interface
|vpiName:l1_request
|vpiModport:
\_modport: (master)
|vpiName:master
|vpiIODecl:
\_io_decl: (addr)
|vpiName:addr
|vpiDirection:2
|vpiExpr:
\_logic_net: (addr), line:27
|vpiIODecl:
\_io_decl: (data)
|vpiName:data
|vpiDirection:2
|vpiExpr:
\_logic_net: (data), line:124
|vpiIODecl:
\_io_decl: (rnw)
|vpiName:rnw
|vpiDirection:2
|vpiExpr:
\_logic_net: (rnw), line:29
|vpiIODecl:
\_io_decl: (be)
|vpiName:be
|vpiDirection:2
|vpiExpr:
\_logic_net: (be), line:28
|vpiIODecl:
\_io_decl: (size)
|vpiName:size
|vpiDirection:2
|vpiExpr:
\_logic_net: (size), line:127
|vpiIODecl:
\_io_decl: (is_amo)
|vpiName:is_amo
|vpiDirection:2
|vpiExpr:
\_logic_net: (is_amo), line:30
|vpiIODecl:
\_io_decl: (amo)
|vpiName:amo
|vpiDirection:2
|vpiExpr:
\_logic_net: (amo), line:129
|vpiIODecl:
\_io_decl: (request)
|vpiName:request
|vpiDirection:2
|vpiExpr:
\_logic_net: (request), line:131
|vpiIODecl:
\_io_decl: (ack)
|vpiName:ack
|vpiDirection:1
|vpiExpr:
\_logic_net: (ack), line:132
|vpiInterface:
\_interface: work@l1_arbiter_request_interface (l1_request), file:third_party/cores/taiga/core/taiga.sv, line:155
|vpiModport:
\_modport: (slave)
|vpiPort:
\_port: (l1_response), line:38, parent:arb
|vpiName:l1_response
|vpiDirection:5
|vpiHighConn:
\_ref_obj: (l1_response), line:155
|vpiName:l1_response
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_modport: (slave)
|vpiName:slave
|vpiIODecl:
\_io_decl: (inv_addr)
|vpiName:inv_addr
|vpiDirection:2
|vpiExpr:
\_logic_net: (inv_addr), line:37
|vpiIODecl:
\_io_decl: (inv_valid)
|vpiName:inv_valid
|vpiDirection:2
|vpiExpr:
\_logic_net: (inv_valid), line:38
|vpiIODecl:
\_io_decl: (data)
|vpiName:data
|vpiDirection:2
|vpiExpr:
\_logic_net: (data), line:124
|vpiIODecl:
\_io_decl: (data_valid)
|vpiName:data_valid
|vpiDirection:2
|vpiExpr:
\_logic_net: (data_valid), line:153
|vpiName:data_valid
|vpiNetType:36
|vpiIODecl:
\_io_decl: (inv_ack)
|vpiName:inv_ack
|vpiDirection:1
|vpiExpr:
\_logic_net: (inv_ack), line:39
|vpiInterface:
\_interface: work@l1_arbiter_return_interface (l1_response), file:third_party/cores/taiga/core/taiga.sv, line:155
|vpiDefName:work@l1_arbiter_return_interface
|vpiName:l1_response
|vpiModport:
\_modport: (master)
|vpiName:master
|vpiIODecl:
\_io_decl: (inv_addr)
|vpiName:inv_addr
|vpiDirection:1
|vpiExpr:
\_logic_net: (inv_addr), line:37
|vpiIODecl:
\_io_decl: (inv_valid)
|vpiName:inv_valid
|vpiDirection:1
|vpiExpr:
\_logic_net: (inv_valid), line:38
|vpiIODecl:
\_io_decl: (data)
|vpiName:data
|vpiDirection:1
|vpiExpr:
\_logic_net: (data), line:124
|vpiIODecl:
\_io_decl: (data_valid)
|vpiName:data_valid
|vpiDirection:1
|vpiExpr:
\_logic_net: (data_valid), line:153
|vpiIODecl:
\_io_decl: (inv_ack)
|vpiName:inv_ack
|vpiDirection:2
|vpiExpr:
\_logic_net: (inv_ack), line:39
|vpiInterface:
\_interface: work@l1_arbiter_return_interface (l1_response), file:third_party/cores/taiga/core/taiga.sv, line:155
|vpiModport:
\_modport: (slave)
|vpiGenScopeArray:
\_gen_scope_array: (genblk1[0]), line:54, parent:arb
|vpiName:genblk1[0]
|vpiFullName:work@taiga_wrapper.cpu.genblk1.arb.genblk1[0]
|vpiGenScope:
\_gen_scope: , parent:genblk1[0]
|vpiFullName:work@taiga_wrapper.cpu.genblk1.arb.genblk1[0]
|vpiContAssign:
\_cont_assign: , line:55
|vpiRhs:
\_bit_select: (l1_request.request), line:55
|vpiName:l1_request.request
|vpiFullName:work@taiga_wrapper.cpu.genblk1.arb.genblk1[0].l1_request.request
|vpiIndex:
\_ref_obj: (i), line:55
|vpiName:i
|vpiLhs:
\_bit_select: (requests), line:55
|vpiName:requests
|vpiFullName:work@taiga_wrapper.cpu.genblk1.arb.genblk1[0].requests
|vpiIndex:
\_ref_obj: (i), line:55
|vpiName:i
|vpiContAssign:
\_cont_assign: , line:56
|vpiRhs:
\_bit_select: (acks), line:56
|vpiName:acks
|vpiFullName:work@taiga_wrapper.cpu.genblk1.arb.genblk1[0].acks
|vpiIndex:
\_ref_obj: (i), line:56
|vpiName:i
|vpiLhs:
\_ref_obj: (l1_request[i].ack), line:56
|vpiName:l1_request[i].ack
|vpiFullName:work@taiga_wrapper.cpu.genblk1.arb.genblk1[0].l1_request[i].ack
|vpiParameter:
\_parameter: (ALU_UNIT_WB_ID), line:190
|vpiName:ALU_UNIT_WB_ID
|INT:32
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (BRANCH_PREDICTOR_WAYS), line:159
|vpiName:BRANCH_PREDICTOR_WAYS
|INT:9
|vpiParameter:
\_parameter: (BRANCH_TABLE_ENTRIES), line:160
|vpiName:BRANCH_TABLE_ENTRIES
|INT:4
|vpiParameter:
\_parameter: (BRANCH_UNIT_ID), line:195
|vpiName:BRANCH_UNIT_ID
|INT:8
|vpiParameter:
\_parameter: (BUS_ADDR_H), line:107
|vpiName:BUS_ADDR_H
|INT:1
|vpiParameter:
\_parameter: (BUS_ADDR_L), line:106
|vpiName:BUS_ADDR_L
|INT:0
|vpiParameter:
\_parameter: (BUS_BIT_CHECK), line:108
|vpiName:BUS_BIT_CHECK
|INT:1
|vpiParameter:
\_parameter: (BUS_TYPE), line:89
|vpiName:BUS_TYPE
|INT:5
|vpiParameter:
\_parameter: (COUNTER_W), line:42
|vpiName:COUNTER_W
|INT:33
|vpiParameter:
\_parameter: (CPU_ID), line:38
|vpiName:CPU_ID
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_ADDR_WIDTH), line:113
|vpiName:C_M_AXI_ADDR_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_DATA_WIDTH), line:114
|vpiName:C_M_AXI_DATA_WIDTH
|INT:1
|vpiParameter:
\_parameter: (DCACHE_LINES), line:133
|vpiName:DCACHE_LINES
|INT:-2146435073
|vpiParameter:
\_parameter: (DCACHE_LINE_ADDR_W), line:135
|vpiName:DCACHE_LINE_ADDR_W
|INT:1073741824
|vpiParameter:
\_parameter: (DCACHE_LINE_W), line:136
|vpiName:DCACHE_LINE_W
|INT:1342177279
|vpiParameter:
\_parameter: (DCACHE_SUB_LINE_ADDR_W), line:137
|vpiName:DCACHE_SUB_LINE_ADDR_W
|INT:4
|vpiParameter:
\_parameter: (DCACHE_TAG_W), line:138
|vpiName:DCACHE_TAG_W
|INT:1610612736
|vpiParameter:
\_parameter: (DCACHE_WAYS), line:134
|vpiName:DCACHE_WAYS
|INT:4
|vpiParameter:
\_parameter: (DIV_ALGORITHM), line:67
|vpiName:DIV_ALGORITHM
|INT:0
|vpiParameter:
\_parameter: (DIV_UNIT_WB_ID), line:192
|vpiName:DIV_UNIT_WB_ID
|INT:2
|vpiParameter:
\_parameter: (DTLB_DEPTH), line:152
|vpiName:DTLB_DEPTH
|INT:512
|vpiParameter:
\_parameter: (DTLB_WAYS), line:151
|vpiName:DTLB_WAYS
|INT:32
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (ENABLE_M_MODE), line:34
|vpiName:ENABLE_M_MODE
|INT:1
|vpiParameter:
\_parameter: (ENABLE_S_MODE), line:36
|vpiName:ENABLE_S_MODE
|INT:0
|vpiParameter:
\_parameter: (ENABLE_TRACE_INTERFACE), line:172
|vpiName:ENABLE_TRACE_INTERFACE
|INT:2
|vpiParameter:
\_parameter: (FETCH_BUFFER_DEPTH), line:168
|vpiName:FETCH_BUFFER_DEPTH
|INT:512
|vpiParameter:
\_parameter: (FPGA_VENDOR), line:27
|vpiName:FPGA_VENDOR
|STRING:"xilinx"
|vpiParameter:
\_parameter: (GC_UNIT_ID), line:196
|vpiName:GC_UNIT_ID
|INT:4
|vpiParameter:
\_parameter: (ICACHE_LINES), line:121
|vpiName:ICACHE_LINES
|INT:2
|vpiParameter:
\_parameter: (ICACHE_LINE_ADDR_W), line:123
|vpiName:ICACHE_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_LINE_W), line:124
|vpiName:ICACHE_LINE_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_SUB_LINE_ADDR_W), line:125
|vpiName:ICACHE_SUB_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_TAG_W), line:126
|vpiName:ICACHE_TAG_W
|INT:-2147483648
|vpiParameter:
\_parameter: (ICACHE_WAYS), line:122
|vpiName:ICACHE_WAYS
|INT:1
|vpiParameter:
\_parameter: (ITLB_DEPTH), line:146
|vpiName:ITLB_DEPTH
|INT:32
|vpiParameter:
\_parameter: (ITLB_WAYS), line:145
|vpiName:ITLB_WAYS
|INT:4
|vpiParameter:
\_parameter: (L1_CONNECTIONS), line:177
|vpiName:L1_CONNECTIONS
|INT:9
|vpiParameter:
\_parameter: (L1_DCACHE_ID), line:178
|vpiName:L1_DCACHE_ID
|INT:4
|vpiParameter:
\_parameter: (L1_DMMU_ID), line:179
|vpiName:L1_DMMU_ID
|INT:2
|vpiParameter:
\_parameter: (L1_ICACHE_ID), line:180
|vpiName:L1_ICACHE_ID
|INT:19
|vpiParameter:
\_parameter: (L1_IMMU_ID), line:181
|vpiName:L1_IMMU_ID
|INT:0
|vpiParameter:
\_parameter: (L2_DATA_ATTRIBUTES_FIFO_DEPTH), line:41
|vpiName:L2_DATA_ATTRIBUTES_FIFO_DEPTH
|INT:16
|vpiParameter:
\_parameter: (L2_ID_W), line:46
|vpiName:L2_ID_W
|INT:3
|vpiParameter:
\_parameter: (L2_INPUT_FIFO_DEPTHS), line:34
|vpiName:L2_INPUT_FIFO_DEPTHS
|INT:4
|vpiParameter:
\_parameter: (L2_INVALIDATION_FIFO_DEPTHS), line:35
|vpiName:L2_INVALIDATION_FIFO_DEPTHS
|INT:4
|vpiParameter:
\_parameter: (L2_MEM_ADDR_FIFO_DEPTH), line:39
|vpiName:L2_MEM_ADDR_FIFO_DEPTH
|INT:8
|vpiParameter:
\_parameter: (L2_NUM_PORTS), line:26
|vpiName:L2_NUM_PORTS
|INT:2
|vpiParameter:
\_parameter: (L2_READ_RETURN_FIFO_DEPTHS), line:36
|vpiName:L2_READ_RETURN_FIFO_DEPTHS
|INT:1
|vpiParameter:
\_parameter: (L2_SUB_ID_W), line:27
|vpiName:L2_SUB_ID_W
|INT:2
|vpiParameter:
\_parameter: (LS_UNIT_WB_ID), line:191
|vpiName:LS_UNIT_WB_ID
|INT:1
|vpiParameter:
\_parameter: (MAX_INFLIGHT_COUNT), line:167
|vpiName:MAX_INFLIGHT_COUNT
|INT:19
|vpiParameter:
\_parameter: (MEMORY_ADDR_H), line:103
|vpiName:MEMORY_ADDR_H
|INT:12
|vpiParameter:
\_parameter: (MEMORY_ADDR_L), line:102
|vpiName:MEMORY_ADDR_L
|INT:11
|vpiParameter:
\_parameter: (MEMORY_BIT_CHECK), line:104
|vpiName:MEMORY_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (MUL_UNIT_WB_ID), line:193
|vpiName:MUL_UNIT_WB_ID
|INT:512
|vpiParameter:
\_parameter: (NUM_UNITS), line:188
|vpiName:NUM_UNITS
|INT:2
|vpiParameter:
\_parameter: (NUM_WB_UNITS), line:186
|vpiName:NUM_WB_UNITS
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (RAS_DEPTH), line:161
|vpiName:RAS_DEPTH
|INT:2
|vpiParameter:
\_parameter: (RESET_VEC), line:39
|vpiName:RESET_VEC
|INT:-2147483648
|vpiParameter:
\_parameter: (SCRATCH_ADDR_H), line:99
|vpiName:SCRATCH_ADDR_H
|INT:9
|vpiParameter:
\_parameter: (SCRATCH_ADDR_L), line:98
|vpiName:SCRATCH_ADDR_L
|INT:8
|vpiParameter:
\_parameter: (SCRATCH_BIT_CHECK), line:100
|vpiName:SCRATCH_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (USE_AMO), line:70
|vpiName:USE_AMO
|INT:1
|vpiParameter:
\_parameter: (USE_BRANCH_PREDICTOR), line:158
|vpiName:USE_BRANCH_PREDICTOR
|INT:2
|vpiParameter:
\_parameter: (USE_BUS), line:88
|vpiName:USE_BUS
|INT:4
|vpiParameter:
\_parameter: (USE_DCACHE), line:92
|vpiName:USE_DCACHE
|INT:6
|vpiParameter:
\_parameter: (USE_DIV), line:49
|vpiName:USE_DIV
|INT:1
|vpiParameter:
\_parameter: (USE_DTAG_INVALIDATIONS), line:140
|vpiName:USE_DTAG_INVALIDATIONS
|INT:1879048191
|vpiParameter:
\_parameter: (USE_D_SCRATCH_MEM), line:79
|vpiName:USE_D_SCRATCH_MEM
|INT:3
|vpiParameter:
\_parameter: (USE_ICACHE), line:93
|vpiName:USE_ICACHE
|INT:7
|vpiParameter:
\_parameter: (USE_I_SCRATCH_MEM), line:78
|vpiName:USE_I_SCRATCH_MEM
|INT:2
|vpiParameter:
\_parameter: (USE_MUL), line:48
|vpiName:USE_MUL
|INT:1
|vpiParameter:
\_parameter: (WB_UNITS_WIDTH), line:187
|vpiName:WB_UNITS_WIDTH
|INT:32
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiParameter:
\_parameter: (i), line:54
|vpiName:i
|INT:0
|vpiGenScopeArray:
\_gen_scope_array: (genblk1[1]), line:54, parent:arb
|vpiName:genblk1[1]
|vpiFullName:work@taiga_wrapper.cpu.genblk1.arb.genblk1[1]
|vpiGenScope:
\_gen_scope: , parent:genblk1[1]
|vpiFullName:work@taiga_wrapper.cpu.genblk1.arb.genblk1[1]
|vpiContAssign:
\_cont_assign: , line:55
|vpiRhs:
\_bit_select: (l1_request.request), line:55
|vpiName:l1_request.request
|vpiFullName:work@taiga_wrapper.cpu.genblk1.arb.genblk1[1].l1_request.request
|vpiIndex:
\_ref_obj: (i), line:55
|vpiName:i
|vpiLhs:
\_bit_select: (requests), line:55
|vpiName:requests
|vpiFullName:work@taiga_wrapper.cpu.genblk1.arb.genblk1[1].requests
|vpiIndex:
\_ref_obj: (i), line:55
|vpiName:i
|vpiContAssign:
\_cont_assign: , line:56
|vpiRhs:
\_bit_select: (acks), line:56
|vpiName:acks
|vpiFullName:work@taiga_wrapper.cpu.genblk1.arb.genblk1[1].acks
|vpiIndex:
\_ref_obj: (i), line:56
|vpiName:i
|vpiLhs:
\_ref_obj: (l1_request[i].ack), line:56
|vpiName:l1_request[i].ack
|vpiFullName:work@taiga_wrapper.cpu.genblk1.arb.genblk1[1].l1_request[i].ack
|vpiParameter:
\_parameter: (ALU_UNIT_WB_ID), line:190
|vpiName:ALU_UNIT_WB_ID
|INT:32
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (BRANCH_PREDICTOR_WAYS), line:159
|vpiName:BRANCH_PREDICTOR_WAYS
|INT:9
|vpiParameter:
\_parameter: (BRANCH_TABLE_ENTRIES), line:160
|vpiName:BRANCH_TABLE_ENTRIES
|INT:4
|vpiParameter:
\_parameter: (BRANCH_UNIT_ID), line:195
|vpiName:BRANCH_UNIT_ID
|INT:8
|vpiParameter:
\_parameter: (BUS_ADDR_H), line:107
|vpiName:BUS_ADDR_H
|INT:1
|vpiParameter:
\_parameter: (BUS_ADDR_L), line:106
|vpiName:BUS_ADDR_L
|INT:0
|vpiParameter:
\_parameter: (BUS_BIT_CHECK), line:108
|vpiName:BUS_BIT_CHECK
|INT:1
|vpiParameter:
\_parameter: (BUS_TYPE), line:89
|vpiName:BUS_TYPE
|INT:5
|vpiParameter:
\_parameter: (COUNTER_W), line:42
|vpiName:COUNTER_W
|INT:33
|vpiParameter:
\_parameter: (CPU_ID), line:38
|vpiName:CPU_ID
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_ADDR_WIDTH), line:113
|vpiName:C_M_AXI_ADDR_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_DATA_WIDTH), line:114
|vpiName:C_M_AXI_DATA_WIDTH
|INT:1
|vpiParameter:
\_parameter: (DCACHE_LINES), line:133
|vpiName:DCACHE_LINES
|INT:-2146435073
|vpiParameter:
\_parameter: (DCACHE_LINE_ADDR_W), line:135
|vpiName:DCACHE_LINE_ADDR_W
|INT:1073741824
|vpiParameter:
\_parameter: (DCACHE_LINE_W), line:136
|vpiName:DCACHE_LINE_W
|INT:1342177279
|vpiParameter:
\_parameter: (DCACHE_SUB_LINE_ADDR_W), line:137
|vpiName:DCACHE_SUB_LINE_ADDR_W
|INT:4
|vpiParameter:
\_parameter: (DCACHE_TAG_W), line:138
|vpiName:DCACHE_TAG_W
|INT:1610612736
|vpiParameter:
\_parameter: (DCACHE_WAYS), line:134
|vpiName:DCACHE_WAYS
|INT:4
|vpiParameter:
\_parameter: (DIV_ALGORITHM), line:67
|vpiName:DIV_ALGORITHM
|INT:0
|vpiParameter:
\_parameter: (DIV_UNIT_WB_ID), line:192
|vpiName:DIV_UNIT_WB_ID
|INT:2
|vpiParameter:
\_parameter: (DTLB_DEPTH), line:152
|vpiName:DTLB_DEPTH
|INT:512
|vpiParameter:
\_parameter: (DTLB_WAYS), line:151
|vpiName:DTLB_WAYS
|INT:32
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (ENABLE_M_MODE), line:34
|vpiName:ENABLE_M_MODE
|INT:1
|vpiParameter:
\_parameter: (ENABLE_S_MODE), line:36
|vpiName:ENABLE_S_MODE
|INT:0
|vpiParameter:
\_parameter: (ENABLE_TRACE_INTERFACE), line:172
|vpiName:ENABLE_TRACE_INTERFACE
|INT:2
|vpiParameter:
\_parameter: (FETCH_BUFFER_DEPTH), line:168
|vpiName:FETCH_BUFFER_DEPTH
|INT:512
|vpiParameter:
\_parameter: (FPGA_VENDOR), line:27
|vpiName:FPGA_VENDOR
|STRING:"xilinx"
|vpiParameter:
\_parameter: (GC_UNIT_ID), line:196
|vpiName:GC_UNIT_ID
|INT:4
|vpiParameter:
\_parameter: (ICACHE_LINES), line:121
|vpiName:ICACHE_LINES
|INT:2
|vpiParameter:
\_parameter: (ICACHE_LINE_ADDR_W), line:123
|vpiName:ICACHE_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_LINE_W), line:124
|vpiName:ICACHE_LINE_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_SUB_LINE_ADDR_W), line:125
|vpiName:ICACHE_SUB_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_TAG_W), line:126
|vpiName:ICACHE_TAG_W
|INT:-2147483648
|vpiParameter:
\_parameter: (ICACHE_WAYS), line:122
|vpiName:ICACHE_WAYS
|INT:1
|vpiParameter:
\_parameter: (ITLB_DEPTH), line:146
|vpiName:ITLB_DEPTH
|INT:32
|vpiParameter:
\_parameter: (ITLB_WAYS), line:145
|vpiName:ITLB_WAYS
|INT:4
|vpiParameter:
\_parameter: (L1_CONNECTIONS), line:177
|vpiName:L1_CONNECTIONS
|INT:9
|vpiParameter:
\_parameter: (L1_DCACHE_ID), line:178
|vpiName:L1_DCACHE_ID
|INT:4
|vpiParameter:
\_parameter: (L1_DMMU_ID), line:179
|vpiName:L1_DMMU_ID
|INT:2
|vpiParameter:
\_parameter: (L1_ICACHE_ID), line:180
|vpiName:L1_ICACHE_ID
|INT:19
|vpiParameter:
\_parameter: (L1_IMMU_ID), line:181
|vpiName:L1_IMMU_ID
|INT:0
|vpiParameter:
\_parameter: (L2_DATA_ATTRIBUTES_FIFO_DEPTH), line:41
|vpiName:L2_DATA_ATTRIBUTES_FIFO_DEPTH
|INT:16
|vpiParameter:
\_parameter: (L2_ID_W), line:46
|vpiName:L2_ID_W
|INT:3
|vpiParameter:
\_parameter: (L2_INPUT_FIFO_DEPTHS), line:34
|vpiName:L2_INPUT_FIFO_DEPTHS
|INT:4
|vpiParameter:
\_parameter: (L2_INVALIDATION_FIFO_DEPTHS), line:35
|vpiName:L2_INVALIDATION_FIFO_DEPTHS
|INT:4
|vpiParameter:
\_parameter: (L2_MEM_ADDR_FIFO_DEPTH), line:39
|vpiName:L2_MEM_ADDR_FIFO_DEPTH
|INT:8
|vpiParameter:
\_parameter: (L2_NUM_PORTS), line:26
|vpiName:L2_NUM_PORTS
|INT:2
|vpiParameter:
\_parameter: (L2_READ_RETURN_FIFO_DEPTHS), line:36
|vpiName:L2_READ_RETURN_FIFO_DEPTHS
|INT:1
|vpiParameter:
\_parameter: (L2_SUB_ID_W), line:27
|vpiName:L2_SUB_ID_W
|INT:2
|vpiParameter:
\_parameter: (LS_UNIT_WB_ID), line:191
|vpiName:LS_UNIT_WB_ID
|INT:1
|vpiParameter:
\_parameter: (MAX_INFLIGHT_COUNT), line:167
|vpiName:MAX_INFLIGHT_COUNT
|INT:19
|vpiParameter:
\_parameter: (MEMORY_ADDR_H), line:103
|vpiName:MEMORY_ADDR_H
|INT:12
|vpiParameter:
\_parameter: (MEMORY_ADDR_L), line:102
|vpiName:MEMORY_ADDR_L
|INT:11
|vpiParameter:
\_parameter: (MEMORY_BIT_CHECK), line:104
|vpiName:MEMORY_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (MUL_UNIT_WB_ID), line:193
|vpiName:MUL_UNIT_WB_ID
|INT:512
|vpiParameter:
\_parameter: (NUM_UNITS), line:188
|vpiName:NUM_UNITS
|INT:2
|vpiParameter:
\_parameter: (NUM_WB_UNITS), line:186
|vpiName:NUM_WB_UNITS
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (RAS_DEPTH), line:161
|vpiName:RAS_DEPTH
|INT:2
|vpiParameter:
\_parameter: (RESET_VEC), line:39
|vpiName:RESET_VEC
|INT:-2147483648
|vpiParameter:
\_parameter: (SCRATCH_ADDR_H), line:99
|vpiName:SCRATCH_ADDR_H
|INT:9
|vpiParameter:
\_parameter: (SCRATCH_ADDR_L), line:98
|vpiName:SCRATCH_ADDR_L
|INT:8
|vpiParameter:
\_parameter: (SCRATCH_BIT_CHECK), line:100
|vpiName:SCRATCH_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (USE_AMO), line:70
|vpiName:USE_AMO
|INT:1
|vpiParameter:
\_parameter: (USE_BRANCH_PREDICTOR), line:158
|vpiName:USE_BRANCH_PREDICTOR
|INT:2
|vpiParameter:
\_parameter: (USE_BUS), line:88
|vpiName:USE_BUS
|INT:4
|vpiParameter:
\_parameter: (USE_DCACHE), line:92
|vpiName:USE_DCACHE
|INT:6
|vpiParameter:
\_parameter: (USE_DIV), line:49
|vpiName:USE_DIV
|INT:1
|vpiParameter:
\_parameter: (USE_DTAG_INVALIDATIONS), line:140
|vpiName:USE_DTAG_INVALIDATIONS
|INT:1879048191
|vpiParameter:
\_parameter: (USE_D_SCRATCH_MEM), line:79
|vpiName:USE_D_SCRATCH_MEM
|INT:3
|vpiParameter:
\_parameter: (USE_ICACHE), line:93
|vpiName:USE_ICACHE
|INT:7
|vpiParameter:
\_parameter: (USE_I_SCRATCH_MEM), line:78
|vpiName:USE_I_SCRATCH_MEM
|INT:2
|vpiParameter:
\_parameter: (USE_MUL), line:48
|vpiName:USE_MUL
|INT:1
|vpiParameter:
\_parameter: (WB_UNITS_WIDTH), line:187
|vpiName:WB_UNITS_WIDTH
|INT:32
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiParameter:
\_parameter: (i), line:54
|vpiName:i
|INT:1
|vpiGenScopeArray:
\_gen_scope_array: (genblk1[2]), line:54, parent:arb
|vpiName:genblk1[2]
|vpiFullName:work@taiga_wrapper.cpu.genblk1.arb.genblk1[2]
|vpiGenScope:
\_gen_scope: , parent:genblk1[2]
|vpiFullName:work@taiga_wrapper.cpu.genblk1.arb.genblk1[2]
|vpiContAssign:
\_cont_assign: , line:55
|vpiRhs:
\_bit_select: (l1_request.request), line:55
|vpiName:l1_request.request
|vpiFullName:work@taiga_wrapper.cpu.genblk1.arb.genblk1[2].l1_request.request
|vpiIndex:
\_ref_obj: (i), line:55
|vpiName:i
|vpiLhs:
\_bit_select: (requests), line:55
|vpiName:requests
|vpiFullName:work@taiga_wrapper.cpu.genblk1.arb.genblk1[2].requests
|vpiIndex:
\_ref_obj: (i), line:55
|vpiName:i
|vpiContAssign:
\_cont_assign: , line:56
|vpiRhs:
\_bit_select: (acks), line:56
|vpiName:acks
|vpiFullName:work@taiga_wrapper.cpu.genblk1.arb.genblk1[2].acks
|vpiIndex:
\_ref_obj: (i), line:56
|vpiName:i
|vpiLhs:
\_ref_obj: (l1_request[i].ack), line:56
|vpiName:l1_request[i].ack
|vpiFullName:work@taiga_wrapper.cpu.genblk1.arb.genblk1[2].l1_request[i].ack
|vpiParameter:
\_parameter: (ALU_UNIT_WB_ID), line:190
|vpiName:ALU_UNIT_WB_ID
|INT:32
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (BRANCH_PREDICTOR_WAYS), line:159
|vpiName:BRANCH_PREDICTOR_WAYS
|INT:9
|vpiParameter:
\_parameter: (BRANCH_TABLE_ENTRIES), line:160
|vpiName:BRANCH_TABLE_ENTRIES
|INT:4
|vpiParameter:
\_parameter: (BRANCH_UNIT_ID), line:195
|vpiName:BRANCH_UNIT_ID
|INT:8
|vpiParameter:
\_parameter: (BUS_ADDR_H), line:107
|vpiName:BUS_ADDR_H
|INT:1
|vpiParameter:
\_parameter: (BUS_ADDR_L), line:106
|vpiName:BUS_ADDR_L
|INT:0
|vpiParameter:
\_parameter: (BUS_BIT_CHECK), line:108
|vpiName:BUS_BIT_CHECK
|INT:1
|vpiParameter:
\_parameter: (BUS_TYPE), line:89
|vpiName:BUS_TYPE
|INT:5
|vpiParameter:
\_parameter: (COUNTER_W), line:42
|vpiName:COUNTER_W
|INT:33
|vpiParameter:
\_parameter: (CPU_ID), line:38
|vpiName:CPU_ID
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_ADDR_WIDTH), line:113
|vpiName:C_M_AXI_ADDR_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_DATA_WIDTH), line:114
|vpiName:C_M_AXI_DATA_WIDTH
|INT:1
|vpiParameter:
\_parameter: (DCACHE_LINES), line:133
|vpiName:DCACHE_LINES
|INT:-2146435073
|vpiParameter:
\_parameter: (DCACHE_LINE_ADDR_W), line:135
|vpiName:DCACHE_LINE_ADDR_W
|INT:1073741824
|vpiParameter:
\_parameter: (DCACHE_LINE_W), line:136
|vpiName:DCACHE_LINE_W
|INT:1342177279
|vpiParameter:
\_parameter: (DCACHE_SUB_LINE_ADDR_W), line:137
|vpiName:DCACHE_SUB_LINE_ADDR_W
|INT:4
|vpiParameter:
\_parameter: (DCACHE_TAG_W), line:138
|vpiName:DCACHE_TAG_W
|INT:1610612736
|vpiParameter:
\_parameter: (DCACHE_WAYS), line:134
|vpiName:DCACHE_WAYS
|INT:4
|vpiParameter:
\_parameter: (DIV_ALGORITHM), line:67
|vpiName:DIV_ALGORITHM
|INT:0
|vpiParameter:
\_parameter: (DIV_UNIT_WB_ID), line:192
|vpiName:DIV_UNIT_WB_ID
|INT:2
|vpiParameter:
\_parameter: (DTLB_DEPTH), line:152
|vpiName:DTLB_DEPTH
|INT:512
|vpiParameter:
\_parameter: (DTLB_WAYS), line:151
|vpiName:DTLB_WAYS
|INT:32
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (ENABLE_M_MODE), line:34
|vpiName:ENABLE_M_MODE
|INT:1
|vpiParameter:
\_parameter: (ENABLE_S_MODE), line:36
|vpiName:ENABLE_S_MODE
|INT:0
|vpiParameter:
\_parameter: (ENABLE_TRACE_INTERFACE), line:172
|vpiName:ENABLE_TRACE_INTERFACE
|INT:2
|vpiParameter:
\_parameter: (FETCH_BUFFER_DEPTH), line:168
|vpiName:FETCH_BUFFER_DEPTH
|INT:512
|vpiParameter:
\_parameter: (FPGA_VENDOR), line:27
|vpiName:FPGA_VENDOR
|STRING:"xilinx"
|vpiParameter:
\_parameter: (GC_UNIT_ID), line:196
|vpiName:GC_UNIT_ID
|INT:4
|vpiParameter:
\_parameter: (ICACHE_LINES), line:121
|vpiName:ICACHE_LINES
|INT:2
|vpiParameter:
\_parameter: (ICACHE_LINE_ADDR_W), line:123
|vpiName:ICACHE_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_LINE_W), line:124
|vpiName:ICACHE_LINE_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_SUB_LINE_ADDR_W), line:125
|vpiName:ICACHE_SUB_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_TAG_W), line:126
|vpiName:ICACHE_TAG_W
|INT:-2147483648
|vpiParameter:
\_parameter: (ICACHE_WAYS), line:122
|vpiName:ICACHE_WAYS
|INT:1
|vpiParameter:
\_parameter: (ITLB_DEPTH), line:146
|vpiName:ITLB_DEPTH
|INT:32
|vpiParameter:
\_parameter: (ITLB_WAYS), line:145
|vpiName:ITLB_WAYS
|INT:4
|vpiParameter:
\_parameter: (L1_CONNECTIONS), line:177
|vpiName:L1_CONNECTIONS
|INT:9
|vpiParameter:
\_parameter: (L1_DCACHE_ID), line:178
|vpiName:L1_DCACHE_ID
|INT:4
|vpiParameter:
\_parameter: (L1_DMMU_ID), line:179
|vpiName:L1_DMMU_ID
|INT:2
|vpiParameter:
\_parameter: (L1_ICACHE_ID), line:180
|vpiName:L1_ICACHE_ID
|INT:19
|vpiParameter:
\_parameter: (L1_IMMU_ID), line:181
|vpiName:L1_IMMU_ID
|INT:0
|vpiParameter:
\_parameter: (L2_DATA_ATTRIBUTES_FIFO_DEPTH), line:41
|vpiName:L2_DATA_ATTRIBUTES_FIFO_DEPTH
|INT:16
|vpiParameter:
\_parameter: (L2_ID_W), line:46
|vpiName:L2_ID_W
|INT:3
|vpiParameter:
\_parameter: (L2_INPUT_FIFO_DEPTHS), line:34
|vpiName:L2_INPUT_FIFO_DEPTHS
|INT:4
|vpiParameter:
\_parameter: (L2_INVALIDATION_FIFO_DEPTHS), line:35
|vpiName:L2_INVALIDATION_FIFO_DEPTHS
|INT:4
|vpiParameter:
\_parameter: (L2_MEM_ADDR_FIFO_DEPTH), line:39
|vpiName:L2_MEM_ADDR_FIFO_DEPTH
|INT:8
|vpiParameter:
\_parameter: (L2_NUM_PORTS), line:26
|vpiName:L2_NUM_PORTS
|INT:2
|vpiParameter:
\_parameter: (L2_READ_RETURN_FIFO_DEPTHS), line:36
|vpiName:L2_READ_RETURN_FIFO_DEPTHS
|INT:1
|vpiParameter:
\_parameter: (L2_SUB_ID_W), line:27
|vpiName:L2_SUB_ID_W
|INT:2
|vpiParameter:
\_parameter: (LS_UNIT_WB_ID), line:191
|vpiName:LS_UNIT_WB_ID
|INT:1
|vpiParameter:
\_parameter: (MAX_INFLIGHT_COUNT), line:167
|vpiName:MAX_INFLIGHT_COUNT
|INT:19
|vpiParameter:
\_parameter: (MEMORY_ADDR_H), line:103
|vpiName:MEMORY_ADDR_H
|INT:12
|vpiParameter:
\_parameter: (MEMORY_ADDR_L), line:102
|vpiName:MEMORY_ADDR_L
|INT:11
|vpiParameter:
\_parameter: (MEMORY_BIT_CHECK), line:104
|vpiName:MEMORY_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (MUL_UNIT_WB_ID), line:193
|vpiName:MUL_UNIT_WB_ID
|INT:512
|vpiParameter:
\_parameter: (NUM_UNITS), line:188
|vpiName:NUM_UNITS
|INT:2
|vpiParameter:
\_parameter: (NUM_WB_UNITS), line:186
|vpiName:NUM_WB_UNITS
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (RAS_DEPTH), line:161
|vpiName:RAS_DEPTH
|INT:2
|vpiParameter:
\_parameter: (RESET_VEC), line:39
|vpiName:RESET_VEC
|INT:-2147483648
|vpiParameter:
\_parameter: (SCRATCH_ADDR_H), line:99
|vpiName:SCRATCH_ADDR_H
|INT:9
|vpiParameter:
\_parameter: (SCRATCH_ADDR_L), line:98
|vpiName:SCRATCH_ADDR_L
|INT:8
|vpiParameter:
\_parameter: (SCRATCH_BIT_CHECK), line:100
|vpiName:SCRATCH_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (USE_AMO), line:70
|vpiName:USE_AMO
|INT:1
|vpiParameter:
\_parameter: (USE_BRANCH_PREDICTOR), line:158
|vpiName:USE_BRANCH_PREDICTOR
|INT:2
|vpiParameter:
\_parameter: (USE_BUS), line:88
|vpiName:USE_BUS
|INT:4
|vpiParameter:
\_parameter: (USE_DCACHE), line:92
|vpiName:USE_DCACHE
|INT:6
|vpiParameter:
\_parameter: (USE_DIV), line:49
|vpiName:USE_DIV
|INT:1
|vpiParameter:
\_parameter: (USE_DTAG_INVALIDATIONS), line:140
|vpiName:USE_DTAG_INVALIDATIONS
|INT:1879048191
|vpiParameter:
\_parameter: (USE_D_SCRATCH_MEM), line:79
|vpiName:USE_D_SCRATCH_MEM
|INT:3
|vpiParameter:
\_parameter: (USE_ICACHE), line:93
|vpiName:USE_ICACHE
|INT:7
|vpiParameter:
\_parameter: (USE_I_SCRATCH_MEM), line:78
|vpiName:USE_I_SCRATCH_MEM
|INT:2
|vpiParameter:
\_parameter: (USE_MUL), line:48
|vpiName:USE_MUL
|INT:1
|vpiParameter:
\_parameter: (WB_UNITS_WIDTH), line:187
|vpiName:WB_UNITS_WIDTH
|INT:32
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiParameter:
\_parameter: (i), line:54
|vpiName:i
|INT:2
|vpiGenScopeArray:
\_gen_scope_array: (genblk1[3]), line:54, parent:arb
|vpiName:genblk1[3]
|vpiFullName:work@taiga_wrapper.cpu.genblk1.arb.genblk1[3]
|vpiGenScope:
\_gen_scope: , parent:genblk1[3]
|vpiFullName:work@taiga_wrapper.cpu.genblk1.arb.genblk1[3]
|vpiContAssign:
\_cont_assign: , line:55
|vpiRhs:
\_bit_select: (l1_request.request), line:55
|vpiName:l1_request.request
|vpiFullName:work@taiga_wrapper.cpu.genblk1.arb.genblk1[3].l1_request.request
|vpiIndex:
\_ref_obj: (i), line:55
|vpiName:i
|vpiLhs:
\_bit_select: (requests), line:55
|vpiName:requests
|vpiFullName:work@taiga_wrapper.cpu.genblk1.arb.genblk1[3].requests
|vpiIndex:
\_ref_obj: (i), line:55
|vpiName:i
|vpiContAssign:
\_cont_assign: , line:56
|vpiRhs:
\_bit_select: (acks), line:56
|vpiName:acks
|vpiFullName:work@taiga_wrapper.cpu.genblk1.arb.genblk1[3].acks
|vpiIndex:
\_ref_obj: (i), line:56
|vpiName:i
|vpiLhs:
\_ref_obj: (l1_request[i].ack), line:56
|vpiName:l1_request[i].ack
|vpiFullName:work@taiga_wrapper.cpu.genblk1.arb.genblk1[3].l1_request[i].ack
|vpiParameter:
\_parameter: (ALU_UNIT_WB_ID), line:190
|vpiName:ALU_UNIT_WB_ID
|INT:32
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (BRANCH_PREDICTOR_WAYS), line:159
|vpiName:BRANCH_PREDICTOR_WAYS
|INT:9
|vpiParameter:
\_parameter: (BRANCH_TABLE_ENTRIES), line:160
|vpiName:BRANCH_TABLE_ENTRIES
|INT:4
|vpiParameter:
\_parameter: (BRANCH_UNIT_ID), line:195
|vpiName:BRANCH_UNIT_ID
|INT:8
|vpiParameter:
\_parameter: (BUS_ADDR_H), line:107
|vpiName:BUS_ADDR_H
|INT:1
|vpiParameter:
\_parameter: (BUS_ADDR_L), line:106
|vpiName:BUS_ADDR_L
|INT:0
|vpiParameter:
\_parameter: (BUS_BIT_CHECK), line:108
|vpiName:BUS_BIT_CHECK
|INT:1
|vpiParameter:
\_parameter: (BUS_TYPE), line:89
|vpiName:BUS_TYPE
|INT:5
|vpiParameter:
\_parameter: (COUNTER_W), line:42
|vpiName:COUNTER_W
|INT:33
|vpiParameter:
\_parameter: (CPU_ID), line:38
|vpiName:CPU_ID
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_ADDR_WIDTH), line:113
|vpiName:C_M_AXI_ADDR_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_DATA_WIDTH), line:114
|vpiName:C_M_AXI_DATA_WIDTH
|INT:1
|vpiParameter:
\_parameter: (DCACHE_LINES), line:133
|vpiName:DCACHE_LINES
|INT:-2146435073
|vpiParameter:
\_parameter: (DCACHE_LINE_ADDR_W), line:135
|vpiName:DCACHE_LINE_ADDR_W
|INT:1073741824
|vpiParameter:
\_parameter: (DCACHE_LINE_W), line:136
|vpiName:DCACHE_LINE_W
|INT:1342177279
|vpiParameter:
\_parameter: (DCACHE_SUB_LINE_ADDR_W), line:137
|vpiName:DCACHE_SUB_LINE_ADDR_W
|INT:4
|vpiParameter:
\_parameter: (DCACHE_TAG_W), line:138
|vpiName:DCACHE_TAG_W
|INT:1610612736
|vpiParameter:
\_parameter: (DCACHE_WAYS), line:134
|vpiName:DCACHE_WAYS
|INT:4
|vpiParameter:
\_parameter: (DIV_ALGORITHM), line:67
|vpiName:DIV_ALGORITHM
|INT:0
|vpiParameter:
\_parameter: (DIV_UNIT_WB_ID), line:192
|vpiName:DIV_UNIT_WB_ID
|INT:2
|vpiParameter:
\_parameter: (DTLB_DEPTH), line:152
|vpiName:DTLB_DEPTH
|INT:512
|vpiParameter:
\_parameter: (DTLB_WAYS), line:151
|vpiName:DTLB_WAYS
|INT:32
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (ENABLE_M_MODE), line:34
|vpiName:ENABLE_M_MODE
|INT:1
|vpiParameter:
\_parameter: (ENABLE_S_MODE), line:36
|vpiName:ENABLE_S_MODE
|INT:0
|vpiParameter:
\_parameter: (ENABLE_TRACE_INTERFACE), line:172
|vpiName:ENABLE_TRACE_INTERFACE
|INT:2
|vpiParameter:
\_parameter: (FETCH_BUFFER_DEPTH), line:168
|vpiName:FETCH_BUFFER_DEPTH
|INT:512
|vpiParameter:
\_parameter: (FPGA_VENDOR), line:27
|vpiName:FPGA_VENDOR
|STRING:"xilinx"
|vpiParameter:
\_parameter: (GC_UNIT_ID), line:196
|vpiName:GC_UNIT_ID
|INT:4
|vpiParameter:
\_parameter: (ICACHE_LINES), line:121
|vpiName:ICACHE_LINES
|INT:2
|vpiParameter:
\_parameter: (ICACHE_LINE_ADDR_W), line:123
|vpiName:ICACHE_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_LINE_W), line:124
|vpiName:ICACHE_LINE_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_SUB_LINE_ADDR_W), line:125
|vpiName:ICACHE_SUB_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_TAG_W), line:126
|vpiName:ICACHE_TAG_W
|INT:-2147483648
|vpiParameter:
\_parameter: (ICACHE_WAYS), line:122
|vpiName:ICACHE_WAYS
|INT:1
|vpiParameter:
\_parameter: (ITLB_DEPTH), line:146
|vpiName:ITLB_DEPTH
|INT:32
|vpiParameter:
\_parameter: (ITLB_WAYS), line:145
|vpiName:ITLB_WAYS
|INT:4
|vpiParameter:
\_parameter: (L1_CONNECTIONS), line:177
|vpiName:L1_CONNECTIONS
|INT:9
|vpiParameter:
\_parameter: (L1_DCACHE_ID), line:178
|vpiName:L1_DCACHE_ID
|INT:4
|vpiParameter:
\_parameter: (L1_DMMU_ID), line:179
|vpiName:L1_DMMU_ID
|INT:2
|vpiParameter:
\_parameter: (L1_ICACHE_ID), line:180
|vpiName:L1_ICACHE_ID
|INT:19
|vpiParameter:
\_parameter: (L1_IMMU_ID), line:181
|vpiName:L1_IMMU_ID
|INT:0
|vpiParameter:
\_parameter: (L2_DATA_ATTRIBUTES_FIFO_DEPTH), line:41
|vpiName:L2_DATA_ATTRIBUTES_FIFO_DEPTH
|INT:16
|vpiParameter:
\_parameter: (L2_ID_W), line:46
|vpiName:L2_ID_W
|INT:3
|vpiParameter:
\_parameter: (L2_INPUT_FIFO_DEPTHS), line:34
|vpiName:L2_INPUT_FIFO_DEPTHS
|INT:4
|vpiParameter:
\_parameter: (L2_INVALIDATION_FIFO_DEPTHS), line:35
|vpiName:L2_INVALIDATION_FIFO_DEPTHS
|INT:4
|vpiParameter:
\_parameter: (L2_MEM_ADDR_FIFO_DEPTH), line:39
|vpiName:L2_MEM_ADDR_FIFO_DEPTH
|INT:8
|vpiParameter:
\_parameter: (L2_NUM_PORTS), line:26
|vpiName:L2_NUM_PORTS
|INT:2
|vpiParameter:
\_parameter: (L2_READ_RETURN_FIFO_DEPTHS), line:36
|vpiName:L2_READ_RETURN_FIFO_DEPTHS
|INT:1
|vpiParameter:
\_parameter: (L2_SUB_ID_W), line:27
|vpiName:L2_SUB_ID_W
|INT:2
|vpiParameter:
\_parameter: (LS_UNIT_WB_ID), line:191
|vpiName:LS_UNIT_WB_ID
|INT:1
|vpiParameter:
\_parameter: (MAX_INFLIGHT_COUNT), line:167
|vpiName:MAX_INFLIGHT_COUNT
|INT:19
|vpiParameter:
\_parameter: (MEMORY_ADDR_H), line:103
|vpiName:MEMORY_ADDR_H
|INT:12
|vpiParameter:
\_parameter: (MEMORY_ADDR_L), line:102
|vpiName:MEMORY_ADDR_L
|INT:11
|vpiParameter:
\_parameter: (MEMORY_BIT_CHECK), line:104
|vpiName:MEMORY_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (MUL_UNIT_WB_ID), line:193
|vpiName:MUL_UNIT_WB_ID
|INT:512
|vpiParameter:
\_parameter: (NUM_UNITS), line:188
|vpiName:NUM_UNITS
|INT:2
|vpiParameter:
\_parameter: (NUM_WB_UNITS), line:186
|vpiName:NUM_WB_UNITS
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (RAS_DEPTH), line:161
|vpiName:RAS_DEPTH
|INT:2
|vpiParameter:
\_parameter: (RESET_VEC), line:39
|vpiName:RESET_VEC
|INT:-2147483648
|vpiParameter:
\_parameter: (SCRATCH_ADDR_H), line:99
|vpiName:SCRATCH_ADDR_H
|INT:9
|vpiParameter:
\_parameter: (SCRATCH_ADDR_L), line:98
|vpiName:SCRATCH_ADDR_L
|INT:8
|vpiParameter:
\_parameter: (SCRATCH_BIT_CHECK), line:100
|vpiName:SCRATCH_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (USE_AMO), line:70
|vpiName:USE_AMO
|INT:1
|vpiParameter:
\_parameter: (USE_BRANCH_PREDICTOR), line:158
|vpiName:USE_BRANCH_PREDICTOR
|INT:2
|vpiParameter:
\_parameter: (USE_BUS), line:88
|vpiName:USE_BUS
|INT:4
|vpiParameter:
\_parameter: (USE_DCACHE), line:92
|vpiName:USE_DCACHE
|INT:6
|vpiParameter:
\_parameter: (USE_DIV), line:49
|vpiName:USE_DIV
|INT:1
|vpiParameter:
\_parameter: (USE_DTAG_INVALIDATIONS), line:140
|vpiName:USE_DTAG_INVALIDATIONS
|INT:1879048191
|vpiParameter:
\_parameter: (USE_D_SCRATCH_MEM), line:79
|vpiName:USE_D_SCRATCH_MEM
|INT:3
|vpiParameter:
\_parameter: (USE_ICACHE), line:93
|vpiName:USE_ICACHE
|INT:7
|vpiParameter:
\_parameter: (USE_I_SCRATCH_MEM), line:78
|vpiName:USE_I_SCRATCH_MEM
|INT:2
|vpiParameter:
\_parameter: (USE_MUL), line:48
|vpiName:USE_MUL
|INT:1
|vpiParameter:
\_parameter: (WB_UNITS_WIDTH), line:187
|vpiName:WB_UNITS_WIDTH
|INT:32
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiParameter:
\_parameter: (i), line:54
|vpiName:i
|INT:3
|vpiGenScopeArray:
\_gen_scope_array: (genblk1[4]), line:54, parent:arb
|vpiName:genblk1[4]
|vpiFullName:work@taiga_wrapper.cpu.genblk1.arb.genblk1[4]
|vpiGenScope:
\_gen_scope: , parent:genblk1[4]
|vpiFullName:work@taiga_wrapper.cpu.genblk1.arb.genblk1[4]
|vpiContAssign:
\_cont_assign: , line:55
|vpiRhs:
\_bit_select: (l1_request.request), line:55
|vpiName:l1_request.request
|vpiFullName:work@taiga_wrapper.cpu.genblk1.arb.genblk1[4].l1_request.request
|vpiIndex:
\_ref_obj: (i), line:55
|vpiName:i
|vpiLhs:
\_bit_select: (requests), line:55
|vpiName:requests
|vpiFullName:work@taiga_wrapper.cpu.genblk1.arb.genblk1[4].requests
|vpiIndex:
\_ref_obj: (i), line:55
|vpiName:i
|vpiContAssign:
\_cont_assign: , line:56
|vpiRhs:
\_bit_select: (acks), line:56
|vpiName:acks
|vpiFullName:work@taiga_wrapper.cpu.genblk1.arb.genblk1[4].acks
|vpiIndex:
\_ref_obj: (i), line:56
|vpiName:i
|vpiLhs:
\_ref_obj: (l1_request[i].ack), line:56
|vpiName:l1_request[i].ack
|vpiFullName:work@taiga_wrapper.cpu.genblk1.arb.genblk1[4].l1_request[i].ack
|vpiParameter:
\_parameter: (ALU_UNIT_WB_ID), line:190
|vpiName:ALU_UNIT_WB_ID
|INT:32
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (BRANCH_PREDICTOR_WAYS), line:159
|vpiName:BRANCH_PREDICTOR_WAYS
|INT:9
|vpiParameter:
\_parameter: (BRANCH_TABLE_ENTRIES), line:160
|vpiName:BRANCH_TABLE_ENTRIES
|INT:4
|vpiParameter:
\_parameter: (BRANCH_UNIT_ID), line:195
|vpiName:BRANCH_UNIT_ID
|INT:8
|vpiParameter:
\_parameter: (BUS_ADDR_H), line:107
|vpiName:BUS_ADDR_H
|INT:1
|vpiParameter:
\_parameter: (BUS_ADDR_L), line:106
|vpiName:BUS_ADDR_L
|INT:0
|vpiParameter:
\_parameter: (BUS_BIT_CHECK), line:108
|vpiName:BUS_BIT_CHECK
|INT:1
|vpiParameter:
\_parameter: (BUS_TYPE), line:89
|vpiName:BUS_TYPE
|INT:5
|vpiParameter:
\_parameter: (COUNTER_W), line:42
|vpiName:COUNTER_W
|INT:33
|vpiParameter:
\_parameter: (CPU_ID), line:38
|vpiName:CPU_ID
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_ADDR_WIDTH), line:113
|vpiName:C_M_AXI_ADDR_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_DATA_WIDTH), line:114
|vpiName:C_M_AXI_DATA_WIDTH
|INT:1
|vpiParameter:
\_parameter: (DCACHE_LINES), line:133
|vpiName:DCACHE_LINES
|INT:-2146435073
|vpiParameter:
\_parameter: (DCACHE_LINE_ADDR_W), line:135
|vpiName:DCACHE_LINE_ADDR_W
|INT:1073741824
|vpiParameter:
\_parameter: (DCACHE_LINE_W), line:136
|vpiName:DCACHE_LINE_W
|INT:1342177279
|vpiParameter:
\_parameter: (DCACHE_SUB_LINE_ADDR_W), line:137
|vpiName:DCACHE_SUB_LINE_ADDR_W
|INT:4
|vpiParameter:
\_parameter: (DCACHE_TAG_W), line:138
|vpiName:DCACHE_TAG_W
|INT:1610612736
|vpiParameter:
\_parameter: (DCACHE_WAYS), line:134
|vpiName:DCACHE_WAYS
|INT:4
|vpiParameter:
\_parameter: (DIV_ALGORITHM), line:67
|vpiName:DIV_ALGORITHM
|INT:0
|vpiParameter:
\_parameter: (DIV_UNIT_WB_ID), line:192
|vpiName:DIV_UNIT_WB_ID
|INT:2
|vpiParameter:
\_parameter: (DTLB_DEPTH), line:152
|vpiName:DTLB_DEPTH
|INT:512
|vpiParameter:
\_parameter: (DTLB_WAYS), line:151
|vpiName:DTLB_WAYS
|INT:32
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (ENABLE_M_MODE), line:34
|vpiName:ENABLE_M_MODE
|INT:1
|vpiParameter:
\_parameter: (ENABLE_S_MODE), line:36
|vpiName:ENABLE_S_MODE
|INT:0
|vpiParameter:
\_parameter: (ENABLE_TRACE_INTERFACE), line:172
|vpiName:ENABLE_TRACE_INTERFACE
|INT:2
|vpiParameter:
\_parameter: (FETCH_BUFFER_DEPTH), line:168
|vpiName:FETCH_BUFFER_DEPTH
|INT:512
|vpiParameter:
\_parameter: (FPGA_VENDOR), line:27
|vpiName:FPGA_VENDOR
|STRING:"xilinx"
|vpiParameter:
\_parameter: (GC_UNIT_ID), line:196
|vpiName:GC_UNIT_ID
|INT:4
|vpiParameter:
\_parameter: (ICACHE_LINES), line:121
|vpiName:ICACHE_LINES
|INT:2
|vpiParameter:
\_parameter: (ICACHE_LINE_ADDR_W), line:123
|vpiName:ICACHE_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_LINE_W), line:124
|vpiName:ICACHE_LINE_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_SUB_LINE_ADDR_W), line:125
|vpiName:ICACHE_SUB_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_TAG_W), line:126
|vpiName:ICACHE_TAG_W
|INT:-2147483648
|vpiParameter:
\_parameter: (ICACHE_WAYS), line:122
|vpiName:ICACHE_WAYS
|INT:1
|vpiParameter:
\_parameter: (ITLB_DEPTH), line:146
|vpiName:ITLB_DEPTH
|INT:32
|vpiParameter:
\_parameter: (ITLB_WAYS), line:145
|vpiName:ITLB_WAYS
|INT:4
|vpiParameter:
\_parameter: (L1_CONNECTIONS), line:177
|vpiName:L1_CONNECTIONS
|INT:9
|vpiParameter:
\_parameter: (L1_DCACHE_ID), line:178
|vpiName:L1_DCACHE_ID
|INT:4
|vpiParameter:
\_parameter: (L1_DMMU_ID), line:179
|vpiName:L1_DMMU_ID
|INT:2
|vpiParameter:
\_parameter: (L1_ICACHE_ID), line:180
|vpiName:L1_ICACHE_ID
|INT:19
|vpiParameter:
\_parameter: (L1_IMMU_ID), line:181
|vpiName:L1_IMMU_ID
|INT:0
|vpiParameter:
\_parameter: (L2_DATA_ATTRIBUTES_FIFO_DEPTH), line:41
|vpiName:L2_DATA_ATTRIBUTES_FIFO_DEPTH
|INT:16
|vpiParameter:
\_parameter: (L2_ID_W), line:46
|vpiName:L2_ID_W
|INT:3
|vpiParameter:
\_parameter: (L2_INPUT_FIFO_DEPTHS), line:34
|vpiName:L2_INPUT_FIFO_DEPTHS
|INT:4
|vpiParameter:
\_parameter: (L2_INVALIDATION_FIFO_DEPTHS), line:35
|vpiName:L2_INVALIDATION_FIFO_DEPTHS
|INT:4
|vpiParameter:
\_parameter: (L2_MEM_ADDR_FIFO_DEPTH), line:39
|vpiName:L2_MEM_ADDR_FIFO_DEPTH
|INT:8
|vpiParameter:
\_parameter: (L2_NUM_PORTS), line:26
|vpiName:L2_NUM_PORTS
|INT:2
|vpiParameter:
\_parameter: (L2_READ_RETURN_FIFO_DEPTHS), line:36
|vpiName:L2_READ_RETURN_FIFO_DEPTHS
|INT:1
|vpiParameter:
\_parameter: (L2_SUB_ID_W), line:27
|vpiName:L2_SUB_ID_W
|INT:2
|vpiParameter:
\_parameter: (LS_UNIT_WB_ID), line:191
|vpiName:LS_UNIT_WB_ID
|INT:1
|vpiParameter:
\_parameter: (MAX_INFLIGHT_COUNT), line:167
|vpiName:MAX_INFLIGHT_COUNT
|INT:19
|vpiParameter:
\_parameter: (MEMORY_ADDR_H), line:103
|vpiName:MEMORY_ADDR_H
|INT:12
|vpiParameter:
\_parameter: (MEMORY_ADDR_L), line:102
|vpiName:MEMORY_ADDR_L
|INT:11
|vpiParameter:
\_parameter: (MEMORY_BIT_CHECK), line:104
|vpiName:MEMORY_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (MUL_UNIT_WB_ID), line:193
|vpiName:MUL_UNIT_WB_ID
|INT:512
|vpiParameter:
\_parameter: (NUM_UNITS), line:188
|vpiName:NUM_UNITS
|INT:2
|vpiParameter:
\_parameter: (NUM_WB_UNITS), line:186
|vpiName:NUM_WB_UNITS
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (RAS_DEPTH), line:161
|vpiName:RAS_DEPTH
|INT:2
|vpiParameter:
\_parameter: (RESET_VEC), line:39
|vpiName:RESET_VEC
|INT:-2147483648
|vpiParameter:
\_parameter: (SCRATCH_ADDR_H), line:99
|vpiName:SCRATCH_ADDR_H
|INT:9
|vpiParameter:
\_parameter: (SCRATCH_ADDR_L), line:98
|vpiName:SCRATCH_ADDR_L
|INT:8
|vpiParameter:
\_parameter: (SCRATCH_BIT_CHECK), line:100
|vpiName:SCRATCH_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (USE_AMO), line:70
|vpiName:USE_AMO
|INT:1
|vpiParameter:
\_parameter: (USE_BRANCH_PREDICTOR), line:158
|vpiName:USE_BRANCH_PREDICTOR
|INT:2
|vpiParameter:
\_parameter: (USE_BUS), line:88
|vpiName:USE_BUS
|INT:4
|vpiParameter:
\_parameter: (USE_DCACHE), line:92
|vpiName:USE_DCACHE
|INT:6
|vpiParameter:
\_parameter: (USE_DIV), line:49
|vpiName:USE_DIV
|INT:1
|vpiParameter:
\_parameter: (USE_DTAG_INVALIDATIONS), line:140
|vpiName:USE_DTAG_INVALIDATIONS
|INT:1879048191
|vpiParameter:
\_parameter: (USE_D_SCRATCH_MEM), line:79
|vpiName:USE_D_SCRATCH_MEM
|INT:3
|vpiParameter:
\_parameter: (USE_ICACHE), line:93
|vpiName:USE_ICACHE
|INT:7
|vpiParameter:
\_parameter: (USE_I_SCRATCH_MEM), line:78
|vpiName:USE_I_SCRATCH_MEM
|INT:2
|vpiParameter:
\_parameter: (USE_MUL), line:48
|vpiName:USE_MUL
|INT:1
|vpiParameter:
\_parameter: (WB_UNITS_WIDTH), line:187
|vpiName:WB_UNITS_WIDTH
|INT:32
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiParameter:
\_parameter: (i), line:54
|vpiName:i
|INT:4
|vpiGenScopeArray:
\_gen_scope_array: (genblk1[5]), line:54, parent:arb
|vpiName:genblk1[5]
|vpiFullName:work@taiga_wrapper.cpu.genblk1.arb.genblk1[5]
|vpiGenScope:
\_gen_scope: , parent:genblk1[5]
|vpiFullName:work@taiga_wrapper.cpu.genblk1.arb.genblk1[5]
|vpiContAssign:
\_cont_assign: , line:55
|vpiRhs:
\_bit_select: (l1_request.request), line:55
|vpiName:l1_request.request
|vpiFullName:work@taiga_wrapper.cpu.genblk1.arb.genblk1[5].l1_request.request
|vpiIndex:
\_ref_obj: (i), line:55
|vpiName:i
|vpiLhs:
\_bit_select: (requests), line:55
|vpiName:requests
|vpiFullName:work@taiga_wrapper.cpu.genblk1.arb.genblk1[5].requests
|vpiIndex:
\_ref_obj: (i), line:55
|vpiName:i
|vpiContAssign:
\_cont_assign: , line:56
|vpiRhs:
\_bit_select: (acks), line:56
|vpiName:acks
|vpiFullName:work@taiga_wrapper.cpu.genblk1.arb.genblk1[5].acks
|vpiIndex:
\_ref_obj: (i), line:56
|vpiName:i
|vpiLhs:
\_ref_obj: (l1_request[i].ack), line:56
|vpiName:l1_request[i].ack
|vpiFullName:work@taiga_wrapper.cpu.genblk1.arb.genblk1[5].l1_request[i].ack
|vpiParameter:
\_parameter: (ALU_UNIT_WB_ID), line:190
|vpiName:ALU_UNIT_WB_ID
|INT:32
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (BRANCH_PREDICTOR_WAYS), line:159
|vpiName:BRANCH_PREDICTOR_WAYS
|INT:9
|vpiParameter:
\_parameter: (BRANCH_TABLE_ENTRIES), line:160
|vpiName:BRANCH_TABLE_ENTRIES
|INT:4
|vpiParameter:
\_parameter: (BRANCH_UNIT_ID), line:195
|vpiName:BRANCH_UNIT_ID
|INT:8
|vpiParameter:
\_parameter: (BUS_ADDR_H), line:107
|vpiName:BUS_ADDR_H
|INT:1
|vpiParameter:
\_parameter: (BUS_ADDR_L), line:106
|vpiName:BUS_ADDR_L
|INT:0
|vpiParameter:
\_parameter: (BUS_BIT_CHECK), line:108
|vpiName:BUS_BIT_CHECK
|INT:1
|vpiParameter:
\_parameter: (BUS_TYPE), line:89
|vpiName:BUS_TYPE
|INT:5
|vpiParameter:
\_parameter: (COUNTER_W), line:42
|vpiName:COUNTER_W
|INT:33
|vpiParameter:
\_parameter: (CPU_ID), line:38
|vpiName:CPU_ID
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_ADDR_WIDTH), line:113
|vpiName:C_M_AXI_ADDR_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_DATA_WIDTH), line:114
|vpiName:C_M_AXI_DATA_WIDTH
|INT:1
|vpiParameter:
\_parameter: (DCACHE_LINES), line:133
|vpiName:DCACHE_LINES
|INT:-2146435073
|vpiParameter:
\_parameter: (DCACHE_LINE_ADDR_W), line:135
|vpiName:DCACHE_LINE_ADDR_W
|INT:1073741824
|vpiParameter:
\_parameter: (DCACHE_LINE_W), line:136
|vpiName:DCACHE_LINE_W
|INT:1342177279
|vpiParameter:
\_parameter: (DCACHE_SUB_LINE_ADDR_W), line:137
|vpiName:DCACHE_SUB_LINE_ADDR_W
|INT:4
|vpiParameter:
\_parameter: (DCACHE_TAG_W), line:138
|vpiName:DCACHE_TAG_W
|INT:1610612736
|vpiParameter:
\_parameter: (DCACHE_WAYS), line:134
|vpiName:DCACHE_WAYS
|INT:4
|vpiParameter:
\_parameter: (DIV_ALGORITHM), line:67
|vpiName:DIV_ALGORITHM
|INT:0
|vpiParameter:
\_parameter: (DIV_UNIT_WB_ID), line:192
|vpiName:DIV_UNIT_WB_ID
|INT:2
|vpiParameter:
\_parameter: (DTLB_DEPTH), line:152
|vpiName:DTLB_DEPTH
|INT:512
|vpiParameter:
\_parameter: (DTLB_WAYS), line:151
|vpiName:DTLB_WAYS
|INT:32
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (ENABLE_M_MODE), line:34
|vpiName:ENABLE_M_MODE
|INT:1
|vpiParameter:
\_parameter: (ENABLE_S_MODE), line:36
|vpiName:ENABLE_S_MODE
|INT:0
|vpiParameter:
\_parameter: (ENABLE_TRACE_INTERFACE), line:172
|vpiName:ENABLE_TRACE_INTERFACE
|INT:2
|vpiParameter:
\_parameter: (FETCH_BUFFER_DEPTH), line:168
|vpiName:FETCH_BUFFER_DEPTH
|INT:512
|vpiParameter:
\_parameter: (FPGA_VENDOR), line:27
|vpiName:FPGA_VENDOR
|STRING:"xilinx"
|vpiParameter:
\_parameter: (GC_UNIT_ID), line:196
|vpiName:GC_UNIT_ID
|INT:4
|vpiParameter:
\_parameter: (ICACHE_LINES), line:121
|vpiName:ICACHE_LINES
|INT:2
|vpiParameter:
\_parameter: (ICACHE_LINE_ADDR_W), line:123
|vpiName:ICACHE_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_LINE_W), line:124
|vpiName:ICACHE_LINE_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_SUB_LINE_ADDR_W), line:125
|vpiName:ICACHE_SUB_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_TAG_W), line:126
|vpiName:ICACHE_TAG_W
|INT:-2147483648
|vpiParameter:
\_parameter: (ICACHE_WAYS), line:122
|vpiName:ICACHE_WAYS
|INT:1
|vpiParameter:
\_parameter: (ITLB_DEPTH), line:146
|vpiName:ITLB_DEPTH
|INT:32
|vpiParameter:
\_parameter: (ITLB_WAYS), line:145
|vpiName:ITLB_WAYS
|INT:4
|vpiParameter:
\_parameter: (L1_CONNECTIONS), line:177
|vpiName:L1_CONNECTIONS
|INT:9
|vpiParameter:
\_parameter: (L1_DCACHE_ID), line:178
|vpiName:L1_DCACHE_ID
|INT:4
|vpiParameter:
\_parameter: (L1_DMMU_ID), line:179
|vpiName:L1_DMMU_ID
|INT:2
|vpiParameter:
\_parameter: (L1_ICACHE_ID), line:180
|vpiName:L1_ICACHE_ID
|INT:19
|vpiParameter:
\_parameter: (L1_IMMU_ID), line:181
|vpiName:L1_IMMU_ID
|INT:0
|vpiParameter:
\_parameter: (L2_DATA_ATTRIBUTES_FIFO_DEPTH), line:41
|vpiName:L2_DATA_ATTRIBUTES_FIFO_DEPTH
|INT:16
|vpiParameter:
\_parameter: (L2_ID_W), line:46
|vpiName:L2_ID_W
|INT:3
|vpiParameter:
\_parameter: (L2_INPUT_FIFO_DEPTHS), line:34
|vpiName:L2_INPUT_FIFO_DEPTHS
|INT:4
|vpiParameter:
\_parameter: (L2_INVALIDATION_FIFO_DEPTHS), line:35
|vpiName:L2_INVALIDATION_FIFO_DEPTHS
|INT:4
|vpiParameter:
\_parameter: (L2_MEM_ADDR_FIFO_DEPTH), line:39
|vpiName:L2_MEM_ADDR_FIFO_DEPTH
|INT:8
|vpiParameter:
\_parameter: (L2_NUM_PORTS), line:26
|vpiName:L2_NUM_PORTS
|INT:2
|vpiParameter:
\_parameter: (L2_READ_RETURN_FIFO_DEPTHS), line:36
|vpiName:L2_READ_RETURN_FIFO_DEPTHS
|INT:1
|vpiParameter:
\_parameter: (L2_SUB_ID_W), line:27
|vpiName:L2_SUB_ID_W
|INT:2
|vpiParameter:
\_parameter: (LS_UNIT_WB_ID), line:191
|vpiName:LS_UNIT_WB_ID
|INT:1
|vpiParameter:
\_parameter: (MAX_INFLIGHT_COUNT), line:167
|vpiName:MAX_INFLIGHT_COUNT
|INT:19
|vpiParameter:
\_parameter: (MEMORY_ADDR_H), line:103
|vpiName:MEMORY_ADDR_H
|INT:12
|vpiParameter:
\_parameter: (MEMORY_ADDR_L), line:102
|vpiName:MEMORY_ADDR_L
|INT:11
|vpiParameter:
\_parameter: (MEMORY_BIT_CHECK), line:104
|vpiName:MEMORY_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (MUL_UNIT_WB_ID), line:193
|vpiName:MUL_UNIT_WB_ID
|INT:512
|vpiParameter:
\_parameter: (NUM_UNITS), line:188
|vpiName:NUM_UNITS
|INT:2
|vpiParameter:
\_parameter: (NUM_WB_UNITS), line:186
|vpiName:NUM_WB_UNITS
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (RAS_DEPTH), line:161
|vpiName:RAS_DEPTH
|INT:2
|vpiParameter:
\_parameter: (RESET_VEC), line:39
|vpiName:RESET_VEC
|INT:-2147483648
|vpiParameter:
\_parameter: (SCRATCH_ADDR_H), line:99
|vpiName:SCRATCH_ADDR_H
|INT:9
|vpiParameter:
\_parameter: (SCRATCH_ADDR_L), line:98
|vpiName:SCRATCH_ADDR_L
|INT:8
|vpiParameter:
\_parameter: (SCRATCH_BIT_CHECK), line:100
|vpiName:SCRATCH_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (USE_AMO), line:70
|vpiName:USE_AMO
|INT:1
|vpiParameter:
\_parameter: (USE_BRANCH_PREDICTOR), line:158
|vpiName:USE_BRANCH_PREDICTOR
|INT:2
|vpiParameter:
\_parameter: (USE_BUS), line:88
|vpiName:USE_BUS
|INT:4
|vpiParameter:
\_parameter: (USE_DCACHE), line:92
|vpiName:USE_DCACHE
|INT:6
|vpiParameter:
\_parameter: (USE_DIV), line:49
|vpiName:USE_DIV
|INT:1
|vpiParameter:
\_parameter: (USE_DTAG_INVALIDATIONS), line:140
|vpiName:USE_DTAG_INVALIDATIONS
|INT:1879048191
|vpiParameter:
\_parameter: (USE_D_SCRATCH_MEM), line:79
|vpiName:USE_D_SCRATCH_MEM
|INT:3
|vpiParameter:
\_parameter: (USE_ICACHE), line:93
|vpiName:USE_ICACHE
|INT:7
|vpiParameter:
\_parameter: (USE_I_SCRATCH_MEM), line:78
|vpiName:USE_I_SCRATCH_MEM
|INT:2
|vpiParameter:
\_parameter: (USE_MUL), line:48
|vpiName:USE_MUL
|INT:1
|vpiParameter:
\_parameter: (WB_UNITS_WIDTH), line:187
|vpiName:WB_UNITS_WIDTH
|INT:32
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiParameter:
\_parameter: (i), line:54
|vpiName:i
|INT:5
|vpiGenScopeArray:
\_gen_scope_array: (genblk1[6]), line:54, parent:arb
|vpiName:genblk1[6]
|vpiFullName:work@taiga_wrapper.cpu.genblk1.arb.genblk1[6]
|vpiGenScope:
\_gen_scope: , parent:genblk1[6]
|vpiFullName:work@taiga_wrapper.cpu.genblk1.arb.genblk1[6]
|vpiContAssign:
\_cont_assign: , line:55
|vpiRhs:
\_bit_select: (l1_request.request), line:55
|vpiName:l1_request.request
|vpiFullName:work@taiga_wrapper.cpu.genblk1.arb.genblk1[6].l1_request.request
|vpiIndex:
\_ref_obj: (i), line:55
|vpiName:i
|vpiLhs:
\_bit_select: (requests), line:55
|vpiName:requests
|vpiFullName:work@taiga_wrapper.cpu.genblk1.arb.genblk1[6].requests
|vpiIndex:
\_ref_obj: (i), line:55
|vpiName:i
|vpiContAssign:
\_cont_assign: , line:56
|vpiRhs:
\_bit_select: (acks), line:56
|vpiName:acks
|vpiFullName:work@taiga_wrapper.cpu.genblk1.arb.genblk1[6].acks
|vpiIndex:
\_ref_obj: (i), line:56
|vpiName:i
|vpiLhs:
\_ref_obj: (l1_request[i].ack), line:56
|vpiName:l1_request[i].ack
|vpiFullName:work@taiga_wrapper.cpu.genblk1.arb.genblk1[6].l1_request[i].ack
|vpiParameter:
\_parameter: (ALU_UNIT_WB_ID), line:190
|vpiName:ALU_UNIT_WB_ID
|INT:32
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (BRANCH_PREDICTOR_WAYS), line:159
|vpiName:BRANCH_PREDICTOR_WAYS
|INT:9
|vpiParameter:
\_parameter: (BRANCH_TABLE_ENTRIES), line:160
|vpiName:BRANCH_TABLE_ENTRIES
|INT:4
|vpiParameter:
\_parameter: (BRANCH_UNIT_ID), line:195
|vpiName:BRANCH_UNIT_ID
|INT:8
|vpiParameter:
\_parameter: (BUS_ADDR_H), line:107
|vpiName:BUS_ADDR_H
|INT:1
|vpiParameter:
\_parameter: (BUS_ADDR_L), line:106
|vpiName:BUS_ADDR_L
|INT:0
|vpiParameter:
\_parameter: (BUS_BIT_CHECK), line:108
|vpiName:BUS_BIT_CHECK
|INT:1
|vpiParameter:
\_parameter: (BUS_TYPE), line:89
|vpiName:BUS_TYPE
|INT:5
|vpiParameter:
\_parameter: (COUNTER_W), line:42
|vpiName:COUNTER_W
|INT:33
|vpiParameter:
\_parameter: (CPU_ID), line:38
|vpiName:CPU_ID
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_ADDR_WIDTH), line:113
|vpiName:C_M_AXI_ADDR_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_DATA_WIDTH), line:114
|vpiName:C_M_AXI_DATA_WIDTH
|INT:1
|vpiParameter:
\_parameter: (DCACHE_LINES), line:133
|vpiName:DCACHE_LINES
|INT:-2146435073
|vpiParameter:
\_parameter: (DCACHE_LINE_ADDR_W), line:135
|vpiName:DCACHE_LINE_ADDR_W
|INT:1073741824
|vpiParameter:
\_parameter: (DCACHE_LINE_W), line:136
|vpiName:DCACHE_LINE_W
|INT:1342177279
|vpiParameter:
\_parameter: (DCACHE_SUB_LINE_ADDR_W), line:137
|vpiName:DCACHE_SUB_LINE_ADDR_W
|INT:4
|vpiParameter:
\_parameter: (DCACHE_TAG_W), line:138
|vpiName:DCACHE_TAG_W
|INT:1610612736
|vpiParameter:
\_parameter: (DCACHE_WAYS), line:134
|vpiName:DCACHE_WAYS
|INT:4
|vpiParameter:
\_parameter: (DIV_ALGORITHM), line:67
|vpiName:DIV_ALGORITHM
|INT:0
|vpiParameter:
\_parameter: (DIV_UNIT_WB_ID), line:192
|vpiName:DIV_UNIT_WB_ID
|INT:2
|vpiParameter:
\_parameter: (DTLB_DEPTH), line:152
|vpiName:DTLB_DEPTH
|INT:512
|vpiParameter:
\_parameter: (DTLB_WAYS), line:151
|vpiName:DTLB_WAYS
|INT:32
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (ENABLE_M_MODE), line:34
|vpiName:ENABLE_M_MODE
|INT:1
|vpiParameter:
\_parameter: (ENABLE_S_MODE), line:36
|vpiName:ENABLE_S_MODE
|INT:0
|vpiParameter:
\_parameter: (ENABLE_TRACE_INTERFACE), line:172
|vpiName:ENABLE_TRACE_INTERFACE
|INT:2
|vpiParameter:
\_parameter: (FETCH_BUFFER_DEPTH), line:168
|vpiName:FETCH_BUFFER_DEPTH
|INT:512
|vpiParameter:
\_parameter: (FPGA_VENDOR), line:27
|vpiName:FPGA_VENDOR
|STRING:"xilinx"
|vpiParameter:
\_parameter: (GC_UNIT_ID), line:196
|vpiName:GC_UNIT_ID
|INT:4
|vpiParameter:
\_parameter: (ICACHE_LINES), line:121
|vpiName:ICACHE_LINES
|INT:2
|vpiParameter:
\_parameter: (ICACHE_LINE_ADDR_W), line:123
|vpiName:ICACHE_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_LINE_W), line:124
|vpiName:ICACHE_LINE_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_SUB_LINE_ADDR_W), line:125
|vpiName:ICACHE_SUB_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_TAG_W), line:126
|vpiName:ICACHE_TAG_W
|INT:-2147483648
|vpiParameter:
\_parameter: (ICACHE_WAYS), line:122
|vpiName:ICACHE_WAYS
|INT:1
|vpiParameter:
\_parameter: (ITLB_DEPTH), line:146
|vpiName:ITLB_DEPTH
|INT:32
|vpiParameter:
\_parameter: (ITLB_WAYS), line:145
|vpiName:ITLB_WAYS
|INT:4
|vpiParameter:
\_parameter: (L1_CONNECTIONS), line:177
|vpiName:L1_CONNECTIONS
|INT:9
|vpiParameter:
\_parameter: (L1_DCACHE_ID), line:178
|vpiName:L1_DCACHE_ID
|INT:4
|vpiParameter:
\_parameter: (L1_DMMU_ID), line:179
|vpiName:L1_DMMU_ID
|INT:2
|vpiParameter:
\_parameter: (L1_ICACHE_ID), line:180
|vpiName:L1_ICACHE_ID
|INT:19
|vpiParameter:
\_parameter: (L1_IMMU_ID), line:181
|vpiName:L1_IMMU_ID
|INT:0
|vpiParameter:
\_parameter: (L2_DATA_ATTRIBUTES_FIFO_DEPTH), line:41
|vpiName:L2_DATA_ATTRIBUTES_FIFO_DEPTH
|INT:16
|vpiParameter:
\_parameter: (L2_ID_W), line:46
|vpiName:L2_ID_W
|INT:3
|vpiParameter:
\_parameter: (L2_INPUT_FIFO_DEPTHS), line:34
|vpiName:L2_INPUT_FIFO_DEPTHS
|INT:4
|vpiParameter:
\_parameter: (L2_INVALIDATION_FIFO_DEPTHS), line:35
|vpiName:L2_INVALIDATION_FIFO_DEPTHS
|INT:4
|vpiParameter:
\_parameter: (L2_MEM_ADDR_FIFO_DEPTH), line:39
|vpiName:L2_MEM_ADDR_FIFO_DEPTH
|INT:8
|vpiParameter:
\_parameter: (L2_NUM_PORTS), line:26
|vpiName:L2_NUM_PORTS
|INT:2
|vpiParameter:
\_parameter: (L2_READ_RETURN_FIFO_DEPTHS), line:36
|vpiName:L2_READ_RETURN_FIFO_DEPTHS
|INT:1
|vpiParameter:
\_parameter: (L2_SUB_ID_W), line:27
|vpiName:L2_SUB_ID_W
|INT:2
|vpiParameter:
\_parameter: (LS_UNIT_WB_ID), line:191
|vpiName:LS_UNIT_WB_ID
|INT:1
|vpiParameter:
\_parameter: (MAX_INFLIGHT_COUNT), line:167
|vpiName:MAX_INFLIGHT_COUNT
|INT:19
|vpiParameter:
\_parameter: (MEMORY_ADDR_H), line:103
|vpiName:MEMORY_ADDR_H
|INT:12
|vpiParameter:
\_parameter: (MEMORY_ADDR_L), line:102
|vpiName:MEMORY_ADDR_L
|INT:11
|vpiParameter:
\_parameter: (MEMORY_BIT_CHECK), line:104
|vpiName:MEMORY_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (MUL_UNIT_WB_ID), line:193
|vpiName:MUL_UNIT_WB_ID
|INT:512
|vpiParameter:
\_parameter: (NUM_UNITS), line:188
|vpiName:NUM_UNITS
|INT:2
|vpiParameter:
\_parameter: (NUM_WB_UNITS), line:186
|vpiName:NUM_WB_UNITS
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (RAS_DEPTH), line:161
|vpiName:RAS_DEPTH
|INT:2
|vpiParameter:
\_parameter: (RESET_VEC), line:39
|vpiName:RESET_VEC
|INT:-2147483648
|vpiParameter:
\_parameter: (SCRATCH_ADDR_H), line:99
|vpiName:SCRATCH_ADDR_H
|INT:9
|vpiParameter:
\_parameter: (SCRATCH_ADDR_L), line:98
|vpiName:SCRATCH_ADDR_L
|INT:8
|vpiParameter:
\_parameter: (SCRATCH_BIT_CHECK), line:100
|vpiName:SCRATCH_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (USE_AMO), line:70
|vpiName:USE_AMO
|INT:1
|vpiParameter:
\_parameter: (USE_BRANCH_PREDICTOR), line:158
|vpiName:USE_BRANCH_PREDICTOR
|INT:2
|vpiParameter:
\_parameter: (USE_BUS), line:88
|vpiName:USE_BUS
|INT:4
|vpiParameter:
\_parameter: (USE_DCACHE), line:92
|vpiName:USE_DCACHE
|INT:6
|vpiParameter:
\_parameter: (USE_DIV), line:49
|vpiName:USE_DIV
|INT:1
|vpiParameter:
\_parameter: (USE_DTAG_INVALIDATIONS), line:140
|vpiName:USE_DTAG_INVALIDATIONS
|INT:1879048191
|vpiParameter:
\_parameter: (USE_D_SCRATCH_MEM), line:79
|vpiName:USE_D_SCRATCH_MEM
|INT:3
|vpiParameter:
\_parameter: (USE_ICACHE), line:93
|vpiName:USE_ICACHE
|INT:7
|vpiParameter:
\_parameter: (USE_I_SCRATCH_MEM), line:78
|vpiName:USE_I_SCRATCH_MEM
|INT:2
|vpiParameter:
\_parameter: (USE_MUL), line:48
|vpiName:USE_MUL
|INT:1
|vpiParameter:
\_parameter: (WB_UNITS_WIDTH), line:187
|vpiName:WB_UNITS_WIDTH
|INT:32
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiParameter:
\_parameter: (i), line:54
|vpiName:i
|INT:6
|vpiGenScopeArray:
\_gen_scope_array: (genblk1[7]), line:54, parent:arb
|vpiName:genblk1[7]
|vpiFullName:work@taiga_wrapper.cpu.genblk1.arb.genblk1[7]
|vpiGenScope:
\_gen_scope: , parent:genblk1[7]
|vpiFullName:work@taiga_wrapper.cpu.genblk1.arb.genblk1[7]
|vpiContAssign:
\_cont_assign: , line:55
|vpiRhs:
\_bit_select: (l1_request.request), line:55
|vpiName:l1_request.request
|vpiFullName:work@taiga_wrapper.cpu.genblk1.arb.genblk1[7].l1_request.request
|vpiIndex:
\_ref_obj: (i), line:55
|vpiName:i
|vpiLhs:
\_bit_select: (requests), line:55
|vpiName:requests
|vpiFullName:work@taiga_wrapper.cpu.genblk1.arb.genblk1[7].requests
|vpiIndex:
\_ref_obj: (i), line:55
|vpiName:i
|vpiContAssign:
\_cont_assign: , line:56
|vpiRhs:
\_bit_select: (acks), line:56
|vpiName:acks
|vpiFullName:work@taiga_wrapper.cpu.genblk1.arb.genblk1[7].acks
|vpiIndex:
\_ref_obj: (i), line:56
|vpiName:i
|vpiLhs:
\_ref_obj: (l1_request[i].ack), line:56
|vpiName:l1_request[i].ack
|vpiFullName:work@taiga_wrapper.cpu.genblk1.arb.genblk1[7].l1_request[i].ack
|vpiParameter:
\_parameter: (ALU_UNIT_WB_ID), line:190
|vpiName:ALU_UNIT_WB_ID
|INT:32
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (BRANCH_PREDICTOR_WAYS), line:159
|vpiName:BRANCH_PREDICTOR_WAYS
|INT:9
|vpiParameter:
\_parameter: (BRANCH_TABLE_ENTRIES), line:160
|vpiName:BRANCH_TABLE_ENTRIES
|INT:4
|vpiParameter:
\_parameter: (BRANCH_UNIT_ID), line:195
|vpiName:BRANCH_UNIT_ID
|INT:8
|vpiParameter:
\_parameter: (BUS_ADDR_H), line:107
|vpiName:BUS_ADDR_H
|INT:1
|vpiParameter:
\_parameter: (BUS_ADDR_L), line:106
|vpiName:BUS_ADDR_L
|INT:0
|vpiParameter:
\_parameter: (BUS_BIT_CHECK), line:108
|vpiName:BUS_BIT_CHECK
|INT:1
|vpiParameter:
\_parameter: (BUS_TYPE), line:89
|vpiName:BUS_TYPE
|INT:5
|vpiParameter:
\_parameter: (COUNTER_W), line:42
|vpiName:COUNTER_W
|INT:33
|vpiParameter:
\_parameter: (CPU_ID), line:38
|vpiName:CPU_ID
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_ADDR_WIDTH), line:113
|vpiName:C_M_AXI_ADDR_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_DATA_WIDTH), line:114
|vpiName:C_M_AXI_DATA_WIDTH
|INT:1
|vpiParameter:
\_parameter: (DCACHE_LINES), line:133
|vpiName:DCACHE_LINES
|INT:-2146435073
|vpiParameter:
\_parameter: (DCACHE_LINE_ADDR_W), line:135
|vpiName:DCACHE_LINE_ADDR_W
|INT:1073741824
|vpiParameter:
\_parameter: (DCACHE_LINE_W), line:136
|vpiName:DCACHE_LINE_W
|INT:1342177279
|vpiParameter:
\_parameter: (DCACHE_SUB_LINE_ADDR_W), line:137
|vpiName:DCACHE_SUB_LINE_ADDR_W
|INT:4
|vpiParameter:
\_parameter: (DCACHE_TAG_W), line:138
|vpiName:DCACHE_TAG_W
|INT:1610612736
|vpiParameter:
\_parameter: (DCACHE_WAYS), line:134
|vpiName:DCACHE_WAYS
|INT:4
|vpiParameter:
\_parameter: (DIV_ALGORITHM), line:67
|vpiName:DIV_ALGORITHM
|INT:0
|vpiParameter:
\_parameter: (DIV_UNIT_WB_ID), line:192
|vpiName:DIV_UNIT_WB_ID
|INT:2
|vpiParameter:
\_parameter: (DTLB_DEPTH), line:152
|vpiName:DTLB_DEPTH
|INT:512
|vpiParameter:
\_parameter: (DTLB_WAYS), line:151
|vpiName:DTLB_WAYS
|INT:32
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (ENABLE_M_MODE), line:34
|vpiName:ENABLE_M_MODE
|INT:1
|vpiParameter:
\_parameter: (ENABLE_S_MODE), line:36
|vpiName:ENABLE_S_MODE
|INT:0
|vpiParameter:
\_parameter: (ENABLE_TRACE_INTERFACE), line:172
|vpiName:ENABLE_TRACE_INTERFACE
|INT:2
|vpiParameter:
\_parameter: (FETCH_BUFFER_DEPTH), line:168
|vpiName:FETCH_BUFFER_DEPTH
|INT:512
|vpiParameter:
\_parameter: (FPGA_VENDOR), line:27
|vpiName:FPGA_VENDOR
|STRING:"xilinx"
|vpiParameter:
\_parameter: (GC_UNIT_ID), line:196
|vpiName:GC_UNIT_ID
|INT:4
|vpiParameter:
\_parameter: (ICACHE_LINES), line:121
|vpiName:ICACHE_LINES
|INT:2
|vpiParameter:
\_parameter: (ICACHE_LINE_ADDR_W), line:123
|vpiName:ICACHE_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_LINE_W), line:124
|vpiName:ICACHE_LINE_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_SUB_LINE_ADDR_W), line:125
|vpiName:ICACHE_SUB_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_TAG_W), line:126
|vpiName:ICACHE_TAG_W
|INT:-2147483648
|vpiParameter:
\_parameter: (ICACHE_WAYS), line:122
|vpiName:ICACHE_WAYS
|INT:1
|vpiParameter:
\_parameter: (ITLB_DEPTH), line:146
|vpiName:ITLB_DEPTH
|INT:32
|vpiParameter:
\_parameter: (ITLB_WAYS), line:145
|vpiName:ITLB_WAYS
|INT:4
|vpiParameter:
\_parameter: (L1_CONNECTIONS), line:177
|vpiName:L1_CONNECTIONS
|INT:9
|vpiParameter:
\_parameter: (L1_DCACHE_ID), line:178
|vpiName:L1_DCACHE_ID
|INT:4
|vpiParameter:
\_parameter: (L1_DMMU_ID), line:179
|vpiName:L1_DMMU_ID
|INT:2
|vpiParameter:
\_parameter: (L1_ICACHE_ID), line:180
|vpiName:L1_ICACHE_ID
|INT:19
|vpiParameter:
\_parameter: (L1_IMMU_ID), line:181
|vpiName:L1_IMMU_ID
|INT:0
|vpiParameter:
\_parameter: (L2_DATA_ATTRIBUTES_FIFO_DEPTH), line:41
|vpiName:L2_DATA_ATTRIBUTES_FIFO_DEPTH
|INT:16
|vpiParameter:
\_parameter: (L2_ID_W), line:46
|vpiName:L2_ID_W
|INT:3
|vpiParameter:
\_parameter: (L2_INPUT_FIFO_DEPTHS), line:34
|vpiName:L2_INPUT_FIFO_DEPTHS
|INT:4
|vpiParameter:
\_parameter: (L2_INVALIDATION_FIFO_DEPTHS), line:35
|vpiName:L2_INVALIDATION_FIFO_DEPTHS
|INT:4
|vpiParameter:
\_parameter: (L2_MEM_ADDR_FIFO_DEPTH), line:39
|vpiName:L2_MEM_ADDR_FIFO_DEPTH
|INT:8
|vpiParameter:
\_parameter: (L2_NUM_PORTS), line:26
|vpiName:L2_NUM_PORTS
|INT:2
|vpiParameter:
\_parameter: (L2_READ_RETURN_FIFO_DEPTHS), line:36
|vpiName:L2_READ_RETURN_FIFO_DEPTHS
|INT:1
|vpiParameter:
\_parameter: (L2_SUB_ID_W), line:27
|vpiName:L2_SUB_ID_W
|INT:2
|vpiParameter:
\_parameter: (LS_UNIT_WB_ID), line:191
|vpiName:LS_UNIT_WB_ID
|INT:1
|vpiParameter:
\_parameter: (MAX_INFLIGHT_COUNT), line:167
|vpiName:MAX_INFLIGHT_COUNT
|INT:19
|vpiParameter:
\_parameter: (MEMORY_ADDR_H), line:103
|vpiName:MEMORY_ADDR_H
|INT:12
|vpiParameter:
\_parameter: (MEMORY_ADDR_L), line:102
|vpiName:MEMORY_ADDR_L
|INT:11
|vpiParameter:
\_parameter: (MEMORY_BIT_CHECK), line:104
|vpiName:MEMORY_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (MUL_UNIT_WB_ID), line:193
|vpiName:MUL_UNIT_WB_ID
|INT:512
|vpiParameter:
\_parameter: (NUM_UNITS), line:188
|vpiName:NUM_UNITS
|INT:2
|vpiParameter:
\_parameter: (NUM_WB_UNITS), line:186
|vpiName:NUM_WB_UNITS
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (RAS_DEPTH), line:161
|vpiName:RAS_DEPTH
|INT:2
|vpiParameter:
\_parameter: (RESET_VEC), line:39
|vpiName:RESET_VEC
|INT:-2147483648
|vpiParameter:
\_parameter: (SCRATCH_ADDR_H), line:99
|vpiName:SCRATCH_ADDR_H
|INT:9
|vpiParameter:
\_parameter: (SCRATCH_ADDR_L), line:98
|vpiName:SCRATCH_ADDR_L
|INT:8
|vpiParameter:
\_parameter: (SCRATCH_BIT_CHECK), line:100
|vpiName:SCRATCH_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (USE_AMO), line:70
|vpiName:USE_AMO
|INT:1
|vpiParameter:
\_parameter: (USE_BRANCH_PREDICTOR), line:158
|vpiName:USE_BRANCH_PREDICTOR
|INT:2
|vpiParameter:
\_parameter: (USE_BUS), line:88
|vpiName:USE_BUS
|INT:4
|vpiParameter:
\_parameter: (USE_DCACHE), line:92
|vpiName:USE_DCACHE
|INT:6
|vpiParameter:
\_parameter: (USE_DIV), line:49
|vpiName:USE_DIV
|INT:1
|vpiParameter:
\_parameter: (USE_DTAG_INVALIDATIONS), line:140
|vpiName:USE_DTAG_INVALIDATIONS
|INT:1879048191
|vpiParameter:
\_parameter: (USE_D_SCRATCH_MEM), line:79
|vpiName:USE_D_SCRATCH_MEM
|INT:3
|vpiParameter:
\_parameter: (USE_ICACHE), line:93
|vpiName:USE_ICACHE
|INT:7
|vpiParameter:
\_parameter: (USE_I_SCRATCH_MEM), line:78
|vpiName:USE_I_SCRATCH_MEM
|INT:2
|vpiParameter:
\_parameter: (USE_MUL), line:48
|vpiName:USE_MUL
|INT:1
|vpiParameter:
\_parameter: (WB_UNITS_WIDTH), line:187
|vpiName:WB_UNITS_WIDTH
|INT:32
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiParameter:
\_parameter: (i), line:54
|vpiName:i
|INT:7
|vpiGenScopeArray:
\_gen_scope_array: (genblk1[8]), line:54, parent:arb
|vpiName:genblk1[8]
|vpiFullName:work@taiga_wrapper.cpu.genblk1.arb.genblk1[8]
|vpiGenScope:
\_gen_scope: , parent:genblk1[8]
|vpiFullName:work@taiga_wrapper.cpu.genblk1.arb.genblk1[8]
|vpiContAssign:
\_cont_assign: , line:55
|vpiRhs:
\_bit_select: (l1_request.request), line:55
|vpiName:l1_request.request
|vpiFullName:work@taiga_wrapper.cpu.genblk1.arb.genblk1[8].l1_request.request
|vpiIndex:
\_ref_obj: (i), line:55
|vpiName:i
|vpiLhs:
\_bit_select: (requests), line:55
|vpiName:requests
|vpiFullName:work@taiga_wrapper.cpu.genblk1.arb.genblk1[8].requests
|vpiIndex:
\_ref_obj: (i), line:55
|vpiName:i
|vpiContAssign:
\_cont_assign: , line:56
|vpiRhs:
\_bit_select: (acks), line:56
|vpiName:acks
|vpiFullName:work@taiga_wrapper.cpu.genblk1.arb.genblk1[8].acks
|vpiIndex:
\_ref_obj: (i), line:56
|vpiName:i
|vpiLhs:
\_ref_obj: (l1_request[i].ack), line:56
|vpiName:l1_request[i].ack
|vpiFullName:work@taiga_wrapper.cpu.genblk1.arb.genblk1[8].l1_request[i].ack
|vpiParameter:
\_parameter: (ALU_UNIT_WB_ID), line:190
|vpiName:ALU_UNIT_WB_ID
|INT:32
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (BRANCH_PREDICTOR_WAYS), line:159
|vpiName:BRANCH_PREDICTOR_WAYS
|INT:9
|vpiParameter:
\_parameter: (BRANCH_TABLE_ENTRIES), line:160
|vpiName:BRANCH_TABLE_ENTRIES
|INT:4
|vpiParameter:
\_parameter: (BRANCH_UNIT_ID), line:195
|vpiName:BRANCH_UNIT_ID
|INT:8
|vpiParameter:
\_parameter: (BUS_ADDR_H), line:107
|vpiName:BUS_ADDR_H
|INT:1
|vpiParameter:
\_parameter: (BUS_ADDR_L), line:106
|vpiName:BUS_ADDR_L
|INT:0
|vpiParameter:
\_parameter: (BUS_BIT_CHECK), line:108
|vpiName:BUS_BIT_CHECK
|INT:1
|vpiParameter:
\_parameter: (BUS_TYPE), line:89
|vpiName:BUS_TYPE
|INT:5
|vpiParameter:
\_parameter: (COUNTER_W), line:42
|vpiName:COUNTER_W
|INT:33
|vpiParameter:
\_parameter: (CPU_ID), line:38
|vpiName:CPU_ID
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_ADDR_WIDTH), line:113
|vpiName:C_M_AXI_ADDR_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_DATA_WIDTH), line:114
|vpiName:C_M_AXI_DATA_WIDTH
|INT:1
|vpiParameter:
\_parameter: (DCACHE_LINES), line:133
|vpiName:DCACHE_LINES
|INT:-2146435073
|vpiParameter:
\_parameter: (DCACHE_LINE_ADDR_W), line:135
|vpiName:DCACHE_LINE_ADDR_W
|INT:1073741824
|vpiParameter:
\_parameter: (DCACHE_LINE_W), line:136
|vpiName:DCACHE_LINE_W
|INT:1342177279
|vpiParameter:
\_parameter: (DCACHE_SUB_LINE_ADDR_W), line:137
|vpiName:DCACHE_SUB_LINE_ADDR_W
|INT:4
|vpiParameter:
\_parameter: (DCACHE_TAG_W), line:138
|vpiName:DCACHE_TAG_W
|INT:1610612736
|vpiParameter:
\_parameter: (DCACHE_WAYS), line:134
|vpiName:DCACHE_WAYS
|INT:4
|vpiParameter:
\_parameter: (DIV_ALGORITHM), line:67
|vpiName:DIV_ALGORITHM
|INT:0
|vpiParameter:
\_parameter: (DIV_UNIT_WB_ID), line:192
|vpiName:DIV_UNIT_WB_ID
|INT:2
|vpiParameter:
\_parameter: (DTLB_DEPTH), line:152
|vpiName:DTLB_DEPTH
|INT:512
|vpiParameter:
\_parameter: (DTLB_WAYS), line:151
|vpiName:DTLB_WAYS
|INT:32
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (ENABLE_M_MODE), line:34
|vpiName:ENABLE_M_MODE
|INT:1
|vpiParameter:
\_parameter: (ENABLE_S_MODE), line:36
|vpiName:ENABLE_S_MODE
|INT:0
|vpiParameter:
\_parameter: (ENABLE_TRACE_INTERFACE), line:172
|vpiName:ENABLE_TRACE_INTERFACE
|INT:2
|vpiParameter:
\_parameter: (FETCH_BUFFER_DEPTH), line:168
|vpiName:FETCH_BUFFER_DEPTH
|INT:512
|vpiParameter:
\_parameter: (FPGA_VENDOR), line:27
|vpiName:FPGA_VENDOR
|STRING:"xilinx"
|vpiParameter:
\_parameter: (GC_UNIT_ID), line:196
|vpiName:GC_UNIT_ID
|INT:4
|vpiParameter:
\_parameter: (ICACHE_LINES), line:121
|vpiName:ICACHE_LINES
|INT:2
|vpiParameter:
\_parameter: (ICACHE_LINE_ADDR_W), line:123
|vpiName:ICACHE_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_LINE_W), line:124
|vpiName:ICACHE_LINE_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_SUB_LINE_ADDR_W), line:125
|vpiName:ICACHE_SUB_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_TAG_W), line:126
|vpiName:ICACHE_TAG_W
|INT:-2147483648
|vpiParameter:
\_parameter: (ICACHE_WAYS), line:122
|vpiName:ICACHE_WAYS
|INT:1
|vpiParameter:
\_parameter: (ITLB_DEPTH), line:146
|vpiName:ITLB_DEPTH
|INT:32
|vpiParameter:
\_parameter: (ITLB_WAYS), line:145
|vpiName:ITLB_WAYS
|INT:4
|vpiParameter:
\_parameter: (L1_CONNECTIONS), line:177
|vpiName:L1_CONNECTIONS
|INT:9
|vpiParameter:
\_parameter: (L1_DCACHE_ID), line:178
|vpiName:L1_DCACHE_ID
|INT:4
|vpiParameter:
\_parameter: (L1_DMMU_ID), line:179
|vpiName:L1_DMMU_ID
|INT:2
|vpiParameter:
\_parameter: (L1_ICACHE_ID), line:180
|vpiName:L1_ICACHE_ID
|INT:19
|vpiParameter:
\_parameter: (L1_IMMU_ID), line:181
|vpiName:L1_IMMU_ID
|INT:0
|vpiParameter:
\_parameter: (L2_DATA_ATTRIBUTES_FIFO_DEPTH), line:41
|vpiName:L2_DATA_ATTRIBUTES_FIFO_DEPTH
|INT:16
|vpiParameter:
\_parameter: (L2_ID_W), line:46
|vpiName:L2_ID_W
|INT:3
|vpiParameter:
\_parameter: (L2_INPUT_FIFO_DEPTHS), line:34
|vpiName:L2_INPUT_FIFO_DEPTHS
|INT:4
|vpiParameter:
\_parameter: (L2_INVALIDATION_FIFO_DEPTHS), line:35
|vpiName:L2_INVALIDATION_FIFO_DEPTHS
|INT:4
|vpiParameter:
\_parameter: (L2_MEM_ADDR_FIFO_DEPTH), line:39
|vpiName:L2_MEM_ADDR_FIFO_DEPTH
|INT:8
|vpiParameter:
\_parameter: (L2_NUM_PORTS), line:26
|vpiName:L2_NUM_PORTS
|INT:2
|vpiParameter:
\_parameter: (L2_READ_RETURN_FIFO_DEPTHS), line:36
|vpiName:L2_READ_RETURN_FIFO_DEPTHS
|INT:1
|vpiParameter:
\_parameter: (L2_SUB_ID_W), line:27
|vpiName:L2_SUB_ID_W
|INT:2
|vpiParameter:
\_parameter: (LS_UNIT_WB_ID), line:191
|vpiName:LS_UNIT_WB_ID
|INT:1
|vpiParameter:
\_parameter: (MAX_INFLIGHT_COUNT), line:167
|vpiName:MAX_INFLIGHT_COUNT
|INT:19
|vpiParameter:
\_parameter: (MEMORY_ADDR_H), line:103
|vpiName:MEMORY_ADDR_H
|INT:12
|vpiParameter:
\_parameter: (MEMORY_ADDR_L), line:102
|vpiName:MEMORY_ADDR_L
|INT:11
|vpiParameter:
\_parameter: (MEMORY_BIT_CHECK), line:104
|vpiName:MEMORY_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (MUL_UNIT_WB_ID), line:193
|vpiName:MUL_UNIT_WB_ID
|INT:512
|vpiParameter:
\_parameter: (NUM_UNITS), line:188
|vpiName:NUM_UNITS
|INT:2
|vpiParameter:
\_parameter: (NUM_WB_UNITS), line:186
|vpiName:NUM_WB_UNITS
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (RAS_DEPTH), line:161
|vpiName:RAS_DEPTH
|INT:2
|vpiParameter:
\_parameter: (RESET_VEC), line:39
|vpiName:RESET_VEC
|INT:-2147483648
|vpiParameter:
\_parameter: (SCRATCH_ADDR_H), line:99
|vpiName:SCRATCH_ADDR_H
|INT:9
|vpiParameter:
\_parameter: (SCRATCH_ADDR_L), line:98
|vpiName:SCRATCH_ADDR_L
|INT:8
|vpiParameter:
\_parameter: (SCRATCH_BIT_CHECK), line:100
|vpiName:SCRATCH_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (USE_AMO), line:70
|vpiName:USE_AMO
|INT:1
|vpiParameter:
\_parameter: (USE_BRANCH_PREDICTOR), line:158
|vpiName:USE_BRANCH_PREDICTOR
|INT:2
|vpiParameter:
\_parameter: (USE_BUS), line:88
|vpiName:USE_BUS
|INT:4
|vpiParameter:
\_parameter: (USE_DCACHE), line:92
|vpiName:USE_DCACHE
|INT:6
|vpiParameter:
\_parameter: (USE_DIV), line:49
|vpiName:USE_DIV
|INT:1
|vpiParameter:
\_parameter: (USE_DTAG_INVALIDATIONS), line:140
|vpiName:USE_DTAG_INVALIDATIONS
|INT:1879048191
|vpiParameter:
\_parameter: (USE_D_SCRATCH_MEM), line:79
|vpiName:USE_D_SCRATCH_MEM
|INT:3
|vpiParameter:
\_parameter: (USE_ICACHE), line:93
|vpiName:USE_ICACHE
|INT:7
|vpiParameter:
\_parameter: (USE_I_SCRATCH_MEM), line:78
|vpiName:USE_I_SCRATCH_MEM
|INT:2
|vpiParameter:
\_parameter: (USE_MUL), line:48
|vpiName:USE_MUL
|INT:1
|vpiParameter:
\_parameter: (WB_UNITS_WIDTH), line:187
|vpiName:WB_UNITS_WIDTH
|INT:32
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiParameter:
\_parameter: (i), line:54
|vpiName:i
|INT:8
|vpiGenScopeArray:
\_gen_scope_array: (genblk2), line:61, parent:arb
|vpiName:genblk2
|vpiFullName:work@taiga_wrapper.cpu.genblk1.arb.genblk2
|vpiGenScope:
\_gen_scope: , parent:genblk2
|vpiFullName:work@taiga_wrapper.cpu.genblk1.arb.genblk2
|vpiContAssign:
\_cont_assign: , line:62
|vpiRhs:
\_bit_select: (l1_response.inv_ack), line:62
|vpiName:l1_response.inv_ack
|vpiFullName:work@taiga_wrapper.cpu.genblk1.arb.genblk2.l1_response.inv_ack
|vpiIndex:
\_ref_obj: (L1_DCACHE_ID), line:62
|vpiName:L1_DCACHE_ID
|vpiLhs:
\_ref_obj: (l2.inv_ack), line:62
|vpiName:l2.inv_ack
|vpiFullName:work@taiga_wrapper.cpu.genblk1.arb.genblk2.l2.inv_ack
|vpiContAssign:
\_cont_assign: , line:64
|vpiRhs:
\_ref_obj: (l2.inv_valid), line:64
|vpiName:l2.inv_valid
|vpiFullName:work@taiga_wrapper.cpu.genblk1.arb.genblk2.l2.inv_valid
|vpiLhs:
\_ref_obj: (l2.inv_ack), line:64
|vpiName:l2.inv_ack
|vpiFullName:work@taiga_wrapper.cpu.genblk1.arb.genblk2.l2.inv_ack
|vpiParameter:
\_parameter: (ALU_UNIT_WB_ID), line:190
|vpiName:ALU_UNIT_WB_ID
|INT:32
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (BRANCH_PREDICTOR_WAYS), line:159
|vpiName:BRANCH_PREDICTOR_WAYS
|INT:9
|vpiParameter:
\_parameter: (BRANCH_TABLE_ENTRIES), line:160
|vpiName:BRANCH_TABLE_ENTRIES
|INT:4
|vpiParameter:
\_parameter: (BRANCH_UNIT_ID), line:195
|vpiName:BRANCH_UNIT_ID
|INT:8
|vpiParameter:
\_parameter: (BUS_ADDR_H), line:107
|vpiName:BUS_ADDR_H
|INT:1
|vpiParameter:
\_parameter: (BUS_ADDR_L), line:106
|vpiName:BUS_ADDR_L
|INT:0
|vpiParameter:
\_parameter: (BUS_BIT_CHECK), line:108
|vpiName:BUS_BIT_CHECK
|INT:1
|vpiParameter:
\_parameter: (BUS_TYPE), line:89
|vpiName:BUS_TYPE
|INT:5
|vpiParameter:
\_parameter: (COUNTER_W), line:42
|vpiName:COUNTER_W
|INT:33
|vpiParameter:
\_parameter: (CPU_ID), line:38
|vpiName:CPU_ID
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_ADDR_WIDTH), line:113
|vpiName:C_M_AXI_ADDR_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_DATA_WIDTH), line:114
|vpiName:C_M_AXI_DATA_WIDTH
|INT:1
|vpiParameter:
\_parameter: (DCACHE_LINES), line:133
|vpiName:DCACHE_LINES
|INT:-2146435073
|vpiParameter:
\_parameter: (DCACHE_LINE_ADDR_W), line:135
|vpiName:DCACHE_LINE_ADDR_W
|INT:1073741824
|vpiParameter:
\_parameter: (DCACHE_LINE_W), line:136
|vpiName:DCACHE_LINE_W
|INT:1342177279
|vpiParameter:
\_parameter: (DCACHE_SUB_LINE_ADDR_W), line:137
|vpiName:DCACHE_SUB_LINE_ADDR_W
|INT:4
|vpiParameter:
\_parameter: (DCACHE_TAG_W), line:138
|vpiName:DCACHE_TAG_W
|INT:1610612736
|vpiParameter:
\_parameter: (DCACHE_WAYS), line:134
|vpiName:DCACHE_WAYS
|INT:4
|vpiParameter:
\_parameter: (DIV_ALGORITHM), line:67
|vpiName:DIV_ALGORITHM
|INT:0
|vpiParameter:
\_parameter: (DIV_UNIT_WB_ID), line:192
|vpiName:DIV_UNIT_WB_ID
|INT:2
|vpiParameter:
\_parameter: (DTLB_DEPTH), line:152
|vpiName:DTLB_DEPTH
|INT:512
|vpiParameter:
\_parameter: (DTLB_WAYS), line:151
|vpiName:DTLB_WAYS
|INT:32
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (ENABLE_M_MODE), line:34
|vpiName:ENABLE_M_MODE
|INT:1
|vpiParameter:
\_parameter: (ENABLE_S_MODE), line:36
|vpiName:ENABLE_S_MODE
|INT:0
|vpiParameter:
\_parameter: (ENABLE_TRACE_INTERFACE), line:172
|vpiName:ENABLE_TRACE_INTERFACE
|INT:2
|vpiParameter:
\_parameter: (FETCH_BUFFER_DEPTH), line:168
|vpiName:FETCH_BUFFER_DEPTH
|INT:512
|vpiParameter:
\_parameter: (FPGA_VENDOR), line:27
|vpiName:FPGA_VENDOR
|STRING:"xilinx"
|vpiParameter:
\_parameter: (GC_UNIT_ID), line:196
|vpiName:GC_UNIT_ID
|INT:4
|vpiParameter:
\_parameter: (ICACHE_LINES), line:121
|vpiName:ICACHE_LINES
|INT:2
|vpiParameter:
\_parameter: (ICACHE_LINE_ADDR_W), line:123
|vpiName:ICACHE_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_LINE_W), line:124
|vpiName:ICACHE_LINE_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_SUB_LINE_ADDR_W), line:125
|vpiName:ICACHE_SUB_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_TAG_W), line:126
|vpiName:ICACHE_TAG_W
|INT:-2147483648
|vpiParameter:
\_parameter: (ICACHE_WAYS), line:122
|vpiName:ICACHE_WAYS
|INT:1
|vpiParameter:
\_parameter: (ITLB_DEPTH), line:146
|vpiName:ITLB_DEPTH
|INT:32
|vpiParameter:
\_parameter: (ITLB_WAYS), line:145
|vpiName:ITLB_WAYS
|INT:4
|vpiParameter:
\_parameter: (L1_CONNECTIONS), line:177
|vpiName:L1_CONNECTIONS
|INT:9
|vpiParameter:
\_parameter: (L1_DCACHE_ID), line:178
|vpiName:L1_DCACHE_ID
|INT:4
|vpiParameter:
\_parameter: (L1_DMMU_ID), line:179
|vpiName:L1_DMMU_ID
|INT:2
|vpiParameter:
\_parameter: (L1_ICACHE_ID), line:180
|vpiName:L1_ICACHE_ID
|INT:19
|vpiParameter:
\_parameter: (L1_IMMU_ID), line:181
|vpiName:L1_IMMU_ID
|INT:0
|vpiParameter:
\_parameter: (L2_DATA_ATTRIBUTES_FIFO_DEPTH), line:41
|vpiName:L2_DATA_ATTRIBUTES_FIFO_DEPTH
|INT:16
|vpiParameter:
\_parameter: (L2_ID_W), line:46
|vpiName:L2_ID_W
|INT:3
|vpiParameter:
\_parameter: (L2_INPUT_FIFO_DEPTHS), line:34
|vpiName:L2_INPUT_FIFO_DEPTHS
|INT:4
|vpiParameter:
\_parameter: (L2_INVALIDATION_FIFO_DEPTHS), line:35
|vpiName:L2_INVALIDATION_FIFO_DEPTHS
|INT:4
|vpiParameter:
\_parameter: (L2_MEM_ADDR_FIFO_DEPTH), line:39
|vpiName:L2_MEM_ADDR_FIFO_DEPTH
|INT:8
|vpiParameter:
\_parameter: (L2_NUM_PORTS), line:26
|vpiName:L2_NUM_PORTS
|INT:2
|vpiParameter:
\_parameter: (L2_READ_RETURN_FIFO_DEPTHS), line:36
|vpiName:L2_READ_RETURN_FIFO_DEPTHS
|INT:1
|vpiParameter:
\_parameter: (L2_SUB_ID_W), line:27
|vpiName:L2_SUB_ID_W
|INT:2
|vpiParameter:
\_parameter: (LS_UNIT_WB_ID), line:191
|vpiName:LS_UNIT_WB_ID
|INT:1
|vpiParameter:
\_parameter: (MAX_INFLIGHT_COUNT), line:167
|vpiName:MAX_INFLIGHT_COUNT
|INT:19
|vpiParameter:
\_parameter: (MEMORY_ADDR_H), line:103
|vpiName:MEMORY_ADDR_H
|INT:12
|vpiParameter:
\_parameter: (MEMORY_ADDR_L), line:102
|vpiName:MEMORY_ADDR_L
|INT:11
|vpiParameter:
\_parameter: (MEMORY_BIT_CHECK), line:104
|vpiName:MEMORY_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (MUL_UNIT_WB_ID), line:193
|vpiName:MUL_UNIT_WB_ID
|INT:512
|vpiParameter:
\_parameter: (NUM_UNITS), line:188
|vpiName:NUM_UNITS
|INT:2
|vpiParameter:
\_parameter: (NUM_WB_UNITS), line:186
|vpiName:NUM_WB_UNITS
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (RAS_DEPTH), line:161
|vpiName:RAS_DEPTH
|INT:2
|vpiParameter:
\_parameter: (RESET_VEC), line:39
|vpiName:RESET_VEC
|INT:-2147483648
|vpiParameter:
\_parameter: (SCRATCH_ADDR_H), line:99
|vpiName:SCRATCH_ADDR_H
|INT:9
|vpiParameter:
\_parameter: (SCRATCH_ADDR_L), line:98
|vpiName:SCRATCH_ADDR_L
|INT:8
|vpiParameter:
\_parameter: (SCRATCH_BIT_CHECK), line:100
|vpiName:SCRATCH_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (USE_AMO), line:70
|vpiName:USE_AMO
|INT:1
|vpiParameter:
\_parameter: (USE_BRANCH_PREDICTOR), line:158
|vpiName:USE_BRANCH_PREDICTOR
|INT:2
|vpiParameter:
\_parameter: (USE_BUS), line:88
|vpiName:USE_BUS
|INT:4
|vpiParameter:
\_parameter: (USE_DCACHE), line:92
|vpiName:USE_DCACHE
|INT:6
|vpiParameter:
\_parameter: (USE_DIV), line:49
|vpiName:USE_DIV
|INT:1
|vpiParameter:
\_parameter: (USE_DTAG_INVALIDATIONS), line:140
|vpiName:USE_DTAG_INVALIDATIONS
|INT:1879048191
|vpiParameter:
\_parameter: (USE_D_SCRATCH_MEM), line:79
|vpiName:USE_D_SCRATCH_MEM
|INT:3
|vpiParameter:
\_parameter: (USE_ICACHE), line:93
|vpiName:USE_ICACHE
|INT:7
|vpiParameter:
\_parameter: (USE_I_SCRATCH_MEM), line:78
|vpiName:USE_I_SCRATCH_MEM
|INT:2
|vpiParameter:
\_parameter: (USE_MUL), line:48
|vpiName:USE_MUL
|INT:1
|vpiParameter:
\_parameter: (WB_UNITS_WIDTH), line:187
|vpiName:WB_UNITS_WIDTH
|INT:32
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiGenScopeArray:
\_gen_scope_array: (genblk3), line:90, parent:arb
|vpiName:genblk3
|vpiFullName:work@taiga_wrapper.cpu.genblk1.arb.genblk3
|vpiGenScope:
\_gen_scope: , parent:genblk3
|vpiFullName:work@taiga_wrapper.cpu.genblk1.arb.genblk3
|vpiContAssign:
\_cont_assign: , line:91
|vpiRhs:
\_operation: , line:91
|vpiOpType:28
|vpiOperand:
\_operation: , line:91
|vpiOpType:28
|vpiOperand:
\_ref_obj: (push_ready), line:91
|vpiName:push_ready
|vpiFullName:work@taiga_wrapper.cpu.genblk1.arb.genblk3.push_ready
|vpiOperand:
\_bit_select: (l1_request.request), line:91
|vpiName:l1_request.request
|vpiFullName:work@taiga_wrapper.cpu.genblk1.arb.genblk3.l1_request.request
|vpiIndex:
\_ref_obj: (L1_DCACHE_ID), line:91
|vpiName:L1_DCACHE_ID
|vpiFullName:work@taiga_wrapper.cpu.genblk1.arb.genblk3.L1_DCACHE_ID
|vpiOperand:
\_operation: , line:91
|vpiOpType:4
|vpiOperand:
\_bit_select: (l1_request.rnw), line:91
|vpiName:l1_request.rnw
|vpiFullName:work@taiga_wrapper.cpu.genblk1.arb.genblk3.l1_request.rnw
|vpiIndex:
\_ref_obj: (L1_DCACHE_ID), line:91
|vpiName:L1_DCACHE_ID
|vpiFullName:work@taiga_wrapper.cpu.genblk1.arb.genblk3.L1_DCACHE_ID
|vpiLhs:
\_ref_obj: (l2.wr_data_push), line:91
|vpiName:l2.wr_data_push
|vpiFullName:work@taiga_wrapper.cpu.genblk1.arb.genblk3.l2.wr_data_push
|vpiContAssign:
\_cont_assign: , line:92
|vpiRhs:
\_bit_select: (l1_request.data), line:92
|vpiName:l1_request.data
|vpiFullName:work@taiga_wrapper.cpu.genblk1.arb.genblk3.l1_request.data
|vpiIndex:
\_ref_obj: (L1_DCACHE_ID), line:92
|vpiName:L1_DCACHE_ID
|vpiLhs:
\_ref_obj: (l2.wr_data), line:92
|vpiName:l2.wr_data
|vpiFullName:work@taiga_wrapper.cpu.genblk1.arb.genblk3.l2.wr_data
|vpiContAssign:
\_cont_assign: , line:95
|vpiRhs:
\_constant: , line:95
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiLhs:
\_ref_obj: (l2.wr_data_push), line:95
|vpiName:l2.wr_data_push
|vpiFullName:work@taiga_wrapper.cpu.genblk1.arb.genblk3.l2.wr_data_push
|vpiContAssign:
\_cont_assign: , line:96
|vpiRhs:
\_constant: , line:96
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiLhs:
\_ref_obj: (l2.wr_data), line:96
|vpiName:l2.wr_data
|vpiFullName:work@taiga_wrapper.cpu.genblk1.arb.genblk3.l2.wr_data
|vpiParameter:
\_parameter: (ALU_UNIT_WB_ID), line:190
|vpiName:ALU_UNIT_WB_ID
|INT:32
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (BRANCH_PREDICTOR_WAYS), line:159
|vpiName:BRANCH_PREDICTOR_WAYS
|INT:9
|vpiParameter:
\_parameter: (BRANCH_TABLE_ENTRIES), line:160
|vpiName:BRANCH_TABLE_ENTRIES
|INT:4
|vpiParameter:
\_parameter: (BRANCH_UNIT_ID), line:195
|vpiName:BRANCH_UNIT_ID
|INT:8
|vpiParameter:
\_parameter: (BUS_ADDR_H), line:107
|vpiName:BUS_ADDR_H
|INT:1
|vpiParameter:
\_parameter: (BUS_ADDR_L), line:106
|vpiName:BUS_ADDR_L
|INT:0
|vpiParameter:
\_parameter: (BUS_BIT_CHECK), line:108
|vpiName:BUS_BIT_CHECK
|INT:1
|vpiParameter:
\_parameter: (BUS_TYPE), line:89
|vpiName:BUS_TYPE
|INT:5
|vpiParameter:
\_parameter: (COUNTER_W), line:42
|vpiName:COUNTER_W
|INT:33
|vpiParameter:
\_parameter: (CPU_ID), line:38
|vpiName:CPU_ID
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_ADDR_WIDTH), line:113
|vpiName:C_M_AXI_ADDR_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_DATA_WIDTH), line:114
|vpiName:C_M_AXI_DATA_WIDTH
|INT:1
|vpiParameter:
\_parameter: (DCACHE_LINES), line:133
|vpiName:DCACHE_LINES
|INT:-2146435073
|vpiParameter:
\_parameter: (DCACHE_LINE_ADDR_W), line:135
|vpiName:DCACHE_LINE_ADDR_W
|INT:1073741824
|vpiParameter:
\_parameter: (DCACHE_LINE_W), line:136
|vpiName:DCACHE_LINE_W
|INT:1342177279
|vpiParameter:
\_parameter: (DCACHE_SUB_LINE_ADDR_W), line:137
|vpiName:DCACHE_SUB_LINE_ADDR_W
|INT:4
|vpiParameter:
\_parameter: (DCACHE_TAG_W), line:138
|vpiName:DCACHE_TAG_W
|INT:1610612736
|vpiParameter:
\_parameter: (DCACHE_WAYS), line:134
|vpiName:DCACHE_WAYS
|INT:4
|vpiParameter:
\_parameter: (DIV_ALGORITHM), line:67
|vpiName:DIV_ALGORITHM
|INT:0
|vpiParameter:
\_parameter: (DIV_UNIT_WB_ID), line:192
|vpiName:DIV_UNIT_WB_ID
|INT:2
|vpiParameter:
\_parameter: (DTLB_DEPTH), line:152
|vpiName:DTLB_DEPTH
|INT:512
|vpiParameter:
\_parameter: (DTLB_WAYS), line:151
|vpiName:DTLB_WAYS
|INT:32
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (ENABLE_M_MODE), line:34
|vpiName:ENABLE_M_MODE
|INT:1
|vpiParameter:
\_parameter: (ENABLE_S_MODE), line:36
|vpiName:ENABLE_S_MODE
|INT:0
|vpiParameter:
\_parameter: (ENABLE_TRACE_INTERFACE), line:172
|vpiName:ENABLE_TRACE_INTERFACE
|INT:2
|vpiParameter:
\_parameter: (FETCH_BUFFER_DEPTH), line:168
|vpiName:FETCH_BUFFER_DEPTH
|INT:512
|vpiParameter:
\_parameter: (FPGA_VENDOR), line:27
|vpiName:FPGA_VENDOR
|STRING:"xilinx"
|vpiParameter:
\_parameter: (GC_UNIT_ID), line:196
|vpiName:GC_UNIT_ID
|INT:4
|vpiParameter:
\_parameter: (ICACHE_LINES), line:121
|vpiName:ICACHE_LINES
|INT:2
|vpiParameter:
\_parameter: (ICACHE_LINE_ADDR_W), line:123
|vpiName:ICACHE_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_LINE_W), line:124
|vpiName:ICACHE_LINE_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_SUB_LINE_ADDR_W), line:125
|vpiName:ICACHE_SUB_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_TAG_W), line:126
|vpiName:ICACHE_TAG_W
|INT:-2147483648
|vpiParameter:
\_parameter: (ICACHE_WAYS), line:122
|vpiName:ICACHE_WAYS
|INT:1
|vpiParameter:
\_parameter: (ITLB_DEPTH), line:146
|vpiName:ITLB_DEPTH
|INT:32
|vpiParameter:
\_parameter: (ITLB_WAYS), line:145
|vpiName:ITLB_WAYS
|INT:4
|vpiParameter:
\_parameter: (L1_CONNECTIONS), line:177
|vpiName:L1_CONNECTIONS
|INT:9
|vpiParameter:
\_parameter: (L1_DCACHE_ID), line:178
|vpiName:L1_DCACHE_ID
|INT:4
|vpiParameter:
\_parameter: (L1_DMMU_ID), line:179
|vpiName:L1_DMMU_ID
|INT:2
|vpiParameter:
\_parameter: (L1_ICACHE_ID), line:180
|vpiName:L1_ICACHE_ID
|INT:19
|vpiParameter:
\_parameter: (L1_IMMU_ID), line:181
|vpiName:L1_IMMU_ID
|INT:0
|vpiParameter:
\_parameter: (L2_DATA_ATTRIBUTES_FIFO_DEPTH), line:41
|vpiName:L2_DATA_ATTRIBUTES_FIFO_DEPTH
|INT:16
|vpiParameter:
\_parameter: (L2_ID_W), line:46
|vpiName:L2_ID_W
|INT:3
|vpiParameter:
\_parameter: (L2_INPUT_FIFO_DEPTHS), line:34
|vpiName:L2_INPUT_FIFO_DEPTHS
|INT:4
|vpiParameter:
\_parameter: (L2_INVALIDATION_FIFO_DEPTHS), line:35
|vpiName:L2_INVALIDATION_FIFO_DEPTHS
|INT:4
|vpiParameter:
\_parameter: (L2_MEM_ADDR_FIFO_DEPTH), line:39
|vpiName:L2_MEM_ADDR_FIFO_DEPTH
|INT:8
|vpiParameter:
\_parameter: (L2_NUM_PORTS), line:26
|vpiName:L2_NUM_PORTS
|INT:2
|vpiParameter:
\_parameter: (L2_READ_RETURN_FIFO_DEPTHS), line:36
|vpiName:L2_READ_RETURN_FIFO_DEPTHS
|INT:1
|vpiParameter:
\_parameter: (L2_SUB_ID_W), line:27
|vpiName:L2_SUB_ID_W
|INT:2
|vpiParameter:
\_parameter: (LS_UNIT_WB_ID), line:191
|vpiName:LS_UNIT_WB_ID
|INT:1
|vpiParameter:
\_parameter: (MAX_INFLIGHT_COUNT), line:167
|vpiName:MAX_INFLIGHT_COUNT
|INT:19
|vpiParameter:
\_parameter: (MEMORY_ADDR_H), line:103
|vpiName:MEMORY_ADDR_H
|INT:12
|vpiParameter:
\_parameter: (MEMORY_ADDR_L), line:102
|vpiName:MEMORY_ADDR_L
|INT:11
|vpiParameter:
\_parameter: (MEMORY_BIT_CHECK), line:104
|vpiName:MEMORY_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (MUL_UNIT_WB_ID), line:193
|vpiName:MUL_UNIT_WB_ID
|INT:512
|vpiParameter:
\_parameter: (NUM_UNITS), line:188
|vpiName:NUM_UNITS
|INT:2
|vpiParameter:
\_parameter: (NUM_WB_UNITS), line:186
|vpiName:NUM_WB_UNITS
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (RAS_DEPTH), line:161
|vpiName:RAS_DEPTH
|INT:2
|vpiParameter:
\_parameter: (RESET_VEC), line:39
|vpiName:RESET_VEC
|INT:-2147483648
|vpiParameter:
\_parameter: (SCRATCH_ADDR_H), line:99
|vpiName:SCRATCH_ADDR_H
|INT:9
|vpiParameter:
\_parameter: (SCRATCH_ADDR_L), line:98
|vpiName:SCRATCH_ADDR_L
|INT:8
|vpiParameter:
\_parameter: (SCRATCH_BIT_CHECK), line:100
|vpiName:SCRATCH_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (USE_AMO), line:70
|vpiName:USE_AMO
|INT:1
|vpiParameter:
\_parameter: (USE_BRANCH_PREDICTOR), line:158
|vpiName:USE_BRANCH_PREDICTOR
|INT:2
|vpiParameter:
\_parameter: (USE_BUS), line:88
|vpiName:USE_BUS
|INT:4
|vpiParameter:
\_parameter: (USE_DCACHE), line:92
|vpiName:USE_DCACHE
|INT:6
|vpiParameter:
\_parameter: (USE_DIV), line:49
|vpiName:USE_DIV
|INT:1
|vpiParameter:
\_parameter: (USE_DTAG_INVALIDATIONS), line:140
|vpiName:USE_DTAG_INVALIDATIONS
|INT:1879048191
|vpiParameter:
\_parameter: (USE_D_SCRATCH_MEM), line:79
|vpiName:USE_D_SCRATCH_MEM
|INT:3
|vpiParameter:
\_parameter: (USE_ICACHE), line:93
|vpiName:USE_ICACHE
|INT:7
|vpiParameter:
\_parameter: (USE_I_SCRATCH_MEM), line:78
|vpiName:USE_I_SCRATCH_MEM
|INT:2
|vpiParameter:
\_parameter: (USE_MUL), line:48
|vpiName:USE_MUL
|INT:1
|vpiParameter:
\_parameter: (WB_UNITS_WIDTH), line:187
|vpiName:WB_UNITS_WIDTH
|INT:32
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiGenScopeArray:
\_gen_scope_array: (genblk4), line:98, parent:arb
|vpiName:genblk4
|vpiFullName:work@taiga_wrapper.cpu.genblk1.arb.genblk4
|vpiGenScope:
\_gen_scope: , parent:genblk4
|vpiFullName:work@taiga_wrapper.cpu.genblk1.arb.genblk4
|vpiContAssign:
\_cont_assign: , line:99
|vpiRhs:
\_ref_obj: (l2.inv_addr), line:99
|vpiName:l2.inv_addr
|vpiFullName:work@taiga_wrapper.cpu.genblk1.arb.genblk4.l2.inv_addr
|vpiLhs:
\_ref_obj: (l1_response[L1_DCACHE_ID].inv_addr), line:99
|vpiName:l1_response[L1_DCACHE_ID].inv_addr
|vpiFullName:work@taiga_wrapper.cpu.genblk1.arb.genblk4.l1_response[L1_DCACHE_ID].inv_addr
|vpiContAssign:
\_cont_assign: , line:100
|vpiRhs:
\_ref_obj: (l2.inv_valid), line:100
|vpiName:l2.inv_valid
|vpiFullName:work@taiga_wrapper.cpu.genblk1.arb.genblk4.l2.inv_valid
|vpiLhs:
\_ref_obj: (l1_response[L1_DCACHE_ID].inv_valid), line:100
|vpiName:l1_response[L1_DCACHE_ID].inv_valid
|vpiFullName:work@taiga_wrapper.cpu.genblk1.arb.genblk4.l1_response[L1_DCACHE_ID].inv_valid
|vpiContAssign:
\_cont_assign: , line:103
|vpiRhs:
\_constant: , line:103
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiLhs:
\_ref_obj: (l1_response[L1_DCACHE_ID].inv_addr), line:103
|vpiName:l1_response[L1_DCACHE_ID].inv_addr
|vpiFullName:work@taiga_wrapper.cpu.genblk1.arb.genblk4.l1_response[L1_DCACHE_ID].inv_addr
|vpiContAssign:
\_cont_assign: , line:104
|vpiRhs:
\_constant: , line:104
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiLhs:
\_ref_obj: (l1_response[L1_DCACHE_ID].inv_valid), line:104
|vpiName:l1_response[L1_DCACHE_ID].inv_valid
|vpiFullName:work@taiga_wrapper.cpu.genblk1.arb.genblk4.l1_response[L1_DCACHE_ID].inv_valid
|vpiParameter:
\_parameter: (ALU_UNIT_WB_ID), line:190
|vpiName:ALU_UNIT_WB_ID
|INT:32
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (BRANCH_PREDICTOR_WAYS), line:159
|vpiName:BRANCH_PREDICTOR_WAYS
|INT:9
|vpiParameter:
\_parameter: (BRANCH_TABLE_ENTRIES), line:160
|vpiName:BRANCH_TABLE_ENTRIES
|INT:4
|vpiParameter:
\_parameter: (BRANCH_UNIT_ID), line:195
|vpiName:BRANCH_UNIT_ID
|INT:8
|vpiParameter:
\_parameter: (BUS_ADDR_H), line:107
|vpiName:BUS_ADDR_H
|INT:1
|vpiParameter:
\_parameter: (BUS_ADDR_L), line:106
|vpiName:BUS_ADDR_L
|INT:0
|vpiParameter:
\_parameter: (BUS_BIT_CHECK), line:108
|vpiName:BUS_BIT_CHECK
|INT:1
|vpiParameter:
\_parameter: (BUS_TYPE), line:89
|vpiName:BUS_TYPE
|INT:5
|vpiParameter:
\_parameter: (COUNTER_W), line:42
|vpiName:COUNTER_W
|INT:33
|vpiParameter:
\_parameter: (CPU_ID), line:38
|vpiName:CPU_ID
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_ADDR_WIDTH), line:113
|vpiName:C_M_AXI_ADDR_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_DATA_WIDTH), line:114
|vpiName:C_M_AXI_DATA_WIDTH
|INT:1
|vpiParameter:
\_parameter: (DCACHE_LINES), line:133
|vpiName:DCACHE_LINES
|INT:-2146435073
|vpiParameter:
\_parameter: (DCACHE_LINE_ADDR_W), line:135
|vpiName:DCACHE_LINE_ADDR_W
|INT:1073741824
|vpiParameter:
\_parameter: (DCACHE_LINE_W), line:136
|vpiName:DCACHE_LINE_W
|INT:1342177279
|vpiParameter:
\_parameter: (DCACHE_SUB_LINE_ADDR_W), line:137
|vpiName:DCACHE_SUB_LINE_ADDR_W
|INT:4
|vpiParameter:
\_parameter: (DCACHE_TAG_W), line:138
|vpiName:DCACHE_TAG_W
|INT:1610612736
|vpiParameter:
\_parameter: (DCACHE_WAYS), line:134
|vpiName:DCACHE_WAYS
|INT:4
|vpiParameter:
\_parameter: (DIV_ALGORITHM), line:67
|vpiName:DIV_ALGORITHM
|INT:0
|vpiParameter:
\_parameter: (DIV_UNIT_WB_ID), line:192
|vpiName:DIV_UNIT_WB_ID
|INT:2
|vpiParameter:
\_parameter: (DTLB_DEPTH), line:152
|vpiName:DTLB_DEPTH
|INT:512
|vpiParameter:
\_parameter: (DTLB_WAYS), line:151
|vpiName:DTLB_WAYS
|INT:32
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (ENABLE_M_MODE), line:34
|vpiName:ENABLE_M_MODE
|INT:1
|vpiParameter:
\_parameter: (ENABLE_S_MODE), line:36
|vpiName:ENABLE_S_MODE
|INT:0
|vpiParameter:
\_parameter: (ENABLE_TRACE_INTERFACE), line:172
|vpiName:ENABLE_TRACE_INTERFACE
|INT:2
|vpiParameter:
\_parameter: (FETCH_BUFFER_DEPTH), line:168
|vpiName:FETCH_BUFFER_DEPTH
|INT:512
|vpiParameter:
\_parameter: (FPGA_VENDOR), line:27
|vpiName:FPGA_VENDOR
|STRING:"xilinx"
|vpiParameter:
\_parameter: (GC_UNIT_ID), line:196
|vpiName:GC_UNIT_ID
|INT:4
|vpiParameter:
\_parameter: (ICACHE_LINES), line:121
|vpiName:ICACHE_LINES
|INT:2
|vpiParameter:
\_parameter: (ICACHE_LINE_ADDR_W), line:123
|vpiName:ICACHE_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_LINE_W), line:124
|vpiName:ICACHE_LINE_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_SUB_LINE_ADDR_W), line:125
|vpiName:ICACHE_SUB_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_TAG_W), line:126
|vpiName:ICACHE_TAG_W
|INT:-2147483648
|vpiParameter:
\_parameter: (ICACHE_WAYS), line:122
|vpiName:ICACHE_WAYS
|INT:1
|vpiParameter:
\_parameter: (ITLB_DEPTH), line:146
|vpiName:ITLB_DEPTH
|INT:32
|vpiParameter:
\_parameter: (ITLB_WAYS), line:145
|vpiName:ITLB_WAYS
|INT:4
|vpiParameter:
\_parameter: (L1_CONNECTIONS), line:177
|vpiName:L1_CONNECTIONS
|INT:9
|vpiParameter:
\_parameter: (L1_DCACHE_ID), line:178
|vpiName:L1_DCACHE_ID
|INT:4
|vpiParameter:
\_parameter: (L1_DMMU_ID), line:179
|vpiName:L1_DMMU_ID
|INT:2
|vpiParameter:
\_parameter: (L1_ICACHE_ID), line:180
|vpiName:L1_ICACHE_ID
|INT:19
|vpiParameter:
\_parameter: (L1_IMMU_ID), line:181
|vpiName:L1_IMMU_ID
|INT:0
|vpiParameter:
\_parameter: (L2_DATA_ATTRIBUTES_FIFO_DEPTH), line:41
|vpiName:L2_DATA_ATTRIBUTES_FIFO_DEPTH
|INT:16
|vpiParameter:
\_parameter: (L2_ID_W), line:46
|vpiName:L2_ID_W
|INT:3
|vpiParameter:
\_parameter: (L2_INPUT_FIFO_DEPTHS), line:34
|vpiName:L2_INPUT_FIFO_DEPTHS
|INT:4
|vpiParameter:
\_parameter: (L2_INVALIDATION_FIFO_DEPTHS), line:35
|vpiName:L2_INVALIDATION_FIFO_DEPTHS
|INT:4
|vpiParameter:
\_parameter: (L2_MEM_ADDR_FIFO_DEPTH), line:39
|vpiName:L2_MEM_ADDR_FIFO_DEPTH
|INT:8
|vpiParameter:
\_parameter: (L2_NUM_PORTS), line:26
|vpiName:L2_NUM_PORTS
|INT:2
|vpiParameter:
\_parameter: (L2_READ_RETURN_FIFO_DEPTHS), line:36
|vpiName:L2_READ_RETURN_FIFO_DEPTHS
|INT:1
|vpiParameter:
\_parameter: (L2_SUB_ID_W), line:27
|vpiName:L2_SUB_ID_W
|INT:2
|vpiParameter:
\_parameter: (LS_UNIT_WB_ID), line:191
|vpiName:LS_UNIT_WB_ID
|INT:1
|vpiParameter:
\_parameter: (MAX_INFLIGHT_COUNT), line:167
|vpiName:MAX_INFLIGHT_COUNT
|INT:19
|vpiParameter:
\_parameter: (MEMORY_ADDR_H), line:103
|vpiName:MEMORY_ADDR_H
|INT:12
|vpiParameter:
\_parameter: (MEMORY_ADDR_L), line:102
|vpiName:MEMORY_ADDR_L
|INT:11
|vpiParameter:
\_parameter: (MEMORY_BIT_CHECK), line:104
|vpiName:MEMORY_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (MUL_UNIT_WB_ID), line:193
|vpiName:MUL_UNIT_WB_ID
|INT:512
|vpiParameter:
\_parameter: (NUM_UNITS), line:188
|vpiName:NUM_UNITS
|INT:2
|vpiParameter:
\_parameter: (NUM_WB_UNITS), line:186
|vpiName:NUM_WB_UNITS
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (RAS_DEPTH), line:161
|vpiName:RAS_DEPTH
|INT:2
|vpiParameter:
\_parameter: (RESET_VEC), line:39
|vpiName:RESET_VEC
|INT:-2147483648
|vpiParameter:
\_parameter: (SCRATCH_ADDR_H), line:99
|vpiName:SCRATCH_ADDR_H
|INT:9
|vpiParameter:
\_parameter: (SCRATCH_ADDR_L), line:98
|vpiName:SCRATCH_ADDR_L
|INT:8
|vpiParameter:
\_parameter: (SCRATCH_BIT_CHECK), line:100
|vpiName:SCRATCH_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (USE_AMO), line:70
|vpiName:USE_AMO
|INT:1
|vpiParameter:
\_parameter: (USE_BRANCH_PREDICTOR), line:158
|vpiName:USE_BRANCH_PREDICTOR
|INT:2
|vpiParameter:
\_parameter: (USE_BUS), line:88
|vpiName:USE_BUS
|INT:4
|vpiParameter:
\_parameter: (USE_DCACHE), line:92
|vpiName:USE_DCACHE
|INT:6
|vpiParameter:
\_parameter: (USE_DIV), line:49
|vpiName:USE_DIV
|INT:1
|vpiParameter:
\_parameter: (USE_DTAG_INVALIDATIONS), line:140
|vpiName:USE_DTAG_INVALIDATIONS
|INT:1879048191
|vpiParameter:
\_parameter: (USE_D_SCRATCH_MEM), line:79
|vpiName:USE_D_SCRATCH_MEM
|INT:3
|vpiParameter:
\_parameter: (USE_ICACHE), line:93
|vpiName:USE_ICACHE
|INT:7
|vpiParameter:
\_parameter: (USE_I_SCRATCH_MEM), line:78
|vpiName:USE_I_SCRATCH_MEM
|INT:2
|vpiParameter:
\_parameter: (USE_MUL), line:48
|vpiName:USE_MUL
|INT:1
|vpiParameter:
\_parameter: (WB_UNITS_WIDTH), line:187
|vpiName:WB_UNITS_WIDTH
|INT:32
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiGenScopeArray:
\_gen_scope_array: (genblk5), line:108, parent:arb
|vpiName:genblk5
|vpiFullName:work@taiga_wrapper.cpu.genblk1.arb.genblk5
|vpiGenScope:
\_gen_scope: , parent:genblk5
|vpiFullName:work@taiga_wrapper.cpu.genblk1.arb.genblk5
|vpiProcess:
\_always: , line:109
|vpiAlwaysType:2
|vpiStmt:
\_begin: , line:109
|vpiFullName:work@taiga_wrapper.cpu.genblk1.arb.genblk5
|vpiStmt:
\_assignment: , line:110
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (l2_requests[L1_DCACHE_ID].addr), line:110
|vpiName:l2_requests[L1_DCACHE_ID].addr
|vpiFullName:work@taiga_wrapper.cpu.genblk1.arb.genblk5.l2_requests[L1_DCACHE_ID].addr
|vpiRhs:
\_bit_select: (l1_request.addr), line:110
|vpiName:l1_request.addr
|vpiFullName:work@taiga_wrapper.cpu.genblk1.arb.genblk5.l1_request.addr
|vpiIndex:
\_ref_obj: (L1_DCACHE_ID), line:110
|vpiName:L1_DCACHE_ID
|vpiStmt:
\_assignment: , line:111
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (l2_requests[L1_DCACHE_ID].rnw), line:111
|vpiName:l2_requests[L1_DCACHE_ID].rnw
|vpiFullName:work@taiga_wrapper.cpu.genblk1.arb.genblk5.l2_requests[L1_DCACHE_ID].rnw
|vpiRhs:
\_bit_select: (l1_request.rnw), line:111
|vpiName:l1_request.rnw
|vpiFullName:work@taiga_wrapper.cpu.genblk1.arb.genblk5.l1_request.rnw
|vpiIndex:
\_ref_obj: (L1_DCACHE_ID), line:111
|vpiName:L1_DCACHE_ID
|vpiStmt:
\_assignment: , line:112
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (l2_requests[L1_DCACHE_ID].be), line:112
|vpiName:l2_requests[L1_DCACHE_ID].be
|vpiFullName:work@taiga_wrapper.cpu.genblk1.arb.genblk5.l2_requests[L1_DCACHE_ID].be
|vpiRhs:
\_bit_select: (l1_request.be), line:112
|vpiName:l1_request.be
|vpiFullName:work@taiga_wrapper.cpu.genblk1.arb.genblk5.l1_request.be
|vpiIndex:
\_ref_obj: (L1_DCACHE_ID), line:112
|vpiName:L1_DCACHE_ID
|vpiStmt:
\_assignment: , line:113
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (l2_requests[L1_DCACHE_ID].is_amo), line:113
|vpiName:l2_requests[L1_DCACHE_ID].is_amo
|vpiFullName:work@taiga_wrapper.cpu.genblk1.arb.genblk5.l2_requests[L1_DCACHE_ID].is_amo
|vpiRhs:
\_bit_select: (l1_request.is_amo), line:113
|vpiName:l1_request.is_amo
|vpiFullName:work@taiga_wrapper.cpu.genblk1.arb.genblk5.l1_request.is_amo
|vpiIndex:
\_ref_obj: (L1_DCACHE_ID), line:113
|vpiName:L1_DCACHE_ID
|vpiStmt:
\_assignment: , line:114
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (l2_requests[L1_DCACHE_ID].amo_type_or_burst_size), line:114
|vpiName:l2_requests[L1_DCACHE_ID].amo_type_or_burst_size
|vpiFullName:work@taiga_wrapper.cpu.genblk1.arb.genblk5.l2_requests[L1_DCACHE_ID].amo_type_or_burst_size
|vpiRhs:
\_operation: , line:114
|vpiOpType:32
|vpiOperand:
\_bit_select: (l1_request.is_amo), line:114
|vpiName:l1_request.is_amo
|vpiFullName:work@taiga_wrapper.cpu.genblk1.arb.genblk5.l1_request.is_amo
|vpiIndex:
\_ref_obj: (L1_DCACHE_ID), line:114
|vpiName:L1_DCACHE_ID
|vpiOperand:
\_bit_select: (l1_request.amo), line:114
|vpiName:l1_request.amo
|vpiFullName:work@taiga_wrapper.cpu.genblk1.arb.genblk5.l1_request.amo
|vpiIndex:
\_ref_obj: (L1_DCACHE_ID), line:114
|vpiName:L1_DCACHE_ID
|vpiFullName:work@taiga_wrapper.cpu.genblk1.arb.genblk5.L1_DCACHE_ID
|vpiOperand:
\_bit_select: (l1_request.size), line:114
|vpiName:l1_request.size
|vpiFullName:work@taiga_wrapper.cpu.genblk1.arb.genblk5.l1_request.size
|vpiIndex:
\_ref_obj: (L1_DCACHE_ID), line:114
|vpiName:L1_DCACHE_ID
|vpiFullName:work@taiga_wrapper.cpu.genblk1.arb.genblk5.L1_DCACHE_ID
|vpiStmt:
\_assignment: , line:115
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (l2_requests[L1_DCACHE_ID].sub_id), line:115
|vpiName:l2_requests[L1_DCACHE_ID].sub_id
|vpiFullName:work@taiga_wrapper.cpu.genblk1.arb.genblk5.l2_requests[L1_DCACHE_ID].sub_id
|vpiRhs:
\_ref_obj: (L1_DCACHE_ID), line:115
|vpiName:L1_DCACHE_ID
|vpiFullName:work@taiga_wrapper.cpu.genblk1.arb.genblk5.L1_DCACHE_ID
|vpiParameter:
\_parameter: (ALU_UNIT_WB_ID), line:190
|vpiName:ALU_UNIT_WB_ID
|INT:32
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (BRANCH_PREDICTOR_WAYS), line:159
|vpiName:BRANCH_PREDICTOR_WAYS
|INT:9
|vpiParameter:
\_parameter: (BRANCH_TABLE_ENTRIES), line:160
|vpiName:BRANCH_TABLE_ENTRIES
|INT:4
|vpiParameter:
\_parameter: (BRANCH_UNIT_ID), line:195
|vpiName:BRANCH_UNIT_ID
|INT:8
|vpiParameter:
\_parameter: (BUS_ADDR_H), line:107
|vpiName:BUS_ADDR_H
|INT:1
|vpiParameter:
\_parameter: (BUS_ADDR_L), line:106
|vpiName:BUS_ADDR_L
|INT:0
|vpiParameter:
\_parameter: (BUS_BIT_CHECK), line:108
|vpiName:BUS_BIT_CHECK
|INT:1
|vpiParameter:
\_parameter: (BUS_TYPE), line:89
|vpiName:BUS_TYPE
|INT:5
|vpiParameter:
\_parameter: (COUNTER_W), line:42
|vpiName:COUNTER_W
|INT:33
|vpiParameter:
\_parameter: (CPU_ID), line:38
|vpiName:CPU_ID
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_ADDR_WIDTH), line:113
|vpiName:C_M_AXI_ADDR_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_DATA_WIDTH), line:114
|vpiName:C_M_AXI_DATA_WIDTH
|INT:1
|vpiParameter:
\_parameter: (DCACHE_LINES), line:133
|vpiName:DCACHE_LINES
|INT:-2146435073
|vpiParameter:
\_parameter: (DCACHE_LINE_ADDR_W), line:135
|vpiName:DCACHE_LINE_ADDR_W
|INT:1073741824
|vpiParameter:
\_parameter: (DCACHE_LINE_W), line:136
|vpiName:DCACHE_LINE_W
|INT:1342177279
|vpiParameter:
\_parameter: (DCACHE_SUB_LINE_ADDR_W), line:137
|vpiName:DCACHE_SUB_LINE_ADDR_W
|INT:4
|vpiParameter:
\_parameter: (DCACHE_TAG_W), line:138
|vpiName:DCACHE_TAG_W
|INT:1610612736
|vpiParameter:
\_parameter: (DCACHE_WAYS), line:134
|vpiName:DCACHE_WAYS
|INT:4
|vpiParameter:
\_parameter: (DIV_ALGORITHM), line:67
|vpiName:DIV_ALGORITHM
|INT:0
|vpiParameter:
\_parameter: (DIV_UNIT_WB_ID), line:192
|vpiName:DIV_UNIT_WB_ID
|INT:2
|vpiParameter:
\_parameter: (DTLB_DEPTH), line:152
|vpiName:DTLB_DEPTH
|INT:512
|vpiParameter:
\_parameter: (DTLB_WAYS), line:151
|vpiName:DTLB_WAYS
|INT:32
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (ENABLE_M_MODE), line:34
|vpiName:ENABLE_M_MODE
|INT:1
|vpiParameter:
\_parameter: (ENABLE_S_MODE), line:36
|vpiName:ENABLE_S_MODE
|INT:0
|vpiParameter:
\_parameter: (ENABLE_TRACE_INTERFACE), line:172
|vpiName:ENABLE_TRACE_INTERFACE
|INT:2
|vpiParameter:
\_parameter: (FETCH_BUFFER_DEPTH), line:168
|vpiName:FETCH_BUFFER_DEPTH
|INT:512
|vpiParameter:
\_parameter: (FPGA_VENDOR), line:27
|vpiName:FPGA_VENDOR
|STRING:"xilinx"
|vpiParameter:
\_parameter: (GC_UNIT_ID), line:196
|vpiName:GC_UNIT_ID
|INT:4
|vpiParameter:
\_parameter: (ICACHE_LINES), line:121
|vpiName:ICACHE_LINES
|INT:2
|vpiParameter:
\_parameter: (ICACHE_LINE_ADDR_W), line:123
|vpiName:ICACHE_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_LINE_W), line:124
|vpiName:ICACHE_LINE_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_SUB_LINE_ADDR_W), line:125
|vpiName:ICACHE_SUB_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_TAG_W), line:126
|vpiName:ICACHE_TAG_W
|INT:-2147483648
|vpiParameter:
\_parameter: (ICACHE_WAYS), line:122
|vpiName:ICACHE_WAYS
|INT:1
|vpiParameter:
\_parameter: (ITLB_DEPTH), line:146
|vpiName:ITLB_DEPTH
|INT:32
|vpiParameter:
\_parameter: (ITLB_WAYS), line:145
|vpiName:ITLB_WAYS
|INT:4
|vpiParameter:
\_parameter: (L1_CONNECTIONS), line:177
|vpiName:L1_CONNECTIONS
|INT:9
|vpiParameter:
\_parameter: (L1_DCACHE_ID), line:178
|vpiName:L1_DCACHE_ID
|INT:4
|vpiParameter:
\_parameter: (L1_DMMU_ID), line:179
|vpiName:L1_DMMU_ID
|INT:2
|vpiParameter:
\_parameter: (L1_ICACHE_ID), line:180
|vpiName:L1_ICACHE_ID
|INT:19
|vpiParameter:
\_parameter: (L1_IMMU_ID), line:181
|vpiName:L1_IMMU_ID
|INT:0
|vpiParameter:
\_parameter: (L2_DATA_ATTRIBUTES_FIFO_DEPTH), line:41
|vpiName:L2_DATA_ATTRIBUTES_FIFO_DEPTH
|INT:16
|vpiParameter:
\_parameter: (L2_ID_W), line:46
|vpiName:L2_ID_W
|INT:3
|vpiParameter:
\_parameter: (L2_INPUT_FIFO_DEPTHS), line:34
|vpiName:L2_INPUT_FIFO_DEPTHS
|INT:4
|vpiParameter:
\_parameter: (L2_INVALIDATION_FIFO_DEPTHS), line:35
|vpiName:L2_INVALIDATION_FIFO_DEPTHS
|INT:4
|vpiParameter:
\_parameter: (L2_MEM_ADDR_FIFO_DEPTH), line:39
|vpiName:L2_MEM_ADDR_FIFO_DEPTH
|INT:8
|vpiParameter:
\_parameter: (L2_NUM_PORTS), line:26
|vpiName:L2_NUM_PORTS
|INT:2
|vpiParameter:
\_parameter: (L2_READ_RETURN_FIFO_DEPTHS), line:36
|vpiName:L2_READ_RETURN_FIFO_DEPTHS
|INT:1
|vpiParameter:
\_parameter: (L2_SUB_ID_W), line:27
|vpiName:L2_SUB_ID_W
|INT:2
|vpiParameter:
\_parameter: (LS_UNIT_WB_ID), line:191
|vpiName:LS_UNIT_WB_ID
|INT:1
|vpiParameter:
\_parameter: (MAX_INFLIGHT_COUNT), line:167
|vpiName:MAX_INFLIGHT_COUNT
|INT:19
|vpiParameter:
\_parameter: (MEMORY_ADDR_H), line:103
|vpiName:MEMORY_ADDR_H
|INT:12
|vpiParameter:
\_parameter: (MEMORY_ADDR_L), line:102
|vpiName:MEMORY_ADDR_L
|INT:11
|vpiParameter:
\_parameter: (MEMORY_BIT_CHECK), line:104
|vpiName:MEMORY_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (MUL_UNIT_WB_ID), line:193
|vpiName:MUL_UNIT_WB_ID
|INT:512
|vpiParameter:
\_parameter: (NUM_UNITS), line:188
|vpiName:NUM_UNITS
|INT:2
|vpiParameter:
\_parameter: (NUM_WB_UNITS), line:186
|vpiName:NUM_WB_UNITS
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (RAS_DEPTH), line:161
|vpiName:RAS_DEPTH
|INT:2
|vpiParameter:
\_parameter: (RESET_VEC), line:39
|vpiName:RESET_VEC
|INT:-2147483648
|vpiParameter:
\_parameter: (SCRATCH_ADDR_H), line:99
|vpiName:SCRATCH_ADDR_H
|INT:9
|vpiParameter:
\_parameter: (SCRATCH_ADDR_L), line:98
|vpiName:SCRATCH_ADDR_L
|INT:8
|vpiParameter:
\_parameter: (SCRATCH_BIT_CHECK), line:100
|vpiName:SCRATCH_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (USE_AMO), line:70
|vpiName:USE_AMO
|INT:1
|vpiParameter:
\_parameter: (USE_BRANCH_PREDICTOR), line:158
|vpiName:USE_BRANCH_PREDICTOR
|INT:2
|vpiParameter:
\_parameter: (USE_BUS), line:88
|vpiName:USE_BUS
|INT:4
|vpiParameter:
\_parameter: (USE_DCACHE), line:92
|vpiName:USE_DCACHE
|INT:6
|vpiParameter:
\_parameter: (USE_DIV), line:49
|vpiName:USE_DIV
|INT:1
|vpiParameter:
\_parameter: (USE_DTAG_INVALIDATIONS), line:140
|vpiName:USE_DTAG_INVALIDATIONS
|INT:1879048191
|vpiParameter:
\_parameter: (USE_D_SCRATCH_MEM), line:79
|vpiName:USE_D_SCRATCH_MEM
|INT:3
|vpiParameter:
\_parameter: (USE_ICACHE), line:93
|vpiName:USE_ICACHE
|INT:7
|vpiParameter:
\_parameter: (USE_I_SCRATCH_MEM), line:78
|vpiName:USE_I_SCRATCH_MEM
|INT:2
|vpiParameter:
\_parameter: (USE_MUL), line:48
|vpiName:USE_MUL
|INT:1
|vpiParameter:
\_parameter: (WB_UNITS_WIDTH), line:187
|vpiName:WB_UNITS_WIDTH
|INT:32
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiGenScopeArray:
\_gen_scope_array: (genblk6), line:120, parent:arb
|vpiName:genblk6
|vpiFullName:work@taiga_wrapper.cpu.genblk1.arb.genblk6
|vpiGenScope:
\_gen_scope: , parent:genblk6
|vpiFullName:work@taiga_wrapper.cpu.genblk1.arb.genblk6
|vpiProcess:
\_always: , line:121
|vpiAlwaysType:2
|vpiStmt:
\_begin: , line:121
|vpiFullName:work@taiga_wrapper.cpu.genblk1.arb.genblk6
|vpiStmt:
\_assignment: , line:122
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (l2_requests[L1_ICACHE_ID].addr), line:122
|vpiName:l2_requests[L1_ICACHE_ID].addr
|vpiFullName:work@taiga_wrapper.cpu.genblk1.arb.genblk6.l2_requests[L1_ICACHE_ID].addr
|vpiRhs:
\_bit_select: (l1_request.addr), line:122
|vpiName:l1_request.addr
|vpiFullName:work@taiga_wrapper.cpu.genblk1.arb.genblk6.l1_request.addr
|vpiIndex:
\_ref_obj: (L1_ICACHE_ID), line:122
|vpiName:L1_ICACHE_ID
|vpiStmt:
\_assignment: , line:123
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (l2_requests[L1_ICACHE_ID].rnw), line:123
|vpiName:l2_requests[L1_ICACHE_ID].rnw
|vpiFullName:work@taiga_wrapper.cpu.genblk1.arb.genblk6.l2_requests[L1_ICACHE_ID].rnw
|vpiRhs:
\_bit_select: (l1_request.rnw), line:123
|vpiName:l1_request.rnw
|vpiFullName:work@taiga_wrapper.cpu.genblk1.arb.genblk6.l1_request.rnw
|vpiIndex:
\_ref_obj: (L1_ICACHE_ID), line:123
|vpiName:L1_ICACHE_ID
|vpiStmt:
\_assignment: , line:124
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (l2_requests[L1_ICACHE_ID].be), line:124
|vpiName:l2_requests[L1_ICACHE_ID].be
|vpiFullName:work@taiga_wrapper.cpu.genblk1.arb.genblk6.l2_requests[L1_ICACHE_ID].be
|vpiRhs:
\_bit_select: (l1_request.be), line:124
|vpiName:l1_request.be
|vpiFullName:work@taiga_wrapper.cpu.genblk1.arb.genblk6.l1_request.be
|vpiIndex:
\_ref_obj: (L1_ICACHE_ID), line:124
|vpiName:L1_ICACHE_ID
|vpiStmt:
\_assignment: , line:125
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (l2_requests[L1_ICACHE_ID].is_amo), line:125
|vpiName:l2_requests[L1_ICACHE_ID].is_amo
|vpiFullName:work@taiga_wrapper.cpu.genblk1.arb.genblk6.l2_requests[L1_ICACHE_ID].is_amo
|vpiRhs:
\_bit_select: (l1_request.is_amo), line:125
|vpiName:l1_request.is_amo
|vpiFullName:work@taiga_wrapper.cpu.genblk1.arb.genblk6.l1_request.is_amo
|vpiIndex:
\_ref_obj: (L1_ICACHE_ID), line:125
|vpiName:L1_ICACHE_ID
|vpiStmt:
\_assignment: , line:126
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (l2_requests[L1_ICACHE_ID].amo_type_or_burst_size), line:126
|vpiName:l2_requests[L1_ICACHE_ID].amo_type_or_burst_size
|vpiFullName:work@taiga_wrapper.cpu.genblk1.arb.genblk6.l2_requests[L1_ICACHE_ID].amo_type_or_burst_size
|vpiRhs:
\_bit_select: (l1_request.size), line:126
|vpiName:l1_request.size
|vpiFullName:work@taiga_wrapper.cpu.genblk1.arb.genblk6.l1_request.size
|vpiIndex:
\_ref_obj: (L1_ICACHE_ID), line:126
|vpiName:L1_ICACHE_ID
|vpiStmt:
\_assignment: , line:127
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (l2_requests[L1_ICACHE_ID].sub_id), line:127
|vpiName:l2_requests[L1_ICACHE_ID].sub_id
|vpiFullName:work@taiga_wrapper.cpu.genblk1.arb.genblk6.l2_requests[L1_ICACHE_ID].sub_id
|vpiRhs:
\_ref_obj: (L1_ICACHE_ID), line:127
|vpiName:L1_ICACHE_ID
|vpiFullName:work@taiga_wrapper.cpu.genblk1.arb.genblk6.L1_ICACHE_ID
|vpiParameter:
\_parameter: (ALU_UNIT_WB_ID), line:190
|vpiName:ALU_UNIT_WB_ID
|INT:32
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (BRANCH_PREDICTOR_WAYS), line:159
|vpiName:BRANCH_PREDICTOR_WAYS
|INT:9
|vpiParameter:
\_parameter: (BRANCH_TABLE_ENTRIES), line:160
|vpiName:BRANCH_TABLE_ENTRIES
|INT:4
|vpiParameter:
\_parameter: (BRANCH_UNIT_ID), line:195
|vpiName:BRANCH_UNIT_ID
|INT:8
|vpiParameter:
\_parameter: (BUS_ADDR_H), line:107
|vpiName:BUS_ADDR_H
|INT:1
|vpiParameter:
\_parameter: (BUS_ADDR_L), line:106
|vpiName:BUS_ADDR_L
|INT:0
|vpiParameter:
\_parameter: (BUS_BIT_CHECK), line:108
|vpiName:BUS_BIT_CHECK
|INT:1
|vpiParameter:
\_parameter: (BUS_TYPE), line:89
|vpiName:BUS_TYPE
|INT:5
|vpiParameter:
\_parameter: (COUNTER_W), line:42
|vpiName:COUNTER_W
|INT:33
|vpiParameter:
\_parameter: (CPU_ID), line:38
|vpiName:CPU_ID
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_ADDR_WIDTH), line:113
|vpiName:C_M_AXI_ADDR_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_DATA_WIDTH), line:114
|vpiName:C_M_AXI_DATA_WIDTH
|INT:1
|vpiParameter:
\_parameter: (DCACHE_LINES), line:133
|vpiName:DCACHE_LINES
|INT:-2146435073
|vpiParameter:
\_parameter: (DCACHE_LINE_ADDR_W), line:135
|vpiName:DCACHE_LINE_ADDR_W
|INT:1073741824
|vpiParameter:
\_parameter: (DCACHE_LINE_W), line:136
|vpiName:DCACHE_LINE_W
|INT:1342177279
|vpiParameter:
\_parameter: (DCACHE_SUB_LINE_ADDR_W), line:137
|vpiName:DCACHE_SUB_LINE_ADDR_W
|INT:4
|vpiParameter:
\_parameter: (DCACHE_TAG_W), line:138
|vpiName:DCACHE_TAG_W
|INT:1610612736
|vpiParameter:
\_parameter: (DCACHE_WAYS), line:134
|vpiName:DCACHE_WAYS
|INT:4
|vpiParameter:
\_parameter: (DIV_ALGORITHM), line:67
|vpiName:DIV_ALGORITHM
|INT:0
|vpiParameter:
\_parameter: (DIV_UNIT_WB_ID), line:192
|vpiName:DIV_UNIT_WB_ID
|INT:2
|vpiParameter:
\_parameter: (DTLB_DEPTH), line:152
|vpiName:DTLB_DEPTH
|INT:512
|vpiParameter:
\_parameter: (DTLB_WAYS), line:151
|vpiName:DTLB_WAYS
|INT:32
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (ENABLE_M_MODE), line:34
|vpiName:ENABLE_M_MODE
|INT:1
|vpiParameter:
\_parameter: (ENABLE_S_MODE), line:36
|vpiName:ENABLE_S_MODE
|INT:0
|vpiParameter:
\_parameter: (ENABLE_TRACE_INTERFACE), line:172
|vpiName:ENABLE_TRACE_INTERFACE
|INT:2
|vpiParameter:
\_parameter: (FETCH_BUFFER_DEPTH), line:168
|vpiName:FETCH_BUFFER_DEPTH
|INT:512
|vpiParameter:
\_parameter: (FPGA_VENDOR), line:27
|vpiName:FPGA_VENDOR
|STRING:"xilinx"
|vpiParameter:
\_parameter: (GC_UNIT_ID), line:196
|vpiName:GC_UNIT_ID
|INT:4
|vpiParameter:
\_parameter: (ICACHE_LINES), line:121
|vpiName:ICACHE_LINES
|INT:2
|vpiParameter:
\_parameter: (ICACHE_LINE_ADDR_W), line:123
|vpiName:ICACHE_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_LINE_W), line:124
|vpiName:ICACHE_LINE_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_SUB_LINE_ADDR_W), line:125
|vpiName:ICACHE_SUB_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_TAG_W), line:126
|vpiName:ICACHE_TAG_W
|INT:-2147483648
|vpiParameter:
\_parameter: (ICACHE_WAYS), line:122
|vpiName:ICACHE_WAYS
|INT:1
|vpiParameter:
\_parameter: (ITLB_DEPTH), line:146
|vpiName:ITLB_DEPTH
|INT:32
|vpiParameter:
\_parameter: (ITLB_WAYS), line:145
|vpiName:ITLB_WAYS
|INT:4
|vpiParameter:
\_parameter: (L1_CONNECTIONS), line:177
|vpiName:L1_CONNECTIONS
|INT:9
|vpiParameter:
\_parameter: (L1_DCACHE_ID), line:178
|vpiName:L1_DCACHE_ID
|INT:4
|vpiParameter:
\_parameter: (L1_DMMU_ID), line:179
|vpiName:L1_DMMU_ID
|INT:2
|vpiParameter:
\_parameter: (L1_ICACHE_ID), line:180
|vpiName:L1_ICACHE_ID
|INT:19
|vpiParameter:
\_parameter: (L1_IMMU_ID), line:181
|vpiName:L1_IMMU_ID
|INT:0
|vpiParameter:
\_parameter: (L2_DATA_ATTRIBUTES_FIFO_DEPTH), line:41
|vpiName:L2_DATA_ATTRIBUTES_FIFO_DEPTH
|INT:16
|vpiParameter:
\_parameter: (L2_ID_W), line:46
|vpiName:L2_ID_W
|INT:3
|vpiParameter:
\_parameter: (L2_INPUT_FIFO_DEPTHS), line:34
|vpiName:L2_INPUT_FIFO_DEPTHS
|INT:4
|vpiParameter:
\_parameter: (L2_INVALIDATION_FIFO_DEPTHS), line:35
|vpiName:L2_INVALIDATION_FIFO_DEPTHS
|INT:4
|vpiParameter:
\_parameter: (L2_MEM_ADDR_FIFO_DEPTH), line:39
|vpiName:L2_MEM_ADDR_FIFO_DEPTH
|INT:8
|vpiParameter:
\_parameter: (L2_NUM_PORTS), line:26
|vpiName:L2_NUM_PORTS
|INT:2
|vpiParameter:
\_parameter: (L2_READ_RETURN_FIFO_DEPTHS), line:36
|vpiName:L2_READ_RETURN_FIFO_DEPTHS
|INT:1
|vpiParameter:
\_parameter: (L2_SUB_ID_W), line:27
|vpiName:L2_SUB_ID_W
|INT:2
|vpiParameter:
\_parameter: (LS_UNIT_WB_ID), line:191
|vpiName:LS_UNIT_WB_ID
|INT:1
|vpiParameter:
\_parameter: (MAX_INFLIGHT_COUNT), line:167
|vpiName:MAX_INFLIGHT_COUNT
|INT:19
|vpiParameter:
\_parameter: (MEMORY_ADDR_H), line:103
|vpiName:MEMORY_ADDR_H
|INT:12
|vpiParameter:
\_parameter: (MEMORY_ADDR_L), line:102
|vpiName:MEMORY_ADDR_L
|INT:11
|vpiParameter:
\_parameter: (MEMORY_BIT_CHECK), line:104
|vpiName:MEMORY_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (MUL_UNIT_WB_ID), line:193
|vpiName:MUL_UNIT_WB_ID
|INT:512
|vpiParameter:
\_parameter: (NUM_UNITS), line:188
|vpiName:NUM_UNITS
|INT:2
|vpiParameter:
\_parameter: (NUM_WB_UNITS), line:186
|vpiName:NUM_WB_UNITS
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (RAS_DEPTH), line:161
|vpiName:RAS_DEPTH
|INT:2
|vpiParameter:
\_parameter: (RESET_VEC), line:39
|vpiName:RESET_VEC
|INT:-2147483648
|vpiParameter:
\_parameter: (SCRATCH_ADDR_H), line:99
|vpiName:SCRATCH_ADDR_H
|INT:9
|vpiParameter:
\_parameter: (SCRATCH_ADDR_L), line:98
|vpiName:SCRATCH_ADDR_L
|INT:8
|vpiParameter:
\_parameter: (SCRATCH_BIT_CHECK), line:100
|vpiName:SCRATCH_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (USE_AMO), line:70
|vpiName:USE_AMO
|INT:1
|vpiParameter:
\_parameter: (USE_BRANCH_PREDICTOR), line:158
|vpiName:USE_BRANCH_PREDICTOR
|INT:2
|vpiParameter:
\_parameter: (USE_BUS), line:88
|vpiName:USE_BUS
|INT:4
|vpiParameter:
\_parameter: (USE_DCACHE), line:92
|vpiName:USE_DCACHE
|INT:6
|vpiParameter:
\_parameter: (USE_DIV), line:49
|vpiName:USE_DIV
|INT:1
|vpiParameter:
\_parameter: (USE_DTAG_INVALIDATIONS), line:140
|vpiName:USE_DTAG_INVALIDATIONS
|INT:1879048191
|vpiParameter:
\_parameter: (USE_D_SCRATCH_MEM), line:79
|vpiName:USE_D_SCRATCH_MEM
|INT:3
|vpiParameter:
\_parameter: (USE_ICACHE), line:93
|vpiName:USE_ICACHE
|INT:7
|vpiParameter:
\_parameter: (USE_I_SCRATCH_MEM), line:78
|vpiName:USE_I_SCRATCH_MEM
|INT:2
|vpiParameter:
\_parameter: (USE_MUL), line:48
|vpiName:USE_MUL
|INT:1
|vpiParameter:
\_parameter: (WB_UNITS_WIDTH), line:187
|vpiName:WB_UNITS_WIDTH
|INT:32
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiGenScopeArray:
\_gen_scope_array: (genblk8[0]), line:180, parent:arb
|vpiName:genblk8[0]
|vpiFullName:work@taiga_wrapper.cpu.genblk1.arb.genblk8[0]
|vpiGenScope:
\_gen_scope: , parent:genblk8[0]
|vpiFullName:work@taiga_wrapper.cpu.genblk1.arb.genblk8[0]
|vpiContAssign:
\_cont_assign: , line:181
|vpiRhs:
\_ref_obj: (l2.rd_data), line:181
|vpiName:l2.rd_data
|vpiFullName:work@taiga_wrapper.cpu.genblk1.arb.genblk8[0].l2.rd_data
|vpiLhs:
\_ref_obj: (l1_response[i].data), line:181
|vpiName:l1_response[i].data
|vpiFullName:work@taiga_wrapper.cpu.genblk1.arb.genblk8[0].l1_response[i].data
|vpiContAssign:
\_cont_assign: , line:182
|vpiRhs:
\_operation: , line:182
|vpiOpType:26
|vpiOperand:
\_ref_obj: (l2.rd_data_valid), line:182
|vpiName:l2.rd_data_valid
|vpiFullName:work@taiga_wrapper.cpu.genblk1.arb.genblk8[0].l2.rd_data_valid
|vpiOperand:
\_operation: , line:182
|vpiOpType:14
|vpiOperand:
\_ref_obj: (l2.rd_sub_id), line:182
|vpiName:l2.rd_sub_id
|vpiFullName:work@taiga_wrapper.cpu.genblk1.arb.genblk8[0].l2.rd_sub_id
|vpiOperand:
\_ref_obj: (i), line:182
|vpiName:i
|vpiFullName:work@taiga_wrapper.cpu.genblk1.arb.genblk8[0].i
|vpiLhs:
\_ref_obj: (l1_response[i].data_valid), line:182
|vpiName:l1_response[i].data_valid
|vpiFullName:work@taiga_wrapper.cpu.genblk1.arb.genblk8[0].l1_response[i].data_valid
|vpiParameter:
\_parameter: (ALU_UNIT_WB_ID), line:190
|vpiName:ALU_UNIT_WB_ID
|INT:32
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (BRANCH_PREDICTOR_WAYS), line:159
|vpiName:BRANCH_PREDICTOR_WAYS
|INT:9
|vpiParameter:
\_parameter: (BRANCH_TABLE_ENTRIES), line:160
|vpiName:BRANCH_TABLE_ENTRIES
|INT:4
|vpiParameter:
\_parameter: (BRANCH_UNIT_ID), line:195
|vpiName:BRANCH_UNIT_ID
|INT:8
|vpiParameter:
\_parameter: (BUS_ADDR_H), line:107
|vpiName:BUS_ADDR_H
|INT:1
|vpiParameter:
\_parameter: (BUS_ADDR_L), line:106
|vpiName:BUS_ADDR_L
|INT:0
|vpiParameter:
\_parameter: (BUS_BIT_CHECK), line:108
|vpiName:BUS_BIT_CHECK
|INT:1
|vpiParameter:
\_parameter: (BUS_TYPE), line:89
|vpiName:BUS_TYPE
|INT:5
|vpiParameter:
\_parameter: (COUNTER_W), line:42
|vpiName:COUNTER_W
|INT:33
|vpiParameter:
\_parameter: (CPU_ID), line:38
|vpiName:CPU_ID
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_ADDR_WIDTH), line:113
|vpiName:C_M_AXI_ADDR_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_DATA_WIDTH), line:114
|vpiName:C_M_AXI_DATA_WIDTH
|INT:1
|vpiParameter:
\_parameter: (DCACHE_LINES), line:133
|vpiName:DCACHE_LINES
|INT:-2146435073
|vpiParameter:
\_parameter: (DCACHE_LINE_ADDR_W), line:135
|vpiName:DCACHE_LINE_ADDR_W
|INT:1073741824
|vpiParameter:
\_parameter: (DCACHE_LINE_W), line:136
|vpiName:DCACHE_LINE_W
|INT:1342177279
|vpiParameter:
\_parameter: (DCACHE_SUB_LINE_ADDR_W), line:137
|vpiName:DCACHE_SUB_LINE_ADDR_W
|INT:4
|vpiParameter:
\_parameter: (DCACHE_TAG_W), line:138
|vpiName:DCACHE_TAG_W
|INT:1610612736
|vpiParameter:
\_parameter: (DCACHE_WAYS), line:134
|vpiName:DCACHE_WAYS
|INT:4
|vpiParameter:
\_parameter: (DIV_ALGORITHM), line:67
|vpiName:DIV_ALGORITHM
|INT:0
|vpiParameter:
\_parameter: (DIV_UNIT_WB_ID), line:192
|vpiName:DIV_UNIT_WB_ID
|INT:2
|vpiParameter:
\_parameter: (DTLB_DEPTH), line:152
|vpiName:DTLB_DEPTH
|INT:512
|vpiParameter:
\_parameter: (DTLB_WAYS), line:151
|vpiName:DTLB_WAYS
|INT:32
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (ENABLE_M_MODE), line:34
|vpiName:ENABLE_M_MODE
|INT:1
|vpiParameter:
\_parameter: (ENABLE_S_MODE), line:36
|vpiName:ENABLE_S_MODE
|INT:0
|vpiParameter:
\_parameter: (ENABLE_TRACE_INTERFACE), line:172
|vpiName:ENABLE_TRACE_INTERFACE
|INT:2
|vpiParameter:
\_parameter: (FETCH_BUFFER_DEPTH), line:168
|vpiName:FETCH_BUFFER_DEPTH
|INT:512
|vpiParameter:
\_parameter: (FPGA_VENDOR), line:27
|vpiName:FPGA_VENDOR
|STRING:"xilinx"
|vpiParameter:
\_parameter: (GC_UNIT_ID), line:196
|vpiName:GC_UNIT_ID
|INT:4
|vpiParameter:
\_parameter: (ICACHE_LINES), line:121
|vpiName:ICACHE_LINES
|INT:2
|vpiParameter:
\_parameter: (ICACHE_LINE_ADDR_W), line:123
|vpiName:ICACHE_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_LINE_W), line:124
|vpiName:ICACHE_LINE_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_SUB_LINE_ADDR_W), line:125
|vpiName:ICACHE_SUB_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_TAG_W), line:126
|vpiName:ICACHE_TAG_W
|INT:-2147483648
|vpiParameter:
\_parameter: (ICACHE_WAYS), line:122
|vpiName:ICACHE_WAYS
|INT:1
|vpiParameter:
\_parameter: (ITLB_DEPTH), line:146
|vpiName:ITLB_DEPTH
|INT:32
|vpiParameter:
\_parameter: (ITLB_WAYS), line:145
|vpiName:ITLB_WAYS
|INT:4
|vpiParameter:
\_parameter: (L1_CONNECTIONS), line:177
|vpiName:L1_CONNECTIONS
|INT:9
|vpiParameter:
\_parameter: (L1_DCACHE_ID), line:178
|vpiName:L1_DCACHE_ID
|INT:4
|vpiParameter:
\_parameter: (L1_DMMU_ID), line:179
|vpiName:L1_DMMU_ID
|INT:2
|vpiParameter:
\_parameter: (L1_ICACHE_ID), line:180
|vpiName:L1_ICACHE_ID
|INT:19
|vpiParameter:
\_parameter: (L1_IMMU_ID), line:181
|vpiName:L1_IMMU_ID
|INT:0
|vpiParameter:
\_parameter: (L2_DATA_ATTRIBUTES_FIFO_DEPTH), line:41
|vpiName:L2_DATA_ATTRIBUTES_FIFO_DEPTH
|INT:16
|vpiParameter:
\_parameter: (L2_ID_W), line:46
|vpiName:L2_ID_W
|INT:3
|vpiParameter:
\_parameter: (L2_INPUT_FIFO_DEPTHS), line:34
|vpiName:L2_INPUT_FIFO_DEPTHS
|INT:4
|vpiParameter:
\_parameter: (L2_INVALIDATION_FIFO_DEPTHS), line:35
|vpiName:L2_INVALIDATION_FIFO_DEPTHS
|INT:4
|vpiParameter:
\_parameter: (L2_MEM_ADDR_FIFO_DEPTH), line:39
|vpiName:L2_MEM_ADDR_FIFO_DEPTH
|INT:8
|vpiParameter:
\_parameter: (L2_NUM_PORTS), line:26
|vpiName:L2_NUM_PORTS
|INT:2
|vpiParameter:
\_parameter: (L2_READ_RETURN_FIFO_DEPTHS), line:36
|vpiName:L2_READ_RETURN_FIFO_DEPTHS
|INT:1
|vpiParameter:
\_parameter: (L2_SUB_ID_W), line:27
|vpiName:L2_SUB_ID_W
|INT:2
|vpiParameter:
\_parameter: (LS_UNIT_WB_ID), line:191
|vpiName:LS_UNIT_WB_ID
|INT:1
|vpiParameter:
\_parameter: (MAX_INFLIGHT_COUNT), line:167
|vpiName:MAX_INFLIGHT_COUNT
|INT:19
|vpiParameter:
\_parameter: (MEMORY_ADDR_H), line:103
|vpiName:MEMORY_ADDR_H
|INT:12
|vpiParameter:
\_parameter: (MEMORY_ADDR_L), line:102
|vpiName:MEMORY_ADDR_L
|INT:11
|vpiParameter:
\_parameter: (MEMORY_BIT_CHECK), line:104
|vpiName:MEMORY_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (MUL_UNIT_WB_ID), line:193
|vpiName:MUL_UNIT_WB_ID
|INT:512
|vpiParameter:
\_parameter: (NUM_UNITS), line:188
|vpiName:NUM_UNITS
|INT:2
|vpiParameter:
\_parameter: (NUM_WB_UNITS), line:186
|vpiName:NUM_WB_UNITS
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (RAS_DEPTH), line:161
|vpiName:RAS_DEPTH
|INT:2
|vpiParameter:
\_parameter: (RESET_VEC), line:39
|vpiName:RESET_VEC
|INT:-2147483648
|vpiParameter:
\_parameter: (SCRATCH_ADDR_H), line:99
|vpiName:SCRATCH_ADDR_H
|INT:9
|vpiParameter:
\_parameter: (SCRATCH_ADDR_L), line:98
|vpiName:SCRATCH_ADDR_L
|INT:8
|vpiParameter:
\_parameter: (SCRATCH_BIT_CHECK), line:100
|vpiName:SCRATCH_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (USE_AMO), line:70
|vpiName:USE_AMO
|INT:1
|vpiParameter:
\_parameter: (USE_BRANCH_PREDICTOR), line:158
|vpiName:USE_BRANCH_PREDICTOR
|INT:2
|vpiParameter:
\_parameter: (USE_BUS), line:88
|vpiName:USE_BUS
|INT:4
|vpiParameter:
\_parameter: (USE_DCACHE), line:92
|vpiName:USE_DCACHE
|INT:6
|vpiParameter:
\_parameter: (USE_DIV), line:49
|vpiName:USE_DIV
|INT:1
|vpiParameter:
\_parameter: (USE_DTAG_INVALIDATIONS), line:140
|vpiName:USE_DTAG_INVALIDATIONS
|INT:1879048191
|vpiParameter:
\_parameter: (USE_D_SCRATCH_MEM), line:79
|vpiName:USE_D_SCRATCH_MEM
|INT:3
|vpiParameter:
\_parameter: (USE_ICACHE), line:93
|vpiName:USE_ICACHE
|INT:7
|vpiParameter:
\_parameter: (USE_I_SCRATCH_MEM), line:78
|vpiName:USE_I_SCRATCH_MEM
|INT:2
|vpiParameter:
\_parameter: (USE_MUL), line:48
|vpiName:USE_MUL
|INT:1
|vpiParameter:
\_parameter: (WB_UNITS_WIDTH), line:187
|vpiName:WB_UNITS_WIDTH
|INT:32
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiParameter:
\_parameter: (i), line:180
|vpiName:i
|INT:0
|vpiGenScopeArray:
\_gen_scope_array: (genblk8[1]), line:180, parent:arb
|vpiName:genblk8[1]
|vpiFullName:work@taiga_wrapper.cpu.genblk1.arb.genblk8[1]
|vpiGenScope:
\_gen_scope: , parent:genblk8[1]
|vpiFullName:work@taiga_wrapper.cpu.genblk1.arb.genblk8[1]
|vpiContAssign:
\_cont_assign: , line:181
|vpiRhs:
\_ref_obj: (l2.rd_data), line:181
|vpiName:l2.rd_data
|vpiFullName:work@taiga_wrapper.cpu.genblk1.arb.genblk8[1].l2.rd_data
|vpiLhs:
\_ref_obj: (l1_response[i].data), line:181
|vpiName:l1_response[i].data
|vpiFullName:work@taiga_wrapper.cpu.genblk1.arb.genblk8[1].l1_response[i].data
|vpiContAssign:
\_cont_assign: , line:182
|vpiRhs:
\_operation: , line:182
|vpiOpType:26
|vpiOperand:
\_ref_obj: (l2.rd_data_valid), line:182
|vpiName:l2.rd_data_valid
|vpiFullName:work@taiga_wrapper.cpu.genblk1.arb.genblk8[1].l2.rd_data_valid
|vpiOperand:
\_operation: , line:182
|vpiOpType:14
|vpiOperand:
\_ref_obj: (l2.rd_sub_id), line:182
|vpiName:l2.rd_sub_id
|vpiFullName:work@taiga_wrapper.cpu.genblk1.arb.genblk8[1].l2.rd_sub_id
|vpiOperand:
\_ref_obj: (i), line:182
|vpiName:i
|vpiFullName:work@taiga_wrapper.cpu.genblk1.arb.genblk8[1].i
|vpiLhs:
\_ref_obj: (l1_response[i].data_valid), line:182
|vpiName:l1_response[i].data_valid
|vpiFullName:work@taiga_wrapper.cpu.genblk1.arb.genblk8[1].l1_response[i].data_valid
|vpiParameter:
\_parameter: (ALU_UNIT_WB_ID), line:190
|vpiName:ALU_UNIT_WB_ID
|INT:32
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (BRANCH_PREDICTOR_WAYS), line:159
|vpiName:BRANCH_PREDICTOR_WAYS
|INT:9
|vpiParameter:
\_parameter: (BRANCH_TABLE_ENTRIES), line:160
|vpiName:BRANCH_TABLE_ENTRIES
|INT:4
|vpiParameter:
\_parameter: (BRANCH_UNIT_ID), line:195
|vpiName:BRANCH_UNIT_ID
|INT:8
|vpiParameter:
\_parameter: (BUS_ADDR_H), line:107
|vpiName:BUS_ADDR_H
|INT:1
|vpiParameter:
\_parameter: (BUS_ADDR_L), line:106
|vpiName:BUS_ADDR_L
|INT:0
|vpiParameter:
\_parameter: (BUS_BIT_CHECK), line:108
|vpiName:BUS_BIT_CHECK
|INT:1
|vpiParameter:
\_parameter: (BUS_TYPE), line:89
|vpiName:BUS_TYPE
|INT:5
|vpiParameter:
\_parameter: (COUNTER_W), line:42
|vpiName:COUNTER_W
|INT:33
|vpiParameter:
\_parameter: (CPU_ID), line:38
|vpiName:CPU_ID
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_ADDR_WIDTH), line:113
|vpiName:C_M_AXI_ADDR_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_DATA_WIDTH), line:114
|vpiName:C_M_AXI_DATA_WIDTH
|INT:1
|vpiParameter:
\_parameter: (DCACHE_LINES), line:133
|vpiName:DCACHE_LINES
|INT:-2146435073
|vpiParameter:
\_parameter: (DCACHE_LINE_ADDR_W), line:135
|vpiName:DCACHE_LINE_ADDR_W
|INT:1073741824
|vpiParameter:
\_parameter: (DCACHE_LINE_W), line:136
|vpiName:DCACHE_LINE_W
|INT:1342177279
|vpiParameter:
\_parameter: (DCACHE_SUB_LINE_ADDR_W), line:137
|vpiName:DCACHE_SUB_LINE_ADDR_W
|INT:4
|vpiParameter:
\_parameter: (DCACHE_TAG_W), line:138
|vpiName:DCACHE_TAG_W
|INT:1610612736
|vpiParameter:
\_parameter: (DCACHE_WAYS), line:134
|vpiName:DCACHE_WAYS
|INT:4
|vpiParameter:
\_parameter: (DIV_ALGORITHM), line:67
|vpiName:DIV_ALGORITHM
|INT:0
|vpiParameter:
\_parameter: (DIV_UNIT_WB_ID), line:192
|vpiName:DIV_UNIT_WB_ID
|INT:2
|vpiParameter:
\_parameter: (DTLB_DEPTH), line:152
|vpiName:DTLB_DEPTH
|INT:512
|vpiParameter:
\_parameter: (DTLB_WAYS), line:151
|vpiName:DTLB_WAYS
|INT:32
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (ENABLE_M_MODE), line:34
|vpiName:ENABLE_M_MODE
|INT:1
|vpiParameter:
\_parameter: (ENABLE_S_MODE), line:36
|vpiName:ENABLE_S_MODE
|INT:0
|vpiParameter:
\_parameter: (ENABLE_TRACE_INTERFACE), line:172
|vpiName:ENABLE_TRACE_INTERFACE
|INT:2
|vpiParameter:
\_parameter: (FETCH_BUFFER_DEPTH), line:168
|vpiName:FETCH_BUFFER_DEPTH
|INT:512
|vpiParameter:
\_parameter: (FPGA_VENDOR), line:27
|vpiName:FPGA_VENDOR
|STRING:"xilinx"
|vpiParameter:
\_parameter: (GC_UNIT_ID), line:196
|vpiName:GC_UNIT_ID
|INT:4
|vpiParameter:
\_parameter: (ICACHE_LINES), line:121
|vpiName:ICACHE_LINES
|INT:2
|vpiParameter:
\_parameter: (ICACHE_LINE_ADDR_W), line:123
|vpiName:ICACHE_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_LINE_W), line:124
|vpiName:ICACHE_LINE_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_SUB_LINE_ADDR_W), line:125
|vpiName:ICACHE_SUB_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_TAG_W), line:126
|vpiName:ICACHE_TAG_W
|INT:-2147483648
|vpiParameter:
\_parameter: (ICACHE_WAYS), line:122
|vpiName:ICACHE_WAYS
|INT:1
|vpiParameter:
\_parameter: (ITLB_DEPTH), line:146
|vpiName:ITLB_DEPTH
|INT:32
|vpiParameter:
\_parameter: (ITLB_WAYS), line:145
|vpiName:ITLB_WAYS
|INT:4
|vpiParameter:
\_parameter: (L1_CONNECTIONS), line:177
|vpiName:L1_CONNECTIONS
|INT:9
|vpiParameter:
\_parameter: (L1_DCACHE_ID), line:178
|vpiName:L1_DCACHE_ID
|INT:4
|vpiParameter:
\_parameter: (L1_DMMU_ID), line:179
|vpiName:L1_DMMU_ID
|INT:2
|vpiParameter:
\_parameter: (L1_ICACHE_ID), line:180
|vpiName:L1_ICACHE_ID
|INT:19
|vpiParameter:
\_parameter: (L1_IMMU_ID), line:181
|vpiName:L1_IMMU_ID
|INT:0
|vpiParameter:
\_parameter: (L2_DATA_ATTRIBUTES_FIFO_DEPTH), line:41
|vpiName:L2_DATA_ATTRIBUTES_FIFO_DEPTH
|INT:16
|vpiParameter:
\_parameter: (L2_ID_W), line:46
|vpiName:L2_ID_W
|INT:3
|vpiParameter:
\_parameter: (L2_INPUT_FIFO_DEPTHS), line:34
|vpiName:L2_INPUT_FIFO_DEPTHS
|INT:4
|vpiParameter:
\_parameter: (L2_INVALIDATION_FIFO_DEPTHS), line:35
|vpiName:L2_INVALIDATION_FIFO_DEPTHS
|INT:4
|vpiParameter:
\_parameter: (L2_MEM_ADDR_FIFO_DEPTH), line:39
|vpiName:L2_MEM_ADDR_FIFO_DEPTH
|INT:8
|vpiParameter:
\_parameter: (L2_NUM_PORTS), line:26
|vpiName:L2_NUM_PORTS
|INT:2
|vpiParameter:
\_parameter: (L2_READ_RETURN_FIFO_DEPTHS), line:36
|vpiName:L2_READ_RETURN_FIFO_DEPTHS
|INT:1
|vpiParameter:
\_parameter: (L2_SUB_ID_W), line:27
|vpiName:L2_SUB_ID_W
|INT:2
|vpiParameter:
\_parameter: (LS_UNIT_WB_ID), line:191
|vpiName:LS_UNIT_WB_ID
|INT:1
|vpiParameter:
\_parameter: (MAX_INFLIGHT_COUNT), line:167
|vpiName:MAX_INFLIGHT_COUNT
|INT:19
|vpiParameter:
\_parameter: (MEMORY_ADDR_H), line:103
|vpiName:MEMORY_ADDR_H
|INT:12
|vpiParameter:
\_parameter: (MEMORY_ADDR_L), line:102
|vpiName:MEMORY_ADDR_L
|INT:11
|vpiParameter:
\_parameter: (MEMORY_BIT_CHECK), line:104
|vpiName:MEMORY_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (MUL_UNIT_WB_ID), line:193
|vpiName:MUL_UNIT_WB_ID
|INT:512
|vpiParameter:
\_parameter: (NUM_UNITS), line:188
|vpiName:NUM_UNITS
|INT:2
|vpiParameter:
\_parameter: (NUM_WB_UNITS), line:186
|vpiName:NUM_WB_UNITS
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (RAS_DEPTH), line:161
|vpiName:RAS_DEPTH
|INT:2
|vpiParameter:
\_parameter: (RESET_VEC), line:39
|vpiName:RESET_VEC
|INT:-2147483648
|vpiParameter:
\_parameter: (SCRATCH_ADDR_H), line:99
|vpiName:SCRATCH_ADDR_H
|INT:9
|vpiParameter:
\_parameter: (SCRATCH_ADDR_L), line:98
|vpiName:SCRATCH_ADDR_L
|INT:8
|vpiParameter:
\_parameter: (SCRATCH_BIT_CHECK), line:100
|vpiName:SCRATCH_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (USE_AMO), line:70
|vpiName:USE_AMO
|INT:1
|vpiParameter:
\_parameter: (USE_BRANCH_PREDICTOR), line:158
|vpiName:USE_BRANCH_PREDICTOR
|INT:2
|vpiParameter:
\_parameter: (USE_BUS), line:88
|vpiName:USE_BUS
|INT:4
|vpiParameter:
\_parameter: (USE_DCACHE), line:92
|vpiName:USE_DCACHE
|INT:6
|vpiParameter:
\_parameter: (USE_DIV), line:49
|vpiName:USE_DIV
|INT:1
|vpiParameter:
\_parameter: (USE_DTAG_INVALIDATIONS), line:140
|vpiName:USE_DTAG_INVALIDATIONS
|INT:1879048191
|vpiParameter:
\_parameter: (USE_D_SCRATCH_MEM), line:79
|vpiName:USE_D_SCRATCH_MEM
|INT:3
|vpiParameter:
\_parameter: (USE_ICACHE), line:93
|vpiName:USE_ICACHE
|INT:7
|vpiParameter:
\_parameter: (USE_I_SCRATCH_MEM), line:78
|vpiName:USE_I_SCRATCH_MEM
|INT:2
|vpiParameter:
\_parameter: (USE_MUL), line:48
|vpiName:USE_MUL
|INT:1
|vpiParameter:
\_parameter: (WB_UNITS_WIDTH), line:187
|vpiName:WB_UNITS_WIDTH
|INT:32
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiParameter:
\_parameter: (i), line:180
|vpiName:i
|INT:1
|vpiGenScopeArray:
\_gen_scope_array: (genblk8[2]), line:180, parent:arb
|vpiName:genblk8[2]
|vpiFullName:work@taiga_wrapper.cpu.genblk1.arb.genblk8[2]
|vpiGenScope:
\_gen_scope: , parent:genblk8[2]
|vpiFullName:work@taiga_wrapper.cpu.genblk1.arb.genblk8[2]
|vpiContAssign:
\_cont_assign: , line:181
|vpiRhs:
\_ref_obj: (l2.rd_data), line:181
|vpiName:l2.rd_data
|vpiFullName:work@taiga_wrapper.cpu.genblk1.arb.genblk8[2].l2.rd_data
|vpiLhs:
\_ref_obj: (l1_response[i].data), line:181
|vpiName:l1_response[i].data
|vpiFullName:work@taiga_wrapper.cpu.genblk1.arb.genblk8[2].l1_response[i].data
|vpiContAssign:
\_cont_assign: , line:182
|vpiRhs:
\_operation: , line:182
|vpiOpType:26
|vpiOperand:
\_ref_obj: (l2.rd_data_valid), line:182
|vpiName:l2.rd_data_valid
|vpiFullName:work@taiga_wrapper.cpu.genblk1.arb.genblk8[2].l2.rd_data_valid
|vpiOperand:
\_operation: , line:182
|vpiOpType:14
|vpiOperand:
\_ref_obj: (l2.rd_sub_id), line:182
|vpiName:l2.rd_sub_id
|vpiFullName:work@taiga_wrapper.cpu.genblk1.arb.genblk8[2].l2.rd_sub_id
|vpiOperand:
\_ref_obj: (i), line:182
|vpiName:i
|vpiFullName:work@taiga_wrapper.cpu.genblk1.arb.genblk8[2].i
|vpiLhs:
\_ref_obj: (l1_response[i].data_valid), line:182
|vpiName:l1_response[i].data_valid
|vpiFullName:work@taiga_wrapper.cpu.genblk1.arb.genblk8[2].l1_response[i].data_valid
|vpiParameter:
\_parameter: (ALU_UNIT_WB_ID), line:190
|vpiName:ALU_UNIT_WB_ID
|INT:32
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (BRANCH_PREDICTOR_WAYS), line:159
|vpiName:BRANCH_PREDICTOR_WAYS
|INT:9
|vpiParameter:
\_parameter: (BRANCH_TABLE_ENTRIES), line:160
|vpiName:BRANCH_TABLE_ENTRIES
|INT:4
|vpiParameter:
\_parameter: (BRANCH_UNIT_ID), line:195
|vpiName:BRANCH_UNIT_ID
|INT:8
|vpiParameter:
\_parameter: (BUS_ADDR_H), line:107
|vpiName:BUS_ADDR_H
|INT:1
|vpiParameter:
\_parameter: (BUS_ADDR_L), line:106
|vpiName:BUS_ADDR_L
|INT:0
|vpiParameter:
\_parameter: (BUS_BIT_CHECK), line:108
|vpiName:BUS_BIT_CHECK
|INT:1
|vpiParameter:
\_parameter: (BUS_TYPE), line:89
|vpiName:BUS_TYPE
|INT:5
|vpiParameter:
\_parameter: (COUNTER_W), line:42
|vpiName:COUNTER_W
|INT:33
|vpiParameter:
\_parameter: (CPU_ID), line:38
|vpiName:CPU_ID
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_ADDR_WIDTH), line:113
|vpiName:C_M_AXI_ADDR_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_DATA_WIDTH), line:114
|vpiName:C_M_AXI_DATA_WIDTH
|INT:1
|vpiParameter:
\_parameter: (DCACHE_LINES), line:133
|vpiName:DCACHE_LINES
|INT:-2146435073
|vpiParameter:
\_parameter: (DCACHE_LINE_ADDR_W), line:135
|vpiName:DCACHE_LINE_ADDR_W
|INT:1073741824
|vpiParameter:
\_parameter: (DCACHE_LINE_W), line:136
|vpiName:DCACHE_LINE_W
|INT:1342177279
|vpiParameter:
\_parameter: (DCACHE_SUB_LINE_ADDR_W), line:137
|vpiName:DCACHE_SUB_LINE_ADDR_W
|INT:4
|vpiParameter:
\_parameter: (DCACHE_TAG_W), line:138
|vpiName:DCACHE_TAG_W
|INT:1610612736
|vpiParameter:
\_parameter: (DCACHE_WAYS), line:134
|vpiName:DCACHE_WAYS
|INT:4
|vpiParameter:
\_parameter: (DIV_ALGORITHM), line:67
|vpiName:DIV_ALGORITHM
|INT:0
|vpiParameter:
\_parameter: (DIV_UNIT_WB_ID), line:192
|vpiName:DIV_UNIT_WB_ID
|INT:2
|vpiParameter:
\_parameter: (DTLB_DEPTH), line:152
|vpiName:DTLB_DEPTH
|INT:512
|vpiParameter:
\_parameter: (DTLB_WAYS), line:151
|vpiName:DTLB_WAYS
|INT:32
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (ENABLE_M_MODE), line:34
|vpiName:ENABLE_M_MODE
|INT:1
|vpiParameter:
\_parameter: (ENABLE_S_MODE), line:36
|vpiName:ENABLE_S_MODE
|INT:0
|vpiParameter:
\_parameter: (ENABLE_TRACE_INTERFACE), line:172
|vpiName:ENABLE_TRACE_INTERFACE
|INT:2
|vpiParameter:
\_parameter: (FETCH_BUFFER_DEPTH), line:168
|vpiName:FETCH_BUFFER_DEPTH
|INT:512
|vpiParameter:
\_parameter: (FPGA_VENDOR), line:27
|vpiName:FPGA_VENDOR
|STRING:"xilinx"
|vpiParameter:
\_parameter: (GC_UNIT_ID), line:196
|vpiName:GC_UNIT_ID
|INT:4
|vpiParameter:
\_parameter: (ICACHE_LINES), line:121
|vpiName:ICACHE_LINES
|INT:2
|vpiParameter:
\_parameter: (ICACHE_LINE_ADDR_W), line:123
|vpiName:ICACHE_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_LINE_W), line:124
|vpiName:ICACHE_LINE_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_SUB_LINE_ADDR_W), line:125
|vpiName:ICACHE_SUB_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_TAG_W), line:126
|vpiName:ICACHE_TAG_W
|INT:-2147483648
|vpiParameter:
\_parameter: (ICACHE_WAYS), line:122
|vpiName:ICACHE_WAYS
|INT:1
|vpiParameter:
\_parameter: (ITLB_DEPTH), line:146
|vpiName:ITLB_DEPTH
|INT:32
|vpiParameter:
\_parameter: (ITLB_WAYS), line:145
|vpiName:ITLB_WAYS
|INT:4
|vpiParameter:
\_parameter: (L1_CONNECTIONS), line:177
|vpiName:L1_CONNECTIONS
|INT:9
|vpiParameter:
\_parameter: (L1_DCACHE_ID), line:178
|vpiName:L1_DCACHE_ID
|INT:4
|vpiParameter:
\_parameter: (L1_DMMU_ID), line:179
|vpiName:L1_DMMU_ID
|INT:2
|vpiParameter:
\_parameter: (L1_ICACHE_ID), line:180
|vpiName:L1_ICACHE_ID
|INT:19
|vpiParameter:
\_parameter: (L1_IMMU_ID), line:181
|vpiName:L1_IMMU_ID
|INT:0
|vpiParameter:
\_parameter: (L2_DATA_ATTRIBUTES_FIFO_DEPTH), line:41
|vpiName:L2_DATA_ATTRIBUTES_FIFO_DEPTH
|INT:16
|vpiParameter:
\_parameter: (L2_ID_W), line:46
|vpiName:L2_ID_W
|INT:3
|vpiParameter:
\_parameter: (L2_INPUT_FIFO_DEPTHS), line:34
|vpiName:L2_INPUT_FIFO_DEPTHS
|INT:4
|vpiParameter:
\_parameter: (L2_INVALIDATION_FIFO_DEPTHS), line:35
|vpiName:L2_INVALIDATION_FIFO_DEPTHS
|INT:4
|vpiParameter:
\_parameter: (L2_MEM_ADDR_FIFO_DEPTH), line:39
|vpiName:L2_MEM_ADDR_FIFO_DEPTH
|INT:8
|vpiParameter:
\_parameter: (L2_NUM_PORTS), line:26
|vpiName:L2_NUM_PORTS
|INT:2
|vpiParameter:
\_parameter: (L2_READ_RETURN_FIFO_DEPTHS), line:36
|vpiName:L2_READ_RETURN_FIFO_DEPTHS
|INT:1
|vpiParameter:
\_parameter: (L2_SUB_ID_W), line:27
|vpiName:L2_SUB_ID_W
|INT:2
|vpiParameter:
\_parameter: (LS_UNIT_WB_ID), line:191
|vpiName:LS_UNIT_WB_ID
|INT:1
|vpiParameter:
\_parameter: (MAX_INFLIGHT_COUNT), line:167
|vpiName:MAX_INFLIGHT_COUNT
|INT:19
|vpiParameter:
\_parameter: (MEMORY_ADDR_H), line:103
|vpiName:MEMORY_ADDR_H
|INT:12
|vpiParameter:
\_parameter: (MEMORY_ADDR_L), line:102
|vpiName:MEMORY_ADDR_L
|INT:11
|vpiParameter:
\_parameter: (MEMORY_BIT_CHECK), line:104
|vpiName:MEMORY_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (MUL_UNIT_WB_ID), line:193
|vpiName:MUL_UNIT_WB_ID
|INT:512
|vpiParameter:
\_parameter: (NUM_UNITS), line:188
|vpiName:NUM_UNITS
|INT:2
|vpiParameter:
\_parameter: (NUM_WB_UNITS), line:186
|vpiName:NUM_WB_UNITS
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (RAS_DEPTH), line:161
|vpiName:RAS_DEPTH
|INT:2
|vpiParameter:
\_parameter: (RESET_VEC), line:39
|vpiName:RESET_VEC
|INT:-2147483648
|vpiParameter:
\_parameter: (SCRATCH_ADDR_H), line:99
|vpiName:SCRATCH_ADDR_H
|INT:9
|vpiParameter:
\_parameter: (SCRATCH_ADDR_L), line:98
|vpiName:SCRATCH_ADDR_L
|INT:8
|vpiParameter:
\_parameter: (SCRATCH_BIT_CHECK), line:100
|vpiName:SCRATCH_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (USE_AMO), line:70
|vpiName:USE_AMO
|INT:1
|vpiParameter:
\_parameter: (USE_BRANCH_PREDICTOR), line:158
|vpiName:USE_BRANCH_PREDICTOR
|INT:2
|vpiParameter:
\_parameter: (USE_BUS), line:88
|vpiName:USE_BUS
|INT:4
|vpiParameter:
\_parameter: (USE_DCACHE), line:92
|vpiName:USE_DCACHE
|INT:6
|vpiParameter:
\_parameter: (USE_DIV), line:49
|vpiName:USE_DIV
|INT:1
|vpiParameter:
\_parameter: (USE_DTAG_INVALIDATIONS), line:140
|vpiName:USE_DTAG_INVALIDATIONS
|INT:1879048191
|vpiParameter:
\_parameter: (USE_D_SCRATCH_MEM), line:79
|vpiName:USE_D_SCRATCH_MEM
|INT:3
|vpiParameter:
\_parameter: (USE_ICACHE), line:93
|vpiName:USE_ICACHE
|INT:7
|vpiParameter:
\_parameter: (USE_I_SCRATCH_MEM), line:78
|vpiName:USE_I_SCRATCH_MEM
|INT:2
|vpiParameter:
\_parameter: (USE_MUL), line:48
|vpiName:USE_MUL
|INT:1
|vpiParameter:
\_parameter: (WB_UNITS_WIDTH), line:187
|vpiName:WB_UNITS_WIDTH
|INT:32
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiParameter:
\_parameter: (i), line:180
|vpiName:i
|INT:2
|vpiGenScopeArray:
\_gen_scope_array: (genblk8[3]), line:180, parent:arb
|vpiName:genblk8[3]
|vpiFullName:work@taiga_wrapper.cpu.genblk1.arb.genblk8[3]
|vpiGenScope:
\_gen_scope: , parent:genblk8[3]
|vpiFullName:work@taiga_wrapper.cpu.genblk1.arb.genblk8[3]
|vpiContAssign:
\_cont_assign: , line:181
|vpiRhs:
\_ref_obj: (l2.rd_data), line:181
|vpiName:l2.rd_data
|vpiFullName:work@taiga_wrapper.cpu.genblk1.arb.genblk8[3].l2.rd_data
|vpiLhs:
\_ref_obj: (l1_response[i].data), line:181
|vpiName:l1_response[i].data
|vpiFullName:work@taiga_wrapper.cpu.genblk1.arb.genblk8[3].l1_response[i].data
|vpiContAssign:
\_cont_assign: , line:182
|vpiRhs:
\_operation: , line:182
|vpiOpType:26
|vpiOperand:
\_ref_obj: (l2.rd_data_valid), line:182
|vpiName:l2.rd_data_valid
|vpiFullName:work@taiga_wrapper.cpu.genblk1.arb.genblk8[3].l2.rd_data_valid
|vpiOperand:
\_operation: , line:182
|vpiOpType:14
|vpiOperand:
\_ref_obj: (l2.rd_sub_id), line:182
|vpiName:l2.rd_sub_id
|vpiFullName:work@taiga_wrapper.cpu.genblk1.arb.genblk8[3].l2.rd_sub_id
|vpiOperand:
\_ref_obj: (i), line:182
|vpiName:i
|vpiFullName:work@taiga_wrapper.cpu.genblk1.arb.genblk8[3].i
|vpiLhs:
\_ref_obj: (l1_response[i].data_valid), line:182
|vpiName:l1_response[i].data_valid
|vpiFullName:work@taiga_wrapper.cpu.genblk1.arb.genblk8[3].l1_response[i].data_valid
|vpiParameter:
\_parameter: (ALU_UNIT_WB_ID), line:190
|vpiName:ALU_UNIT_WB_ID
|INT:32
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (BRANCH_PREDICTOR_WAYS), line:159
|vpiName:BRANCH_PREDICTOR_WAYS
|INT:9
|vpiParameter:
\_parameter: (BRANCH_TABLE_ENTRIES), line:160
|vpiName:BRANCH_TABLE_ENTRIES
|INT:4
|vpiParameter:
\_parameter: (BRANCH_UNIT_ID), line:195
|vpiName:BRANCH_UNIT_ID
|INT:8
|vpiParameter:
\_parameter: (BUS_ADDR_H), line:107
|vpiName:BUS_ADDR_H
|INT:1
|vpiParameter:
\_parameter: (BUS_ADDR_L), line:106
|vpiName:BUS_ADDR_L
|INT:0
|vpiParameter:
\_parameter: (BUS_BIT_CHECK), line:108
|vpiName:BUS_BIT_CHECK
|INT:1
|vpiParameter:
\_parameter: (BUS_TYPE), line:89
|vpiName:BUS_TYPE
|INT:5
|vpiParameter:
\_parameter: (COUNTER_W), line:42
|vpiName:COUNTER_W
|INT:33
|vpiParameter:
\_parameter: (CPU_ID), line:38
|vpiName:CPU_ID
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_ADDR_WIDTH), line:113
|vpiName:C_M_AXI_ADDR_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_DATA_WIDTH), line:114
|vpiName:C_M_AXI_DATA_WIDTH
|INT:1
|vpiParameter:
\_parameter: (DCACHE_LINES), line:133
|vpiName:DCACHE_LINES
|INT:-2146435073
|vpiParameter:
\_parameter: (DCACHE_LINE_ADDR_W), line:135
|vpiName:DCACHE_LINE_ADDR_W
|INT:1073741824
|vpiParameter:
\_parameter: (DCACHE_LINE_W), line:136
|vpiName:DCACHE_LINE_W
|INT:1342177279
|vpiParameter:
\_parameter: (DCACHE_SUB_LINE_ADDR_W), line:137
|vpiName:DCACHE_SUB_LINE_ADDR_W
|INT:4
|vpiParameter:
\_parameter: (DCACHE_TAG_W), line:138
|vpiName:DCACHE_TAG_W
|INT:1610612736
|vpiParameter:
\_parameter: (DCACHE_WAYS), line:134
|vpiName:DCACHE_WAYS
|INT:4
|vpiParameter:
\_parameter: (DIV_ALGORITHM), line:67
|vpiName:DIV_ALGORITHM
|INT:0
|vpiParameter:
\_parameter: (DIV_UNIT_WB_ID), line:192
|vpiName:DIV_UNIT_WB_ID
|INT:2
|vpiParameter:
\_parameter: (DTLB_DEPTH), line:152
|vpiName:DTLB_DEPTH
|INT:512
|vpiParameter:
\_parameter: (DTLB_WAYS), line:151
|vpiName:DTLB_WAYS
|INT:32
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (ENABLE_M_MODE), line:34
|vpiName:ENABLE_M_MODE
|INT:1
|vpiParameter:
\_parameter: (ENABLE_S_MODE), line:36
|vpiName:ENABLE_S_MODE
|INT:0
|vpiParameter:
\_parameter: (ENABLE_TRACE_INTERFACE), line:172
|vpiName:ENABLE_TRACE_INTERFACE
|INT:2
|vpiParameter:
\_parameter: (FETCH_BUFFER_DEPTH), line:168
|vpiName:FETCH_BUFFER_DEPTH
|INT:512
|vpiParameter:
\_parameter: (FPGA_VENDOR), line:27
|vpiName:FPGA_VENDOR
|STRING:"xilinx"
|vpiParameter:
\_parameter: (GC_UNIT_ID), line:196
|vpiName:GC_UNIT_ID
|INT:4
|vpiParameter:
\_parameter: (ICACHE_LINES), line:121
|vpiName:ICACHE_LINES
|INT:2
|vpiParameter:
\_parameter: (ICACHE_LINE_ADDR_W), line:123
|vpiName:ICACHE_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_LINE_W), line:124
|vpiName:ICACHE_LINE_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_SUB_LINE_ADDR_W), line:125
|vpiName:ICACHE_SUB_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_TAG_W), line:126
|vpiName:ICACHE_TAG_W
|INT:-2147483648
|vpiParameter:
\_parameter: (ICACHE_WAYS), line:122
|vpiName:ICACHE_WAYS
|INT:1
|vpiParameter:
\_parameter: (ITLB_DEPTH), line:146
|vpiName:ITLB_DEPTH
|INT:32
|vpiParameter:
\_parameter: (ITLB_WAYS), line:145
|vpiName:ITLB_WAYS
|INT:4
|vpiParameter:
\_parameter: (L1_CONNECTIONS), line:177
|vpiName:L1_CONNECTIONS
|INT:9
|vpiParameter:
\_parameter: (L1_DCACHE_ID), line:178
|vpiName:L1_DCACHE_ID
|INT:4
|vpiParameter:
\_parameter: (L1_DMMU_ID), line:179
|vpiName:L1_DMMU_ID
|INT:2
|vpiParameter:
\_parameter: (L1_ICACHE_ID), line:180
|vpiName:L1_ICACHE_ID
|INT:19
|vpiParameter:
\_parameter: (L1_IMMU_ID), line:181
|vpiName:L1_IMMU_ID
|INT:0
|vpiParameter:
\_parameter: (L2_DATA_ATTRIBUTES_FIFO_DEPTH), line:41
|vpiName:L2_DATA_ATTRIBUTES_FIFO_DEPTH
|INT:16
|vpiParameter:
\_parameter: (L2_ID_W), line:46
|vpiName:L2_ID_W
|INT:3
|vpiParameter:
\_parameter: (L2_INPUT_FIFO_DEPTHS), line:34
|vpiName:L2_INPUT_FIFO_DEPTHS
|INT:4
|vpiParameter:
\_parameter: (L2_INVALIDATION_FIFO_DEPTHS), line:35
|vpiName:L2_INVALIDATION_FIFO_DEPTHS
|INT:4
|vpiParameter:
\_parameter: (L2_MEM_ADDR_FIFO_DEPTH), line:39
|vpiName:L2_MEM_ADDR_FIFO_DEPTH
|INT:8
|vpiParameter:
\_parameter: (L2_NUM_PORTS), line:26
|vpiName:L2_NUM_PORTS
|INT:2
|vpiParameter:
\_parameter: (L2_READ_RETURN_FIFO_DEPTHS), line:36
|vpiName:L2_READ_RETURN_FIFO_DEPTHS
|INT:1
|vpiParameter:
\_parameter: (L2_SUB_ID_W), line:27
|vpiName:L2_SUB_ID_W
|INT:2
|vpiParameter:
\_parameter: (LS_UNIT_WB_ID), line:191
|vpiName:LS_UNIT_WB_ID
|INT:1
|vpiParameter:
\_parameter: (MAX_INFLIGHT_COUNT), line:167
|vpiName:MAX_INFLIGHT_COUNT
|INT:19
|vpiParameter:
\_parameter: (MEMORY_ADDR_H), line:103
|vpiName:MEMORY_ADDR_H
|INT:12
|vpiParameter:
\_parameter: (MEMORY_ADDR_L), line:102
|vpiName:MEMORY_ADDR_L
|INT:11
|vpiParameter:
\_parameter: (MEMORY_BIT_CHECK), line:104
|vpiName:MEMORY_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (MUL_UNIT_WB_ID), line:193
|vpiName:MUL_UNIT_WB_ID
|INT:512
|vpiParameter:
\_parameter: (NUM_UNITS), line:188
|vpiName:NUM_UNITS
|INT:2
|vpiParameter:
\_parameter: (NUM_WB_UNITS), line:186
|vpiName:NUM_WB_UNITS
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (RAS_DEPTH), line:161
|vpiName:RAS_DEPTH
|INT:2
|vpiParameter:
\_parameter: (RESET_VEC), line:39
|vpiName:RESET_VEC
|INT:-2147483648
|vpiParameter:
\_parameter: (SCRATCH_ADDR_H), line:99
|vpiName:SCRATCH_ADDR_H
|INT:9
|vpiParameter:
\_parameter: (SCRATCH_ADDR_L), line:98
|vpiName:SCRATCH_ADDR_L
|INT:8
|vpiParameter:
\_parameter: (SCRATCH_BIT_CHECK), line:100
|vpiName:SCRATCH_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (USE_AMO), line:70
|vpiName:USE_AMO
|INT:1
|vpiParameter:
\_parameter: (USE_BRANCH_PREDICTOR), line:158
|vpiName:USE_BRANCH_PREDICTOR
|INT:2
|vpiParameter:
\_parameter: (USE_BUS), line:88
|vpiName:USE_BUS
|INT:4
|vpiParameter:
\_parameter: (USE_DCACHE), line:92
|vpiName:USE_DCACHE
|INT:6
|vpiParameter:
\_parameter: (USE_DIV), line:49
|vpiName:USE_DIV
|INT:1
|vpiParameter:
\_parameter: (USE_DTAG_INVALIDATIONS), line:140
|vpiName:USE_DTAG_INVALIDATIONS
|INT:1879048191
|vpiParameter:
\_parameter: (USE_D_SCRATCH_MEM), line:79
|vpiName:USE_D_SCRATCH_MEM
|INT:3
|vpiParameter:
\_parameter: (USE_ICACHE), line:93
|vpiName:USE_ICACHE
|INT:7
|vpiParameter:
\_parameter: (USE_I_SCRATCH_MEM), line:78
|vpiName:USE_I_SCRATCH_MEM
|INT:2
|vpiParameter:
\_parameter: (USE_MUL), line:48
|vpiName:USE_MUL
|INT:1
|vpiParameter:
\_parameter: (WB_UNITS_WIDTH), line:187
|vpiName:WB_UNITS_WIDTH
|INT:32
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiParameter:
\_parameter: (i), line:180
|vpiName:i
|INT:3
|vpiGenScopeArray:
\_gen_scope_array: (genblk8[4]), line:180, parent:arb
|vpiName:genblk8[4]
|vpiFullName:work@taiga_wrapper.cpu.genblk1.arb.genblk8[4]
|vpiGenScope:
\_gen_scope: , parent:genblk8[4]
|vpiFullName:work@taiga_wrapper.cpu.genblk1.arb.genblk8[4]
|vpiContAssign:
\_cont_assign: , line:181
|vpiRhs:
\_ref_obj: (l2.rd_data), line:181
|vpiName:l2.rd_data
|vpiFullName:work@taiga_wrapper.cpu.genblk1.arb.genblk8[4].l2.rd_data
|vpiLhs:
\_ref_obj: (l1_response[i].data), line:181
|vpiName:l1_response[i].data
|vpiFullName:work@taiga_wrapper.cpu.genblk1.arb.genblk8[4].l1_response[i].data
|vpiContAssign:
\_cont_assign: , line:182
|vpiRhs:
\_operation: , line:182
|vpiOpType:26
|vpiOperand:
\_ref_obj: (l2.rd_data_valid), line:182
|vpiName:l2.rd_data_valid
|vpiFullName:work@taiga_wrapper.cpu.genblk1.arb.genblk8[4].l2.rd_data_valid
|vpiOperand:
\_operation: , line:182
|vpiOpType:14
|vpiOperand:
\_ref_obj: (l2.rd_sub_id), line:182
|vpiName:l2.rd_sub_id
|vpiFullName:work@taiga_wrapper.cpu.genblk1.arb.genblk8[4].l2.rd_sub_id
|vpiOperand:
\_ref_obj: (i), line:182
|vpiName:i
|vpiFullName:work@taiga_wrapper.cpu.genblk1.arb.genblk8[4].i
|vpiLhs:
\_ref_obj: (l1_response[i].data_valid), line:182
|vpiName:l1_response[i].data_valid
|vpiFullName:work@taiga_wrapper.cpu.genblk1.arb.genblk8[4].l1_response[i].data_valid
|vpiParameter:
\_parameter: (ALU_UNIT_WB_ID), line:190
|vpiName:ALU_UNIT_WB_ID
|INT:32
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (BRANCH_PREDICTOR_WAYS), line:159
|vpiName:BRANCH_PREDICTOR_WAYS
|INT:9
|vpiParameter:
\_parameter: (BRANCH_TABLE_ENTRIES), line:160
|vpiName:BRANCH_TABLE_ENTRIES
|INT:4
|vpiParameter:
\_parameter: (BRANCH_UNIT_ID), line:195
|vpiName:BRANCH_UNIT_ID
|INT:8
|vpiParameter:
\_parameter: (BUS_ADDR_H), line:107
|vpiName:BUS_ADDR_H
|INT:1
|vpiParameter:
\_parameter: (BUS_ADDR_L), line:106
|vpiName:BUS_ADDR_L
|INT:0
|vpiParameter:
\_parameter: (BUS_BIT_CHECK), line:108
|vpiName:BUS_BIT_CHECK
|INT:1
|vpiParameter:
\_parameter: (BUS_TYPE), line:89
|vpiName:BUS_TYPE
|INT:5
|vpiParameter:
\_parameter: (COUNTER_W), line:42
|vpiName:COUNTER_W
|INT:33
|vpiParameter:
\_parameter: (CPU_ID), line:38
|vpiName:CPU_ID
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_ADDR_WIDTH), line:113
|vpiName:C_M_AXI_ADDR_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_DATA_WIDTH), line:114
|vpiName:C_M_AXI_DATA_WIDTH
|INT:1
|vpiParameter:
\_parameter: (DCACHE_LINES), line:133
|vpiName:DCACHE_LINES
|INT:-2146435073
|vpiParameter:
\_parameter: (DCACHE_LINE_ADDR_W), line:135
|vpiName:DCACHE_LINE_ADDR_W
|INT:1073741824
|vpiParameter:
\_parameter: (DCACHE_LINE_W), line:136
|vpiName:DCACHE_LINE_W
|INT:1342177279
|vpiParameter:
\_parameter: (DCACHE_SUB_LINE_ADDR_W), line:137
|vpiName:DCACHE_SUB_LINE_ADDR_W
|INT:4
|vpiParameter:
\_parameter: (DCACHE_TAG_W), line:138
|vpiName:DCACHE_TAG_W
|INT:1610612736
|vpiParameter:
\_parameter: (DCACHE_WAYS), line:134
|vpiName:DCACHE_WAYS
|INT:4
|vpiParameter:
\_parameter: (DIV_ALGORITHM), line:67
|vpiName:DIV_ALGORITHM
|INT:0
|vpiParameter:
\_parameter: (DIV_UNIT_WB_ID), line:192
|vpiName:DIV_UNIT_WB_ID
|INT:2
|vpiParameter:
\_parameter: (DTLB_DEPTH), line:152
|vpiName:DTLB_DEPTH
|INT:512
|vpiParameter:
\_parameter: (DTLB_WAYS), line:151
|vpiName:DTLB_WAYS
|INT:32
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (ENABLE_M_MODE), line:34
|vpiName:ENABLE_M_MODE
|INT:1
|vpiParameter:
\_parameter: (ENABLE_S_MODE), line:36
|vpiName:ENABLE_S_MODE
|INT:0
|vpiParameter:
\_parameter: (ENABLE_TRACE_INTERFACE), line:172
|vpiName:ENABLE_TRACE_INTERFACE
|INT:2
|vpiParameter:
\_parameter: (FETCH_BUFFER_DEPTH), line:168
|vpiName:FETCH_BUFFER_DEPTH
|INT:512
|vpiParameter:
\_parameter: (FPGA_VENDOR), line:27
|vpiName:FPGA_VENDOR
|STRING:"xilinx"
|vpiParameter:
\_parameter: (GC_UNIT_ID), line:196
|vpiName:GC_UNIT_ID
|INT:4
|vpiParameter:
\_parameter: (ICACHE_LINES), line:121
|vpiName:ICACHE_LINES
|INT:2
|vpiParameter:
\_parameter: (ICACHE_LINE_ADDR_W), line:123
|vpiName:ICACHE_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_LINE_W), line:124
|vpiName:ICACHE_LINE_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_SUB_LINE_ADDR_W), line:125
|vpiName:ICACHE_SUB_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_TAG_W), line:126
|vpiName:ICACHE_TAG_W
|INT:-2147483648
|vpiParameter:
\_parameter: (ICACHE_WAYS), line:122
|vpiName:ICACHE_WAYS
|INT:1
|vpiParameter:
\_parameter: (ITLB_DEPTH), line:146
|vpiName:ITLB_DEPTH
|INT:32
|vpiParameter:
\_parameter: (ITLB_WAYS), line:145
|vpiName:ITLB_WAYS
|INT:4
|vpiParameter:
\_parameter: (L1_CONNECTIONS), line:177
|vpiName:L1_CONNECTIONS
|INT:9
|vpiParameter:
\_parameter: (L1_DCACHE_ID), line:178
|vpiName:L1_DCACHE_ID
|INT:4
|vpiParameter:
\_parameter: (L1_DMMU_ID), line:179
|vpiName:L1_DMMU_ID
|INT:2
|vpiParameter:
\_parameter: (L1_ICACHE_ID), line:180
|vpiName:L1_ICACHE_ID
|INT:19
|vpiParameter:
\_parameter: (L1_IMMU_ID), line:181
|vpiName:L1_IMMU_ID
|INT:0
|vpiParameter:
\_parameter: (L2_DATA_ATTRIBUTES_FIFO_DEPTH), line:41
|vpiName:L2_DATA_ATTRIBUTES_FIFO_DEPTH
|INT:16
|vpiParameter:
\_parameter: (L2_ID_W), line:46
|vpiName:L2_ID_W
|INT:3
|vpiParameter:
\_parameter: (L2_INPUT_FIFO_DEPTHS), line:34
|vpiName:L2_INPUT_FIFO_DEPTHS
|INT:4
|vpiParameter:
\_parameter: (L2_INVALIDATION_FIFO_DEPTHS), line:35
|vpiName:L2_INVALIDATION_FIFO_DEPTHS
|INT:4
|vpiParameter:
\_parameter: (L2_MEM_ADDR_FIFO_DEPTH), line:39
|vpiName:L2_MEM_ADDR_FIFO_DEPTH
|INT:8
|vpiParameter:
\_parameter: (L2_NUM_PORTS), line:26
|vpiName:L2_NUM_PORTS
|INT:2
|vpiParameter:
\_parameter: (L2_READ_RETURN_FIFO_DEPTHS), line:36
|vpiName:L2_READ_RETURN_FIFO_DEPTHS
|INT:1
|vpiParameter:
\_parameter: (L2_SUB_ID_W), line:27
|vpiName:L2_SUB_ID_W
|INT:2
|vpiParameter:
\_parameter: (LS_UNIT_WB_ID), line:191
|vpiName:LS_UNIT_WB_ID
|INT:1
|vpiParameter:
\_parameter: (MAX_INFLIGHT_COUNT), line:167
|vpiName:MAX_INFLIGHT_COUNT
|INT:19
|vpiParameter:
\_parameter: (MEMORY_ADDR_H), line:103
|vpiName:MEMORY_ADDR_H
|INT:12
|vpiParameter:
\_parameter: (MEMORY_ADDR_L), line:102
|vpiName:MEMORY_ADDR_L
|INT:11
|vpiParameter:
\_parameter: (MEMORY_BIT_CHECK), line:104
|vpiName:MEMORY_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (MUL_UNIT_WB_ID), line:193
|vpiName:MUL_UNIT_WB_ID
|INT:512
|vpiParameter:
\_parameter: (NUM_UNITS), line:188
|vpiName:NUM_UNITS
|INT:2
|vpiParameter:
\_parameter: (NUM_WB_UNITS), line:186
|vpiName:NUM_WB_UNITS
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (RAS_DEPTH), line:161
|vpiName:RAS_DEPTH
|INT:2
|vpiParameter:
\_parameter: (RESET_VEC), line:39
|vpiName:RESET_VEC
|INT:-2147483648
|vpiParameter:
\_parameter: (SCRATCH_ADDR_H), line:99
|vpiName:SCRATCH_ADDR_H
|INT:9
|vpiParameter:
\_parameter: (SCRATCH_ADDR_L), line:98
|vpiName:SCRATCH_ADDR_L
|INT:8
|vpiParameter:
\_parameter: (SCRATCH_BIT_CHECK), line:100
|vpiName:SCRATCH_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (USE_AMO), line:70
|vpiName:USE_AMO
|INT:1
|vpiParameter:
\_parameter: (USE_BRANCH_PREDICTOR), line:158
|vpiName:USE_BRANCH_PREDICTOR
|INT:2
|vpiParameter:
\_parameter: (USE_BUS), line:88
|vpiName:USE_BUS
|INT:4
|vpiParameter:
\_parameter: (USE_DCACHE), line:92
|vpiName:USE_DCACHE
|INT:6
|vpiParameter:
\_parameter: (USE_DIV), line:49
|vpiName:USE_DIV
|INT:1
|vpiParameter:
\_parameter: (USE_DTAG_INVALIDATIONS), line:140
|vpiName:USE_DTAG_INVALIDATIONS
|INT:1879048191
|vpiParameter:
\_parameter: (USE_D_SCRATCH_MEM), line:79
|vpiName:USE_D_SCRATCH_MEM
|INT:3
|vpiParameter:
\_parameter: (USE_ICACHE), line:93
|vpiName:USE_ICACHE
|INT:7
|vpiParameter:
\_parameter: (USE_I_SCRATCH_MEM), line:78
|vpiName:USE_I_SCRATCH_MEM
|INT:2
|vpiParameter:
\_parameter: (USE_MUL), line:48
|vpiName:USE_MUL
|INT:1
|vpiParameter:
\_parameter: (WB_UNITS_WIDTH), line:187
|vpiName:WB_UNITS_WIDTH
|INT:32
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiParameter:
\_parameter: (i), line:180
|vpiName:i
|INT:4
|vpiGenScopeArray:
\_gen_scope_array: (genblk8[5]), line:180, parent:arb
|vpiName:genblk8[5]
|vpiFullName:work@taiga_wrapper.cpu.genblk1.arb.genblk8[5]
|vpiGenScope:
\_gen_scope: , parent:genblk8[5]
|vpiFullName:work@taiga_wrapper.cpu.genblk1.arb.genblk8[5]
|vpiContAssign:
\_cont_assign: , line:181
|vpiRhs:
\_ref_obj: (l2.rd_data), line:181
|vpiName:l2.rd_data
|vpiFullName:work@taiga_wrapper.cpu.genblk1.arb.genblk8[5].l2.rd_data
|vpiLhs:
\_ref_obj: (l1_response[i].data), line:181
|vpiName:l1_response[i].data
|vpiFullName:work@taiga_wrapper.cpu.genblk1.arb.genblk8[5].l1_response[i].data
|vpiContAssign:
\_cont_assign: , line:182
|vpiRhs:
\_operation: , line:182
|vpiOpType:26
|vpiOperand:
\_ref_obj: (l2.rd_data_valid), line:182
|vpiName:l2.rd_data_valid
|vpiFullName:work@taiga_wrapper.cpu.genblk1.arb.genblk8[5].l2.rd_data_valid
|vpiOperand:
\_operation: , line:182
|vpiOpType:14
|vpiOperand:
\_ref_obj: (l2.rd_sub_id), line:182
|vpiName:l2.rd_sub_id
|vpiFullName:work@taiga_wrapper.cpu.genblk1.arb.genblk8[5].l2.rd_sub_id
|vpiOperand:
\_ref_obj: (i), line:182
|vpiName:i
|vpiFullName:work@taiga_wrapper.cpu.genblk1.arb.genblk8[5].i
|vpiLhs:
\_ref_obj: (l1_response[i].data_valid), line:182
|vpiName:l1_response[i].data_valid
|vpiFullName:work@taiga_wrapper.cpu.genblk1.arb.genblk8[5].l1_response[i].data_valid
|vpiParameter:
\_parameter: (ALU_UNIT_WB_ID), line:190
|vpiName:ALU_UNIT_WB_ID
|INT:32
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (BRANCH_PREDICTOR_WAYS), line:159
|vpiName:BRANCH_PREDICTOR_WAYS
|INT:9
|vpiParameter:
\_parameter: (BRANCH_TABLE_ENTRIES), line:160
|vpiName:BRANCH_TABLE_ENTRIES
|INT:4
|vpiParameter:
\_parameter: (BRANCH_UNIT_ID), line:195
|vpiName:BRANCH_UNIT_ID
|INT:8
|vpiParameter:
\_parameter: (BUS_ADDR_H), line:107
|vpiName:BUS_ADDR_H
|INT:1
|vpiParameter:
\_parameter: (BUS_ADDR_L), line:106
|vpiName:BUS_ADDR_L
|INT:0
|vpiParameter:
\_parameter: (BUS_BIT_CHECK), line:108
|vpiName:BUS_BIT_CHECK
|INT:1
|vpiParameter:
\_parameter: (BUS_TYPE), line:89
|vpiName:BUS_TYPE
|INT:5
|vpiParameter:
\_parameter: (COUNTER_W), line:42
|vpiName:COUNTER_W
|INT:33
|vpiParameter:
\_parameter: (CPU_ID), line:38
|vpiName:CPU_ID
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_ADDR_WIDTH), line:113
|vpiName:C_M_AXI_ADDR_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_DATA_WIDTH), line:114
|vpiName:C_M_AXI_DATA_WIDTH
|INT:1
|vpiParameter:
\_parameter: (DCACHE_LINES), line:133
|vpiName:DCACHE_LINES
|INT:-2146435073
|vpiParameter:
\_parameter: (DCACHE_LINE_ADDR_W), line:135
|vpiName:DCACHE_LINE_ADDR_W
|INT:1073741824
|vpiParameter:
\_parameter: (DCACHE_LINE_W), line:136
|vpiName:DCACHE_LINE_W
|INT:1342177279
|vpiParameter:
\_parameter: (DCACHE_SUB_LINE_ADDR_W), line:137
|vpiName:DCACHE_SUB_LINE_ADDR_W
|INT:4
|vpiParameter:
\_parameter: (DCACHE_TAG_W), line:138
|vpiName:DCACHE_TAG_W
|INT:1610612736
|vpiParameter:
\_parameter: (DCACHE_WAYS), line:134
|vpiName:DCACHE_WAYS
|INT:4
|vpiParameter:
\_parameter: (DIV_ALGORITHM), line:67
|vpiName:DIV_ALGORITHM
|INT:0
|vpiParameter:
\_parameter: (DIV_UNIT_WB_ID), line:192
|vpiName:DIV_UNIT_WB_ID
|INT:2
|vpiParameter:
\_parameter: (DTLB_DEPTH), line:152
|vpiName:DTLB_DEPTH
|INT:512
|vpiParameter:
\_parameter: (DTLB_WAYS), line:151
|vpiName:DTLB_WAYS
|INT:32
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (ENABLE_M_MODE), line:34
|vpiName:ENABLE_M_MODE
|INT:1
|vpiParameter:
\_parameter: (ENABLE_S_MODE), line:36
|vpiName:ENABLE_S_MODE
|INT:0
|vpiParameter:
\_parameter: (ENABLE_TRACE_INTERFACE), line:172
|vpiName:ENABLE_TRACE_INTERFACE
|INT:2
|vpiParameter:
\_parameter: (FETCH_BUFFER_DEPTH), line:168
|vpiName:FETCH_BUFFER_DEPTH
|INT:512
|vpiParameter:
\_parameter: (FPGA_VENDOR), line:27
|vpiName:FPGA_VENDOR
|STRING:"xilinx"
|vpiParameter:
\_parameter: (GC_UNIT_ID), line:196
|vpiName:GC_UNIT_ID
|INT:4
|vpiParameter:
\_parameter: (ICACHE_LINES), line:121
|vpiName:ICACHE_LINES
|INT:2
|vpiParameter:
\_parameter: (ICACHE_LINE_ADDR_W), line:123
|vpiName:ICACHE_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_LINE_W), line:124
|vpiName:ICACHE_LINE_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_SUB_LINE_ADDR_W), line:125
|vpiName:ICACHE_SUB_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_TAG_W), line:126
|vpiName:ICACHE_TAG_W
|INT:-2147483648
|vpiParameter:
\_parameter: (ICACHE_WAYS), line:122
|vpiName:ICACHE_WAYS
|INT:1
|vpiParameter:
\_parameter: (ITLB_DEPTH), line:146
|vpiName:ITLB_DEPTH
|INT:32
|vpiParameter:
\_parameter: (ITLB_WAYS), line:145
|vpiName:ITLB_WAYS
|INT:4
|vpiParameter:
\_parameter: (L1_CONNECTIONS), line:177
|vpiName:L1_CONNECTIONS
|INT:9
|vpiParameter:
\_parameter: (L1_DCACHE_ID), line:178
|vpiName:L1_DCACHE_ID
|INT:4
|vpiParameter:
\_parameter: (L1_DMMU_ID), line:179
|vpiName:L1_DMMU_ID
|INT:2
|vpiParameter:
\_parameter: (L1_ICACHE_ID), line:180
|vpiName:L1_ICACHE_ID
|INT:19
|vpiParameter:
\_parameter: (L1_IMMU_ID), line:181
|vpiName:L1_IMMU_ID
|INT:0
|vpiParameter:
\_parameter: (L2_DATA_ATTRIBUTES_FIFO_DEPTH), line:41
|vpiName:L2_DATA_ATTRIBUTES_FIFO_DEPTH
|INT:16
|vpiParameter:
\_parameter: (L2_ID_W), line:46
|vpiName:L2_ID_W
|INT:3
|vpiParameter:
\_parameter: (L2_INPUT_FIFO_DEPTHS), line:34
|vpiName:L2_INPUT_FIFO_DEPTHS
|INT:4
|vpiParameter:
\_parameter: (L2_INVALIDATION_FIFO_DEPTHS), line:35
|vpiName:L2_INVALIDATION_FIFO_DEPTHS
|INT:4
|vpiParameter:
\_parameter: (L2_MEM_ADDR_FIFO_DEPTH), line:39
|vpiName:L2_MEM_ADDR_FIFO_DEPTH
|INT:8
|vpiParameter:
\_parameter: (L2_NUM_PORTS), line:26
|vpiName:L2_NUM_PORTS
|INT:2
|vpiParameter:
\_parameter: (L2_READ_RETURN_FIFO_DEPTHS), line:36
|vpiName:L2_READ_RETURN_FIFO_DEPTHS
|INT:1
|vpiParameter:
\_parameter: (L2_SUB_ID_W), line:27
|vpiName:L2_SUB_ID_W
|INT:2
|vpiParameter:
\_parameter: (LS_UNIT_WB_ID), line:191
|vpiName:LS_UNIT_WB_ID
|INT:1
|vpiParameter:
\_parameter: (MAX_INFLIGHT_COUNT), line:167
|vpiName:MAX_INFLIGHT_COUNT
|INT:19
|vpiParameter:
\_parameter: (MEMORY_ADDR_H), line:103
|vpiName:MEMORY_ADDR_H
|INT:12
|vpiParameter:
\_parameter: (MEMORY_ADDR_L), line:102
|vpiName:MEMORY_ADDR_L
|INT:11
|vpiParameter:
\_parameter: (MEMORY_BIT_CHECK), line:104
|vpiName:MEMORY_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (MUL_UNIT_WB_ID), line:193
|vpiName:MUL_UNIT_WB_ID
|INT:512
|vpiParameter:
\_parameter: (NUM_UNITS), line:188
|vpiName:NUM_UNITS
|INT:2
|vpiParameter:
\_parameter: (NUM_WB_UNITS), line:186
|vpiName:NUM_WB_UNITS
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (RAS_DEPTH), line:161
|vpiName:RAS_DEPTH
|INT:2
|vpiParameter:
\_parameter: (RESET_VEC), line:39
|vpiName:RESET_VEC
|INT:-2147483648
|vpiParameter:
\_parameter: (SCRATCH_ADDR_H), line:99
|vpiName:SCRATCH_ADDR_H
|INT:9
|vpiParameter:
\_parameter: (SCRATCH_ADDR_L), line:98
|vpiName:SCRATCH_ADDR_L
|INT:8
|vpiParameter:
\_parameter: (SCRATCH_BIT_CHECK), line:100
|vpiName:SCRATCH_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (USE_AMO), line:70
|vpiName:USE_AMO
|INT:1
|vpiParameter:
\_parameter: (USE_BRANCH_PREDICTOR), line:158
|vpiName:USE_BRANCH_PREDICTOR
|INT:2
|vpiParameter:
\_parameter: (USE_BUS), line:88
|vpiName:USE_BUS
|INT:4
|vpiParameter:
\_parameter: (USE_DCACHE), line:92
|vpiName:USE_DCACHE
|INT:6
|vpiParameter:
\_parameter: (USE_DIV), line:49
|vpiName:USE_DIV
|INT:1
|vpiParameter:
\_parameter: (USE_DTAG_INVALIDATIONS), line:140
|vpiName:USE_DTAG_INVALIDATIONS
|INT:1879048191
|vpiParameter:
\_parameter: (USE_D_SCRATCH_MEM), line:79
|vpiName:USE_D_SCRATCH_MEM
|INT:3
|vpiParameter:
\_parameter: (USE_ICACHE), line:93
|vpiName:USE_ICACHE
|INT:7
|vpiParameter:
\_parameter: (USE_I_SCRATCH_MEM), line:78
|vpiName:USE_I_SCRATCH_MEM
|INT:2
|vpiParameter:
\_parameter: (USE_MUL), line:48
|vpiName:USE_MUL
|INT:1
|vpiParameter:
\_parameter: (WB_UNITS_WIDTH), line:187
|vpiName:WB_UNITS_WIDTH
|INT:32
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiParameter:
\_parameter: (i), line:180
|vpiName:i
|INT:5
|vpiGenScopeArray:
\_gen_scope_array: (genblk8[6]), line:180, parent:arb
|vpiName:genblk8[6]
|vpiFullName:work@taiga_wrapper.cpu.genblk1.arb.genblk8[6]
|vpiGenScope:
\_gen_scope: , parent:genblk8[6]
|vpiFullName:work@taiga_wrapper.cpu.genblk1.arb.genblk8[6]
|vpiContAssign:
\_cont_assign: , line:181
|vpiRhs:
\_ref_obj: (l2.rd_data), line:181
|vpiName:l2.rd_data
|vpiFullName:work@taiga_wrapper.cpu.genblk1.arb.genblk8[6].l2.rd_data
|vpiLhs:
\_ref_obj: (l1_response[i].data), line:181
|vpiName:l1_response[i].data
|vpiFullName:work@taiga_wrapper.cpu.genblk1.arb.genblk8[6].l1_response[i].data
|vpiContAssign:
\_cont_assign: , line:182
|vpiRhs:
\_operation: , line:182
|vpiOpType:26
|vpiOperand:
\_ref_obj: (l2.rd_data_valid), line:182
|vpiName:l2.rd_data_valid
|vpiFullName:work@taiga_wrapper.cpu.genblk1.arb.genblk8[6].l2.rd_data_valid
|vpiOperand:
\_operation: , line:182
|vpiOpType:14
|vpiOperand:
\_ref_obj: (l2.rd_sub_id), line:182
|vpiName:l2.rd_sub_id
|vpiFullName:work@taiga_wrapper.cpu.genblk1.arb.genblk8[6].l2.rd_sub_id
|vpiOperand:
\_ref_obj: (i), line:182
|vpiName:i
|vpiFullName:work@taiga_wrapper.cpu.genblk1.arb.genblk8[6].i
|vpiLhs:
\_ref_obj: (l1_response[i].data_valid), line:182
|vpiName:l1_response[i].data_valid
|vpiFullName:work@taiga_wrapper.cpu.genblk1.arb.genblk8[6].l1_response[i].data_valid
|vpiParameter:
\_parameter: (ALU_UNIT_WB_ID), line:190
|vpiName:ALU_UNIT_WB_ID
|INT:32
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (BRANCH_PREDICTOR_WAYS), line:159
|vpiName:BRANCH_PREDICTOR_WAYS
|INT:9
|vpiParameter:
\_parameter: (BRANCH_TABLE_ENTRIES), line:160
|vpiName:BRANCH_TABLE_ENTRIES
|INT:4
|vpiParameter:
\_parameter: (BRANCH_UNIT_ID), line:195
|vpiName:BRANCH_UNIT_ID
|INT:8
|vpiParameter:
\_parameter: (BUS_ADDR_H), line:107
|vpiName:BUS_ADDR_H
|INT:1
|vpiParameter:
\_parameter: (BUS_ADDR_L), line:106
|vpiName:BUS_ADDR_L
|INT:0
|vpiParameter:
\_parameter: (BUS_BIT_CHECK), line:108
|vpiName:BUS_BIT_CHECK
|INT:1
|vpiParameter:
\_parameter: (BUS_TYPE), line:89
|vpiName:BUS_TYPE
|INT:5
|vpiParameter:
\_parameter: (COUNTER_W), line:42
|vpiName:COUNTER_W
|INT:33
|vpiParameter:
\_parameter: (CPU_ID), line:38
|vpiName:CPU_ID
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_ADDR_WIDTH), line:113
|vpiName:C_M_AXI_ADDR_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_DATA_WIDTH), line:114
|vpiName:C_M_AXI_DATA_WIDTH
|INT:1
|vpiParameter:
\_parameter: (DCACHE_LINES), line:133
|vpiName:DCACHE_LINES
|INT:-2146435073
|vpiParameter:
\_parameter: (DCACHE_LINE_ADDR_W), line:135
|vpiName:DCACHE_LINE_ADDR_W
|INT:1073741824
|vpiParameter:
\_parameter: (DCACHE_LINE_W), line:136
|vpiName:DCACHE_LINE_W
|INT:1342177279
|vpiParameter:
\_parameter: (DCACHE_SUB_LINE_ADDR_W), line:137
|vpiName:DCACHE_SUB_LINE_ADDR_W
|INT:4
|vpiParameter:
\_parameter: (DCACHE_TAG_W), line:138
|vpiName:DCACHE_TAG_W
|INT:1610612736
|vpiParameter:
\_parameter: (DCACHE_WAYS), line:134
|vpiName:DCACHE_WAYS
|INT:4
|vpiParameter:
\_parameter: (DIV_ALGORITHM), line:67
|vpiName:DIV_ALGORITHM
|INT:0
|vpiParameter:
\_parameter: (DIV_UNIT_WB_ID), line:192
|vpiName:DIV_UNIT_WB_ID
|INT:2
|vpiParameter:
\_parameter: (DTLB_DEPTH), line:152
|vpiName:DTLB_DEPTH
|INT:512
|vpiParameter:
\_parameter: (DTLB_WAYS), line:151
|vpiName:DTLB_WAYS
|INT:32
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (ENABLE_M_MODE), line:34
|vpiName:ENABLE_M_MODE
|INT:1
|vpiParameter:
\_parameter: (ENABLE_S_MODE), line:36
|vpiName:ENABLE_S_MODE
|INT:0
|vpiParameter:
\_parameter: (ENABLE_TRACE_INTERFACE), line:172
|vpiName:ENABLE_TRACE_INTERFACE
|INT:2
|vpiParameter:
\_parameter: (FETCH_BUFFER_DEPTH), line:168
|vpiName:FETCH_BUFFER_DEPTH
|INT:512
|vpiParameter:
\_parameter: (FPGA_VENDOR), line:27
|vpiName:FPGA_VENDOR
|STRING:"xilinx"
|vpiParameter:
\_parameter: (GC_UNIT_ID), line:196
|vpiName:GC_UNIT_ID
|INT:4
|vpiParameter:
\_parameter: (ICACHE_LINES), line:121
|vpiName:ICACHE_LINES
|INT:2
|vpiParameter:
\_parameter: (ICACHE_LINE_ADDR_W), line:123
|vpiName:ICACHE_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_LINE_W), line:124
|vpiName:ICACHE_LINE_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_SUB_LINE_ADDR_W), line:125
|vpiName:ICACHE_SUB_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_TAG_W), line:126
|vpiName:ICACHE_TAG_W
|INT:-2147483648
|vpiParameter:
\_parameter: (ICACHE_WAYS), line:122
|vpiName:ICACHE_WAYS
|INT:1
|vpiParameter:
\_parameter: (ITLB_DEPTH), line:146
|vpiName:ITLB_DEPTH
|INT:32
|vpiParameter:
\_parameter: (ITLB_WAYS), line:145
|vpiName:ITLB_WAYS
|INT:4
|vpiParameter:
\_parameter: (L1_CONNECTIONS), line:177
|vpiName:L1_CONNECTIONS
|INT:9
|vpiParameter:
\_parameter: (L1_DCACHE_ID), line:178
|vpiName:L1_DCACHE_ID
|INT:4
|vpiParameter:
\_parameter: (L1_DMMU_ID), line:179
|vpiName:L1_DMMU_ID
|INT:2
|vpiParameter:
\_parameter: (L1_ICACHE_ID), line:180
|vpiName:L1_ICACHE_ID
|INT:19
|vpiParameter:
\_parameter: (L1_IMMU_ID), line:181
|vpiName:L1_IMMU_ID
|INT:0
|vpiParameter:
\_parameter: (L2_DATA_ATTRIBUTES_FIFO_DEPTH), line:41
|vpiName:L2_DATA_ATTRIBUTES_FIFO_DEPTH
|INT:16
|vpiParameter:
\_parameter: (L2_ID_W), line:46
|vpiName:L2_ID_W
|INT:3
|vpiParameter:
\_parameter: (L2_INPUT_FIFO_DEPTHS), line:34
|vpiName:L2_INPUT_FIFO_DEPTHS
|INT:4
|vpiParameter:
\_parameter: (L2_INVALIDATION_FIFO_DEPTHS), line:35
|vpiName:L2_INVALIDATION_FIFO_DEPTHS
|INT:4
|vpiParameter:
\_parameter: (L2_MEM_ADDR_FIFO_DEPTH), line:39
|vpiName:L2_MEM_ADDR_FIFO_DEPTH
|INT:8
|vpiParameter:
\_parameter: (L2_NUM_PORTS), line:26
|vpiName:L2_NUM_PORTS
|INT:2
|vpiParameter:
\_parameter: (L2_READ_RETURN_FIFO_DEPTHS), line:36
|vpiName:L2_READ_RETURN_FIFO_DEPTHS
|INT:1
|vpiParameter:
\_parameter: (L2_SUB_ID_W), line:27
|vpiName:L2_SUB_ID_W
|INT:2
|vpiParameter:
\_parameter: (LS_UNIT_WB_ID), line:191
|vpiName:LS_UNIT_WB_ID
|INT:1
|vpiParameter:
\_parameter: (MAX_INFLIGHT_COUNT), line:167
|vpiName:MAX_INFLIGHT_COUNT
|INT:19
|vpiParameter:
\_parameter: (MEMORY_ADDR_H), line:103
|vpiName:MEMORY_ADDR_H
|INT:12
|vpiParameter:
\_parameter: (MEMORY_ADDR_L), line:102
|vpiName:MEMORY_ADDR_L
|INT:11
|vpiParameter:
\_parameter: (MEMORY_BIT_CHECK), line:104
|vpiName:MEMORY_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (MUL_UNIT_WB_ID), line:193
|vpiName:MUL_UNIT_WB_ID
|INT:512
|vpiParameter:
\_parameter: (NUM_UNITS), line:188
|vpiName:NUM_UNITS
|INT:2
|vpiParameter:
\_parameter: (NUM_WB_UNITS), line:186
|vpiName:NUM_WB_UNITS
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (RAS_DEPTH), line:161
|vpiName:RAS_DEPTH
|INT:2
|vpiParameter:
\_parameter: (RESET_VEC), line:39
|vpiName:RESET_VEC
|INT:-2147483648
|vpiParameter:
\_parameter: (SCRATCH_ADDR_H), line:99
|vpiName:SCRATCH_ADDR_H
|INT:9
|vpiParameter:
\_parameter: (SCRATCH_ADDR_L), line:98
|vpiName:SCRATCH_ADDR_L
|INT:8
|vpiParameter:
\_parameter: (SCRATCH_BIT_CHECK), line:100
|vpiName:SCRATCH_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (USE_AMO), line:70
|vpiName:USE_AMO
|INT:1
|vpiParameter:
\_parameter: (USE_BRANCH_PREDICTOR), line:158
|vpiName:USE_BRANCH_PREDICTOR
|INT:2
|vpiParameter:
\_parameter: (USE_BUS), line:88
|vpiName:USE_BUS
|INT:4
|vpiParameter:
\_parameter: (USE_DCACHE), line:92
|vpiName:USE_DCACHE
|INT:6
|vpiParameter:
\_parameter: (USE_DIV), line:49
|vpiName:USE_DIV
|INT:1
|vpiParameter:
\_parameter: (USE_DTAG_INVALIDATIONS), line:140
|vpiName:USE_DTAG_INVALIDATIONS
|INT:1879048191
|vpiParameter:
\_parameter: (USE_D_SCRATCH_MEM), line:79
|vpiName:USE_D_SCRATCH_MEM
|INT:3
|vpiParameter:
\_parameter: (USE_ICACHE), line:93
|vpiName:USE_ICACHE
|INT:7
|vpiParameter:
\_parameter: (USE_I_SCRATCH_MEM), line:78
|vpiName:USE_I_SCRATCH_MEM
|INT:2
|vpiParameter:
\_parameter: (USE_MUL), line:48
|vpiName:USE_MUL
|INT:1
|vpiParameter:
\_parameter: (WB_UNITS_WIDTH), line:187
|vpiName:WB_UNITS_WIDTH
|INT:32
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiParameter:
\_parameter: (i), line:180
|vpiName:i
|INT:6
|vpiGenScopeArray:
\_gen_scope_array: (genblk8[7]), line:180, parent:arb
|vpiName:genblk8[7]
|vpiFullName:work@taiga_wrapper.cpu.genblk1.arb.genblk8[7]
|vpiGenScope:
\_gen_scope: , parent:genblk8[7]
|vpiFullName:work@taiga_wrapper.cpu.genblk1.arb.genblk8[7]
|vpiContAssign:
\_cont_assign: , line:181
|vpiRhs:
\_ref_obj: (l2.rd_data), line:181
|vpiName:l2.rd_data
|vpiFullName:work@taiga_wrapper.cpu.genblk1.arb.genblk8[7].l2.rd_data
|vpiLhs:
\_ref_obj: (l1_response[i].data), line:181
|vpiName:l1_response[i].data
|vpiFullName:work@taiga_wrapper.cpu.genblk1.arb.genblk8[7].l1_response[i].data
|vpiContAssign:
\_cont_assign: , line:182
|vpiRhs:
\_operation: , line:182
|vpiOpType:26
|vpiOperand:
\_ref_obj: (l2.rd_data_valid), line:182
|vpiName:l2.rd_data_valid
|vpiFullName:work@taiga_wrapper.cpu.genblk1.arb.genblk8[7].l2.rd_data_valid
|vpiOperand:
\_operation: , line:182
|vpiOpType:14
|vpiOperand:
\_ref_obj: (l2.rd_sub_id), line:182
|vpiName:l2.rd_sub_id
|vpiFullName:work@taiga_wrapper.cpu.genblk1.arb.genblk8[7].l2.rd_sub_id
|vpiOperand:
\_ref_obj: (i), line:182
|vpiName:i
|vpiFullName:work@taiga_wrapper.cpu.genblk1.arb.genblk8[7].i
|vpiLhs:
\_ref_obj: (l1_response[i].data_valid), line:182
|vpiName:l1_response[i].data_valid
|vpiFullName:work@taiga_wrapper.cpu.genblk1.arb.genblk8[7].l1_response[i].data_valid
|vpiParameter:
\_parameter: (ALU_UNIT_WB_ID), line:190
|vpiName:ALU_UNIT_WB_ID
|INT:32
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (BRANCH_PREDICTOR_WAYS), line:159
|vpiName:BRANCH_PREDICTOR_WAYS
|INT:9
|vpiParameter:
\_parameter: (BRANCH_TABLE_ENTRIES), line:160
|vpiName:BRANCH_TABLE_ENTRIES
|INT:4
|vpiParameter:
\_parameter: (BRANCH_UNIT_ID), line:195
|vpiName:BRANCH_UNIT_ID
|INT:8
|vpiParameter:
\_parameter: (BUS_ADDR_H), line:107
|vpiName:BUS_ADDR_H
|INT:1
|vpiParameter:
\_parameter: (BUS_ADDR_L), line:106
|vpiName:BUS_ADDR_L
|INT:0
|vpiParameter:
\_parameter: (BUS_BIT_CHECK), line:108
|vpiName:BUS_BIT_CHECK
|INT:1
|vpiParameter:
\_parameter: (BUS_TYPE), line:89
|vpiName:BUS_TYPE
|INT:5
|vpiParameter:
\_parameter: (COUNTER_W), line:42
|vpiName:COUNTER_W
|INT:33
|vpiParameter:
\_parameter: (CPU_ID), line:38
|vpiName:CPU_ID
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_ADDR_WIDTH), line:113
|vpiName:C_M_AXI_ADDR_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_DATA_WIDTH), line:114
|vpiName:C_M_AXI_DATA_WIDTH
|INT:1
|vpiParameter:
\_parameter: (DCACHE_LINES), line:133
|vpiName:DCACHE_LINES
|INT:-2146435073
|vpiParameter:
\_parameter: (DCACHE_LINE_ADDR_W), line:135
|vpiName:DCACHE_LINE_ADDR_W
|INT:1073741824
|vpiParameter:
\_parameter: (DCACHE_LINE_W), line:136
|vpiName:DCACHE_LINE_W
|INT:1342177279
|vpiParameter:
\_parameter: (DCACHE_SUB_LINE_ADDR_W), line:137
|vpiName:DCACHE_SUB_LINE_ADDR_W
|INT:4
|vpiParameter:
\_parameter: (DCACHE_TAG_W), line:138
|vpiName:DCACHE_TAG_W
|INT:1610612736
|vpiParameter:
\_parameter: (DCACHE_WAYS), line:134
|vpiName:DCACHE_WAYS
|INT:4
|vpiParameter:
\_parameter: (DIV_ALGORITHM), line:67
|vpiName:DIV_ALGORITHM
|INT:0
|vpiParameter:
\_parameter: (DIV_UNIT_WB_ID), line:192
|vpiName:DIV_UNIT_WB_ID
|INT:2
|vpiParameter:
\_parameter: (DTLB_DEPTH), line:152
|vpiName:DTLB_DEPTH
|INT:512
|vpiParameter:
\_parameter: (DTLB_WAYS), line:151
|vpiName:DTLB_WAYS
|INT:32
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (ENABLE_M_MODE), line:34
|vpiName:ENABLE_M_MODE
|INT:1
|vpiParameter:
\_parameter: (ENABLE_S_MODE), line:36
|vpiName:ENABLE_S_MODE
|INT:0
|vpiParameter:
\_parameter: (ENABLE_TRACE_INTERFACE), line:172
|vpiName:ENABLE_TRACE_INTERFACE
|INT:2
|vpiParameter:
\_parameter: (FETCH_BUFFER_DEPTH), line:168
|vpiName:FETCH_BUFFER_DEPTH
|INT:512
|vpiParameter:
\_parameter: (FPGA_VENDOR), line:27
|vpiName:FPGA_VENDOR
|STRING:"xilinx"
|vpiParameter:
\_parameter: (GC_UNIT_ID), line:196
|vpiName:GC_UNIT_ID
|INT:4
|vpiParameter:
\_parameter: (ICACHE_LINES), line:121
|vpiName:ICACHE_LINES
|INT:2
|vpiParameter:
\_parameter: (ICACHE_LINE_ADDR_W), line:123
|vpiName:ICACHE_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_LINE_W), line:124
|vpiName:ICACHE_LINE_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_SUB_LINE_ADDR_W), line:125
|vpiName:ICACHE_SUB_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_TAG_W), line:126
|vpiName:ICACHE_TAG_W
|INT:-2147483648
|vpiParameter:
\_parameter: (ICACHE_WAYS), line:122
|vpiName:ICACHE_WAYS
|INT:1
|vpiParameter:
\_parameter: (ITLB_DEPTH), line:146
|vpiName:ITLB_DEPTH
|INT:32
|vpiParameter:
\_parameter: (ITLB_WAYS), line:145
|vpiName:ITLB_WAYS
|INT:4
|vpiParameter:
\_parameter: (L1_CONNECTIONS), line:177
|vpiName:L1_CONNECTIONS
|INT:9
|vpiParameter:
\_parameter: (L1_DCACHE_ID), line:178
|vpiName:L1_DCACHE_ID
|INT:4
|vpiParameter:
\_parameter: (L1_DMMU_ID), line:179
|vpiName:L1_DMMU_ID
|INT:2
|vpiParameter:
\_parameter: (L1_ICACHE_ID), line:180
|vpiName:L1_ICACHE_ID
|INT:19
|vpiParameter:
\_parameter: (L1_IMMU_ID), line:181
|vpiName:L1_IMMU_ID
|INT:0
|vpiParameter:
\_parameter: (L2_DATA_ATTRIBUTES_FIFO_DEPTH), line:41
|vpiName:L2_DATA_ATTRIBUTES_FIFO_DEPTH
|INT:16
|vpiParameter:
\_parameter: (L2_ID_W), line:46
|vpiName:L2_ID_W
|INT:3
|vpiParameter:
\_parameter: (L2_INPUT_FIFO_DEPTHS), line:34
|vpiName:L2_INPUT_FIFO_DEPTHS
|INT:4
|vpiParameter:
\_parameter: (L2_INVALIDATION_FIFO_DEPTHS), line:35
|vpiName:L2_INVALIDATION_FIFO_DEPTHS
|INT:4
|vpiParameter:
\_parameter: (L2_MEM_ADDR_FIFO_DEPTH), line:39
|vpiName:L2_MEM_ADDR_FIFO_DEPTH
|INT:8
|vpiParameter:
\_parameter: (L2_NUM_PORTS), line:26
|vpiName:L2_NUM_PORTS
|INT:2
|vpiParameter:
\_parameter: (L2_READ_RETURN_FIFO_DEPTHS), line:36
|vpiName:L2_READ_RETURN_FIFO_DEPTHS
|INT:1
|vpiParameter:
\_parameter: (L2_SUB_ID_W), line:27
|vpiName:L2_SUB_ID_W
|INT:2
|vpiParameter:
\_parameter: (LS_UNIT_WB_ID), line:191
|vpiName:LS_UNIT_WB_ID
|INT:1
|vpiParameter:
\_parameter: (MAX_INFLIGHT_COUNT), line:167
|vpiName:MAX_INFLIGHT_COUNT
|INT:19
|vpiParameter:
\_parameter: (MEMORY_ADDR_H), line:103
|vpiName:MEMORY_ADDR_H
|INT:12
|vpiParameter:
\_parameter: (MEMORY_ADDR_L), line:102
|vpiName:MEMORY_ADDR_L
|INT:11
|vpiParameter:
\_parameter: (MEMORY_BIT_CHECK), line:104
|vpiName:MEMORY_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (MUL_UNIT_WB_ID), line:193
|vpiName:MUL_UNIT_WB_ID
|INT:512
|vpiParameter:
\_parameter: (NUM_UNITS), line:188
|vpiName:NUM_UNITS
|INT:2
|vpiParameter:
\_parameter: (NUM_WB_UNITS), line:186
|vpiName:NUM_WB_UNITS
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (RAS_DEPTH), line:161
|vpiName:RAS_DEPTH
|INT:2
|vpiParameter:
\_parameter: (RESET_VEC), line:39
|vpiName:RESET_VEC
|INT:-2147483648
|vpiParameter:
\_parameter: (SCRATCH_ADDR_H), line:99
|vpiName:SCRATCH_ADDR_H
|INT:9
|vpiParameter:
\_parameter: (SCRATCH_ADDR_L), line:98
|vpiName:SCRATCH_ADDR_L
|INT:8
|vpiParameter:
\_parameter: (SCRATCH_BIT_CHECK), line:100
|vpiName:SCRATCH_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (USE_AMO), line:70
|vpiName:USE_AMO
|INT:1
|vpiParameter:
\_parameter: (USE_BRANCH_PREDICTOR), line:158
|vpiName:USE_BRANCH_PREDICTOR
|INT:2
|vpiParameter:
\_parameter: (USE_BUS), line:88
|vpiName:USE_BUS
|INT:4
|vpiParameter:
\_parameter: (USE_DCACHE), line:92
|vpiName:USE_DCACHE
|INT:6
|vpiParameter:
\_parameter: (USE_DIV), line:49
|vpiName:USE_DIV
|INT:1
|vpiParameter:
\_parameter: (USE_DTAG_INVALIDATIONS), line:140
|vpiName:USE_DTAG_INVALIDATIONS
|INT:1879048191
|vpiParameter:
\_parameter: (USE_D_SCRATCH_MEM), line:79
|vpiName:USE_D_SCRATCH_MEM
|INT:3
|vpiParameter:
\_parameter: (USE_ICACHE), line:93
|vpiName:USE_ICACHE
|INT:7
|vpiParameter:
\_parameter: (USE_I_SCRATCH_MEM), line:78
|vpiName:USE_I_SCRATCH_MEM
|INT:2
|vpiParameter:
\_parameter: (USE_MUL), line:48
|vpiName:USE_MUL
|INT:1
|vpiParameter:
\_parameter: (WB_UNITS_WIDTH), line:187
|vpiName:WB_UNITS_WIDTH
|INT:32
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiParameter:
\_parameter: (i), line:180
|vpiName:i
|INT:7
|vpiGenScopeArray:
\_gen_scope_array: (genblk8[8]), line:180, parent:arb
|vpiName:genblk8[8]
|vpiFullName:work@taiga_wrapper.cpu.genblk1.arb.genblk8[8]
|vpiGenScope:
\_gen_scope: , parent:genblk8[8]
|vpiFullName:work@taiga_wrapper.cpu.genblk1.arb.genblk8[8]
|vpiContAssign:
\_cont_assign: , line:181
|vpiRhs:
\_ref_obj: (l2.rd_data), line:181
|vpiName:l2.rd_data
|vpiFullName:work@taiga_wrapper.cpu.genblk1.arb.genblk8[8].l2.rd_data
|vpiLhs:
\_ref_obj: (l1_response[i].data), line:181
|vpiName:l1_response[i].data
|vpiFullName:work@taiga_wrapper.cpu.genblk1.arb.genblk8[8].l1_response[i].data
|vpiContAssign:
\_cont_assign: , line:182
|vpiRhs:
\_operation: , line:182
|vpiOpType:26
|vpiOperand:
\_ref_obj: (l2.rd_data_valid), line:182
|vpiName:l2.rd_data_valid
|vpiFullName:work@taiga_wrapper.cpu.genblk1.arb.genblk8[8].l2.rd_data_valid
|vpiOperand:
\_operation: , line:182
|vpiOpType:14
|vpiOperand:
\_ref_obj: (l2.rd_sub_id), line:182
|vpiName:l2.rd_sub_id
|vpiFullName:work@taiga_wrapper.cpu.genblk1.arb.genblk8[8].l2.rd_sub_id
|vpiOperand:
\_ref_obj: (i), line:182
|vpiName:i
|vpiFullName:work@taiga_wrapper.cpu.genblk1.arb.genblk8[8].i
|vpiLhs:
\_ref_obj: (l1_response[i].data_valid), line:182
|vpiName:l1_response[i].data_valid
|vpiFullName:work@taiga_wrapper.cpu.genblk1.arb.genblk8[8].l1_response[i].data_valid
|vpiParameter:
\_parameter: (ALU_UNIT_WB_ID), line:190
|vpiName:ALU_UNIT_WB_ID
|INT:32
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (BRANCH_PREDICTOR_WAYS), line:159
|vpiName:BRANCH_PREDICTOR_WAYS
|INT:9
|vpiParameter:
\_parameter: (BRANCH_TABLE_ENTRIES), line:160
|vpiName:BRANCH_TABLE_ENTRIES
|INT:4
|vpiParameter:
\_parameter: (BRANCH_UNIT_ID), line:195
|vpiName:BRANCH_UNIT_ID
|INT:8
|vpiParameter:
\_parameter: (BUS_ADDR_H), line:107
|vpiName:BUS_ADDR_H
|INT:1
|vpiParameter:
\_parameter: (BUS_ADDR_L), line:106
|vpiName:BUS_ADDR_L
|INT:0
|vpiParameter:
\_parameter: (BUS_BIT_CHECK), line:108
|vpiName:BUS_BIT_CHECK
|INT:1
|vpiParameter:
\_parameter: (BUS_TYPE), line:89
|vpiName:BUS_TYPE
|INT:5
|vpiParameter:
\_parameter: (COUNTER_W), line:42
|vpiName:COUNTER_W
|INT:33
|vpiParameter:
\_parameter: (CPU_ID), line:38
|vpiName:CPU_ID
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_ADDR_WIDTH), line:113
|vpiName:C_M_AXI_ADDR_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_DATA_WIDTH), line:114
|vpiName:C_M_AXI_DATA_WIDTH
|INT:1
|vpiParameter:
\_parameter: (DCACHE_LINES), line:133
|vpiName:DCACHE_LINES
|INT:-2146435073
|vpiParameter:
\_parameter: (DCACHE_LINE_ADDR_W), line:135
|vpiName:DCACHE_LINE_ADDR_W
|INT:1073741824
|vpiParameter:
\_parameter: (DCACHE_LINE_W), line:136
|vpiName:DCACHE_LINE_W
|INT:1342177279
|vpiParameter:
\_parameter: (DCACHE_SUB_LINE_ADDR_W), line:137
|vpiName:DCACHE_SUB_LINE_ADDR_W
|INT:4
|vpiParameter:
\_parameter: (DCACHE_TAG_W), line:138
|vpiName:DCACHE_TAG_W
|INT:1610612736
|vpiParameter:
\_parameter: (DCACHE_WAYS), line:134
|vpiName:DCACHE_WAYS
|INT:4
|vpiParameter:
\_parameter: (DIV_ALGORITHM), line:67
|vpiName:DIV_ALGORITHM
|INT:0
|vpiParameter:
\_parameter: (DIV_UNIT_WB_ID), line:192
|vpiName:DIV_UNIT_WB_ID
|INT:2
|vpiParameter:
\_parameter: (DTLB_DEPTH), line:152
|vpiName:DTLB_DEPTH
|INT:512
|vpiParameter:
\_parameter: (DTLB_WAYS), line:151
|vpiName:DTLB_WAYS
|INT:32
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (ENABLE_M_MODE), line:34
|vpiName:ENABLE_M_MODE
|INT:1
|vpiParameter:
\_parameter: (ENABLE_S_MODE), line:36
|vpiName:ENABLE_S_MODE
|INT:0
|vpiParameter:
\_parameter: (ENABLE_TRACE_INTERFACE), line:172
|vpiName:ENABLE_TRACE_INTERFACE
|INT:2
|vpiParameter:
\_parameter: (FETCH_BUFFER_DEPTH), line:168
|vpiName:FETCH_BUFFER_DEPTH
|INT:512
|vpiParameter:
\_parameter: (FPGA_VENDOR), line:27
|vpiName:FPGA_VENDOR
|STRING:"xilinx"
|vpiParameter:
\_parameter: (GC_UNIT_ID), line:196
|vpiName:GC_UNIT_ID
|INT:4
|vpiParameter:
\_parameter: (ICACHE_LINES), line:121
|vpiName:ICACHE_LINES
|INT:2
|vpiParameter:
\_parameter: (ICACHE_LINE_ADDR_W), line:123
|vpiName:ICACHE_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_LINE_W), line:124
|vpiName:ICACHE_LINE_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_SUB_LINE_ADDR_W), line:125
|vpiName:ICACHE_SUB_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_TAG_W), line:126
|vpiName:ICACHE_TAG_W
|INT:-2147483648
|vpiParameter:
\_parameter: (ICACHE_WAYS), line:122
|vpiName:ICACHE_WAYS
|INT:1
|vpiParameter:
\_parameter: (ITLB_DEPTH), line:146
|vpiName:ITLB_DEPTH
|INT:32
|vpiParameter:
\_parameter: (ITLB_WAYS), line:145
|vpiName:ITLB_WAYS
|INT:4
|vpiParameter:
\_parameter: (L1_CONNECTIONS), line:177
|vpiName:L1_CONNECTIONS
|INT:9
|vpiParameter:
\_parameter: (L1_DCACHE_ID), line:178
|vpiName:L1_DCACHE_ID
|INT:4
|vpiParameter:
\_parameter: (L1_DMMU_ID), line:179
|vpiName:L1_DMMU_ID
|INT:2
|vpiParameter:
\_parameter: (L1_ICACHE_ID), line:180
|vpiName:L1_ICACHE_ID
|INT:19
|vpiParameter:
\_parameter: (L1_IMMU_ID), line:181
|vpiName:L1_IMMU_ID
|INT:0
|vpiParameter:
\_parameter: (L2_DATA_ATTRIBUTES_FIFO_DEPTH), line:41
|vpiName:L2_DATA_ATTRIBUTES_FIFO_DEPTH
|INT:16
|vpiParameter:
\_parameter: (L2_ID_W), line:46
|vpiName:L2_ID_W
|INT:3
|vpiParameter:
\_parameter: (L2_INPUT_FIFO_DEPTHS), line:34
|vpiName:L2_INPUT_FIFO_DEPTHS
|INT:4
|vpiParameter:
\_parameter: (L2_INVALIDATION_FIFO_DEPTHS), line:35
|vpiName:L2_INVALIDATION_FIFO_DEPTHS
|INT:4
|vpiParameter:
\_parameter: (L2_MEM_ADDR_FIFO_DEPTH), line:39
|vpiName:L2_MEM_ADDR_FIFO_DEPTH
|INT:8
|vpiParameter:
\_parameter: (L2_NUM_PORTS), line:26
|vpiName:L2_NUM_PORTS
|INT:2
|vpiParameter:
\_parameter: (L2_READ_RETURN_FIFO_DEPTHS), line:36
|vpiName:L2_READ_RETURN_FIFO_DEPTHS
|INT:1
|vpiParameter:
\_parameter: (L2_SUB_ID_W), line:27
|vpiName:L2_SUB_ID_W
|INT:2
|vpiParameter:
\_parameter: (LS_UNIT_WB_ID), line:191
|vpiName:LS_UNIT_WB_ID
|INT:1
|vpiParameter:
\_parameter: (MAX_INFLIGHT_COUNT), line:167
|vpiName:MAX_INFLIGHT_COUNT
|INT:19
|vpiParameter:
\_parameter: (MEMORY_ADDR_H), line:103
|vpiName:MEMORY_ADDR_H
|INT:12
|vpiParameter:
\_parameter: (MEMORY_ADDR_L), line:102
|vpiName:MEMORY_ADDR_L
|INT:11
|vpiParameter:
\_parameter: (MEMORY_BIT_CHECK), line:104
|vpiName:MEMORY_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (MUL_UNIT_WB_ID), line:193
|vpiName:MUL_UNIT_WB_ID
|INT:512
|vpiParameter:
\_parameter: (NUM_UNITS), line:188
|vpiName:NUM_UNITS
|INT:2
|vpiParameter:
\_parameter: (NUM_WB_UNITS), line:186
|vpiName:NUM_WB_UNITS
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (RAS_DEPTH), line:161
|vpiName:RAS_DEPTH
|INT:2
|vpiParameter:
\_parameter: (RESET_VEC), line:39
|vpiName:RESET_VEC
|INT:-2147483648
|vpiParameter:
\_parameter: (SCRATCH_ADDR_H), line:99
|vpiName:SCRATCH_ADDR_H
|INT:9
|vpiParameter:
\_parameter: (SCRATCH_ADDR_L), line:98
|vpiName:SCRATCH_ADDR_L
|INT:8
|vpiParameter:
\_parameter: (SCRATCH_BIT_CHECK), line:100
|vpiName:SCRATCH_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (USE_AMO), line:70
|vpiName:USE_AMO
|INT:1
|vpiParameter:
\_parameter: (USE_BRANCH_PREDICTOR), line:158
|vpiName:USE_BRANCH_PREDICTOR
|INT:2
|vpiParameter:
\_parameter: (USE_BUS), line:88
|vpiName:USE_BUS
|INT:4
|vpiParameter:
\_parameter: (USE_DCACHE), line:92
|vpiName:USE_DCACHE
|INT:6
|vpiParameter:
\_parameter: (USE_DIV), line:49
|vpiName:USE_DIV
|INT:1
|vpiParameter:
\_parameter: (USE_DTAG_INVALIDATIONS), line:140
|vpiName:USE_DTAG_INVALIDATIONS
|INT:1879048191
|vpiParameter:
\_parameter: (USE_D_SCRATCH_MEM), line:79
|vpiName:USE_D_SCRATCH_MEM
|INT:3
|vpiParameter:
\_parameter: (USE_ICACHE), line:93
|vpiName:USE_ICACHE
|INT:7
|vpiParameter:
\_parameter: (USE_I_SCRATCH_MEM), line:78
|vpiName:USE_I_SCRATCH_MEM
|INT:2
|vpiParameter:
\_parameter: (USE_MUL), line:48
|vpiName:USE_MUL
|INT:1
|vpiParameter:
\_parameter: (WB_UNITS_WIDTH), line:187
|vpiName:WB_UNITS_WIDTH
|INT:32
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiParameter:
\_parameter: (i), line:180
|vpiName:i
|INT:8
|vpiNet:
\_logic_net: (clk), line:29, parent:arb
|vpiNet:
\_logic_net: (rst), line:30, parent:arb
|vpiNet:
\_logic_net: (sc_complete), line:34, parent:arb
|vpiNet:
\_logic_net: (sc_success), line:35, parent:arb
|vpiNet:
\_logic_net: (l2_requests), line:41, parent:arb
|vpiName:l2_requests
|vpiFullName:work@taiga_wrapper.cpu.genblk1.arb.l2_requests
|vpiRange:
\_range: , line:41
|vpiLeftRange:
\_constant: , line:41
|vpiConstType:7
|vpiDecompile:8
|vpiSize:32
|INT:8
|vpiRightRange:
\_constant: , line:41
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (requests), line:43, parent:arb
|vpiName:requests
|vpiFullName:work@taiga_wrapper.cpu.genblk1.arb.requests
|vpiNetType:36
|vpiRange:
\_range: , line:43
|vpiLeftRange:
\_constant: , line:43
|vpiConstType:7
|vpiDecompile:8
|vpiSize:32
|INT:8
|vpiRightRange:
\_constant: , line:43
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (acks), line:44, parent:arb
|vpiName:acks
|vpiFullName:work@taiga_wrapper.cpu.genblk1.arb.acks
|vpiNetType:36
|vpiRange:
\_range: , line:44
|vpiLeftRange:
\_constant: , line:44
|vpiConstType:7
|vpiDecompile:8
|vpiSize:32
|INT:8
|vpiRightRange:
\_constant: , line:44
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (push_ready), line:46, parent:arb
|vpiName:push_ready
|vpiFullName:work@taiga_wrapper.cpu.genblk1.arb.push_ready
|vpiNetType:36
|vpiNet:
\_logic_net: (request_exists), line:47, parent:arb
|vpiName:request_exists
|vpiFullName:work@taiga_wrapper.cpu.genblk1.arb.request_exists
|vpiNetType:36
|vpiNet:
\_logic_net: (busy), line:75, parent:arb
|vpiName:busy
|vpiFullName:work@taiga_wrapper.cpu.genblk1.arb.busy
|vpiNetType:36
|vpiNet:
\_logic_net: (l2), line:32, parent:arb
|vpiName:l2
|vpiFullName:work@taiga_wrapper.cpu.genblk1.arb.l2
|vpiNet:
\_logic_net: (l1_request), line:37, parent:arb
|vpiName:l1_request
|vpiFullName:work@taiga_wrapper.cpu.genblk1.arb.l1_request
|vpiNet:
\_logic_net: (l1_response), line:38, parent:arb
|vpiName:l1_response
|vpiFullName:work@taiga_wrapper.cpu.genblk1.arb.l1_response
|vpiParameter:
\_parameter: (ALU_UNIT_WB_ID), line:190
|vpiName:ALU_UNIT_WB_ID
|INT:32
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (BRANCH_PREDICTOR_WAYS), line:159
|vpiName:BRANCH_PREDICTOR_WAYS
|INT:9
|vpiParameter:
\_parameter: (BRANCH_TABLE_ENTRIES), line:160
|vpiName:BRANCH_TABLE_ENTRIES
|INT:4
|vpiParameter:
\_parameter: (BRANCH_UNIT_ID), line:195
|vpiName:BRANCH_UNIT_ID
|INT:8
|vpiParameter:
\_parameter: (BUS_ADDR_H), line:107
|vpiName:BUS_ADDR_H
|INT:1
|vpiParameter:
\_parameter: (BUS_ADDR_L), line:106
|vpiName:BUS_ADDR_L
|INT:0
|vpiParameter:
\_parameter: (BUS_BIT_CHECK), line:108
|vpiName:BUS_BIT_CHECK
|INT:1
|vpiParameter:
\_parameter: (BUS_TYPE), line:89
|vpiName:BUS_TYPE
|INT:5
|vpiParameter:
\_parameter: (COUNTER_W), line:42
|vpiName:COUNTER_W
|INT:33
|vpiParameter:
\_parameter: (CPU_ID), line:38
|vpiName:CPU_ID
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_ADDR_WIDTH), line:113
|vpiName:C_M_AXI_ADDR_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_DATA_WIDTH), line:114
|vpiName:C_M_AXI_DATA_WIDTH
|INT:1
|vpiParameter:
\_parameter: (DCACHE_LINES), line:133
|vpiName:DCACHE_LINES
|INT:-2146435073
|vpiParameter:
\_parameter: (DCACHE_LINE_ADDR_W), line:135
|vpiName:DCACHE_LINE_ADDR_W
|INT:1073741824
|vpiParameter:
\_parameter: (DCACHE_LINE_W), line:136
|vpiName:DCACHE_LINE_W
|INT:1342177279
|vpiParameter:
\_parameter: (DCACHE_SUB_LINE_ADDR_W), line:137
|vpiName:DCACHE_SUB_LINE_ADDR_W
|INT:4
|vpiParameter:
\_parameter: (DCACHE_TAG_W), line:138
|vpiName:DCACHE_TAG_W
|INT:1610612736
|vpiParameter:
\_parameter: (DCACHE_WAYS), line:134
|vpiName:DCACHE_WAYS
|INT:4
|vpiParameter:
\_parameter: (DIV_ALGORITHM), line:67
|vpiName:DIV_ALGORITHM
|INT:0
|vpiParameter:
\_parameter: (DIV_UNIT_WB_ID), line:192
|vpiName:DIV_UNIT_WB_ID
|INT:2
|vpiParameter:
\_parameter: (DTLB_DEPTH), line:152
|vpiName:DTLB_DEPTH
|INT:512
|vpiParameter:
\_parameter: (DTLB_WAYS), line:151
|vpiName:DTLB_WAYS
|INT:32
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (ENABLE_M_MODE), line:34
|vpiName:ENABLE_M_MODE
|INT:1
|vpiParameter:
\_parameter: (ENABLE_S_MODE), line:36
|vpiName:ENABLE_S_MODE
|INT:0
|vpiParameter:
\_parameter: (ENABLE_TRACE_INTERFACE), line:172
|vpiName:ENABLE_TRACE_INTERFACE
|INT:2
|vpiParameter:
\_parameter: (FETCH_BUFFER_DEPTH), line:168
|vpiName:FETCH_BUFFER_DEPTH
|INT:512
|vpiParameter:
\_parameter: (FPGA_VENDOR), line:27
|vpiName:FPGA_VENDOR
|STRING:"xilinx"
|vpiParameter:
\_parameter: (GC_UNIT_ID), line:196
|vpiName:GC_UNIT_ID
|INT:4
|vpiParameter:
\_parameter: (ICACHE_LINES), line:121
|vpiName:ICACHE_LINES
|INT:2
|vpiParameter:
\_parameter: (ICACHE_LINE_ADDR_W), line:123
|vpiName:ICACHE_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_LINE_W), line:124
|vpiName:ICACHE_LINE_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_SUB_LINE_ADDR_W), line:125
|vpiName:ICACHE_SUB_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_TAG_W), line:126
|vpiName:ICACHE_TAG_W
|INT:-2147483648
|vpiParameter:
\_parameter: (ICACHE_WAYS), line:122
|vpiName:ICACHE_WAYS
|INT:1
|vpiParameter:
\_parameter: (ITLB_DEPTH), line:146
|vpiName:ITLB_DEPTH
|INT:32
|vpiParameter:
\_parameter: (ITLB_WAYS), line:145
|vpiName:ITLB_WAYS
|INT:4
|vpiParameter:
\_parameter: (L1_CONNECTIONS), line:177
|vpiName:L1_CONNECTIONS
|INT:9
|vpiParameter:
\_parameter: (L1_DCACHE_ID), line:178
|vpiName:L1_DCACHE_ID
|INT:4
|vpiParameter:
\_parameter: (L1_DMMU_ID), line:179
|vpiName:L1_DMMU_ID
|INT:2
|vpiParameter:
\_parameter: (L1_ICACHE_ID), line:180
|vpiName:L1_ICACHE_ID
|INT:19
|vpiParameter:
\_parameter: (L1_IMMU_ID), line:181
|vpiName:L1_IMMU_ID
|INT:0
|vpiParameter:
\_parameter: (L2_DATA_ATTRIBUTES_FIFO_DEPTH), line:41
|vpiName:L2_DATA_ATTRIBUTES_FIFO_DEPTH
|INT:16
|vpiParameter:
\_parameter: (L2_ID_W), line:46
|vpiName:L2_ID_W
|INT:3
|vpiParameter:
\_parameter: (L2_INPUT_FIFO_DEPTHS), line:34
|vpiName:L2_INPUT_FIFO_DEPTHS
|INT:4
|vpiParameter:
\_parameter: (L2_INVALIDATION_FIFO_DEPTHS), line:35
|vpiName:L2_INVALIDATION_FIFO_DEPTHS
|INT:4
|vpiParameter:
\_parameter: (L2_MEM_ADDR_FIFO_DEPTH), line:39
|vpiName:L2_MEM_ADDR_FIFO_DEPTH
|INT:8
|vpiParameter:
\_parameter: (L2_NUM_PORTS), line:26
|vpiName:L2_NUM_PORTS
|INT:2
|vpiParameter:
\_parameter: (L2_READ_RETURN_FIFO_DEPTHS), line:36
|vpiName:L2_READ_RETURN_FIFO_DEPTHS
|INT:1
|vpiParameter:
\_parameter: (L2_SUB_ID_W), line:27
|vpiName:L2_SUB_ID_W
|INT:2
|vpiParameter:
\_parameter: (LS_UNIT_WB_ID), line:191
|vpiName:LS_UNIT_WB_ID
|INT:1
|vpiParameter:
\_parameter: (MAX_INFLIGHT_COUNT), line:167
|vpiName:MAX_INFLIGHT_COUNT
|INT:19
|vpiParameter:
\_parameter: (MEMORY_ADDR_H), line:103
|vpiName:MEMORY_ADDR_H
|INT:12
|vpiParameter:
\_parameter: (MEMORY_ADDR_L), line:102
|vpiName:MEMORY_ADDR_L
|INT:11
|vpiParameter:
\_parameter: (MEMORY_BIT_CHECK), line:104
|vpiName:MEMORY_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (MUL_UNIT_WB_ID), line:193
|vpiName:MUL_UNIT_WB_ID
|INT:512
|vpiParameter:
\_parameter: (NUM_UNITS), line:188
|vpiName:NUM_UNITS
|INT:2
|vpiParameter:
\_parameter: (NUM_WB_UNITS), line:186
|vpiName:NUM_WB_UNITS
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (RAS_DEPTH), line:161
|vpiName:RAS_DEPTH
|INT:2
|vpiParameter:
\_parameter: (RESET_VEC), line:39
|vpiName:RESET_VEC
|INT:-2147483648
|vpiParameter:
\_parameter: (SCRATCH_ADDR_H), line:99
|vpiName:SCRATCH_ADDR_H
|INT:9
|vpiParameter:
\_parameter: (SCRATCH_ADDR_L), line:98
|vpiName:SCRATCH_ADDR_L
|INT:8
|vpiParameter:
\_parameter: (SCRATCH_BIT_CHECK), line:100
|vpiName:SCRATCH_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (USE_AMO), line:70
|vpiName:USE_AMO
|INT:1
|vpiParameter:
\_parameter: (USE_BRANCH_PREDICTOR), line:158
|vpiName:USE_BRANCH_PREDICTOR
|INT:2
|vpiParameter:
\_parameter: (USE_BUS), line:88
|vpiName:USE_BUS
|INT:4
|vpiParameter:
\_parameter: (USE_DCACHE), line:92
|vpiName:USE_DCACHE
|INT:6
|vpiParameter:
\_parameter: (USE_DIV), line:49
|vpiName:USE_DIV
|INT:1
|vpiParameter:
\_parameter: (USE_DTAG_INVALIDATIONS), line:140
|vpiName:USE_DTAG_INVALIDATIONS
|INT:1879048191
|vpiParameter:
\_parameter: (USE_D_SCRATCH_MEM), line:79
|vpiName:USE_D_SCRATCH_MEM
|INT:3
|vpiParameter:
\_parameter: (USE_ICACHE), line:93
|vpiName:USE_ICACHE
|INT:7
|vpiParameter:
\_parameter: (USE_I_SCRATCH_MEM), line:78
|vpiName:USE_I_SCRATCH_MEM
|INT:2
|vpiParameter:
\_parameter: (USE_MUL), line:48
|vpiName:USE_MUL
|INT:1
|vpiParameter:
\_parameter: (WB_UNITS_WIDTH), line:187
|vpiName:WB_UNITS_WIDTH
|INT:32
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiParameter:
\_parameter: (ALU_UNIT_WB_ID), line:190
|vpiName:ALU_UNIT_WB_ID
|INT:32
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (BRANCH_PREDICTOR_WAYS), line:159
|vpiName:BRANCH_PREDICTOR_WAYS
|INT:9
|vpiParameter:
\_parameter: (BRANCH_TABLE_ENTRIES), line:160
|vpiName:BRANCH_TABLE_ENTRIES
|INT:4
|vpiParameter:
\_parameter: (BRANCH_UNIT_ID), line:195
|vpiName:BRANCH_UNIT_ID
|INT:8
|vpiParameter:
\_parameter: (BUS_ADDR_H), line:107
|vpiName:BUS_ADDR_H
|INT:1
|vpiParameter:
\_parameter: (BUS_ADDR_L), line:106
|vpiName:BUS_ADDR_L
|INT:0
|vpiParameter:
\_parameter: (BUS_BIT_CHECK), line:108
|vpiName:BUS_BIT_CHECK
|INT:1
|vpiParameter:
\_parameter: (BUS_TYPE), line:89
|vpiName:BUS_TYPE
|INT:5
|vpiParameter:
\_parameter: (COUNTER_W), line:42
|vpiName:COUNTER_W
|INT:33
|vpiParameter:
\_parameter: (CPU_ID), line:38
|vpiName:CPU_ID
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_ADDR_WIDTH), line:113
|vpiName:C_M_AXI_ADDR_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_DATA_WIDTH), line:114
|vpiName:C_M_AXI_DATA_WIDTH
|INT:1
|vpiParameter:
\_parameter: (DCACHE_LINES), line:133
|vpiName:DCACHE_LINES
|INT:-2146435073
|vpiParameter:
\_parameter: (DCACHE_LINE_ADDR_W), line:135
|vpiName:DCACHE_LINE_ADDR_W
|INT:1073741824
|vpiParameter:
\_parameter: (DCACHE_LINE_W), line:136
|vpiName:DCACHE_LINE_W
|INT:1342177279
|vpiParameter:
\_parameter: (DCACHE_SUB_LINE_ADDR_W), line:137
|vpiName:DCACHE_SUB_LINE_ADDR_W
|INT:4
|vpiParameter:
\_parameter: (DCACHE_TAG_W), line:138
|vpiName:DCACHE_TAG_W
|INT:1610612736
|vpiParameter:
\_parameter: (DCACHE_WAYS), line:134
|vpiName:DCACHE_WAYS
|INT:4
|vpiParameter:
\_parameter: (DIV_ALGORITHM), line:67
|vpiName:DIV_ALGORITHM
|INT:0
|vpiParameter:
\_parameter: (DIV_UNIT_WB_ID), line:192
|vpiName:DIV_UNIT_WB_ID
|INT:2
|vpiParameter:
\_parameter: (DTLB_DEPTH), line:152
|vpiName:DTLB_DEPTH
|INT:512
|vpiParameter:
\_parameter: (DTLB_WAYS), line:151
|vpiName:DTLB_WAYS
|INT:32
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (ENABLE_M_MODE), line:34
|vpiName:ENABLE_M_MODE
|INT:1
|vpiParameter:
\_parameter: (ENABLE_S_MODE), line:36
|vpiName:ENABLE_S_MODE
|INT:0
|vpiParameter:
\_parameter: (ENABLE_TRACE_INTERFACE), line:172
|vpiName:ENABLE_TRACE_INTERFACE
|INT:2
|vpiParameter:
\_parameter: (FETCH_BUFFER_DEPTH), line:168
|vpiName:FETCH_BUFFER_DEPTH
|INT:512
|vpiParameter:
\_parameter: (FPGA_VENDOR), line:27
|vpiName:FPGA_VENDOR
|STRING:"xilinx"
|vpiParameter:
\_parameter: (GC_UNIT_ID), line:196
|vpiName:GC_UNIT_ID
|INT:4
|vpiParameter:
\_parameter: (ICACHE_LINES), line:121
|vpiName:ICACHE_LINES
|INT:2
|vpiParameter:
\_parameter: (ICACHE_LINE_ADDR_W), line:123
|vpiName:ICACHE_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_LINE_W), line:124
|vpiName:ICACHE_LINE_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_SUB_LINE_ADDR_W), line:125
|vpiName:ICACHE_SUB_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_TAG_W), line:126
|vpiName:ICACHE_TAG_W
|INT:-2147483648
|vpiParameter:
\_parameter: (ICACHE_WAYS), line:122
|vpiName:ICACHE_WAYS
|INT:1
|vpiParameter:
\_parameter: (ITLB_DEPTH), line:146
|vpiName:ITLB_DEPTH
|INT:32
|vpiParameter:
\_parameter: (ITLB_WAYS), line:145
|vpiName:ITLB_WAYS
|INT:4
|vpiParameter:
\_parameter: (L1_CONNECTIONS), line:177
|vpiName:L1_CONNECTIONS
|INT:9
|vpiParameter:
\_parameter: (L1_DCACHE_ID), line:178
|vpiName:L1_DCACHE_ID
|INT:4
|vpiParameter:
\_parameter: (L1_DMMU_ID), line:179
|vpiName:L1_DMMU_ID
|INT:2
|vpiParameter:
\_parameter: (L1_ICACHE_ID), line:180
|vpiName:L1_ICACHE_ID
|INT:19
|vpiParameter:
\_parameter: (L1_IMMU_ID), line:181
|vpiName:L1_IMMU_ID
|INT:0
|vpiParameter:
\_parameter: (LS_UNIT_WB_ID), line:191
|vpiName:LS_UNIT_WB_ID
|INT:1
|vpiParameter:
\_parameter: (MAX_INFLIGHT_COUNT), line:167
|vpiName:MAX_INFLIGHT_COUNT
|INT:19
|vpiParameter:
\_parameter: (MEMORY_ADDR_H), line:103
|vpiName:MEMORY_ADDR_H
|INT:12
|vpiParameter:
\_parameter: (MEMORY_ADDR_L), line:102
|vpiName:MEMORY_ADDR_L
|INT:11
|vpiParameter:
\_parameter: (MEMORY_BIT_CHECK), line:104
|vpiName:MEMORY_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (MUL_UNIT_WB_ID), line:193
|vpiName:MUL_UNIT_WB_ID
|INT:512
|vpiParameter:
\_parameter: (NUM_UNITS), line:188
|vpiName:NUM_UNITS
|INT:2
|vpiParameter:
\_parameter: (NUM_WB_UNITS), line:186
|vpiName:NUM_WB_UNITS
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (RAS_DEPTH), line:161
|vpiName:RAS_DEPTH
|INT:2
|vpiParameter:
\_parameter: (RESET_VEC), line:39
|vpiName:RESET_VEC
|INT:-2147483648
|vpiParameter:
\_parameter: (SCRATCH_ADDR_H), line:99
|vpiName:SCRATCH_ADDR_H
|INT:9
|vpiParameter:
\_parameter: (SCRATCH_ADDR_L), line:98
|vpiName:SCRATCH_ADDR_L
|INT:8
|vpiParameter:
\_parameter: (SCRATCH_BIT_CHECK), line:100
|vpiName:SCRATCH_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (USE_AMO), line:70
|vpiName:USE_AMO
|INT:1
|vpiParameter:
\_parameter: (USE_BRANCH_PREDICTOR), line:158
|vpiName:USE_BRANCH_PREDICTOR
|INT:2
|vpiParameter:
\_parameter: (USE_BUS), line:88
|vpiName:USE_BUS
|INT:4
|vpiParameter:
\_parameter: (USE_DCACHE), line:92
|vpiName:USE_DCACHE
|INT:6
|vpiParameter:
\_parameter: (USE_DIV), line:49
|vpiName:USE_DIV
|INT:1
|vpiParameter:
\_parameter: (USE_DTAG_INVALIDATIONS), line:140
|vpiName:USE_DTAG_INVALIDATIONS
|INT:1879048191
|vpiParameter:
\_parameter: (USE_D_SCRATCH_MEM), line:79
|vpiName:USE_D_SCRATCH_MEM
|INT:3
|vpiParameter:
\_parameter: (USE_ICACHE), line:93
|vpiName:USE_ICACHE
|INT:7
|vpiParameter:
\_parameter: (USE_I_SCRATCH_MEM), line:78
|vpiName:USE_I_SCRATCH_MEM
|INT:2
|vpiParameter:
\_parameter: (USE_MUL), line:48
|vpiName:USE_MUL
|INT:1
|vpiParameter:
\_parameter: (WB_UNITS_WIDTH), line:187
|vpiName:WB_UNITS_WIDTH
|INT:32
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiGenScopeArray:
\_gen_scope_array: (genblk2), line:167, parent:cpu
|vpiName:genblk2
|vpiFullName:work@taiga_wrapper.cpu.genblk2
|vpiGenScope:
\_gen_scope: , parent:genblk2
|vpiFullName:work@taiga_wrapper.cpu.genblk2
|vpiContAssign:
\_cont_assign: , line:168
|vpiRhs:
\_constant: , line:168
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiLhs:
\_ref_obj: (itlb.complete), line:168
|vpiName:itlb.complete
|vpiFullName:work@taiga_wrapper.cpu.genblk2.itlb.complete
|vpiContAssign:
\_cont_assign: , line:169
|vpiRhs:
\_ref_obj: (itlb.virtual_address), line:169
|vpiName:itlb.virtual_address
|vpiFullName:work@taiga_wrapper.cpu.genblk2.itlb.virtual_address
|vpiLhs:
\_ref_obj: (itlb.physical_address), line:169
|vpiName:itlb.physical_address
|vpiFullName:work@taiga_wrapper.cpu.genblk2.itlb.physical_address
|vpiParameter:
\_parameter: (ALU_UNIT_WB_ID), line:190
|vpiName:ALU_UNIT_WB_ID
|INT:32
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (BRANCH_PREDICTOR_WAYS), line:159
|vpiName:BRANCH_PREDICTOR_WAYS
|INT:9
|vpiParameter:
\_parameter: (BRANCH_TABLE_ENTRIES), line:160
|vpiName:BRANCH_TABLE_ENTRIES
|INT:4
|vpiParameter:
\_parameter: (BRANCH_UNIT_ID), line:195
|vpiName:BRANCH_UNIT_ID
|INT:8
|vpiParameter:
\_parameter: (BUS_ADDR_H), line:107
|vpiName:BUS_ADDR_H
|INT:1
|vpiParameter:
\_parameter: (BUS_ADDR_L), line:106
|vpiName:BUS_ADDR_L
|INT:0
|vpiParameter:
\_parameter: (BUS_BIT_CHECK), line:108
|vpiName:BUS_BIT_CHECK
|INT:1
|vpiParameter:
\_parameter: (BUS_TYPE), line:89
|vpiName:BUS_TYPE
|INT:5
|vpiParameter:
\_parameter: (COUNTER_W), line:42
|vpiName:COUNTER_W
|INT:33
|vpiParameter:
\_parameter: (CPU_ID), line:38
|vpiName:CPU_ID
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_ADDR_WIDTH), line:113
|vpiName:C_M_AXI_ADDR_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_DATA_WIDTH), line:114
|vpiName:C_M_AXI_DATA_WIDTH
|INT:1
|vpiParameter:
\_parameter: (DCACHE_LINES), line:133
|vpiName:DCACHE_LINES
|INT:-2146435073
|vpiParameter:
\_parameter: (DCACHE_LINE_ADDR_W), line:135
|vpiName:DCACHE_LINE_ADDR_W
|INT:1073741824
|vpiParameter:
\_parameter: (DCACHE_LINE_W), line:136
|vpiName:DCACHE_LINE_W
|INT:1342177279
|vpiParameter:
\_parameter: (DCACHE_SUB_LINE_ADDR_W), line:137
|vpiName:DCACHE_SUB_LINE_ADDR_W
|INT:4
|vpiParameter:
\_parameter: (DCACHE_TAG_W), line:138
|vpiName:DCACHE_TAG_W
|INT:1610612736
|vpiParameter:
\_parameter: (DCACHE_WAYS), line:134
|vpiName:DCACHE_WAYS
|INT:4
|vpiParameter:
\_parameter: (DIV_ALGORITHM), line:67
|vpiName:DIV_ALGORITHM
|INT:0
|vpiParameter:
\_parameter: (DIV_UNIT_WB_ID), line:192
|vpiName:DIV_UNIT_WB_ID
|INT:2
|vpiParameter:
\_parameter: (DTLB_DEPTH), line:152
|vpiName:DTLB_DEPTH
|INT:512
|vpiParameter:
\_parameter: (DTLB_WAYS), line:151
|vpiName:DTLB_WAYS
|INT:32
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (ENABLE_M_MODE), line:34
|vpiName:ENABLE_M_MODE
|INT:1
|vpiParameter:
\_parameter: (ENABLE_S_MODE), line:36
|vpiName:ENABLE_S_MODE
|INT:0
|vpiParameter:
\_parameter: (ENABLE_TRACE_INTERFACE), line:172
|vpiName:ENABLE_TRACE_INTERFACE
|INT:2
|vpiParameter:
\_parameter: (FETCH_BUFFER_DEPTH), line:168
|vpiName:FETCH_BUFFER_DEPTH
|INT:512
|vpiParameter:
\_parameter: (FPGA_VENDOR), line:27
|vpiName:FPGA_VENDOR
|STRING:"xilinx"
|vpiParameter:
\_parameter: (GC_UNIT_ID), line:196
|vpiName:GC_UNIT_ID
|INT:4
|vpiParameter:
\_parameter: (ICACHE_LINES), line:121
|vpiName:ICACHE_LINES
|INT:2
|vpiParameter:
\_parameter: (ICACHE_LINE_ADDR_W), line:123
|vpiName:ICACHE_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_LINE_W), line:124
|vpiName:ICACHE_LINE_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_SUB_LINE_ADDR_W), line:125
|vpiName:ICACHE_SUB_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_TAG_W), line:126
|vpiName:ICACHE_TAG_W
|INT:-2147483648
|vpiParameter:
\_parameter: (ICACHE_WAYS), line:122
|vpiName:ICACHE_WAYS
|INT:1
|vpiParameter:
\_parameter: (ITLB_DEPTH), line:146
|vpiName:ITLB_DEPTH
|INT:32
|vpiParameter:
\_parameter: (ITLB_WAYS), line:145
|vpiName:ITLB_WAYS
|INT:4
|vpiParameter:
\_parameter: (L1_CONNECTIONS), line:177
|vpiName:L1_CONNECTIONS
|INT:9
|vpiParameter:
\_parameter: (L1_DCACHE_ID), line:178
|vpiName:L1_DCACHE_ID
|INT:4
|vpiParameter:
\_parameter: (L1_DMMU_ID), line:179
|vpiName:L1_DMMU_ID
|INT:2
|vpiParameter:
\_parameter: (L1_ICACHE_ID), line:180
|vpiName:L1_ICACHE_ID
|INT:19
|vpiParameter:
\_parameter: (L1_IMMU_ID), line:181
|vpiName:L1_IMMU_ID
|INT:0
|vpiParameter:
\_parameter: (LS_UNIT_WB_ID), line:191
|vpiName:LS_UNIT_WB_ID
|INT:1
|vpiParameter:
\_parameter: (MAX_INFLIGHT_COUNT), line:167
|vpiName:MAX_INFLIGHT_COUNT
|INT:19
|vpiParameter:
\_parameter: (MEMORY_ADDR_H), line:103
|vpiName:MEMORY_ADDR_H
|INT:12
|vpiParameter:
\_parameter: (MEMORY_ADDR_L), line:102
|vpiName:MEMORY_ADDR_L
|INT:11
|vpiParameter:
\_parameter: (MEMORY_BIT_CHECK), line:104
|vpiName:MEMORY_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (MUL_UNIT_WB_ID), line:193
|vpiName:MUL_UNIT_WB_ID
|INT:512
|vpiParameter:
\_parameter: (NUM_UNITS), line:188
|vpiName:NUM_UNITS
|INT:2
|vpiParameter:
\_parameter: (NUM_WB_UNITS), line:186
|vpiName:NUM_WB_UNITS
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (RAS_DEPTH), line:161
|vpiName:RAS_DEPTH
|INT:2
|vpiParameter:
\_parameter: (RESET_VEC), line:39
|vpiName:RESET_VEC
|INT:-2147483648
|vpiParameter:
\_parameter: (SCRATCH_ADDR_H), line:99
|vpiName:SCRATCH_ADDR_H
|INT:9
|vpiParameter:
\_parameter: (SCRATCH_ADDR_L), line:98
|vpiName:SCRATCH_ADDR_L
|INT:8
|vpiParameter:
\_parameter: (SCRATCH_BIT_CHECK), line:100
|vpiName:SCRATCH_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (USE_AMO), line:70
|vpiName:USE_AMO
|INT:1
|vpiParameter:
\_parameter: (USE_BRANCH_PREDICTOR), line:158
|vpiName:USE_BRANCH_PREDICTOR
|INT:2
|vpiParameter:
\_parameter: (USE_BUS), line:88
|vpiName:USE_BUS
|INT:4
|vpiParameter:
\_parameter: (USE_DCACHE), line:92
|vpiName:USE_DCACHE
|INT:6
|vpiParameter:
\_parameter: (USE_DIV), line:49
|vpiName:USE_DIV
|INT:1
|vpiParameter:
\_parameter: (USE_DTAG_INVALIDATIONS), line:140
|vpiName:USE_DTAG_INVALIDATIONS
|INT:1879048191
|vpiParameter:
\_parameter: (USE_D_SCRATCH_MEM), line:79
|vpiName:USE_D_SCRATCH_MEM
|INT:3
|vpiParameter:
\_parameter: (USE_ICACHE), line:93
|vpiName:USE_ICACHE
|INT:7
|vpiParameter:
\_parameter: (USE_I_SCRATCH_MEM), line:78
|vpiName:USE_I_SCRATCH_MEM
|INT:2
|vpiParameter:
\_parameter: (USE_MUL), line:48
|vpiName:USE_MUL
|INT:1
|vpiParameter:
\_parameter: (WB_UNITS_WIDTH), line:187
|vpiName:WB_UNITS_WIDTH
|INT:32
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiGenScopeArray:
\_gen_scope_array: (genblk3), line:188, parent:cpu
|vpiName:genblk3
|vpiFullName:work@taiga_wrapper.cpu.genblk3
|vpiGenScope:
\_gen_scope: , parent:genblk3
|vpiFullName:work@taiga_wrapper.cpu.genblk3
|vpiContAssign:
\_cont_assign: , line:189
|vpiRhs:
\_constant: , line:189
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiLhs:
\_ref_obj: (dtlb.complete), line:189
|vpiName:dtlb.complete
|vpiFullName:work@taiga_wrapper.cpu.genblk3.dtlb.complete
|vpiContAssign:
\_cont_assign: , line:190
|vpiRhs:
\_ref_obj: (dtlb.virtual_address), line:190
|vpiName:dtlb.virtual_address
|vpiFullName:work@taiga_wrapper.cpu.genblk3.dtlb.virtual_address
|vpiLhs:
\_ref_obj: (dtlb.physical_address), line:190
|vpiName:dtlb.physical_address
|vpiFullName:work@taiga_wrapper.cpu.genblk3.dtlb.physical_address
|vpiParameter:
\_parameter: (ALU_UNIT_WB_ID), line:190
|vpiName:ALU_UNIT_WB_ID
|INT:32
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (BRANCH_PREDICTOR_WAYS), line:159
|vpiName:BRANCH_PREDICTOR_WAYS
|INT:9
|vpiParameter:
\_parameter: (BRANCH_TABLE_ENTRIES), line:160
|vpiName:BRANCH_TABLE_ENTRIES
|INT:4
|vpiParameter:
\_parameter: (BRANCH_UNIT_ID), line:195
|vpiName:BRANCH_UNIT_ID
|INT:8
|vpiParameter:
\_parameter: (BUS_ADDR_H), line:107
|vpiName:BUS_ADDR_H
|INT:1
|vpiParameter:
\_parameter: (BUS_ADDR_L), line:106
|vpiName:BUS_ADDR_L
|INT:0
|vpiParameter:
\_parameter: (BUS_BIT_CHECK), line:108
|vpiName:BUS_BIT_CHECK
|INT:1
|vpiParameter:
\_parameter: (BUS_TYPE), line:89
|vpiName:BUS_TYPE
|INT:5
|vpiParameter:
\_parameter: (COUNTER_W), line:42
|vpiName:COUNTER_W
|INT:33
|vpiParameter:
\_parameter: (CPU_ID), line:38
|vpiName:CPU_ID
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_ADDR_WIDTH), line:113
|vpiName:C_M_AXI_ADDR_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_DATA_WIDTH), line:114
|vpiName:C_M_AXI_DATA_WIDTH
|INT:1
|vpiParameter:
\_parameter: (DCACHE_LINES), line:133
|vpiName:DCACHE_LINES
|INT:-2146435073
|vpiParameter:
\_parameter: (DCACHE_LINE_ADDR_W), line:135
|vpiName:DCACHE_LINE_ADDR_W
|INT:1073741824
|vpiParameter:
\_parameter: (DCACHE_LINE_W), line:136
|vpiName:DCACHE_LINE_W
|INT:1342177279
|vpiParameter:
\_parameter: (DCACHE_SUB_LINE_ADDR_W), line:137
|vpiName:DCACHE_SUB_LINE_ADDR_W
|INT:4
|vpiParameter:
\_parameter: (DCACHE_TAG_W), line:138
|vpiName:DCACHE_TAG_W
|INT:1610612736
|vpiParameter:
\_parameter: (DCACHE_WAYS), line:134
|vpiName:DCACHE_WAYS
|INT:4
|vpiParameter:
\_parameter: (DIV_ALGORITHM), line:67
|vpiName:DIV_ALGORITHM
|INT:0
|vpiParameter:
\_parameter: (DIV_UNIT_WB_ID), line:192
|vpiName:DIV_UNIT_WB_ID
|INT:2
|vpiParameter:
\_parameter: (DTLB_DEPTH), line:152
|vpiName:DTLB_DEPTH
|INT:512
|vpiParameter:
\_parameter: (DTLB_WAYS), line:151
|vpiName:DTLB_WAYS
|INT:32
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (ENABLE_M_MODE), line:34
|vpiName:ENABLE_M_MODE
|INT:1
|vpiParameter:
\_parameter: (ENABLE_S_MODE), line:36
|vpiName:ENABLE_S_MODE
|INT:0
|vpiParameter:
\_parameter: (ENABLE_TRACE_INTERFACE), line:172
|vpiName:ENABLE_TRACE_INTERFACE
|INT:2
|vpiParameter:
\_parameter: (FETCH_BUFFER_DEPTH), line:168
|vpiName:FETCH_BUFFER_DEPTH
|INT:512
|vpiParameter:
\_parameter: (FPGA_VENDOR), line:27
|vpiName:FPGA_VENDOR
|STRING:"xilinx"
|vpiParameter:
\_parameter: (GC_UNIT_ID), line:196
|vpiName:GC_UNIT_ID
|INT:4
|vpiParameter:
\_parameter: (ICACHE_LINES), line:121
|vpiName:ICACHE_LINES
|INT:2
|vpiParameter:
\_parameter: (ICACHE_LINE_ADDR_W), line:123
|vpiName:ICACHE_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_LINE_W), line:124
|vpiName:ICACHE_LINE_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_SUB_LINE_ADDR_W), line:125
|vpiName:ICACHE_SUB_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_TAG_W), line:126
|vpiName:ICACHE_TAG_W
|INT:-2147483648
|vpiParameter:
\_parameter: (ICACHE_WAYS), line:122
|vpiName:ICACHE_WAYS
|INT:1
|vpiParameter:
\_parameter: (ITLB_DEPTH), line:146
|vpiName:ITLB_DEPTH
|INT:32
|vpiParameter:
\_parameter: (ITLB_WAYS), line:145
|vpiName:ITLB_WAYS
|INT:4
|vpiParameter:
\_parameter: (L1_CONNECTIONS), line:177
|vpiName:L1_CONNECTIONS
|INT:9
|vpiParameter:
\_parameter: (L1_DCACHE_ID), line:178
|vpiName:L1_DCACHE_ID
|INT:4
|vpiParameter:
\_parameter: (L1_DMMU_ID), line:179
|vpiName:L1_DMMU_ID
|INT:2
|vpiParameter:
\_parameter: (L1_ICACHE_ID), line:180
|vpiName:L1_ICACHE_ID
|INT:19
|vpiParameter:
\_parameter: (L1_IMMU_ID), line:181
|vpiName:L1_IMMU_ID
|INT:0
|vpiParameter:
\_parameter: (LS_UNIT_WB_ID), line:191
|vpiName:LS_UNIT_WB_ID
|INT:1
|vpiParameter:
\_parameter: (MAX_INFLIGHT_COUNT), line:167
|vpiName:MAX_INFLIGHT_COUNT
|INT:19
|vpiParameter:
\_parameter: (MEMORY_ADDR_H), line:103
|vpiName:MEMORY_ADDR_H
|INT:12
|vpiParameter:
\_parameter: (MEMORY_ADDR_L), line:102
|vpiName:MEMORY_ADDR_L
|INT:11
|vpiParameter:
\_parameter: (MEMORY_BIT_CHECK), line:104
|vpiName:MEMORY_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (MUL_UNIT_WB_ID), line:193
|vpiName:MUL_UNIT_WB_ID
|INT:512
|vpiParameter:
\_parameter: (NUM_UNITS), line:188
|vpiName:NUM_UNITS
|INT:2
|vpiParameter:
\_parameter: (NUM_WB_UNITS), line:186
|vpiName:NUM_WB_UNITS
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (RAS_DEPTH), line:161
|vpiName:RAS_DEPTH
|INT:2
|vpiParameter:
\_parameter: (RESET_VEC), line:39
|vpiName:RESET_VEC
|INT:-2147483648
|vpiParameter:
\_parameter: (SCRATCH_ADDR_H), line:99
|vpiName:SCRATCH_ADDR_H
|INT:9
|vpiParameter:
\_parameter: (SCRATCH_ADDR_L), line:98
|vpiName:SCRATCH_ADDR_L
|INT:8
|vpiParameter:
\_parameter: (SCRATCH_BIT_CHECK), line:100
|vpiName:SCRATCH_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (USE_AMO), line:70
|vpiName:USE_AMO
|INT:1
|vpiParameter:
\_parameter: (USE_BRANCH_PREDICTOR), line:158
|vpiName:USE_BRANCH_PREDICTOR
|INT:2
|vpiParameter:
\_parameter: (USE_BUS), line:88
|vpiName:USE_BUS
|INT:4
|vpiParameter:
\_parameter: (USE_DCACHE), line:92
|vpiName:USE_DCACHE
|INT:6
|vpiParameter:
\_parameter: (USE_DIV), line:49
|vpiName:USE_DIV
|INT:1
|vpiParameter:
\_parameter: (USE_DTAG_INVALIDATIONS), line:140
|vpiName:USE_DTAG_INVALIDATIONS
|INT:1879048191
|vpiParameter:
\_parameter: (USE_D_SCRATCH_MEM), line:79
|vpiName:USE_D_SCRATCH_MEM
|INT:3
|vpiParameter:
\_parameter: (USE_ICACHE), line:93
|vpiName:USE_ICACHE
|INT:7
|vpiParameter:
\_parameter: (USE_I_SCRATCH_MEM), line:78
|vpiName:USE_I_SCRATCH_MEM
|INT:2
|vpiParameter:
\_parameter: (USE_MUL), line:48
|vpiName:USE_MUL
|INT:1
|vpiParameter:
\_parameter: (WB_UNITS_WIDTH), line:187
|vpiName:WB_UNITS_WIDTH
|INT:32
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiGenScopeArray:
\_gen_scope_array: (genblk4), line:195, parent:cpu
|vpiName:genblk4
|vpiFullName:work@taiga_wrapper.cpu.genblk4
|vpiGenScope:
\_gen_scope: , parent:genblk4
|vpiFullName:work@taiga_wrapper.cpu.genblk4
|vpiModule:
\_module: work@mul_unit (mul_unit_block), file:third_party/cores/taiga/core/taiga.sv, line:196
|vpiDefName:work@mul_unit
|vpiName:mul_unit_block
|vpiFullName:work@taiga_wrapper.cpu.genblk4.mul_unit_block
|vpiPort:
\_port: (clk), line:27, parent:mul_unit_block
|vpiName:clk
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (clk), line:196
|vpiName:clk
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (clk), line:27, parent:mul_unit_block
|vpiName:clk
|vpiFullName:work@taiga_wrapper.cpu.genblk4.mul_unit_block.clk
|vpiNetType:36
|vpiPort:
\_port: (rst), line:28, parent:mul_unit_block
|vpiName:rst
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (rst), line:196
|vpiName:rst
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (rst), line:28, parent:mul_unit_block
|vpiName:rst
|vpiFullName:work@taiga_wrapper.cpu.genblk4.mul_unit_block.rst
|vpiNetType:36
|vpiPort:
\_port: (mul_inputs), line:30, parent:mul_unit_block
|vpiName:mul_inputs
|vpiDirection:1
|vpiTypedef:
\_struct_typespec: (mul_inputs_t), line:383
|vpiHighConn:
\_ref_obj: (mul_inputs), line:196
|vpiName:mul_inputs
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (mul_inputs), line:30, parent:mul_unit_block
|vpiName:mul_inputs
|vpiFullName:work@taiga_wrapper.cpu.genblk4.mul_unit_block.mul_inputs
|vpiPort:
\_port: (issue), line:31, parent:mul_unit_block
|vpiName:issue
|vpiDirection:5
|vpiHighConn:
\_ref_obj: (issue), line:196
|vpiName:issue
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_modport: (unit)
|vpiName:unit
|vpiIODecl:
\_io_decl: (ready)
|vpiName:ready
|vpiDirection:2
|vpiExpr:
\_logic_net: (ready), line:58
|vpiName:ready
|vpiNetType:36
|vpiIODecl:
\_io_decl: (possible_issue)
|vpiName:possible_issue
|vpiDirection:1
|vpiExpr:
\_logic_net: (possible_issue), line:53
|vpiName:possible_issue
|vpiNetType:36
|vpiIODecl:
\_io_decl: (new_request)
|vpiName:new_request
|vpiDirection:1
|vpiExpr:
\_logic_net: (new_request), line:54
|vpiName:new_request
|vpiNetType:36
|vpiIODecl:
\_io_decl: (new_request_r)
|vpiName:new_request_r
|vpiDirection:1
|vpiExpr:
\_logic_net: (new_request_r), line:55
|vpiName:new_request_r
|vpiNetType:36
|vpiIODecl:
\_io_decl: (instruction_id)
|vpiName:instruction_id
|vpiDirection:1
|vpiInterface:
\_interface: work@unit_issue_interface (issue), file:third_party/cores/taiga/core/taiga.sv, line:196
|vpiDefName:work@unit_issue_interface
|vpiName:issue
|vpiModport:
\_modport: (decode)
|vpiName:decode
|vpiIODecl:
\_io_decl: (ready)
|vpiName:ready
|vpiDirection:1
|vpiExpr:
\_logic_net: (ready), line:58
|vpiIODecl:
\_io_decl: (possible_issue)
|vpiName:possible_issue
|vpiDirection:2
|vpiExpr:
\_logic_net: (possible_issue), line:53
|vpiIODecl:
\_io_decl: (new_request)
|vpiName:new_request
|vpiDirection:2
|vpiExpr:
\_logic_net: (new_request), line:54
|vpiIODecl:
\_io_decl: (new_request_r)
|vpiName:new_request_r
|vpiDirection:2
|vpiExpr:
\_logic_net: (new_request_r), line:55
|vpiIODecl:
\_io_decl: (instruction_id)
|vpiName:instruction_id
|vpiDirection:2
|vpiInterface:
\_interface: work@unit_issue_interface (issue), file:third_party/cores/taiga/core/taiga.sv, line:196
|vpiModport:
\_modport: (unit)
|vpiPort:
\_port: (wb), line:32, parent:mul_unit_block
|vpiName:wb
|vpiDirection:2
|vpiTypedef:
\_struct_typespec: (unit_writeback_t), line:295
|vpiHighConn:
\_ref_obj: (wb), line:196
|vpiName:wb
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (wb), line:32, parent:mul_unit_block
|vpiName:wb
|vpiFullName:work@taiga_wrapper.cpu.genblk4.mul_unit_block.wb
|vpiNet:
\_logic_net: (clk), line:27, parent:mul_unit_block
|vpiNet:
\_logic_net: (rst), line:28, parent:mul_unit_block
|vpiNet:
\_logic_net: (mul_inputs), line:30, parent:mul_unit_block
|vpiNet:
\_logic_net: (wb), line:32, parent:mul_unit_block
|vpiNet:
\_logic_net: (result), line:35, parent:mul_unit_block
|vpiName:result
|vpiFullName:work@taiga_wrapper.cpu.genblk4.mul_unit_block.result
|vpiNetType:36
|vpiNet:
\_logic_net: (mulh), line:36, parent:mul_unit_block
|vpiName:mulh
|vpiFullName:work@taiga_wrapper.cpu.genblk4.mul_unit_block.mulh
|vpiNetType:36
|vpiRange:
\_range: , line:36
|vpiLeftRange:
\_constant: , line:36
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:36
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (done), line:37, parent:mul_unit_block
|vpiName:done
|vpiFullName:work@taiga_wrapper.cpu.genblk4.mul_unit_block.done
|vpiNetType:36
|vpiRange:
\_range: , line:37
|vpiLeftRange:
\_constant: , line:37
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:37
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (rs1_signed), line:40, parent:mul_unit_block
|vpiName:rs1_signed
|vpiFullName:work@taiga_wrapper.cpu.genblk4.mul_unit_block.rs1_signed
|vpiNetType:36
|vpiNet:
\_logic_net: (rs2_signed), line:40, parent:mul_unit_block
|vpiName:rs2_signed
|vpiFullName:work@taiga_wrapper.cpu.genblk4.mul_unit_block.rs2_signed
|vpiNetType:36
|vpiNet:
\_logic_net: (rs1_ext), line:41, parent:mul_unit_block
|vpiName:rs1_ext
|vpiFullName:work@taiga_wrapper.cpu.genblk4.mul_unit_block.rs1_ext
|vpiNetType:36
|vpiNet:
\_logic_net: (rs2_ext), line:41, parent:mul_unit_block
|vpiName:rs2_ext
|vpiFullName:work@taiga_wrapper.cpu.genblk4.mul_unit_block.rs2_ext
|vpiNetType:36
|vpiNet:
\_logic_net: (rs1_r), line:42, parent:mul_unit_block
|vpiName:rs1_r
|vpiFullName:work@taiga_wrapper.cpu.genblk4.mul_unit_block.rs1_r
|vpiNetType:36
|vpiNet:
\_logic_net: (rs2_r), line:42, parent:mul_unit_block
|vpiName:rs2_r
|vpiFullName:work@taiga_wrapper.cpu.genblk4.mul_unit_block.rs2_r
|vpiNetType:36
|vpiNet:
\_logic_net: (issue), line:31, parent:mul_unit_block
|vpiName:issue
|vpiFullName:work@taiga_wrapper.cpu.genblk4.mul_unit_block.issue
|vpiVariables:
\_array_var: (id), parent:mul_unit_block
|vpiArrayType:1
|vpiName:id
|vpiFullName:work@taiga_wrapper.cpu.genblk4.mul_unit_block.id
|vpiRandType:1
|vpiVisibility:1
|vpiSize:2
|vpiReg:
\_logic_var: (id), line:38, parent:id
|vpiName:id
|vpiFullName:work@taiga_wrapper.cpu.genblk4.mul_unit_block.id.id
|vpiRange:
\_range: , line:38
|vpiLeftRange:
\_constant: , line:38
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:38
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiParameter:
\_parameter: (ALU_UNIT_WB_ID), line:190
|vpiName:ALU_UNIT_WB_ID
|INT:32
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (BRANCH_PREDICTOR_WAYS), line:159
|vpiName:BRANCH_PREDICTOR_WAYS
|INT:9
|vpiParameter:
\_parameter: (BRANCH_TABLE_ENTRIES), line:160
|vpiName:BRANCH_TABLE_ENTRIES
|INT:4
|vpiParameter:
\_parameter: (BRANCH_UNIT_ID), line:195
|vpiName:BRANCH_UNIT_ID
|INT:8
|vpiParameter:
\_parameter: (BUS_ADDR_H), line:107
|vpiName:BUS_ADDR_H
|INT:1
|vpiParameter:
\_parameter: (BUS_ADDR_L), line:106
|vpiName:BUS_ADDR_L
|INT:0
|vpiParameter:
\_parameter: (BUS_BIT_CHECK), line:108
|vpiName:BUS_BIT_CHECK
|INT:1
|vpiParameter:
\_parameter: (BUS_TYPE), line:89
|vpiName:BUS_TYPE
|INT:5
|vpiParameter:
\_parameter: (COUNTER_W), line:42
|vpiName:COUNTER_W
|INT:33
|vpiParameter:
\_parameter: (CPU_ID), line:38
|vpiName:CPU_ID
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_ADDR_WIDTH), line:113
|vpiName:C_M_AXI_ADDR_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_DATA_WIDTH), line:114
|vpiName:C_M_AXI_DATA_WIDTH
|INT:1
|vpiParameter:
\_parameter: (DCACHE_LINES), line:133
|vpiName:DCACHE_LINES
|INT:-2146435073
|vpiParameter:
\_parameter: (DCACHE_LINE_ADDR_W), line:135
|vpiName:DCACHE_LINE_ADDR_W
|INT:1073741824
|vpiParameter:
\_parameter: (DCACHE_LINE_W), line:136
|vpiName:DCACHE_LINE_W
|INT:1342177279
|vpiParameter:
\_parameter: (DCACHE_SUB_LINE_ADDR_W), line:137
|vpiName:DCACHE_SUB_LINE_ADDR_W
|INT:4
|vpiParameter:
\_parameter: (DCACHE_TAG_W), line:138
|vpiName:DCACHE_TAG_W
|INT:1610612736
|vpiParameter:
\_parameter: (DCACHE_WAYS), line:134
|vpiName:DCACHE_WAYS
|INT:4
|vpiParameter:
\_parameter: (DIV_ALGORITHM), line:67
|vpiName:DIV_ALGORITHM
|INT:0
|vpiParameter:
\_parameter: (DIV_UNIT_WB_ID), line:192
|vpiName:DIV_UNIT_WB_ID
|INT:2
|vpiParameter:
\_parameter: (DTLB_DEPTH), line:152
|vpiName:DTLB_DEPTH
|INT:512
|vpiParameter:
\_parameter: (DTLB_WAYS), line:151
|vpiName:DTLB_WAYS
|INT:32
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (ENABLE_M_MODE), line:34
|vpiName:ENABLE_M_MODE
|INT:1
|vpiParameter:
\_parameter: (ENABLE_S_MODE), line:36
|vpiName:ENABLE_S_MODE
|INT:0
|vpiParameter:
\_parameter: (ENABLE_TRACE_INTERFACE), line:172
|vpiName:ENABLE_TRACE_INTERFACE
|INT:2
|vpiParameter:
\_parameter: (FETCH_BUFFER_DEPTH), line:168
|vpiName:FETCH_BUFFER_DEPTH
|INT:512
|vpiParameter:
\_parameter: (FPGA_VENDOR), line:27
|vpiName:FPGA_VENDOR
|STRING:"xilinx"
|vpiParameter:
\_parameter: (GC_UNIT_ID), line:196
|vpiName:GC_UNIT_ID
|INT:4
|vpiParameter:
\_parameter: (ICACHE_LINES), line:121
|vpiName:ICACHE_LINES
|INT:2
|vpiParameter:
\_parameter: (ICACHE_LINE_ADDR_W), line:123
|vpiName:ICACHE_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_LINE_W), line:124
|vpiName:ICACHE_LINE_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_SUB_LINE_ADDR_W), line:125
|vpiName:ICACHE_SUB_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_TAG_W), line:126
|vpiName:ICACHE_TAG_W
|INT:-2147483648
|vpiParameter:
\_parameter: (ICACHE_WAYS), line:122
|vpiName:ICACHE_WAYS
|INT:1
|vpiParameter:
\_parameter: (ITLB_DEPTH), line:146
|vpiName:ITLB_DEPTH
|INT:32
|vpiParameter:
\_parameter: (ITLB_WAYS), line:145
|vpiName:ITLB_WAYS
|INT:4
|vpiParameter:
\_parameter: (L1_CONNECTIONS), line:177
|vpiName:L1_CONNECTIONS
|INT:9
|vpiParameter:
\_parameter: (L1_DCACHE_ID), line:178
|vpiName:L1_DCACHE_ID
|INT:4
|vpiParameter:
\_parameter: (L1_DMMU_ID), line:179
|vpiName:L1_DMMU_ID
|INT:2
|vpiParameter:
\_parameter: (L1_ICACHE_ID), line:180
|vpiName:L1_ICACHE_ID
|INT:19
|vpiParameter:
\_parameter: (L1_IMMU_ID), line:181
|vpiName:L1_IMMU_ID
|INT:0
|vpiParameter:
\_parameter: (LS_UNIT_WB_ID), line:191
|vpiName:LS_UNIT_WB_ID
|INT:1
|vpiParameter:
\_parameter: (MAX_INFLIGHT_COUNT), line:167
|vpiName:MAX_INFLIGHT_COUNT
|INT:19
|vpiParameter:
\_parameter: (MEMORY_ADDR_H), line:103
|vpiName:MEMORY_ADDR_H
|INT:12
|vpiParameter:
\_parameter: (MEMORY_ADDR_L), line:102
|vpiName:MEMORY_ADDR_L
|INT:11
|vpiParameter:
\_parameter: (MEMORY_BIT_CHECK), line:104
|vpiName:MEMORY_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (MUL_UNIT_WB_ID), line:193
|vpiName:MUL_UNIT_WB_ID
|INT:512
|vpiParameter:
\_parameter: (NUM_UNITS), line:188
|vpiName:NUM_UNITS
|INT:2
|vpiParameter:
\_parameter: (NUM_WB_UNITS), line:186
|vpiName:NUM_WB_UNITS
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (RAS_DEPTH), line:161
|vpiName:RAS_DEPTH
|INT:2
|vpiParameter:
\_parameter: (RESET_VEC), line:39
|vpiName:RESET_VEC
|INT:-2147483648
|vpiParameter:
\_parameter: (SCRATCH_ADDR_H), line:99
|vpiName:SCRATCH_ADDR_H
|INT:9
|vpiParameter:
\_parameter: (SCRATCH_ADDR_L), line:98
|vpiName:SCRATCH_ADDR_L
|INT:8
|vpiParameter:
\_parameter: (SCRATCH_BIT_CHECK), line:100
|vpiName:SCRATCH_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (USE_AMO), line:70
|vpiName:USE_AMO
|INT:1
|vpiParameter:
\_parameter: (USE_BRANCH_PREDICTOR), line:158
|vpiName:USE_BRANCH_PREDICTOR
|INT:2
|vpiParameter:
\_parameter: (USE_BUS), line:88
|vpiName:USE_BUS
|INT:4
|vpiParameter:
\_parameter: (USE_DCACHE), line:92
|vpiName:USE_DCACHE
|INT:6
|vpiParameter:
\_parameter: (USE_DIV), line:49
|vpiName:USE_DIV
|INT:1
|vpiParameter:
\_parameter: (USE_DTAG_INVALIDATIONS), line:140
|vpiName:USE_DTAG_INVALIDATIONS
|INT:1879048191
|vpiParameter:
\_parameter: (USE_D_SCRATCH_MEM), line:79
|vpiName:USE_D_SCRATCH_MEM
|INT:3
|vpiParameter:
\_parameter: (USE_ICACHE), line:93
|vpiName:USE_ICACHE
|INT:7
|vpiParameter:
\_parameter: (USE_I_SCRATCH_MEM), line:78
|vpiName:USE_I_SCRATCH_MEM
|INT:2
|vpiParameter:
\_parameter: (USE_MUL), line:48
|vpiName:USE_MUL
|INT:1
|vpiParameter:
\_parameter: (WB_UNITS_WIDTH), line:187
|vpiName:WB_UNITS_WIDTH
|INT:32
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiParameter:
\_parameter: (ALU_UNIT_WB_ID), line:190
|vpiName:ALU_UNIT_WB_ID
|INT:32
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (BRANCH_PREDICTOR_WAYS), line:159
|vpiName:BRANCH_PREDICTOR_WAYS
|INT:9
|vpiParameter:
\_parameter: (BRANCH_TABLE_ENTRIES), line:160
|vpiName:BRANCH_TABLE_ENTRIES
|INT:4
|vpiParameter:
\_parameter: (BRANCH_UNIT_ID), line:195
|vpiName:BRANCH_UNIT_ID
|INT:8
|vpiParameter:
\_parameter: (BUS_ADDR_H), line:107
|vpiName:BUS_ADDR_H
|INT:1
|vpiParameter:
\_parameter: (BUS_ADDR_L), line:106
|vpiName:BUS_ADDR_L
|INT:0
|vpiParameter:
\_parameter: (BUS_BIT_CHECK), line:108
|vpiName:BUS_BIT_CHECK
|INT:1
|vpiParameter:
\_parameter: (BUS_TYPE), line:89
|vpiName:BUS_TYPE
|INT:5
|vpiParameter:
\_parameter: (COUNTER_W), line:42
|vpiName:COUNTER_W
|INT:33
|vpiParameter:
\_parameter: (CPU_ID), line:38
|vpiName:CPU_ID
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_ADDR_WIDTH), line:113
|vpiName:C_M_AXI_ADDR_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_DATA_WIDTH), line:114
|vpiName:C_M_AXI_DATA_WIDTH
|INT:1
|vpiParameter:
\_parameter: (DCACHE_LINES), line:133
|vpiName:DCACHE_LINES
|INT:-2146435073
|vpiParameter:
\_parameter: (DCACHE_LINE_ADDR_W), line:135
|vpiName:DCACHE_LINE_ADDR_W
|INT:1073741824
|vpiParameter:
\_parameter: (DCACHE_LINE_W), line:136
|vpiName:DCACHE_LINE_W
|INT:1342177279
|vpiParameter:
\_parameter: (DCACHE_SUB_LINE_ADDR_W), line:137
|vpiName:DCACHE_SUB_LINE_ADDR_W
|INT:4
|vpiParameter:
\_parameter: (DCACHE_TAG_W), line:138
|vpiName:DCACHE_TAG_W
|INT:1610612736
|vpiParameter:
\_parameter: (DCACHE_WAYS), line:134
|vpiName:DCACHE_WAYS
|INT:4
|vpiParameter:
\_parameter: (DIV_ALGORITHM), line:67
|vpiName:DIV_ALGORITHM
|INT:0
|vpiParameter:
\_parameter: (DIV_UNIT_WB_ID), line:192
|vpiName:DIV_UNIT_WB_ID
|INT:2
|vpiParameter:
\_parameter: (DTLB_DEPTH), line:152
|vpiName:DTLB_DEPTH
|INT:512
|vpiParameter:
\_parameter: (DTLB_WAYS), line:151
|vpiName:DTLB_WAYS
|INT:32
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (ENABLE_M_MODE), line:34
|vpiName:ENABLE_M_MODE
|INT:1
|vpiParameter:
\_parameter: (ENABLE_S_MODE), line:36
|vpiName:ENABLE_S_MODE
|INT:0
|vpiParameter:
\_parameter: (ENABLE_TRACE_INTERFACE), line:172
|vpiName:ENABLE_TRACE_INTERFACE
|INT:2
|vpiParameter:
\_parameter: (FETCH_BUFFER_DEPTH), line:168
|vpiName:FETCH_BUFFER_DEPTH
|INT:512
|vpiParameter:
\_parameter: (FPGA_VENDOR), line:27
|vpiName:FPGA_VENDOR
|STRING:"xilinx"
|vpiParameter:
\_parameter: (GC_UNIT_ID), line:196
|vpiName:GC_UNIT_ID
|INT:4
|vpiParameter:
\_parameter: (ICACHE_LINES), line:121
|vpiName:ICACHE_LINES
|INT:2
|vpiParameter:
\_parameter: (ICACHE_LINE_ADDR_W), line:123
|vpiName:ICACHE_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_LINE_W), line:124
|vpiName:ICACHE_LINE_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_SUB_LINE_ADDR_W), line:125
|vpiName:ICACHE_SUB_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_TAG_W), line:126
|vpiName:ICACHE_TAG_W
|INT:-2147483648
|vpiParameter:
\_parameter: (ICACHE_WAYS), line:122
|vpiName:ICACHE_WAYS
|INT:1
|vpiParameter:
\_parameter: (ITLB_DEPTH), line:146
|vpiName:ITLB_DEPTH
|INT:32
|vpiParameter:
\_parameter: (ITLB_WAYS), line:145
|vpiName:ITLB_WAYS
|INT:4
|vpiParameter:
\_parameter: (L1_CONNECTIONS), line:177
|vpiName:L1_CONNECTIONS
|INT:9
|vpiParameter:
\_parameter: (L1_DCACHE_ID), line:178
|vpiName:L1_DCACHE_ID
|INT:4
|vpiParameter:
\_parameter: (L1_DMMU_ID), line:179
|vpiName:L1_DMMU_ID
|INT:2
|vpiParameter:
\_parameter: (L1_ICACHE_ID), line:180
|vpiName:L1_ICACHE_ID
|INT:19
|vpiParameter:
\_parameter: (L1_IMMU_ID), line:181
|vpiName:L1_IMMU_ID
|INT:0
|vpiParameter:
\_parameter: (LS_UNIT_WB_ID), line:191
|vpiName:LS_UNIT_WB_ID
|INT:1
|vpiParameter:
\_parameter: (MAX_INFLIGHT_COUNT), line:167
|vpiName:MAX_INFLIGHT_COUNT
|INT:19
|vpiParameter:
\_parameter: (MEMORY_ADDR_H), line:103
|vpiName:MEMORY_ADDR_H
|INT:12
|vpiParameter:
\_parameter: (MEMORY_ADDR_L), line:102
|vpiName:MEMORY_ADDR_L
|INT:11
|vpiParameter:
\_parameter: (MEMORY_BIT_CHECK), line:104
|vpiName:MEMORY_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (MUL_UNIT_WB_ID), line:193
|vpiName:MUL_UNIT_WB_ID
|INT:512
|vpiParameter:
\_parameter: (NUM_UNITS), line:188
|vpiName:NUM_UNITS
|INT:2
|vpiParameter:
\_parameter: (NUM_WB_UNITS), line:186
|vpiName:NUM_WB_UNITS
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (RAS_DEPTH), line:161
|vpiName:RAS_DEPTH
|INT:2
|vpiParameter:
\_parameter: (RESET_VEC), line:39
|vpiName:RESET_VEC
|INT:-2147483648
|vpiParameter:
\_parameter: (SCRATCH_ADDR_H), line:99
|vpiName:SCRATCH_ADDR_H
|INT:9
|vpiParameter:
\_parameter: (SCRATCH_ADDR_L), line:98
|vpiName:SCRATCH_ADDR_L
|INT:8
|vpiParameter:
\_parameter: (SCRATCH_BIT_CHECK), line:100
|vpiName:SCRATCH_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (USE_AMO), line:70
|vpiName:USE_AMO
|INT:1
|vpiParameter:
\_parameter: (USE_BRANCH_PREDICTOR), line:158
|vpiName:USE_BRANCH_PREDICTOR
|INT:2
|vpiParameter:
\_parameter: (USE_BUS), line:88
|vpiName:USE_BUS
|INT:4
|vpiParameter:
\_parameter: (USE_DCACHE), line:92
|vpiName:USE_DCACHE
|INT:6
|vpiParameter:
\_parameter: (USE_DIV), line:49
|vpiName:USE_DIV
|INT:1
|vpiParameter:
\_parameter: (USE_DTAG_INVALIDATIONS), line:140
|vpiName:USE_DTAG_INVALIDATIONS
|INT:1879048191
|vpiParameter:
\_parameter: (USE_D_SCRATCH_MEM), line:79
|vpiName:USE_D_SCRATCH_MEM
|INT:3
|vpiParameter:
\_parameter: (USE_ICACHE), line:93
|vpiName:USE_ICACHE
|INT:7
|vpiParameter:
\_parameter: (USE_I_SCRATCH_MEM), line:78
|vpiName:USE_I_SCRATCH_MEM
|INT:2
|vpiParameter:
\_parameter: (USE_MUL), line:48
|vpiName:USE_MUL
|INT:1
|vpiParameter:
\_parameter: (WB_UNITS_WIDTH), line:187
|vpiName:WB_UNITS_WIDTH
|INT:32
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiGenScopeArray:
\_gen_scope_array: (genblk5), line:198, parent:cpu
|vpiName:genblk5
|vpiFullName:work@taiga_wrapper.cpu.genblk5
|vpiGenScope:
\_gen_scope: , parent:genblk5
|vpiFullName:work@taiga_wrapper.cpu.genblk5
|vpiModule:
\_module: work@div_unit (div_unit_block), file:third_party/cores/taiga/core/taiga.sv, line:199
|vpiDefName:work@div_unit
|vpiName:div_unit_block
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block
|vpiPort:
\_port: (clk), line:28, parent:div_unit_block
|vpiName:clk
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (clk), line:199
|vpiName:clk
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (clk), line:28, parent:div_unit_block
|vpiName:clk
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.clk
|vpiNetType:36
|vpiPort:
\_port: (rst), line:29, parent:div_unit_block
|vpiName:rst
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (rst), line:199
|vpiName:rst
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (rst), line:29, parent:div_unit_block
|vpiName:rst
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.rst
|vpiNetType:36
|vpiPort:
\_port: (gc_fetch_flush), line:31, parent:div_unit_block
|vpiName:gc_fetch_flush
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (gc_fetch_flush), line:199
|vpiName:gc_fetch_flush
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (gc_fetch_flush), line:31, parent:div_unit_block
|vpiName:gc_fetch_flush
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.gc_fetch_flush
|vpiNetType:36
|vpiPort:
\_port: (div_inputs), line:33, parent:div_unit_block
|vpiName:div_inputs
|vpiDirection:1
|vpiTypedef:
\_struct_typespec: (div_inputs_t), line:389
|vpiHighConn:
\_ref_obj: (div_inputs), line:199
|vpiName:div_inputs
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (div_inputs), line:33, parent:div_unit_block
|vpiName:div_inputs
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.div_inputs
|vpiPort:
\_port: (issue), line:34, parent:div_unit_block
|vpiName:issue
|vpiDirection:5
|vpiHighConn:
\_ref_obj: (issue), line:199
|vpiName:issue
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_modport: (unit)
|vpiName:unit
|vpiIODecl:
\_io_decl: (ready)
|vpiName:ready
|vpiDirection:2
|vpiExpr:
\_logic_net: (ready), line:58
|vpiName:ready
|vpiNetType:36
|vpiIODecl:
\_io_decl: (possible_issue)
|vpiName:possible_issue
|vpiDirection:1
|vpiExpr:
\_logic_net: (possible_issue), line:53
|vpiName:possible_issue
|vpiNetType:36
|vpiIODecl:
\_io_decl: (new_request)
|vpiName:new_request
|vpiDirection:1
|vpiExpr:
\_logic_net: (new_request), line:54
|vpiName:new_request
|vpiNetType:36
|vpiIODecl:
\_io_decl: (new_request_r)
|vpiName:new_request_r
|vpiDirection:1
|vpiExpr:
\_logic_net: (new_request_r), line:55
|vpiName:new_request_r
|vpiNetType:36
|vpiIODecl:
\_io_decl: (instruction_id)
|vpiName:instruction_id
|vpiDirection:1
|vpiInterface:
\_interface: work@unit_issue_interface (issue), file:third_party/cores/taiga/core/taiga.sv, line:199
|vpiDefName:work@unit_issue_interface
|vpiName:issue
|vpiModport:
\_modport: (decode)
|vpiName:decode
|vpiIODecl:
\_io_decl: (ready)
|vpiName:ready
|vpiDirection:1
|vpiExpr:
\_logic_net: (ready), line:58
|vpiIODecl:
\_io_decl: (possible_issue)
|vpiName:possible_issue
|vpiDirection:2
|vpiExpr:
\_logic_net: (possible_issue), line:53
|vpiIODecl:
\_io_decl: (new_request)
|vpiName:new_request
|vpiDirection:2
|vpiExpr:
\_logic_net: (new_request), line:54
|vpiIODecl:
\_io_decl: (new_request_r)
|vpiName:new_request_r
|vpiDirection:2
|vpiExpr:
\_logic_net: (new_request_r), line:55
|vpiIODecl:
\_io_decl: (instruction_id)
|vpiName:instruction_id
|vpiDirection:2
|vpiInterface:
\_interface: work@unit_issue_interface (issue), file:third_party/cores/taiga/core/taiga.sv, line:199
|vpiModport:
\_modport: (unit)
|vpiPort:
\_port: (wb), line:35, parent:div_unit_block
|vpiName:wb
|vpiDirection:2
|vpiTypedef:
\_struct_typespec: (unit_writeback_t), line:295
|vpiHighConn:
\_ref_obj: (wb), line:199
|vpiName:wb
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (wb), line:35, parent:div_unit_block
|vpiName:wb
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.wb
|vpiInterface:
\_interface: work@unsigned_division_interface (div_core), file:third_party/cores/taiga/core/div_unit.sv, line:61, parent:div_unit_block
|vpiDefName:work@unsigned_division_interface
|vpiName:div_core
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.div_core
|vpiModport:
\_modport: (divider), parent:div_core
|vpiName:divider
|vpiIODecl:
\_io_decl: (remainder), parent:divider
|vpiName:remainder
|vpiDirection:2
|vpiIODecl:
\_io_decl: (quotient), parent:divider
|vpiName:quotient
|vpiDirection:2
|vpiIODecl:
\_io_decl: (done), parent:divider
|vpiName:done
|vpiDirection:2
|vpiIODecl:
\_io_decl: (divisor_is_zero), parent:divider
|vpiName:divisor_is_zero
|vpiDirection:2
|vpiIODecl:
\_io_decl: (dividend), parent:divider
|vpiName:dividend
|vpiDirection:1
|vpiIODecl:
\_io_decl: (divisor), parent:divider
|vpiName:divisor
|vpiDirection:1
|vpiIODecl:
\_io_decl: (start), parent:divider
|vpiName:start
|vpiDirection:1
|vpiInterface:
\_interface: work@unsigned_division_interface (div_core), file:third_party/cores/taiga/core/div_unit.sv, line:61, parent:div_unit_block
|vpiModport:
\_modport: (requester), parent:div_core
|vpiName:requester
|vpiIODecl:
\_io_decl: (remainder), parent:requester
|vpiName:remainder
|vpiDirection:1
|vpiIODecl:
\_io_decl: (quotient), parent:requester
|vpiName:quotient
|vpiDirection:1
|vpiIODecl:
\_io_decl: (done), parent:requester
|vpiName:done
|vpiDirection:1
|vpiIODecl:
\_io_decl: (divisor_is_zero), parent:requester
|vpiName:divisor_is_zero
|vpiDirection:1
|vpiIODecl:
\_io_decl: (dividend), parent:requester
|vpiName:dividend
|vpiDirection:2
|vpiIODecl:
\_io_decl: (divisor), parent:requester
|vpiName:divisor
|vpiDirection:2
|vpiIODecl:
\_io_decl: (start), parent:requester
|vpiName:start
|vpiDirection:2
|vpiInterface:
\_interface: work@unsigned_division_interface (div_core), file:third_party/cores/taiga/core/div_unit.sv, line:61, parent:div_unit_block
|vpiNet:
\_logic_net: (start), line:244, parent:div_core
|vpiName:start
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.div_core.start
|vpiNetType:36
|vpiNet:
\_logic_net: (dividend), line:245, parent:div_core
|vpiName:dividend
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.div_core.dividend
|vpiNetType:36
|vpiRange:
\_range: , line:245
|vpiLeftRange:
\_constant: , line:245
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:245
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (divisor), line:246, parent:div_core
|vpiName:divisor
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.div_core.divisor
|vpiNetType:36
|vpiRange:
\_range: , line:246
|vpiLeftRange:
\_constant: , line:246
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:246
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (remainder), line:247, parent:div_core
|vpiName:remainder
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.div_core.remainder
|vpiNetType:36
|vpiRange:
\_range: , line:247
|vpiLeftRange:
\_constant: , line:247
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:247
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (quotient), line:248, parent:div_core
|vpiName:quotient
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.div_core.quotient
|vpiNetType:36
|vpiRange:
\_range: , line:248
|vpiLeftRange:
\_constant: , line:248
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:248
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (done), line:249, parent:div_core
|vpiName:done
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.div_core.done
|vpiNetType:36
|vpiNet:
\_logic_net: (divisor_is_zero), line:250, parent:div_core
|vpiName:divisor_is_zero
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.div_core.divisor_is_zero
|vpiNetType:36
|vpiInstance:
\_module: work@div_unit (div_unit_block), file:third_party/cores/taiga/core/taiga.sv, line:199
|vpiInterface:
\_interface: work@fifo_interface (input_fifo), file:third_party/cores/taiga/core/div_unit.sv, line:67, parent:div_unit_block
|vpiDefName:work@fifo_interface
|vpiName:input_fifo
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.input_fifo
|vpiModport:
\_modport: (dequeue), parent:input_fifo
|vpiName:dequeue
|vpiIODecl:
\_io_decl: (valid), parent:dequeue
|vpiName:valid
|vpiDirection:1
|vpiIODecl:
\_io_decl: (data_out), parent:dequeue
|vpiName:data_out
|vpiDirection:1
|vpiIODecl:
\_io_decl: (pop), parent:dequeue
|vpiName:pop
|vpiDirection:2
|vpiInterface:
\_interface: work@fifo_interface (input_fifo), file:third_party/cores/taiga/core/div_unit.sv, line:67, parent:div_unit_block
|vpiModport:
\_modport: (enqueue), parent:input_fifo
|vpiName:enqueue
|vpiIODecl:
\_io_decl: (full), parent:enqueue
|vpiName:full
|vpiDirection:1
|vpiIODecl:
\_io_decl: (data_in), parent:enqueue
|vpiName:data_in
|vpiDirection:2
|vpiIODecl:
\_io_decl: (push), parent:enqueue
|vpiName:push
|vpiDirection:2
|vpiIODecl:
\_io_decl: (supress_push), parent:enqueue
|vpiName:supress_push
|vpiDirection:2
|vpiInterface:
\_interface: work@fifo_interface (input_fifo), file:third_party/cores/taiga/core/div_unit.sv, line:67, parent:div_unit_block
|vpiModport:
\_modport: (structure), parent:input_fifo
|vpiName:structure
|vpiIODecl:
\_io_decl: (push), parent:structure
|vpiName:push
|vpiDirection:1
|vpiIODecl:
\_io_decl: (pop), parent:structure
|vpiName:pop
|vpiDirection:1
|vpiIODecl:
\_io_decl: (data_in), parent:structure
|vpiName:data_in
|vpiDirection:1
|vpiIODecl:
\_io_decl: (supress_push), parent:structure
|vpiName:supress_push
|vpiDirection:1
|vpiIODecl:
\_io_decl: (data_out), parent:structure
|vpiName:data_out
|vpiDirection:2
|vpiIODecl:
\_io_decl: (valid), parent:structure
|vpiName:valid
|vpiDirection:2
|vpiIODecl:
\_io_decl: (full), parent:structure
|vpiName:full
|vpiDirection:2
|vpiInterface:
\_interface: work@fifo_interface (input_fifo), file:third_party/cores/taiga/core/div_unit.sv, line:67, parent:div_unit_block
|vpiNet:
\_logic_net: (push), line:158, parent:input_fifo
|vpiName:push
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.input_fifo.push
|vpiNetType:36
|vpiNet:
\_logic_net: (pop), line:159, parent:input_fifo
|vpiName:pop
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.input_fifo.pop
|vpiNetType:36
|vpiNet:
\_logic_net: (data_in), line:160, parent:input_fifo
|vpiName:data_in
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.input_fifo.data_in
|vpiNetType:36
|vpiRange:
\_range: , line:160
|vpiLeftRange:
\_constant: , line:160
|vpiDecompile:-1
|INT:-1
|vpiRightRange:
\_constant: , line:160
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (data_out), line:161, parent:input_fifo
|vpiName:data_out
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.input_fifo.data_out
|vpiNetType:36
|vpiRange:
\_range: , line:161
|vpiLeftRange:
\_constant: , line:161
|vpiDecompile:-1
|INT:-1
|vpiRightRange:
\_constant: , line:161
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (valid), line:162, parent:input_fifo
|vpiName:valid
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.input_fifo.valid
|vpiNetType:36
|vpiNet:
\_logic_net: (full), line:163, parent:input_fifo
|vpiName:full
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.input_fifo.full
|vpiNetType:36
|vpiNet:
\_logic_net: (supress_push), line:164, parent:input_fifo
|vpiName:supress_push
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.input_fifo.supress_push
|vpiNetType:36
|vpiNet:
\_logic_net: (push), line:158, parent:input_fifo
|vpiName:push
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.input_fifo.push
|vpiNetType:36
|vpiNet:
\_logic_net: (pop), line:159, parent:input_fifo
|vpiName:pop
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.input_fifo.pop
|vpiNetType:36
|vpiNet:
\_logic_net: (data_in), line:160, parent:input_fifo
|vpiName:data_in
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.input_fifo.data_in
|vpiNetType:36
|vpiRange:
\_range: , line:160
|vpiLeftRange:
\_constant: , line:160
|vpiDecompile:-1
|INT:-1
|vpiRightRange:
\_constant: , line:160
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (data_out), line:161, parent:input_fifo
|vpiName:data_out
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.input_fifo.data_out
|vpiNetType:36
|vpiRange:
\_range: , line:161
|vpiLeftRange:
\_constant: , line:161
|vpiDecompile:-1
|INT:-1
|vpiRightRange:
\_constant: , line:161
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (valid), line:162, parent:input_fifo
|vpiName:valid
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.input_fifo.valid
|vpiNetType:36
|vpiNet:
\_logic_net: (full), line:163, parent:input_fifo
|vpiName:full
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.input_fifo.full
|vpiNetType:36
|vpiNet:
\_logic_net: (supress_push), line:164, parent:input_fifo
|vpiName:supress_push
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.input_fifo.supress_push
|vpiNetType:36
|vpiInstance:
\_module: work@div_unit (div_unit_block), file:third_party/cores/taiga/core/taiga.sv, line:199
|vpiInterface:
\_interface: work@fifo_interface (wb_fifo), file:third_party/cores/taiga/core/div_unit.sv, line:68, parent:div_unit_block
|vpiDefName:work@fifo_interface
|vpiName:wb_fifo
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.wb_fifo
|vpiModport:
\_modport: (dequeue), parent:wb_fifo
|vpiName:dequeue
|vpiIODecl:
\_io_decl: (valid), parent:dequeue
|vpiName:valid
|vpiDirection:1
|vpiIODecl:
\_io_decl: (data_out), parent:dequeue
|vpiName:data_out
|vpiDirection:1
|vpiIODecl:
\_io_decl: (pop), parent:dequeue
|vpiName:pop
|vpiDirection:2
|vpiInterface:
\_interface: work@fifo_interface (wb_fifo), file:third_party/cores/taiga/core/div_unit.sv, line:68, parent:div_unit_block
|vpiModport:
\_modport: (enqueue), parent:wb_fifo
|vpiName:enqueue
|vpiIODecl:
\_io_decl: (full), parent:enqueue
|vpiName:full
|vpiDirection:1
|vpiIODecl:
\_io_decl: (data_in), parent:enqueue
|vpiName:data_in
|vpiDirection:2
|vpiIODecl:
\_io_decl: (push), parent:enqueue
|vpiName:push
|vpiDirection:2
|vpiIODecl:
\_io_decl: (supress_push), parent:enqueue
|vpiName:supress_push
|vpiDirection:2
|vpiInterface:
\_interface: work@fifo_interface (wb_fifo), file:third_party/cores/taiga/core/div_unit.sv, line:68, parent:div_unit_block
|vpiModport:
\_modport: (structure), parent:wb_fifo
|vpiName:structure
|vpiIODecl:
\_io_decl: (push), parent:structure
|vpiName:push
|vpiDirection:1
|vpiIODecl:
\_io_decl: (pop), parent:structure
|vpiName:pop
|vpiDirection:1
|vpiIODecl:
\_io_decl: (data_in), parent:structure
|vpiName:data_in
|vpiDirection:1
|vpiIODecl:
\_io_decl: (supress_push), parent:structure
|vpiName:supress_push
|vpiDirection:1
|vpiIODecl:
\_io_decl: (data_out), parent:structure
|vpiName:data_out
|vpiDirection:2
|vpiIODecl:
\_io_decl: (valid), parent:structure
|vpiName:valid
|vpiDirection:2
|vpiIODecl:
\_io_decl: (full), parent:structure
|vpiName:full
|vpiDirection:2
|vpiInterface:
\_interface: work@fifo_interface (wb_fifo), file:third_party/cores/taiga/core/div_unit.sv, line:68, parent:div_unit_block
|vpiNet:
\_logic_net: (push), line:158, parent:wb_fifo
|vpiName:push
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.wb_fifo.push
|vpiNetType:36
|vpiNet:
\_logic_net: (pop), line:159, parent:wb_fifo
|vpiName:pop
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.wb_fifo.pop
|vpiNetType:36
|vpiNet:
\_logic_net: (data_in), line:160, parent:wb_fifo
|vpiName:data_in
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.wb_fifo.data_in
|vpiNetType:36
|vpiRange:
\_range: , line:160
|vpiLeftRange:
\_constant: , line:160
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiRightRange:
\_constant: , line:160
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (data_out), line:161, parent:wb_fifo
|vpiName:data_out
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.wb_fifo.data_out
|vpiNetType:36
|vpiRange:
\_range: , line:161
|vpiLeftRange:
\_constant: , line:161
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiRightRange:
\_constant: , line:161
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (valid), line:162, parent:wb_fifo
|vpiName:valid
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.wb_fifo.valid
|vpiNetType:36
|vpiNet:
\_logic_net: (full), line:163, parent:wb_fifo
|vpiName:full
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.wb_fifo.full
|vpiNetType:36
|vpiNet:
\_logic_net: (supress_push), line:164, parent:wb_fifo
|vpiName:supress_push
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.wb_fifo.supress_push
|vpiNetType:36
|vpiInstance:
\_module: work@div_unit (div_unit_block), file:third_party/cores/taiga/core/taiga.sv, line:199
|vpiModule:
\_module: work@taiga_fifo (div_input_fifo), file:third_party/cores/taiga/core/div_unit.sv, line:100, parent:div_unit_block
|vpiDefName:work@taiga_fifo
|vpiName:div_input_fifo
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.div_input_fifo
|vpiPort:
\_port: (fifo), line:33, parent:div_input_fifo
|vpiName:fifo
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (input_fifo), line:101
|vpiName:input_fifo
|vpiActual:
\_interface: work@fifo_interface (input_fifo), file:third_party/cores/taiga/core/div_unit.sv, line:67
|vpiDefName:work@fifo_interface
|vpiName:input_fifo
|vpiModport:
\_modport: (dequeue)
|vpiName:dequeue
|vpiIODecl:
\_io_decl: (valid)
|vpiName:valid
|vpiDirection:1
|vpiIODecl:
\_io_decl: (data_out)
|vpiName:data_out
|vpiDirection:1
|vpiIODecl:
\_io_decl: (pop)
|vpiName:pop
|vpiDirection:2
|vpiInterface:
\_interface: work@fifo_interface (input_fifo), file:third_party/cores/taiga/core/div_unit.sv, line:67
|vpiModport:
\_modport: (enqueue)
|vpiName:enqueue
|vpiIODecl:
\_io_decl: (full)
|vpiName:full
|vpiDirection:1
|vpiIODecl:
\_io_decl: (data_in)
|vpiName:data_in
|vpiDirection:2
|vpiIODecl:
\_io_decl: (push)
|vpiName:push
|vpiDirection:2
|vpiIODecl:
\_io_decl: (supress_push)
|vpiName:supress_push
|vpiDirection:2
|vpiInterface:
\_interface: work@fifo_interface (input_fifo), file:third_party/cores/taiga/core/div_unit.sv, line:67
|vpiModport:
\_modport: (structure)
|vpiName:structure
|vpiIODecl:
\_io_decl: (push)
|vpiName:push
|vpiDirection:1
|vpiIODecl:
\_io_decl: (pop)
|vpiName:pop
|vpiDirection:1
|vpiIODecl:
\_io_decl: (data_in)
|vpiName:data_in
|vpiDirection:1
|vpiIODecl:
\_io_decl: (supress_push)
|vpiName:supress_push
|vpiDirection:1
|vpiIODecl:
\_io_decl: (data_out)
|vpiName:data_out
|vpiDirection:2
|vpiIODecl:
\_io_decl: (valid)
|vpiName:valid
|vpiDirection:2
|vpiIODecl:
\_io_decl: (full)
|vpiName:full
|vpiDirection:2
|vpiInterface:
\_interface: work@fifo_interface (input_fifo), file:third_party/cores/taiga/core/div_unit.sv, line:67
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_interface: work@fifo_interface (fifo), file:third_party/cores/taiga/core/div_unit.sv, line:100
|vpiDefName:work@fifo_interface
|vpiName:fifo
|vpiModport:
\_modport: (dequeue)
|vpiName:dequeue
|vpiIODecl:
\_io_decl: (valid)
|vpiName:valid
|vpiDirection:1
|vpiExpr:
\_logic_net: (valid), line:162
|vpiName:valid
|vpiNetType:36
|vpiIODecl:
\_io_decl: (data_out)
|vpiName:data_out
|vpiDirection:1
|vpiExpr:
\_logic_net: (data_out), line:161
|vpiName:data_out
|vpiNetType:36
|vpiRange:
\_range: , line:161
|vpiLeftRange:
\_constant: , line:161
|vpiDecompile:-1
|INT:-1
|vpiRightRange:
\_constant: , line:161
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (pop)
|vpiName:pop
|vpiDirection:2
|vpiExpr:
\_logic_net: (pop), line:159
|vpiName:pop
|vpiNetType:36
|vpiInterface:
\_interface: work@fifo_interface (fifo), file:third_party/cores/taiga/core/div_unit.sv, line:100
|vpiModport:
\_modport: (enqueue)
|vpiName:enqueue
|vpiIODecl:
\_io_decl: (full)
|vpiName:full
|vpiDirection:1
|vpiExpr:
\_logic_net: (full), line:163
|vpiName:full
|vpiNetType:36
|vpiIODecl:
\_io_decl: (data_in)
|vpiName:data_in
|vpiDirection:2
|vpiExpr:
\_logic_net: (data_in), line:160
|vpiName:data_in
|vpiNetType:36
|vpiRange:
\_range: , line:160
|vpiLeftRange:
\_constant: , line:160
|vpiDecompile:-1
|INT:-1
|vpiRightRange:
\_constant: , line:160
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (push)
|vpiName:push
|vpiDirection:2
|vpiExpr:
\_logic_net: (push), line:158
|vpiName:push
|vpiNetType:36
|vpiIODecl:
\_io_decl: (supress_push)
|vpiName:supress_push
|vpiDirection:2
|vpiExpr:
\_logic_net: (supress_push), line:164
|vpiName:supress_push
|vpiNetType:36
|vpiInterface:
\_interface: work@fifo_interface (fifo), file:third_party/cores/taiga/core/div_unit.sv, line:100
|vpiModport:
\_modport: (structure)
|vpiName:structure
|vpiIODecl:
\_io_decl: (push)
|vpiName:push
|vpiDirection:1
|vpiExpr:
\_logic_net: (push), line:158
|vpiIODecl:
\_io_decl: (pop)
|vpiName:pop
|vpiDirection:1
|vpiExpr:
\_logic_net: (pop), line:159
|vpiIODecl:
\_io_decl: (data_in)
|vpiName:data_in
|vpiDirection:1
|vpiExpr:
\_logic_net: (data_in), line:160
|vpiIODecl:
\_io_decl: (supress_push)
|vpiName:supress_push
|vpiDirection:1
|vpiExpr:
\_logic_net: (supress_push), line:164
|vpiIODecl:
\_io_decl: (data_out)
|vpiName:data_out
|vpiDirection:2
|vpiExpr:
\_logic_net: (data_out), line:161
|vpiIODecl:
\_io_decl: (valid)
|vpiName:valid
|vpiDirection:2
|vpiExpr:
\_logic_net: (valid), line:162
|vpiIODecl:
\_io_decl: (full)
|vpiName:full
|vpiDirection:2
|vpiExpr:
\_logic_net: (full), line:163
|vpiInterface:
\_interface: work@fifo_interface (fifo), file:third_party/cores/taiga/core/div_unit.sv, line:100
|vpiPort:
\_port: (clk), line:34, parent:div_input_fifo
|vpiName:clk
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (clk), line:101
|vpiName:clk
|vpiActual:
\_logic_net: (clk), line:28, parent:div_unit_block
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (rst), line:34, parent:div_input_fifo
|vpiName:rst
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.div_input_fifo.rst
|vpiNetType:36
|vpiPort:
\_port: (rst), line:35, parent:div_input_fifo
|vpiName:rst
|vpiDirection:5
|vpiHighConn:
\_ref_obj: (rst), line:101
|vpiName:rst
|vpiActual:
\_logic_net: (rst), line:29, parent:div_unit_block
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_modport: (structure)
|vpiName:structure
|vpiIODecl:
\_io_decl: (push)
|vpiName:push
|vpiDirection:1
|vpiExpr:
\_logic_net: (push), line:158
|vpiIODecl:
\_io_decl: (pop)
|vpiName:pop
|vpiDirection:1
|vpiExpr:
\_logic_net: (pop), line:159
|vpiIODecl:
\_io_decl: (data_in)
|vpiName:data_in
|vpiDirection:1
|vpiExpr:
\_logic_net: (data_in), line:160
|vpiIODecl:
\_io_decl: (supress_push)
|vpiName:supress_push
|vpiDirection:1
|vpiExpr:
\_logic_net: (supress_push), line:164
|vpiIODecl:
\_io_decl: (data_out)
|vpiName:data_out
|vpiDirection:2
|vpiExpr:
\_logic_net: (data_out), line:161
|vpiIODecl:
\_io_decl: (valid)
|vpiName:valid
|vpiDirection:2
|vpiExpr:
\_logic_net: (valid), line:162
|vpiIODecl:
\_io_decl: (full)
|vpiName:full
|vpiDirection:2
|vpiExpr:
\_logic_net: (full), line:163
|vpiInterface:
\_interface: work@fifo_interface (fifo), file:third_party/cores/taiga/core/div_unit.sv, line:100
|vpiDefName:work@fifo_interface
|vpiName:fifo
|vpiModport:
\_modport: (dequeue)
|vpiName:dequeue
|vpiIODecl:
\_io_decl: (valid)
|vpiName:valid
|vpiDirection:1
|vpiExpr:
\_logic_net: (valid), line:162
|vpiIODecl:
\_io_decl: (data_out)
|vpiName:data_out
|vpiDirection:1
|vpiExpr:
\_logic_net: (data_out), line:161
|vpiIODecl:
\_io_decl: (pop)
|vpiName:pop
|vpiDirection:2
|vpiExpr:
\_logic_net: (pop), line:159
|vpiInterface:
\_interface: work@fifo_interface (fifo), file:third_party/cores/taiga/core/div_unit.sv, line:100
|vpiModport:
\_modport: (enqueue)
|vpiName:enqueue
|vpiIODecl:
\_io_decl: (full)
|vpiName:full
|vpiDirection:1
|vpiExpr:
\_logic_net: (full), line:163
|vpiIODecl:
\_io_decl: (data_in)
|vpiName:data_in
|vpiDirection:2
|vpiExpr:
\_logic_net: (data_in), line:160
|vpiIODecl:
\_io_decl: (push)
|vpiName:push
|vpiDirection:2
|vpiExpr:
\_logic_net: (push), line:158
|vpiIODecl:
\_io_decl: (supress_push)
|vpiName:supress_push
|vpiDirection:2
|vpiExpr:
\_logic_net: (supress_push), line:164
|vpiInterface:
\_interface: work@fifo_interface (fifo), file:third_party/cores/taiga/core/div_unit.sv, line:100
|vpiModport:
\_modport: (structure)
|vpiPort:
\_port: (fifo), parent:div_input_fifo
|vpiName:fifo
|vpiHighConn:
\_ref_obj: (fifo), line:101
|vpiName:fifo
|vpiGenScopeArray:
\_gen_scope_array: (genblk1), line:65, parent:div_input_fifo
|vpiName:genblk1
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.div_input_fifo.genblk1
|vpiGenScope:
\_gen_scope: , parent:genblk1
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.div_input_fifo.genblk1
|vpiProcess:
\_always: , line:68
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:68
|vpiCondition:
\_operation: , line:68
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:68
|vpiName:clk
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.div_input_fifo.genblk1.clk
|vpiStmt:
\_begin: , line:68
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.div_input_fifo.genblk1
|vpiStmt:
\_if_else: , line:69
|vpiCondition:
\_ref_obj: (rst), line:69
|vpiName:rst
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.div_input_fifo.genblk1.rst
|vpiStmt:
\_assignment: , line:70
|vpiOpType:82
|vpiLhs:
\_ref_obj: (inflight_count), line:70
|vpiName:inflight_count
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.div_input_fifo.genblk1.inflight_count
|vpiRhs:
\_constant: , line:70
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiElseStmt:
\_assignment: , line:72
|vpiOpType:82
|vpiLhs:
\_ref_obj: (inflight_count), line:72
|vpiName:inflight_count
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.div_input_fifo.genblk1.inflight_count
|vpiRhs:
\_operation: , line:72
|vpiOpType:11
|vpiOperand:
\_operation: , line:72
|vpiOpType:24
|vpiOperand:
\_ref_obj: (inflight_count), line:72
|vpiName:inflight_count
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.div_input_fifo.genblk1.inflight_count
|vpiOperand:
\_operation: , line:72
|vpiOpType:67
|vpiOperand:
\_ref_obj: (fifo.pop), line:72
|vpiName:fifo.pop
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.div_input_fifo.genblk1.fifo.pop
|vpiOperand:
\_operation: , line:72
|vpiOpType:67
|vpiOperand:
\_ref_obj: (supressed_push), line:72
|vpiName:supressed_push
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.div_input_fifo.genblk1.supressed_push
|vpiProcess:
\_always: , line:78
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:78
|vpiCondition:
\_operation: , line:78
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:78
|vpiName:clk
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.div_input_fifo.genblk1.clk
|vpiStmt:
\_begin: , line:78
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.div_input_fifo.genblk1
|vpiStmt:
\_if_else: , line:79
|vpiCondition:
\_ref_obj: (rst), line:79
|vpiName:rst
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.div_input_fifo.genblk1.rst
|vpiStmt:
\_begin: , line:79
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.div_input_fifo.genblk1
|vpiStmt:
\_assignment: , line:80
|vpiOpType:82
|vpiLhs:
\_ref_obj: (read_index), line:80
|vpiName:read_index
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.div_input_fifo.genblk1.read_index
|vpiRhs:
\_constant: , line:80
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiStmt:
\_assignment: , line:81
|vpiOpType:82
|vpiLhs:
\_ref_obj: (write_index), line:81
|vpiName:write_index
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.div_input_fifo.genblk1.write_index
|vpiRhs:
\_constant: , line:81
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiElseStmt:
\_begin: , line:83
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.div_input_fifo.genblk1
|vpiStmt:
\_assignment: , line:84
|vpiOpType:82
|vpiLhs:
\_ref_obj: (read_index), line:84
|vpiName:read_index
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.div_input_fifo.genblk1.read_index
|vpiRhs:
\_operation: , line:84
|vpiOpType:24
|vpiOperand:
\_ref_obj: (read_index), line:84
|vpiName:read_index
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.div_input_fifo.genblk1.read_index
|vpiOperand:
\_operation: , line:84
|vpiOpType:67
|vpiOperand:
\_ref_obj: (fifo.pop), line:84
|vpiName:fifo.pop
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.div_input_fifo.genblk1.fifo.pop
|vpiTypespec:
\_void_typespec: (LOG2_FIFO_DEPTH), line:84
|vpiName:LOG2_FIFO_DEPTH
|vpiStmt:
\_assignment: , line:85
|vpiOpType:82
|vpiLhs:
\_ref_obj: (write_index), line:85
|vpiName:write_index
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.div_input_fifo.genblk1.write_index
|vpiRhs:
\_operation: , line:85
|vpiOpType:24
|vpiOperand:
\_ref_obj: (write_index), line:85
|vpiName:write_index
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.div_input_fifo.genblk1.write_index
|vpiOperand:
\_operation: , line:85
|vpiOpType:67
|vpiOperand:
\_ref_obj: (supressed_push), line:85
|vpiName:supressed_push
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.div_input_fifo.genblk1.supressed_push
|vpiTypespec:
\_void_typespec: (LOG2_FIFO_DEPTH), line:85
|vpiName:LOG2_FIFO_DEPTH
|vpiProcess:
\_always: , line:89
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:89
|vpiCondition:
\_operation: , line:89
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:89
|vpiName:clk
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.div_input_fifo.genblk1.clk
|vpiStmt:
\_begin: , line:89
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.div_input_fifo.genblk1
|vpiStmt:
\_if_stmt: , line:90
|vpiCondition:
\_ref_obj: (fifo.push), line:90
|vpiName:fifo.push
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.div_input_fifo.genblk1.fifo.push
|vpiStmt:
\_assignment: , line:91
|vpiOpType:82
|vpiLhs:
\_bit_select: (lut_ram), line:91
|vpiName:lut_ram
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.div_input_fifo.genblk1.lut_ram
|vpiIndex:
\_ref_obj: (write_index), line:91
|vpiName:write_index
|vpiRhs:
\_ref_obj: (fifo.data_in), line:91
|vpiName:fifo.data_in
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.div_input_fifo.genblk1.fifo.data_in
|vpiContAssign:
\_cont_assign: , line:75
|vpiRhs:
\_bit_select: (inflight_count), line:75
|vpiName:inflight_count
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.div_input_fifo.genblk1.inflight_count
|vpiIndex:
\_ref_obj: (LOG2_FIFO_DEPTH), line:75
|vpiName:LOG2_FIFO_DEPTH
|vpiLhs:
\_ref_obj: (fifo.valid), line:75
|vpiName:fifo.valid
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.div_input_fifo.genblk1.fifo.valid
|vpiContAssign:
\_cont_assign: , line:76
|vpiRhs:
\_operation: , line:76
|vpiOpType:28
|vpiOperand:
\_ref_obj: (fifo.valid), line:76
|vpiName:fifo.valid
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.div_input_fifo.genblk1.fifo.valid
|vpiOperand:
\_operation: , line:76
|vpiOpType:8
|vpiOperand:
\_part_select: , line:76, parent:inflight_count
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (inflight_count)
|vpiLeftRange:
\_operation: , line:76
|vpiOpType:11
|vpiOperand:
\_ref_obj: (LOG2_FIFO_DEPTH), line:76
|vpiName:LOG2_FIFO_DEPTH
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.div_input_fifo.genblk1.LOG2_FIFO_DEPTH
|vpiOperand:
\_constant: , line:76
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:76
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiLhs:
\_ref_obj: (fifo.full), line:76
|vpiName:fifo.full
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.div_input_fifo.genblk1.fifo.full
|vpiContAssign:
\_cont_assign: , line:93
|vpiRhs:
\_bit_select: (lut_ram), line:93
|vpiName:lut_ram
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.div_input_fifo.genblk1.lut_ram
|vpiIndex:
\_ref_obj: (read_index), line:93
|vpiName:read_index
|vpiLhs:
\_ref_obj: (fifo.data_out), line:93
|vpiName:fifo.data_out
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.div_input_fifo.genblk1.fifo.data_out
|vpiParameter:
\_parameter: (ALU_UNIT_WB_ID), line:190
|vpiName:ALU_UNIT_WB_ID
|INT:32
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (BRANCH_PREDICTOR_WAYS), line:159
|vpiName:BRANCH_PREDICTOR_WAYS
|INT:9
|vpiParameter:
\_parameter: (BRANCH_TABLE_ENTRIES), line:160
|vpiName:BRANCH_TABLE_ENTRIES
|INT:4
|vpiParameter:
\_parameter: (BRANCH_UNIT_ID), line:195
|vpiName:BRANCH_UNIT_ID
|INT:8
|vpiParameter:
\_parameter: (BUS_ADDR_H), line:107
|vpiName:BUS_ADDR_H
|INT:1
|vpiParameter:
\_parameter: (BUS_ADDR_L), line:106
|vpiName:BUS_ADDR_L
|INT:0
|vpiParameter:
\_parameter: (BUS_BIT_CHECK), line:108
|vpiName:BUS_BIT_CHECK
|INT:1
|vpiParameter:
\_parameter: (BUS_TYPE), line:89
|vpiName:BUS_TYPE
|INT:5
|vpiParameter:
\_parameter: (COUNTER_W), line:42
|vpiName:COUNTER_W
|INT:33
|vpiParameter:
\_parameter: (CPU_ID), line:38
|vpiName:CPU_ID
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_ADDR_WIDTH), line:113
|vpiName:C_M_AXI_ADDR_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_DATA_WIDTH), line:114
|vpiName:C_M_AXI_DATA_WIDTH
|INT:1
|vpiParameter:
\_parameter: (DCACHE_LINES), line:133
|vpiName:DCACHE_LINES
|INT:-2146435073
|vpiParameter:
\_parameter: (DCACHE_LINE_ADDR_W), line:135
|vpiName:DCACHE_LINE_ADDR_W
|INT:1073741824
|vpiParameter:
\_parameter: (DCACHE_LINE_W), line:136
|vpiName:DCACHE_LINE_W
|INT:1342177279
|vpiParameter:
\_parameter: (DCACHE_SUB_LINE_ADDR_W), line:137
|vpiName:DCACHE_SUB_LINE_ADDR_W
|INT:4
|vpiParameter:
\_parameter: (DCACHE_TAG_W), line:138
|vpiName:DCACHE_TAG_W
|INT:1610612736
|vpiParameter:
\_parameter: (DCACHE_WAYS), line:134
|vpiName:DCACHE_WAYS
|INT:4
|vpiParameter:
\_parameter: (DIV_ALGORITHM), line:67
|vpiName:DIV_ALGORITHM
|INT:0
|vpiParameter:
\_parameter: (DIV_UNIT_WB_ID), line:192
|vpiName:DIV_UNIT_WB_ID
|INT:2
|vpiParameter:
\_parameter: (DTLB_DEPTH), line:152
|vpiName:DTLB_DEPTH
|INT:512
|vpiParameter:
\_parameter: (DTLB_WAYS), line:151
|vpiName:DTLB_WAYS
|INT:32
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (ENABLE_M_MODE), line:34
|vpiName:ENABLE_M_MODE
|INT:1
|vpiParameter:
\_parameter: (ENABLE_S_MODE), line:36
|vpiName:ENABLE_S_MODE
|INT:0
|vpiParameter:
\_parameter: (ENABLE_TRACE_INTERFACE), line:172
|vpiName:ENABLE_TRACE_INTERFACE
|INT:2
|vpiParameter:
\_parameter: (FETCH_BUFFER_DEPTH), line:168
|vpiName:FETCH_BUFFER_DEPTH
|INT:512
|vpiParameter:
\_parameter: (FPGA_VENDOR), line:27
|vpiName:FPGA_VENDOR
|STRING:"xilinx"
|vpiParameter:
\_parameter: (GC_UNIT_ID), line:196
|vpiName:GC_UNIT_ID
|INT:4
|vpiParameter:
\_parameter: (ICACHE_LINES), line:121
|vpiName:ICACHE_LINES
|INT:2
|vpiParameter:
\_parameter: (ICACHE_LINE_ADDR_W), line:123
|vpiName:ICACHE_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_LINE_W), line:124
|vpiName:ICACHE_LINE_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_SUB_LINE_ADDR_W), line:125
|vpiName:ICACHE_SUB_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_TAG_W), line:126
|vpiName:ICACHE_TAG_W
|INT:-2147483648
|vpiParameter:
\_parameter: (ICACHE_WAYS), line:122
|vpiName:ICACHE_WAYS
|INT:1
|vpiParameter:
\_parameter: (ITLB_DEPTH), line:146
|vpiName:ITLB_DEPTH
|INT:32
|vpiParameter:
\_parameter: (ITLB_WAYS), line:145
|vpiName:ITLB_WAYS
|INT:4
|vpiParameter:
\_parameter: (L1_CONNECTIONS), line:177
|vpiName:L1_CONNECTIONS
|INT:9
|vpiParameter:
\_parameter: (L1_DCACHE_ID), line:178
|vpiName:L1_DCACHE_ID
|INT:4
|vpiParameter:
\_parameter: (L1_DMMU_ID), line:179
|vpiName:L1_DMMU_ID
|INT:2
|vpiParameter:
\_parameter: (L1_ICACHE_ID), line:180
|vpiName:L1_ICACHE_ID
|INT:19
|vpiParameter:
\_parameter: (L1_IMMU_ID), line:181
|vpiName:L1_IMMU_ID
|INT:0
|vpiParameter:
\_parameter: (LS_UNIT_WB_ID), line:191
|vpiName:LS_UNIT_WB_ID
|INT:1
|vpiParameter:
\_parameter: (MAX_INFLIGHT_COUNT), line:167
|vpiName:MAX_INFLIGHT_COUNT
|INT:19
|vpiParameter:
\_parameter: (MEMORY_ADDR_H), line:103
|vpiName:MEMORY_ADDR_H
|INT:12
|vpiParameter:
\_parameter: (MEMORY_ADDR_L), line:102
|vpiName:MEMORY_ADDR_L
|INT:11
|vpiParameter:
\_parameter: (MEMORY_BIT_CHECK), line:104
|vpiName:MEMORY_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (MUL_UNIT_WB_ID), line:193
|vpiName:MUL_UNIT_WB_ID
|INT:512
|vpiParameter:
\_parameter: (NUM_UNITS), line:188
|vpiName:NUM_UNITS
|INT:2
|vpiParameter:
\_parameter: (NUM_WB_UNITS), line:186
|vpiName:NUM_WB_UNITS
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (RAS_DEPTH), line:161
|vpiName:RAS_DEPTH
|INT:2
|vpiParameter:
\_parameter: (RESET_VEC), line:39
|vpiName:RESET_VEC
|INT:-2147483648
|vpiParameter:
\_parameter: (SCRATCH_ADDR_H), line:99
|vpiName:SCRATCH_ADDR_H
|INT:9
|vpiParameter:
\_parameter: (SCRATCH_ADDR_L), line:98
|vpiName:SCRATCH_ADDR_L
|INT:8
|vpiParameter:
\_parameter: (SCRATCH_BIT_CHECK), line:100
|vpiName:SCRATCH_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (USE_AMO), line:70
|vpiName:USE_AMO
|INT:1
|vpiParameter:
\_parameter: (USE_BRANCH_PREDICTOR), line:158
|vpiName:USE_BRANCH_PREDICTOR
|INT:2
|vpiParameter:
\_parameter: (USE_BUS), line:88
|vpiName:USE_BUS
|INT:4
|vpiParameter:
\_parameter: (USE_DCACHE), line:92
|vpiName:USE_DCACHE
|INT:6
|vpiParameter:
\_parameter: (USE_DIV), line:49
|vpiName:USE_DIV
|INT:1
|vpiParameter:
\_parameter: (USE_DTAG_INVALIDATIONS), line:140
|vpiName:USE_DTAG_INVALIDATIONS
|INT:1879048191
|vpiParameter:
\_parameter: (USE_D_SCRATCH_MEM), line:79
|vpiName:USE_D_SCRATCH_MEM
|INT:3
|vpiParameter:
\_parameter: (USE_ICACHE), line:93
|vpiName:USE_ICACHE
|INT:7
|vpiParameter:
\_parameter: (USE_I_SCRATCH_MEM), line:78
|vpiName:USE_I_SCRATCH_MEM
|INT:2
|vpiParameter:
\_parameter: (USE_MUL), line:48
|vpiName:USE_MUL
|INT:1
|vpiParameter:
\_parameter: (WB_UNITS_WIDTH), line:187
|vpiName:WB_UNITS_WIDTH
|INT:32
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiNet:
\_logic_net: (clk), line:33, parent:div_input_fifo
|vpiName:clk
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.div_input_fifo.clk
|vpiNetType:36
|vpiNet:
\_logic_net: (rst), line:34, parent:div_input_fifo
|vpiNet:
\_logic_net: (write_index), line:41, parent:div_input_fifo
|vpiName:write_index
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.div_input_fifo.write_index
|vpiNetType:36
|vpiRange:
\_range: , line:41
|vpiLeftRange:
\_constant: , line:41
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:41
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (read_index), line:42, parent:div_input_fifo
|vpiName:read_index
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.div_input_fifo.read_index
|vpiNetType:36
|vpiRange:
\_range: , line:42
|vpiLeftRange:
\_constant: , line:42
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:42
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (inflight_count), line:43, parent:div_input_fifo
|vpiName:inflight_count
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.div_input_fifo.inflight_count
|vpiNetType:36
|vpiRange:
\_range: , line:43
|vpiLeftRange:
\_constant: , line:43
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiRightRange:
\_constant: , line:43
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (supressed_push), line:44, parent:div_input_fifo
|vpiName:supressed_push
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.div_input_fifo.supressed_push
|vpiNetType:36
|vpiNet:
\_logic_net: (fifo), line:35, parent:div_input_fifo
|vpiName:fifo
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.div_input_fifo.fifo
|vpiInstance:
\_module: work@div_unit (div_unit_block), file:third_party/cores/taiga/core/taiga.sv, line:199
|vpiArrayNet:
\_array_net: (lut_ram), line:40, parent:div_input_fifo
|vpiName:lut_ram
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.div_input_fifo.lut_ram
|vpiSize:2
|vpiNet:
\_logic_net: , parent:lut_ram
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.div_input_fifo.lut_ram
|vpiNetType:36
|vpiRange:
\_range: , line:40
|vpiLeftRange:
\_constant: , line:40
|vpiDecompile:-1
|INT:-1
|vpiRightRange:
\_constant: , line:40
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiRange:
\_range: , line:40
|vpiLeftRange:
\_constant: , line:40
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:40
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiParameter:
\_parameter: (ALU_UNIT_WB_ID), line:190
|vpiName:ALU_UNIT_WB_ID
|INT:32
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (BRANCH_PREDICTOR_WAYS), line:159
|vpiName:BRANCH_PREDICTOR_WAYS
|INT:9
|vpiParameter:
\_parameter: (BRANCH_TABLE_ENTRIES), line:160
|vpiName:BRANCH_TABLE_ENTRIES
|INT:4
|vpiParameter:
\_parameter: (BRANCH_UNIT_ID), line:195
|vpiName:BRANCH_UNIT_ID
|INT:8
|vpiParameter:
\_parameter: (BUS_ADDR_H), line:107
|vpiName:BUS_ADDR_H
|INT:1
|vpiParameter:
\_parameter: (BUS_ADDR_L), line:106
|vpiName:BUS_ADDR_L
|INT:0
|vpiParameter:
\_parameter: (BUS_BIT_CHECK), line:108
|vpiName:BUS_BIT_CHECK
|INT:1
|vpiParameter:
\_parameter: (BUS_TYPE), line:89
|vpiName:BUS_TYPE
|INT:5
|vpiParameter:
\_parameter: (COUNTER_W), line:42
|vpiName:COUNTER_W
|INT:33
|vpiParameter:
\_parameter: (CPU_ID), line:38
|vpiName:CPU_ID
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_ADDR_WIDTH), line:113
|vpiName:C_M_AXI_ADDR_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_DATA_WIDTH), line:114
|vpiName:C_M_AXI_DATA_WIDTH
|INT:1
|vpiParameter:
\_parameter: (DATA_WIDTH), line:100
|vpiName:DATA_WIDTH
|INT:0
|vpiParameter:
\_parameter: (DCACHE_LINES), line:133
|vpiName:DCACHE_LINES
|INT:-2146435073
|vpiParameter:
\_parameter: (DCACHE_LINE_ADDR_W), line:135
|vpiName:DCACHE_LINE_ADDR_W
|INT:1073741824
|vpiParameter:
\_parameter: (DCACHE_LINE_W), line:136
|vpiName:DCACHE_LINE_W
|INT:1342177279
|vpiParameter:
\_parameter: (DCACHE_SUB_LINE_ADDR_W), line:137
|vpiName:DCACHE_SUB_LINE_ADDR_W
|INT:4
|vpiParameter:
\_parameter: (DCACHE_TAG_W), line:138
|vpiName:DCACHE_TAG_W
|INT:1610612736
|vpiParameter:
\_parameter: (DCACHE_WAYS), line:134
|vpiName:DCACHE_WAYS
|INT:4
|vpiParameter:
\_parameter: (DIV_ALGORITHM), line:67
|vpiName:DIV_ALGORITHM
|INT:0
|vpiParameter:
\_parameter: (DIV_UNIT_WB_ID), line:192
|vpiName:DIV_UNIT_WB_ID
|INT:2
|vpiParameter:
\_parameter: (DTLB_DEPTH), line:152
|vpiName:DTLB_DEPTH
|INT:512
|vpiParameter:
\_parameter: (DTLB_WAYS), line:151
|vpiName:DTLB_WAYS
|INT:32
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (ENABLE_M_MODE), line:34
|vpiName:ENABLE_M_MODE
|INT:1
|vpiParameter:
\_parameter: (ENABLE_S_MODE), line:36
|vpiName:ENABLE_S_MODE
|INT:0
|vpiParameter:
\_parameter: (ENABLE_TRACE_INTERFACE), line:172
|vpiName:ENABLE_TRACE_INTERFACE
|INT:2
|vpiParameter:
\_parameter: (FETCH_BUFFER_DEPTH), line:168
|vpiName:FETCH_BUFFER_DEPTH
|INT:512
|vpiParameter:
\_parameter: (FIFO_DEPTH), line:100
|vpiName:FIFO_DEPTH
|INT:19
|vpiParameter:
\_parameter: (FPGA_VENDOR), line:27
|vpiName:FPGA_VENDOR
|STRING:"xilinx"
|vpiParameter:
\_parameter: (GC_UNIT_ID), line:196
|vpiName:GC_UNIT_ID
|INT:4
|vpiParameter:
\_parameter: (ICACHE_LINES), line:121
|vpiName:ICACHE_LINES
|INT:2
|vpiParameter:
\_parameter: (ICACHE_LINE_ADDR_W), line:123
|vpiName:ICACHE_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_LINE_W), line:124
|vpiName:ICACHE_LINE_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_SUB_LINE_ADDR_W), line:125
|vpiName:ICACHE_SUB_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_TAG_W), line:126
|vpiName:ICACHE_TAG_W
|INT:-2147483648
|vpiParameter:
\_parameter: (ICACHE_WAYS), line:122
|vpiName:ICACHE_WAYS
|INT:1
|vpiParameter:
\_parameter: (ITLB_DEPTH), line:146
|vpiName:ITLB_DEPTH
|INT:32
|vpiParameter:
\_parameter: (ITLB_WAYS), line:145
|vpiName:ITLB_WAYS
|INT:4
|vpiParameter:
\_parameter: (L1_CONNECTIONS), line:177
|vpiName:L1_CONNECTIONS
|INT:9
|vpiParameter:
\_parameter: (L1_DCACHE_ID), line:178
|vpiName:L1_DCACHE_ID
|INT:4
|vpiParameter:
\_parameter: (L1_DMMU_ID), line:179
|vpiName:L1_DMMU_ID
|INT:2
|vpiParameter:
\_parameter: (L1_ICACHE_ID), line:180
|vpiName:L1_ICACHE_ID
|INT:19
|vpiParameter:
\_parameter: (L1_IMMU_ID), line:181
|vpiName:L1_IMMU_ID
|INT:0
|vpiParameter:
\_parameter: (LOG2_FIFO_DEPTH), line:38
|vpiName:LOG2_FIFO_DEPTH
|INT:2
|vpiParameter:
\_parameter: (LS_UNIT_WB_ID), line:191
|vpiName:LS_UNIT_WB_ID
|INT:1
|vpiParameter:
\_parameter: (MAX_INFLIGHT_COUNT), line:167
|vpiName:MAX_INFLIGHT_COUNT
|INT:19
|vpiParameter:
\_parameter: (MEMORY_ADDR_H), line:103
|vpiName:MEMORY_ADDR_H
|INT:12
|vpiParameter:
\_parameter: (MEMORY_ADDR_L), line:102
|vpiName:MEMORY_ADDR_L
|INT:11
|vpiParameter:
\_parameter: (MEMORY_BIT_CHECK), line:104
|vpiName:MEMORY_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (MUL_UNIT_WB_ID), line:193
|vpiName:MUL_UNIT_WB_ID
|INT:512
|vpiParameter:
\_parameter: (NUM_UNITS), line:188
|vpiName:NUM_UNITS
|INT:2
|vpiParameter:
\_parameter: (NUM_WB_UNITS), line:186
|vpiName:NUM_WB_UNITS
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (RAS_DEPTH), line:161
|vpiName:RAS_DEPTH
|INT:2
|vpiParameter:
\_parameter: (RESET_VEC), line:39
|vpiName:RESET_VEC
|INT:-2147483648
|vpiParameter:
\_parameter: (SCRATCH_ADDR_H), line:99
|vpiName:SCRATCH_ADDR_H
|INT:9
|vpiParameter:
\_parameter: (SCRATCH_ADDR_L), line:98
|vpiName:SCRATCH_ADDR_L
|INT:8
|vpiParameter:
\_parameter: (SCRATCH_BIT_CHECK), line:100
|vpiName:SCRATCH_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (USE_AMO), line:70
|vpiName:USE_AMO
|INT:1
|vpiParameter:
\_parameter: (USE_BRANCH_PREDICTOR), line:158
|vpiName:USE_BRANCH_PREDICTOR
|INT:2
|vpiParameter:
\_parameter: (USE_BUS), line:88
|vpiName:USE_BUS
|INT:4
|vpiParameter:
\_parameter: (USE_DCACHE), line:92
|vpiName:USE_DCACHE
|INT:6
|vpiParameter:
\_parameter: (USE_DIV), line:49
|vpiName:USE_DIV
|INT:1
|vpiParameter:
\_parameter: (USE_DTAG_INVALIDATIONS), line:140
|vpiName:USE_DTAG_INVALIDATIONS
|INT:1879048191
|vpiParameter:
\_parameter: (USE_D_SCRATCH_MEM), line:79
|vpiName:USE_D_SCRATCH_MEM
|INT:3
|vpiParameter:
\_parameter: (USE_ICACHE), line:93
|vpiName:USE_ICACHE
|INT:7
|vpiParameter:
\_parameter: (USE_I_SCRATCH_MEM), line:78
|vpiName:USE_I_SCRATCH_MEM
|INT:2
|vpiParameter:
\_parameter: (USE_MUL), line:48
|vpiName:USE_MUL
|INT:1
|vpiParameter:
\_parameter: (WB_UNITS_WIDTH), line:187
|vpiName:WB_UNITS_WIDTH
|INT:32
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiModule:
\_module: work@div_algorithm (divider_block), file:third_party/cores/taiga/core/div_unit.sv, line:129, parent:div_unit_block
|vpiDefName:work@div_algorithm
|vpiName:divider_block
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block
|vpiPort:
\_port: (clk), line:29, parent:divider_block
|vpiName:clk
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (clk), line:129
|vpiName:clk
|vpiActual:
\_logic_net: (clk), line:28, parent:div_unit_block
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (clk), line:29, parent:divider_block
|vpiName:clk
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.clk
|vpiNetType:36
|vpiPort:
\_port: (rst), line:30, parent:divider_block
|vpiName:rst
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (rst), line:129
|vpiName:rst
|vpiActual:
\_logic_net: (rst), line:29, parent:div_unit_block
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (rst), line:30, parent:divider_block
|vpiName:rst
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.rst
|vpiNetType:36
|vpiPort:
\_port: (div), line:31, parent:divider_block
|vpiName:div
|vpiDirection:5
|vpiHighConn:
\_ref_obj: (div), line:129
|vpiName:div
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_modport: (divider)
|vpiName:divider
|vpiIODecl:
\_io_decl: (remainder)
|vpiName:remainder
|vpiDirection:2
|vpiExpr:
\_logic_net: (remainder), line:247
|vpiName:remainder
|vpiNetType:36
|vpiRange:
\_range: , line:247
|vpiLeftRange:
\_constant: , line:247
|vpiDecompile:31
|INT:31
|vpiRightRange:
\_constant: , line:247
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (quotient)
|vpiName:quotient
|vpiDirection:2
|vpiExpr:
\_logic_net: (quotient), line:248
|vpiName:quotient
|vpiNetType:36
|vpiRange:
\_range: , line:248
|vpiLeftRange:
\_constant: , line:248
|vpiDecompile:31
|INT:31
|vpiRightRange:
\_constant: , line:248
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (done)
|vpiName:done
|vpiDirection:2
|vpiExpr:
\_logic_net: (done), line:249
|vpiName:done
|vpiNetType:36
|vpiIODecl:
\_io_decl: (divisor_is_zero)
|vpiName:divisor_is_zero
|vpiDirection:2
|vpiExpr:
\_logic_net: (divisor_is_zero), line:250
|vpiName:divisor_is_zero
|vpiNetType:36
|vpiIODecl:
\_io_decl: (dividend)
|vpiName:dividend
|vpiDirection:1
|vpiExpr:
\_logic_net: (dividend), line:245
|vpiName:dividend
|vpiNetType:36
|vpiRange:
\_range: , line:245
|vpiLeftRange:
\_constant: , line:245
|vpiDecompile:31
|INT:31
|vpiRightRange:
\_constant: , line:245
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (divisor)
|vpiName:divisor
|vpiDirection:1
|vpiExpr:
\_logic_net: (divisor), line:246
|vpiName:divisor
|vpiNetType:36
|vpiRange:
\_range: , line:246
|vpiLeftRange:
\_constant: , line:246
|vpiDecompile:31
|INT:31
|vpiRightRange:
\_constant: , line:246
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (start)
|vpiName:start
|vpiDirection:1
|vpiExpr:
\_logic_net: (start), line:244
|vpiName:start
|vpiNetType:36
|vpiInterface:
\_interface: work@unsigned_division_interface (div), file:third_party/cores/taiga/core/div_unit.sv, line:129
|vpiDefName:work@unsigned_division_interface
|vpiName:div
|vpiModport:
\_modport: (divider)
|vpiModport:
\_modport: (requester)
|vpiName:requester
|vpiIODecl:
\_io_decl: (remainder)
|vpiName:remainder
|vpiDirection:1
|vpiExpr:
\_logic_net: (remainder), line:247
|vpiIODecl:
\_io_decl: (quotient)
|vpiName:quotient
|vpiDirection:1
|vpiExpr:
\_logic_net: (quotient), line:248
|vpiIODecl:
\_io_decl: (done)
|vpiName:done
|vpiDirection:1
|vpiExpr:
\_logic_net: (done), line:249
|vpiIODecl:
\_io_decl: (divisor_is_zero)
|vpiName:divisor_is_zero
|vpiDirection:1
|vpiExpr:
\_logic_net: (divisor_is_zero), line:250
|vpiIODecl:
\_io_decl: (dividend)
|vpiName:dividend
|vpiDirection:2
|vpiExpr:
\_logic_net: (dividend), line:245
|vpiIODecl:
\_io_decl: (divisor)
|vpiName:divisor
|vpiDirection:2
|vpiExpr:
\_logic_net: (divisor), line:246
|vpiIODecl:
\_io_decl: (start)
|vpiName:start
|vpiDirection:2
|vpiExpr:
\_logic_net: (start), line:244
|vpiInterface:
\_interface: work@unsigned_division_interface (div), file:third_party/cores/taiga/core/div_unit.sv, line:129
|vpiModule:
\_module: work@div_radix2 (div_block), file:third_party/cores/taiga/core/div_algorithms/div_algorithm.sv, line:36, parent:divider_block
|vpiDefName:work@div_radix2
|vpiName:div_block
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block
|vpiPort:
\_port: (clk), line:27, parent:div_block
|vpiName:clk
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (clk), line:36
|vpiName:clk
|vpiActual:
\_logic_net: (clk), line:29, parent:divider_block
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (clk), line:27, parent:div_block
|vpiName:clk
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.clk
|vpiNetType:36
|vpiPort:
\_port: (rst), line:28, parent:div_block
|vpiName:rst
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (rst), line:36
|vpiName:rst
|vpiActual:
\_logic_net: (rst), line:30, parent:divider_block
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (rst), line:28, parent:div_block
|vpiName:rst
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.rst
|vpiNetType:36
|vpiPort:
\_port: (div), line:29, parent:div_block
|vpiName:div
|vpiDirection:5
|vpiHighConn:
\_ref_obj: (div), line:36
|vpiName:div
|vpiActual:
\_interface: work@unsigned_division_interface (div), file:third_party/cores/taiga/core/div_unit.sv, line:129
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_modport: (divider)
|vpiName:divider
|vpiIODecl:
\_io_decl: (remainder)
|vpiName:remainder
|vpiDirection:2
|vpiExpr:
\_logic_net: (remainder), line:247
|vpiName:remainder
|vpiNetType:36
|vpiRange:
\_range: , line:247
|vpiLeftRange:
\_constant: , line:247
|vpiDecompile:31
|INT:31
|vpiRightRange:
\_constant: , line:247
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (quotient)
|vpiName:quotient
|vpiDirection:2
|vpiExpr:
\_logic_net: (quotient), line:248
|vpiName:quotient
|vpiNetType:36
|vpiRange:
\_range: , line:248
|vpiLeftRange:
\_constant: , line:248
|vpiDecompile:31
|INT:31
|vpiRightRange:
\_constant: , line:248
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (done)
|vpiName:done
|vpiDirection:2
|vpiExpr:
\_logic_net: (done), line:249
|vpiName:done
|vpiNetType:36
|vpiIODecl:
\_io_decl: (divisor_is_zero)
|vpiName:divisor_is_zero
|vpiDirection:2
|vpiExpr:
\_logic_net: (divisor_is_zero), line:250
|vpiName:divisor_is_zero
|vpiNetType:36
|vpiIODecl:
\_io_decl: (dividend)
|vpiName:dividend
|vpiDirection:1
|vpiExpr:
\_logic_net: (dividend), line:245
|vpiName:dividend
|vpiNetType:36
|vpiRange:
\_range: , line:245
|vpiLeftRange:
\_constant: , line:245
|vpiDecompile:31
|INT:31
|vpiRightRange:
\_constant: , line:245
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (divisor)
|vpiName:divisor
|vpiDirection:1
|vpiExpr:
\_logic_net: (divisor), line:246
|vpiName:divisor
|vpiNetType:36
|vpiRange:
\_range: , line:246
|vpiLeftRange:
\_constant: , line:246
|vpiDecompile:31
|INT:31
|vpiRightRange:
\_constant: , line:246
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (start)
|vpiName:start
|vpiDirection:1
|vpiExpr:
\_logic_net: (start), line:244
|vpiName:start
|vpiNetType:36
|vpiInterface:
\_interface: work@unsigned_division_interface (div), file:third_party/cores/taiga/core/div_algorithms/div_algorithm.sv, line:36
|vpiDefName:work@unsigned_division_interface
|vpiName:div
|vpiModport:
\_modport: (divider)
|vpiModport:
\_modport: (requester)
|vpiName:requester
|vpiIODecl:
\_io_decl: (remainder)
|vpiName:remainder
|vpiDirection:1
|vpiExpr:
\_logic_net: (remainder), line:247
|vpiIODecl:
\_io_decl: (quotient)
|vpiName:quotient
|vpiDirection:1
|vpiExpr:
\_logic_net: (quotient), line:248
|vpiIODecl:
\_io_decl: (done)
|vpiName:done
|vpiDirection:1
|vpiExpr:
\_logic_net: (done), line:249
|vpiIODecl:
\_io_decl: (divisor_is_zero)
|vpiName:divisor_is_zero
|vpiDirection:1
|vpiExpr:
\_logic_net: (divisor_is_zero), line:250
|vpiIODecl:
\_io_decl: (dividend)
|vpiName:dividend
|vpiDirection:2
|vpiExpr:
\_logic_net: (dividend), line:245
|vpiIODecl:
\_io_decl: (divisor)
|vpiName:divisor
|vpiDirection:2
|vpiExpr:
\_logic_net: (divisor), line:246
|vpiIODecl:
\_io_decl: (start)
|vpiName:start
|vpiDirection:2
|vpiExpr:
\_logic_net: (start), line:244
|vpiInterface:
\_interface: work@unsigned_division_interface (div), file:third_party/cores/taiga/core/div_algorithms/div_algorithm.sv, line:36
|vpiNet:
\_logic_net: (clk), line:27, parent:div_block
|vpiNet:
\_logic_net: (rst), line:28, parent:div_block
|vpiNet:
\_logic_net: (terminate), line:32, parent:div_block
|vpiName:terminate
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.terminate
|vpiNetType:36
|vpiNet:
\_logic_net: (new_PR), line:34, parent:div_block
|vpiName:new_PR
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.new_PR
|vpiNetType:36
|vpiRange:
\_range: , line:34
|vpiLeftRange:
\_ref_obj: (div.DATA_WIDTH), line:34
|vpiName:div.DATA_WIDTH
|vpiRightRange:
\_constant: , line:34
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (PR), line:35, parent:div_block
|vpiName:PR
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.PR
|vpiNetType:36
|vpiRange:
\_range: , line:35
|vpiLeftRange:
\_ref_obj: (div.DATA_WIDTH), line:35
|vpiName:div.DATA_WIDTH
|vpiRightRange:
\_constant: , line:35
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (shift_count), line:36, parent:div_block
|vpiName:shift_count
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.shift_count
|vpiNetType:36
|vpiRange:
\_range: , line:36
|vpiLeftRange:
\_operation: , line:36
|vpiOpType:11
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:36
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:36
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:36
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (negative_sub_rst), line:37, parent:div_block
|vpiName:negative_sub_rst
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.negative_sub_rst
|vpiNetType:36
|vpiNet:
\_logic_net: (div), line:29, parent:div_block
|vpiName:div
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.div
|vpiInstance:
\_module: work@div_algorithm (divider_block), file:third_party/cores/taiga/core/div_unit.sv, line:129, parent:div_unit_block
|vpiModule:
\_module: work@div_radix2_ET (div_block), file:third_party/cores/taiga/core/div_algorithms/div_algorithm.sv, line:37, parent:divider_block
|vpiDefName:work@div_radix2_ET
|vpiName:div_block
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block
|vpiPort:
\_port: (clk), line:27, parent:div_block
|vpiName:clk
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (clk), line:37
|vpiName:clk
|vpiActual:
\_logic_net: (clk), line:29, parent:divider_block
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (clk), line:27, parent:div_block
|vpiName:clk
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.clk
|vpiNetType:36
|vpiPort:
\_port: (rst), line:28, parent:div_block
|vpiName:rst
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (rst), line:37
|vpiName:rst
|vpiActual:
\_logic_net: (rst), line:30, parent:divider_block
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (rst), line:28, parent:div_block
|vpiName:rst
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.rst
|vpiNetType:36
|vpiPort:
\_port: (div), line:29, parent:div_block
|vpiName:div
|vpiDirection:5
|vpiHighConn:
\_ref_obj: (div), line:37
|vpiName:div
|vpiActual:
\_interface: work@unsigned_division_interface (div), file:third_party/cores/taiga/core/div_unit.sv, line:129
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_modport: (divider)
|vpiName:divider
|vpiIODecl:
\_io_decl: (remainder)
|vpiName:remainder
|vpiDirection:2
|vpiExpr:
\_logic_net: (remainder), line:247
|vpiName:remainder
|vpiNetType:36
|vpiRange:
\_range: , line:247
|vpiLeftRange:
\_constant: , line:247
|vpiDecompile:31
|INT:31
|vpiRightRange:
\_constant: , line:247
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (quotient)
|vpiName:quotient
|vpiDirection:2
|vpiExpr:
\_logic_net: (quotient), line:248
|vpiName:quotient
|vpiNetType:36
|vpiRange:
\_range: , line:248
|vpiLeftRange:
\_constant: , line:248
|vpiDecompile:31
|INT:31
|vpiRightRange:
\_constant: , line:248
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (done)
|vpiName:done
|vpiDirection:2
|vpiExpr:
\_logic_net: (done), line:249
|vpiName:done
|vpiNetType:36
|vpiIODecl:
\_io_decl: (divisor_is_zero)
|vpiName:divisor_is_zero
|vpiDirection:2
|vpiExpr:
\_logic_net: (divisor_is_zero), line:250
|vpiName:divisor_is_zero
|vpiNetType:36
|vpiIODecl:
\_io_decl: (dividend)
|vpiName:dividend
|vpiDirection:1
|vpiExpr:
\_logic_net: (dividend), line:245
|vpiName:dividend
|vpiNetType:36
|vpiRange:
\_range: , line:245
|vpiLeftRange:
\_constant: , line:245
|vpiDecompile:31
|INT:31
|vpiRightRange:
\_constant: , line:245
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (divisor)
|vpiName:divisor
|vpiDirection:1
|vpiExpr:
\_logic_net: (divisor), line:246
|vpiName:divisor
|vpiNetType:36
|vpiRange:
\_range: , line:246
|vpiLeftRange:
\_constant: , line:246
|vpiDecompile:31
|INT:31
|vpiRightRange:
\_constant: , line:246
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (start)
|vpiName:start
|vpiDirection:1
|vpiExpr:
\_logic_net: (start), line:244
|vpiName:start
|vpiNetType:36
|vpiInterface:
\_interface: work@unsigned_division_interface (div), file:third_party/cores/taiga/core/div_algorithms/div_algorithm.sv, line:37
|vpiDefName:work@unsigned_division_interface
|vpiName:div
|vpiModport:
\_modport: (divider)
|vpiModport:
\_modport: (requester)
|vpiName:requester
|vpiIODecl:
\_io_decl: (remainder)
|vpiName:remainder
|vpiDirection:1
|vpiExpr:
\_logic_net: (remainder), line:247
|vpiIODecl:
\_io_decl: (quotient)
|vpiName:quotient
|vpiDirection:1
|vpiExpr:
\_logic_net: (quotient), line:248
|vpiIODecl:
\_io_decl: (done)
|vpiName:done
|vpiDirection:1
|vpiExpr:
\_logic_net: (done), line:249
|vpiIODecl:
\_io_decl: (divisor_is_zero)
|vpiName:divisor_is_zero
|vpiDirection:1
|vpiExpr:
\_logic_net: (divisor_is_zero), line:250
|vpiIODecl:
\_io_decl: (dividend)
|vpiName:dividend
|vpiDirection:2
|vpiExpr:
\_logic_net: (dividend), line:245
|vpiIODecl:
\_io_decl: (divisor)
|vpiName:divisor
|vpiDirection:2
|vpiExpr:
\_logic_net: (divisor), line:246
|vpiIODecl:
\_io_decl: (start)
|vpiName:start
|vpiDirection:2
|vpiExpr:
\_logic_net: (start), line:244
|vpiInterface:
\_interface: work@unsigned_division_interface (div), file:third_party/cores/taiga/core/div_algorithms/div_algorithm.sv, line:37
|vpiNet:
\_logic_net: (clk), line:27, parent:div_block
|vpiNet:
\_logic_net: (rst), line:28, parent:div_block
|vpiNet:
\_logic_net: (terminate), line:32, parent:div_block
|vpiName:terminate
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.terminate
|vpiNetType:36
|vpiNet:
\_logic_net: (terminate_early), line:33, parent:div_block
|vpiName:terminate_early
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.terminate_early
|vpiNetType:36
|vpiNet:
\_logic_net: (new_PR), line:35, parent:div_block
|vpiName:new_PR
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.new_PR
|vpiNetType:36
|vpiRange:
\_range: , line:35
|vpiLeftRange:
\_ref_obj: (div.DATA_WIDTH), line:35
|vpiName:div.DATA_WIDTH
|vpiRightRange:
\_constant: , line:35
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (PR), line:36, parent:div_block
|vpiName:PR
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.PR
|vpiNetType:36
|vpiRange:
\_range: , line:36
|vpiLeftRange:
\_ref_obj: (div.DATA_WIDTH), line:36
|vpiName:div.DATA_WIDTH
|vpiRightRange:
\_constant: , line:36
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (shift_count), line:38, parent:div_block
|vpiName:shift_count
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.shift_count
|vpiNetType:36
|vpiRange:
\_range: , line:38
|vpiLeftRange:
\_operation: , line:38
|vpiOpType:11
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:38
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:38
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:38
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (negative_sub_rst), line:40, parent:div_block
|vpiName:negative_sub_rst
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.negative_sub_rst
|vpiNetType:36
|vpiNet:
\_logic_net: (div), line:29, parent:div_block
|vpiName:div
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.div
|vpiInstance:
\_module: work@div_algorithm (divider_block), file:third_party/cores/taiga/core/div_unit.sv, line:129, parent:div_unit_block
|vpiModule:
\_module: work@div_radix2_ET_full (div_block), file:third_party/cores/taiga/core/div_algorithms/div_algorithm.sv, line:38, parent:divider_block
|vpiDefName:work@div_radix2_ET_full
|vpiName:div_block
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block
|vpiPort:
\_port: (clk), line:27, parent:div_block
|vpiName:clk
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (clk), line:38
|vpiName:clk
|vpiActual:
\_logic_net: (clk), line:29, parent:divider_block
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (clk), line:27, parent:div_block
|vpiName:clk
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.clk
|vpiNetType:36
|vpiPort:
\_port: (rst), line:28, parent:div_block
|vpiName:rst
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (rst), line:38
|vpiName:rst
|vpiActual:
\_logic_net: (rst), line:30, parent:divider_block
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (rst), line:28, parent:div_block
|vpiName:rst
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.rst
|vpiNetType:36
|vpiPort:
\_port: (div), line:29, parent:div_block
|vpiName:div
|vpiDirection:5
|vpiHighConn:
\_ref_obj: (div), line:38
|vpiName:div
|vpiActual:
\_interface: work@unsigned_division_interface (div), file:third_party/cores/taiga/core/div_unit.sv, line:129
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_modport: (divider)
|vpiName:divider
|vpiIODecl:
\_io_decl: (remainder)
|vpiName:remainder
|vpiDirection:2
|vpiExpr:
\_logic_net: (remainder), line:247
|vpiName:remainder
|vpiNetType:36
|vpiRange:
\_range: , line:247
|vpiLeftRange:
\_constant: , line:247
|vpiDecompile:31
|INT:31
|vpiRightRange:
\_constant: , line:247
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (quotient)
|vpiName:quotient
|vpiDirection:2
|vpiExpr:
\_logic_net: (quotient), line:248
|vpiName:quotient
|vpiNetType:36
|vpiRange:
\_range: , line:248
|vpiLeftRange:
\_constant: , line:248
|vpiDecompile:31
|INT:31
|vpiRightRange:
\_constant: , line:248
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (done)
|vpiName:done
|vpiDirection:2
|vpiExpr:
\_logic_net: (done), line:249
|vpiName:done
|vpiNetType:36
|vpiIODecl:
\_io_decl: (divisor_is_zero)
|vpiName:divisor_is_zero
|vpiDirection:2
|vpiExpr:
\_logic_net: (divisor_is_zero), line:250
|vpiName:divisor_is_zero
|vpiNetType:36
|vpiIODecl:
\_io_decl: (dividend)
|vpiName:dividend
|vpiDirection:1
|vpiExpr:
\_logic_net: (dividend), line:245
|vpiName:dividend
|vpiNetType:36
|vpiRange:
\_range: , line:245
|vpiLeftRange:
\_constant: , line:245
|vpiDecompile:31
|INT:31
|vpiRightRange:
\_constant: , line:245
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (divisor)
|vpiName:divisor
|vpiDirection:1
|vpiExpr:
\_logic_net: (divisor), line:246
|vpiName:divisor
|vpiNetType:36
|vpiRange:
\_range: , line:246
|vpiLeftRange:
\_constant: , line:246
|vpiDecompile:31
|INT:31
|vpiRightRange:
\_constant: , line:246
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (start)
|vpiName:start
|vpiDirection:1
|vpiExpr:
\_logic_net: (start), line:244
|vpiName:start
|vpiNetType:36
|vpiInterface:
\_interface: work@unsigned_division_interface (div), file:third_party/cores/taiga/core/div_algorithms/div_algorithm.sv, line:38
|vpiDefName:work@unsigned_division_interface
|vpiName:div
|vpiModport:
\_modport: (divider)
|vpiModport:
\_modport: (requester)
|vpiName:requester
|vpiIODecl:
\_io_decl: (remainder)
|vpiName:remainder
|vpiDirection:1
|vpiExpr:
\_logic_net: (remainder), line:247
|vpiIODecl:
\_io_decl: (quotient)
|vpiName:quotient
|vpiDirection:1
|vpiExpr:
\_logic_net: (quotient), line:248
|vpiIODecl:
\_io_decl: (done)
|vpiName:done
|vpiDirection:1
|vpiExpr:
\_logic_net: (done), line:249
|vpiIODecl:
\_io_decl: (divisor_is_zero)
|vpiName:divisor_is_zero
|vpiDirection:1
|vpiExpr:
\_logic_net: (divisor_is_zero), line:250
|vpiIODecl:
\_io_decl: (dividend)
|vpiName:dividend
|vpiDirection:2
|vpiExpr:
\_logic_net: (dividend), line:245
|vpiIODecl:
\_io_decl: (divisor)
|vpiName:divisor
|vpiDirection:2
|vpiExpr:
\_logic_net: (divisor), line:246
|vpiIODecl:
\_io_decl: (start)
|vpiName:start
|vpiDirection:2
|vpiExpr:
\_logic_net: (start), line:244
|vpiInterface:
\_interface: work@unsigned_division_interface (div), file:third_party/cores/taiga/core/div_algorithms/div_algorithm.sv, line:38
|vpiNet:
\_logic_net: (clk), line:27, parent:div_block
|vpiNet:
\_logic_net: (rst), line:28, parent:div_block
|vpiNet:
\_logic_net: (terminate), line:32, parent:div_block
|vpiName:terminate
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.terminate
|vpiNetType:36
|vpiNet:
\_logic_net: (new_PR), line:34, parent:div_block
|vpiName:new_PR
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.new_PR
|vpiNetType:36
|vpiRange:
\_range: , line:34
|vpiLeftRange:
\_ref_obj: (div.DATA_WIDTH), line:34
|vpiName:div.DATA_WIDTH
|vpiRightRange:
\_constant: , line:34
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (PR), line:35, parent:div_block
|vpiName:PR
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.PR
|vpiNetType:36
|vpiRange:
\_range: , line:35
|vpiLeftRange:
\_ref_obj: (div.DATA_WIDTH), line:35
|vpiName:div.DATA_WIDTH
|vpiRightRange:
\_constant: , line:35
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (shift_count), line:37, parent:div_block
|vpiName:shift_count
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.shift_count
|vpiNetType:36
|vpiRange:
\_range: , line:37
|vpiLeftRange:
\_operation: , line:37
|vpiOpType:11
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:37
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:37
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:37
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (negative_sub_rst), line:39, parent:div_block
|vpiName:negative_sub_rst
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.negative_sub_rst
|vpiNetType:36
|vpiNet:
\_logic_net: (AR_r), line:40, parent:div_block
|vpiName:AR_r
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.AR_r
|vpiNetType:36
|vpiRange:
\_range: , line:40
|vpiLeftRange:
\_operation: , line:40
|vpiOpType:11
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:40
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:40
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:40
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (Q_temp), line:41, parent:div_block
|vpiName:Q_temp
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.Q_temp
|vpiNetType:36
|vpiRange:
\_range: , line:41
|vpiLeftRange:
\_operation: , line:41
|vpiOpType:11
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:41
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:41
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:41
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (shift_num_R), line:42, parent:div_block
|vpiName:shift_num_R
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.shift_num_R
|vpiNetType:36
|vpiRange:
\_range: , line:42
|vpiLeftRange:
\_constant: , line:42
|vpiConstType:7
|vpiDecompile:5
|vpiSize:32
|INT:5
|vpiRightRange:
\_constant: , line:42
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (shift_num_Q), line:43, parent:div_block
|vpiName:shift_num_Q
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.shift_num_Q
|vpiNetType:36
|vpiRange:
\_range: , line:43
|vpiLeftRange:
\_constant: , line:43
|vpiConstType:7
|vpiDecompile:5
|vpiSize:32
|INT:5
|vpiRightRange:
\_constant: , line:43
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (combined), line:44, parent:div_block
|vpiName:combined
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.combined
|vpiNetType:36
|vpiRange:
\_range: , line:44
|vpiLeftRange:
\_operation: , line:44
|vpiOpType:25
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:44
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:44
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiRightRange:
\_constant: , line:44
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (combined_r), line:45, parent:div_block
|vpiName:combined_r
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.combined_r
|vpiNetType:36
|vpiRange:
\_range: , line:45
|vpiLeftRange:
\_operation: , line:45
|vpiOpType:25
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:45
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:45
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiRightRange:
\_constant: , line:45
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (terminate_early), line:46, parent:div_block
|vpiName:terminate_early
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.terminate_early
|vpiNetType:36
|vpiNet:
\_logic_net: (terminate_early_r), line:47, parent:div_block
|vpiName:terminate_early_r
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.terminate_early_r
|vpiNetType:36
|vpiNet:
\_logic_net: (div), line:29, parent:div_block
|vpiName:div
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.div
|vpiInstance:
\_module: work@div_algorithm (divider_block), file:third_party/cores/taiga/core/div_unit.sv, line:129, parent:div_unit_block
|vpiModule:
\_module: work@div_radix4 (div_block), file:third_party/cores/taiga/core/div_algorithms/div_algorithm.sv, line:39, parent:divider_block
|vpiDefName:work@div_radix4
|vpiName:div_block
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block
|vpiPort:
\_port: (clk), line:27, parent:div_block
|vpiName:clk
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (clk), line:39
|vpiName:clk
|vpiActual:
\_logic_net: (clk), line:29, parent:divider_block
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (clk), line:27, parent:div_block
|vpiName:clk
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.clk
|vpiNetType:36
|vpiPort:
\_port: (rst), line:28, parent:div_block
|vpiName:rst
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (rst), line:39
|vpiName:rst
|vpiActual:
\_logic_net: (rst), line:30, parent:divider_block
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (rst), line:28, parent:div_block
|vpiName:rst
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.rst
|vpiNetType:36
|vpiPort:
\_port: (div), line:29, parent:div_block
|vpiName:div
|vpiDirection:5
|vpiHighConn:
\_ref_obj: (div), line:39
|vpiName:div
|vpiActual:
\_interface: work@unsigned_division_interface (div), file:third_party/cores/taiga/core/div_unit.sv, line:129
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_modport: (divider)
|vpiName:divider
|vpiIODecl:
\_io_decl: (remainder)
|vpiName:remainder
|vpiDirection:2
|vpiExpr:
\_logic_net: (remainder), line:247
|vpiName:remainder
|vpiNetType:36
|vpiRange:
\_range: , line:247
|vpiLeftRange:
\_constant: , line:247
|vpiDecompile:31
|INT:31
|vpiRightRange:
\_constant: , line:247
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (quotient)
|vpiName:quotient
|vpiDirection:2
|vpiExpr:
\_logic_net: (quotient), line:248
|vpiName:quotient
|vpiNetType:36
|vpiRange:
\_range: , line:248
|vpiLeftRange:
\_constant: , line:248
|vpiDecompile:31
|INT:31
|vpiRightRange:
\_constant: , line:248
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (done)
|vpiName:done
|vpiDirection:2
|vpiExpr:
\_logic_net: (done), line:249
|vpiName:done
|vpiNetType:36
|vpiIODecl:
\_io_decl: (divisor_is_zero)
|vpiName:divisor_is_zero
|vpiDirection:2
|vpiExpr:
\_logic_net: (divisor_is_zero), line:250
|vpiName:divisor_is_zero
|vpiNetType:36
|vpiIODecl:
\_io_decl: (dividend)
|vpiName:dividend
|vpiDirection:1
|vpiExpr:
\_logic_net: (dividend), line:245
|vpiName:dividend
|vpiNetType:36
|vpiRange:
\_range: , line:245
|vpiLeftRange:
\_constant: , line:245
|vpiDecompile:31
|INT:31
|vpiRightRange:
\_constant: , line:245
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (divisor)
|vpiName:divisor
|vpiDirection:1
|vpiExpr:
\_logic_net: (divisor), line:246
|vpiName:divisor
|vpiNetType:36
|vpiRange:
\_range: , line:246
|vpiLeftRange:
\_constant: , line:246
|vpiDecompile:31
|INT:31
|vpiRightRange:
\_constant: , line:246
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (start)
|vpiName:start
|vpiDirection:1
|vpiExpr:
\_logic_net: (start), line:244
|vpiName:start
|vpiNetType:36
|vpiInterface:
\_interface: work@unsigned_division_interface (div), file:third_party/cores/taiga/core/div_algorithms/div_algorithm.sv, line:39
|vpiDefName:work@unsigned_division_interface
|vpiName:div
|vpiModport:
\_modport: (divider)
|vpiModport:
\_modport: (requester)
|vpiName:requester
|vpiIODecl:
\_io_decl: (remainder)
|vpiName:remainder
|vpiDirection:1
|vpiExpr:
\_logic_net: (remainder), line:247
|vpiIODecl:
\_io_decl: (quotient)
|vpiName:quotient
|vpiDirection:1
|vpiExpr:
\_logic_net: (quotient), line:248
|vpiIODecl:
\_io_decl: (done)
|vpiName:done
|vpiDirection:1
|vpiExpr:
\_logic_net: (done), line:249
|vpiIODecl:
\_io_decl: (divisor_is_zero)
|vpiName:divisor_is_zero
|vpiDirection:1
|vpiExpr:
\_logic_net: (divisor_is_zero), line:250
|vpiIODecl:
\_io_decl: (dividend)
|vpiName:dividend
|vpiDirection:2
|vpiExpr:
\_logic_net: (dividend), line:245
|vpiIODecl:
\_io_decl: (divisor)
|vpiName:divisor
|vpiDirection:2
|vpiExpr:
\_logic_net: (divisor), line:246
|vpiIODecl:
\_io_decl: (start)
|vpiName:start
|vpiDirection:2
|vpiExpr:
\_logic_net: (start), line:244
|vpiInterface:
\_interface: work@unsigned_division_interface (div), file:third_party/cores/taiga/core/div_algorithms/div_algorithm.sv, line:39
|vpiNet:
\_logic_net: (clk), line:27, parent:div_block
|vpiNet:
\_logic_net: (rst), line:28, parent:div_block
|vpiNet:
\_logic_net: (terminate), line:32, parent:div_block
|vpiName:terminate
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.terminate
|vpiNetType:36
|vpiNet:
\_logic_net: (shift_count), line:33, parent:div_block
|vpiName:shift_count
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.shift_count
|vpiNetType:36
|vpiRange:
\_range: , line:33
|vpiLeftRange:
\_operation: , line:33
|vpiOpType:11
|vpiOperand:
\_operation: , line:33
|vpiOpType:12
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:33
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:33
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiOperand:
\_constant: , line:33
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:33
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (PR), line:35, parent:div_block
|vpiName:PR
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.PR
|vpiNetType:36
|vpiRange:
\_range: , line:35
|vpiLeftRange:
\_operation: , line:35
|vpiOpType:24
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:35
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:35
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:35
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (new_PR_sign), line:36, parent:div_block
|vpiName:new_PR_sign
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.new_PR_sign
|vpiNetType:36
|vpiRange:
\_range: , line:36
|vpiLeftRange:
\_constant: , line:36
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiRightRange:
\_constant: , line:36
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (new_PR_1), line:37, parent:div_block
|vpiName:new_PR_1
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.new_PR_1
|vpiNetType:36
|vpiRange:
\_range: , line:37
|vpiLeftRange:
\_operation: , line:37
|vpiOpType:24
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:37
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:37
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiRightRange:
\_constant: , line:37
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (new_PR_2), line:38, parent:div_block
|vpiName:new_PR_2
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.new_PR_2
|vpiNetType:36
|vpiRange:
\_range: , line:38
|vpiLeftRange:
\_operation: , line:38
|vpiOpType:24
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:38
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:38
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiRightRange:
\_constant: , line:38
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (new_PR_3), line:39, parent:div_block
|vpiName:new_PR_3
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.new_PR_3
|vpiNetType:36
|vpiRange:
\_range: , line:39
|vpiLeftRange:
\_operation: , line:39
|vpiOpType:24
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:39
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:39
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiRightRange:
\_constant: , line:39
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (B_1), line:40, parent:div_block
|vpiName:B_1
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.B_1
|vpiNetType:36
|vpiRange:
\_range: , line:40
|vpiLeftRange:
\_operation: , line:40
|vpiOpType:24
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:40
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:40
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:40
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (B_2), line:41, parent:div_block
|vpiName:B_2
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.B_2
|vpiNetType:36
|vpiRange:
\_range: , line:41
|vpiLeftRange:
\_operation: , line:41
|vpiOpType:24
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:41
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:41
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:41
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (B_3), line:42, parent:div_block
|vpiName:B_3
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.B_3
|vpiNetType:36
|vpiRange:
\_range: , line:42
|vpiLeftRange:
\_operation: , line:42
|vpiOpType:24
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:42
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:42
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:42
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (div), line:29, parent:div_block
|vpiName:div
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.div
|vpiInstance:
\_module: work@div_algorithm (divider_block), file:third_party/cores/taiga/core/div_unit.sv, line:129, parent:div_unit_block
|vpiModule:
\_module: work@div_radix4_ET (div_block), file:third_party/cores/taiga/core/div_algorithms/div_algorithm.sv, line:40, parent:divider_block
|vpiDefName:work@div_radix4_ET
|vpiName:div_block
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block
|vpiPort:
\_port: (clk), line:27, parent:div_block
|vpiName:clk
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (clk), line:40
|vpiName:clk
|vpiActual:
\_logic_net: (clk), line:29, parent:divider_block
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (clk), line:27, parent:div_block
|vpiName:clk
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.clk
|vpiNetType:36
|vpiPort:
\_port: (rst), line:28, parent:div_block
|vpiName:rst
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (rst), line:40
|vpiName:rst
|vpiActual:
\_logic_net: (rst), line:30, parent:divider_block
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (rst), line:28, parent:div_block
|vpiName:rst
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.rst
|vpiNetType:36
|vpiPort:
\_port: (div), line:29, parent:div_block
|vpiName:div
|vpiDirection:5
|vpiHighConn:
\_ref_obj: (div), line:40
|vpiName:div
|vpiActual:
\_interface: work@unsigned_division_interface (div), file:third_party/cores/taiga/core/div_unit.sv, line:129
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_modport: (divider)
|vpiName:divider
|vpiIODecl:
\_io_decl: (remainder)
|vpiName:remainder
|vpiDirection:2
|vpiExpr:
\_logic_net: (remainder), line:247
|vpiName:remainder
|vpiNetType:36
|vpiRange:
\_range: , line:247
|vpiLeftRange:
\_constant: , line:247
|vpiDecompile:31
|INT:31
|vpiRightRange:
\_constant: , line:247
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (quotient)
|vpiName:quotient
|vpiDirection:2
|vpiExpr:
\_logic_net: (quotient), line:248
|vpiName:quotient
|vpiNetType:36
|vpiRange:
\_range: , line:248
|vpiLeftRange:
\_constant: , line:248
|vpiDecompile:31
|INT:31
|vpiRightRange:
\_constant: , line:248
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (done)
|vpiName:done
|vpiDirection:2
|vpiExpr:
\_logic_net: (done), line:249
|vpiName:done
|vpiNetType:36
|vpiIODecl:
\_io_decl: (divisor_is_zero)
|vpiName:divisor_is_zero
|vpiDirection:2
|vpiExpr:
\_logic_net: (divisor_is_zero), line:250
|vpiName:divisor_is_zero
|vpiNetType:36
|vpiIODecl:
\_io_decl: (dividend)
|vpiName:dividend
|vpiDirection:1
|vpiExpr:
\_logic_net: (dividend), line:245
|vpiName:dividend
|vpiNetType:36
|vpiRange:
\_range: , line:245
|vpiLeftRange:
\_constant: , line:245
|vpiDecompile:31
|INT:31
|vpiRightRange:
\_constant: , line:245
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (divisor)
|vpiName:divisor
|vpiDirection:1
|vpiExpr:
\_logic_net: (divisor), line:246
|vpiName:divisor
|vpiNetType:36
|vpiRange:
\_range: , line:246
|vpiLeftRange:
\_constant: , line:246
|vpiDecompile:31
|INT:31
|vpiRightRange:
\_constant: , line:246
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (start)
|vpiName:start
|vpiDirection:1
|vpiExpr:
\_logic_net: (start), line:244
|vpiName:start
|vpiNetType:36
|vpiInterface:
\_interface: work@unsigned_division_interface (div), file:third_party/cores/taiga/core/div_algorithms/div_algorithm.sv, line:40
|vpiDefName:work@unsigned_division_interface
|vpiName:div
|vpiModport:
\_modport: (divider)
|vpiModport:
\_modport: (requester)
|vpiName:requester
|vpiIODecl:
\_io_decl: (remainder)
|vpiName:remainder
|vpiDirection:1
|vpiExpr:
\_logic_net: (remainder), line:247
|vpiIODecl:
\_io_decl: (quotient)
|vpiName:quotient
|vpiDirection:1
|vpiExpr:
\_logic_net: (quotient), line:248
|vpiIODecl:
\_io_decl: (done)
|vpiName:done
|vpiDirection:1
|vpiExpr:
\_logic_net: (done), line:249
|vpiIODecl:
\_io_decl: (divisor_is_zero)
|vpiName:divisor_is_zero
|vpiDirection:1
|vpiExpr:
\_logic_net: (divisor_is_zero), line:250
|vpiIODecl:
\_io_decl: (dividend)
|vpiName:dividend
|vpiDirection:2
|vpiExpr:
\_logic_net: (dividend), line:245
|vpiIODecl:
\_io_decl: (divisor)
|vpiName:divisor
|vpiDirection:2
|vpiExpr:
\_logic_net: (divisor), line:246
|vpiIODecl:
\_io_decl: (start)
|vpiName:start
|vpiDirection:2
|vpiExpr:
\_logic_net: (start), line:244
|vpiInterface:
\_interface: work@unsigned_division_interface (div), file:third_party/cores/taiga/core/div_algorithms/div_algorithm.sv, line:40
|vpiNet:
\_logic_net: (clk), line:27, parent:div_block
|vpiNet:
\_logic_net: (rst), line:28, parent:div_block
|vpiNet:
\_logic_net: (terminate), line:32, parent:div_block
|vpiName:terminate
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.terminate
|vpiNetType:36
|vpiNet:
\_logic_net: (terminate_early), line:33, parent:div_block
|vpiName:terminate_early
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.terminate_early
|vpiNetType:36
|vpiNet:
\_logic_net: (shift_count), line:34, parent:div_block
|vpiName:shift_count
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.shift_count
|vpiNetType:36
|vpiRange:
\_range: , line:34
|vpiLeftRange:
\_operation: , line:34
|vpiOpType:11
|vpiOperand:
\_operation: , line:34
|vpiOpType:12
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:34
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:34
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiOperand:
\_constant: , line:34
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:34
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (PR), line:36, parent:div_block
|vpiName:PR
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.PR
|vpiNetType:36
|vpiRange:
\_range: , line:36
|vpiLeftRange:
\_operation: , line:36
|vpiOpType:24
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:36
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:36
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:36
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (new_PR_sign), line:37, parent:div_block
|vpiName:new_PR_sign
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.new_PR_sign
|vpiNetType:36
|vpiRange:
\_range: , line:37
|vpiLeftRange:
\_constant: , line:37
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiRightRange:
\_constant: , line:37
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (new_PR_1), line:38, parent:div_block
|vpiName:new_PR_1
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.new_PR_1
|vpiNetType:36
|vpiRange:
\_range: , line:38
|vpiLeftRange:
\_operation: , line:38
|vpiOpType:24
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:38
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:38
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiRightRange:
\_constant: , line:38
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (new_PR_2), line:39, parent:div_block
|vpiName:new_PR_2
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.new_PR_2
|vpiNetType:36
|vpiRange:
\_range: , line:39
|vpiLeftRange:
\_operation: , line:39
|vpiOpType:24
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:39
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:39
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiRightRange:
\_constant: , line:39
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (new_PR_3), line:40, parent:div_block
|vpiName:new_PR_3
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.new_PR_3
|vpiNetType:36
|vpiRange:
\_range: , line:40
|vpiLeftRange:
\_operation: , line:40
|vpiOpType:24
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:40
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:40
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiRightRange:
\_constant: , line:40
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (B_1), line:41, parent:div_block
|vpiName:B_1
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.B_1
|vpiNetType:36
|vpiRange:
\_range: , line:41
|vpiLeftRange:
\_operation: , line:41
|vpiOpType:24
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:41
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:41
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:41
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (B_2), line:42, parent:div_block
|vpiName:B_2
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.B_2
|vpiNetType:36
|vpiRange:
\_range: , line:42
|vpiLeftRange:
\_operation: , line:42
|vpiOpType:24
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:42
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:42
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:42
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (B_3), line:43, parent:div_block
|vpiName:B_3
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.B_3
|vpiNetType:36
|vpiRange:
\_range: , line:43
|vpiLeftRange:
\_operation: , line:43
|vpiOpType:24
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:43
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:43
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:43
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (div), line:29, parent:div_block
|vpiName:div
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.div
|vpiInstance:
\_module: work@div_algorithm (divider_block), file:third_party/cores/taiga/core/div_unit.sv, line:129, parent:div_unit_block
|vpiModule:
\_module: work@div_radix4_ET_full (div_block), file:third_party/cores/taiga/core/div_algorithms/div_algorithm.sv, line:41, parent:divider_block
|vpiDefName:work@div_radix4_ET_full
|vpiName:div_block
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block
|vpiPort:
\_port: (clk), line:27, parent:div_block
|vpiName:clk
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (clk), line:41
|vpiName:clk
|vpiActual:
\_logic_net: (clk), line:29, parent:divider_block
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (clk), line:27, parent:div_block
|vpiName:clk
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.clk
|vpiNetType:36
|vpiPort:
\_port: (rst), line:28, parent:div_block
|vpiName:rst
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (rst), line:41
|vpiName:rst
|vpiActual:
\_logic_net: (rst), line:30, parent:divider_block
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (rst), line:28, parent:div_block
|vpiName:rst
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.rst
|vpiNetType:36
|vpiPort:
\_port: (div), line:29, parent:div_block
|vpiName:div
|vpiDirection:5
|vpiHighConn:
\_ref_obj: (div), line:41
|vpiName:div
|vpiActual:
\_interface: work@unsigned_division_interface (div), file:third_party/cores/taiga/core/div_unit.sv, line:129
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_modport: (divider)
|vpiName:divider
|vpiIODecl:
\_io_decl: (remainder)
|vpiName:remainder
|vpiDirection:2
|vpiExpr:
\_logic_net: (remainder), line:247
|vpiName:remainder
|vpiNetType:36
|vpiRange:
\_range: , line:247
|vpiLeftRange:
\_constant: , line:247
|vpiDecompile:31
|INT:31
|vpiRightRange:
\_constant: , line:247
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (quotient)
|vpiName:quotient
|vpiDirection:2
|vpiExpr:
\_logic_net: (quotient), line:248
|vpiName:quotient
|vpiNetType:36
|vpiRange:
\_range: , line:248
|vpiLeftRange:
\_constant: , line:248
|vpiDecompile:31
|INT:31
|vpiRightRange:
\_constant: , line:248
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (done)
|vpiName:done
|vpiDirection:2
|vpiExpr:
\_logic_net: (done), line:249
|vpiName:done
|vpiNetType:36
|vpiIODecl:
\_io_decl: (divisor_is_zero)
|vpiName:divisor_is_zero
|vpiDirection:2
|vpiExpr:
\_logic_net: (divisor_is_zero), line:250
|vpiName:divisor_is_zero
|vpiNetType:36
|vpiIODecl:
\_io_decl: (dividend)
|vpiName:dividend
|vpiDirection:1
|vpiExpr:
\_logic_net: (dividend), line:245
|vpiName:dividend
|vpiNetType:36
|vpiRange:
\_range: , line:245
|vpiLeftRange:
\_constant: , line:245
|vpiDecompile:31
|INT:31
|vpiRightRange:
\_constant: , line:245
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (divisor)
|vpiName:divisor
|vpiDirection:1
|vpiExpr:
\_logic_net: (divisor), line:246
|vpiName:divisor
|vpiNetType:36
|vpiRange:
\_range: , line:246
|vpiLeftRange:
\_constant: , line:246
|vpiDecompile:31
|INT:31
|vpiRightRange:
\_constant: , line:246
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (start)
|vpiName:start
|vpiDirection:1
|vpiExpr:
\_logic_net: (start), line:244
|vpiName:start
|vpiNetType:36
|vpiInterface:
\_interface: work@unsigned_division_interface (div), file:third_party/cores/taiga/core/div_algorithms/div_algorithm.sv, line:41
|vpiDefName:work@unsigned_division_interface
|vpiName:div
|vpiModport:
\_modport: (divider)
|vpiModport:
\_modport: (requester)
|vpiName:requester
|vpiIODecl:
\_io_decl: (remainder)
|vpiName:remainder
|vpiDirection:1
|vpiExpr:
\_logic_net: (remainder), line:247
|vpiIODecl:
\_io_decl: (quotient)
|vpiName:quotient
|vpiDirection:1
|vpiExpr:
\_logic_net: (quotient), line:248
|vpiIODecl:
\_io_decl: (done)
|vpiName:done
|vpiDirection:1
|vpiExpr:
\_logic_net: (done), line:249
|vpiIODecl:
\_io_decl: (divisor_is_zero)
|vpiName:divisor_is_zero
|vpiDirection:1
|vpiExpr:
\_logic_net: (divisor_is_zero), line:250
|vpiIODecl:
\_io_decl: (dividend)
|vpiName:dividend
|vpiDirection:2
|vpiExpr:
\_logic_net: (dividend), line:245
|vpiIODecl:
\_io_decl: (divisor)
|vpiName:divisor
|vpiDirection:2
|vpiExpr:
\_logic_net: (divisor), line:246
|vpiIODecl:
\_io_decl: (start)
|vpiName:start
|vpiDirection:2
|vpiExpr:
\_logic_net: (start), line:244
|vpiInterface:
\_interface: work@unsigned_division_interface (div), file:third_party/cores/taiga/core/div_algorithms/div_algorithm.sv, line:41
|vpiNet:
\_logic_net: (clk), line:27, parent:div_block
|vpiNet:
\_logic_net: (rst), line:28, parent:div_block
|vpiNet:
\_logic_net: (terminate), line:32, parent:div_block
|vpiName:terminate
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.terminate
|vpiNetType:36
|vpiNet:
\_logic_net: (shift_count), line:33, parent:div_block
|vpiName:shift_count
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.shift_count
|vpiNetType:36
|vpiRange:
\_range: , line:33
|vpiLeftRange:
\_operation: , line:33
|vpiOpType:11
|vpiOperand:
\_operation: , line:33
|vpiOpType:12
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:33
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:33
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiOperand:
\_constant: , line:33
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:33
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (PR), line:35, parent:div_block
|vpiName:PR
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.PR
|vpiNetType:36
|vpiRange:
\_range: , line:35
|vpiLeftRange:
\_operation: , line:35
|vpiOpType:24
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:35
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:35
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:35
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (new_PR_sign), line:36, parent:div_block
|vpiName:new_PR_sign
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.new_PR_sign
|vpiNetType:36
|vpiRange:
\_range: , line:36
|vpiLeftRange:
\_constant: , line:36
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiRightRange:
\_constant: , line:36
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (new_PR_1), line:37, parent:div_block
|vpiName:new_PR_1
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.new_PR_1
|vpiNetType:36
|vpiRange:
\_range: , line:37
|vpiLeftRange:
\_operation: , line:37
|vpiOpType:24
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:37
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:37
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiRightRange:
\_constant: , line:37
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (new_PR_2), line:38, parent:div_block
|vpiName:new_PR_2
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.new_PR_2
|vpiNetType:36
|vpiRange:
\_range: , line:38
|vpiLeftRange:
\_operation: , line:38
|vpiOpType:24
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:38
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:38
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiRightRange:
\_constant: , line:38
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (new_PR_3), line:39, parent:div_block
|vpiName:new_PR_3
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.new_PR_3
|vpiNetType:36
|vpiRange:
\_range: , line:39
|vpiLeftRange:
\_operation: , line:39
|vpiOpType:24
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:39
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:39
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiRightRange:
\_constant: , line:39
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (B_1), line:40, parent:div_block
|vpiName:B_1
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.B_1
|vpiNetType:36
|vpiRange:
\_range: , line:40
|vpiLeftRange:
\_operation: , line:40
|vpiOpType:24
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:40
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:40
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:40
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (B_2), line:41, parent:div_block
|vpiName:B_2
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.B_2
|vpiNetType:36
|vpiRange:
\_range: , line:41
|vpiLeftRange:
\_operation: , line:41
|vpiOpType:24
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:41
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:41
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:41
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (B_3), line:42, parent:div_block
|vpiName:B_3
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.B_3
|vpiNetType:36
|vpiRange:
\_range: , line:42
|vpiLeftRange:
\_operation: , line:42
|vpiOpType:24
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:42
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:42
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:42
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (B_r), line:44, parent:div_block
|vpiName:B_r
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.B_r
|vpiNetType:36
|vpiRange:
\_range: , line:44
|vpiLeftRange:
\_operation: , line:44
|vpiOpType:11
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:44
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:44
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:44
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (AR_r), line:45, parent:div_block
|vpiName:AR_r
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.AR_r
|vpiNetType:36
|vpiRange:
\_range: , line:45
|vpiLeftRange:
\_operation: , line:45
|vpiOpType:11
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:45
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:45
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:45
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (Q_temp), line:46, parent:div_block
|vpiName:Q_temp
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.Q_temp
|vpiNetType:36
|vpiRange:
\_range: , line:46
|vpiLeftRange:
\_operation: , line:46
|vpiOpType:11
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:46
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:46
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:46
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (shift_num_R), line:47, parent:div_block
|vpiName:shift_num_R
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.shift_num_R
|vpiNetType:36
|vpiRange:
\_range: , line:47
|vpiLeftRange:
\_constant: , line:47
|vpiConstType:7
|vpiDecompile:5
|vpiSize:32
|INT:5
|vpiRightRange:
\_constant: , line:47
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (shift_num_Q), line:48, parent:div_block
|vpiName:shift_num_Q
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.shift_num_Q
|vpiNetType:36
|vpiRange:
\_range: , line:48
|vpiLeftRange:
\_constant: , line:48
|vpiConstType:7
|vpiDecompile:5
|vpiSize:32
|INT:5
|vpiRightRange:
\_constant: , line:48
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (combined), line:49, parent:div_block
|vpiName:combined
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.combined
|vpiNetType:36
|vpiRange:
\_range: , line:49
|vpiLeftRange:
\_operation: , line:49
|vpiOpType:25
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:49
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:49
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiRightRange:
\_constant: , line:49
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (terminate_early), line:50, parent:div_block
|vpiName:terminate_early
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.terminate_early
|vpiNetType:36
|vpiNet:
\_logic_net: (div), line:29, parent:div_block
|vpiName:div
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.div
|vpiInstance:
\_module: work@div_algorithm (divider_block), file:third_party/cores/taiga/core/div_unit.sv, line:129, parent:div_unit_block
|vpiModule:
\_module: work@div_radix8 (div_block), file:third_party/cores/taiga/core/div_algorithms/div_algorithm.sv, line:42, parent:divider_block
|vpiDefName:work@div_radix8
|vpiName:div_block
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block
|vpiPort:
\_port: (clk), line:27, parent:div_block
|vpiName:clk
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (clk), line:42
|vpiName:clk
|vpiActual:
\_logic_net: (clk), line:29, parent:divider_block
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (clk), line:27, parent:div_block
|vpiName:clk
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.clk
|vpiNetType:36
|vpiPort:
\_port: (rst), line:28, parent:div_block
|vpiName:rst
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (rst), line:42
|vpiName:rst
|vpiActual:
\_logic_net: (rst), line:30, parent:divider_block
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (rst), line:28, parent:div_block
|vpiName:rst
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.rst
|vpiNetType:36
|vpiPort:
\_port: (div), line:29, parent:div_block
|vpiName:div
|vpiDirection:5
|vpiHighConn:
\_ref_obj: (div), line:42
|vpiName:div
|vpiActual:
\_interface: work@unsigned_division_interface (div), file:third_party/cores/taiga/core/div_unit.sv, line:129
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_modport: (divider)
|vpiName:divider
|vpiIODecl:
\_io_decl: (remainder)
|vpiName:remainder
|vpiDirection:2
|vpiExpr:
\_logic_net: (remainder), line:247
|vpiName:remainder
|vpiNetType:36
|vpiRange:
\_range: , line:247
|vpiLeftRange:
\_constant: , line:247
|vpiDecompile:31
|INT:31
|vpiRightRange:
\_constant: , line:247
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (quotient)
|vpiName:quotient
|vpiDirection:2
|vpiExpr:
\_logic_net: (quotient), line:248
|vpiName:quotient
|vpiNetType:36
|vpiRange:
\_range: , line:248
|vpiLeftRange:
\_constant: , line:248
|vpiDecompile:31
|INT:31
|vpiRightRange:
\_constant: , line:248
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (done)
|vpiName:done
|vpiDirection:2
|vpiExpr:
\_logic_net: (done), line:249
|vpiName:done
|vpiNetType:36
|vpiIODecl:
\_io_decl: (divisor_is_zero)
|vpiName:divisor_is_zero
|vpiDirection:2
|vpiExpr:
\_logic_net: (divisor_is_zero), line:250
|vpiName:divisor_is_zero
|vpiNetType:36
|vpiIODecl:
\_io_decl: (dividend)
|vpiName:dividend
|vpiDirection:1
|vpiExpr:
\_logic_net: (dividend), line:245
|vpiName:dividend
|vpiNetType:36
|vpiRange:
\_range: , line:245
|vpiLeftRange:
\_constant: , line:245
|vpiDecompile:31
|INT:31
|vpiRightRange:
\_constant: , line:245
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (divisor)
|vpiName:divisor
|vpiDirection:1
|vpiExpr:
\_logic_net: (divisor), line:246
|vpiName:divisor
|vpiNetType:36
|vpiRange:
\_range: , line:246
|vpiLeftRange:
\_constant: , line:246
|vpiDecompile:31
|INT:31
|vpiRightRange:
\_constant: , line:246
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (start)
|vpiName:start
|vpiDirection:1
|vpiExpr:
\_logic_net: (start), line:244
|vpiName:start
|vpiNetType:36
|vpiInterface:
\_interface: work@unsigned_division_interface (div), file:third_party/cores/taiga/core/div_algorithms/div_algorithm.sv, line:42
|vpiDefName:work@unsigned_division_interface
|vpiName:div
|vpiModport:
\_modport: (divider)
|vpiModport:
\_modport: (requester)
|vpiName:requester
|vpiIODecl:
\_io_decl: (remainder)
|vpiName:remainder
|vpiDirection:1
|vpiExpr:
\_logic_net: (remainder), line:247
|vpiIODecl:
\_io_decl: (quotient)
|vpiName:quotient
|vpiDirection:1
|vpiExpr:
\_logic_net: (quotient), line:248
|vpiIODecl:
\_io_decl: (done)
|vpiName:done
|vpiDirection:1
|vpiExpr:
\_logic_net: (done), line:249
|vpiIODecl:
\_io_decl: (divisor_is_zero)
|vpiName:divisor_is_zero
|vpiDirection:1
|vpiExpr:
\_logic_net: (divisor_is_zero), line:250
|vpiIODecl:
\_io_decl: (dividend)
|vpiName:dividend
|vpiDirection:2
|vpiExpr:
\_logic_net: (dividend), line:245
|vpiIODecl:
\_io_decl: (divisor)
|vpiName:divisor
|vpiDirection:2
|vpiExpr:
\_logic_net: (divisor), line:246
|vpiIODecl:
\_io_decl: (start)
|vpiName:start
|vpiDirection:2
|vpiExpr:
\_logic_net: (start), line:244
|vpiInterface:
\_interface: work@unsigned_division_interface (div), file:third_party/cores/taiga/core/div_algorithms/div_algorithm.sv, line:42
|vpiNet:
\_logic_net: (clk), line:27, parent:div_block
|vpiNet:
\_logic_net: (rst), line:28, parent:div_block
|vpiNet:
\_logic_net: (terminate), line:32, parent:div_block
|vpiName:terminate
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.terminate
|vpiNetType:36
|vpiNet:
\_logic_net: (shift_count), line:33, parent:div_block
|vpiName:shift_count
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.shift_count
|vpiNetType:36
|vpiRange:
\_range: , line:33
|vpiLeftRange:
\_constant: , line:33
|vpiConstType:7
|vpiDecompile:10
|vpiSize:32
|INT:10
|vpiRightRange:
\_constant: , line:33
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (PR), line:35, parent:div_block
|vpiName:PR
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.PR
|vpiNetType:36
|vpiRange:
\_range: , line:35
|vpiLeftRange:
\_operation: , line:35
|vpiOpType:24
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:35
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:35
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiRightRange:
\_constant: , line:35
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (Q_33), line:36, parent:div_block
|vpiName:Q_33
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.Q_33
|vpiNetType:36
|vpiRange:
\_range: , line:36
|vpiLeftRange:
\_ref_obj: (div.DATA_WIDTH), line:36
|vpiName:div.DATA_WIDTH
|vpiRightRange:
\_constant: , line:36
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (new_PR_sign), line:37, parent:div_block
|vpiName:new_PR_sign
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.new_PR_sign
|vpiNetType:36
|vpiRange:
\_range: , line:37
|vpiLeftRange:
\_constant: , line:37
|vpiConstType:7
|vpiDecompile:6
|vpiSize:32
|INT:6
|vpiRightRange:
\_constant: , line:37
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (new_PR_1), line:39, parent:div_block
|vpiName:new_PR_1
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.new_PR_1
|vpiNetType:36
|vpiRange:
\_range: , line:39
|vpiLeftRange:
\_operation: , line:39
|vpiOpType:24
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:39
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:39
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiRightRange:
\_constant: , line:39
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (new_PR_2), line:40, parent:div_block
|vpiName:new_PR_2
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.new_PR_2
|vpiNetType:36
|vpiRange:
\_range: , line:40
|vpiLeftRange:
\_operation: , line:40
|vpiOpType:24
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:40
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:40
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiRightRange:
\_constant: , line:40
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (new_PR_3), line:41, parent:div_block
|vpiName:new_PR_3
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.new_PR_3
|vpiNetType:36
|vpiRange:
\_range: , line:41
|vpiLeftRange:
\_operation: , line:41
|vpiOpType:24
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:41
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:41
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiRightRange:
\_constant: , line:41
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (new_PR_4), line:42, parent:div_block
|vpiName:new_PR_4
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.new_PR_4
|vpiNetType:36
|vpiRange:
\_range: , line:42
|vpiLeftRange:
\_operation: , line:42
|vpiOpType:24
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:42
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:42
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiRightRange:
\_constant: , line:42
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (new_PR_5), line:43, parent:div_block
|vpiName:new_PR_5
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.new_PR_5
|vpiNetType:36
|vpiRange:
\_range: , line:43
|vpiLeftRange:
\_operation: , line:43
|vpiOpType:24
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:43
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:43
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiRightRange:
\_constant: , line:43
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (new_PR_6), line:44, parent:div_block
|vpiName:new_PR_6
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.new_PR_6
|vpiNetType:36
|vpiRange:
\_range: , line:44
|vpiLeftRange:
\_operation: , line:44
|vpiOpType:24
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:44
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:44
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiRightRange:
\_constant: , line:44
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (new_PR_7), line:45, parent:div_block
|vpiName:new_PR_7
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.new_PR_7
|vpiNetType:36
|vpiRange:
\_range: , line:45
|vpiLeftRange:
\_operation: , line:45
|vpiOpType:24
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:45
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:45
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiRightRange:
\_constant: , line:45
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (B_1), line:46, parent:div_block
|vpiName:B_1
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.B_1
|vpiNetType:36
|vpiRange:
\_range: , line:46
|vpiLeftRange:
\_operation: , line:46
|vpiOpType:24
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:46
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:46
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiRightRange:
\_constant: , line:46
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (B_2), line:47, parent:div_block
|vpiName:B_2
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.B_2
|vpiNetType:36
|vpiRange:
\_range: , line:47
|vpiLeftRange:
\_operation: , line:47
|vpiOpType:24
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:47
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:47
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiRightRange:
\_constant: , line:47
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (B_3), line:48, parent:div_block
|vpiName:B_3
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.B_3
|vpiNetType:36
|vpiRange:
\_range: , line:48
|vpiLeftRange:
\_operation: , line:48
|vpiOpType:24
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:48
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:48
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiRightRange:
\_constant: , line:48
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (B_4), line:49, parent:div_block
|vpiName:B_4
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.B_4
|vpiNetType:36
|vpiRange:
\_range: , line:49
|vpiLeftRange:
\_operation: , line:49
|vpiOpType:24
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:49
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:49
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiRightRange:
\_constant: , line:49
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (B_5), line:50, parent:div_block
|vpiName:B_5
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.B_5
|vpiNetType:36
|vpiRange:
\_range: , line:50
|vpiLeftRange:
\_operation: , line:50
|vpiOpType:24
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:50
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:50
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiRightRange:
\_constant: , line:50
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (B_6), line:51, parent:div_block
|vpiName:B_6
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.B_6
|vpiNetType:36
|vpiRange:
\_range: , line:51
|vpiLeftRange:
\_operation: , line:51
|vpiOpType:24
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:51
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:51
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiRightRange:
\_constant: , line:51
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (B_7), line:52, parent:div_block
|vpiName:B_7
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.B_7
|vpiNetType:36
|vpiRange:
\_range: , line:52
|vpiLeftRange:
\_operation: , line:52
|vpiOpType:24
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:52
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:52
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiRightRange:
\_constant: , line:52
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (div), line:29, parent:div_block
|vpiName:div
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.div
|vpiInstance:
\_module: work@div_algorithm (divider_block), file:third_party/cores/taiga/core/div_unit.sv, line:129, parent:div_unit_block
|vpiModule:
\_module: work@div_radix8_ET (div_block), file:third_party/cores/taiga/core/div_algorithms/div_algorithm.sv, line:43, parent:divider_block
|vpiDefName:work@div_radix8_ET
|vpiName:div_block
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block
|vpiPort:
\_port: (clk), line:27, parent:div_block
|vpiName:clk
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (clk), line:43
|vpiName:clk
|vpiActual:
\_logic_net: (clk), line:29, parent:divider_block
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (clk), line:27, parent:div_block
|vpiName:clk
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.clk
|vpiNetType:36
|vpiPort:
\_port: (rst), line:28, parent:div_block
|vpiName:rst
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (rst), line:43
|vpiName:rst
|vpiActual:
\_logic_net: (rst), line:30, parent:divider_block
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (rst), line:28, parent:div_block
|vpiName:rst
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.rst
|vpiNetType:36
|vpiPort:
\_port: (div), line:29, parent:div_block
|vpiName:div
|vpiDirection:5
|vpiHighConn:
\_ref_obj: (div), line:43
|vpiName:div
|vpiActual:
\_interface: work@unsigned_division_interface (div), file:third_party/cores/taiga/core/div_unit.sv, line:129
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_modport: (divider)
|vpiName:divider
|vpiIODecl:
\_io_decl: (remainder)
|vpiName:remainder
|vpiDirection:2
|vpiExpr:
\_logic_net: (remainder), line:247
|vpiName:remainder
|vpiNetType:36
|vpiRange:
\_range: , line:247
|vpiLeftRange:
\_constant: , line:247
|vpiDecompile:31
|INT:31
|vpiRightRange:
\_constant: , line:247
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (quotient)
|vpiName:quotient
|vpiDirection:2
|vpiExpr:
\_logic_net: (quotient), line:248
|vpiName:quotient
|vpiNetType:36
|vpiRange:
\_range: , line:248
|vpiLeftRange:
\_constant: , line:248
|vpiDecompile:31
|INT:31
|vpiRightRange:
\_constant: , line:248
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (done)
|vpiName:done
|vpiDirection:2
|vpiExpr:
\_logic_net: (done), line:249
|vpiName:done
|vpiNetType:36
|vpiIODecl:
\_io_decl: (divisor_is_zero)
|vpiName:divisor_is_zero
|vpiDirection:2
|vpiExpr:
\_logic_net: (divisor_is_zero), line:250
|vpiName:divisor_is_zero
|vpiNetType:36
|vpiIODecl:
\_io_decl: (dividend)
|vpiName:dividend
|vpiDirection:1
|vpiExpr:
\_logic_net: (dividend), line:245
|vpiName:dividend
|vpiNetType:36
|vpiRange:
\_range: , line:245
|vpiLeftRange:
\_constant: , line:245
|vpiDecompile:31
|INT:31
|vpiRightRange:
\_constant: , line:245
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (divisor)
|vpiName:divisor
|vpiDirection:1
|vpiExpr:
\_logic_net: (divisor), line:246
|vpiName:divisor
|vpiNetType:36
|vpiRange:
\_range: , line:246
|vpiLeftRange:
\_constant: , line:246
|vpiDecompile:31
|INT:31
|vpiRightRange:
\_constant: , line:246
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (start)
|vpiName:start
|vpiDirection:1
|vpiExpr:
\_logic_net: (start), line:244
|vpiName:start
|vpiNetType:36
|vpiInterface:
\_interface: work@unsigned_division_interface (div), file:third_party/cores/taiga/core/div_algorithms/div_algorithm.sv, line:43
|vpiDefName:work@unsigned_division_interface
|vpiName:div
|vpiModport:
\_modport: (divider)
|vpiModport:
\_modport: (requester)
|vpiName:requester
|vpiIODecl:
\_io_decl: (remainder)
|vpiName:remainder
|vpiDirection:1
|vpiExpr:
\_logic_net: (remainder), line:247
|vpiIODecl:
\_io_decl: (quotient)
|vpiName:quotient
|vpiDirection:1
|vpiExpr:
\_logic_net: (quotient), line:248
|vpiIODecl:
\_io_decl: (done)
|vpiName:done
|vpiDirection:1
|vpiExpr:
\_logic_net: (done), line:249
|vpiIODecl:
\_io_decl: (divisor_is_zero)
|vpiName:divisor_is_zero
|vpiDirection:1
|vpiExpr:
\_logic_net: (divisor_is_zero), line:250
|vpiIODecl:
\_io_decl: (dividend)
|vpiName:dividend
|vpiDirection:2
|vpiExpr:
\_logic_net: (dividend), line:245
|vpiIODecl:
\_io_decl: (divisor)
|vpiName:divisor
|vpiDirection:2
|vpiExpr:
\_logic_net: (divisor), line:246
|vpiIODecl:
\_io_decl: (start)
|vpiName:start
|vpiDirection:2
|vpiExpr:
\_logic_net: (start), line:244
|vpiInterface:
\_interface: work@unsigned_division_interface (div), file:third_party/cores/taiga/core/div_algorithms/div_algorithm.sv, line:43
|vpiNet:
\_logic_net: (clk), line:27, parent:div_block
|vpiNet:
\_logic_net: (rst), line:28, parent:div_block
|vpiNet:
\_logic_net: (terminate), line:32, parent:div_block
|vpiName:terminate
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.terminate
|vpiNetType:36
|vpiNet:
\_logic_net: (terminate_early), line:33, parent:div_block
|vpiName:terminate_early
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.terminate_early
|vpiNetType:36
|vpiNet:
\_logic_net: (shift_count), line:34, parent:div_block
|vpiName:shift_count
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.shift_count
|vpiNetType:36
|vpiRange:
\_range: , line:34
|vpiLeftRange:
\_constant: , line:34
|vpiConstType:7
|vpiDecompile:10
|vpiSize:32
|INT:10
|vpiRightRange:
\_constant: , line:34
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (PR), line:36, parent:div_block
|vpiName:PR
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.PR
|vpiNetType:36
|vpiRange:
\_range: , line:36
|vpiLeftRange:
\_operation: , line:36
|vpiOpType:24
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:36
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:36
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiRightRange:
\_constant: , line:36
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (Q_33), line:37, parent:div_block
|vpiName:Q_33
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.Q_33
|vpiNetType:36
|vpiRange:
\_range: , line:37
|vpiLeftRange:
\_ref_obj: (div.DATA_WIDTH), line:37
|vpiName:div.DATA_WIDTH
|vpiRightRange:
\_constant: , line:37
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (new_PR_sign), line:38, parent:div_block
|vpiName:new_PR_sign
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.new_PR_sign
|vpiNetType:36
|vpiRange:
\_range: , line:38
|vpiLeftRange:
\_constant: , line:38
|vpiConstType:7
|vpiDecompile:6
|vpiSize:32
|INT:6
|vpiRightRange:
\_constant: , line:38
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (new_PR_1), line:40, parent:div_block
|vpiName:new_PR_1
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.new_PR_1
|vpiNetType:36
|vpiRange:
\_range: , line:40
|vpiLeftRange:
\_operation: , line:40
|vpiOpType:24
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:40
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:40
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiRightRange:
\_constant: , line:40
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (new_PR_2), line:41, parent:div_block
|vpiName:new_PR_2
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.new_PR_2
|vpiNetType:36
|vpiRange:
\_range: , line:41
|vpiLeftRange:
\_operation: , line:41
|vpiOpType:24
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:41
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:41
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiRightRange:
\_constant: , line:41
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (new_PR_3), line:42, parent:div_block
|vpiName:new_PR_3
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.new_PR_3
|vpiNetType:36
|vpiRange:
\_range: , line:42
|vpiLeftRange:
\_operation: , line:42
|vpiOpType:24
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:42
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:42
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiRightRange:
\_constant: , line:42
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (new_PR_4), line:43, parent:div_block
|vpiName:new_PR_4
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.new_PR_4
|vpiNetType:36
|vpiRange:
\_range: , line:43
|vpiLeftRange:
\_operation: , line:43
|vpiOpType:24
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:43
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:43
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiRightRange:
\_constant: , line:43
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (new_PR_5), line:44, parent:div_block
|vpiName:new_PR_5
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.new_PR_5
|vpiNetType:36
|vpiRange:
\_range: , line:44
|vpiLeftRange:
\_operation: , line:44
|vpiOpType:24
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:44
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:44
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiRightRange:
\_constant: , line:44
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (new_PR_6), line:45, parent:div_block
|vpiName:new_PR_6
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.new_PR_6
|vpiNetType:36
|vpiRange:
\_range: , line:45
|vpiLeftRange:
\_operation: , line:45
|vpiOpType:24
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:45
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:45
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiRightRange:
\_constant: , line:45
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (new_PR_7), line:46, parent:div_block
|vpiName:new_PR_7
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.new_PR_7
|vpiNetType:36
|vpiRange:
\_range: , line:46
|vpiLeftRange:
\_operation: , line:46
|vpiOpType:24
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:46
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:46
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiRightRange:
\_constant: , line:46
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (div), line:29, parent:div_block
|vpiName:div
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.div
|vpiInstance:
\_module: work@div_algorithm (divider_block), file:third_party/cores/taiga/core/div_unit.sv, line:129, parent:div_unit_block
|vpiModule:
\_module: work@div_radix16 (div_block), file:third_party/cores/taiga/core/div_algorithms/div_algorithm.sv, line:44, parent:divider_block
|vpiDefName:work@div_radix16
|vpiName:div_block
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block
|vpiPort:
\_port: (clk), line:27, parent:div_block
|vpiName:clk
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (clk), line:44
|vpiName:clk
|vpiActual:
\_logic_net: (clk), line:29, parent:divider_block
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (clk), line:27, parent:div_block
|vpiName:clk
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.clk
|vpiNetType:36
|vpiPort:
\_port: (rst), line:28, parent:div_block
|vpiName:rst
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (rst), line:44
|vpiName:rst
|vpiActual:
\_logic_net: (rst), line:30, parent:divider_block
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (rst), line:28, parent:div_block
|vpiName:rst
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.rst
|vpiNetType:36
|vpiPort:
\_port: (div), line:29, parent:div_block
|vpiName:div
|vpiDirection:5
|vpiHighConn:
\_ref_obj: (div), line:44
|vpiName:div
|vpiActual:
\_interface: work@unsigned_division_interface (div), file:third_party/cores/taiga/core/div_unit.sv, line:129
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_modport: (divider)
|vpiName:divider
|vpiIODecl:
\_io_decl: (remainder)
|vpiName:remainder
|vpiDirection:2
|vpiExpr:
\_logic_net: (remainder), line:247
|vpiName:remainder
|vpiNetType:36
|vpiRange:
\_range: , line:247
|vpiLeftRange:
\_constant: , line:247
|vpiDecompile:31
|INT:31
|vpiRightRange:
\_constant: , line:247
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (quotient)
|vpiName:quotient
|vpiDirection:2
|vpiExpr:
\_logic_net: (quotient), line:248
|vpiName:quotient
|vpiNetType:36
|vpiRange:
\_range: , line:248
|vpiLeftRange:
\_constant: , line:248
|vpiDecompile:31
|INT:31
|vpiRightRange:
\_constant: , line:248
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (done)
|vpiName:done
|vpiDirection:2
|vpiExpr:
\_logic_net: (done), line:249
|vpiName:done
|vpiNetType:36
|vpiIODecl:
\_io_decl: (divisor_is_zero)
|vpiName:divisor_is_zero
|vpiDirection:2
|vpiExpr:
\_logic_net: (divisor_is_zero), line:250
|vpiName:divisor_is_zero
|vpiNetType:36
|vpiIODecl:
\_io_decl: (dividend)
|vpiName:dividend
|vpiDirection:1
|vpiExpr:
\_logic_net: (dividend), line:245
|vpiName:dividend
|vpiNetType:36
|vpiRange:
\_range: , line:245
|vpiLeftRange:
\_constant: , line:245
|vpiDecompile:31
|INT:31
|vpiRightRange:
\_constant: , line:245
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (divisor)
|vpiName:divisor
|vpiDirection:1
|vpiExpr:
\_logic_net: (divisor), line:246
|vpiName:divisor
|vpiNetType:36
|vpiRange:
\_range: , line:246
|vpiLeftRange:
\_constant: , line:246
|vpiDecompile:31
|INT:31
|vpiRightRange:
\_constant: , line:246
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (start)
|vpiName:start
|vpiDirection:1
|vpiExpr:
\_logic_net: (start), line:244
|vpiName:start
|vpiNetType:36
|vpiInterface:
\_interface: work@unsigned_division_interface (div), file:third_party/cores/taiga/core/div_algorithms/div_algorithm.sv, line:44
|vpiDefName:work@unsigned_division_interface
|vpiName:div
|vpiModport:
\_modport: (divider)
|vpiModport:
\_modport: (requester)
|vpiName:requester
|vpiIODecl:
\_io_decl: (remainder)
|vpiName:remainder
|vpiDirection:1
|vpiExpr:
\_logic_net: (remainder), line:247
|vpiIODecl:
\_io_decl: (quotient)
|vpiName:quotient
|vpiDirection:1
|vpiExpr:
\_logic_net: (quotient), line:248
|vpiIODecl:
\_io_decl: (done)
|vpiName:done
|vpiDirection:1
|vpiExpr:
\_logic_net: (done), line:249
|vpiIODecl:
\_io_decl: (divisor_is_zero)
|vpiName:divisor_is_zero
|vpiDirection:1
|vpiExpr:
\_logic_net: (divisor_is_zero), line:250
|vpiIODecl:
\_io_decl: (dividend)
|vpiName:dividend
|vpiDirection:2
|vpiExpr:
\_logic_net: (dividend), line:245
|vpiIODecl:
\_io_decl: (divisor)
|vpiName:divisor
|vpiDirection:2
|vpiExpr:
\_logic_net: (divisor), line:246
|vpiIODecl:
\_io_decl: (start)
|vpiName:start
|vpiDirection:2
|vpiExpr:
\_logic_net: (start), line:244
|vpiInterface:
\_interface: work@unsigned_division_interface (div), file:third_party/cores/taiga/core/div_algorithms/div_algorithm.sv, line:44
|vpiNet:
\_logic_net: (clk), line:27, parent:div_block
|vpiNet:
\_logic_net: (rst), line:28, parent:div_block
|vpiNet:
\_logic_net: (terminate), line:33, parent:div_block
|vpiName:terminate
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.terminate
|vpiNetType:36
|vpiNet:
\_logic_net: (shift_count), line:34, parent:div_block
|vpiName:shift_count
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.shift_count
|vpiNetType:36
|vpiRange:
\_range: , line:34
|vpiLeftRange:
\_operation: , line:34
|vpiOpType:11
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:34
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:34
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:34
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (PR), line:36, parent:div_block
|vpiName:PR
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.PR
|vpiNetType:36
|vpiRange:
\_range: , line:36
|vpiLeftRange:
\_operation: , line:36
|vpiOpType:24
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:36
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:36
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiRightRange:
\_constant: , line:36
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (PR_lower), line:37, parent:div_block
|vpiName:PR_lower
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.PR_lower
|vpiNetType:36
|vpiRange:
\_range: , line:37
|vpiLeftRange:
\_operation: , line:37
|vpiOpType:24
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:37
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:37
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiRightRange:
\_constant: , line:37
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (PR_upper), line:38, parent:div_block
|vpiName:PR_upper
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.PR_upper
|vpiNetType:36
|vpiRange:
\_range: , line:38
|vpiLeftRange:
\_operation: , line:38
|vpiOpType:24
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:38
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:38
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiRightRange:
\_constant: , line:38
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (Q_lower), line:39, parent:div_block
|vpiName:Q_lower
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.Q_lower
|vpiNetType:36
|vpiRange:
\_range: , line:39
|vpiLeftRange:
\_operation: , line:39
|vpiOpType:11
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:39
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:39
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:39
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (Q_upper), line:40, parent:div_block
|vpiName:Q_upper
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.Q_upper
|vpiNetType:36
|vpiRange:
\_range: , line:40
|vpiLeftRange:
\_operation: , line:40
|vpiOpType:11
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:40
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:40
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:40
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (new_PR_sign), line:42, parent:div_block
|vpiName:new_PR_sign
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.new_PR_sign
|vpiNetType:36
|vpiRange:
\_range: , line:42
|vpiLeftRange:
\_constant: , line:42
|vpiConstType:7
|vpiDecompile:6
|vpiSize:32
|INT:6
|vpiRightRange:
\_constant: , line:42
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (new_PR_8), line:43, parent:div_block
|vpiName:new_PR_8
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.new_PR_8
|vpiNetType:36
|vpiRange:
\_range: , line:43
|vpiLeftRange:
\_operation: , line:43
|vpiOpType:24
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:43
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:43
|vpiConstType:7
|vpiDecompile:4
|vpiSize:32
|INT:4
|vpiRightRange:
\_constant: , line:43
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (B_6), line:46, parent:div_block
|vpiName:B_6
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.B_6
|vpiNetType:36
|vpiRange:
\_range: , line:46
|vpiLeftRange:
\_operation: , line:46
|vpiOpType:24
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:46
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:46
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiRightRange:
\_constant: , line:46
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (B_10), line:47, parent:div_block
|vpiName:B_10
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.B_10
|vpiNetType:36
|vpiRange:
\_range: , line:47
|vpiLeftRange:
\_operation: , line:47
|vpiOpType:24
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:47
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:47
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiRightRange:
\_constant: , line:47
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (B_12), line:48, parent:div_block
|vpiName:B_12
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.B_12
|vpiNetType:36
|vpiRange:
\_range: , line:48
|vpiLeftRange:
\_operation: , line:48
|vpiOpType:24
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:48
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:48
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiRightRange:
\_constant: , line:48
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (B_14), line:49, parent:div_block
|vpiName:B_14
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.B_14
|vpiNetType:36
|vpiRange:
\_range: , line:49
|vpiLeftRange:
\_operation: , line:49
|vpiOpType:24
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:49
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:49
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiRightRange:
\_constant: , line:49
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (div), line:29, parent:div_block
|vpiName:div
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.div
|vpiInstance:
\_module: work@div_algorithm (divider_block), file:third_party/cores/taiga/core/div_unit.sv, line:129, parent:div_unit_block
|vpiArrayNet:
\_array_net: (new_PR), line:44, parent:div_block
|vpiName:new_PR
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.new_PR
|vpiSize:7
|vpiNet:
\_logic_net: , parent:new_PR
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.new_PR
|vpiNetType:36
|vpiRange:
\_range: , line:44
|vpiLeftRange:
\_operation: , line:44
|vpiOpType:24
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:44
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:44
|vpiConstType:7
|vpiDecompile:4
|vpiSize:32
|INT:4
|vpiRightRange:
\_constant: , line:44
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiRange:
\_range: , line:44
|vpiLeftRange:
\_constant: , line:44
|vpiConstType:7
|vpiDecompile:6
|vpiSize:32
|INT:6
|vpiRightRange:
\_constant: , line:44
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiModule:
\_module: work@div_quick_naive (div_block), file:third_party/cores/taiga/core/div_algorithms/div_algorithm.sv, line:45, parent:divider_block
|vpiDefName:work@div_quick_naive
|vpiName:div_block
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block
|vpiPort:
\_port: (clk), line:27, parent:div_block
|vpiName:clk
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (clk), line:45
|vpiName:clk
|vpiActual:
\_logic_net: (clk), line:29, parent:divider_block
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (clk), line:27, parent:div_block
|vpiName:clk
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.clk
|vpiNetType:36
|vpiPort:
\_port: (rst), line:28, parent:div_block
|vpiName:rst
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (rst), line:45
|vpiName:rst
|vpiActual:
\_logic_net: (rst), line:30, parent:divider_block
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (rst), line:28, parent:div_block
|vpiName:rst
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.rst
|vpiNetType:36
|vpiPort:
\_port: (div), line:29, parent:div_block
|vpiName:div
|vpiDirection:5
|vpiHighConn:
\_ref_obj: (div), line:45
|vpiName:div
|vpiActual:
\_interface: work@unsigned_division_interface (div), file:third_party/cores/taiga/core/div_unit.sv, line:129
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_modport: (divider)
|vpiName:divider
|vpiIODecl:
\_io_decl: (remainder)
|vpiName:remainder
|vpiDirection:2
|vpiExpr:
\_logic_net: (remainder), line:247
|vpiName:remainder
|vpiNetType:36
|vpiRange:
\_range: , line:247
|vpiLeftRange:
\_constant: , line:247
|vpiDecompile:31
|INT:31
|vpiRightRange:
\_constant: , line:247
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (quotient)
|vpiName:quotient
|vpiDirection:2
|vpiExpr:
\_logic_net: (quotient), line:248
|vpiName:quotient
|vpiNetType:36
|vpiRange:
\_range: , line:248
|vpiLeftRange:
\_constant: , line:248
|vpiDecompile:31
|INT:31
|vpiRightRange:
\_constant: , line:248
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (done)
|vpiName:done
|vpiDirection:2
|vpiExpr:
\_logic_net: (done), line:249
|vpiName:done
|vpiNetType:36
|vpiIODecl:
\_io_decl: (divisor_is_zero)
|vpiName:divisor_is_zero
|vpiDirection:2
|vpiExpr:
\_logic_net: (divisor_is_zero), line:250
|vpiName:divisor_is_zero
|vpiNetType:36
|vpiIODecl:
\_io_decl: (dividend)
|vpiName:dividend
|vpiDirection:1
|vpiExpr:
\_logic_net: (dividend), line:245
|vpiName:dividend
|vpiNetType:36
|vpiRange:
\_range: , line:245
|vpiLeftRange:
\_constant: , line:245
|vpiDecompile:31
|INT:31
|vpiRightRange:
\_constant: , line:245
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (divisor)
|vpiName:divisor
|vpiDirection:1
|vpiExpr:
\_logic_net: (divisor), line:246
|vpiName:divisor
|vpiNetType:36
|vpiRange:
\_range: , line:246
|vpiLeftRange:
\_constant: , line:246
|vpiDecompile:31
|INT:31
|vpiRightRange:
\_constant: , line:246
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (start)
|vpiName:start
|vpiDirection:1
|vpiExpr:
\_logic_net: (start), line:244
|vpiName:start
|vpiNetType:36
|vpiInterface:
\_interface: work@unsigned_division_interface (div), file:third_party/cores/taiga/core/div_algorithms/div_algorithm.sv, line:45
|vpiDefName:work@unsigned_division_interface
|vpiName:div
|vpiModport:
\_modport: (divider)
|vpiModport:
\_modport: (requester)
|vpiName:requester
|vpiIODecl:
\_io_decl: (remainder)
|vpiName:remainder
|vpiDirection:1
|vpiExpr:
\_logic_net: (remainder), line:247
|vpiIODecl:
\_io_decl: (quotient)
|vpiName:quotient
|vpiDirection:1
|vpiExpr:
\_logic_net: (quotient), line:248
|vpiIODecl:
\_io_decl: (done)
|vpiName:done
|vpiDirection:1
|vpiExpr:
\_logic_net: (done), line:249
|vpiIODecl:
\_io_decl: (divisor_is_zero)
|vpiName:divisor_is_zero
|vpiDirection:1
|vpiExpr:
\_logic_net: (divisor_is_zero), line:250
|vpiIODecl:
\_io_decl: (dividend)
|vpiName:dividend
|vpiDirection:2
|vpiExpr:
\_logic_net: (dividend), line:245
|vpiIODecl:
\_io_decl: (divisor)
|vpiName:divisor
|vpiDirection:2
|vpiExpr:
\_logic_net: (divisor), line:246
|vpiIODecl:
\_io_decl: (start)
|vpiName:start
|vpiDirection:2
|vpiExpr:
\_logic_net: (start), line:244
|vpiInterface:
\_interface: work@unsigned_division_interface (div), file:third_party/cores/taiga/core/div_algorithms/div_algorithm.sv, line:45
|vpiModule:
\_module: work@msb_naive (msb_r), file:third_party/cores/taiga/core/div_algorithms/div_quick_naive.sv, line:53, parent:div_block
|vpiDefName:work@msb_naive
|vpiName:msb_r
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.msb_r
|vpiPort:
\_port: (msb_input), line:27, parent:msb_r
|vpiName:msb_input
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (div.remainder), line:53
|vpiName:div.remainder
|vpiActual:
\_logic_net: (remainder), line:247
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (msb_input), line:27, parent:msb_r
|vpiName:msb_input
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.msb_r.msb_input
|vpiNetType:36
|vpiRange:
\_range: , line:27
|vpiLeftRange:
\_constant: , line:27
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:27
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiPort:
\_port: (msb), line:28, parent:msb_r
|vpiName:msb
|vpiDirection:2
|vpiHighConn:
\_ref_obj: (R_MSB), line:53
|vpiName:R_MSB
|vpiActual:
\_logic_net: (R_MSB), line:48, parent:div_block
|vpiName:R_MSB
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.R_MSB
|vpiNetType:36
|vpiRange:
\_range: , line:48
|vpiLeftRange:
\_constant: , line:48
|vpiDecompile:-1
|INT:-1
|vpiRightRange:
\_constant: , line:48
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (msb), line:28, parent:msb_r
|vpiName:msb
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.msb_r.msb
|vpiNetType:36
|vpiRange:
\_range: , line:28
|vpiLeftRange:
\_constant: , line:28
|vpiConstType:7
|vpiDecompile:4
|vpiSize:32
|INT:4
|vpiRightRange:
\_constant: , line:28
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (msb_input), line:27, parent:msb_r
|vpiNet:
\_logic_net: (msb), line:28, parent:msb_r
|vpiInstance:
\_module: work@div_quick_naive (div_block), file:third_party/cores/taiga/core/div_algorithms/div_algorithm.sv, line:45, parent:divider_block
|vpiModule:
\_module: work@msb_naive (msb_b), file:third_party/cores/taiga/core/div_algorithms/div_quick_naive.sv, line:54, parent:div_block
|vpiDefName:work@msb_naive
|vpiName:msb_b
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.msb_b
|vpiPort:
\_port: (msb_input), line:27, parent:msb_b
|vpiName:msb_input
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (div.divisor), line:54
|vpiName:div.divisor
|vpiActual:
\_logic_net: (divisor), line:246
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (msb_input), line:27, parent:msb_b
|vpiName:msb_input
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.msb_b.msb_input
|vpiNetType:36
|vpiRange:
\_range: , line:27
|vpiLeftRange:
\_constant: , line:27
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:27
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiPort:
\_port: (msb), line:28, parent:msb_b
|vpiName:msb
|vpiDirection:2
|vpiHighConn:
\_ref_obj: (B_MSB), line:54
|vpiName:B_MSB
|vpiActual:
\_logic_net: (B_MSB), line:49, parent:div_block
|vpiName:B_MSB
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.B_MSB
|vpiNetType:36
|vpiRange:
\_range: , line:49
|vpiLeftRange:
\_constant: , line:49
|vpiDecompile:-1
|INT:-1
|vpiRightRange:
\_constant: , line:49
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (msb), line:28, parent:msb_b
|vpiName:msb
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.msb_b.msb
|vpiNetType:36
|vpiRange:
\_range: , line:28
|vpiLeftRange:
\_constant: , line:28
|vpiConstType:7
|vpiDecompile:4
|vpiSize:32
|INT:4
|vpiRightRange:
\_constant: , line:28
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (msb_input), line:27, parent:msb_b
|vpiNet:
\_logic_net: (msb), line:28, parent:msb_b
|vpiInstance:
\_module: work@div_quick_naive (div_block), file:third_party/cores/taiga/core/div_algorithms/div_algorithm.sv, line:45, parent:divider_block
|vpiNet:
\_logic_net: (clk), line:27, parent:div_block
|vpiNet:
\_logic_net: (rst), line:28, parent:div_block
|vpiNet:
\_logic_net: (running), line:32, parent:div_block
|vpiName:running
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.running
|vpiNetType:36
|vpiNet:
\_logic_net: (terminate), line:33, parent:div_block
|vpiName:terminate
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.terminate
|vpiNetType:36
|vpiNet:
\_logic_net: (A1), line:35, parent:div_block
|vpiName:A1
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.A1
|vpiNetType:36
|vpiRange:
\_range: , line:35
|vpiLeftRange:
\_ref_obj: (div.DATA_WIDTH), line:35
|vpiName:div.DATA_WIDTH
|vpiRightRange:
\_constant: , line:35
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (A2), line:36, parent:div_block
|vpiName:A2
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.A2
|vpiNetType:36
|vpiRange:
\_range: , line:36
|vpiLeftRange:
\_operation: , line:36
|vpiOpType:11
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:36
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:36
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:36
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (new_R), line:38, parent:div_block
|vpiName:new_R
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.new_R
|vpiNetType:36
|vpiRange:
\_range: , line:38
|vpiLeftRange:
\_operation: , line:38
|vpiOpType:11
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:38
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:38
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:38
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (new_Q_bit), line:39, parent:div_block
|vpiName:new_Q_bit
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.new_Q_bit
|vpiNetType:36
|vpiRange:
\_range: , line:39
|vpiLeftRange:
\_operation: , line:39
|vpiOpType:11
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:39
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:39
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:39
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (Q_bit1), line:41, parent:div_block
|vpiName:Q_bit1
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.Q_bit1
|vpiNetType:36
|vpiRange:
\_range: , line:41
|vpiLeftRange:
\_operation: , line:41
|vpiOpType:11
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:41
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:41
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:41
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (Q_bit2), line:42, parent:div_block
|vpiName:Q_bit2
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.Q_bit2
|vpiNetType:36
|vpiRange:
\_range: , line:42
|vpiLeftRange:
\_operation: , line:42
|vpiOpType:11
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:42
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:42
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:42
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (B1), line:44, parent:div_block
|vpiName:B1
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.B1
|vpiNetType:36
|vpiRange:
\_range: , line:44
|vpiLeftRange:
\_operation: , line:44
|vpiOpType:11
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:44
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:44
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:44
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (B2), line:45, parent:div_block
|vpiName:B2
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.B2
|vpiNetType:36
|vpiRange:
\_range: , line:45
|vpiLeftRange:
\_operation: , line:45
|vpiOpType:11
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:45
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:45
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:45
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (R_MSB), line:48, parent:div_block
|vpiNet:
\_logic_net: (B_MSB), line:49, parent:div_block
|vpiNet:
\_logic_net: (B_MSB_r), line:50, parent:div_block
|vpiName:B_MSB_r
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.B_MSB_r
|vpiNetType:36
|vpiRange:
\_range: , line:50
|vpiLeftRange:
\_constant: , line:50
|vpiDecompile:-1
|INT:-1
|vpiRightRange:
\_constant: , line:50
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (MSB_delta), line:51, parent:div_block
|vpiName:MSB_delta
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.MSB_delta
|vpiNetType:36
|vpiRange:
\_range: , line:51
|vpiLeftRange:
\_constant: , line:51
|vpiDecompile:-1
|INT:-1
|vpiRightRange:
\_constant: , line:51
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (div), line:29, parent:div_block
|vpiName:div
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.div
|vpiInstance:
\_module: work@div_algorithm (divider_block), file:third_party/cores/taiga/core/div_unit.sv, line:129, parent:div_unit_block
|vpiParameter:
\_parameter: (MSB_W), line:47
|vpiName:MSB_W
|INT:0
|vpiModule:
\_module: work@div_quick_clz (div_block), file:third_party/cores/taiga/core/div_algorithms/div_algorithm.sv, line:46, parent:divider_block
|vpiDefName:work@div_quick_clz
|vpiName:div_block
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block
|vpiPort:
\_port: (clk), line:27, parent:div_block
|vpiName:clk
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (clk), line:46
|vpiName:clk
|vpiActual:
\_logic_net: (clk), line:29, parent:divider_block
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (clk), line:27, parent:div_block
|vpiName:clk
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.clk
|vpiNetType:36
|vpiPort:
\_port: (rst), line:28, parent:div_block
|vpiName:rst
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (rst), line:46
|vpiName:rst
|vpiActual:
\_logic_net: (rst), line:30, parent:divider_block
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (rst), line:28, parent:div_block
|vpiName:rst
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.rst
|vpiNetType:36
|vpiPort:
\_port: (div), line:29, parent:div_block
|vpiName:div
|vpiDirection:5
|vpiHighConn:
\_ref_obj: (div), line:46
|vpiName:div
|vpiActual:
\_interface: work@unsigned_division_interface (div), file:third_party/cores/taiga/core/div_unit.sv, line:129
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_modport: (divider)
|vpiName:divider
|vpiIODecl:
\_io_decl: (remainder)
|vpiName:remainder
|vpiDirection:2
|vpiExpr:
\_logic_net: (remainder), line:247
|vpiName:remainder
|vpiNetType:36
|vpiRange:
\_range: , line:247
|vpiLeftRange:
\_constant: , line:247
|vpiDecompile:31
|INT:31
|vpiRightRange:
\_constant: , line:247
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (quotient)
|vpiName:quotient
|vpiDirection:2
|vpiExpr:
\_logic_net: (quotient), line:248
|vpiName:quotient
|vpiNetType:36
|vpiRange:
\_range: , line:248
|vpiLeftRange:
\_constant: , line:248
|vpiDecompile:31
|INT:31
|vpiRightRange:
\_constant: , line:248
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (done)
|vpiName:done
|vpiDirection:2
|vpiExpr:
\_logic_net: (done), line:249
|vpiName:done
|vpiNetType:36
|vpiIODecl:
\_io_decl: (divisor_is_zero)
|vpiName:divisor_is_zero
|vpiDirection:2
|vpiExpr:
\_logic_net: (divisor_is_zero), line:250
|vpiName:divisor_is_zero
|vpiNetType:36
|vpiIODecl:
\_io_decl: (dividend)
|vpiName:dividend
|vpiDirection:1
|vpiExpr:
\_logic_net: (dividend), line:245
|vpiName:dividend
|vpiNetType:36
|vpiRange:
\_range: , line:245
|vpiLeftRange:
\_constant: , line:245
|vpiDecompile:31
|INT:31
|vpiRightRange:
\_constant: , line:245
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (divisor)
|vpiName:divisor
|vpiDirection:1
|vpiExpr:
\_logic_net: (divisor), line:246
|vpiName:divisor
|vpiNetType:36
|vpiRange:
\_range: , line:246
|vpiLeftRange:
\_constant: , line:246
|vpiDecompile:31
|INT:31
|vpiRightRange:
\_constant: , line:246
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (start)
|vpiName:start
|vpiDirection:1
|vpiExpr:
\_logic_net: (start), line:244
|vpiName:start
|vpiNetType:36
|vpiInterface:
\_interface: work@unsigned_division_interface (div), file:third_party/cores/taiga/core/div_algorithms/div_algorithm.sv, line:46
|vpiDefName:work@unsigned_division_interface
|vpiName:div
|vpiModport:
\_modport: (divider)
|vpiModport:
\_modport: (requester)
|vpiName:requester
|vpiIODecl:
\_io_decl: (remainder)
|vpiName:remainder
|vpiDirection:1
|vpiExpr:
\_logic_net: (remainder), line:247
|vpiIODecl:
\_io_decl: (quotient)
|vpiName:quotient
|vpiDirection:1
|vpiExpr:
\_logic_net: (quotient), line:248
|vpiIODecl:
\_io_decl: (done)
|vpiName:done
|vpiDirection:1
|vpiExpr:
\_logic_net: (done), line:249
|vpiIODecl:
\_io_decl: (divisor_is_zero)
|vpiName:divisor_is_zero
|vpiDirection:1
|vpiExpr:
\_logic_net: (divisor_is_zero), line:250
|vpiIODecl:
\_io_decl: (dividend)
|vpiName:dividend
|vpiDirection:2
|vpiExpr:
\_logic_net: (dividend), line:245
|vpiIODecl:
\_io_decl: (divisor)
|vpiName:divisor
|vpiDirection:2
|vpiExpr:
\_logic_net: (divisor), line:246
|vpiIODecl:
\_io_decl: (start)
|vpiName:start
|vpiDirection:2
|vpiExpr:
\_logic_net: (start), line:244
|vpiInterface:
\_interface: work@unsigned_division_interface (div), file:third_party/cores/taiga/core/div_algorithms/div_algorithm.sv, line:46
|vpiModule:
\_module: work@clz (remainder_clz_block), file:third_party/cores/taiga/core/div_algorithms/div_quick_clz.sv, line:57, parent:div_block
|vpiDefName:work@clz
|vpiName:remainder_clz_block
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.remainder_clz_block
|vpiPort:
\_port: (clz_input), line:25, parent:remainder_clz_block
|vpiName:clz_input
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (div.remainder), line:57
|vpiName:div.remainder
|vpiActual:
\_logic_net: (remainder), line:247
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (clz_input), line:25, parent:remainder_clz_block
|vpiName:clz_input
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.remainder_clz_block.clz_input
|vpiNetType:36
|vpiRange:
\_range: , line:25
|vpiLeftRange:
\_constant: , line:25
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:25
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiPort:
\_port: (clz), line:26, parent:remainder_clz_block
|vpiName:clz
|vpiDirection:2
|vpiHighConn:
\_ref_obj: (remainder_CLZ), line:57
|vpiName:remainder_CLZ
|vpiActual:
\_logic_net: (remainder_CLZ), line:51, parent:div_block
|vpiName:remainder_CLZ
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.remainder_CLZ
|vpiNetType:36
|vpiRange:
\_range: , line:51
|vpiLeftRange:
\_constant: , line:51
|vpiDecompile:-1
|INT:-1
|vpiRightRange:
\_constant: , line:51
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (clz), line:26, parent:remainder_clz_block
|vpiName:clz
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.remainder_clz_block.clz
|vpiNetType:36
|vpiRange:
\_range: , line:26
|vpiLeftRange:
\_constant: , line:26
|vpiConstType:7
|vpiDecompile:4
|vpiSize:32
|INT:4
|vpiRightRange:
\_constant: , line:26
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (clz_input), line:25, parent:remainder_clz_block
|vpiNet:
\_logic_net: (clz), line:26, parent:remainder_clz_block
|vpiNet:
\_logic_net: (sub_clz), line:30, parent:remainder_clz_block
|vpiName:sub_clz
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.remainder_clz_block.sub_clz
|vpiNetType:36
|vpiRange:
\_range: , line:30
|vpiLeftRange:
\_constant: , line:30
|vpiConstType:7
|vpiDecompile:7
|vpiSize:32
|INT:7
|vpiRightRange:
\_constant: , line:30
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiInstance:
\_module: work@div_quick_clz (div_block), file:third_party/cores/taiga/core/div_algorithms/div_algorithm.sv, line:46, parent:divider_block
|vpiArrayNet:
\_array_net: (low_order_clz), line:29, parent:remainder_clz_block
|vpiName:low_order_clz
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.remainder_clz_block.low_order_clz
|vpiSize:8
|vpiNet:
\_logic_net: , parent:low_order_clz
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.remainder_clz_block.low_order_clz
|vpiNetType:36
|vpiRange:
\_range: , line:29
|vpiLeftRange:
\_constant: , line:29
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:29
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiRange:
\_range: , line:29
|vpiLeftRange:
\_constant: , line:29
|vpiConstType:7
|vpiDecompile:7
|vpiSize:32
|INT:7
|vpiRightRange:
\_constant: , line:29
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiArrayNet:
\_array_net: (upper_lower), line:32, parent:remainder_clz_block
|vpiName:upper_lower
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.remainder_clz_block.upper_lower
|vpiSize:4
|vpiNet:
\_logic_net: , parent:upper_lower
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.remainder_clz_block.upper_lower
|vpiNetType:36
|vpiRange:
\_range: , line:32
|vpiLeftRange:
\_constant: , line:32
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:32
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiRange:
\_range: , line:32
|vpiLeftRange:
\_constant: , line:32
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiRightRange:
\_constant: , line:32
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiModule:
\_module: work@clz (divisor_clz_block), file:third_party/cores/taiga/core/div_algorithms/div_quick_clz.sv, line:58, parent:div_block
|vpiDefName:work@clz
|vpiName:divisor_clz_block
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.divisor_clz_block
|vpiPort:
\_port: (clz_input), line:25, parent:divisor_clz_block
|vpiName:clz_input
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (div.divisor), line:58
|vpiName:div.divisor
|vpiActual:
\_logic_net: (divisor), line:246
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (clz_input), line:25, parent:divisor_clz_block
|vpiName:clz_input
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.divisor_clz_block.clz_input
|vpiNetType:36
|vpiRange:
\_range: , line:25
|vpiLeftRange:
\_constant: , line:25
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:25
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiPort:
\_port: (clz), line:26, parent:divisor_clz_block
|vpiName:clz
|vpiDirection:2
|vpiHighConn:
\_ref_obj: (divisor_CLZ), line:58
|vpiName:divisor_CLZ
|vpiActual:
\_logic_net: (divisor_CLZ), line:52, parent:div_block
|vpiName:divisor_CLZ
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.divisor_CLZ
|vpiNetType:36
|vpiRange:
\_range: , line:52
|vpiLeftRange:
\_constant: , line:52
|vpiDecompile:-1
|INT:-1
|vpiRightRange:
\_constant: , line:52
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (clz), line:26, parent:divisor_clz_block
|vpiName:clz
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.divisor_clz_block.clz
|vpiNetType:36
|vpiRange:
\_range: , line:26
|vpiLeftRange:
\_constant: , line:26
|vpiConstType:7
|vpiDecompile:4
|vpiSize:32
|INT:4
|vpiRightRange:
\_constant: , line:26
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (clz_input), line:25, parent:divisor_clz_block
|vpiNet:
\_logic_net: (clz), line:26, parent:divisor_clz_block
|vpiNet:
\_logic_net: (sub_clz), line:30, parent:divisor_clz_block
|vpiName:sub_clz
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.divisor_clz_block.sub_clz
|vpiNetType:36
|vpiRange:
\_range: , line:30
|vpiLeftRange:
\_constant: , line:30
|vpiConstType:7
|vpiDecompile:7
|vpiSize:32
|INT:7
|vpiRightRange:
\_constant: , line:30
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiInstance:
\_module: work@div_quick_clz (div_block), file:third_party/cores/taiga/core/div_algorithms/div_algorithm.sv, line:46, parent:divider_block
|vpiArrayNet:
\_array_net: (low_order_clz), line:29, parent:divisor_clz_block
|vpiName:low_order_clz
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.divisor_clz_block.low_order_clz
|vpiSize:8
|vpiNet:
\_logic_net: , parent:low_order_clz
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.divisor_clz_block.low_order_clz
|vpiNetType:36
|vpiRange:
\_range: , line:29
|vpiLeftRange:
\_constant: , line:29
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:29
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiRange:
\_range: , line:29
|vpiLeftRange:
\_constant: , line:29
|vpiConstType:7
|vpiDecompile:7
|vpiSize:32
|INT:7
|vpiRightRange:
\_constant: , line:29
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiArrayNet:
\_array_net: (upper_lower), line:32, parent:divisor_clz_block
|vpiName:upper_lower
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.divisor_clz_block.upper_lower
|vpiSize:4
|vpiNet:
\_logic_net: , parent:upper_lower
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.divisor_clz_block.upper_lower
|vpiNetType:36
|vpiRange:
\_range: , line:32
|vpiLeftRange:
\_constant: , line:32
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:32
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiRange:
\_range: , line:32
|vpiLeftRange:
\_constant: , line:32
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiRightRange:
\_constant: , line:32
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (clk), line:27, parent:div_block
|vpiNet:
\_logic_net: (rst), line:28, parent:div_block
|vpiNet:
\_logic_net: (running), line:32, parent:div_block
|vpiName:running
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.running
|vpiNetType:36
|vpiNet:
\_logic_net: (terminate), line:33, parent:div_block
|vpiName:terminate
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.terminate
|vpiNetType:36
|vpiNet:
\_logic_net: (normalized_divisor), line:35, parent:div_block
|vpiName:normalized_divisor
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.normalized_divisor
|vpiNetType:36
|vpiRange:
\_range: , line:35
|vpiLeftRange:
\_operation: , line:35
|vpiOpType:11
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:35
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:35
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:35
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (overflow), line:37, parent:div_block
|vpiName:overflow
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.overflow
|vpiNetType:36
|vpiNet:
\_logic_net: (subtraction1), line:38, parent:div_block
|vpiName:subtraction1
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.subtraction1
|vpiNetType:36
|vpiRange:
\_range: , line:38
|vpiLeftRange:
\_operation: , line:38
|vpiOpType:11
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:38
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:38
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:38
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (subtraction2), line:39, parent:div_block
|vpiName:subtraction2
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.subtraction2
|vpiNetType:36
|vpiRange:
\_range: , line:39
|vpiLeftRange:
\_operation: , line:39
|vpiOpType:11
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:39
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:39
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:39
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (new_remainder), line:41, parent:div_block
|vpiName:new_remainder
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.new_remainder
|vpiNetType:36
|vpiRange:
\_range: , line:41
|vpiLeftRange:
\_operation: , line:41
|vpiOpType:11
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:41
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:41
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:41
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (new_quotient), line:42, parent:div_block
|vpiName:new_quotient
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.new_quotient
|vpiNetType:36
|vpiRange:
\_range: , line:42
|vpiLeftRange:
\_operation: , line:42
|vpiOpType:11
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:42
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:42
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:42
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (new_Q_bit1), line:44, parent:div_block
|vpiName:new_Q_bit1
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.new_Q_bit1
|vpiNetType:36
|vpiRange:
\_range: , line:44
|vpiLeftRange:
\_operation: , line:44
|vpiOpType:11
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:44
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:44
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:44
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (new_Q_bit2), line:45, parent:div_block
|vpiName:new_Q_bit2
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.new_Q_bit2
|vpiNetType:36
|vpiRange:
\_range: , line:45
|vpiLeftRange:
\_operation: , line:45
|vpiOpType:11
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:45
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:45
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:45
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (test_multiple1), line:47, parent:div_block
|vpiName:test_multiple1
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.test_multiple1
|vpiNetType:36
|vpiRange:
\_range: , line:47
|vpiLeftRange:
\_operation: , line:47
|vpiOpType:11
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:47
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:47
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:47
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (test_multiple2), line:48, parent:div_block
|vpiName:test_multiple2
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.test_multiple2
|vpiNetType:36
|vpiRange:
\_range: , line:48
|vpiLeftRange:
\_operation: , line:48
|vpiOpType:11
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:48
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:48
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:48
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (remainder_CLZ), line:51, parent:div_block
|vpiNet:
\_logic_net: (divisor_CLZ), line:52, parent:div_block
|vpiNet:
\_logic_net: (divisor_CLZ_r), line:53, parent:div_block
|vpiName:divisor_CLZ_r
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.divisor_CLZ_r
|vpiNetType:36
|vpiRange:
\_range: , line:53
|vpiLeftRange:
\_constant: , line:53
|vpiDecompile:-1
|INT:-1
|vpiRightRange:
\_constant: , line:53
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (CLZ_delta), line:54, parent:div_block
|vpiName:CLZ_delta
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.CLZ_delta
|vpiNetType:36
|vpiRange:
\_range: , line:54
|vpiLeftRange:
\_constant: , line:54
|vpiDecompile:-1
|INT:-1
|vpiRightRange:
\_constant: , line:54
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (div), line:29, parent:div_block
|vpiName:div
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.div
|vpiInstance:
\_module: work@div_algorithm (divider_block), file:third_party/cores/taiga/core/div_unit.sv, line:129, parent:div_unit_block
|vpiParameter:
\_parameter: (CLZ_W), line:50
|vpiName:CLZ_W
|INT:0
|vpiModule:
\_module: work@div_quick_clz_mk2 (div_block), file:third_party/cores/taiga/core/div_algorithms/div_algorithm.sv, line:47, parent:divider_block
|vpiDefName:work@div_quick_clz_mk2
|vpiName:div_block
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block
|vpiPort:
\_port: (clk), line:27, parent:div_block
|vpiName:clk
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (clk), line:47
|vpiName:clk
|vpiActual:
\_logic_net: (clk), line:29, parent:divider_block
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (clk), line:27, parent:div_block
|vpiName:clk
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.clk
|vpiNetType:36
|vpiPort:
\_port: (rst), line:28, parent:div_block
|vpiName:rst
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (rst), line:47
|vpiName:rst
|vpiActual:
\_logic_net: (rst), line:30, parent:divider_block
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (rst), line:28, parent:div_block
|vpiName:rst
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.rst
|vpiNetType:36
|vpiPort:
\_port: (div), line:29, parent:div_block
|vpiName:div
|vpiDirection:5
|vpiHighConn:
\_ref_obj: (div), line:47
|vpiName:div
|vpiActual:
\_interface: work@unsigned_division_interface (div), file:third_party/cores/taiga/core/div_unit.sv, line:129
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_modport: (divider)
|vpiName:divider
|vpiIODecl:
\_io_decl: (remainder)
|vpiName:remainder
|vpiDirection:2
|vpiExpr:
\_logic_net: (remainder), line:247
|vpiName:remainder
|vpiNetType:36
|vpiRange:
\_range: , line:247
|vpiLeftRange:
\_constant: , line:247
|vpiDecompile:31
|INT:31
|vpiRightRange:
\_constant: , line:247
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (quotient)
|vpiName:quotient
|vpiDirection:2
|vpiExpr:
\_logic_net: (quotient), line:248
|vpiName:quotient
|vpiNetType:36
|vpiRange:
\_range: , line:248
|vpiLeftRange:
\_constant: , line:248
|vpiDecompile:31
|INT:31
|vpiRightRange:
\_constant: , line:248
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (done)
|vpiName:done
|vpiDirection:2
|vpiExpr:
\_logic_net: (done), line:249
|vpiName:done
|vpiNetType:36
|vpiIODecl:
\_io_decl: (divisor_is_zero)
|vpiName:divisor_is_zero
|vpiDirection:2
|vpiExpr:
\_logic_net: (divisor_is_zero), line:250
|vpiName:divisor_is_zero
|vpiNetType:36
|vpiIODecl:
\_io_decl: (dividend)
|vpiName:dividend
|vpiDirection:1
|vpiExpr:
\_logic_net: (dividend), line:245
|vpiName:dividend
|vpiNetType:36
|vpiRange:
\_range: , line:245
|vpiLeftRange:
\_constant: , line:245
|vpiDecompile:31
|INT:31
|vpiRightRange:
\_constant: , line:245
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (divisor)
|vpiName:divisor
|vpiDirection:1
|vpiExpr:
\_logic_net: (divisor), line:246
|vpiName:divisor
|vpiNetType:36
|vpiRange:
\_range: , line:246
|vpiLeftRange:
\_constant: , line:246
|vpiDecompile:31
|INT:31
|vpiRightRange:
\_constant: , line:246
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (start)
|vpiName:start
|vpiDirection:1
|vpiExpr:
\_logic_net: (start), line:244
|vpiName:start
|vpiNetType:36
|vpiInterface:
\_interface: work@unsigned_division_interface (div), file:third_party/cores/taiga/core/div_algorithms/div_algorithm.sv, line:47
|vpiDefName:work@unsigned_division_interface
|vpiName:div
|vpiModport:
\_modport: (divider)
|vpiModport:
\_modport: (requester)
|vpiName:requester
|vpiIODecl:
\_io_decl: (remainder)
|vpiName:remainder
|vpiDirection:1
|vpiExpr:
\_logic_net: (remainder), line:247
|vpiIODecl:
\_io_decl: (quotient)
|vpiName:quotient
|vpiDirection:1
|vpiExpr:
\_logic_net: (quotient), line:248
|vpiIODecl:
\_io_decl: (done)
|vpiName:done
|vpiDirection:1
|vpiExpr:
\_logic_net: (done), line:249
|vpiIODecl:
\_io_decl: (divisor_is_zero)
|vpiName:divisor_is_zero
|vpiDirection:1
|vpiExpr:
\_logic_net: (divisor_is_zero), line:250
|vpiIODecl:
\_io_decl: (dividend)
|vpiName:dividend
|vpiDirection:2
|vpiExpr:
\_logic_net: (dividend), line:245
|vpiIODecl:
\_io_decl: (divisor)
|vpiName:divisor
|vpiDirection:2
|vpiExpr:
\_logic_net: (divisor), line:246
|vpiIODecl:
\_io_decl: (start)
|vpiName:start
|vpiDirection:2
|vpiExpr:
\_logic_net: (start), line:244
|vpiInterface:
\_interface: work@unsigned_division_interface (div), file:third_party/cores/taiga/core/div_algorithms/div_algorithm.sv, line:47
|vpiModule:
\_module: work@clz (clz_r), file:third_party/cores/taiga/core/div_algorithms/div_quick_clz_mk2.sv, line:58, parent:div_block
|vpiDefName:work@clz
|vpiName:clz_r
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.clz_r
|vpiPort:
\_port: (clz_input), line:25, parent:clz_r
|vpiName:clz_input
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (div.remainder), line:58
|vpiName:div.remainder
|vpiActual:
\_logic_net: (remainder), line:247
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (clz_input), line:25, parent:clz_r
|vpiName:clz_input
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.clz_r.clz_input
|vpiNetType:36
|vpiRange:
\_range: , line:25
|vpiLeftRange:
\_constant: , line:25
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:25
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiPort:
\_port: (clz), line:26, parent:clz_r
|vpiName:clz
|vpiDirection:2
|vpiHighConn:
\_ref_obj: (R_CLZ), line:58
|vpiName:R_CLZ
|vpiActual:
\_logic_net: (R_CLZ), line:50, parent:div_block
|vpiName:R_CLZ
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.R_CLZ
|vpiNetType:36
|vpiRange:
\_range: , line:50
|vpiLeftRange:
\_constant: , line:50
|vpiDecompile:-1
|INT:-1
|vpiRightRange:
\_constant: , line:50
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (clz), line:26, parent:clz_r
|vpiName:clz
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.clz_r.clz
|vpiNetType:36
|vpiRange:
\_range: , line:26
|vpiLeftRange:
\_constant: , line:26
|vpiConstType:7
|vpiDecompile:4
|vpiSize:32
|INT:4
|vpiRightRange:
\_constant: , line:26
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (clz_input), line:25, parent:clz_r
|vpiNet:
\_logic_net: (clz), line:26, parent:clz_r
|vpiNet:
\_logic_net: (sub_clz), line:30, parent:clz_r
|vpiName:sub_clz
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.clz_r.sub_clz
|vpiNetType:36
|vpiRange:
\_range: , line:30
|vpiLeftRange:
\_constant: , line:30
|vpiConstType:7
|vpiDecompile:7
|vpiSize:32
|INT:7
|vpiRightRange:
\_constant: , line:30
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiInstance:
\_module: work@div_quick_clz_mk2 (div_block), file:third_party/cores/taiga/core/div_algorithms/div_algorithm.sv, line:47, parent:divider_block
|vpiArrayNet:
\_array_net: (low_order_clz), line:29, parent:clz_r
|vpiName:low_order_clz
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.clz_r.low_order_clz
|vpiSize:8
|vpiNet:
\_logic_net: , parent:low_order_clz
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.clz_r.low_order_clz
|vpiNetType:36
|vpiRange:
\_range: , line:29
|vpiLeftRange:
\_constant: , line:29
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:29
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiRange:
\_range: , line:29
|vpiLeftRange:
\_constant: , line:29
|vpiConstType:7
|vpiDecompile:7
|vpiSize:32
|INT:7
|vpiRightRange:
\_constant: , line:29
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiArrayNet:
\_array_net: (upper_lower), line:32, parent:clz_r
|vpiName:upper_lower
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.clz_r.upper_lower
|vpiSize:4
|vpiNet:
\_logic_net: , parent:upper_lower
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.clz_r.upper_lower
|vpiNetType:36
|vpiRange:
\_range: , line:32
|vpiLeftRange:
\_constant: , line:32
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:32
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiRange:
\_range: , line:32
|vpiLeftRange:
\_constant: , line:32
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiRightRange:
\_constant: , line:32
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiModule:
\_module: work@clz (clz_b), file:third_party/cores/taiga/core/div_algorithms/div_quick_clz_mk2.sv, line:59, parent:div_block
|vpiDefName:work@clz
|vpiName:clz_b
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.clz_b
|vpiPort:
\_port: (clz_input), line:25, parent:clz_b
|vpiName:clz_input
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (div.divisor), line:59
|vpiName:div.divisor
|vpiActual:
\_logic_net: (divisor), line:246
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (clz_input), line:25, parent:clz_b
|vpiName:clz_input
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.clz_b.clz_input
|vpiNetType:36
|vpiRange:
\_range: , line:25
|vpiLeftRange:
\_constant: , line:25
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:25
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiPort:
\_port: (clz), line:26, parent:clz_b
|vpiName:clz
|vpiDirection:2
|vpiHighConn:
\_ref_obj: (B_CLZ), line:59
|vpiName:B_CLZ
|vpiActual:
\_logic_net: (B_CLZ), line:51, parent:div_block
|vpiName:B_CLZ
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.B_CLZ
|vpiNetType:36
|vpiRange:
\_range: , line:51
|vpiLeftRange:
\_constant: , line:51
|vpiDecompile:-1
|INT:-1
|vpiRightRange:
\_constant: , line:51
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (clz), line:26, parent:clz_b
|vpiName:clz
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.clz_b.clz
|vpiNetType:36
|vpiRange:
\_range: , line:26
|vpiLeftRange:
\_constant: , line:26
|vpiConstType:7
|vpiDecompile:4
|vpiSize:32
|INT:4
|vpiRightRange:
\_constant: , line:26
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (clz_input), line:25, parent:clz_b
|vpiNet:
\_logic_net: (clz), line:26, parent:clz_b
|vpiNet:
\_logic_net: (sub_clz), line:30, parent:clz_b
|vpiName:sub_clz
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.clz_b.sub_clz
|vpiNetType:36
|vpiRange:
\_range: , line:30
|vpiLeftRange:
\_constant: , line:30
|vpiConstType:7
|vpiDecompile:7
|vpiSize:32
|INT:7
|vpiRightRange:
\_constant: , line:30
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiInstance:
\_module: work@div_quick_clz_mk2 (div_block), file:third_party/cores/taiga/core/div_algorithms/div_algorithm.sv, line:47, parent:divider_block
|vpiArrayNet:
\_array_net: (low_order_clz), line:29, parent:clz_b
|vpiName:low_order_clz
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.clz_b.low_order_clz
|vpiSize:8
|vpiNet:
\_logic_net: , parent:low_order_clz
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.clz_b.low_order_clz
|vpiNetType:36
|vpiRange:
\_range: , line:29
|vpiLeftRange:
\_constant: , line:29
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:29
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiRange:
\_range: , line:29
|vpiLeftRange:
\_constant: , line:29
|vpiConstType:7
|vpiDecompile:7
|vpiSize:32
|INT:7
|vpiRightRange:
\_constant: , line:29
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiArrayNet:
\_array_net: (upper_lower), line:32, parent:clz_b
|vpiName:upper_lower
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.clz_b.upper_lower
|vpiSize:4
|vpiNet:
\_logic_net: , parent:upper_lower
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.clz_b.upper_lower
|vpiNetType:36
|vpiRange:
\_range: , line:32
|vpiLeftRange:
\_constant: , line:32
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:32
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiRange:
\_range: , line:32
|vpiLeftRange:
\_constant: , line:32
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiRightRange:
\_constant: , line:32
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (clk), line:27, parent:div_block
|vpiNet:
\_logic_net: (rst), line:28, parent:div_block
|vpiNet:
\_logic_net: (running), line:32, parent:div_block
|vpiName:running
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.running
|vpiNetType:36
|vpiNet:
\_logic_net: (terminate), line:33, parent:div_block
|vpiName:terminate
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.terminate
|vpiNetType:36
|vpiNet:
\_logic_net: (A0), line:35, parent:div_block
|vpiName:A0
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.A0
|vpiNetType:36
|vpiRange:
\_range: , line:35
|vpiLeftRange:
\_ref_obj: (div.DATA_WIDTH), line:35
|vpiName:div.DATA_WIDTH
|vpiRightRange:
\_constant: , line:35
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (A1), line:36, parent:div_block
|vpiName:A1
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.A1
|vpiNetType:36
|vpiRange:
\_range: , line:36
|vpiLeftRange:
\_ref_obj: (div.DATA_WIDTH), line:36
|vpiName:div.DATA_WIDTH
|vpiRightRange:
\_constant: , line:36
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (A2), line:37, parent:div_block
|vpiName:A2
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.A2
|vpiNetType:36
|vpiRange:
\_range: , line:37
|vpiLeftRange:
\_operation: , line:37
|vpiOpType:11
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:37
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:37
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:37
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (new_R), line:39, parent:div_block
|vpiName:new_R
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.new_R
|vpiNetType:36
|vpiRange:
\_range: , line:39
|vpiLeftRange:
\_operation: , line:39
|vpiOpType:11
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:39
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:39
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:39
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (new_Q_bit), line:40, parent:div_block
|vpiName:new_Q_bit
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.new_Q_bit
|vpiNetType:36
|vpiRange:
\_range: , line:40
|vpiLeftRange:
\_operation: , line:40
|vpiOpType:11
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:40
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:40
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:40
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (new_R2), line:41, parent:div_block
|vpiName:new_R2
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.new_R2
|vpiNetType:36
|vpiRange:
\_range: , line:41
|vpiLeftRange:
\_operation: , line:41
|vpiOpType:11
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:41
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:41
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:41
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (Q_bit1), line:43, parent:div_block
|vpiName:Q_bit1
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.Q_bit1
|vpiNetType:36
|vpiRange:
\_range: , line:43
|vpiLeftRange:
\_operation: , line:43
|vpiOpType:11
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:43
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:43
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:43
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (Q_bit2), line:44, parent:div_block
|vpiName:Q_bit2
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.Q_bit2
|vpiNetType:36
|vpiRange:
\_range: , line:44
|vpiLeftRange:
\_operation: , line:44
|vpiOpType:11
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:44
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:44
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:44
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (B1), line:46, parent:div_block
|vpiName:B1
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.B1
|vpiNetType:36
|vpiRange:
\_range: , line:46
|vpiLeftRange:
\_operation: , line:46
|vpiOpType:11
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:46
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:46
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:46
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (B2), line:47, parent:div_block
|vpiName:B2
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.B2
|vpiNetType:36
|vpiRange:
\_range: , line:47
|vpiLeftRange:
\_operation: , line:47
|vpiOpType:11
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:47
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:47
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:47
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (R_CLZ), line:50, parent:div_block
|vpiNet:
\_logic_net: (B_CLZ), line:51, parent:div_block
|vpiNet:
\_logic_net: (B_CLZ_r), line:52, parent:div_block
|vpiName:B_CLZ_r
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.B_CLZ_r
|vpiNetType:36
|vpiRange:
\_range: , line:52
|vpiLeftRange:
\_constant: , line:52
|vpiDecompile:-1
|INT:-1
|vpiRightRange:
\_constant: , line:52
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (CLZ_delta), line:53, parent:div_block
|vpiName:CLZ_delta
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.CLZ_delta
|vpiNetType:36
|vpiRange:
\_range: , line:53
|vpiLeftRange:
\_constant: , line:53
|vpiDecompile:-1
|INT:-1
|vpiRightRange:
\_constant: , line:53
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (shiftedB), line:55, parent:div_block
|vpiName:shiftedB
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.shiftedB
|vpiNetType:36
|vpiRange:
\_range: , line:55
|vpiLeftRange:
\_operation: , line:55
|vpiOpType:11
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:55
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:55
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:55
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (div), line:29, parent:div_block
|vpiName:div
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.div
|vpiInstance:
\_module: work@div_algorithm (divider_block), file:third_party/cores/taiga/core/div_unit.sv, line:129, parent:div_unit_block
|vpiParameter:
\_parameter: (CLZ_W), line:49
|vpiName:CLZ_W
|INT:0
|vpiModule:
\_module: work@div_quick_radix_4 (div_block), file:third_party/cores/taiga/core/div_algorithms/div_algorithm.sv, line:48, parent:divider_block
|vpiDefName:work@div_quick_radix_4
|vpiName:div_block
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block
|vpiPort:
\_port: (clk), line:27, parent:div_block
|vpiName:clk
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (clk), line:48
|vpiName:clk
|vpiActual:
\_logic_net: (clk), line:29, parent:divider_block
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (clk), line:27, parent:div_block
|vpiName:clk
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.clk
|vpiNetType:36
|vpiPort:
\_port: (rst), line:28, parent:div_block
|vpiName:rst
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (rst), line:48
|vpiName:rst
|vpiActual:
\_logic_net: (rst), line:30, parent:divider_block
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (rst), line:28, parent:div_block
|vpiName:rst
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.rst
|vpiNetType:36
|vpiPort:
\_port: (div), line:29, parent:div_block
|vpiName:div
|vpiDirection:5
|vpiHighConn:
\_ref_obj: (div), line:48
|vpiName:div
|vpiActual:
\_interface: work@unsigned_division_interface (div), file:third_party/cores/taiga/core/div_unit.sv, line:129
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_modport: (divider)
|vpiName:divider
|vpiIODecl:
\_io_decl: (remainder)
|vpiName:remainder
|vpiDirection:2
|vpiExpr:
\_logic_net: (remainder), line:247
|vpiName:remainder
|vpiNetType:36
|vpiRange:
\_range: , line:247
|vpiLeftRange:
\_constant: , line:247
|vpiDecompile:31
|INT:31
|vpiRightRange:
\_constant: , line:247
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (quotient)
|vpiName:quotient
|vpiDirection:2
|vpiExpr:
\_logic_net: (quotient), line:248
|vpiName:quotient
|vpiNetType:36
|vpiRange:
\_range: , line:248
|vpiLeftRange:
\_constant: , line:248
|vpiDecompile:31
|INT:31
|vpiRightRange:
\_constant: , line:248
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (done)
|vpiName:done
|vpiDirection:2
|vpiExpr:
\_logic_net: (done), line:249
|vpiName:done
|vpiNetType:36
|vpiIODecl:
\_io_decl: (divisor_is_zero)
|vpiName:divisor_is_zero
|vpiDirection:2
|vpiExpr:
\_logic_net: (divisor_is_zero), line:250
|vpiName:divisor_is_zero
|vpiNetType:36
|vpiIODecl:
\_io_decl: (dividend)
|vpiName:dividend
|vpiDirection:1
|vpiExpr:
\_logic_net: (dividend), line:245
|vpiName:dividend
|vpiNetType:36
|vpiRange:
\_range: , line:245
|vpiLeftRange:
\_constant: , line:245
|vpiDecompile:31
|INT:31
|vpiRightRange:
\_constant: , line:245
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (divisor)
|vpiName:divisor
|vpiDirection:1
|vpiExpr:
\_logic_net: (divisor), line:246
|vpiName:divisor
|vpiNetType:36
|vpiRange:
\_range: , line:246
|vpiLeftRange:
\_constant: , line:246
|vpiDecompile:31
|INT:31
|vpiRightRange:
\_constant: , line:246
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (start)
|vpiName:start
|vpiDirection:1
|vpiExpr:
\_logic_net: (start), line:244
|vpiName:start
|vpiNetType:36
|vpiInterface:
\_interface: work@unsigned_division_interface (div), file:third_party/cores/taiga/core/div_algorithms/div_algorithm.sv, line:48
|vpiDefName:work@unsigned_division_interface
|vpiName:div
|vpiModport:
\_modport: (divider)
|vpiModport:
\_modport: (requester)
|vpiName:requester
|vpiIODecl:
\_io_decl: (remainder)
|vpiName:remainder
|vpiDirection:1
|vpiExpr:
\_logic_net: (remainder), line:247
|vpiIODecl:
\_io_decl: (quotient)
|vpiName:quotient
|vpiDirection:1
|vpiExpr:
\_logic_net: (quotient), line:248
|vpiIODecl:
\_io_decl: (done)
|vpiName:done
|vpiDirection:1
|vpiExpr:
\_logic_net: (done), line:249
|vpiIODecl:
\_io_decl: (divisor_is_zero)
|vpiName:divisor_is_zero
|vpiDirection:1
|vpiExpr:
\_logic_net: (divisor_is_zero), line:250
|vpiIODecl:
\_io_decl: (dividend)
|vpiName:dividend
|vpiDirection:2
|vpiExpr:
\_logic_net: (dividend), line:245
|vpiIODecl:
\_io_decl: (divisor)
|vpiName:divisor
|vpiDirection:2
|vpiExpr:
\_logic_net: (divisor), line:246
|vpiIODecl:
\_io_decl: (start)
|vpiName:start
|vpiDirection:2
|vpiExpr:
\_logic_net: (start), line:244
|vpiInterface:
\_interface: work@unsigned_division_interface (div), file:third_party/cores/taiga/core/div_algorithms/div_algorithm.sv, line:48
|vpiModule:
\_module: work@clz (clz_r), file:third_party/cores/taiga/core/div_algorithms/div_quick_radix4.sv, line:69, parent:div_block
|vpiDefName:work@clz
|vpiName:clz_r
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.clz_r
|vpiPort:
\_port: (clz_input), line:25, parent:clz_r
|vpiName:clz_input
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (div.dividend), line:69
|vpiName:div.dividend
|vpiActual:
\_logic_net: (dividend), line:245
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (clz_input), line:25, parent:clz_r
|vpiName:clz_input
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.clz_r.clz_input
|vpiNetType:36
|vpiRange:
\_range: , line:25
|vpiLeftRange:
\_constant: , line:25
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:25
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiPort:
\_port: (clz), line:26, parent:clz_r
|vpiName:clz
|vpiDirection:2
|vpiHighConn:
\_ref_obj: (A_CLZ), line:69
|vpiName:A_CLZ
|vpiActual:
\_logic_net: (A_CLZ), line:54, parent:div_block
|vpiName:A_CLZ
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.A_CLZ
|vpiNetType:36
|vpiRange:
\_range: , line:54
|vpiLeftRange:
\_constant: , line:54
|vpiDecompile:-1
|INT:-1
|vpiRightRange:
\_constant: , line:54
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (clz), line:26, parent:clz_r
|vpiName:clz
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.clz_r.clz
|vpiNetType:36
|vpiRange:
\_range: , line:26
|vpiLeftRange:
\_constant: , line:26
|vpiConstType:7
|vpiDecompile:4
|vpiSize:32
|INT:4
|vpiRightRange:
\_constant: , line:26
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (clz_input), line:25, parent:clz_r
|vpiNet:
\_logic_net: (clz), line:26, parent:clz_r
|vpiNet:
\_logic_net: (sub_clz), line:30, parent:clz_r
|vpiName:sub_clz
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.clz_r.sub_clz
|vpiNetType:36
|vpiRange:
\_range: , line:30
|vpiLeftRange:
\_constant: , line:30
|vpiConstType:7
|vpiDecompile:7
|vpiSize:32
|INT:7
|vpiRightRange:
\_constant: , line:30
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiInstance:
\_module: work@div_quick_radix_4 (div_block), file:third_party/cores/taiga/core/div_algorithms/div_algorithm.sv, line:48, parent:divider_block
|vpiArrayNet:
\_array_net: (low_order_clz), line:29, parent:clz_r
|vpiName:low_order_clz
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.clz_r.low_order_clz
|vpiSize:8
|vpiNet:
\_logic_net: , parent:low_order_clz
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.clz_r.low_order_clz
|vpiNetType:36
|vpiRange:
\_range: , line:29
|vpiLeftRange:
\_constant: , line:29
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:29
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiRange:
\_range: , line:29
|vpiLeftRange:
\_constant: , line:29
|vpiConstType:7
|vpiDecompile:7
|vpiSize:32
|INT:7
|vpiRightRange:
\_constant: , line:29
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiArrayNet:
\_array_net: (upper_lower), line:32, parent:clz_r
|vpiName:upper_lower
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.clz_r.upper_lower
|vpiSize:4
|vpiNet:
\_logic_net: , parent:upper_lower
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.clz_r.upper_lower
|vpiNetType:36
|vpiRange:
\_range: , line:32
|vpiLeftRange:
\_constant: , line:32
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:32
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiRange:
\_range: , line:32
|vpiLeftRange:
\_constant: , line:32
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiRightRange:
\_constant: , line:32
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiModule:
\_module: work@clz (clz_b), file:third_party/cores/taiga/core/div_algorithms/div_quick_radix4.sv, line:70, parent:div_block
|vpiDefName:work@clz
|vpiName:clz_b
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.clz_b
|vpiPort:
\_port: (clz_input), line:25, parent:clz_b
|vpiName:clz_input
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (div.divisor), line:70
|vpiName:div.divisor
|vpiActual:
\_logic_net: (divisor), line:246
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (clz_input), line:25, parent:clz_b
|vpiName:clz_input
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.clz_b.clz_input
|vpiNetType:36
|vpiRange:
\_range: , line:25
|vpiLeftRange:
\_constant: , line:25
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:25
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiPort:
\_port: (clz), line:26, parent:clz_b
|vpiName:clz
|vpiDirection:2
|vpiHighConn:
\_ref_obj: (B_CLZ), line:70
|vpiName:B_CLZ
|vpiActual:
\_logic_net: (B_CLZ), line:55, parent:div_block
|vpiName:B_CLZ
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.B_CLZ
|vpiNetType:36
|vpiRange:
\_range: , line:55
|vpiLeftRange:
\_constant: , line:55
|vpiDecompile:-1
|INT:-1
|vpiRightRange:
\_constant: , line:55
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (clz), line:26, parent:clz_b
|vpiName:clz
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.clz_b.clz
|vpiNetType:36
|vpiRange:
\_range: , line:26
|vpiLeftRange:
\_constant: , line:26
|vpiConstType:7
|vpiDecompile:4
|vpiSize:32
|INT:4
|vpiRightRange:
\_constant: , line:26
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (clz_input), line:25, parent:clz_b
|vpiNet:
\_logic_net: (clz), line:26, parent:clz_b
|vpiNet:
\_logic_net: (sub_clz), line:30, parent:clz_b
|vpiName:sub_clz
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.clz_b.sub_clz
|vpiNetType:36
|vpiRange:
\_range: , line:30
|vpiLeftRange:
\_constant: , line:30
|vpiConstType:7
|vpiDecompile:7
|vpiSize:32
|INT:7
|vpiRightRange:
\_constant: , line:30
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiInstance:
\_module: work@div_quick_radix_4 (div_block), file:third_party/cores/taiga/core/div_algorithms/div_algorithm.sv, line:48, parent:divider_block
|vpiArrayNet:
\_array_net: (low_order_clz), line:29, parent:clz_b
|vpiName:low_order_clz
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.clz_b.low_order_clz
|vpiSize:8
|vpiNet:
\_logic_net: , parent:low_order_clz
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.clz_b.low_order_clz
|vpiNetType:36
|vpiRange:
\_range: , line:29
|vpiLeftRange:
\_constant: , line:29
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:29
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiRange:
\_range: , line:29
|vpiLeftRange:
\_constant: , line:29
|vpiConstType:7
|vpiDecompile:7
|vpiSize:32
|INT:7
|vpiRightRange:
\_constant: , line:29
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiArrayNet:
\_array_net: (upper_lower), line:32, parent:clz_b
|vpiName:upper_lower
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.clz_b.upper_lower
|vpiSize:4
|vpiNet:
\_logic_net: , parent:upper_lower
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.clz_b.upper_lower
|vpiNetType:36
|vpiRange:
\_range: , line:32
|vpiLeftRange:
\_constant: , line:32
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:32
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiRange:
\_range: , line:32
|vpiLeftRange:
\_constant: , line:32
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiRightRange:
\_constant: , line:32
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (clk), line:27, parent:div_block
|vpiNet:
\_logic_net: (rst), line:28, parent:div_block
|vpiNet:
\_logic_net: (terminate), line:32, parent:div_block
|vpiName:terminate
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.terminate
|vpiNetType:36
|vpiNet:
\_logic_net: (shift_count), line:33, parent:div_block
|vpiName:shift_count
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.shift_count
|vpiNetType:36
|vpiRange:
\_range: , line:33
|vpiLeftRange:
\_operation: , line:33
|vpiOpType:11
|vpiOperand:
\_operation: , line:33
|vpiOpType:12
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:33
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:33
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiOperand:
\_constant: , line:33
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:33
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (PR), line:35, parent:div_block
|vpiName:PR
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.PR
|vpiNetType:36
|vpiRange:
\_range: , line:35
|vpiLeftRange:
\_operation: , line:35
|vpiOpType:24
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:35
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:35
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:35
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (new_PR_sign), line:36, parent:div_block
|vpiName:new_PR_sign
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.new_PR_sign
|vpiNetType:36
|vpiRange:
\_range: , line:36
|vpiLeftRange:
\_constant: , line:36
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiRightRange:
\_constant: , line:36
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (new_PR_1), line:37, parent:div_block
|vpiName:new_PR_1
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.new_PR_1
|vpiNetType:36
|vpiRange:
\_range: , line:37
|vpiLeftRange:
\_operation: , line:37
|vpiOpType:24
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:37
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:37
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiRightRange:
\_constant: , line:37
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (new_PR_2), line:38, parent:div_block
|vpiName:new_PR_2
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.new_PR_2
|vpiNetType:36
|vpiRange:
\_range: , line:38
|vpiLeftRange:
\_operation: , line:38
|vpiOpType:24
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:38
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:38
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiRightRange:
\_constant: , line:38
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (new_PR_3), line:39, parent:div_block
|vpiName:new_PR_3
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.new_PR_3
|vpiNetType:36
|vpiRange:
\_range: , line:39
|vpiLeftRange:
\_operation: , line:39
|vpiOpType:24
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:39
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:39
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiRightRange:
\_constant: , line:39
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (B_1), line:40, parent:div_block
|vpiName:B_1
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.B_1
|vpiNetType:36
|vpiRange:
\_range: , line:40
|vpiLeftRange:
\_operation: , line:40
|vpiOpType:24
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:40
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:40
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:40
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (B_2), line:41, parent:div_block
|vpiName:B_2
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.B_2
|vpiNetType:36
|vpiRange:
\_range: , line:41
|vpiLeftRange:
\_operation: , line:41
|vpiOpType:24
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:41
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:41
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:41
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (B_3), line:42, parent:div_block
|vpiName:B_3
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.B_3
|vpiNetType:36
|vpiRange:
\_range: , line:42
|vpiLeftRange:
\_operation: , line:42
|vpiOpType:24
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:42
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:42
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:42
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (AR_r), line:44, parent:div_block
|vpiName:AR_r
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.AR_r
|vpiNetType:36
|vpiRange:
\_range: , line:44
|vpiLeftRange:
\_operation: , line:44
|vpiOpType:11
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:44
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:44
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:44
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (Q_temp), line:45, parent:div_block
|vpiName:Q_temp
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.Q_temp
|vpiNetType:36
|vpiRange:
\_range: , line:45
|vpiLeftRange:
\_operation: , line:45
|vpiOpType:11
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:45
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:45
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:45
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (shift_num_R), line:46, parent:div_block
|vpiName:shift_num_R
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.shift_num_R
|vpiNetType:36
|vpiRange:
\_range: , line:46
|vpiLeftRange:
\_constant: , line:46
|vpiConstType:7
|vpiDecompile:5
|vpiSize:32
|INT:5
|vpiRightRange:
\_constant: , line:46
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (shift_num_R_normalized), line:47, parent:div_block
|vpiName:shift_num_R_normalized
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.shift_num_R_normalized
|vpiNetType:36
|vpiRange:
\_range: , line:47
|vpiLeftRange:
\_constant: , line:47
|vpiConstType:7
|vpiDecompile:6
|vpiSize:32
|INT:6
|vpiRightRange:
\_constant: , line:47
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (shift_num_Q), line:48, parent:div_block
|vpiName:shift_num_Q
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.shift_num_Q
|vpiNetType:36
|vpiRange:
\_range: , line:48
|vpiLeftRange:
\_constant: , line:48
|vpiConstType:7
|vpiDecompile:5
|vpiSize:32
|INT:5
|vpiRightRange:
\_constant: , line:48
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (combined), line:49, parent:div_block
|vpiName:combined
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.combined
|vpiNetType:36
|vpiRange:
\_range: , line:49
|vpiLeftRange:
\_operation: , line:49
|vpiOpType:24
|vpiOperand:
\_operation: , line:49
|vpiOpType:25
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:49
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:49
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiOperand:
\_constant: , line:49
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:49
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (combined_normalized), line:50, parent:div_block
|vpiName:combined_normalized
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.combined_normalized
|vpiNetType:36
|vpiRange:
\_range: , line:50
|vpiLeftRange:
\_operation: , line:50
|vpiOpType:24
|vpiOperand:
\_operation: , line:50
|vpiOpType:25
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:50
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:50
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiOperand:
\_constant: , line:50
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:50
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (terminate_early), line:51, parent:div_block
|vpiName:terminate_early
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.terminate_early
|vpiNetType:36
|vpiNet:
\_logic_net: (A_CLZ), line:54, parent:div_block
|vpiNet:
\_logic_net: (B_CLZ), line:55, parent:div_block
|vpiNet:
\_logic_net: (A_CLZ_r), line:56, parent:div_block
|vpiName:A_CLZ_r
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.A_CLZ_r
|vpiNetType:36
|vpiRange:
\_range: , line:56
|vpiLeftRange:
\_constant: , line:56
|vpiDecompile:-1
|INT:-1
|vpiRightRange:
\_constant: , line:56
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (B_CLZ_r), line:57, parent:div_block
|vpiName:B_CLZ_r
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.B_CLZ_r
|vpiNetType:36
|vpiRange:
\_range: , line:57
|vpiLeftRange:
\_constant: , line:57
|vpiDecompile:-1
|INT:-1
|vpiRightRange:
\_constant: , line:57
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (CLZ_delta), line:58, parent:div_block
|vpiName:CLZ_delta
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.CLZ_delta
|vpiNetType:36
|vpiRange:
\_range: , line:58
|vpiLeftRange:
\_constant: , line:58
|vpiDecompile:-1
|INT:-1
|vpiRightRange:
\_constant: , line:58
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (firstCycle), line:60, parent:div_block
|vpiName:firstCycle
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.firstCycle
|vpiNetType:36
|vpiNet:
\_logic_net: (greaterDivisor), line:61, parent:div_block
|vpiName:greaterDivisor
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.greaterDivisor
|vpiNetType:36
|vpiNet:
\_logic_net: (A_shifted), line:62, parent:div_block
|vpiName:A_shifted
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.A_shifted
|vpiNetType:36
|vpiRange:
\_range: , line:62
|vpiLeftRange:
\_operation: , line:62
|vpiOpType:11
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:62
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:62
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:62
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (B_shifted), line:63, parent:div_block
|vpiName:B_shifted
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.B_shifted
|vpiNetType:36
|vpiRange:
\_range: , line:63
|vpiLeftRange:
\_operation: , line:63
|vpiOpType:11
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:63
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:63
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:63
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (R_shifted), line:64, parent:div_block
|vpiName:R_shifted
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.R_shifted
|vpiNetType:36
|vpiRange:
\_range: , line:64
|vpiLeftRange:
\_operation: , line:64
|vpiOpType:11
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:64
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:64
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:64
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (B_shifted_r), line:65, parent:div_block
|vpiName:B_shifted_r
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.B_shifted_r
|vpiNetType:36
|vpiRange:
\_range: , line:65
|vpiLeftRange:
\_operation: , line:65
|vpiOpType:11
|vpiOperand:
\_ref_obj: (div.DATA_WIDTH), line:65
|vpiName:div.DATA_WIDTH
|vpiOperand:
\_constant: , line:65
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:65
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (div), line:29, parent:div_block
|vpiName:div
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div_block.div
|vpiInstance:
\_module: work@div_algorithm (divider_block), file:third_party/cores/taiga/core/div_unit.sv, line:129, parent:div_unit_block
|vpiParameter:
\_parameter: (CLZ_W), line:53
|vpiName:CLZ_W
|INT:0
|vpiNet:
\_logic_net: (clk), line:29, parent:divider_block
|vpiNet:
\_logic_net: (rst), line:30, parent:divider_block
|vpiNet:
\_logic_net: (div), line:31, parent:divider_block
|vpiName:div
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.divider_block.div
|vpiInstance:
\_module: work@div_unit (div_unit_block), file:third_party/cores/taiga/core/taiga.sv, line:199
|vpiParameter:
\_parameter: (ALU_UNIT_WB_ID), line:190
|vpiName:ALU_UNIT_WB_ID
|INT:32
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (BRANCH_PREDICTOR_WAYS), line:159
|vpiName:BRANCH_PREDICTOR_WAYS
|INT:9
|vpiParameter:
\_parameter: (BRANCH_TABLE_ENTRIES), line:160
|vpiName:BRANCH_TABLE_ENTRIES
|INT:4
|vpiParameter:
\_parameter: (BRANCH_UNIT_ID), line:195
|vpiName:BRANCH_UNIT_ID
|INT:8
|vpiParameter:
\_parameter: (BUS_ADDR_H), line:107
|vpiName:BUS_ADDR_H
|INT:1
|vpiParameter:
\_parameter: (BUS_ADDR_L), line:106
|vpiName:BUS_ADDR_L
|INT:0
|vpiParameter:
\_parameter: (BUS_BIT_CHECK), line:108
|vpiName:BUS_BIT_CHECK
|INT:1
|vpiParameter:
\_parameter: (BUS_TYPE), line:89
|vpiName:BUS_TYPE
|INT:5
|vpiParameter:
\_parameter: (COUNTER_W), line:42
|vpiName:COUNTER_W
|INT:33
|vpiParameter:
\_parameter: (CPU_ID), line:38
|vpiName:CPU_ID
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_ADDR_WIDTH), line:113
|vpiName:C_M_AXI_ADDR_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_DATA_WIDTH), line:114
|vpiName:C_M_AXI_DATA_WIDTH
|INT:1
|vpiParameter:
\_parameter: (DCACHE_LINES), line:133
|vpiName:DCACHE_LINES
|INT:-2146435073
|vpiParameter:
\_parameter: (DCACHE_LINE_ADDR_W), line:135
|vpiName:DCACHE_LINE_ADDR_W
|INT:1073741824
|vpiParameter:
\_parameter: (DCACHE_LINE_W), line:136
|vpiName:DCACHE_LINE_W
|INT:1342177279
|vpiParameter:
\_parameter: (DCACHE_SUB_LINE_ADDR_W), line:137
|vpiName:DCACHE_SUB_LINE_ADDR_W
|INT:4
|vpiParameter:
\_parameter: (DCACHE_TAG_W), line:138
|vpiName:DCACHE_TAG_W
|INT:1610612736
|vpiParameter:
\_parameter: (DCACHE_WAYS), line:134
|vpiName:DCACHE_WAYS
|INT:4
|vpiParameter:
\_parameter: (DIV_ALGORITHM), line:67
|vpiName:DIV_ALGORITHM
|INT:0
|vpiParameter:
\_parameter: (DIV_UNIT_WB_ID), line:192
|vpiName:DIV_UNIT_WB_ID
|INT:2
|vpiParameter:
\_parameter: (DTLB_DEPTH), line:152
|vpiName:DTLB_DEPTH
|INT:512
|vpiParameter:
\_parameter: (DTLB_WAYS), line:151
|vpiName:DTLB_WAYS
|INT:32
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (ENABLE_M_MODE), line:34
|vpiName:ENABLE_M_MODE
|INT:1
|vpiParameter:
\_parameter: (ENABLE_S_MODE), line:36
|vpiName:ENABLE_S_MODE
|INT:0
|vpiParameter:
\_parameter: (ENABLE_TRACE_INTERFACE), line:172
|vpiName:ENABLE_TRACE_INTERFACE
|INT:2
|vpiParameter:
\_parameter: (FETCH_BUFFER_DEPTH), line:168
|vpiName:FETCH_BUFFER_DEPTH
|INT:512
|vpiParameter:
\_parameter: (FPGA_VENDOR), line:27
|vpiName:FPGA_VENDOR
|STRING:"xilinx"
|vpiParameter:
\_parameter: (GC_UNIT_ID), line:196
|vpiName:GC_UNIT_ID
|INT:4
|vpiParameter:
\_parameter: (ICACHE_LINES), line:121
|vpiName:ICACHE_LINES
|INT:2
|vpiParameter:
\_parameter: (ICACHE_LINE_ADDR_W), line:123
|vpiName:ICACHE_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_LINE_W), line:124
|vpiName:ICACHE_LINE_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_SUB_LINE_ADDR_W), line:125
|vpiName:ICACHE_SUB_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_TAG_W), line:126
|vpiName:ICACHE_TAG_W
|INT:-2147483648
|vpiParameter:
\_parameter: (ICACHE_WAYS), line:122
|vpiName:ICACHE_WAYS
|INT:1
|vpiParameter:
\_parameter: (ITLB_DEPTH), line:146
|vpiName:ITLB_DEPTH
|INT:32
|vpiParameter:
\_parameter: (ITLB_WAYS), line:145
|vpiName:ITLB_WAYS
|INT:4
|vpiParameter:
\_parameter: (L1_CONNECTIONS), line:177
|vpiName:L1_CONNECTIONS
|INT:9
|vpiParameter:
\_parameter: (L1_DCACHE_ID), line:178
|vpiName:L1_DCACHE_ID
|INT:4
|vpiParameter:
\_parameter: (L1_DMMU_ID), line:179
|vpiName:L1_DMMU_ID
|INT:2
|vpiParameter:
\_parameter: (L1_ICACHE_ID), line:180
|vpiName:L1_ICACHE_ID
|INT:19
|vpiParameter:
\_parameter: (L1_IMMU_ID), line:181
|vpiName:L1_IMMU_ID
|INT:0
|vpiParameter:
\_parameter: (LS_UNIT_WB_ID), line:191
|vpiName:LS_UNIT_WB_ID
|INT:1
|vpiParameter:
\_parameter: (MAX_INFLIGHT_COUNT), line:167
|vpiName:MAX_INFLIGHT_COUNT
|INT:19
|vpiParameter:
\_parameter: (MEMORY_ADDR_H), line:103
|vpiName:MEMORY_ADDR_H
|INT:12
|vpiParameter:
\_parameter: (MEMORY_ADDR_L), line:102
|vpiName:MEMORY_ADDR_L
|INT:11
|vpiParameter:
\_parameter: (MEMORY_BIT_CHECK), line:104
|vpiName:MEMORY_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (MUL_UNIT_WB_ID), line:193
|vpiName:MUL_UNIT_WB_ID
|INT:512
|vpiParameter:
\_parameter: (NUM_UNITS), line:188
|vpiName:NUM_UNITS
|INT:2
|vpiParameter:
\_parameter: (NUM_WB_UNITS), line:186
|vpiName:NUM_WB_UNITS
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (RAS_DEPTH), line:161
|vpiName:RAS_DEPTH
|INT:2
|vpiParameter:
\_parameter: (RESET_VEC), line:39
|vpiName:RESET_VEC
|INT:-2147483648
|vpiParameter:
\_parameter: (SCRATCH_ADDR_H), line:99
|vpiName:SCRATCH_ADDR_H
|INT:9
|vpiParameter:
\_parameter: (SCRATCH_ADDR_L), line:98
|vpiName:SCRATCH_ADDR_L
|INT:8
|vpiParameter:
\_parameter: (SCRATCH_BIT_CHECK), line:100
|vpiName:SCRATCH_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (USE_AMO), line:70
|vpiName:USE_AMO
|INT:1
|vpiParameter:
\_parameter: (USE_BRANCH_PREDICTOR), line:158
|vpiName:USE_BRANCH_PREDICTOR
|INT:2
|vpiParameter:
\_parameter: (USE_BUS), line:88
|vpiName:USE_BUS
|INT:4
|vpiParameter:
\_parameter: (USE_DCACHE), line:92
|vpiName:USE_DCACHE
|INT:6
|vpiParameter:
\_parameter: (USE_DIV), line:49
|vpiName:USE_DIV
|INT:1
|vpiParameter:
\_parameter: (USE_DTAG_INVALIDATIONS), line:140
|vpiName:USE_DTAG_INVALIDATIONS
|INT:1879048191
|vpiParameter:
\_parameter: (USE_D_SCRATCH_MEM), line:79
|vpiName:USE_D_SCRATCH_MEM
|INT:3
|vpiParameter:
\_parameter: (USE_ICACHE), line:93
|vpiName:USE_ICACHE
|INT:7
|vpiParameter:
\_parameter: (USE_I_SCRATCH_MEM), line:78
|vpiName:USE_I_SCRATCH_MEM
|INT:2
|vpiParameter:
\_parameter: (USE_MUL), line:48
|vpiName:USE_MUL
|INT:1
|vpiParameter:
\_parameter: (WB_UNITS_WIDTH), line:187
|vpiName:WB_UNITS_WIDTH
|INT:32
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiNet:
\_logic_net: (clk), line:28, parent:div_unit_block
|vpiNet:
\_logic_net: (rst), line:29, parent:div_unit_block
|vpiNet:
\_logic_net: (gc_fetch_flush), line:31, parent:div_unit_block
|vpiNet:
\_logic_net: (div_inputs), line:33, parent:div_unit_block
|vpiNet:
\_logic_net: (wb), line:35, parent:div_unit_block
|vpiNet:
\_logic_net: (signed_divop), line:38, parent:div_unit_block
|vpiName:signed_divop
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.signed_divop
|vpiNetType:36
|vpiNet:
\_logic_net: (negate_quotient), line:39, parent:div_unit_block
|vpiName:negate_quotient
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.negate_quotient
|vpiNetType:36
|vpiNet:
\_logic_net: (negate_remainder), line:40, parent:div_unit_block
|vpiName:negate_remainder
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.negate_remainder
|vpiNetType:36
|vpiNet:
\_logic_net: (negate_dividend), line:41, parent:div_unit_block
|vpiName:negate_dividend
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.negate_dividend
|vpiNetType:36
|vpiNet:
\_logic_net: (negate_divisor), line:42, parent:div_unit_block
|vpiName:negate_divisor
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.negate_divisor
|vpiNetType:36
|vpiNet:
\_logic_net: (unsigned_dividend), line:44, parent:div_unit_block
|vpiName:unsigned_dividend
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.unsigned_dividend
|vpiNetType:36
|vpiRange:
\_range: , line:44
|vpiLeftRange:
\_constant: , line:44
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:44
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (unsigned_divisor), line:45, parent:div_unit_block
|vpiName:unsigned_divisor
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.unsigned_divisor
|vpiNetType:36
|vpiRange:
\_range: , line:45
|vpiLeftRange:
\_constant: , line:45
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:45
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (remainder_op), line:46, parent:div_unit_block
|vpiName:remainder_op
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.remainder_op
|vpiNetType:36
|vpiNet:
\_logic_net: (in_progress), line:63, parent:div_unit_block
|vpiName:in_progress
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.in_progress
|vpiNetType:36
|vpiNet:
\_logic_net: (div_done), line:64, parent:div_unit_block
|vpiName:div_done
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.div_done
|vpiNetType:36
|vpiNet:
\_logic_net: (negate_result), line:65, parent:div_unit_block
|vpiName:negate_result
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.negate_result
|vpiNetType:36
|vpiNet:
\_logic_net: (issue), line:34, parent:div_unit_block
|vpiName:issue
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.issue
|vpiVariables:
\_struct_var: (fifo_inputs), line:58, parent:div_unit_block
|vpiName:fifo_inputs
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.fifo_inputs
|vpiTypespec:
\_struct_typespec: (div_fifo_inputs_t), line:48
|vpiVariables:
\_struct_var: (div_op), line:59, parent:div_unit_block
|vpiName:div_op
|vpiFullName:work@taiga_wrapper.cpu.genblk5.div_unit_block.div_op
|vpiTypespec:
\_struct_typespec: (div_fifo_inputs_t), line:48
|vpiParameter:
\_parameter: (ALU_UNIT_WB_ID), line:190
|vpiName:ALU_UNIT_WB_ID
|INT:32
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (BRANCH_PREDICTOR_WAYS), line:159
|vpiName:BRANCH_PREDICTOR_WAYS
|INT:9
|vpiParameter:
\_parameter: (BRANCH_TABLE_ENTRIES), line:160
|vpiName:BRANCH_TABLE_ENTRIES
|INT:4
|vpiParameter:
\_parameter: (BRANCH_UNIT_ID), line:195
|vpiName:BRANCH_UNIT_ID
|INT:8
|vpiParameter:
\_parameter: (BUS_ADDR_H), line:107
|vpiName:BUS_ADDR_H
|INT:1
|vpiParameter:
\_parameter: (BUS_ADDR_L), line:106
|vpiName:BUS_ADDR_L
|INT:0
|vpiParameter:
\_parameter: (BUS_BIT_CHECK), line:108
|vpiName:BUS_BIT_CHECK
|INT:1
|vpiParameter:
\_parameter: (BUS_TYPE), line:89
|vpiName:BUS_TYPE
|INT:5
|vpiParameter:
\_parameter: (COUNTER_W), line:42
|vpiName:COUNTER_W
|INT:33
|vpiParameter:
\_parameter: (CPU_ID), line:38
|vpiName:CPU_ID
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_ADDR_WIDTH), line:113
|vpiName:C_M_AXI_ADDR_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_DATA_WIDTH), line:114
|vpiName:C_M_AXI_DATA_WIDTH
|INT:1
|vpiParameter:
\_parameter: (DCACHE_LINES), line:133
|vpiName:DCACHE_LINES
|INT:-2146435073
|vpiParameter:
\_parameter: (DCACHE_LINE_ADDR_W), line:135
|vpiName:DCACHE_LINE_ADDR_W
|INT:1073741824
|vpiParameter:
\_parameter: (DCACHE_LINE_W), line:136
|vpiName:DCACHE_LINE_W
|INT:1342177279
|vpiParameter:
\_parameter: (DCACHE_SUB_LINE_ADDR_W), line:137
|vpiName:DCACHE_SUB_LINE_ADDR_W
|INT:4
|vpiParameter:
\_parameter: (DCACHE_TAG_W), line:138
|vpiName:DCACHE_TAG_W
|INT:1610612736
|vpiParameter:
\_parameter: (DCACHE_WAYS), line:134
|vpiName:DCACHE_WAYS
|INT:4
|vpiParameter:
\_parameter: (DIV_ALGORITHM), line:67
|vpiName:DIV_ALGORITHM
|INT:0
|vpiParameter:
\_parameter: (DIV_UNIT_WB_ID), line:192
|vpiName:DIV_UNIT_WB_ID
|INT:2
|vpiParameter:
\_parameter: (DTLB_DEPTH), line:152
|vpiName:DTLB_DEPTH
|INT:512
|vpiParameter:
\_parameter: (DTLB_WAYS), line:151
|vpiName:DTLB_WAYS
|INT:32
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (ENABLE_M_MODE), line:34
|vpiName:ENABLE_M_MODE
|INT:1
|vpiParameter:
\_parameter: (ENABLE_S_MODE), line:36
|vpiName:ENABLE_S_MODE
|INT:0
|vpiParameter:
\_parameter: (ENABLE_TRACE_INTERFACE), line:172
|vpiName:ENABLE_TRACE_INTERFACE
|INT:2
|vpiParameter:
\_parameter: (FETCH_BUFFER_DEPTH), line:168
|vpiName:FETCH_BUFFER_DEPTH
|INT:512
|vpiParameter:
\_parameter: (FPGA_VENDOR), line:27
|vpiName:FPGA_VENDOR
|STRING:"xilinx"
|vpiParameter:
\_parameter: (GC_UNIT_ID), line:196
|vpiName:GC_UNIT_ID
|INT:4
|vpiParameter:
\_parameter: (ICACHE_LINES), line:121
|vpiName:ICACHE_LINES
|INT:2
|vpiParameter:
\_parameter: (ICACHE_LINE_ADDR_W), line:123
|vpiName:ICACHE_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_LINE_W), line:124
|vpiName:ICACHE_LINE_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_SUB_LINE_ADDR_W), line:125
|vpiName:ICACHE_SUB_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_TAG_W), line:126
|vpiName:ICACHE_TAG_W
|INT:-2147483648
|vpiParameter:
\_parameter: (ICACHE_WAYS), line:122
|vpiName:ICACHE_WAYS
|INT:1
|vpiParameter:
\_parameter: (ITLB_DEPTH), line:146
|vpiName:ITLB_DEPTH
|INT:32
|vpiParameter:
\_parameter: (ITLB_WAYS), line:145
|vpiName:ITLB_WAYS
|INT:4
|vpiParameter:
\_parameter: (L1_CONNECTIONS), line:177
|vpiName:L1_CONNECTIONS
|INT:9
|vpiParameter:
\_parameter: (L1_DCACHE_ID), line:178
|vpiName:L1_DCACHE_ID
|INT:4
|vpiParameter:
\_parameter: (L1_DMMU_ID), line:179
|vpiName:L1_DMMU_ID
|INT:2
|vpiParameter:
\_parameter: (L1_ICACHE_ID), line:180
|vpiName:L1_ICACHE_ID
|INT:19
|vpiParameter:
\_parameter: (L1_IMMU_ID), line:181
|vpiName:L1_IMMU_ID
|INT:0
|vpiParameter:
\_parameter: (LS_UNIT_WB_ID), line:191
|vpiName:LS_UNIT_WB_ID
|INT:1
|vpiParameter:
\_parameter: (MAX_INFLIGHT_COUNT), line:167
|vpiName:MAX_INFLIGHT_COUNT
|INT:19
|vpiParameter:
\_parameter: (MEMORY_ADDR_H), line:103
|vpiName:MEMORY_ADDR_H
|INT:12
|vpiParameter:
\_parameter: (MEMORY_ADDR_L), line:102
|vpiName:MEMORY_ADDR_L
|INT:11
|vpiParameter:
\_parameter: (MEMORY_BIT_CHECK), line:104
|vpiName:MEMORY_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (MUL_UNIT_WB_ID), line:193
|vpiName:MUL_UNIT_WB_ID
|INT:512
|vpiParameter:
\_parameter: (NUM_UNITS), line:188
|vpiName:NUM_UNITS
|INT:2
|vpiParameter:
\_parameter: (NUM_WB_UNITS), line:186
|vpiName:NUM_WB_UNITS
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (RAS_DEPTH), line:161
|vpiName:RAS_DEPTH
|INT:2
|vpiParameter:
\_parameter: (RESET_VEC), line:39
|vpiName:RESET_VEC
|INT:-2147483648
|vpiParameter:
\_parameter: (SCRATCH_ADDR_H), line:99
|vpiName:SCRATCH_ADDR_H
|INT:9
|vpiParameter:
\_parameter: (SCRATCH_ADDR_L), line:98
|vpiName:SCRATCH_ADDR_L
|INT:8
|vpiParameter:
\_parameter: (SCRATCH_BIT_CHECK), line:100
|vpiName:SCRATCH_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (USE_AMO), line:70
|vpiName:USE_AMO
|INT:1
|vpiParameter:
\_parameter: (USE_BRANCH_PREDICTOR), line:158
|vpiName:USE_BRANCH_PREDICTOR
|INT:2
|vpiParameter:
\_parameter: (USE_BUS), line:88
|vpiName:USE_BUS
|INT:4
|vpiParameter:
\_parameter: (USE_DCACHE), line:92
|vpiName:USE_DCACHE
|INT:6
|vpiParameter:
\_parameter: (USE_DIV), line:49
|vpiName:USE_DIV
|INT:1
|vpiParameter:
\_parameter: (USE_DTAG_INVALIDATIONS), line:140
|vpiName:USE_DTAG_INVALIDATIONS
|INT:1879048191
|vpiParameter:
\_parameter: (USE_D_SCRATCH_MEM), line:79
|vpiName:USE_D_SCRATCH_MEM
|INT:3
|vpiParameter:
\_parameter: (USE_ICACHE), line:93
|vpiName:USE_ICACHE
|INT:7
|vpiParameter:
\_parameter: (USE_I_SCRATCH_MEM), line:78
|vpiName:USE_I_SCRATCH_MEM
|INT:2
|vpiParameter:
\_parameter: (USE_MUL), line:48
|vpiName:USE_MUL
|INT:1
|vpiParameter:
\_parameter: (WB_UNITS_WIDTH), line:187
|vpiName:WB_UNITS_WIDTH
|INT:32
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiParameter:
\_parameter: (ALU_UNIT_WB_ID), line:190
|vpiName:ALU_UNIT_WB_ID
|INT:32
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (BRANCH_PREDICTOR_WAYS), line:159
|vpiName:BRANCH_PREDICTOR_WAYS
|INT:9
|vpiParameter:
\_parameter: (BRANCH_TABLE_ENTRIES), line:160
|vpiName:BRANCH_TABLE_ENTRIES
|INT:4
|vpiParameter:
\_parameter: (BRANCH_UNIT_ID), line:195
|vpiName:BRANCH_UNIT_ID
|INT:8
|vpiParameter:
\_parameter: (BUS_ADDR_H), line:107
|vpiName:BUS_ADDR_H
|INT:1
|vpiParameter:
\_parameter: (BUS_ADDR_L), line:106
|vpiName:BUS_ADDR_L
|INT:0
|vpiParameter:
\_parameter: (BUS_BIT_CHECK), line:108
|vpiName:BUS_BIT_CHECK
|INT:1
|vpiParameter:
\_parameter: (BUS_TYPE), line:89
|vpiName:BUS_TYPE
|INT:5
|vpiParameter:
\_parameter: (COUNTER_W), line:42
|vpiName:COUNTER_W
|INT:33
|vpiParameter:
\_parameter: (CPU_ID), line:38
|vpiName:CPU_ID
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_ADDR_WIDTH), line:113
|vpiName:C_M_AXI_ADDR_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_DATA_WIDTH), line:114
|vpiName:C_M_AXI_DATA_WIDTH
|INT:1
|vpiParameter:
\_parameter: (DCACHE_LINES), line:133
|vpiName:DCACHE_LINES
|INT:-2146435073
|vpiParameter:
\_parameter: (DCACHE_LINE_ADDR_W), line:135
|vpiName:DCACHE_LINE_ADDR_W
|INT:1073741824
|vpiParameter:
\_parameter: (DCACHE_LINE_W), line:136
|vpiName:DCACHE_LINE_W
|INT:1342177279
|vpiParameter:
\_parameter: (DCACHE_SUB_LINE_ADDR_W), line:137
|vpiName:DCACHE_SUB_LINE_ADDR_W
|INT:4
|vpiParameter:
\_parameter: (DCACHE_TAG_W), line:138
|vpiName:DCACHE_TAG_W
|INT:1610612736
|vpiParameter:
\_parameter: (DCACHE_WAYS), line:134
|vpiName:DCACHE_WAYS
|INT:4
|vpiParameter:
\_parameter: (DIV_ALGORITHM), line:67
|vpiName:DIV_ALGORITHM
|INT:0
|vpiParameter:
\_parameter: (DIV_UNIT_WB_ID), line:192
|vpiName:DIV_UNIT_WB_ID
|INT:2
|vpiParameter:
\_parameter: (DTLB_DEPTH), line:152
|vpiName:DTLB_DEPTH
|INT:512
|vpiParameter:
\_parameter: (DTLB_WAYS), line:151
|vpiName:DTLB_WAYS
|INT:32
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (ENABLE_M_MODE), line:34
|vpiName:ENABLE_M_MODE
|INT:1
|vpiParameter:
\_parameter: (ENABLE_S_MODE), line:36
|vpiName:ENABLE_S_MODE
|INT:0
|vpiParameter:
\_parameter: (ENABLE_TRACE_INTERFACE), line:172
|vpiName:ENABLE_TRACE_INTERFACE
|INT:2
|vpiParameter:
\_parameter: (FETCH_BUFFER_DEPTH), line:168
|vpiName:FETCH_BUFFER_DEPTH
|INT:512
|vpiParameter:
\_parameter: (FPGA_VENDOR), line:27
|vpiName:FPGA_VENDOR
|STRING:"xilinx"
|vpiParameter:
\_parameter: (GC_UNIT_ID), line:196
|vpiName:GC_UNIT_ID
|INT:4
|vpiParameter:
\_parameter: (ICACHE_LINES), line:121
|vpiName:ICACHE_LINES
|INT:2
|vpiParameter:
\_parameter: (ICACHE_LINE_ADDR_W), line:123
|vpiName:ICACHE_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_LINE_W), line:124
|vpiName:ICACHE_LINE_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_SUB_LINE_ADDR_W), line:125
|vpiName:ICACHE_SUB_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_TAG_W), line:126
|vpiName:ICACHE_TAG_W
|INT:-2147483648
|vpiParameter:
\_parameter: (ICACHE_WAYS), line:122
|vpiName:ICACHE_WAYS
|INT:1
|vpiParameter:
\_parameter: (ITLB_DEPTH), line:146
|vpiName:ITLB_DEPTH
|INT:32
|vpiParameter:
\_parameter: (ITLB_WAYS), line:145
|vpiName:ITLB_WAYS
|INT:4
|vpiParameter:
\_parameter: (L1_CONNECTIONS), line:177
|vpiName:L1_CONNECTIONS
|INT:9
|vpiParameter:
\_parameter: (L1_DCACHE_ID), line:178
|vpiName:L1_DCACHE_ID
|INT:4
|vpiParameter:
\_parameter: (L1_DMMU_ID), line:179
|vpiName:L1_DMMU_ID
|INT:2
|vpiParameter:
\_parameter: (L1_ICACHE_ID), line:180
|vpiName:L1_ICACHE_ID
|INT:19
|vpiParameter:
\_parameter: (L1_IMMU_ID), line:181
|vpiName:L1_IMMU_ID
|INT:0
|vpiParameter:
\_parameter: (LS_UNIT_WB_ID), line:191
|vpiName:LS_UNIT_WB_ID
|INT:1
|vpiParameter:
\_parameter: (MAX_INFLIGHT_COUNT), line:167
|vpiName:MAX_INFLIGHT_COUNT
|INT:19
|vpiParameter:
\_parameter: (MEMORY_ADDR_H), line:103
|vpiName:MEMORY_ADDR_H
|INT:12
|vpiParameter:
\_parameter: (MEMORY_ADDR_L), line:102
|vpiName:MEMORY_ADDR_L
|INT:11
|vpiParameter:
\_parameter: (MEMORY_BIT_CHECK), line:104
|vpiName:MEMORY_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (MUL_UNIT_WB_ID), line:193
|vpiName:MUL_UNIT_WB_ID
|INT:512
|vpiParameter:
\_parameter: (NUM_UNITS), line:188
|vpiName:NUM_UNITS
|INT:2
|vpiParameter:
\_parameter: (NUM_WB_UNITS), line:186
|vpiName:NUM_WB_UNITS
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (RAS_DEPTH), line:161
|vpiName:RAS_DEPTH
|INT:2
|vpiParameter:
\_parameter: (RESET_VEC), line:39
|vpiName:RESET_VEC
|INT:-2147483648
|vpiParameter:
\_parameter: (SCRATCH_ADDR_H), line:99
|vpiName:SCRATCH_ADDR_H
|INT:9
|vpiParameter:
\_parameter: (SCRATCH_ADDR_L), line:98
|vpiName:SCRATCH_ADDR_L
|INT:8
|vpiParameter:
\_parameter: (SCRATCH_BIT_CHECK), line:100
|vpiName:SCRATCH_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (USE_AMO), line:70
|vpiName:USE_AMO
|INT:1
|vpiParameter:
\_parameter: (USE_BRANCH_PREDICTOR), line:158
|vpiName:USE_BRANCH_PREDICTOR
|INT:2
|vpiParameter:
\_parameter: (USE_BUS), line:88
|vpiName:USE_BUS
|INT:4
|vpiParameter:
\_parameter: (USE_DCACHE), line:92
|vpiName:USE_DCACHE
|INT:6
|vpiParameter:
\_parameter: (USE_DIV), line:49
|vpiName:USE_DIV
|INT:1
|vpiParameter:
\_parameter: (USE_DTAG_INVALIDATIONS), line:140
|vpiName:USE_DTAG_INVALIDATIONS
|INT:1879048191
|vpiParameter:
\_parameter: (USE_D_SCRATCH_MEM), line:79
|vpiName:USE_D_SCRATCH_MEM
|INT:3
|vpiParameter:
\_parameter: (USE_ICACHE), line:93
|vpiName:USE_ICACHE
|INT:7
|vpiParameter:
\_parameter: (USE_I_SCRATCH_MEM), line:78
|vpiName:USE_I_SCRATCH_MEM
|INT:2
|vpiParameter:
\_parameter: (USE_MUL), line:48
|vpiName:USE_MUL
|INT:1
|vpiParameter:
\_parameter: (WB_UNITS_WIDTH), line:187
|vpiName:WB_UNITS_WIDTH
|INT:32
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiGenScopeArray:
\_gen_scope_array: (genblk6), line:223, parent:cpu
|vpiName:genblk6
|vpiFullName:work@taiga_wrapper.cpu.genblk6
|vpiGenScope:
\_gen_scope: , parent:genblk6
|vpiFullName:work@taiga_wrapper.cpu.genblk6
|vpiProcess:
\_always: , line:224
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:224
|vpiCondition:
\_operation: , line:224
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:224
|vpiName:clk
|vpiFullName:work@taiga_wrapper.cpu.genblk6.clk
|vpiStmt:
\_begin: , line:224
|vpiFullName:work@taiga_wrapper.cpu.genblk6
|vpiStmt:
\_assignment: , line:225
|vpiOpType:82
|vpiLhs:
\_ref_obj: (tr.events.operand_stall), line:225
|vpiName:tr.events.operand_stall
|vpiFullName:work@taiga_wrapper.cpu.genblk6.tr.events.operand_stall
|vpiRhs:
\_ref_obj: (tr_operand_stall), line:225
|vpiName:tr_operand_stall
|vpiFullName:work@taiga_wrapper.cpu.genblk6.tr_operand_stall
|vpiStmt:
\_assignment: , line:226
|vpiOpType:82
|vpiLhs:
\_ref_obj: (tr.events.unit_stall), line:226
|vpiName:tr.events.unit_stall
|vpiFullName:work@taiga_wrapper.cpu.genblk6.tr.events.unit_stall
|vpiRhs:
\_ref_obj: (tr_unit_stall), line:226
|vpiName:tr_unit_stall
|vpiFullName:work@taiga_wrapper.cpu.genblk6.tr_unit_stall
|vpiStmt:
\_assignment: , line:227
|vpiOpType:82
|vpiLhs:
\_ref_obj: (tr.events.no_id_stall), line:227
|vpiName:tr.events.no_id_stall
|vpiFullName:work@taiga_wrapper.cpu.genblk6.tr.events.no_id_stall
|vpiRhs:
\_ref_obj: (tr_no_id_stall), line:227
|vpiName:tr_no_id_stall
|vpiFullName:work@taiga_wrapper.cpu.genblk6.tr_no_id_stall
|vpiStmt:
\_assignment: , line:228
|vpiOpType:82
|vpiLhs:
\_ref_obj: (tr.events.no_instruction_stall), line:228
|vpiName:tr.events.no_instruction_stall
|vpiFullName:work@taiga_wrapper.cpu.genblk6.tr.events.no_instruction_stall
|vpiRhs:
\_ref_obj: (tr_no_instruction_stall), line:228
|vpiName:tr_no_instruction_stall
|vpiFullName:work@taiga_wrapper.cpu.genblk6.tr_no_instruction_stall
|vpiStmt:
\_assignment: , line:229
|vpiOpType:82
|vpiLhs:
\_ref_obj: (tr.events.other_stall), line:229
|vpiName:tr.events.other_stall
|vpiFullName:work@taiga_wrapper.cpu.genblk6.tr.events.other_stall
|vpiRhs:
\_ref_obj: (tr_other_stall), line:229
|vpiName:tr_other_stall
|vpiFullName:work@taiga_wrapper.cpu.genblk6.tr_other_stall
|vpiStmt:
\_assignment: , line:230
|vpiOpType:82
|vpiLhs:
\_ref_obj: (tr.events.instruction_issued_dec), line:230
|vpiName:tr.events.instruction_issued_dec
|vpiFullName:work@taiga_wrapper.cpu.genblk6.tr.events.instruction_issued_dec
|vpiRhs:
\_ref_obj: (tr_instruction_issued_dec), line:230
|vpiName:tr_instruction_issued_dec
|vpiFullName:work@taiga_wrapper.cpu.genblk6.tr_instruction_issued_dec
|vpiStmt:
\_assignment: , line:231
|vpiOpType:82
|vpiLhs:
\_ref_obj: (tr.events.branch_operand_stall), line:231
|vpiName:tr.events.branch_operand_stall
|vpiFullName:work@taiga_wrapper.cpu.genblk6.tr.events.branch_operand_stall
|vpiRhs:
\_ref_obj: (tr_branch_operand_stall), line:231
|vpiName:tr_branch_operand_stall
|vpiFullName:work@taiga_wrapper.cpu.genblk6.tr_branch_operand_stall
|vpiStmt:
\_assignment: , line:232
|vpiOpType:82
|vpiLhs:
\_ref_obj: (tr.events.alu_operand_stall), line:232
|vpiName:tr.events.alu_operand_stall
|vpiFullName:work@taiga_wrapper.cpu.genblk6.tr.events.alu_operand_stall
|vpiRhs:
\_ref_obj: (tr_alu_operand_stall), line:232
|vpiName:tr_alu_operand_stall
|vpiFullName:work@taiga_wrapper.cpu.genblk6.tr_alu_operand_stall
|vpiStmt:
\_assignment: , line:233
|vpiOpType:82
|vpiLhs:
\_ref_obj: (tr.events.ls_operand_stall), line:233
|vpiName:tr.events.ls_operand_stall
|vpiFullName:work@taiga_wrapper.cpu.genblk6.tr.events.ls_operand_stall
|vpiRhs:
\_ref_obj: (tr_ls_operand_stall), line:233
|vpiName:tr_ls_operand_stall
|vpiFullName:work@taiga_wrapper.cpu.genblk6.tr_ls_operand_stall
|vpiStmt:
\_assignment: , line:234
|vpiOpType:82
|vpiLhs:
\_ref_obj: (tr.events.div_operand_stall), line:234
|vpiName:tr.events.div_operand_stall
|vpiFullName:work@taiga_wrapper.cpu.genblk6.tr.events.div_operand_stall
|vpiRhs:
\_ref_obj: (tr_div_operand_stall), line:234
|vpiName:tr_div_operand_stall
|vpiFullName:work@taiga_wrapper.cpu.genblk6.tr_div_operand_stall
|vpiStmt:
\_assignment: , line:235
|vpiOpType:82
|vpiLhs:
\_ref_obj: (tr.events.branch_correct), line:235
|vpiName:tr.events.branch_correct
|vpiFullName:work@taiga_wrapper.cpu.genblk6.tr.events.branch_correct
|vpiRhs:
\_ref_obj: (tr_branch_correct), line:235
|vpiName:tr_branch_correct
|vpiFullName:work@taiga_wrapper.cpu.genblk6.tr_branch_correct
|vpiStmt:
\_assignment: , line:236
|vpiOpType:82
|vpiLhs:
\_ref_obj: (tr.events.branch_misspredict), line:236
|vpiName:tr.events.branch_misspredict
|vpiFullName:work@taiga_wrapper.cpu.genblk6.tr.events.branch_misspredict
|vpiRhs:
\_ref_obj: (tr_branch_misspredict), line:236
|vpiName:tr_branch_misspredict
|vpiFullName:work@taiga_wrapper.cpu.genblk6.tr_branch_misspredict
|vpiStmt:
\_assignment: , line:237
|vpiOpType:82
|vpiLhs:
\_ref_obj: (tr.events.return_misspredict), line:237
|vpiName:tr.events.return_misspredict
|vpiFullName:work@taiga_wrapper.cpu.genblk6.tr.events.return_misspredict
|vpiRhs:
\_ref_obj: (tr_return_misspredict), line:237
|vpiName:tr_return_misspredict
|vpiFullName:work@taiga_wrapper.cpu.genblk6.tr_return_misspredict
|vpiStmt:
\_assignment: , line:238
|vpiOpType:82
|vpiLhs:
\_ref_obj: (tr.events.wb_mux_contention), line:238
|vpiName:tr.events.wb_mux_contention
|vpiFullName:work@taiga_wrapper.cpu.genblk6.tr.events.wb_mux_contention
|vpiRhs:
\_ref_obj: (tr_wb_mux_contention), line:238
|vpiName:tr_wb_mux_contention
|vpiFullName:work@taiga_wrapper.cpu.genblk6.tr_wb_mux_contention
|vpiStmt:
\_assignment: , line:239
|vpiOpType:82
|vpiLhs:
\_ref_obj: (tr.events.rs1_forwarding_needed), line:239
|vpiName:tr.events.rs1_forwarding_needed
|vpiFullName:work@taiga_wrapper.cpu.genblk6.tr.events.rs1_forwarding_needed
|vpiRhs:
\_ref_obj: (tr_rs1_forwarding_needed), line:239
|vpiName:tr_rs1_forwarding_needed
|vpiFullName:work@taiga_wrapper.cpu.genblk6.tr_rs1_forwarding_needed
|vpiStmt:
\_assignment: , line:240
|vpiOpType:82
|vpiLhs:
\_ref_obj: (tr.events.rs2_forwarding_needed), line:240
|vpiName:tr.events.rs2_forwarding_needed
|vpiFullName:work@taiga_wrapper.cpu.genblk6.tr.events.rs2_forwarding_needed
|vpiRhs:
\_ref_obj: (tr_rs2_forwarding_needed), line:240
|vpiName:tr_rs2_forwarding_needed
|vpiFullName:work@taiga_wrapper.cpu.genblk6.tr_rs2_forwarding_needed
|vpiStmt:
\_assignment: , line:241
|vpiOpType:82
|vpiLhs:
\_ref_obj: (tr.events.rs1_and_rs2_forwarding_needed), line:241
|vpiName:tr.events.rs1_and_rs2_forwarding_needed
|vpiFullName:work@taiga_wrapper.cpu.genblk6.tr.events.rs1_and_rs2_forwarding_needed
|vpiRhs:
\_ref_obj: (tr_rs1_and_rs2_forwarding_needed), line:241
|vpiName:tr_rs1_and_rs2_forwarding_needed
|vpiFullName:work@taiga_wrapper.cpu.genblk6.tr_rs1_and_rs2_forwarding_needed
|vpiStmt:
\_assignment: , line:242
|vpiOpType:82
|vpiLhs:
\_ref_obj: (tr.instruction_pc_dec), line:242
|vpiName:tr.instruction_pc_dec
|vpiFullName:work@taiga_wrapper.cpu.genblk6.tr.instruction_pc_dec
|vpiRhs:
\_ref_obj: (tr_instruction_pc_dec), line:242
|vpiName:tr_instruction_pc_dec
|vpiFullName:work@taiga_wrapper.cpu.genblk6.tr_instruction_pc_dec
|vpiStmt:
\_assignment: , line:243
|vpiOpType:82
|vpiLhs:
\_ref_obj: (tr.instruction_data_dec), line:243
|vpiName:tr.instruction_data_dec
|vpiFullName:work@taiga_wrapper.cpu.genblk6.tr.instruction_data_dec
|vpiRhs:
\_ref_obj: (tr_instruction_data_dec), line:243
|vpiName:tr_instruction_data_dec
|vpiFullName:work@taiga_wrapper.cpu.genblk6.tr_instruction_data_dec
|vpiParameter:
\_parameter: (ALU_UNIT_WB_ID), line:190
|vpiName:ALU_UNIT_WB_ID
|INT:32
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (BRANCH_PREDICTOR_WAYS), line:159
|vpiName:BRANCH_PREDICTOR_WAYS
|INT:9
|vpiParameter:
\_parameter: (BRANCH_TABLE_ENTRIES), line:160
|vpiName:BRANCH_TABLE_ENTRIES
|INT:4
|vpiParameter:
\_parameter: (BRANCH_UNIT_ID), line:195
|vpiName:BRANCH_UNIT_ID
|INT:8
|vpiParameter:
\_parameter: (BUS_ADDR_H), line:107
|vpiName:BUS_ADDR_H
|INT:1
|vpiParameter:
\_parameter: (BUS_ADDR_L), line:106
|vpiName:BUS_ADDR_L
|INT:0
|vpiParameter:
\_parameter: (BUS_BIT_CHECK), line:108
|vpiName:BUS_BIT_CHECK
|INT:1
|vpiParameter:
\_parameter: (BUS_TYPE), line:89
|vpiName:BUS_TYPE
|INT:5
|vpiParameter:
\_parameter: (COUNTER_W), line:42
|vpiName:COUNTER_W
|INT:33
|vpiParameter:
\_parameter: (CPU_ID), line:38
|vpiName:CPU_ID
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_ADDR_WIDTH), line:113
|vpiName:C_M_AXI_ADDR_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_DATA_WIDTH), line:114
|vpiName:C_M_AXI_DATA_WIDTH
|INT:1
|vpiParameter:
\_parameter: (DCACHE_LINES), line:133
|vpiName:DCACHE_LINES
|INT:-2146435073
|vpiParameter:
\_parameter: (DCACHE_LINE_ADDR_W), line:135
|vpiName:DCACHE_LINE_ADDR_W
|INT:1073741824
|vpiParameter:
\_parameter: (DCACHE_LINE_W), line:136
|vpiName:DCACHE_LINE_W
|INT:1342177279
|vpiParameter:
\_parameter: (DCACHE_SUB_LINE_ADDR_W), line:137
|vpiName:DCACHE_SUB_LINE_ADDR_W
|INT:4
|vpiParameter:
\_parameter: (DCACHE_TAG_W), line:138
|vpiName:DCACHE_TAG_W
|INT:1610612736
|vpiParameter:
\_parameter: (DCACHE_WAYS), line:134
|vpiName:DCACHE_WAYS
|INT:4
|vpiParameter:
\_parameter: (DIV_ALGORITHM), line:67
|vpiName:DIV_ALGORITHM
|INT:0
|vpiParameter:
\_parameter: (DIV_UNIT_WB_ID), line:192
|vpiName:DIV_UNIT_WB_ID
|INT:2
|vpiParameter:
\_parameter: (DTLB_DEPTH), line:152
|vpiName:DTLB_DEPTH
|INT:512
|vpiParameter:
\_parameter: (DTLB_WAYS), line:151
|vpiName:DTLB_WAYS
|INT:32
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (ENABLE_M_MODE), line:34
|vpiName:ENABLE_M_MODE
|INT:1
|vpiParameter:
\_parameter: (ENABLE_S_MODE), line:36
|vpiName:ENABLE_S_MODE
|INT:0
|vpiParameter:
\_parameter: (ENABLE_TRACE_INTERFACE), line:172
|vpiName:ENABLE_TRACE_INTERFACE
|INT:2
|vpiParameter:
\_parameter: (FETCH_BUFFER_DEPTH), line:168
|vpiName:FETCH_BUFFER_DEPTH
|INT:512
|vpiParameter:
\_parameter: (FPGA_VENDOR), line:27
|vpiName:FPGA_VENDOR
|STRING:"xilinx"
|vpiParameter:
\_parameter: (GC_UNIT_ID), line:196
|vpiName:GC_UNIT_ID
|INT:4
|vpiParameter:
\_parameter: (ICACHE_LINES), line:121
|vpiName:ICACHE_LINES
|INT:2
|vpiParameter:
\_parameter: (ICACHE_LINE_ADDR_W), line:123
|vpiName:ICACHE_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_LINE_W), line:124
|vpiName:ICACHE_LINE_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_SUB_LINE_ADDR_W), line:125
|vpiName:ICACHE_SUB_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_TAG_W), line:126
|vpiName:ICACHE_TAG_W
|INT:-2147483648
|vpiParameter:
\_parameter: (ICACHE_WAYS), line:122
|vpiName:ICACHE_WAYS
|INT:1
|vpiParameter:
\_parameter: (ITLB_DEPTH), line:146
|vpiName:ITLB_DEPTH
|INT:32
|vpiParameter:
\_parameter: (ITLB_WAYS), line:145
|vpiName:ITLB_WAYS
|INT:4
|vpiParameter:
\_parameter: (L1_CONNECTIONS), line:177
|vpiName:L1_CONNECTIONS
|INT:9
|vpiParameter:
\_parameter: (L1_DCACHE_ID), line:178
|vpiName:L1_DCACHE_ID
|INT:4
|vpiParameter:
\_parameter: (L1_DMMU_ID), line:179
|vpiName:L1_DMMU_ID
|INT:2
|vpiParameter:
\_parameter: (L1_ICACHE_ID), line:180
|vpiName:L1_ICACHE_ID
|INT:19
|vpiParameter:
\_parameter: (L1_IMMU_ID), line:181
|vpiName:L1_IMMU_ID
|INT:0
|vpiParameter:
\_parameter: (LS_UNIT_WB_ID), line:191
|vpiName:LS_UNIT_WB_ID
|INT:1
|vpiParameter:
\_parameter: (MAX_INFLIGHT_COUNT), line:167
|vpiName:MAX_INFLIGHT_COUNT
|INT:19
|vpiParameter:
\_parameter: (MEMORY_ADDR_H), line:103
|vpiName:MEMORY_ADDR_H
|INT:12
|vpiParameter:
\_parameter: (MEMORY_ADDR_L), line:102
|vpiName:MEMORY_ADDR_L
|INT:11
|vpiParameter:
\_parameter: (MEMORY_BIT_CHECK), line:104
|vpiName:MEMORY_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (MUL_UNIT_WB_ID), line:193
|vpiName:MUL_UNIT_WB_ID
|INT:512
|vpiParameter:
\_parameter: (NUM_UNITS), line:188
|vpiName:NUM_UNITS
|INT:2
|vpiParameter:
\_parameter: (NUM_WB_UNITS), line:186
|vpiName:NUM_WB_UNITS
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (RAS_DEPTH), line:161
|vpiName:RAS_DEPTH
|INT:2
|vpiParameter:
\_parameter: (RESET_VEC), line:39
|vpiName:RESET_VEC
|INT:-2147483648
|vpiParameter:
\_parameter: (SCRATCH_ADDR_H), line:99
|vpiName:SCRATCH_ADDR_H
|INT:9
|vpiParameter:
\_parameter: (SCRATCH_ADDR_L), line:98
|vpiName:SCRATCH_ADDR_L
|INT:8
|vpiParameter:
\_parameter: (SCRATCH_BIT_CHECK), line:100
|vpiName:SCRATCH_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (USE_AMO), line:70
|vpiName:USE_AMO
|INT:1
|vpiParameter:
\_parameter: (USE_BRANCH_PREDICTOR), line:158
|vpiName:USE_BRANCH_PREDICTOR
|INT:2
|vpiParameter:
\_parameter: (USE_BUS), line:88
|vpiName:USE_BUS
|INT:4
|vpiParameter:
\_parameter: (USE_DCACHE), line:92
|vpiName:USE_DCACHE
|INT:6
|vpiParameter:
\_parameter: (USE_DIV), line:49
|vpiName:USE_DIV
|INT:1
|vpiParameter:
\_parameter: (USE_DTAG_INVALIDATIONS), line:140
|vpiName:USE_DTAG_INVALIDATIONS
|INT:1879048191
|vpiParameter:
\_parameter: (USE_D_SCRATCH_MEM), line:79
|vpiName:USE_D_SCRATCH_MEM
|INT:3
|vpiParameter:
\_parameter: (USE_ICACHE), line:93
|vpiName:USE_ICACHE
|INT:7
|vpiParameter:
\_parameter: (USE_I_SCRATCH_MEM), line:78
|vpiName:USE_I_SCRATCH_MEM
|INT:2
|vpiParameter:
\_parameter: (USE_MUL), line:48
|vpiName:USE_MUL
|INT:1
|vpiParameter:
\_parameter: (WB_UNITS_WIDTH), line:187
|vpiName:WB_UNITS_WIDTH
|INT:32
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiNet:
\_logic_net: (clk), line:27, parent:cpu
|vpiNet:
\_logic_net: (rst), line:28, parent:cpu
|vpiNet:
\_logic_net: (tr), line:37, parent:cpu
|vpiNet:
\_logic_net: (timer_interrupt), line:41, parent:cpu
|vpiNet:
\_logic_net: (interrupt), line:42, parent:cpu
|vpiNet:
\_logic_net: (sc_complete), line:47, parent:cpu
|vpiNet:
\_logic_net: (sc_success), line:48, parent:cpu
|vpiNet:
\_logic_net: (branch_flush), line:52, parent:cpu
|vpiNet:
\_logic_net: (ls_exception_valid), line:67, parent:cpu
|vpiNet:
\_logic_net: (tlb_on), line:78, parent:cpu
|vpiNet:
\_logic_net: (asid), line:79, parent:cpu
|vpiNet:
\_logic_net: (pre_decode_push), line:82, parent:cpu
|vpiNet:
\_logic_net: (pre_decode_pop), line:83, parent:cpu
|vpiNet:
\_logic_net: (pre_decode_instruction), line:84, parent:cpu
|vpiNet:
\_logic_net: (pre_decode_pc), line:85, parent:cpu
|vpiNet:
\_logic_net: (branch_prediction_used), line:87, parent:cpu
|vpiNet:
\_logic_net: (bp_update_way), line:88, parent:cpu
|vpiNet:
\_logic_net: (fb_valid), line:89, parent:cpu
|vpiNet:
\_logic_net: (gc_issue_hold), line:93, parent:cpu
|vpiNet:
\_logic_net: (gc_issue_flush), line:94, parent:cpu
|vpiNet:
\_logic_net: (gc_fetch_flush), line:95, parent:cpu
|vpiNet:
\_logic_net: (gc_fetch_pc_override), line:96, parent:cpu
|vpiNet:
\_logic_net: (gc_supress_writeback), line:97, parent:cpu
|vpiNet:
\_logic_net: (load_store_issue), line:99, parent:cpu
|vpiNet:
\_logic_net: (gc_fetch_pc), line:100, parent:cpu
|vpiNet:
\_logic_net: (csr_rd), line:103, parent:cpu
|vpiNet:
\_logic_net: (csr_done), line:105, parent:cpu
|vpiNet:
\_logic_net: (illegal_instruction), line:108, parent:cpu
|vpiNet:
\_logic_net: (instruction_queue_empty), line:109, parent:cpu
|vpiNet:
\_logic_net: (instruction_issued), line:111, parent:cpu
|vpiNet:
\_logic_net: (instruction_issued_no_rd), line:112, parent:cpu
|vpiNet:
\_logic_net: (instruction_issued_with_rd), line:113, parent:cpu
|vpiNet:
\_logic_net: (instruction_complete), line:114, parent:cpu
|vpiNet:
\_logic_net: (gc_flush_required), line:115, parent:cpu
|vpiNet:
\_logic_net: (store_complete), line:119, parent:cpu
|vpiNet:
\_logic_net: (store_issued_with_data), line:122, parent:cpu
|vpiNet:
\_logic_net: (store_data), line:123, parent:cpu
|vpiNet:
\_logic_net: (tr_operand_stall), line:126, parent:cpu
|vpiNet:
\_logic_net: (tr_unit_stall), line:127, parent:cpu
|vpiNet:
\_logic_net: (tr_no_id_stall), line:128, parent:cpu
|vpiNet:
\_logic_net: (tr_no_instruction_stall), line:129, parent:cpu
|vpiNet:
\_logic_net: (tr_other_stall), line:130, parent:cpu
|vpiNet:
\_logic_net: (tr_branch_operand_stall), line:131, parent:cpu
|vpiNet:
\_logic_net: (tr_alu_operand_stall), line:132, parent:cpu
|vpiNet:
\_logic_net: (tr_ls_operand_stall), line:133, parent:cpu
|vpiNet:
\_logic_net: (tr_div_operand_stall), line:134, parent:cpu
|vpiNet:
\_logic_net: (tr_instruction_issued_dec), line:136, parent:cpu
|vpiNet:
\_logic_net: (tr_instruction_pc_dec), line:137, parent:cpu
|vpiNet:
\_logic_net: (tr_instruction_data_dec), line:138, parent:cpu
|vpiNet:
\_logic_net: (tr_branch_correct), line:140, parent:cpu
|vpiNet:
\_logic_net: (tr_branch_misspredict), line:141, parent:cpu
|vpiNet:
\_logic_net: (tr_return_misspredict), line:142, parent:cpu
|vpiNet:
\_logic_net: (tr_wb_mux_contention), line:143, parent:cpu
|vpiNet:
\_logic_net: (tr_rs1_forwarding_needed), line:145, parent:cpu
|vpiNet:
\_logic_net: (tr_rs2_forwarding_needed), line:146, parent:cpu
|vpiNet:
\_logic_net: (tr_rs1_and_rs2_forwarding_needed), line:147, parent:cpu
|vpiNet:
\_logic_net: (instruction_bram), line:30, parent:cpu
|vpiName:instruction_bram
|vpiFullName:work@taiga_wrapper.cpu.instruction_bram
|vpiNet:
\_logic_net: (data_bram), line:31, parent:cpu
|vpiName:data_bram
|vpiFullName:work@taiga_wrapper.cpu.data_bram
|vpiNet:
\_logic_net: (m_axi), line:33, parent:cpu
|vpiName:m_axi
|vpiFullName:work@taiga_wrapper.cpu.m_axi
|vpiNet:
\_logic_net: (m_avalon), line:34, parent:cpu
|vpiName:m_avalon
|vpiFullName:work@taiga_wrapper.cpu.m_avalon
|vpiNet:
\_logic_net: (m_wishbone), line:35, parent:cpu
|vpiName:m_wishbone
|vpiFullName:work@taiga_wrapper.cpu.m_wishbone
|vpiNet:
\_logic_net: (l2), line:39, parent:cpu
|vpiName:l2
|vpiFullName:work@taiga_wrapper.cpu.l2
|vpiInstance:
\_module: work@taiga_wrapper (work@taiga_wrapper), file:third_party/cores/taiga/examples/zedboard/taiga_wrapper.sv, line:27
|vpiVariables:
\_struct_var: (br_results), line:51, parent:cpu
|vpiName:br_results
|vpiFullName:work@taiga_wrapper.cpu.br_results
|vpiTypespec:
\_struct_typespec: (branch_results_t), line:330
|vpiVariables:
\_struct_var: (alu_inputs), line:57, parent:cpu
|vpiName:alu_inputs
|vpiFullName:work@taiga_wrapper.cpu.alu_inputs
|vpiTypespec:
\_struct_typespec: (alu_inputs_t), line:301
|vpiVariables:
\_struct_var: (ls_inputs), line:58, parent:cpu
|vpiName:ls_inputs
|vpiFullName:work@taiga_wrapper.cpu.ls_inputs
|vpiTypespec:
\_struct_typespec: (load_store_inputs_t), line:369
|vpiVariables:
\_struct_var: (branch_inputs), line:59, parent:cpu
|vpiName:branch_inputs
|vpiFullName:work@taiga_wrapper.cpu.branch_inputs
|vpiTypespec:
\_struct_typespec: (branch_inputs_t), line:313
|vpiVariables:
\_struct_var: (mul_inputs), line:60, parent:cpu
|vpiName:mul_inputs
|vpiFullName:work@taiga_wrapper.cpu.mul_inputs
|vpiTypespec:
\_struct_typespec: (mul_inputs_t), line:383
|vpiVariables:
\_struct_var: (div_inputs), line:61, parent:cpu
|vpiName:div_inputs
|vpiFullName:work@taiga_wrapper.cpu.div_inputs
|vpiTypespec:
\_struct_typespec: (div_inputs_t), line:389
|vpiVariables:
\_struct_var: (gc_inputs), line:62, parent:cpu
|vpiName:gc_inputs
|vpiFullName:work@taiga_wrapper.cpu.gc_inputs
|vpiTypespec:
\_struct_typespec: (gc_inputs_t), line:404
|vpiVariables:
\_struct_var: (ls_exception), line:66, parent:cpu
|vpiName:ls_exception
|vpiFullName:work@taiga_wrapper.cpu.ls_exception
|vpiTypespec:
\_struct_typespec: (exception_packet_t), line:263
|vpiVariables:
\_array_var: (unit_wb), parent:cpu
|vpiArrayType:1
|vpiName:unit_wb
|vpiFullName:work@taiga_wrapper.cpu.unit_wb
|vpiRandType:1
|vpiVisibility:1
|vpiSize:2
|vpiReg:
\_struct_var: , line:70, parent:unit_wb
|vpiFullName:work@taiga_wrapper.cpu.unit_wb
|vpiTypespec:
\_struct_typespec: (unit_writeback_t), line:295
|vpiRange:
\_range: , line:70
|vpiLeftRange:
\_constant: , line:70
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:70
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiVariables:
\_logic_var: (branch_metadata), line:86, parent:cpu
|vpiName:branch_metadata
|vpiFullName:work@taiga_wrapper.cpu.branch_metadata
|vpiVariables:
\_struct_var: (fb), line:90, parent:cpu
|vpiName:fb
|vpiFullName:work@taiga_wrapper.cpu.fb
|vpiTypespec:
\_struct_typespec: (fetch_buffer_packet_t), line:276
|vpiVariables:
\_logic_var: (oldest_id), line:98, parent:cpu
|vpiName:oldest_id
|vpiFullName:work@taiga_wrapper.cpu.oldest_id
|vpiVariables:
\_logic_var: (csr_id), line:104, parent:cpu
|vpiName:csr_id
|vpiFullName:work@taiga_wrapper.cpu.csr_id
|vpiVariables:
\_logic_var: (store_done_id), line:118, parent:cpu
|vpiName:store_done_id
|vpiFullName:work@taiga_wrapper.cpu.store_done_id
|vpiParameter:
\_parameter: (ALU_UNIT_WB_ID), line:190
|vpiName:ALU_UNIT_WB_ID
|INT:32
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (BRANCH_PREDICTOR_WAYS), line:159
|vpiName:BRANCH_PREDICTOR_WAYS
|INT:9
|vpiParameter:
\_parameter: (BRANCH_TABLE_ENTRIES), line:160
|vpiName:BRANCH_TABLE_ENTRIES
|INT:4
|vpiParameter:
\_parameter: (BRANCH_UNIT_ID), line:195
|vpiName:BRANCH_UNIT_ID
|INT:8
|vpiParameter:
\_parameter: (BUS_ADDR_H), line:107
|vpiName:BUS_ADDR_H
|INT:1
|vpiParameter:
\_parameter: (BUS_ADDR_L), line:106
|vpiName:BUS_ADDR_L
|INT:0
|vpiParameter:
\_parameter: (BUS_BIT_CHECK), line:108
|vpiName:BUS_BIT_CHECK
|INT:1
|vpiParameter:
\_parameter: (BUS_TYPE), line:89
|vpiName:BUS_TYPE
|INT:5
|vpiParameter:
\_parameter: (COUNTER_W), line:42
|vpiName:COUNTER_W
|INT:33
|vpiParameter:
\_parameter: (CPU_ID), line:38
|vpiName:CPU_ID
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_ADDR_WIDTH), line:113
|vpiName:C_M_AXI_ADDR_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_DATA_WIDTH), line:114
|vpiName:C_M_AXI_DATA_WIDTH
|INT:1
|vpiParameter:
\_parameter: (DCACHE_LINES), line:133
|vpiName:DCACHE_LINES
|INT:-2146435073
|vpiParameter:
\_parameter: (DCACHE_LINE_ADDR_W), line:135
|vpiName:DCACHE_LINE_ADDR_W
|INT:1073741824
|vpiParameter:
\_parameter: (DCACHE_LINE_W), line:136
|vpiName:DCACHE_LINE_W
|INT:1342177279
|vpiParameter:
\_parameter: (DCACHE_SUB_LINE_ADDR_W), line:137
|vpiName:DCACHE_SUB_LINE_ADDR_W
|INT:4
|vpiParameter:
\_parameter: (DCACHE_TAG_W), line:138
|vpiName:DCACHE_TAG_W
|INT:1610612736
|vpiParameter:
\_parameter: (DCACHE_WAYS), line:134
|vpiName:DCACHE_WAYS
|INT:4
|vpiParameter:
\_parameter: (DIV_ALGORITHM), line:67
|vpiName:DIV_ALGORITHM
|INT:0
|vpiParameter:
\_parameter: (DIV_UNIT_WB_ID), line:192
|vpiName:DIV_UNIT_WB_ID
|INT:2
|vpiParameter:
\_parameter: (DTLB_DEPTH), line:152
|vpiName:DTLB_DEPTH
|INT:512
|vpiParameter:
\_parameter: (DTLB_WAYS), line:151
|vpiName:DTLB_WAYS
|INT:32
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (ENABLE_M_MODE), line:34
|vpiName:ENABLE_M_MODE
|INT:1
|vpiParameter:
\_parameter: (ENABLE_S_MODE), line:36
|vpiName:ENABLE_S_MODE
|INT:0
|vpiParameter:
\_parameter: (ENABLE_TRACE_INTERFACE), line:172
|vpiName:ENABLE_TRACE_INTERFACE
|INT:2
|vpiParameter:
\_parameter: (FETCH_BUFFER_DEPTH), line:168
|vpiName:FETCH_BUFFER_DEPTH
|INT:512
|vpiParameter:
\_parameter: (FPGA_VENDOR), line:27
|vpiName:FPGA_VENDOR
|STRING:"xilinx"
|vpiParameter:
\_parameter: (GC_UNIT_ID), line:196
|vpiName:GC_UNIT_ID
|INT:4
|vpiParameter:
\_parameter: (ICACHE_LINES), line:121
|vpiName:ICACHE_LINES
|INT:2
|vpiParameter:
\_parameter: (ICACHE_LINE_ADDR_W), line:123
|vpiName:ICACHE_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_LINE_W), line:124
|vpiName:ICACHE_LINE_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_SUB_LINE_ADDR_W), line:125
|vpiName:ICACHE_SUB_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_TAG_W), line:126
|vpiName:ICACHE_TAG_W
|INT:-2147483648
|vpiParameter:
\_parameter: (ICACHE_WAYS), line:122
|vpiName:ICACHE_WAYS
|INT:1
|vpiParameter:
\_parameter: (ITLB_DEPTH), line:146
|vpiName:ITLB_DEPTH
|INT:32
|vpiParameter:
\_parameter: (ITLB_WAYS), line:145
|vpiName:ITLB_WAYS
|INT:4
|vpiParameter:
\_parameter: (L1_CONNECTIONS), line:177
|vpiName:L1_CONNECTIONS
|INT:9
|vpiParameter:
\_parameter: (L1_DCACHE_ID), line:178
|vpiName:L1_DCACHE_ID
|INT:4
|vpiParameter:
\_parameter: (L1_DMMU_ID), line:179
|vpiName:L1_DMMU_ID
|INT:2
|vpiParameter:
\_parameter: (L1_ICACHE_ID), line:180
|vpiName:L1_ICACHE_ID
|INT:19
|vpiParameter:
\_parameter: (L1_IMMU_ID), line:181
|vpiName:L1_IMMU_ID
|INT:0
|vpiParameter:
\_parameter: (LS_UNIT_WB_ID), line:191
|vpiName:LS_UNIT_WB_ID
|INT:1
|vpiParameter:
\_parameter: (MAX_INFLIGHT_COUNT), line:167
|vpiName:MAX_INFLIGHT_COUNT
|INT:19
|vpiParameter:
\_parameter: (MEMORY_ADDR_H), line:103
|vpiName:MEMORY_ADDR_H
|INT:12
|vpiParameter:
\_parameter: (MEMORY_ADDR_L), line:102
|vpiName:MEMORY_ADDR_L
|INT:11
|vpiParameter:
\_parameter: (MEMORY_BIT_CHECK), line:104
|vpiName:MEMORY_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (MUL_UNIT_WB_ID), line:193
|vpiName:MUL_UNIT_WB_ID
|INT:512
|vpiParameter:
\_parameter: (NUM_UNITS), line:188
|vpiName:NUM_UNITS
|INT:2
|vpiParameter:
\_parameter: (NUM_WB_UNITS), line:186
|vpiName:NUM_WB_UNITS
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (RAS_DEPTH), line:161
|vpiName:RAS_DEPTH
|INT:2
|vpiParameter:
\_parameter: (RESET_VEC), line:39
|vpiName:RESET_VEC
|INT:-2147483648
|vpiParameter:
\_parameter: (SCRATCH_ADDR_H), line:99
|vpiName:SCRATCH_ADDR_H
|INT:9
|vpiParameter:
\_parameter: (SCRATCH_ADDR_L), line:98
|vpiName:SCRATCH_ADDR_L
|INT:8
|vpiParameter:
\_parameter: (SCRATCH_BIT_CHECK), line:100
|vpiName:SCRATCH_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (USE_AMO), line:70
|vpiName:USE_AMO
|INT:1
|vpiParameter:
\_parameter: (USE_BRANCH_PREDICTOR), line:158
|vpiName:USE_BRANCH_PREDICTOR
|INT:2
|vpiParameter:
\_parameter: (USE_BUS), line:88
|vpiName:USE_BUS
|INT:4
|vpiParameter:
\_parameter: (USE_DCACHE), line:92
|vpiName:USE_DCACHE
|INT:6
|vpiParameter:
\_parameter: (USE_DIV), line:49
|vpiName:USE_DIV
|INT:1
|vpiParameter:
\_parameter: (USE_DTAG_INVALIDATIONS), line:140
|vpiName:USE_DTAG_INVALIDATIONS
|INT:1879048191
|vpiParameter:
\_parameter: (USE_D_SCRATCH_MEM), line:79
|vpiName:USE_D_SCRATCH_MEM
|INT:3
|vpiParameter:
\_parameter: (USE_ICACHE), line:93
|vpiName:USE_ICACHE
|INT:7
|vpiParameter:
\_parameter: (USE_I_SCRATCH_MEM), line:78
|vpiName:USE_I_SCRATCH_MEM
|INT:2
|vpiParameter:
\_parameter: (USE_MUL), line:48
|vpiName:USE_MUL
|INT:1
|vpiParameter:
\_parameter: (WB_UNITS_WIDTH), line:187
|vpiName:WB_UNITS_WIDTH
|INT:32
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiModule:
\_module: work@byte_en_BRAM (inst_data_ram), file:third_party/cores/taiga/examples/zedboard/taiga_wrapper.sv, line:245, parent:work@taiga_wrapper
|vpiDefName:work@byte_en_BRAM
|vpiName:inst_data_ram
|vpiFullName:work@taiga_wrapper.inst_data_ram
|vpiPort:
\_port: (clk), line:32, parent:inst_data_ram
|vpiName:clk
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (clk), line:246
|vpiName:clk
|vpiActual:
\_logic_net: (clk), line:63, parent:work@taiga_wrapper
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (clk), line:32, parent:inst_data_ram
|vpiName:clk
|vpiFullName:work@taiga_wrapper.inst_data_ram.clk
|vpiNetType:36
|vpiPort:
\_port: (addr_a), line:33, parent:inst_data_ram
|vpiName:addr_a
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (instruction_bram.addr), line:247
|vpiName:instruction_bram.addr
|vpiActual:
\_logic_net: (addr), line:25, parent:instruction_bram
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (addr_a), line:33, parent:inst_data_ram
|vpiName:addr_a
|vpiFullName:work@taiga_wrapper.inst_data_ram.addr_a
|vpiNetType:36
|vpiRange:
\_range: , line:33
|vpiLeftRange:
\_constant: , line:33
|vpiConstType:7
|vpiDecompile:11
|vpiSize:32
|INT:11
|vpiRightRange:
\_constant: , line:33
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiPort:
\_port: (en_a), line:34, parent:inst_data_ram
|vpiName:en_a
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (instruction_bram.en), line:248
|vpiName:instruction_bram.en
|vpiActual:
\_logic_net: (en), line:26, parent:instruction_bram
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (en_a), line:34, parent:inst_data_ram
|vpiName:en_a
|vpiFullName:work@taiga_wrapper.inst_data_ram.en_a
|vpiNetType:36
|vpiPort:
\_port: (be_a), line:35, parent:inst_data_ram
|vpiName:be_a
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (instruction_bram.be), line:249
|vpiName:instruction_bram.be
|vpiActual:
\_logic_net: (be), line:27, parent:instruction_bram
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (be_a), line:35, parent:inst_data_ram
|vpiName:be_a
|vpiFullName:work@taiga_wrapper.inst_data_ram.be_a
|vpiNetType:36
|vpiRange:
\_range: , line:35
|vpiLeftRange:
\_constant: , line:35
|vpiConstType:7
|vpiDecompile:18446744073709551615
|vpiSize:32
|INT:-1
|vpiRightRange:
\_constant: , line:35
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiPort:
\_port: (data_in_a), line:36, parent:inst_data_ram
|vpiName:data_in_a
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (instruction_bram.data_in), line:250
|vpiName:instruction_bram.data_in
|vpiActual:
\_logic_net: (data_in), line:28, parent:instruction_bram
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (data_in_a), line:36, parent:inst_data_ram
|vpiName:data_in_a
|vpiFullName:work@taiga_wrapper.inst_data_ram.data_in_a
|vpiNetType:36
|vpiRange:
\_range: , line:36
|vpiLeftRange:
\_constant: , line:36
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiRightRange:
\_constant: , line:36
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiPort:
\_port: (data_out_a), line:37, parent:inst_data_ram
|vpiName:data_out_a
|vpiDirection:2
|vpiHighConn:
\_ref_obj: (instruction_bram.data_out), line:251
|vpiName:instruction_bram.data_out
|vpiActual:
\_logic_net: (data_out), line:29, parent:instruction_bram
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (data_out_a), line:37, parent:inst_data_ram
|vpiName:data_out_a
|vpiFullName:work@taiga_wrapper.inst_data_ram.data_out_a
|vpiNetType:36
|vpiRange:
\_range: , line:37
|vpiLeftRange:
\_constant: , line:37
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiRightRange:
\_constant: , line:37
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiPort:
\_port: (addr_b), line:39, parent:inst_data_ram
|vpiName:addr_b
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (data_bram.addr), line:253
|vpiName:data_bram.addr
|vpiActual:
\_logic_net: (addr), line:25, parent:data_bram
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (addr_b), line:39, parent:inst_data_ram
|vpiName:addr_b
|vpiFullName:work@taiga_wrapper.inst_data_ram.addr_b
|vpiNetType:36
|vpiRange:
\_range: , line:39
|vpiLeftRange:
\_constant: , line:39
|vpiConstType:7
|vpiDecompile:11
|vpiSize:32
|INT:11
|vpiRightRange:
\_constant: , line:39
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiPort:
\_port: (en_b), line:40, parent:inst_data_ram
|vpiName:en_b
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (data_bram.en), line:254
|vpiName:data_bram.en
|vpiActual:
\_logic_net: (en), line:26, parent:data_bram
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (en_b), line:40, parent:inst_data_ram
|vpiName:en_b
|vpiFullName:work@taiga_wrapper.inst_data_ram.en_b
|vpiNetType:36
|vpiPort:
\_port: (be_b), line:41, parent:inst_data_ram
|vpiName:be_b
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (data_bram.be), line:255
|vpiName:data_bram.be
|vpiActual:
\_logic_net: (be), line:27, parent:data_bram
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (be_b), line:41, parent:inst_data_ram
|vpiName:be_b
|vpiFullName:work@taiga_wrapper.inst_data_ram.be_b
|vpiNetType:36
|vpiRange:
\_range: , line:41
|vpiLeftRange:
\_constant: , line:41
|vpiConstType:7
|vpiDecompile:18446744073709551615
|vpiSize:32
|INT:-1
|vpiRightRange:
\_constant: , line:41
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiPort:
\_port: (data_in_b), line:42, parent:inst_data_ram
|vpiName:data_in_b
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (data_bram.data_in), line:256
|vpiName:data_bram.data_in
|vpiActual:
\_logic_net: (data_in), line:28, parent:data_bram
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (data_in_b), line:42, parent:inst_data_ram
|vpiName:data_in_b
|vpiFullName:work@taiga_wrapper.inst_data_ram.data_in_b
|vpiNetType:36
|vpiRange:
\_range: , line:42
|vpiLeftRange:
\_constant: , line:42
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiRightRange:
\_constant: , line:42
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiPort:
\_port: (data_out_b), line:43, parent:inst_data_ram
|vpiName:data_out_b
|vpiDirection:2
|vpiHighConn:
\_ref_obj: (data_bram.data_out), line:257
|vpiName:data_bram.data_out
|vpiActual:
\_logic_net: (data_out), line:29, parent:data_bram
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (data_out_b), line:43, parent:inst_data_ram
|vpiName:data_out_b
|vpiFullName:work@taiga_wrapper.inst_data_ram.data_out_b
|vpiNetType:36
|vpiRange:
\_range: , line:43
|vpiLeftRange:
\_constant: , line:43
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiRightRange:
\_constant: , line:43
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiGenScopeArray:
\_gen_scope_array: (genblk1), line:47, parent:inst_data_ram
|vpiName:genblk1
|vpiFullName:work@taiga_wrapper.inst_data_ram.genblk1
|vpiGenScope:
\_gen_scope: , parent:genblk1
|vpiFullName:work@taiga_wrapper.inst_data_ram.genblk1
|vpiModule:
\_module: work@taiga_wrapper.inst_data_ram.genblk1::intel_byte_enable_ram (ram_block), file:third_party/cores/taiga/core/byte_en_BRAM.sv, line:50
|vpiDefName:work@taiga_wrapper.inst_data_ram.genblk1::intel_byte_enable_ram
|vpiName:ram_block
|vpiFullName:work@taiga_wrapper.inst_data_ram.genblk1.ram_block
|vpiParameter:
\_parameter: (ALU_UNIT_WB_ID), line:190
|vpiName:ALU_UNIT_WB_ID
|INT:32
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (BRANCH_PREDICTOR_WAYS), line:159
|vpiName:BRANCH_PREDICTOR_WAYS
|INT:9
|vpiParameter:
\_parameter: (BRANCH_TABLE_ENTRIES), line:160
|vpiName:BRANCH_TABLE_ENTRIES
|INT:4
|vpiParameter:
\_parameter: (BRANCH_UNIT_ID), line:195
|vpiName:BRANCH_UNIT_ID
|INT:8
|vpiParameter:
\_parameter: (BUS_ADDR_H), line:107
|vpiName:BUS_ADDR_H
|INT:1
|vpiParameter:
\_parameter: (BUS_ADDR_L), line:106
|vpiName:BUS_ADDR_L
|INT:0
|vpiParameter:
\_parameter: (BUS_BIT_CHECK), line:108
|vpiName:BUS_BIT_CHECK
|INT:1
|vpiParameter:
\_parameter: (BUS_TYPE), line:89
|vpiName:BUS_TYPE
|INT:5
|vpiParameter:
\_parameter: (COUNTER_W), line:42
|vpiName:COUNTER_W
|INT:33
|vpiParameter:
\_parameter: (CPU_ID), line:38
|vpiName:CPU_ID
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_ADDR_WIDTH), line:113
|vpiName:C_M_AXI_ADDR_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_DATA_WIDTH), line:114
|vpiName:C_M_AXI_DATA_WIDTH
|INT:1
|vpiParameter:
\_parameter: (DCACHE_LINES), line:133
|vpiName:DCACHE_LINES
|INT:-2146435073
|vpiParameter:
\_parameter: (DCACHE_LINE_ADDR_W), line:135
|vpiName:DCACHE_LINE_ADDR_W
|INT:1073741824
|vpiParameter:
\_parameter: (DCACHE_LINE_W), line:136
|vpiName:DCACHE_LINE_W
|INT:1342177279
|vpiParameter:
\_parameter: (DCACHE_SUB_LINE_ADDR_W), line:137
|vpiName:DCACHE_SUB_LINE_ADDR_W
|INT:4
|vpiParameter:
\_parameter: (DCACHE_TAG_W), line:138
|vpiName:DCACHE_TAG_W
|INT:1610612736
|vpiParameter:
\_parameter: (DCACHE_WAYS), line:134
|vpiName:DCACHE_WAYS
|INT:4
|vpiParameter:
\_parameter: (DIV_ALGORITHM), line:67
|vpiName:DIV_ALGORITHM
|INT:0
|vpiParameter:
\_parameter: (DIV_UNIT_WB_ID), line:192
|vpiName:DIV_UNIT_WB_ID
|INT:2
|vpiParameter:
\_parameter: (DTLB_DEPTH), line:152
|vpiName:DTLB_DEPTH
|INT:512
|vpiParameter:
\_parameter: (DTLB_WAYS), line:151
|vpiName:DTLB_WAYS
|INT:32
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (ENABLE_M_MODE), line:34
|vpiName:ENABLE_M_MODE
|INT:1
|vpiParameter:
\_parameter: (ENABLE_S_MODE), line:36
|vpiName:ENABLE_S_MODE
|INT:0
|vpiParameter:
\_parameter: (ENABLE_TRACE_INTERFACE), line:172
|vpiName:ENABLE_TRACE_INTERFACE
|INT:2
|vpiParameter:
\_parameter: (FETCH_BUFFER_DEPTH), line:168
|vpiName:FETCH_BUFFER_DEPTH
|INT:512
|vpiParameter:
\_parameter: (FPGA_VENDOR), line:27
|vpiName:FPGA_VENDOR
|STRING:"xilinx"
|vpiParameter:
\_parameter: (GC_UNIT_ID), line:196
|vpiName:GC_UNIT_ID
|INT:4
|vpiParameter:
\_parameter: (ICACHE_LINES), line:121
|vpiName:ICACHE_LINES
|INT:2
|vpiParameter:
\_parameter: (ICACHE_LINE_ADDR_W), line:123
|vpiName:ICACHE_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_LINE_W), line:124
|vpiName:ICACHE_LINE_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_SUB_LINE_ADDR_W), line:125
|vpiName:ICACHE_SUB_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_TAG_W), line:126
|vpiName:ICACHE_TAG_W
|INT:-2147483648
|vpiParameter:
\_parameter: (ICACHE_WAYS), line:122
|vpiName:ICACHE_WAYS
|INT:1
|vpiParameter:
\_parameter: (ITLB_DEPTH), line:146
|vpiName:ITLB_DEPTH
|INT:32
|vpiParameter:
\_parameter: (ITLB_WAYS), line:145
|vpiName:ITLB_WAYS
|INT:4
|vpiParameter:
\_parameter: (L1_CONNECTIONS), line:177
|vpiName:L1_CONNECTIONS
|INT:9
|vpiParameter:
\_parameter: (L1_DCACHE_ID), line:178
|vpiName:L1_DCACHE_ID
|INT:4
|vpiParameter:
\_parameter: (L1_DMMU_ID), line:179
|vpiName:L1_DMMU_ID
|INT:2
|vpiParameter:
\_parameter: (L1_ICACHE_ID), line:180
|vpiName:L1_ICACHE_ID
|INT:19
|vpiParameter:
\_parameter: (L1_IMMU_ID), line:181
|vpiName:L1_IMMU_ID
|INT:0
|vpiParameter:
\_parameter: (LS_UNIT_WB_ID), line:191
|vpiName:LS_UNIT_WB_ID
|INT:1
|vpiParameter:
\_parameter: (MAX_INFLIGHT_COUNT), line:167
|vpiName:MAX_INFLIGHT_COUNT
|INT:19
|vpiParameter:
\_parameter: (MEMORY_ADDR_H), line:103
|vpiName:MEMORY_ADDR_H
|INT:12
|vpiParameter:
\_parameter: (MEMORY_ADDR_L), line:102
|vpiName:MEMORY_ADDR_L
|INT:11
|vpiParameter:
\_parameter: (MEMORY_BIT_CHECK), line:104
|vpiName:MEMORY_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (MUL_UNIT_WB_ID), line:193
|vpiName:MUL_UNIT_WB_ID
|INT:512
|vpiParameter:
\_parameter: (NUM_UNITS), line:188
|vpiName:NUM_UNITS
|INT:2
|vpiParameter:
\_parameter: (NUM_WB_UNITS), line:186
|vpiName:NUM_WB_UNITS
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (RAS_DEPTH), line:161
|vpiName:RAS_DEPTH
|INT:2
|vpiParameter:
\_parameter: (RESET_VEC), line:39
|vpiName:RESET_VEC
|INT:-2147483648
|vpiParameter:
\_parameter: (SCRATCH_ADDR_H), line:99
|vpiName:SCRATCH_ADDR_H
|INT:9
|vpiParameter:
\_parameter: (SCRATCH_ADDR_L), line:98
|vpiName:SCRATCH_ADDR_L
|INT:8
|vpiParameter:
\_parameter: (SCRATCH_BIT_CHECK), line:100
|vpiName:SCRATCH_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (USE_AMO), line:70
|vpiName:USE_AMO
|INT:1
|vpiParameter:
\_parameter: (USE_BRANCH_PREDICTOR), line:158
|vpiName:USE_BRANCH_PREDICTOR
|INT:2
|vpiParameter:
\_parameter: (USE_BUS), line:88
|vpiName:USE_BUS
|INT:4
|vpiParameter:
\_parameter: (USE_DCACHE), line:92
|vpiName:USE_DCACHE
|INT:6
|vpiParameter:
\_parameter: (USE_DIV), line:49
|vpiName:USE_DIV
|INT:1
|vpiParameter:
\_parameter: (USE_DTAG_INVALIDATIONS), line:140
|vpiName:USE_DTAG_INVALIDATIONS
|INT:1879048191
|vpiParameter:
\_parameter: (USE_D_SCRATCH_MEM), line:79
|vpiName:USE_D_SCRATCH_MEM
|INT:3
|vpiParameter:
\_parameter: (USE_ICACHE), line:93
|vpiName:USE_ICACHE
|INT:7
|vpiParameter:
\_parameter: (USE_I_SCRATCH_MEM), line:78
|vpiName:USE_I_SCRATCH_MEM
|INT:2
|vpiParameter:
\_parameter: (USE_MUL), line:48
|vpiName:USE_MUL
|INT:1
|vpiParameter:
\_parameter: (WB_UNITS_WIDTH), line:187
|vpiName:WB_UNITS_WIDTH
|INT:32
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiNet:
\_logic_net: (clk), line:32, parent:inst_data_ram
|vpiNet:
\_logic_net: (addr_a), line:33, parent:inst_data_ram
|vpiNet:
\_logic_net: (en_a), line:34, parent:inst_data_ram
|vpiNet:
\_logic_net: (be_a), line:35, parent:inst_data_ram
|vpiNet:
\_logic_net: (data_in_a), line:36, parent:inst_data_ram
|vpiNet:
\_logic_net: (data_out_a), line:37, parent:inst_data_ram
|vpiNet:
\_logic_net: (addr_b), line:39, parent:inst_data_ram
|vpiNet:
\_logic_net: (en_b), line:40, parent:inst_data_ram
|vpiNet:
\_logic_net: (be_b), line:41, parent:inst_data_ram
|vpiNet:
\_logic_net: (data_in_b), line:42, parent:inst_data_ram
|vpiNet:
\_logic_net: (data_out_b), line:43, parent:inst_data_ram
|vpiInstance:
\_module: work@taiga_wrapper (work@taiga_wrapper), file:third_party/cores/taiga/examples/zedboard/taiga_wrapper.sv, line:27
|vpiParameter:
\_parameter: (ALU_UNIT_WB_ID), line:190
|vpiName:ALU_UNIT_WB_ID
|INT:32
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (BRANCH_PREDICTOR_WAYS), line:159
|vpiName:BRANCH_PREDICTOR_WAYS
|INT:9
|vpiParameter:
\_parameter: (BRANCH_TABLE_ENTRIES), line:160
|vpiName:BRANCH_TABLE_ENTRIES
|INT:4
|vpiParameter:
\_parameter: (BRANCH_UNIT_ID), line:195
|vpiName:BRANCH_UNIT_ID
|INT:8
|vpiParameter:
\_parameter: (BUS_ADDR_H), line:107
|vpiName:BUS_ADDR_H
|INT:1
|vpiParameter:
\_parameter: (BUS_ADDR_L), line:106
|vpiName:BUS_ADDR_L
|INT:0
|vpiParameter:
\_parameter: (BUS_BIT_CHECK), line:108
|vpiName:BUS_BIT_CHECK
|INT:1
|vpiParameter:
\_parameter: (BUS_TYPE), line:89
|vpiName:BUS_TYPE
|INT:5
|vpiParameter:
\_parameter: (COUNTER_W), line:42
|vpiName:COUNTER_W
|INT:33
|vpiParameter:
\_parameter: (CPU_ID), line:38
|vpiName:CPU_ID
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_ADDR_WIDTH), line:113
|vpiName:C_M_AXI_ADDR_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_DATA_WIDTH), line:114
|vpiName:C_M_AXI_DATA_WIDTH
|INT:1
|vpiParameter:
\_parameter: (DCACHE_LINES), line:133
|vpiName:DCACHE_LINES
|INT:-2146435073
|vpiParameter:
\_parameter: (DCACHE_LINE_ADDR_W), line:135
|vpiName:DCACHE_LINE_ADDR_W
|INT:1073741824
|vpiParameter:
\_parameter: (DCACHE_LINE_W), line:136
|vpiName:DCACHE_LINE_W
|INT:1342177279
|vpiParameter:
\_parameter: (DCACHE_SUB_LINE_ADDR_W), line:137
|vpiName:DCACHE_SUB_LINE_ADDR_W
|INT:4
|vpiParameter:
\_parameter: (DCACHE_TAG_W), line:138
|vpiName:DCACHE_TAG_W
|INT:1610612736
|vpiParameter:
\_parameter: (DCACHE_WAYS), line:134
|vpiName:DCACHE_WAYS
|INT:4
|vpiParameter:
\_parameter: (DIV_ALGORITHM), line:67
|vpiName:DIV_ALGORITHM
|INT:0
|vpiParameter:
\_parameter: (DIV_UNIT_WB_ID), line:192
|vpiName:DIV_UNIT_WB_ID
|INT:2
|vpiParameter:
\_parameter: (DTLB_DEPTH), line:152
|vpiName:DTLB_DEPTH
|INT:512
|vpiParameter:
\_parameter: (DTLB_WAYS), line:151
|vpiName:DTLB_WAYS
|INT:32
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (ENABLE_M_MODE), line:245
|vpiName:ENABLE_M_MODE
|STRING:"/home/ematthew/Research/RISCV/software2/riscv-tools/riscv-tests/benchmarks/fft.riscv.hw_init"
|vpiParameter:
\_parameter: (ENABLE_S_MODE), line:245
|vpiName:ENABLE_S_MODE
|INT:1
|vpiParameter:
\_parameter: (ENABLE_TRACE_INTERFACE), line:172
|vpiName:ENABLE_TRACE_INTERFACE
|INT:2
|vpiParameter:
\_parameter: (FETCH_BUFFER_DEPTH), line:168
|vpiName:FETCH_BUFFER_DEPTH
|INT:512
|vpiParameter:
\_parameter: (FPGA_VENDOR), line:245
|vpiName:FPGA_VENDOR
|INT:4096
|vpiParameter:
\_parameter: (GC_UNIT_ID), line:196
|vpiName:GC_UNIT_ID
|INT:4
|vpiParameter:
\_parameter: (ICACHE_LINES), line:121
|vpiName:ICACHE_LINES
|INT:2
|vpiParameter:
\_parameter: (ICACHE_LINE_ADDR_W), line:123
|vpiName:ICACHE_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_LINE_W), line:124
|vpiName:ICACHE_LINE_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_SUB_LINE_ADDR_W), line:125
|vpiName:ICACHE_SUB_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_TAG_W), line:126
|vpiName:ICACHE_TAG_W
|INT:-2147483648
|vpiParameter:
\_parameter: (ICACHE_WAYS), line:122
|vpiName:ICACHE_WAYS
|INT:1
|vpiParameter:
\_parameter: (ITLB_DEPTH), line:146
|vpiName:ITLB_DEPTH
|INT:32
|vpiParameter:
\_parameter: (ITLB_WAYS), line:145
|vpiName:ITLB_WAYS
|INT:4
|vpiParameter:
\_parameter: (L1_CONNECTIONS), line:177
|vpiName:L1_CONNECTIONS
|INT:9
|vpiParameter:
\_parameter: (L1_DCACHE_ID), line:178
|vpiName:L1_DCACHE_ID
|INT:4
|vpiParameter:
\_parameter: (L1_DMMU_ID), line:179
|vpiName:L1_DMMU_ID
|INT:2
|vpiParameter:
\_parameter: (L1_ICACHE_ID), line:180
|vpiName:L1_ICACHE_ID
|INT:19
|vpiParameter:
\_parameter: (L1_IMMU_ID), line:181
|vpiName:L1_IMMU_ID
|INT:0
|vpiParameter:
\_parameter: (LINES), line:27
|vpiName:LINES
|INT:4096
|vpiParameter:
\_parameter: (LS_UNIT_WB_ID), line:191
|vpiName:LS_UNIT_WB_ID
|INT:1
|vpiParameter:
\_parameter: (MAX_INFLIGHT_COUNT), line:167
|vpiName:MAX_INFLIGHT_COUNT
|INT:19
|vpiParameter:
\_parameter: (MEMORY_ADDR_H), line:103
|vpiName:MEMORY_ADDR_H
|INT:12
|vpiParameter:
\_parameter: (MEMORY_ADDR_L), line:102
|vpiName:MEMORY_ADDR_L
|INT:11
|vpiParameter:
\_parameter: (MEMORY_BIT_CHECK), line:104
|vpiName:MEMORY_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (MUL_UNIT_WB_ID), line:193
|vpiName:MUL_UNIT_WB_ID
|INT:512
|vpiParameter:
\_parameter: (NUM_UNITS), line:188
|vpiName:NUM_UNITS
|INT:2
|vpiParameter:
\_parameter: (NUM_WB_UNITS), line:186
|vpiName:NUM_WB_UNITS
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (RAS_DEPTH), line:161
|vpiName:RAS_DEPTH
|INT:2
|vpiParameter:
\_parameter: (RESET_VEC), line:39
|vpiName:RESET_VEC
|INT:-2147483648
|vpiParameter:
\_parameter: (SCRATCH_ADDR_H), line:99
|vpiName:SCRATCH_ADDR_H
|INT:9
|vpiParameter:
\_parameter: (SCRATCH_ADDR_L), line:98
|vpiName:SCRATCH_ADDR_L
|INT:8
|vpiParameter:
\_parameter: (SCRATCH_BIT_CHECK), line:100
|vpiName:SCRATCH_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (USE_AMO), line:70
|vpiName:USE_AMO
|INT:1
|vpiParameter:
\_parameter: (USE_BRANCH_PREDICTOR), line:158
|vpiName:USE_BRANCH_PREDICTOR
|INT:2
|vpiParameter:
\_parameter: (USE_BUS), line:88
|vpiName:USE_BUS
|INT:4
|vpiParameter:
\_parameter: (USE_DCACHE), line:92
|vpiName:USE_DCACHE
|INT:6
|vpiParameter:
\_parameter: (USE_DIV), line:49
|vpiName:USE_DIV
|INT:1
|vpiParameter:
\_parameter: (USE_DTAG_INVALIDATIONS), line:140
|vpiName:USE_DTAG_INVALIDATIONS
|INT:1879048191
|vpiParameter:
\_parameter: (USE_D_SCRATCH_MEM), line:79
|vpiName:USE_D_SCRATCH_MEM
|INT:3
|vpiParameter:
\_parameter: (USE_ICACHE), line:93
|vpiName:USE_ICACHE
|INT:7
|vpiParameter:
\_parameter: (USE_I_SCRATCH_MEM), line:78
|vpiName:USE_I_SCRATCH_MEM
|INT:2
|vpiParameter:
\_parameter: (USE_MUL), line:48
|vpiName:USE_MUL
|INT:1
|vpiParameter:
\_parameter: (USE_PRELOAD_FILE), line:29
|vpiName:USE_PRELOAD_FILE
|INT:0
|vpiParameter:
\_parameter: (WB_UNITS_WIDTH), line:187
|vpiName:WB_UNITS_WIDTH
|INT:32
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiParameter:
\_parameter: (preload_file), line:28
|vpiName:preload_file
|STRING:""
|vpiGenScopeArray:
\_gen_scope_array: (genblk1), line:238, parent:work@taiga_wrapper
|vpiName:genblk1
|vpiFullName:work@taiga_wrapper.genblk1
|vpiGenScope:
\_gen_scope: , parent:genblk1
|vpiFullName:work@taiga_wrapper.genblk1
|vpiModule:
\_module: work@l2_arbiter (l2_arb), file:third_party/cores/taiga/examples/zedboard/taiga_wrapper.sv, line:239
|vpiDefName:work@l2_arbiter
|vpiName:l2_arb
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb
|vpiPort:
\_port: (clk), line:27, parent:l2_arb
|vpiName:clk
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (clk), line:239
|vpiName:clk
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (clk), line:27, parent:l2_arb
|vpiName:clk
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.clk
|vpiNetType:36
|vpiPort:
\_port: (rst), line:28, parent:l2_arb
|vpiName:rst
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (rst), line:239
|vpiName:rst
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (rst), line:28, parent:l2_arb
|vpiName:rst
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.rst
|vpiNetType:36
|vpiPort:
\_port: (request), line:30, parent:l2_arb
|vpiName:request
|vpiDirection:5
|vpiHighConn:
\_ref_obj: (request), line:239
|vpiName:request
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_modport: (slave)
|vpiName:slave
|vpiIODecl:
\_io_decl: (addr)
|vpiName:addr
|vpiDirection:1
|vpiExpr:
\_logic_net: (addr), line:27
|vpiName:addr
|vpiNetType:36
|vpiRange:
\_range: , line:27
|vpiLeftRange:
\_constant: , line:27
|vpiConstType:7
|vpiDecompile:29
|vpiSize:32
|INT:29
|vpiRightRange:
\_constant: , line:27
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (be)
|vpiName:be
|vpiDirection:1
|vpiExpr:
\_logic_net: (be), line:28
|vpiName:be
|vpiNetType:36
|vpiRange:
\_range: , line:28
|vpiLeftRange:
\_constant: , line:28
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiRightRange:
\_constant: , line:28
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (rnw)
|vpiName:rnw
|vpiDirection:1
|vpiExpr:
\_logic_net: (rnw), line:29
|vpiName:rnw
|vpiNetType:36
|vpiIODecl:
\_io_decl: (is_amo)
|vpiName:is_amo
|vpiDirection:1
|vpiExpr:
\_logic_net: (is_amo), line:30
|vpiName:is_amo
|vpiNetType:36
|vpiIODecl:
\_io_decl: (amo_type_or_burst_size)
|vpiName:amo_type_or_burst_size
|vpiDirection:1
|vpiExpr:
\_logic_net: (amo_type_or_burst_size), line:31
|vpiName:amo_type_or_burst_size
|vpiNetType:36
|vpiRange:
\_range: , line:31
|vpiLeftRange:
\_constant: , line:31
|vpiConstType:7
|vpiDecompile:4
|vpiSize:32
|INT:4
|vpiRightRange:
\_constant: , line:31
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (sub_id)
|vpiName:sub_id
|vpiDirection:1
|vpiExpr:
\_logic_net: (sub_id), line:32
|vpiName:sub_id
|vpiNetType:36
|vpiRange:
\_range: , line:32
|vpiLeftRange:
\_constant: , line:32
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:32
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (request_push)
|vpiName:request_push
|vpiDirection:1
|vpiExpr:
\_logic_net: (request_push), line:34
|vpiName:request_push
|vpiNetType:36
|vpiIODecl:
\_io_decl: (request_full)
|vpiName:request_full
|vpiDirection:2
|vpiExpr:
\_logic_net: (request_full), line:35
|vpiName:request_full
|vpiNetType:36
|vpiIODecl:
\_io_decl: (inv_addr)
|vpiName:inv_addr
|vpiDirection:2
|vpiExpr:
\_logic_net: (inv_addr), line:37
|vpiName:inv_addr
|vpiNetType:36
|vpiRange:
\_range: , line:37
|vpiLeftRange:
\_constant: , line:37
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:37
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiIODecl:
\_io_decl: (inv_valid)
|vpiName:inv_valid
|vpiDirection:2
|vpiExpr:
\_logic_net: (inv_valid), line:38
|vpiName:inv_valid
|vpiNetType:36
|vpiIODecl:
\_io_decl: (inv_ack)
|vpiName:inv_ack
|vpiDirection:1
|vpiExpr:
\_logic_net: (inv_ack), line:39
|vpiName:inv_ack
|vpiNetType:36
|vpiIODecl:
\_io_decl: (con_result)
|vpiName:con_result
|vpiDirection:2
|vpiExpr:
\_logic_net: (con_result), line:41
|vpiName:con_result
|vpiNetType:36
|vpiIODecl:
\_io_decl: (con_valid)
|vpiName:con_valid
|vpiDirection:2
|vpiExpr:
\_logic_net: (con_valid), line:42
|vpiName:con_valid
|vpiNetType:36
|vpiIODecl:
\_io_decl: (wr_data)
|vpiName:wr_data
|vpiDirection:1
|vpiExpr:
\_logic_net: (wr_data), line:44
|vpiName:wr_data
|vpiNetType:36
|vpiRange:
\_range: , line:44
|vpiLeftRange:
\_constant: , line:44
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:44
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (wr_data_push)
|vpiName:wr_data_push
|vpiDirection:1
|vpiExpr:
\_logic_net: (wr_data_push), line:45
|vpiName:wr_data_push
|vpiNetType:36
|vpiIODecl:
\_io_decl: (data_full)
|vpiName:data_full
|vpiDirection:2
|vpiExpr:
\_logic_net: (data_full), line:46
|vpiName:data_full
|vpiNetType:36
|vpiIODecl:
\_io_decl: (rd_data)
|vpiName:rd_data
|vpiDirection:2
|vpiExpr:
\_logic_net: (rd_data), line:48
|vpiName:rd_data
|vpiNetType:36
|vpiRange:
\_range: , line:48
|vpiLeftRange:
\_constant: , line:48
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:48
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (rd_sub_id)
|vpiName:rd_sub_id
|vpiDirection:2
|vpiExpr:
\_logic_net: (rd_sub_id), line:49
|vpiName:rd_sub_id
|vpiNetType:36
|vpiRange:
\_range: , line:49
|vpiLeftRange:
\_constant: , line:49
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:49
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (rd_data_valid)
|vpiName:rd_data_valid
|vpiDirection:2
|vpiExpr:
\_logic_net: (rd_data_valid), line:50
|vpiName:rd_data_valid
|vpiNetType:36
|vpiIODecl:
\_io_decl: (rd_data_ack)
|vpiName:rd_data_ack
|vpiDirection:1
|vpiExpr:
\_logic_net: (rd_data_ack), line:51
|vpiName:rd_data_ack
|vpiNetType:36
|vpiInterface:
\_interface: work@l2_requester_interface (request), file:third_party/cores/taiga/examples/zedboard/taiga_wrapper.sv, line:239
|vpiDefName:work@l2_requester_interface
|vpiName:request
|vpiModport:
\_modport: (master)
|vpiName:master
|vpiIODecl:
\_io_decl: (addr)
|vpiName:addr
|vpiDirection:2
|vpiExpr:
\_logic_net: (addr), line:27
|vpiIODecl:
\_io_decl: (be)
|vpiName:be
|vpiDirection:2
|vpiExpr:
\_logic_net: (be), line:28
|vpiIODecl:
\_io_decl: (rnw)
|vpiName:rnw
|vpiDirection:2
|vpiExpr:
\_logic_net: (rnw), line:29
|vpiIODecl:
\_io_decl: (is_amo)
|vpiName:is_amo
|vpiDirection:2
|vpiExpr:
\_logic_net: (is_amo), line:30
|vpiIODecl:
\_io_decl: (amo_type_or_burst_size)
|vpiName:amo_type_or_burst_size
|vpiDirection:2
|vpiExpr:
\_logic_net: (amo_type_or_burst_size), line:31
|vpiIODecl:
\_io_decl: (sub_id)
|vpiName:sub_id
|vpiDirection:2
|vpiExpr:
\_logic_net: (sub_id), line:32
|vpiIODecl:
\_io_decl: (request_push)
|vpiName:request_push
|vpiDirection:2
|vpiExpr:
\_logic_net: (request_push), line:34
|vpiIODecl:
\_io_decl: (request_full)
|vpiName:request_full
|vpiDirection:1
|vpiExpr:
\_logic_net: (request_full), line:35
|vpiIODecl:
\_io_decl: (inv_addr)
|vpiName:inv_addr
|vpiDirection:1
|vpiExpr:
\_logic_net: (inv_addr), line:37
|vpiIODecl:
\_io_decl: (inv_valid)
|vpiName:inv_valid
|vpiDirection:1
|vpiExpr:
\_logic_net: (inv_valid), line:38
|vpiIODecl:
\_io_decl: (inv_ack)
|vpiName:inv_ack
|vpiDirection:2
|vpiExpr:
\_logic_net: (inv_ack), line:39
|vpiIODecl:
\_io_decl: (con_result)
|vpiName:con_result
|vpiDirection:1
|vpiExpr:
\_logic_net: (con_result), line:41
|vpiIODecl:
\_io_decl: (con_valid)
|vpiName:con_valid
|vpiDirection:1
|vpiExpr:
\_logic_net: (con_valid), line:42
|vpiIODecl:
\_io_decl: (wr_data)
|vpiName:wr_data
|vpiDirection:2
|vpiExpr:
\_logic_net: (wr_data), line:44
|vpiIODecl:
\_io_decl: (wr_data_push)
|vpiName:wr_data_push
|vpiDirection:2
|vpiExpr:
\_logic_net: (wr_data_push), line:45
|vpiIODecl:
\_io_decl: (data_full)
|vpiName:data_full
|vpiDirection:1
|vpiExpr:
\_logic_net: (data_full), line:46
|vpiIODecl:
\_io_decl: (rd_data)
|vpiName:rd_data
|vpiDirection:1
|vpiExpr:
\_logic_net: (rd_data), line:48
|vpiIODecl:
\_io_decl: (rd_sub_id)
|vpiName:rd_sub_id
|vpiDirection:1
|vpiExpr:
\_logic_net: (rd_sub_id), line:49
|vpiIODecl:
\_io_decl: (rd_data_valid)
|vpiName:rd_data_valid
|vpiDirection:1
|vpiExpr:
\_logic_net: (rd_data_valid), line:50
|vpiIODecl:
\_io_decl: (rd_data_ack)
|vpiName:rd_data_ack
|vpiDirection:2
|vpiExpr:
\_logic_net: (rd_data_ack), line:51
|vpiInterface:
\_interface: work@l2_requester_interface (request), file:third_party/cores/taiga/examples/zedboard/taiga_wrapper.sv, line:239
|vpiModport:
\_modport: (slave)
|vpiPort:
\_port: (mem), line:31, parent:l2_arb
|vpiName:mem
|vpiDirection:5
|vpiHighConn:
\_ref_obj: (mem), line:239
|vpiName:mem
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_modport: (master)
|vpiName:master
|vpiIODecl:
\_io_decl: (addr)
|vpiName:addr
|vpiDirection:2
|vpiExpr:
\_logic_net: (addr), line:27
|vpiIODecl:
\_io_decl: (be)
|vpiName:be
|vpiDirection:2
|vpiExpr:
\_logic_net: (be), line:28
|vpiIODecl:
\_io_decl: (rnw)
|vpiName:rnw
|vpiDirection:2
|vpiExpr:
\_logic_net: (rnw), line:29
|vpiIODecl:
\_io_decl: (is_amo)
|vpiName:is_amo
|vpiDirection:2
|vpiExpr:
\_logic_net: (is_amo), line:30
|vpiIODecl:
\_io_decl: (amo_type_or_burst_size)
|vpiName:amo_type_or_burst_size
|vpiDirection:2
|vpiExpr:
\_logic_net: (amo_type_or_burst_size), line:31
|vpiIODecl:
\_io_decl: (id)
|vpiName:id
|vpiDirection:2
|vpiExpr:
\_logic_net: (id), line:75
|vpiName:id
|vpiNetType:36
|vpiRange:
\_range: , line:75
|vpiLeftRange:
\_constant: , line:75
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiRightRange:
\_constant: , line:75
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (request_valid)
|vpiName:request_valid
|vpiDirection:2
|vpiExpr:
\_logic_net: (request_valid), line:78
|vpiName:request_valid
|vpiNetType:36
|vpiIODecl:
\_io_decl: (abort)
|vpiName:abort
|vpiDirection:2
|vpiExpr:
\_logic_net: (abort), line:80
|vpiName:abort
|vpiNetType:36
|vpiIODecl:
\_io_decl: (request_pop)
|vpiName:request_pop
|vpiDirection:1
|vpiExpr:
\_logic_net: (request_pop), line:77
|vpiName:request_pop
|vpiNetType:36
|vpiIODecl:
\_io_decl: (wr_data)
|vpiName:wr_data
|vpiDirection:2
|vpiExpr:
\_logic_net: (wr_data), line:44
|vpiIODecl:
\_io_decl: (wr_data_valid)
|vpiName:wr_data_valid
|vpiDirection:2
|vpiExpr:
\_logic_net: (wr_data_valid), line:83
|vpiName:wr_data_valid
|vpiNetType:36
|vpiIODecl:
\_io_decl: (wr_data_read)
|vpiName:wr_data_read
|vpiDirection:1
|vpiExpr:
\_logic_net: (wr_data_read), line:84
|vpiName:wr_data_read
|vpiNetType:36
|vpiIODecl:
\_io_decl: (rd_data)
|vpiName:rd_data
|vpiDirection:1
|vpiExpr:
\_logic_net: (rd_data), line:48
|vpiIODecl:
\_io_decl: (rd_id)
|vpiName:rd_id
|vpiDirection:1
|vpiExpr:
\_logic_net: (rd_id), line:87
|vpiName:rd_id
|vpiNetType:36
|vpiRange:
\_range: , line:87
|vpiLeftRange:
\_constant: , line:87
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiRightRange:
\_constant: , line:87
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (rd_data_valid)
|vpiName:rd_data_valid
|vpiDirection:1
|vpiExpr:
\_logic_net: (rd_data_valid), line:50
|vpiInterface:
\_interface: work@l2_memory_interface (mem), file:third_party/cores/taiga/examples/zedboard/taiga_wrapper.sv, line:239
|vpiDefName:work@l2_memory_interface
|vpiName:mem
|vpiModport:
\_modport: (master)
|vpiModport:
\_modport: (slave)
|vpiName:slave
|vpiIODecl:
\_io_decl: (addr)
|vpiName:addr
|vpiDirection:1
|vpiExpr:
\_logic_net: (addr), line:27
|vpiIODecl:
\_io_decl: (be)
|vpiName:be
|vpiDirection:1
|vpiExpr:
\_logic_net: (be), line:28
|vpiIODecl:
\_io_decl: (rnw)
|vpiName:rnw
|vpiDirection:1
|vpiExpr:
\_logic_net: (rnw), line:29
|vpiIODecl:
\_io_decl: (is_amo)
|vpiName:is_amo
|vpiDirection:1
|vpiExpr:
\_logic_net: (is_amo), line:30
|vpiIODecl:
\_io_decl: (amo_type_or_burst_size)
|vpiName:amo_type_or_burst_size
|vpiDirection:1
|vpiExpr:
\_logic_net: (amo_type_or_burst_size), line:31
|vpiIODecl:
\_io_decl: (id)
|vpiName:id
|vpiDirection:1
|vpiExpr:
\_logic_net: (id), line:75
|vpiIODecl:
\_io_decl: (request_valid)
|vpiName:request_valid
|vpiDirection:1
|vpiExpr:
\_logic_net: (request_valid), line:78
|vpiIODecl:
\_io_decl: (abort)
|vpiName:abort
|vpiDirection:1
|vpiExpr:
\_logic_net: (abort), line:80
|vpiIODecl:
\_io_decl: (request_pop)
|vpiName:request_pop
|vpiDirection:2
|vpiExpr:
\_logic_net: (request_pop), line:77
|vpiIODecl:
\_io_decl: (wr_data)
|vpiName:wr_data
|vpiDirection:1
|vpiExpr:
\_logic_net: (wr_data), line:44
|vpiIODecl:
\_io_decl: (wr_data_valid)
|vpiName:wr_data_valid
|vpiDirection:1
|vpiExpr:
\_logic_net: (wr_data_valid), line:83
|vpiIODecl:
\_io_decl: (wr_data_read)
|vpiName:wr_data_read
|vpiDirection:2
|vpiExpr:
\_logic_net: (wr_data_read), line:84
|vpiIODecl:
\_io_decl: (rd_data)
|vpiName:rd_data
|vpiDirection:2
|vpiExpr:
\_logic_net: (rd_data), line:48
|vpiIODecl:
\_io_decl: (rd_id)
|vpiName:rd_id
|vpiDirection:2
|vpiExpr:
\_logic_net: (rd_id), line:87
|vpiIODecl:
\_io_decl: (rd_data_valid)
|vpiName:rd_data_valid
|vpiDirection:2
|vpiExpr:
\_logic_net: (rd_data_valid), line:50
|vpiInterface:
\_interface: work@l2_memory_interface (mem), file:third_party/cores/taiga/examples/zedboard/taiga_wrapper.sv, line:239
|vpiInterface:
\_interface: work@l2_arbitration_interface (arb), file:third_party/cores/taiga/l2_arbiter/l2_arbiter.sv, line:34, parent:l2_arb
|vpiDefName:work@l2_arbitration_interface
|vpiName:arb
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.arb
|vpiModport:
\_modport: (master), parent:arb
|vpiName:master
|vpiIODecl:
\_io_decl: (requests), parent:master
|vpiName:requests
|vpiDirection:2
|vpiIODecl:
\_io_decl: (strobe), parent:master
|vpiName:strobe
|vpiDirection:2
|vpiIODecl:
\_io_decl: (grantee_i), parent:master
|vpiName:grantee_i
|vpiDirection:1
|vpiIODecl:
\_io_decl: (grantee_v), parent:master
|vpiName:grantee_v
|vpiDirection:1
|vpiIODecl:
\_io_decl: (grantee_valid), parent:master
|vpiName:grantee_valid
|vpiDirection:1
|vpiInterface:
\_interface: work@l2_arbitration_interface (arb), file:third_party/cores/taiga/l2_arbiter/l2_arbiter.sv, line:34, parent:l2_arb
|vpiModport:
\_modport: (slave), parent:arb
|vpiName:slave
|vpiIODecl:
\_io_decl: (requests), parent:slave
|vpiName:requests
|vpiDirection:1
|vpiIODecl:
\_io_decl: (strobe), parent:slave
|vpiName:strobe
|vpiDirection:1
|vpiIODecl:
\_io_decl: (grantee_i), parent:slave
|vpiName:grantee_i
|vpiDirection:2
|vpiIODecl:
\_io_decl: (grantee_v), parent:slave
|vpiName:grantee_v
|vpiDirection:2
|vpiIODecl:
\_io_decl: (grantee_valid), parent:slave
|vpiName:grantee_valid
|vpiDirection:2
|vpiInterface:
\_interface: work@l2_arbitration_interface (arb), file:third_party/cores/taiga/l2_arbiter/l2_arbiter.sv, line:34, parent:l2_arb
|vpiNet:
\_logic_net: (requests), line:39, parent:arb
|vpiName:requests
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.arb.requests
|vpiNetType:36
|vpiRange:
\_range: , line:39
|vpiLeftRange:
\_constant: , line:39
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:39
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (grantee_i), line:40, parent:arb
|vpiName:grantee_i
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.arb.grantee_i
|vpiNetType:36
|vpiRange:
\_range: , line:40
|vpiLeftRange:
\_constant: , line:40
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiRightRange:
\_constant: , line:40
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (grantee_v), line:41, parent:arb
|vpiName:grantee_v
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.arb.grantee_v
|vpiNetType:36
|vpiRange:
\_range: , line:41
|vpiLeftRange:
\_constant: , line:41
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:41
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (grantee_valid), line:42, parent:arb
|vpiName:grantee_valid
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.arb.grantee_valid
|vpiNetType:36
|vpiNet:
\_logic_net: (strobe), line:43, parent:arb
|vpiName:strobe
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.arb.strobe
|vpiNetType:36
|vpiInstance:
\_module: work@l2_arbiter (l2_arb), file:third_party/cores/taiga/examples/zedboard/taiga_wrapper.sv, line:239
|vpiInterface:
\_interface: work@l2_fifo_interface (input_fifos0), file:third_party/cores/taiga/l2_arbiter/l2_arbiter.sv, line:37, parent:l2_arb
|vpiDefName:work@l2_fifo_interface
|vpiName:input_fifos0
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.input_fifos0
|vpiModport:
\_modport: (dequeue), parent:input_fifos0
|vpiName:dequeue
|vpiIODecl:
\_io_decl: (valid), parent:dequeue
|vpiName:valid
|vpiDirection:1
|vpiIODecl:
\_io_decl: (data_out), parent:dequeue
|vpiName:data_out
|vpiDirection:1
|vpiIODecl:
\_io_decl: (pop), parent:dequeue
|vpiName:pop
|vpiDirection:2
|vpiInterface:
\_interface: work@l2_fifo_interface (input_fifos0), file:third_party/cores/taiga/l2_arbiter/l2_arbiter.sv, line:37, parent:l2_arb
|vpiModport:
\_modport: (enqueue), parent:input_fifos0
|vpiName:enqueue
|vpiIODecl:
\_io_decl: (full), parent:enqueue
|vpiName:full
|vpiDirection:1
|vpiIODecl:
\_io_decl: (empty), parent:enqueue
|vpiName:empty
|vpiDirection:1
|vpiIODecl:
\_io_decl: (data_in), parent:enqueue
|vpiName:data_in
|vpiDirection:2
|vpiIODecl:
\_io_decl: (push), parent:enqueue
|vpiName:push
|vpiDirection:2
|vpiInterface:
\_interface: work@l2_fifo_interface (input_fifos0), file:third_party/cores/taiga/l2_arbiter/l2_arbiter.sv, line:37, parent:l2_arb
|vpiModport:
\_modport: (structure), parent:input_fifos0
|vpiName:structure
|vpiIODecl:
\_io_decl: (push), parent:structure
|vpiName:push
|vpiDirection:1
|vpiIODecl:
\_io_decl: (pop), parent:structure
|vpiName:pop
|vpiDirection:1
|vpiIODecl:
\_io_decl: (data_in), parent:structure
|vpiName:data_in
|vpiDirection:1
|vpiIODecl:
\_io_decl: (data_out), parent:structure
|vpiName:data_out
|vpiDirection:2
|vpiIODecl:
\_io_decl: (valid), parent:structure
|vpiName:valid
|vpiDirection:2
|vpiIODecl:
\_io_decl: (full), parent:structure
|vpiName:full
|vpiDirection:2
|vpiIODecl:
\_io_decl: (empty), parent:structure
|vpiName:empty
|vpiDirection:2
|vpiInterface:
\_interface: work@l2_fifo_interface (input_fifos0), file:third_party/cores/taiga/l2_arbiter/l2_arbiter.sv, line:37, parent:l2_arb
|vpiNet:
\_logic_net: (push), line:26, parent:input_fifos0
|vpiName:push
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.input_fifos0.push
|vpiNetType:36
|vpiNet:
\_logic_net: (pop), line:27, parent:input_fifos0
|vpiName:pop
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.input_fifos0.pop
|vpiNetType:36
|vpiNet:
\_logic_net: (data_in), line:28, parent:input_fifos0
|vpiName:data_in
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.input_fifos0.data_in
|vpiNetType:36
|vpiRange:
\_range: , line:28
|vpiLeftRange:
\_constant: , line:28
|vpiDecompile:-1
|INT:-1
|vpiRightRange:
\_constant: , line:28
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (data_out), line:29, parent:input_fifos0
|vpiName:data_out
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.input_fifos0.data_out
|vpiNetType:36
|vpiRange:
\_range: , line:29
|vpiLeftRange:
\_constant: , line:29
|vpiDecompile:-1
|INT:-1
|vpiRightRange:
\_constant: , line:29
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (valid), line:30, parent:input_fifos0
|vpiName:valid
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.input_fifos0.valid
|vpiNetType:36
|vpiNet:
\_logic_net: (full), line:31, parent:input_fifos0
|vpiName:full
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.input_fifos0.full
|vpiNetType:36
|vpiNet:
\_logic_net: (empty), line:32, parent:input_fifos0
|vpiName:empty
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.input_fifos0.empty
|vpiNetType:36
|vpiInstance:
\_module: work@l2_arbiter (l2_arb), file:third_party/cores/taiga/examples/zedboard/taiga_wrapper.sv, line:239
|vpiInterface:
\_interface: work@l2_fifo_interface (input_fifos1), file:third_party/cores/taiga/l2_arbiter/l2_arbiter.sv, line:37, parent:l2_arb
|vpiDefName:work@l2_fifo_interface
|vpiName:input_fifos1
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.input_fifos1
|vpiModport:
\_modport: (dequeue), parent:input_fifos1
|vpiName:dequeue
|vpiIODecl:
\_io_decl: (valid), parent:dequeue
|vpiName:valid
|vpiDirection:1
|vpiIODecl:
\_io_decl: (data_out), parent:dequeue
|vpiName:data_out
|vpiDirection:1
|vpiIODecl:
\_io_decl: (pop), parent:dequeue
|vpiName:pop
|vpiDirection:2
|vpiInterface:
\_interface: work@l2_fifo_interface (input_fifos1), file:third_party/cores/taiga/l2_arbiter/l2_arbiter.sv, line:37, parent:l2_arb
|vpiModport:
\_modport: (enqueue), parent:input_fifos1
|vpiName:enqueue
|vpiIODecl:
\_io_decl: (full), parent:enqueue
|vpiName:full
|vpiDirection:1
|vpiIODecl:
\_io_decl: (empty), parent:enqueue
|vpiName:empty
|vpiDirection:1
|vpiIODecl:
\_io_decl: (data_in), parent:enqueue
|vpiName:data_in
|vpiDirection:2
|vpiIODecl:
\_io_decl: (push), parent:enqueue
|vpiName:push
|vpiDirection:2
|vpiInterface:
\_interface: work@l2_fifo_interface (input_fifos1), file:third_party/cores/taiga/l2_arbiter/l2_arbiter.sv, line:37, parent:l2_arb
|vpiModport:
\_modport: (structure), parent:input_fifos1
|vpiName:structure
|vpiIODecl:
\_io_decl: (push), parent:structure
|vpiName:push
|vpiDirection:1
|vpiIODecl:
\_io_decl: (pop), parent:structure
|vpiName:pop
|vpiDirection:1
|vpiIODecl:
\_io_decl: (data_in), parent:structure
|vpiName:data_in
|vpiDirection:1
|vpiIODecl:
\_io_decl: (data_out), parent:structure
|vpiName:data_out
|vpiDirection:2
|vpiIODecl:
\_io_decl: (valid), parent:structure
|vpiName:valid
|vpiDirection:2
|vpiIODecl:
\_io_decl: (full), parent:structure
|vpiName:full
|vpiDirection:2
|vpiIODecl:
\_io_decl: (empty), parent:structure
|vpiName:empty
|vpiDirection:2
|vpiInterface:
\_interface: work@l2_fifo_interface (input_fifos1), file:third_party/cores/taiga/l2_arbiter/l2_arbiter.sv, line:37, parent:l2_arb
|vpiNet:
\_logic_net: (push), line:26, parent:input_fifos1
|vpiName:push
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.input_fifos1.push
|vpiNetType:36
|vpiNet:
\_logic_net: (pop), line:27, parent:input_fifos1
|vpiName:pop
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.input_fifos1.pop
|vpiNetType:36
|vpiNet:
\_logic_net: (data_in), line:28, parent:input_fifos1
|vpiName:data_in
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.input_fifos1.data_in
|vpiNetType:36
|vpiRange:
\_range: , line:28
|vpiLeftRange:
\_constant: , line:28
|vpiDecompile:-1
|INT:-1
|vpiRightRange:
\_constant: , line:28
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (data_out), line:29, parent:input_fifos1
|vpiName:data_out
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.input_fifos1.data_out
|vpiNetType:36
|vpiRange:
\_range: , line:29
|vpiLeftRange:
\_constant: , line:29
|vpiDecompile:-1
|INT:-1
|vpiRightRange:
\_constant: , line:29
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (valid), line:30, parent:input_fifos1
|vpiName:valid
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.input_fifos1.valid
|vpiNetType:36
|vpiNet:
\_logic_net: (full), line:31, parent:input_fifos1
|vpiName:full
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.input_fifos1.full
|vpiNetType:36
|vpiNet:
\_logic_net: (empty), line:32, parent:input_fifos1
|vpiName:empty
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.input_fifos1.empty
|vpiNetType:36
|vpiInstance:
\_module: work@l2_arbiter (l2_arb), file:third_party/cores/taiga/examples/zedboard/taiga_wrapper.sv, line:239
|vpiInterface:
\_interface: work@l2_fifo_interface (input_data_fifos0), file:third_party/cores/taiga/l2_arbiter/l2_arbiter.sv, line:38, parent:l2_arb
|vpiDefName:work@l2_fifo_interface
|vpiName:input_data_fifos0
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.input_data_fifos0
|vpiModport:
\_modport: (dequeue), parent:input_data_fifos0
|vpiName:dequeue
|vpiIODecl:
\_io_decl: (valid), parent:dequeue
|vpiName:valid
|vpiDirection:1
|vpiIODecl:
\_io_decl: (data_out), parent:dequeue
|vpiName:data_out
|vpiDirection:1
|vpiIODecl:
\_io_decl: (pop), parent:dequeue
|vpiName:pop
|vpiDirection:2
|vpiInterface:
\_interface: work@l2_fifo_interface (input_data_fifos0), file:third_party/cores/taiga/l2_arbiter/l2_arbiter.sv, line:38, parent:l2_arb
|vpiModport:
\_modport: (enqueue), parent:input_data_fifos0
|vpiName:enqueue
|vpiIODecl:
\_io_decl: (full), parent:enqueue
|vpiName:full
|vpiDirection:1
|vpiIODecl:
\_io_decl: (empty), parent:enqueue
|vpiName:empty
|vpiDirection:1
|vpiIODecl:
\_io_decl: (data_in), parent:enqueue
|vpiName:data_in
|vpiDirection:2
|vpiIODecl:
\_io_decl: (push), parent:enqueue
|vpiName:push
|vpiDirection:2
|vpiInterface:
\_interface: work@l2_fifo_interface (input_data_fifos0), file:third_party/cores/taiga/l2_arbiter/l2_arbiter.sv, line:38, parent:l2_arb
|vpiModport:
\_modport: (structure), parent:input_data_fifos0
|vpiName:structure
|vpiIODecl:
\_io_decl: (push), parent:structure
|vpiName:push
|vpiDirection:1
|vpiIODecl:
\_io_decl: (pop), parent:structure
|vpiName:pop
|vpiDirection:1
|vpiIODecl:
\_io_decl: (data_in), parent:structure
|vpiName:data_in
|vpiDirection:1
|vpiIODecl:
\_io_decl: (data_out), parent:structure
|vpiName:data_out
|vpiDirection:2
|vpiIODecl:
\_io_decl: (valid), parent:structure
|vpiName:valid
|vpiDirection:2
|vpiIODecl:
\_io_decl: (full), parent:structure
|vpiName:full
|vpiDirection:2
|vpiIODecl:
\_io_decl: (empty), parent:structure
|vpiName:empty
|vpiDirection:2
|vpiInterface:
\_interface: work@l2_fifo_interface (input_data_fifos0), file:third_party/cores/taiga/l2_arbiter/l2_arbiter.sv, line:38, parent:l2_arb
|vpiNet:
\_logic_net: (push), line:26, parent:input_data_fifos0
|vpiName:push
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.input_data_fifos0.push
|vpiNetType:36
|vpiNet:
\_logic_net: (pop), line:27, parent:input_data_fifos0
|vpiName:pop
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.input_data_fifos0.pop
|vpiNetType:36
|vpiNet:
\_logic_net: (data_in), line:28, parent:input_data_fifos0
|vpiName:data_in
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.input_data_fifos0.data_in
|vpiNetType:36
|vpiRange:
\_range: , line:28
|vpiLeftRange:
\_constant: , line:28
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:28
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (data_out), line:29, parent:input_data_fifos0
|vpiName:data_out
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.input_data_fifos0.data_out
|vpiNetType:36
|vpiRange:
\_range: , line:29
|vpiLeftRange:
\_constant: , line:29
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:29
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (valid), line:30, parent:input_data_fifos0
|vpiName:valid
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.input_data_fifos0.valid
|vpiNetType:36
|vpiNet:
\_logic_net: (full), line:31, parent:input_data_fifos0
|vpiName:full
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.input_data_fifos0.full
|vpiNetType:36
|vpiNet:
\_logic_net: (empty), line:32, parent:input_data_fifos0
|vpiName:empty
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.input_data_fifos0.empty
|vpiNetType:36
|vpiInstance:
\_module: work@l2_arbiter (l2_arb), file:third_party/cores/taiga/examples/zedboard/taiga_wrapper.sv, line:239
|vpiInterface:
\_interface: work@l2_fifo_interface (input_data_fifos1), file:third_party/cores/taiga/l2_arbiter/l2_arbiter.sv, line:38, parent:l2_arb
|vpiDefName:work@l2_fifo_interface
|vpiName:input_data_fifos1
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.input_data_fifos1
|vpiModport:
\_modport: (dequeue), parent:input_data_fifos1
|vpiName:dequeue
|vpiIODecl:
\_io_decl: (valid), parent:dequeue
|vpiName:valid
|vpiDirection:1
|vpiIODecl:
\_io_decl: (data_out), parent:dequeue
|vpiName:data_out
|vpiDirection:1
|vpiIODecl:
\_io_decl: (pop), parent:dequeue
|vpiName:pop
|vpiDirection:2
|vpiInterface:
\_interface: work@l2_fifo_interface (input_data_fifos1), file:third_party/cores/taiga/l2_arbiter/l2_arbiter.sv, line:38, parent:l2_arb
|vpiModport:
\_modport: (enqueue), parent:input_data_fifos1
|vpiName:enqueue
|vpiIODecl:
\_io_decl: (full), parent:enqueue
|vpiName:full
|vpiDirection:1
|vpiIODecl:
\_io_decl: (empty), parent:enqueue
|vpiName:empty
|vpiDirection:1
|vpiIODecl:
\_io_decl: (data_in), parent:enqueue
|vpiName:data_in
|vpiDirection:2
|vpiIODecl:
\_io_decl: (push), parent:enqueue
|vpiName:push
|vpiDirection:2
|vpiInterface:
\_interface: work@l2_fifo_interface (input_data_fifos1), file:third_party/cores/taiga/l2_arbiter/l2_arbiter.sv, line:38, parent:l2_arb
|vpiModport:
\_modport: (structure), parent:input_data_fifos1
|vpiName:structure
|vpiIODecl:
\_io_decl: (push), parent:structure
|vpiName:push
|vpiDirection:1
|vpiIODecl:
\_io_decl: (pop), parent:structure
|vpiName:pop
|vpiDirection:1
|vpiIODecl:
\_io_decl: (data_in), parent:structure
|vpiName:data_in
|vpiDirection:1
|vpiIODecl:
\_io_decl: (data_out), parent:structure
|vpiName:data_out
|vpiDirection:2
|vpiIODecl:
\_io_decl: (valid), parent:structure
|vpiName:valid
|vpiDirection:2
|vpiIODecl:
\_io_decl: (full), parent:structure
|vpiName:full
|vpiDirection:2
|vpiIODecl:
\_io_decl: (empty), parent:structure
|vpiName:empty
|vpiDirection:2
|vpiInterface:
\_interface: work@l2_fifo_interface (input_data_fifos1), file:third_party/cores/taiga/l2_arbiter/l2_arbiter.sv, line:38, parent:l2_arb
|vpiNet:
\_logic_net: (push), line:26, parent:input_data_fifos1
|vpiName:push
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.input_data_fifos1.push
|vpiNetType:36
|vpiNet:
\_logic_net: (pop), line:27, parent:input_data_fifos1
|vpiName:pop
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.input_data_fifos1.pop
|vpiNetType:36
|vpiNet:
\_logic_net: (data_in), line:28, parent:input_data_fifos1
|vpiName:data_in
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.input_data_fifos1.data_in
|vpiNetType:36
|vpiRange:
\_range: , line:28
|vpiLeftRange:
\_constant: , line:28
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:28
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (data_out), line:29, parent:input_data_fifos1
|vpiName:data_out
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.input_data_fifos1.data_out
|vpiNetType:36
|vpiRange:
\_range: , line:29
|vpiLeftRange:
\_constant: , line:29
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:29
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (valid), line:30, parent:input_data_fifos1
|vpiName:valid
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.input_data_fifos1.valid
|vpiNetType:36
|vpiNet:
\_logic_net: (full), line:31, parent:input_data_fifos1
|vpiName:full
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.input_data_fifos1.full
|vpiNetType:36
|vpiNet:
\_logic_net: (empty), line:32, parent:input_data_fifos1
|vpiName:empty
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.input_data_fifos1.empty
|vpiNetType:36
|vpiInstance:
\_module: work@l2_arbiter (l2_arb), file:third_party/cores/taiga/examples/zedboard/taiga_wrapper.sv, line:239
|vpiInterface:
\_interface: work@l2_fifo_interface (inv_response_fifos0), file:third_party/cores/taiga/l2_arbiter/l2_arbiter.sv, line:39, parent:l2_arb
|vpiDefName:work@l2_fifo_interface
|vpiName:inv_response_fifos0
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.inv_response_fifos0
|vpiModport:
\_modport: (dequeue), parent:inv_response_fifos0
|vpiName:dequeue
|vpiIODecl:
\_io_decl: (valid), parent:dequeue
|vpiName:valid
|vpiDirection:1
|vpiIODecl:
\_io_decl: (data_out), parent:dequeue
|vpiName:data_out
|vpiDirection:1
|vpiIODecl:
\_io_decl: (pop), parent:dequeue
|vpiName:pop
|vpiDirection:2
|vpiInterface:
\_interface: work@l2_fifo_interface (inv_response_fifos0), file:third_party/cores/taiga/l2_arbiter/l2_arbiter.sv, line:39, parent:l2_arb
|vpiModport:
\_modport: (enqueue), parent:inv_response_fifos0
|vpiName:enqueue
|vpiIODecl:
\_io_decl: (full), parent:enqueue
|vpiName:full
|vpiDirection:1
|vpiIODecl:
\_io_decl: (empty), parent:enqueue
|vpiName:empty
|vpiDirection:1
|vpiIODecl:
\_io_decl: (data_in), parent:enqueue
|vpiName:data_in
|vpiDirection:2
|vpiIODecl:
\_io_decl: (push), parent:enqueue
|vpiName:push
|vpiDirection:2
|vpiInterface:
\_interface: work@l2_fifo_interface (inv_response_fifos0), file:third_party/cores/taiga/l2_arbiter/l2_arbiter.sv, line:39, parent:l2_arb
|vpiModport:
\_modport: (structure), parent:inv_response_fifos0
|vpiName:structure
|vpiIODecl:
\_io_decl: (push), parent:structure
|vpiName:push
|vpiDirection:1
|vpiIODecl:
\_io_decl: (pop), parent:structure
|vpiName:pop
|vpiDirection:1
|vpiIODecl:
\_io_decl: (data_in), parent:structure
|vpiName:data_in
|vpiDirection:1
|vpiIODecl:
\_io_decl: (data_out), parent:structure
|vpiName:data_out
|vpiDirection:2
|vpiIODecl:
\_io_decl: (valid), parent:structure
|vpiName:valid
|vpiDirection:2
|vpiIODecl:
\_io_decl: (full), parent:structure
|vpiName:full
|vpiDirection:2
|vpiIODecl:
\_io_decl: (empty), parent:structure
|vpiName:empty
|vpiDirection:2
|vpiInterface:
\_interface: work@l2_fifo_interface (inv_response_fifos0), file:third_party/cores/taiga/l2_arbiter/l2_arbiter.sv, line:39, parent:l2_arb
|vpiNet:
\_logic_net: (push), line:26, parent:inv_response_fifos0
|vpiName:push
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.inv_response_fifos0.push
|vpiNetType:36
|vpiNet:
\_logic_net: (pop), line:27, parent:inv_response_fifos0
|vpiName:pop
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.inv_response_fifos0.pop
|vpiNetType:36
|vpiNet:
\_logic_net: (data_in), line:28, parent:inv_response_fifos0
|vpiName:data_in
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.inv_response_fifos0.data_in
|vpiNetType:36
|vpiRange:
\_range: , line:28
|vpiLeftRange:
\_constant: , line:28
|vpiConstType:7
|vpiDecompile:29
|vpiSize:32
|INT:29
|vpiRightRange:
\_constant: , line:28
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (data_out), line:29, parent:inv_response_fifos0
|vpiName:data_out
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.inv_response_fifos0.data_out
|vpiNetType:36
|vpiRange:
\_range: , line:29
|vpiLeftRange:
\_constant: , line:29
|vpiConstType:7
|vpiDecompile:29
|vpiSize:32
|INT:29
|vpiRightRange:
\_constant: , line:29
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (valid), line:30, parent:inv_response_fifos0
|vpiName:valid
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.inv_response_fifos0.valid
|vpiNetType:36
|vpiNet:
\_logic_net: (full), line:31, parent:inv_response_fifos0
|vpiName:full
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.inv_response_fifos0.full
|vpiNetType:36
|vpiNet:
\_logic_net: (empty), line:32, parent:inv_response_fifos0
|vpiName:empty
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.inv_response_fifos0.empty
|vpiNetType:36
|vpiInstance:
\_module: work@l2_arbiter (l2_arb), file:third_party/cores/taiga/examples/zedboard/taiga_wrapper.sv, line:239
|vpiInterface:
\_interface: work@l2_fifo_interface (inv_response_fifos1), file:third_party/cores/taiga/l2_arbiter/l2_arbiter.sv, line:39, parent:l2_arb
|vpiDefName:work@l2_fifo_interface
|vpiName:inv_response_fifos1
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.inv_response_fifos1
|vpiModport:
\_modport: (dequeue), parent:inv_response_fifos1
|vpiName:dequeue
|vpiIODecl:
\_io_decl: (valid), parent:dequeue
|vpiName:valid
|vpiDirection:1
|vpiIODecl:
\_io_decl: (data_out), parent:dequeue
|vpiName:data_out
|vpiDirection:1
|vpiIODecl:
\_io_decl: (pop), parent:dequeue
|vpiName:pop
|vpiDirection:2
|vpiInterface:
\_interface: work@l2_fifo_interface (inv_response_fifos1), file:third_party/cores/taiga/l2_arbiter/l2_arbiter.sv, line:39, parent:l2_arb
|vpiModport:
\_modport: (enqueue), parent:inv_response_fifos1
|vpiName:enqueue
|vpiIODecl:
\_io_decl: (full), parent:enqueue
|vpiName:full
|vpiDirection:1
|vpiIODecl:
\_io_decl: (empty), parent:enqueue
|vpiName:empty
|vpiDirection:1
|vpiIODecl:
\_io_decl: (data_in), parent:enqueue
|vpiName:data_in
|vpiDirection:2
|vpiIODecl:
\_io_decl: (push), parent:enqueue
|vpiName:push
|vpiDirection:2
|vpiInterface:
\_interface: work@l2_fifo_interface (inv_response_fifos1), file:third_party/cores/taiga/l2_arbiter/l2_arbiter.sv, line:39, parent:l2_arb
|vpiModport:
\_modport: (structure), parent:inv_response_fifos1
|vpiName:structure
|vpiIODecl:
\_io_decl: (push), parent:structure
|vpiName:push
|vpiDirection:1
|vpiIODecl:
\_io_decl: (pop), parent:structure
|vpiName:pop
|vpiDirection:1
|vpiIODecl:
\_io_decl: (data_in), parent:structure
|vpiName:data_in
|vpiDirection:1
|vpiIODecl:
\_io_decl: (data_out), parent:structure
|vpiName:data_out
|vpiDirection:2
|vpiIODecl:
\_io_decl: (valid), parent:structure
|vpiName:valid
|vpiDirection:2
|vpiIODecl:
\_io_decl: (full), parent:structure
|vpiName:full
|vpiDirection:2
|vpiIODecl:
\_io_decl: (empty), parent:structure
|vpiName:empty
|vpiDirection:2
|vpiInterface:
\_interface: work@l2_fifo_interface (inv_response_fifos1), file:third_party/cores/taiga/l2_arbiter/l2_arbiter.sv, line:39, parent:l2_arb
|vpiNet:
\_logic_net: (push), line:26, parent:inv_response_fifos1
|vpiName:push
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.inv_response_fifos1.push
|vpiNetType:36
|vpiNet:
\_logic_net: (pop), line:27, parent:inv_response_fifos1
|vpiName:pop
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.inv_response_fifos1.pop
|vpiNetType:36
|vpiNet:
\_logic_net: (data_in), line:28, parent:inv_response_fifos1
|vpiName:data_in
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.inv_response_fifos1.data_in
|vpiNetType:36
|vpiRange:
\_range: , line:28
|vpiLeftRange:
\_constant: , line:28
|vpiConstType:7
|vpiDecompile:29
|vpiSize:32
|INT:29
|vpiRightRange:
\_constant: , line:28
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (data_out), line:29, parent:inv_response_fifos1
|vpiName:data_out
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.inv_response_fifos1.data_out
|vpiNetType:36
|vpiRange:
\_range: , line:29
|vpiLeftRange:
\_constant: , line:29
|vpiConstType:7
|vpiDecompile:29
|vpiSize:32
|INT:29
|vpiRightRange:
\_constant: , line:29
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (valid), line:30, parent:inv_response_fifos1
|vpiName:valid
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.inv_response_fifos1.valid
|vpiNetType:36
|vpiNet:
\_logic_net: (full), line:31, parent:inv_response_fifos1
|vpiName:full
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.inv_response_fifos1.full
|vpiNetType:36
|vpiNet:
\_logic_net: (empty), line:32, parent:inv_response_fifos1
|vpiName:empty
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.inv_response_fifos1.empty
|vpiNetType:36
|vpiInstance:
\_module: work@l2_arbiter (l2_arb), file:third_party/cores/taiga/examples/zedboard/taiga_wrapper.sv, line:239
|vpiInterface:
\_interface: work@l2_fifo_interface (returndata_fifos0), file:third_party/cores/taiga/l2_arbiter/l2_arbiter.sv, line:40, parent:l2_arb
|vpiDefName:work@l2_fifo_interface
|vpiName:returndata_fifos0
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.returndata_fifos0
|vpiModport:
\_modport: (dequeue), parent:returndata_fifos0
|vpiName:dequeue
|vpiIODecl:
\_io_decl: (valid), parent:dequeue
|vpiName:valid
|vpiDirection:1
|vpiIODecl:
\_io_decl: (data_out), parent:dequeue
|vpiName:data_out
|vpiDirection:1
|vpiIODecl:
\_io_decl: (pop), parent:dequeue
|vpiName:pop
|vpiDirection:2
|vpiInterface:
\_interface: work@l2_fifo_interface (returndata_fifos0), file:third_party/cores/taiga/l2_arbiter/l2_arbiter.sv, line:40, parent:l2_arb
|vpiModport:
\_modport: (enqueue), parent:returndata_fifos0
|vpiName:enqueue
|vpiIODecl:
\_io_decl: (full), parent:enqueue
|vpiName:full
|vpiDirection:1
|vpiIODecl:
\_io_decl: (empty), parent:enqueue
|vpiName:empty
|vpiDirection:1
|vpiIODecl:
\_io_decl: (data_in), parent:enqueue
|vpiName:data_in
|vpiDirection:2
|vpiIODecl:
\_io_decl: (push), parent:enqueue
|vpiName:push
|vpiDirection:2
|vpiInterface:
\_interface: work@l2_fifo_interface (returndata_fifos0), file:third_party/cores/taiga/l2_arbiter/l2_arbiter.sv, line:40, parent:l2_arb
|vpiModport:
\_modport: (structure), parent:returndata_fifos0
|vpiName:structure
|vpiIODecl:
\_io_decl: (push), parent:structure
|vpiName:push
|vpiDirection:1
|vpiIODecl:
\_io_decl: (pop), parent:structure
|vpiName:pop
|vpiDirection:1
|vpiIODecl:
\_io_decl: (data_in), parent:structure
|vpiName:data_in
|vpiDirection:1
|vpiIODecl:
\_io_decl: (data_out), parent:structure
|vpiName:data_out
|vpiDirection:2
|vpiIODecl:
\_io_decl: (valid), parent:structure
|vpiName:valid
|vpiDirection:2
|vpiIODecl:
\_io_decl: (full), parent:structure
|vpiName:full
|vpiDirection:2
|vpiIODecl:
\_io_decl: (empty), parent:structure
|vpiName:empty
|vpiDirection:2
|vpiInterface:
\_interface: work@l2_fifo_interface (returndata_fifos0), file:third_party/cores/taiga/l2_arbiter/l2_arbiter.sv, line:40, parent:l2_arb
|vpiNet:
\_logic_net: (push), line:26, parent:returndata_fifos0
|vpiName:push
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.returndata_fifos0.push
|vpiNetType:36
|vpiNet:
\_logic_net: (pop), line:27, parent:returndata_fifos0
|vpiName:pop
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.returndata_fifos0.pop
|vpiNetType:36
|vpiNet:
\_logic_net: (data_in), line:28, parent:returndata_fifos0
|vpiName:data_in
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.returndata_fifos0.data_in
|vpiNetType:36
|vpiRange:
\_range: , line:28
|vpiLeftRange:
\_constant: , line:28
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:28
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (data_out), line:29, parent:returndata_fifos0
|vpiName:data_out
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.returndata_fifos0.data_out
|vpiNetType:36
|vpiRange:
\_range: , line:29
|vpiLeftRange:
\_constant: , line:29
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:29
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (valid), line:30, parent:returndata_fifos0
|vpiName:valid
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.returndata_fifos0.valid
|vpiNetType:36
|vpiNet:
\_logic_net: (full), line:31, parent:returndata_fifos0
|vpiName:full
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.returndata_fifos0.full
|vpiNetType:36
|vpiNet:
\_logic_net: (empty), line:32, parent:returndata_fifos0
|vpiName:empty
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.returndata_fifos0.empty
|vpiNetType:36
|vpiInstance:
\_module: work@l2_arbiter (l2_arb), file:third_party/cores/taiga/examples/zedboard/taiga_wrapper.sv, line:239
|vpiInterface:
\_interface: work@l2_fifo_interface (returndata_fifos1), file:third_party/cores/taiga/l2_arbiter/l2_arbiter.sv, line:40, parent:l2_arb
|vpiDefName:work@l2_fifo_interface
|vpiName:returndata_fifos1
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.returndata_fifos1
|vpiModport:
\_modport: (dequeue), parent:returndata_fifos1
|vpiName:dequeue
|vpiIODecl:
\_io_decl: (valid), parent:dequeue
|vpiName:valid
|vpiDirection:1
|vpiIODecl:
\_io_decl: (data_out), parent:dequeue
|vpiName:data_out
|vpiDirection:1
|vpiIODecl:
\_io_decl: (pop), parent:dequeue
|vpiName:pop
|vpiDirection:2
|vpiInterface:
\_interface: work@l2_fifo_interface (returndata_fifos1), file:third_party/cores/taiga/l2_arbiter/l2_arbiter.sv, line:40, parent:l2_arb
|vpiModport:
\_modport: (enqueue), parent:returndata_fifos1
|vpiName:enqueue
|vpiIODecl:
\_io_decl: (full), parent:enqueue
|vpiName:full
|vpiDirection:1
|vpiIODecl:
\_io_decl: (empty), parent:enqueue
|vpiName:empty
|vpiDirection:1
|vpiIODecl:
\_io_decl: (data_in), parent:enqueue
|vpiName:data_in
|vpiDirection:2
|vpiIODecl:
\_io_decl: (push), parent:enqueue
|vpiName:push
|vpiDirection:2
|vpiInterface:
\_interface: work@l2_fifo_interface (returndata_fifos1), file:third_party/cores/taiga/l2_arbiter/l2_arbiter.sv, line:40, parent:l2_arb
|vpiModport:
\_modport: (structure), parent:returndata_fifos1
|vpiName:structure
|vpiIODecl:
\_io_decl: (push), parent:structure
|vpiName:push
|vpiDirection:1
|vpiIODecl:
\_io_decl: (pop), parent:structure
|vpiName:pop
|vpiDirection:1
|vpiIODecl:
\_io_decl: (data_in), parent:structure
|vpiName:data_in
|vpiDirection:1
|vpiIODecl:
\_io_decl: (data_out), parent:structure
|vpiName:data_out
|vpiDirection:2
|vpiIODecl:
\_io_decl: (valid), parent:structure
|vpiName:valid
|vpiDirection:2
|vpiIODecl:
\_io_decl: (full), parent:structure
|vpiName:full
|vpiDirection:2
|vpiIODecl:
\_io_decl: (empty), parent:structure
|vpiName:empty
|vpiDirection:2
|vpiInterface:
\_interface: work@l2_fifo_interface (returndata_fifos1), file:third_party/cores/taiga/l2_arbiter/l2_arbiter.sv, line:40, parent:l2_arb
|vpiNet:
\_logic_net: (push), line:26, parent:returndata_fifos1
|vpiName:push
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.returndata_fifos1.push
|vpiNetType:36
|vpiNet:
\_logic_net: (pop), line:27, parent:returndata_fifos1
|vpiName:pop
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.returndata_fifos1.pop
|vpiNetType:36
|vpiNet:
\_logic_net: (data_in), line:28, parent:returndata_fifos1
|vpiName:data_in
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.returndata_fifos1.data_in
|vpiNetType:36
|vpiRange:
\_range: , line:28
|vpiLeftRange:
\_constant: , line:28
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:28
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (data_out), line:29, parent:returndata_fifos1
|vpiName:data_out
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.returndata_fifos1.data_out
|vpiNetType:36
|vpiRange:
\_range: , line:29
|vpiLeftRange:
\_constant: , line:29
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:29
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (valid), line:30, parent:returndata_fifos1
|vpiName:valid
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.returndata_fifos1.valid
|vpiNetType:36
|vpiNet:
\_logic_net: (full), line:31, parent:returndata_fifos1
|vpiName:full
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.returndata_fifos1.full
|vpiNetType:36
|vpiNet:
\_logic_net: (empty), line:32, parent:returndata_fifos1
|vpiName:empty
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.returndata_fifos1.empty
|vpiNetType:36
|vpiInstance:
\_module: work@l2_arbiter (l2_arb), file:third_party/cores/taiga/examples/zedboard/taiga_wrapper.sv, line:239
|vpiInterface:
\_interface: work@l2_fifo_interface (mem_addr_fifo), file:third_party/cores/taiga/l2_arbiter/l2_arbiter.sv, line:43, parent:l2_arb
|vpiDefName:work@l2_fifo_interface
|vpiName:mem_addr_fifo
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.mem_addr_fifo
|vpiModport:
\_modport: (dequeue), parent:mem_addr_fifo
|vpiName:dequeue
|vpiIODecl:
\_io_decl: (valid), parent:dequeue
|vpiName:valid
|vpiDirection:1
|vpiIODecl:
\_io_decl: (data_out), parent:dequeue
|vpiName:data_out
|vpiDirection:1
|vpiIODecl:
\_io_decl: (pop), parent:dequeue
|vpiName:pop
|vpiDirection:2
|vpiInterface:
\_interface: work@l2_fifo_interface (mem_addr_fifo), file:third_party/cores/taiga/l2_arbiter/l2_arbiter.sv, line:43, parent:l2_arb
|vpiModport:
\_modport: (enqueue), parent:mem_addr_fifo
|vpiName:enqueue
|vpiIODecl:
\_io_decl: (full), parent:enqueue
|vpiName:full
|vpiDirection:1
|vpiIODecl:
\_io_decl: (empty), parent:enqueue
|vpiName:empty
|vpiDirection:1
|vpiIODecl:
\_io_decl: (data_in), parent:enqueue
|vpiName:data_in
|vpiDirection:2
|vpiIODecl:
\_io_decl: (push), parent:enqueue
|vpiName:push
|vpiDirection:2
|vpiInterface:
\_interface: work@l2_fifo_interface (mem_addr_fifo), file:third_party/cores/taiga/l2_arbiter/l2_arbiter.sv, line:43, parent:l2_arb
|vpiModport:
\_modport: (structure), parent:mem_addr_fifo
|vpiName:structure
|vpiIODecl:
\_io_decl: (push), parent:structure
|vpiName:push
|vpiDirection:1
|vpiIODecl:
\_io_decl: (pop), parent:structure
|vpiName:pop
|vpiDirection:1
|vpiIODecl:
\_io_decl: (data_in), parent:structure
|vpiName:data_in
|vpiDirection:1
|vpiIODecl:
\_io_decl: (data_out), parent:structure
|vpiName:data_out
|vpiDirection:2
|vpiIODecl:
\_io_decl: (valid), parent:structure
|vpiName:valid
|vpiDirection:2
|vpiIODecl:
\_io_decl: (full), parent:structure
|vpiName:full
|vpiDirection:2
|vpiIODecl:
\_io_decl: (empty), parent:structure
|vpiName:empty
|vpiDirection:2
|vpiInterface:
\_interface: work@l2_fifo_interface (mem_addr_fifo), file:third_party/cores/taiga/l2_arbiter/l2_arbiter.sv, line:43, parent:l2_arb
|vpiNet:
\_logic_net: (push), line:26, parent:mem_addr_fifo
|vpiName:push
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.mem_addr_fifo.push
|vpiNetType:36
|vpiNet:
\_logic_net: (pop), line:27, parent:mem_addr_fifo
|vpiName:pop
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.mem_addr_fifo.pop
|vpiNetType:36
|vpiNet:
\_logic_net: (data_in), line:28, parent:mem_addr_fifo
|vpiName:data_in
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.mem_addr_fifo.data_in
|vpiNetType:36
|vpiRange:
\_range: , line:28
|vpiLeftRange:
\_constant: , line:28
|vpiDecompile:-1
|INT:-1
|vpiRightRange:
\_constant: , line:28
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (data_out), line:29, parent:mem_addr_fifo
|vpiName:data_out
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.mem_addr_fifo.data_out
|vpiNetType:36
|vpiRange:
\_range: , line:29
|vpiLeftRange:
\_constant: , line:29
|vpiDecompile:-1
|INT:-1
|vpiRightRange:
\_constant: , line:29
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (valid), line:30, parent:mem_addr_fifo
|vpiName:valid
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.mem_addr_fifo.valid
|vpiNetType:36
|vpiNet:
\_logic_net: (full), line:31, parent:mem_addr_fifo
|vpiName:full
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.mem_addr_fifo.full
|vpiNetType:36
|vpiNet:
\_logic_net: (empty), line:32, parent:mem_addr_fifo
|vpiName:empty
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.mem_addr_fifo.empty
|vpiNetType:36
|vpiInstance:
\_module: work@l2_arbiter (l2_arb), file:third_party/cores/taiga/examples/zedboard/taiga_wrapper.sv, line:239
|vpiInterface:
\_interface: work@l2_fifo_interface (mem_data_fifo), file:third_party/cores/taiga/l2_arbiter/l2_arbiter.sv, line:44, parent:l2_arb
|vpiDefName:work@l2_fifo_interface
|vpiName:mem_data_fifo
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.mem_data_fifo
|vpiModport:
\_modport: (dequeue), parent:mem_data_fifo
|vpiName:dequeue
|vpiIODecl:
\_io_decl: (valid), parent:dequeue
|vpiName:valid
|vpiDirection:1
|vpiIODecl:
\_io_decl: (data_out), parent:dequeue
|vpiName:data_out
|vpiDirection:1
|vpiIODecl:
\_io_decl: (pop), parent:dequeue
|vpiName:pop
|vpiDirection:2
|vpiInterface:
\_interface: work@l2_fifo_interface (mem_data_fifo), file:third_party/cores/taiga/l2_arbiter/l2_arbiter.sv, line:44, parent:l2_arb
|vpiModport:
\_modport: (enqueue), parent:mem_data_fifo
|vpiName:enqueue
|vpiIODecl:
\_io_decl: (full), parent:enqueue
|vpiName:full
|vpiDirection:1
|vpiIODecl:
\_io_decl: (empty), parent:enqueue
|vpiName:empty
|vpiDirection:1
|vpiIODecl:
\_io_decl: (data_in), parent:enqueue
|vpiName:data_in
|vpiDirection:2
|vpiIODecl:
\_io_decl: (push), parent:enqueue
|vpiName:push
|vpiDirection:2
|vpiInterface:
\_interface: work@l2_fifo_interface (mem_data_fifo), file:third_party/cores/taiga/l2_arbiter/l2_arbiter.sv, line:44, parent:l2_arb
|vpiModport:
\_modport: (structure), parent:mem_data_fifo
|vpiName:structure
|vpiIODecl:
\_io_decl: (push), parent:structure
|vpiName:push
|vpiDirection:1
|vpiIODecl:
\_io_decl: (pop), parent:structure
|vpiName:pop
|vpiDirection:1
|vpiIODecl:
\_io_decl: (data_in), parent:structure
|vpiName:data_in
|vpiDirection:1
|vpiIODecl:
\_io_decl: (data_out), parent:structure
|vpiName:data_out
|vpiDirection:2
|vpiIODecl:
\_io_decl: (valid), parent:structure
|vpiName:valid
|vpiDirection:2
|vpiIODecl:
\_io_decl: (full), parent:structure
|vpiName:full
|vpiDirection:2
|vpiIODecl:
\_io_decl: (empty), parent:structure
|vpiName:empty
|vpiDirection:2
|vpiInterface:
\_interface: work@l2_fifo_interface (mem_data_fifo), file:third_party/cores/taiga/l2_arbiter/l2_arbiter.sv, line:44, parent:l2_arb
|vpiNet:
\_logic_net: (push), line:26, parent:mem_data_fifo
|vpiName:push
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.mem_data_fifo.push
|vpiNetType:36
|vpiNet:
\_logic_net: (pop), line:27, parent:mem_data_fifo
|vpiName:pop
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.mem_data_fifo.pop
|vpiNetType:36
|vpiNet:
\_logic_net: (data_in), line:28, parent:mem_data_fifo
|vpiName:data_in
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.mem_data_fifo.data_in
|vpiNetType:36
|vpiRange:
\_range: , line:28
|vpiLeftRange:
\_constant: , line:28
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:28
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (data_out), line:29, parent:mem_data_fifo
|vpiName:data_out
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.mem_data_fifo.data_out
|vpiNetType:36
|vpiRange:
\_range: , line:29
|vpiLeftRange:
\_constant: , line:29
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:29
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (valid), line:30, parent:mem_data_fifo
|vpiName:valid
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.mem_data_fifo.valid
|vpiNetType:36
|vpiNet:
\_logic_net: (full), line:31, parent:mem_data_fifo
|vpiName:full
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.mem_data_fifo.full
|vpiNetType:36
|vpiNet:
\_logic_net: (empty), line:32, parent:mem_data_fifo
|vpiName:empty
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.mem_data_fifo.empty
|vpiNetType:36
|vpiInstance:
\_module: work@l2_arbiter (l2_arb), file:third_party/cores/taiga/examples/zedboard/taiga_wrapper.sv, line:239
|vpiInterface:
\_interface: work@l2_fifo_interface (data_attributes), file:third_party/cores/taiga/l2_arbiter/l2_arbiter.sv, line:46, parent:l2_arb
|vpiDefName:work@l2_fifo_interface
|vpiName:data_attributes
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.data_attributes
|vpiModport:
\_modport: (dequeue), parent:data_attributes
|vpiName:dequeue
|vpiIODecl:
\_io_decl: (valid), parent:dequeue
|vpiName:valid
|vpiDirection:1
|vpiIODecl:
\_io_decl: (data_out), parent:dequeue
|vpiName:data_out
|vpiDirection:1
|vpiIODecl:
\_io_decl: (pop), parent:dequeue
|vpiName:pop
|vpiDirection:2
|vpiInterface:
\_interface: work@l2_fifo_interface (data_attributes), file:third_party/cores/taiga/l2_arbiter/l2_arbiter.sv, line:46, parent:l2_arb
|vpiModport:
\_modport: (enqueue), parent:data_attributes
|vpiName:enqueue
|vpiIODecl:
\_io_decl: (full), parent:enqueue
|vpiName:full
|vpiDirection:1
|vpiIODecl:
\_io_decl: (empty), parent:enqueue
|vpiName:empty
|vpiDirection:1
|vpiIODecl:
\_io_decl: (data_in), parent:enqueue
|vpiName:data_in
|vpiDirection:2
|vpiIODecl:
\_io_decl: (push), parent:enqueue
|vpiName:push
|vpiDirection:2
|vpiInterface:
\_interface: work@l2_fifo_interface (data_attributes), file:third_party/cores/taiga/l2_arbiter/l2_arbiter.sv, line:46, parent:l2_arb
|vpiModport:
\_modport: (structure), parent:data_attributes
|vpiName:structure
|vpiIODecl:
\_io_decl: (push), parent:structure
|vpiName:push
|vpiDirection:1
|vpiIODecl:
\_io_decl: (pop), parent:structure
|vpiName:pop
|vpiDirection:1
|vpiIODecl:
\_io_decl: (data_in), parent:structure
|vpiName:data_in
|vpiDirection:1
|vpiIODecl:
\_io_decl: (data_out), parent:structure
|vpiName:data_out
|vpiDirection:2
|vpiIODecl:
\_io_decl: (valid), parent:structure
|vpiName:valid
|vpiDirection:2
|vpiIODecl:
\_io_decl: (full), parent:structure
|vpiName:full
|vpiDirection:2
|vpiIODecl:
\_io_decl: (empty), parent:structure
|vpiName:empty
|vpiDirection:2
|vpiInterface:
\_interface: work@l2_fifo_interface (data_attributes), file:third_party/cores/taiga/l2_arbiter/l2_arbiter.sv, line:46, parent:l2_arb
|vpiNet:
\_logic_net: (push), line:26, parent:data_attributes
|vpiName:push
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.data_attributes.push
|vpiNetType:36
|vpiNet:
\_logic_net: (pop), line:27, parent:data_attributes
|vpiName:pop
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.data_attributes.pop
|vpiNetType:36
|vpiNet:
\_logic_net: (data_in), line:28, parent:data_attributes
|vpiName:data_in
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.data_attributes.data_in
|vpiNetType:36
|vpiRange:
\_range: , line:28
|vpiLeftRange:
\_constant: , line:28
|vpiDecompile:-1
|INT:-1
|vpiRightRange:
\_constant: , line:28
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (data_out), line:29, parent:data_attributes
|vpiName:data_out
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.data_attributes.data_out
|vpiNetType:36
|vpiRange:
\_range: , line:29
|vpiLeftRange:
\_constant: , line:29
|vpiDecompile:-1
|INT:-1
|vpiRightRange:
\_constant: , line:29
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (valid), line:30, parent:data_attributes
|vpiName:valid
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.data_attributes.valid
|vpiNetType:36
|vpiNet:
\_logic_net: (full), line:31, parent:data_attributes
|vpiName:full
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.data_attributes.full
|vpiNetType:36
|vpiNet:
\_logic_net: (empty), line:32, parent:data_attributes
|vpiName:empty
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.data_attributes.empty
|vpiNetType:36
|vpiInstance:
\_module: work@l2_arbiter (l2_arb), file:third_party/cores/taiga/examples/zedboard/taiga_wrapper.sv, line:239
|vpiInterface:
\_interface: work@l2_fifo_interface (mem_returndata_fifo), file:third_party/cores/taiga/l2_arbiter/l2_arbiter.sv, line:48, parent:l2_arb
|vpiDefName:work@l2_fifo_interface
|vpiName:mem_returndata_fifo
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.mem_returndata_fifo
|vpiModport:
\_modport: (dequeue), parent:mem_returndata_fifo
|vpiName:dequeue
|vpiIODecl:
\_io_decl: (valid), parent:dequeue
|vpiName:valid
|vpiDirection:1
|vpiIODecl:
\_io_decl: (data_out), parent:dequeue
|vpiName:data_out
|vpiDirection:1
|vpiIODecl:
\_io_decl: (pop), parent:dequeue
|vpiName:pop
|vpiDirection:2
|vpiInterface:
\_interface: work@l2_fifo_interface (mem_returndata_fifo), file:third_party/cores/taiga/l2_arbiter/l2_arbiter.sv, line:48, parent:l2_arb
|vpiModport:
\_modport: (enqueue), parent:mem_returndata_fifo
|vpiName:enqueue
|vpiIODecl:
\_io_decl: (full), parent:enqueue
|vpiName:full
|vpiDirection:1
|vpiIODecl:
\_io_decl: (empty), parent:enqueue
|vpiName:empty
|vpiDirection:1
|vpiIODecl:
\_io_decl: (data_in), parent:enqueue
|vpiName:data_in
|vpiDirection:2
|vpiIODecl:
\_io_decl: (push), parent:enqueue
|vpiName:push
|vpiDirection:2
|vpiInterface:
\_interface: work@l2_fifo_interface (mem_returndata_fifo), file:third_party/cores/taiga/l2_arbiter/l2_arbiter.sv, line:48, parent:l2_arb
|vpiModport:
\_modport: (structure), parent:mem_returndata_fifo
|vpiName:structure
|vpiIODecl:
\_io_decl: (push), parent:structure
|vpiName:push
|vpiDirection:1
|vpiIODecl:
\_io_decl: (pop), parent:structure
|vpiName:pop
|vpiDirection:1
|vpiIODecl:
\_io_decl: (data_in), parent:structure
|vpiName:data_in
|vpiDirection:1
|vpiIODecl:
\_io_decl: (data_out), parent:structure
|vpiName:data_out
|vpiDirection:2
|vpiIODecl:
\_io_decl: (valid), parent:structure
|vpiName:valid
|vpiDirection:2
|vpiIODecl:
\_io_decl: (full), parent:structure
|vpiName:full
|vpiDirection:2
|vpiIODecl:
\_io_decl: (empty), parent:structure
|vpiName:empty
|vpiDirection:2
|vpiInterface:
\_interface: work@l2_fifo_interface (mem_returndata_fifo), file:third_party/cores/taiga/l2_arbiter/l2_arbiter.sv, line:48, parent:l2_arb
|vpiNet:
\_logic_net: (push), line:26, parent:mem_returndata_fifo
|vpiName:push
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.mem_returndata_fifo.push
|vpiNetType:36
|vpiNet:
\_logic_net: (pop), line:27, parent:mem_returndata_fifo
|vpiName:pop
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.mem_returndata_fifo.pop
|vpiNetType:36
|vpiNet:
\_logic_net: (data_in), line:28, parent:mem_returndata_fifo
|vpiName:data_in
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.mem_returndata_fifo.data_in
|vpiNetType:36
|vpiRange:
\_range: , line:28
|vpiLeftRange:
\_constant: , line:28
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:28
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (data_out), line:29, parent:mem_returndata_fifo
|vpiName:data_out
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.mem_returndata_fifo.data_out
|vpiNetType:36
|vpiRange:
\_range: , line:29
|vpiLeftRange:
\_constant: , line:29
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:29
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (valid), line:30, parent:mem_returndata_fifo
|vpiName:valid
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.mem_returndata_fifo.valid
|vpiNetType:36
|vpiNet:
\_logic_net: (full), line:31, parent:mem_returndata_fifo
|vpiName:full
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.mem_returndata_fifo.full
|vpiNetType:36
|vpiNet:
\_logic_net: (empty), line:32, parent:mem_returndata_fifo
|vpiName:empty
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.mem_returndata_fifo.empty
|vpiNetType:36
|vpiInstance:
\_module: work@l2_arbiter (l2_arb), file:third_party/cores/taiga/examples/zedboard/taiga_wrapper.sv, line:239
|vpiModule:
\_module: work@l2_round_robin (rr), file:third_party/cores/taiga/l2_arbiter/l2_arbiter.sv, line:139, parent:l2_arb
|vpiDefName:work@l2_round_robin
|vpiName:rr
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.rr
|vpiPort:
\_port: (clk), line:27, parent:rr
|vpiName:clk
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (clk), line:139
|vpiName:clk
|vpiActual:
\_logic_net: (clk), line:27, parent:l2_arb
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (clk), line:27, parent:rr
|vpiName:clk
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.rr.clk
|vpiNetType:36
|vpiPort:
\_port: (rst), line:28, parent:rr
|vpiName:rst
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (rst), line:139
|vpiName:rst
|vpiActual:
\_logic_net: (rst), line:28, parent:l2_arb
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (rst), line:28, parent:rr
|vpiName:rst
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.rr.rst
|vpiNetType:36
|vpiPort:
\_port: (arb), line:29, parent:rr
|vpiName:arb
|vpiDirection:5
|vpiHighConn:
\_ref_obj: (arb), line:139
|vpiName:arb
|vpiActual:
\_interface: work@l2_arbitration_interface (arb), file:third_party/cores/taiga/l2_arbiter/l2_arbiter.sv, line:34
|vpiDefName:work@l2_arbitration_interface
|vpiName:arb
|vpiModport:
\_modport: (master)
|vpiName:master
|vpiIODecl:
\_io_decl: (requests)
|vpiName:requests
|vpiDirection:2
|vpiIODecl:
\_io_decl: (strobe)
|vpiName:strobe
|vpiDirection:2
|vpiIODecl:
\_io_decl: (grantee_i)
|vpiName:grantee_i
|vpiDirection:1
|vpiIODecl:
\_io_decl: (grantee_v)
|vpiName:grantee_v
|vpiDirection:1
|vpiIODecl:
\_io_decl: (grantee_valid)
|vpiName:grantee_valid
|vpiDirection:1
|vpiInterface:
\_interface: work@l2_arbitration_interface (arb), file:third_party/cores/taiga/l2_arbiter/l2_arbiter.sv, line:34
|vpiModport:
\_modport: (slave)
|vpiName:slave
|vpiIODecl:
\_io_decl: (requests)
|vpiName:requests
|vpiDirection:1
|vpiIODecl:
\_io_decl: (strobe)
|vpiName:strobe
|vpiDirection:1
|vpiIODecl:
\_io_decl: (grantee_i)
|vpiName:grantee_i
|vpiDirection:2
|vpiIODecl:
\_io_decl: (grantee_v)
|vpiName:grantee_v
|vpiDirection:2
|vpiIODecl:
\_io_decl: (grantee_valid)
|vpiName:grantee_valid
|vpiDirection:2
|vpiInterface:
\_interface: work@l2_arbitration_interface (arb), file:third_party/cores/taiga/l2_arbiter/l2_arbiter.sv, line:34
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_modport: (slave)
|vpiName:slave
|vpiIODecl:
\_io_decl: (requests)
|vpiName:requests
|vpiDirection:1
|vpiExpr:
\_logic_net: (requests), line:39
|vpiName:requests
|vpiNetType:36
|vpiRange:
\_range: , line:39
|vpiLeftRange:
\_constant: , line:39
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:39
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (strobe)
|vpiName:strobe
|vpiDirection:1
|vpiExpr:
\_logic_net: (strobe), line:43
|vpiName:strobe
|vpiNetType:36
|vpiIODecl:
\_io_decl: (grantee_i)
|vpiName:grantee_i
|vpiDirection:2
|vpiExpr:
\_logic_net: (grantee_i), line:40
|vpiName:grantee_i
|vpiNetType:36
|vpiRange:
\_range: , line:40
|vpiLeftRange:
\_constant: , line:40
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiRightRange:
\_constant: , line:40
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (grantee_v)
|vpiName:grantee_v
|vpiDirection:2
|vpiExpr:
\_logic_net: (grantee_v), line:41
|vpiName:grantee_v
|vpiNetType:36
|vpiRange:
\_range: , line:41
|vpiLeftRange:
\_constant: , line:41
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:41
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (grantee_valid)
|vpiName:grantee_valid
|vpiDirection:2
|vpiExpr:
\_logic_net: (grantee_valid), line:42
|vpiName:grantee_valid
|vpiNetType:36
|vpiInterface:
\_interface: work@l2_arbitration_interface (arb), file:third_party/cores/taiga/l2_arbiter/l2_arbiter.sv, line:139
|vpiDefName:work@l2_arbitration_interface
|vpiName:arb
|vpiModport:
\_modport: (master)
|vpiName:master
|vpiIODecl:
\_io_decl: (requests)
|vpiName:requests
|vpiDirection:2
|vpiExpr:
\_logic_net: (requests), line:39
|vpiIODecl:
\_io_decl: (strobe)
|vpiName:strobe
|vpiDirection:2
|vpiExpr:
\_logic_net: (strobe), line:43
|vpiIODecl:
\_io_decl: (grantee_i)
|vpiName:grantee_i
|vpiDirection:1
|vpiExpr:
\_logic_net: (grantee_i), line:40
|vpiIODecl:
\_io_decl: (grantee_v)
|vpiName:grantee_v
|vpiDirection:1
|vpiExpr:
\_logic_net: (grantee_v), line:41
|vpiIODecl:
\_io_decl: (grantee_valid)
|vpiName:grantee_valid
|vpiDirection:1
|vpiExpr:
\_logic_net: (grantee_valid), line:42
|vpiInterface:
\_interface: work@l2_arbitration_interface (arb), file:third_party/cores/taiga/l2_arbiter/l2_arbiter.sv, line:139
|vpiModport:
\_modport: (slave)
|vpiGenScopeArray:
\_gen_scope_array: (genblk1), line:42, parent:rr
|vpiName:genblk1
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.rr.genblk1
|vpiGenScope:
\_gen_scope: , parent:genblk1
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.rr.genblk1
|vpiProcess:
\_always: , line:45
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:45
|vpiCondition:
\_operation: , line:45
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:45
|vpiName:clk
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.rr.genblk1.clk
|vpiStmt:
\_begin: , line:45
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.rr.genblk1
|vpiStmt:
\_if_else: , line:46
|vpiCondition:
\_ref_obj: (rst), line:46
|vpiName:rst
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.rr.genblk1.rst
|vpiStmt:
\_assignment: , line:47
|vpiOpType:82
|vpiLhs:
\_ref_obj: (state), line:47
|vpiName:state
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.rr.genblk1.state
|vpiRhs:
\_constant: , line:47
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiElseStmt:
\_if_stmt: , line:48
|vpiCondition:
\_ref_obj: (arb.strobe), line:48
|vpiName:arb.strobe
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.rr.genblk1.arb.strobe
|vpiStmt:
\_assignment: , line:49
|vpiOpType:82
|vpiLhs:
\_ref_obj: (state), line:49
|vpiName:state
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.rr.genblk1.state
|vpiRhs:
\_ref_obj: (arb.grantee_i), line:49
|vpiName:arb.grantee_i
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.rr.genblk1.arb.grantee_i
|vpiProcess:
\_always: , line:53
|vpiAlwaysType:2
|vpiStmt:
\_begin: , line:53
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.rr.genblk1
|vpiStmt:
\_for_stmt: , line:54
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.rr.genblk1
|vpiCondition:
\_operation: , line:54
|vpiOpType:20
|vpiOperand:
\_ref_obj: (i), line:54
|vpiName:i
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.rr.genblk1.i
|vpiOperand:
\_ref_obj: (L2_NUM_PORTS), line:54
|vpiName:L2_NUM_PORTS
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.rr.genblk1.L2_NUM_PORTS
|vpiForInitStmt:
\_assign_stmt:
|vpiRhs:
\_constant: , line:54
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiLhs:
\_int_var: (i), line:54
|vpiName:i
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.rr.genblk1.i
|vpiForIncStmt:
\_operation: , line:54
|vpiOpType:62
|vpiOperand:
\_ref_obj: (i), line:54
|vpiName:i
|vpiStmt:
\_begin: , line:54
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.rr.genblk1
|vpiStmt:
\_assignment: , line:55
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_bit_select: (muxes), line:55
|vpiName:muxes
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.rr.genblk1.muxes
|vpiIndex:
\_ref_obj: (i), line:55
|vpiName:i
|vpiRhs:
\_ref_obj: (i), line:55
|vpiName:i
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.rr.genblk1.i
|vpiStmt:
\_for_stmt: , line:56
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.rr.genblk1
|vpiCondition:
\_operation: , line:56
|vpiOpType:20
|vpiOperand:
\_ref_obj: (j), line:56
|vpiName:j
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.rr.genblk1.j
|vpiOperand:
\_ref_obj: (L2_NUM_PORTS), line:56
|vpiName:L2_NUM_PORTS
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.rr.genblk1.L2_NUM_PORTS
|vpiForInitStmt:
\_assign_stmt:
|vpiRhs:
\_constant: , line:56
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiLhs:
\_int_var: (j), line:56
|vpiName:j
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.rr.genblk1.j
|vpiForIncStmt:
\_operation: , line:56
|vpiOpType:62
|vpiOperand:
\_ref_obj: (j), line:56
|vpiName:j
|vpiStmt:
\_begin: , line:56
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.rr.genblk1
|vpiStmt:
\_if_stmt: , line:57
|vpiCondition:
\_ref_obj: (arb.requests), line:57
|vpiName:arb.requests
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.rr.genblk1.arb.requests
|vpiStmt:
\_assignment: , line:58
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_bit_select: (muxes), line:58
|vpiName:muxes
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.rr.genblk1.muxes
|vpiIndex:
\_ref_obj: (i), line:58
|vpiName:i
|vpiRhs:
\_operation: , line:58
|vpiOpType:13
|vpiOperand:
\_operation: , line:58
|vpiOpType:24
|vpiOperand:
\_ref_obj: (i), line:58
|vpiName:i
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.rr.genblk1.i
|vpiOperand:
\_ref_obj: (j), line:58
|vpiName:j
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.rr.genblk1.j
|vpiOperand:
\_ref_obj: (L2_NUM_PORTS), line:58
|vpiName:L2_NUM_PORTS
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.rr.genblk1.L2_NUM_PORTS
|vpiProcess:
\_always: , line:67
|vpiAlwaysType:2
|vpiStmt:
\_begin: , line:67
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.rr.genblk1
|vpiStmt:
\_assignment: , line:68
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_ref_obj: (arb.grantee_v), line:68
|vpiName:arb.grantee_v
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.rr.genblk1.arb.grantee_v
|vpiRhs:
\_constant: , line:68
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiStmt:
\_assignment: , line:69
|vpiOpType:82
|vpiBlocking:1
|vpiLhs:
\_bit_select: (arb.grantee_v), line:69
|vpiName:arb.grantee_v
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.rr.genblk1.arb.grantee_v
|vpiIndex:
\_ref_obj: (arb.grantee_i), line:69
|vpiName:arb.grantee_i
|vpiRhs:
\_constant: , line:69
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiContAssign:
\_cont_assign: , line:64
|vpiRhs:
\_bit_select: (muxes), line:64
|vpiName:muxes
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.rr.genblk1.muxes
|vpiIndex:
\_ref_obj: (state), line:64
|vpiName:state
|vpiLhs:
\_ref_obj: (arb.grantee_i), line:64
|vpiName:arb.grantee_i
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.rr.genblk1.arb.grantee_i
|vpiContAssign:
\_cont_assign: , line:73
|vpiRhs:
\_operation: , line:73
|vpiOpType:7
|vpiOperand:
\_ref_obj: (arb.requests), line:73
|vpiName:arb.requests
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.rr.genblk1.arb.requests
|vpiLhs:
\_ref_obj: (arb.grantee_valid), line:73
|vpiName:arb.grantee_valid
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.rr.genblk1.arb.grantee_valid
|vpiParameter:
\_parameter: (L2_DATA_ATTRIBUTES_FIFO_DEPTH), line:41
|vpiName:L2_DATA_ATTRIBUTES_FIFO_DEPTH
|INT:16
|vpiParameter:
\_parameter: (L2_ID_W), line:46
|vpiName:L2_ID_W
|INT:3
|vpiParameter:
\_parameter: (L2_INPUT_FIFO_DEPTHS), line:34
|vpiName:L2_INPUT_FIFO_DEPTHS
|INT:4
|vpiParameter:
\_parameter: (L2_INVALIDATION_FIFO_DEPTHS), line:35
|vpiName:L2_INVALIDATION_FIFO_DEPTHS
|INT:4
|vpiParameter:
\_parameter: (L2_MEM_ADDR_FIFO_DEPTH), line:39
|vpiName:L2_MEM_ADDR_FIFO_DEPTH
|INT:8
|vpiParameter:
\_parameter: (L2_NUM_PORTS), line:26
|vpiName:L2_NUM_PORTS
|INT:2
|vpiParameter:
\_parameter: (L2_READ_RETURN_FIFO_DEPTHS), line:36
|vpiName:L2_READ_RETURN_FIFO_DEPTHS
|INT:1
|vpiParameter:
\_parameter: (L2_SUB_ID_W), line:27
|vpiName:L2_SUB_ID_W
|INT:2
|vpiNet:
\_logic_net: (clk), line:27, parent:rr
|vpiNet:
\_logic_net: (rst), line:28, parent:rr
|vpiNet:
\_logic_net: (state), line:32, parent:rr
|vpiName:state
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.rr.state
|vpiNetType:36
|vpiRange:
\_range: , line:32
|vpiLeftRange:
\_constant: , line:32
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiRightRange:
\_constant: , line:32
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (arb), line:29, parent:rr
|vpiName:arb
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.rr.arb
|vpiInstance:
\_module: work@l2_arbiter (l2_arb), file:third_party/cores/taiga/examples/zedboard/taiga_wrapper.sv, line:239
|vpiArrayNet:
\_array_net: (muxes), line:33, parent:rr
|vpiName:muxes
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.rr.muxes
|vpiSize:2
|vpiNet:
\_logic_net: , parent:muxes
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.rr.muxes
|vpiNetType:36
|vpiRange:
\_range: , line:33
|vpiLeftRange:
\_constant: , line:33
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiRightRange:
\_constant: , line:33
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiRange:
\_range: , line:33
|vpiLeftRange:
\_constant: , line:33
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:33
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiParameter:
\_parameter: (L2_DATA_ATTRIBUTES_FIFO_DEPTH), line:41
|vpiName:L2_DATA_ATTRIBUTES_FIFO_DEPTH
|INT:16
|vpiParameter:
\_parameter: (L2_ID_W), line:46
|vpiName:L2_ID_W
|INT:3
|vpiParameter:
\_parameter: (L2_INPUT_FIFO_DEPTHS), line:34
|vpiName:L2_INPUT_FIFO_DEPTHS
|INT:4
|vpiParameter:
\_parameter: (L2_INVALIDATION_FIFO_DEPTHS), line:35
|vpiName:L2_INVALIDATION_FIFO_DEPTHS
|INT:4
|vpiParameter:
\_parameter: (L2_MEM_ADDR_FIFO_DEPTH), line:39
|vpiName:L2_MEM_ADDR_FIFO_DEPTH
|INT:8
|vpiParameter:
\_parameter: (L2_NUM_PORTS), line:26
|vpiName:L2_NUM_PORTS
|INT:2
|vpiParameter:
\_parameter: (L2_READ_RETURN_FIFO_DEPTHS), line:36
|vpiName:L2_READ_RETURN_FIFO_DEPTHS
|INT:1
|vpiParameter:
\_parameter: (L2_SUB_ID_W), line:27
|vpiName:L2_SUB_ID_W
|INT:2
|vpiModule:
\_module: work@l2_fifo (input_fifo), file:third_party/cores/taiga/l2_arbiter/l2_arbiter.sv, line:166, parent:l2_arb
|vpiDefName:work@l2_fifo
|vpiName:input_fifo
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.input_fifo
|vpiPort:
\_port: (clk), line:25, parent:input_fifo
|vpiName:clk
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (clk), line:166
|vpiName:clk
|vpiActual:
\_logic_net: (clk), line:27, parent:l2_arb
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (clk), line:25, parent:input_fifo
|vpiName:clk
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.input_fifo.clk
|vpiNetType:36
|vpiPort:
\_port: (wr_clk), line:26, parent:input_fifo
|vpiName:wr_clk
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (wr_clk), line:166
|vpiName:wr_clk
|vpiActual:
\_logic_net: (wr_clk), line:77, parent:l2_arb
|vpiName:wr_clk
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.wr_clk
|vpiNetType:36
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (wr_clk), line:26, parent:input_fifo
|vpiName:wr_clk
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.input_fifo.wr_clk
|vpiNetType:36
|vpiPort:
\_port: (rd_clk), line:27, parent:input_fifo
|vpiName:rd_clk
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (rd_clk), line:166
|vpiName:rd_clk
|vpiActual:
\_logic_net: (rd_clk), line:77, parent:l2_arb
|vpiName:rd_clk
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.rd_clk
|vpiNetType:36
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (rd_clk), line:27, parent:input_fifo
|vpiName:rd_clk
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.input_fifo.rd_clk
|vpiNetType:36
|vpiPort:
\_port: (rst), line:29, parent:input_fifo
|vpiName:rst
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (rst), line:166
|vpiName:rst
|vpiActual:
\_logic_net: (rst), line:28, parent:l2_arb
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (rst), line:29, parent:input_fifo
|vpiName:rst
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.input_fifo.rst
|vpiNetType:36
|vpiPort:
\_port: (fifo), line:30, parent:input_fifo
|vpiName:fifo
|vpiDirection:5
|vpiHighConn:
\_ref_obj: (fifo), line:166
|vpiName:fifo
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_modport: (structure)
|vpiName:structure
|vpiIODecl:
\_io_decl: (push)
|vpiName:push
|vpiDirection:1
|vpiExpr:
\_logic_net: (push), line:26
|vpiName:push
|vpiNetType:36
|vpiIODecl:
\_io_decl: (pop)
|vpiName:pop
|vpiDirection:1
|vpiExpr:
\_logic_net: (pop), line:27
|vpiName:pop
|vpiNetType:36
|vpiIODecl:
\_io_decl: (data_in)
|vpiName:data_in
|vpiDirection:1
|vpiExpr:
\_logic_net: (data_in), line:28
|vpiName:data_in
|vpiNetType:36
|vpiRange:
\_range: , line:28
|vpiLeftRange:
\_constant: , line:28
|vpiDecompile:-1
|INT:-1
|vpiRightRange:
\_constant: , line:28
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (data_out)
|vpiName:data_out
|vpiDirection:2
|vpiExpr:
\_logic_net: (data_out), line:29
|vpiName:data_out
|vpiNetType:36
|vpiRange:
\_range: , line:29
|vpiLeftRange:
\_constant: , line:29
|vpiDecompile:-1
|INT:-1
|vpiRightRange:
\_constant: , line:29
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (valid)
|vpiName:valid
|vpiDirection:2
|vpiExpr:
\_logic_net: (valid), line:30
|vpiName:valid
|vpiNetType:36
|vpiIODecl:
\_io_decl: (full)
|vpiName:full
|vpiDirection:2
|vpiExpr:
\_logic_net: (full), line:31
|vpiName:full
|vpiNetType:36
|vpiIODecl:
\_io_decl: (empty)
|vpiName:empty
|vpiDirection:2
|vpiExpr:
\_logic_net: (empty), line:32
|vpiName:empty
|vpiNetType:36
|vpiInterface:
\_interface: work@l2_fifo_interface (fifo), file:third_party/cores/taiga/l2_arbiter/l2_arbiter.sv, line:166
|vpiDefName:work@l2_fifo_interface
|vpiName:fifo
|vpiModport:
\_modport: (dequeue)
|vpiName:dequeue
|vpiIODecl:
\_io_decl: (valid)
|vpiName:valid
|vpiDirection:1
|vpiExpr:
\_logic_net: (valid), line:30
|vpiIODecl:
\_io_decl: (data_out)
|vpiName:data_out
|vpiDirection:1
|vpiExpr:
\_logic_net: (data_out), line:29
|vpiIODecl:
\_io_decl: (pop)
|vpiName:pop
|vpiDirection:2
|vpiExpr:
\_logic_net: (pop), line:27
|vpiInterface:
\_interface: work@l2_fifo_interface (fifo), file:third_party/cores/taiga/l2_arbiter/l2_arbiter.sv, line:166
|vpiModport:
\_modport: (enqueue)
|vpiName:enqueue
|vpiIODecl:
\_io_decl: (full)
|vpiName:full
|vpiDirection:1
|vpiExpr:
\_logic_net: (full), line:31
|vpiIODecl:
\_io_decl: (empty)
|vpiName:empty
|vpiDirection:1
|vpiExpr:
\_logic_net: (empty), line:32
|vpiIODecl:
\_io_decl: (data_in)
|vpiName:data_in
|vpiDirection:2
|vpiExpr:
\_logic_net: (data_in), line:28
|vpiIODecl:
\_io_decl: (push)
|vpiName:push
|vpiDirection:2
|vpiExpr:
\_logic_net: (push), line:26
|vpiInterface:
\_interface: work@l2_fifo_interface (fifo), file:third_party/cores/taiga/l2_arbiter/l2_arbiter.sv, line:166
|vpiModport:
\_modport: (structure)
|vpiGenScopeArray:
\_gen_scope_array: (genblk1), line:37, parent:input_fifo
|vpiName:genblk1
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.input_fifo.genblk1
|vpiGenScope:
\_gen_scope: , parent:genblk1
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.input_fifo.genblk1
|vpiGenScopeArray:
\_gen_scope_array: (genblk1), line:54
|vpiName:genblk1
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.input_fifo.genblk1.genblk1
|vpiGenScope:
\_gen_scope: , parent:genblk1
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.input_fifo.genblk1.genblk1
|vpiNet:
\_logic_net: (write_index), line:58
|vpiName:write_index
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.input_fifo.genblk1.genblk1.write_index
|vpiNetType:36
|vpiRange:
\_range: , line:58
|vpiLeftRange:
\_constant: , line:58
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiRightRange:
\_constant: , line:58
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (read_index), line:59
|vpiName:read_index
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.input_fifo.genblk1.genblk1.read_index
|vpiNetType:36
|vpiRange:
\_range: , line:59
|vpiLeftRange:
\_constant: , line:59
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiRightRange:
\_constant: , line:59
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiProcess:
\_always: , line:67
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:67
|vpiCondition:
\_operation: , line:67
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:67
|vpiName:clk
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.input_fifo.genblk1.genblk1.clk
|vpiStmt:
\_begin: , line:67
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.input_fifo.genblk1.genblk1
|vpiStmt:
\_if_else: , line:68
|vpiCondition:
\_ref_obj: (rst), line:68
|vpiName:rst
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.input_fifo.genblk1.genblk1.rst
|vpiStmt:
\_begin: , line:68
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.input_fifo.genblk1.genblk1
|vpiStmt:
\_assignment: , line:69
|vpiOpType:82
|vpiLhs:
\_ref_obj: (read_index), line:69
|vpiName:read_index
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.input_fifo.genblk1.genblk1.read_index
|vpiRhs:
\_constant: , line:69
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiStmt:
\_assignment: , line:70
|vpiOpType:82
|vpiLhs:
\_ref_obj: (write_index), line:70
|vpiName:write_index
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.input_fifo.genblk1.genblk1.write_index
|vpiRhs:
\_constant: , line:70
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiElseStmt:
\_begin: , line:72
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.input_fifo.genblk1.genblk1
|vpiStmt:
\_assignment: , line:73
|vpiOpType:82
|vpiLhs:
\_ref_obj: (read_index), line:73
|vpiName:read_index
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.input_fifo.genblk1.genblk1.read_index
|vpiRhs:
\_operation: , line:73
|vpiOpType:24
|vpiOperand:
\_ref_obj: (read_index), line:73
|vpiName:read_index
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.input_fifo.genblk1.genblk1.read_index
|vpiOperand:
\_ref_obj: (fifo.pop), line:73
|vpiName:fifo.pop
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.input_fifo.genblk1.genblk1.fifo.pop
|vpiStmt:
\_assignment: , line:74
|vpiOpType:82
|vpiLhs:
\_ref_obj: (write_index), line:74
|vpiName:write_index
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.input_fifo.genblk1.genblk1.write_index
|vpiRhs:
\_operation: , line:74
|vpiOpType:24
|vpiOperand:
\_ref_obj: (write_index), line:74
|vpiName:write_index
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.input_fifo.genblk1.genblk1.write_index
|vpiOperand:
\_ref_obj: (fifo.push), line:74
|vpiName:fifo.push
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.input_fifo.genblk1.genblk1.fifo.push
|vpiProcess:
\_always: , line:81
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:81
|vpiCondition:
\_operation: , line:81
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:81
|vpiName:clk
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.input_fifo.genblk1.genblk1.clk
|vpiStmt:
\_begin: , line:81
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.input_fifo.genblk1.genblk1
|vpiStmt:
\_if_stmt: , line:82
|vpiCondition:
\_ref_obj: (fifo.push), line:82
|vpiName:fifo.push
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.input_fifo.genblk1.genblk1.fifo.push
|vpiStmt:
\_assignment: , line:83
|vpiOpType:82
|vpiLhs:
\_bit_select: (lut_ram), line:83
|vpiName:lut_ram
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.input_fifo.genblk1.genblk1.lut_ram
|vpiIndex:
\_ref_obj: (write_index), line:83
|vpiName:write_index
|vpiRhs:
\_ref_obj: (fifo.data_in), line:83
|vpiName:fifo.data_in
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.input_fifo.genblk1.genblk1.fifo.data_in
|vpiProcess:
\_always: , line:86
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:86
|vpiCondition:
\_operation: , line:86
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:86
|vpiName:clk
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.input_fifo.genblk1.genblk1.clk
|vpiStmt:
\_begin: , line:86
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.input_fifo.genblk1.genblk1
|vpiStmt:
\_if_else: , line:87
|vpiCondition:
\_ref_obj: (rst), line:87
|vpiName:rst
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.input_fifo.genblk1.genblk1.rst
|vpiStmt:
\_begin: , line:87
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.input_fifo.genblk1.genblk1
|vpiStmt:
\_assignment: , line:88
|vpiOpType:82
|vpiLhs:
\_bit_select: (count_v), line:88
|vpiName:count_v
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.input_fifo.genblk1.genblk1.count_v
|vpiIndex:
\_constant: , line:88
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiRhs:
\_constant: , line:88
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiStmt:
\_for_stmt: , line:89
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.input_fifo.genblk1.genblk1
|vpiCondition:
\_operation: , line:89
|vpiOpType:21
|vpiOperand:
\_ref_obj: (i), line:89
|vpiName:i
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.input_fifo.genblk1.genblk1.i
|vpiOperand:
\_ref_obj: (FIFO_DEPTH), line:89
|vpiName:FIFO_DEPTH
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.input_fifo.genblk1.genblk1.FIFO_DEPTH
|vpiForInitStmt:
\_assign_stmt:
|vpiRhs:
\_constant: , line:89
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiLhs:
\_int_var: (i), line:89
|vpiName:i
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.input_fifo.genblk1.genblk1.i
|vpiForIncStmt:
\_operation: , line:89
|vpiOpType:62
|vpiOperand:
\_ref_obj: (i), line:89
|vpiName:i
|vpiStmt:
\_assignment: , line:89
|vpiOpType:82
|vpiLhs:
\_bit_select: (count_v), line:89
|vpiName:count_v
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.input_fifo.genblk1.genblk1.count_v
|vpiIndex:
\_ref_obj: (i), line:89
|vpiName:i
|vpiRhs:
\_constant: , line:89
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiElseStmt:
\_if_else: , line:91
|vpiCondition:
\_operation: , line:91
|vpiOpType:28
|vpiOperand:
\_ref_obj: (fifo.push), line:91
|vpiName:fifo.push
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.input_fifo.genblk1.genblk1.fifo.push
|vpiOperand:
\_operation: , line:91
|vpiOpType:4
|vpiOperand:
\_ref_obj: (fifo.pop), line:91
|vpiName:fifo.pop
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.input_fifo.genblk1.genblk1.fifo.pop
|vpiStmt:
\_assignment: , line:92
|vpiOpType:82
|vpiLhs:
\_ref_obj: (count_v), line:92
|vpiName:count_v
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.input_fifo.genblk1.genblk1.count_v
|vpiRhs:
\_operation: , line:92
|vpiOpType:33
|vpiOperand:
\_part_select: , line:92, parent:count_v
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (count_v)
|vpiLeftRange:
\_operation: , line:92
|vpiOpType:11
|vpiOperand:
\_ref_obj: (FIFO_DEPTH), line:92
|vpiName:FIFO_DEPTH
|vpiOperand:
\_constant: , line:92
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:92
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiOperand:
\_constant: , line:92
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiElseStmt:
\_if_stmt: , line:93
|vpiCondition:
\_operation: , line:93
|vpiOpType:28
|vpiOperand:
\_operation: , line:93
|vpiOpType:4
|vpiOperand:
\_ref_obj: (fifo.push), line:93
|vpiName:fifo.push
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.input_fifo.genblk1.genblk1.fifo.push
|vpiOperand:
\_ref_obj: (fifo.pop), line:93
|vpiName:fifo.pop
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.input_fifo.genblk1.genblk1.fifo.pop
|vpiStmt:
\_assignment: , line:94
|vpiOpType:82
|vpiLhs:
\_ref_obj: (count_v), line:94
|vpiName:count_v
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.input_fifo.genblk1.genblk1.count_v
|vpiRhs:
\_operation: , line:94
|vpiOpType:33
|vpiOperand:
\_constant: , line:94
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiOperand:
\_part_select: , line:94, parent:count_v
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (count_v)
|vpiLeftRange:
\_ref_obj: (FIFO_DEPTH), line:94
|vpiName:FIFO_DEPTH
|vpiRightRange:
\_constant: , line:94
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiArrayNet:
\_array_net: (lut_ram), line:56
|vpiName:lut_ram
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.input_fifo.genblk1.genblk1.lut_ram
|vpiSize:8
|vpiNet:
\_logic_net: , parent:lut_ram
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.input_fifo.genblk1.genblk1.lut_ram
|vpiNetType:36
|vpiRange:
\_range: , line:56
|vpiLeftRange:
\_constant: , line:56
|vpiDecompile:-1
|INT:-1
|vpiRightRange:
\_constant: , line:56
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiRange:
\_range: , line:56
|vpiLeftRange:
\_constant: , line:56
|vpiConstType:7
|vpiDecompile:7
|vpiSize:32
|INT:7
|vpiRightRange:
\_constant: , line:56
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiArrayNet:
\_array_net: (count_v), line:61
|vpiName:count_v
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.input_fifo.genblk1.genblk1.count_v
|vpiSize:9
|vpiNet:
\_logic_net: , parent:count_v
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.input_fifo.genblk1.genblk1.count_v
|vpiNetType:36
|vpiRange:
\_range: , line:61
|vpiLeftRange:
\_constant: , line:61
|vpiConstType:7
|vpiDecompile:8
|vpiSize:32
|INT:8
|vpiRightRange:
\_constant: , line:61
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiContAssign:
\_cont_assign: , line:65
|vpiRhs:
\_bit_select: (lut_ram), line:65
|vpiName:lut_ram
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.input_fifo.genblk1.genblk1.lut_ram
|vpiIndex:
\_ref_obj: (read_index), line:65
|vpiName:read_index
|vpiLhs:
\_ref_obj: (fifo.data_out), line:65
|vpiName:fifo.data_out
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.input_fifo.genblk1.genblk1.fifo.data_out
|vpiContAssign:
\_cont_assign: , line:78
|vpiRhs:
\_bit_select: (count_v), line:78
|vpiName:count_v
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.input_fifo.genblk1.genblk1.count_v
|vpiIndex:
\_ref_obj: (FIFO_DEPTH), line:78
|vpiName:FIFO_DEPTH
|vpiLhs:
\_ref_obj: (fifo.full), line:78
|vpiName:fifo.full
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.input_fifo.genblk1.genblk1.fifo.full
|vpiContAssign:
\_cont_assign: , line:79
|vpiRhs:
\_operation: , line:79
|vpiOpType:4
|vpiOperand:
\_bit_select: (count_v), line:79
|vpiName:count_v
|vpiIndex:
\_constant: , line:79
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiLhs:
\_ref_obj: (fifo.valid), line:79
|vpiName:fifo.valid
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.input_fifo.genblk1.genblk1.fifo.valid
|vpiNet:
\_logic_net: (clk), line:25, parent:input_fifo
|vpiNet:
\_logic_net: (wr_clk), line:26, parent:input_fifo
|vpiNet:
\_logic_net: (rd_clk), line:27, parent:input_fifo
|vpiNet:
\_logic_net: (rst), line:29, parent:input_fifo
|vpiNet:
\_logic_net: (fifo), line:30, parent:input_fifo
|vpiName:fifo
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.input_fifo.fifo
|vpiInstance:
\_module: work@l2_arbiter (l2_arb), file:third_party/cores/taiga/examples/zedboard/taiga_wrapper.sv, line:239
|vpiParameter:
\_parameter: (ASYNC), line:23
|vpiName:ASYNC
|INT:0
|vpiParameter:
\_parameter: (DATA_WIDTH), line:166
|vpiName:DATA_WIDTH
|INT:0
|vpiParameter:
\_parameter: (FIFO_DEPTH), line:166
|vpiName:FIFO_DEPTH
|INT:8
|vpiModule:
\_module: work@l2_reservation_logic (reserv), file:third_party/cores/taiga/l2_arbiter/l2_arbiter.sv, line:190, parent:l2_arb
|vpiDefName:work@l2_reservation_logic
|vpiName:reserv
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.reserv
|vpiPort:
\_port: (clk), line:27, parent:reserv
|vpiName:clk
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (clk), line:190
|vpiName:clk
|vpiActual:
\_logic_net: (clk), line:27, parent:l2_arb
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (clk), line:27, parent:reserv
|vpiName:clk
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.reserv.clk
|vpiNetType:36
|vpiPort:
\_port: (rst), line:28, parent:reserv
|vpiName:rst
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (rst), line:190
|vpiName:rst
|vpiActual:
\_logic_net: (rst), line:28, parent:l2_arb
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (rst), line:28, parent:reserv
|vpiName:rst
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.reserv.rst
|vpiNetType:36
|vpiPort:
\_port: (addr), line:30, parent:reserv
|vpiName:addr
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (addr), line:190
|vpiName:addr
|vpiActual:
\_logic_net: (addr), line:27
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (addr), line:30, parent:reserv
|vpiName:addr
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.reserv.addr
|vpiNetType:36
|vpiRange:
\_range: , line:30
|vpiLeftRange:
\_constant: , line:30
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:30
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiPort:
\_port: (id), line:31, parent:reserv
|vpiName:id
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (id), line:190
|vpiName:id
|vpiActual:
\_logic_net: (id), line:75
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (id), line:31, parent:reserv
|vpiName:id
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.reserv.id
|vpiNetType:36
|vpiRange:
\_range: , line:31
|vpiLeftRange:
\_constant: , line:31
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiRightRange:
\_constant: , line:31
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiPort:
\_port: (strobe), line:32, parent:reserv
|vpiName:strobe
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (strobe), line:190
|vpiName:strobe
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (strobe), line:32, parent:reserv
|vpiName:strobe
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.reserv.strobe
|vpiNetType:36
|vpiPort:
\_port: (lr), line:34, parent:reserv
|vpiName:lr
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (lr), line:190
|vpiName:lr
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (lr), line:34, parent:reserv
|vpiName:lr
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.reserv.lr
|vpiNetType:36
|vpiPort:
\_port: (sc), line:35, parent:reserv
|vpiName:sc
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (sc), line:190
|vpiName:sc
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (sc), line:35, parent:reserv
|vpiName:sc
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.reserv.sc
|vpiNetType:36
|vpiPort:
\_port: (store), line:36, parent:reserv
|vpiName:store
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (store), line:190
|vpiName:store
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (store), line:36, parent:reserv
|vpiName:store
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.reserv.store
|vpiNetType:36
|vpiPort:
\_port: (abort), line:38, parent:reserv
|vpiName:abort
|vpiDirection:2
|vpiHighConn:
\_ref_obj: (abort), line:190
|vpiName:abort
|vpiActual:
\_logic_net: (abort), line:80
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (abort), line:38, parent:reserv
|vpiName:abort
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.reserv.abort
|vpiNetType:36
|vpiNet:
\_logic_net: (clk), line:27, parent:reserv
|vpiNet:
\_logic_net: (rst), line:28, parent:reserv
|vpiNet:
\_logic_net: (addr), line:30, parent:reserv
|vpiNet:
\_logic_net: (id), line:31, parent:reserv
|vpiNet:
\_logic_net: (strobe), line:32, parent:reserv
|vpiNet:
\_logic_net: (lr), line:34, parent:reserv
|vpiNet:
\_logic_net: (sc), line:35, parent:reserv
|vpiNet:
\_logic_net: (store), line:36, parent:reserv
|vpiNet:
\_logic_net: (abort), line:38, parent:reserv
|vpiNet:
\_logic_net: (reservation), line:43, parent:reserv
|vpiName:reservation
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.reserv.reservation
|vpiNetType:36
|vpiRange:
\_range: , line:43
|vpiLeftRange:
\_constant: , line:43
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:43
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (address_match), line:45, parent:reserv
|vpiName:address_match
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.reserv.address_match
|vpiNetType:36
|vpiRange:
\_range: , line:45
|vpiLeftRange:
\_constant: , line:45
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:45
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (revoke_reservation), line:46, parent:reserv
|vpiName:revoke_reservation
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.reserv.revoke_reservation
|vpiNetType:36
|vpiRange:
\_range: , line:46
|vpiLeftRange:
\_constant: , line:46
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:46
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiInstance:
\_module: work@l2_arbiter (l2_arb), file:third_party/cores/taiga/examples/zedboard/taiga_wrapper.sv, line:239
|vpiArrayNet:
\_array_net: (reservation_address), line:42, parent:reserv
|vpiName:reservation_address
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.reserv.reservation_address
|vpiSize:2
|vpiNet:
\_logic_net: , parent:reservation_address
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.reserv.reservation_address
|vpiNetType:36
|vpiRange:
\_range: , line:42
|vpiLeftRange:
\_constant: , line:42
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:42
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiRange:
\_range: , line:42
|vpiLeftRange:
\_constant: , line:42
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:42
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiParameter:
\_parameter: (L2_DATA_ATTRIBUTES_FIFO_DEPTH), line:41
|vpiName:L2_DATA_ATTRIBUTES_FIFO_DEPTH
|INT:16
|vpiParameter:
\_parameter: (L2_ID_W), line:46
|vpiName:L2_ID_W
|INT:3
|vpiParameter:
\_parameter: (L2_INPUT_FIFO_DEPTHS), line:34
|vpiName:L2_INPUT_FIFO_DEPTHS
|INT:4
|vpiParameter:
\_parameter: (L2_INVALIDATION_FIFO_DEPTHS), line:35
|vpiName:L2_INVALIDATION_FIFO_DEPTHS
|INT:4
|vpiParameter:
\_parameter: (L2_MEM_ADDR_FIFO_DEPTH), line:39
|vpiName:L2_MEM_ADDR_FIFO_DEPTH
|INT:8
|vpiParameter:
\_parameter: (L2_NUM_PORTS), line:26
|vpiName:L2_NUM_PORTS
|INT:2
|vpiParameter:
\_parameter: (L2_READ_RETURN_FIFO_DEPTHS), line:36
|vpiName:L2_READ_RETURN_FIFO_DEPTHS
|INT:1
|vpiParameter:
\_parameter: (L2_SUB_ID_W), line:27
|vpiName:L2_SUB_ID_W
|INT:2
|vpiModule:
\_module: work@l2_fifo (data_attributes_fifo), file:third_party/cores/taiga/l2_arbiter/l2_arbiter.sv, line:242, parent:l2_arb
|vpiDefName:work@l2_fifo
|vpiName:data_attributes_fifo
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.data_attributes_fifo
|vpiPort:
\_port: (clk), line:25, parent:data_attributes_fifo
|vpiName:clk
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (clk), line:242
|vpiName:clk
|vpiActual:
\_logic_net: (clk), line:27, parent:l2_arb
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (clk), line:25, parent:data_attributes_fifo
|vpiName:clk
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.data_attributes_fifo.clk
|vpiNetType:36
|vpiPort:
\_port: (wr_clk), line:26, parent:data_attributes_fifo
|vpiName:wr_clk
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (wr_clk), line:242
|vpiName:wr_clk
|vpiActual:
\_logic_net: (wr_clk), line:77, parent:l2_arb
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (wr_clk), line:26, parent:data_attributes_fifo
|vpiName:wr_clk
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.data_attributes_fifo.wr_clk
|vpiNetType:36
|vpiPort:
\_port: (rd_clk), line:27, parent:data_attributes_fifo
|vpiName:rd_clk
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (rd_clk), line:242
|vpiName:rd_clk
|vpiActual:
\_logic_net: (rd_clk), line:77, parent:l2_arb
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (rd_clk), line:27, parent:data_attributes_fifo
|vpiName:rd_clk
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.data_attributes_fifo.rd_clk
|vpiNetType:36
|vpiPort:
\_port: (rst), line:29, parent:data_attributes_fifo
|vpiName:rst
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (rst), line:242
|vpiName:rst
|vpiActual:
\_logic_net: (rst), line:28, parent:l2_arb
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (rst), line:29, parent:data_attributes_fifo
|vpiName:rst
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.data_attributes_fifo.rst
|vpiNetType:36
|vpiPort:
\_port: (fifo), line:30, parent:data_attributes_fifo
|vpiName:fifo
|vpiDirection:5
|vpiHighConn:
\_ref_obj: (fifo), line:242
|vpiName:fifo
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_modport: (structure)
|vpiName:structure
|vpiIODecl:
\_io_decl: (push)
|vpiName:push
|vpiDirection:1
|vpiExpr:
\_logic_net: (push), line:26
|vpiName:push
|vpiNetType:36
|vpiIODecl:
\_io_decl: (pop)
|vpiName:pop
|vpiDirection:1
|vpiExpr:
\_logic_net: (pop), line:27
|vpiName:pop
|vpiNetType:36
|vpiIODecl:
\_io_decl: (data_in)
|vpiName:data_in
|vpiDirection:1
|vpiExpr:
\_logic_net: (data_in), line:28
|vpiName:data_in
|vpiNetType:36
|vpiRange:
\_range: , line:28
|vpiLeftRange:
\_constant: , line:28
|vpiDecompile:-1
|INT:-1
|vpiRightRange:
\_constant: , line:28
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (data_out)
|vpiName:data_out
|vpiDirection:2
|vpiExpr:
\_logic_net: (data_out), line:29
|vpiName:data_out
|vpiNetType:36
|vpiRange:
\_range: , line:29
|vpiLeftRange:
\_constant: , line:29
|vpiDecompile:-1
|INT:-1
|vpiRightRange:
\_constant: , line:29
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (valid)
|vpiName:valid
|vpiDirection:2
|vpiExpr:
\_logic_net: (valid), line:30
|vpiName:valid
|vpiNetType:36
|vpiIODecl:
\_io_decl: (full)
|vpiName:full
|vpiDirection:2
|vpiExpr:
\_logic_net: (full), line:31
|vpiName:full
|vpiNetType:36
|vpiIODecl:
\_io_decl: (empty)
|vpiName:empty
|vpiDirection:2
|vpiExpr:
\_logic_net: (empty), line:32
|vpiName:empty
|vpiNetType:36
|vpiInterface:
\_interface: work@l2_fifo_interface (fifo), file:third_party/cores/taiga/l2_arbiter/l2_arbiter.sv, line:242
|vpiDefName:work@l2_fifo_interface
|vpiName:fifo
|vpiModport:
\_modport: (dequeue)
|vpiName:dequeue
|vpiIODecl:
\_io_decl: (valid)
|vpiName:valid
|vpiDirection:1
|vpiExpr:
\_logic_net: (valid), line:30
|vpiIODecl:
\_io_decl: (data_out)
|vpiName:data_out
|vpiDirection:1
|vpiExpr:
\_logic_net: (data_out), line:29
|vpiIODecl:
\_io_decl: (pop)
|vpiName:pop
|vpiDirection:2
|vpiExpr:
\_logic_net: (pop), line:27
|vpiInterface:
\_interface: work@l2_fifo_interface (fifo), file:third_party/cores/taiga/l2_arbiter/l2_arbiter.sv, line:242
|vpiModport:
\_modport: (enqueue)
|vpiName:enqueue
|vpiIODecl:
\_io_decl: (full)
|vpiName:full
|vpiDirection:1
|vpiExpr:
\_logic_net: (full), line:31
|vpiIODecl:
\_io_decl: (empty)
|vpiName:empty
|vpiDirection:1
|vpiExpr:
\_logic_net: (empty), line:32
|vpiIODecl:
\_io_decl: (data_in)
|vpiName:data_in
|vpiDirection:2
|vpiExpr:
\_logic_net: (data_in), line:28
|vpiIODecl:
\_io_decl: (push)
|vpiName:push
|vpiDirection:2
|vpiExpr:
\_logic_net: (push), line:26
|vpiInterface:
\_interface: work@l2_fifo_interface (fifo), file:third_party/cores/taiga/l2_arbiter/l2_arbiter.sv, line:242
|vpiModport:
\_modport: (structure)
|vpiGenScopeArray:
\_gen_scope_array: (genblk1), line:37, parent:data_attributes_fifo
|vpiName:genblk1
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.data_attributes_fifo.genblk1
|vpiGenScope:
\_gen_scope: , parent:genblk1
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.data_attributes_fifo.genblk1
|vpiGenScopeArray:
\_gen_scope_array: (genblk1), line:54
|vpiName:genblk1
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.data_attributes_fifo.genblk1.genblk1
|vpiGenScope:
\_gen_scope: , parent:genblk1
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.data_attributes_fifo.genblk1.genblk1
|vpiNet:
\_logic_net: (write_index), line:58
|vpiName:write_index
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.data_attributes_fifo.genblk1.genblk1.write_index
|vpiNetType:36
|vpiRange:
\_range: , line:58
|vpiLeftRange:
\_constant: , line:58
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiRightRange:
\_constant: , line:58
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (read_index), line:59
|vpiName:read_index
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.data_attributes_fifo.genblk1.genblk1.read_index
|vpiNetType:36
|vpiRange:
\_range: , line:59
|vpiLeftRange:
\_constant: , line:59
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiRightRange:
\_constant: , line:59
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiProcess:
\_always: , line:67
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:67
|vpiCondition:
\_operation: , line:67
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:67
|vpiName:clk
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.data_attributes_fifo.genblk1.genblk1.clk
|vpiStmt:
\_begin: , line:67
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.data_attributes_fifo.genblk1.genblk1
|vpiStmt:
\_if_else: , line:68
|vpiCondition:
\_ref_obj: (rst), line:68
|vpiName:rst
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.data_attributes_fifo.genblk1.genblk1.rst
|vpiStmt:
\_begin: , line:68
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.data_attributes_fifo.genblk1.genblk1
|vpiStmt:
\_assignment: , line:69
|vpiOpType:82
|vpiLhs:
\_ref_obj: (read_index), line:69
|vpiName:read_index
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.data_attributes_fifo.genblk1.genblk1.read_index
|vpiRhs:
\_constant: , line:69
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiStmt:
\_assignment: , line:70
|vpiOpType:82
|vpiLhs:
\_ref_obj: (write_index), line:70
|vpiName:write_index
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.data_attributes_fifo.genblk1.genblk1.write_index
|vpiRhs:
\_constant: , line:70
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiElseStmt:
\_begin: , line:72
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.data_attributes_fifo.genblk1.genblk1
|vpiStmt:
\_assignment: , line:73
|vpiOpType:82
|vpiLhs:
\_ref_obj: (read_index), line:73
|vpiName:read_index
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.data_attributes_fifo.genblk1.genblk1.read_index
|vpiRhs:
\_operation: , line:73
|vpiOpType:24
|vpiOperand:
\_ref_obj: (read_index), line:73
|vpiName:read_index
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.data_attributes_fifo.genblk1.genblk1.read_index
|vpiOperand:
\_ref_obj: (fifo.pop), line:73
|vpiName:fifo.pop
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.data_attributes_fifo.genblk1.genblk1.fifo.pop
|vpiStmt:
\_assignment: , line:74
|vpiOpType:82
|vpiLhs:
\_ref_obj: (write_index), line:74
|vpiName:write_index
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.data_attributes_fifo.genblk1.genblk1.write_index
|vpiRhs:
\_operation: , line:74
|vpiOpType:24
|vpiOperand:
\_ref_obj: (write_index), line:74
|vpiName:write_index
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.data_attributes_fifo.genblk1.genblk1.write_index
|vpiOperand:
\_ref_obj: (fifo.push), line:74
|vpiName:fifo.push
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.data_attributes_fifo.genblk1.genblk1.fifo.push
|vpiProcess:
\_always: , line:81
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:81
|vpiCondition:
\_operation: , line:81
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:81
|vpiName:clk
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.data_attributes_fifo.genblk1.genblk1.clk
|vpiStmt:
\_begin: , line:81
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.data_attributes_fifo.genblk1.genblk1
|vpiStmt:
\_if_stmt: , line:82
|vpiCondition:
\_ref_obj: (fifo.push), line:82
|vpiName:fifo.push
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.data_attributes_fifo.genblk1.genblk1.fifo.push
|vpiStmt:
\_assignment: , line:83
|vpiOpType:82
|vpiLhs:
\_bit_select: (lut_ram), line:83
|vpiName:lut_ram
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.data_attributes_fifo.genblk1.genblk1.lut_ram
|vpiIndex:
\_ref_obj: (write_index), line:83
|vpiName:write_index
|vpiRhs:
\_ref_obj: (fifo.data_in), line:83
|vpiName:fifo.data_in
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.data_attributes_fifo.genblk1.genblk1.fifo.data_in
|vpiProcess:
\_always: , line:86
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:86
|vpiCondition:
\_operation: , line:86
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:86
|vpiName:clk
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.data_attributes_fifo.genblk1.genblk1.clk
|vpiStmt:
\_begin: , line:86
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.data_attributes_fifo.genblk1.genblk1
|vpiStmt:
\_if_else: , line:87
|vpiCondition:
\_ref_obj: (rst), line:87
|vpiName:rst
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.data_attributes_fifo.genblk1.genblk1.rst
|vpiStmt:
\_begin: , line:87
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.data_attributes_fifo.genblk1.genblk1
|vpiStmt:
\_assignment: , line:88
|vpiOpType:82
|vpiLhs:
\_bit_select: (count_v), line:88
|vpiName:count_v
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.data_attributes_fifo.genblk1.genblk1.count_v
|vpiIndex:
\_constant: , line:88
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiRhs:
\_constant: , line:88
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiStmt:
\_for_stmt: , line:89
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.data_attributes_fifo.genblk1.genblk1
|vpiCondition:
\_operation: , line:89
|vpiOpType:21
|vpiOperand:
\_ref_obj: (i), line:89
|vpiName:i
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.data_attributes_fifo.genblk1.genblk1.i
|vpiOperand:
\_ref_obj: (FIFO_DEPTH), line:89
|vpiName:FIFO_DEPTH
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.data_attributes_fifo.genblk1.genblk1.FIFO_DEPTH
|vpiForInitStmt:
\_assign_stmt:
|vpiRhs:
\_constant: , line:89
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiLhs:
\_int_var: (i), line:89
|vpiName:i
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.data_attributes_fifo.genblk1.genblk1.i
|vpiForIncStmt:
\_operation: , line:89
|vpiOpType:62
|vpiOperand:
\_ref_obj: (i), line:89
|vpiName:i
|vpiStmt:
\_assignment: , line:89
|vpiOpType:82
|vpiLhs:
\_bit_select: (count_v), line:89
|vpiName:count_v
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.data_attributes_fifo.genblk1.genblk1.count_v
|vpiIndex:
\_ref_obj: (i), line:89
|vpiName:i
|vpiRhs:
\_constant: , line:89
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiElseStmt:
\_if_else: , line:91
|vpiCondition:
\_operation: , line:91
|vpiOpType:28
|vpiOperand:
\_ref_obj: (fifo.push), line:91
|vpiName:fifo.push
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.data_attributes_fifo.genblk1.genblk1.fifo.push
|vpiOperand:
\_operation: , line:91
|vpiOpType:4
|vpiOperand:
\_ref_obj: (fifo.pop), line:91
|vpiName:fifo.pop
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.data_attributes_fifo.genblk1.genblk1.fifo.pop
|vpiStmt:
\_assignment: , line:92
|vpiOpType:82
|vpiLhs:
\_ref_obj: (count_v), line:92
|vpiName:count_v
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.data_attributes_fifo.genblk1.genblk1.count_v
|vpiRhs:
\_operation: , line:92
|vpiOpType:33
|vpiOperand:
\_part_select: , line:92, parent:count_v
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (count_v)
|vpiLeftRange:
\_operation: , line:92
|vpiOpType:11
|vpiOperand:
\_ref_obj: (FIFO_DEPTH), line:92
|vpiName:FIFO_DEPTH
|vpiOperand:
\_constant: , line:92
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:92
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiOperand:
\_constant: , line:92
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiElseStmt:
\_if_stmt: , line:93
|vpiCondition:
\_operation: , line:93
|vpiOpType:28
|vpiOperand:
\_operation: , line:93
|vpiOpType:4
|vpiOperand:
\_ref_obj: (fifo.push), line:93
|vpiName:fifo.push
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.data_attributes_fifo.genblk1.genblk1.fifo.push
|vpiOperand:
\_ref_obj: (fifo.pop), line:93
|vpiName:fifo.pop
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.data_attributes_fifo.genblk1.genblk1.fifo.pop
|vpiStmt:
\_assignment: , line:94
|vpiOpType:82
|vpiLhs:
\_ref_obj: (count_v), line:94
|vpiName:count_v
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.data_attributes_fifo.genblk1.genblk1.count_v
|vpiRhs:
\_operation: , line:94
|vpiOpType:33
|vpiOperand:
\_constant: , line:94
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiOperand:
\_part_select: , line:94, parent:count_v
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (count_v)
|vpiLeftRange:
\_ref_obj: (FIFO_DEPTH), line:94
|vpiName:FIFO_DEPTH
|vpiRightRange:
\_constant: , line:94
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiArrayNet:
\_array_net: (lut_ram), line:56
|vpiName:lut_ram
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.data_attributes_fifo.genblk1.genblk1.lut_ram
|vpiSize:16
|vpiNet:
\_logic_net: , parent:lut_ram
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.data_attributes_fifo.genblk1.genblk1.lut_ram
|vpiNetType:36
|vpiRange:
\_range: , line:56
|vpiLeftRange:
\_constant: , line:56
|vpiDecompile:-1
|INT:-1
|vpiRightRange:
\_constant: , line:56
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiRange:
\_range: , line:56
|vpiLeftRange:
\_constant: , line:56
|vpiConstType:7
|vpiDecompile:15
|vpiSize:32
|INT:15
|vpiRightRange:
\_constant: , line:56
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiArrayNet:
\_array_net: (count_v), line:61
|vpiName:count_v
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.data_attributes_fifo.genblk1.genblk1.count_v
|vpiSize:17
|vpiNet:
\_logic_net: , parent:count_v
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.data_attributes_fifo.genblk1.genblk1.count_v
|vpiNetType:36
|vpiRange:
\_range: , line:61
|vpiLeftRange:
\_constant: , line:61
|vpiConstType:7
|vpiDecompile:16
|vpiSize:32
|INT:16
|vpiRightRange:
\_constant: , line:61
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiContAssign:
\_cont_assign: , line:65
|vpiRhs:
\_bit_select: (lut_ram), line:65
|vpiName:lut_ram
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.data_attributes_fifo.genblk1.genblk1.lut_ram
|vpiIndex:
\_ref_obj: (read_index), line:65
|vpiName:read_index
|vpiLhs:
\_ref_obj: (fifo.data_out), line:65
|vpiName:fifo.data_out
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.data_attributes_fifo.genblk1.genblk1.fifo.data_out
|vpiContAssign:
\_cont_assign: , line:78
|vpiRhs:
\_bit_select: (count_v), line:78
|vpiName:count_v
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.data_attributes_fifo.genblk1.genblk1.count_v
|vpiIndex:
\_ref_obj: (FIFO_DEPTH), line:78
|vpiName:FIFO_DEPTH
|vpiLhs:
\_ref_obj: (fifo.full), line:78
|vpiName:fifo.full
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.data_attributes_fifo.genblk1.genblk1.fifo.full
|vpiContAssign:
\_cont_assign: , line:79
|vpiRhs:
\_operation: , line:79
|vpiOpType:4
|vpiOperand:
\_bit_select: (count_v), line:79
|vpiName:count_v
|vpiIndex:
\_constant: , line:79
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiLhs:
\_ref_obj: (fifo.valid), line:79
|vpiName:fifo.valid
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.data_attributes_fifo.genblk1.genblk1.fifo.valid
|vpiNet:
\_logic_net: (clk), line:25, parent:data_attributes_fifo
|vpiNet:
\_logic_net: (wr_clk), line:26, parent:data_attributes_fifo
|vpiNet:
\_logic_net: (rd_clk), line:27, parent:data_attributes_fifo
|vpiNet:
\_logic_net: (rst), line:29, parent:data_attributes_fifo
|vpiNet:
\_logic_net: (fifo), line:30, parent:data_attributes_fifo
|vpiName:fifo
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.data_attributes_fifo.fifo
|vpiInstance:
\_module: work@l2_arbiter (l2_arb), file:third_party/cores/taiga/examples/zedboard/taiga_wrapper.sv, line:239
|vpiParameter:
\_parameter: (ASYNC), line:23
|vpiName:ASYNC
|INT:0
|vpiParameter:
\_parameter: (DATA_WIDTH), line:242
|vpiName:DATA_WIDTH
|INT:0
|vpiParameter:
\_parameter: (FIFO_DEPTH), line:242
|vpiName:FIFO_DEPTH
|INT:16
|vpiModule:
\_module: work@l2_fifo (mem_data), file:third_party/cores/taiga/l2_arbiter/l2_arbiter.sv, line:258, parent:l2_arb
|vpiDefName:work@l2_fifo
|vpiName:mem_data
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.mem_data
|vpiPort:
\_port: (clk), line:25, parent:mem_data
|vpiName:clk
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (clk), line:258
|vpiName:clk
|vpiActual:
\_logic_net: (clk), line:27, parent:l2_arb
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (clk), line:25, parent:mem_data
|vpiName:clk
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.mem_data.clk
|vpiNetType:36
|vpiPort:
\_port: (wr_clk), line:26, parent:mem_data
|vpiName:wr_clk
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (wr_clk), line:258
|vpiName:wr_clk
|vpiActual:
\_logic_net: (wr_clk), line:77, parent:l2_arb
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (wr_clk), line:26, parent:mem_data
|vpiName:wr_clk
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.mem_data.wr_clk
|vpiNetType:36
|vpiPort:
\_port: (rd_clk), line:27, parent:mem_data
|vpiName:rd_clk
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (rd_clk), line:258
|vpiName:rd_clk
|vpiActual:
\_logic_net: (rd_clk), line:77, parent:l2_arb
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (rd_clk), line:27, parent:mem_data
|vpiName:rd_clk
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.mem_data.rd_clk
|vpiNetType:36
|vpiPort:
\_port: (rst), line:29, parent:mem_data
|vpiName:rst
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (rst), line:258
|vpiName:rst
|vpiActual:
\_logic_net: (rst), line:28, parent:l2_arb
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (rst), line:29, parent:mem_data
|vpiName:rst
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.mem_data.rst
|vpiNetType:36
|vpiPort:
\_port: (fifo), line:30, parent:mem_data
|vpiName:fifo
|vpiDirection:5
|vpiHighConn:
\_ref_obj: (fifo), line:258
|vpiName:fifo
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_modport: (structure)
|vpiName:structure
|vpiIODecl:
\_io_decl: (push)
|vpiName:push
|vpiDirection:1
|vpiExpr:
\_logic_net: (push), line:26
|vpiName:push
|vpiNetType:36
|vpiIODecl:
\_io_decl: (pop)
|vpiName:pop
|vpiDirection:1
|vpiExpr:
\_logic_net: (pop), line:27
|vpiName:pop
|vpiNetType:36
|vpiIODecl:
\_io_decl: (data_in)
|vpiName:data_in
|vpiDirection:1
|vpiExpr:
\_logic_net: (data_in), line:28
|vpiName:data_in
|vpiNetType:36
|vpiRange:
\_range: , line:28
|vpiLeftRange:
\_constant: , line:28
|vpiDecompile:-1
|INT:-1
|vpiRightRange:
\_constant: , line:28
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (data_out)
|vpiName:data_out
|vpiDirection:2
|vpiExpr:
\_logic_net: (data_out), line:29
|vpiName:data_out
|vpiNetType:36
|vpiRange:
\_range: , line:29
|vpiLeftRange:
\_constant: , line:29
|vpiDecompile:-1
|INT:-1
|vpiRightRange:
\_constant: , line:29
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (valid)
|vpiName:valid
|vpiDirection:2
|vpiExpr:
\_logic_net: (valid), line:30
|vpiName:valid
|vpiNetType:36
|vpiIODecl:
\_io_decl: (full)
|vpiName:full
|vpiDirection:2
|vpiExpr:
\_logic_net: (full), line:31
|vpiName:full
|vpiNetType:36
|vpiIODecl:
\_io_decl: (empty)
|vpiName:empty
|vpiDirection:2
|vpiExpr:
\_logic_net: (empty), line:32
|vpiName:empty
|vpiNetType:36
|vpiInterface:
\_interface: work@l2_fifo_interface (fifo), file:third_party/cores/taiga/l2_arbiter/l2_arbiter.sv, line:258
|vpiDefName:work@l2_fifo_interface
|vpiName:fifo
|vpiModport:
\_modport: (dequeue)
|vpiName:dequeue
|vpiIODecl:
\_io_decl: (valid)
|vpiName:valid
|vpiDirection:1
|vpiExpr:
\_logic_net: (valid), line:30
|vpiIODecl:
\_io_decl: (data_out)
|vpiName:data_out
|vpiDirection:1
|vpiExpr:
\_logic_net: (data_out), line:29
|vpiIODecl:
\_io_decl: (pop)
|vpiName:pop
|vpiDirection:2
|vpiExpr:
\_logic_net: (pop), line:27
|vpiInterface:
\_interface: work@l2_fifo_interface (fifo), file:third_party/cores/taiga/l2_arbiter/l2_arbiter.sv, line:258
|vpiModport:
\_modport: (enqueue)
|vpiName:enqueue
|vpiIODecl:
\_io_decl: (full)
|vpiName:full
|vpiDirection:1
|vpiExpr:
\_logic_net: (full), line:31
|vpiIODecl:
\_io_decl: (empty)
|vpiName:empty
|vpiDirection:1
|vpiExpr:
\_logic_net: (empty), line:32
|vpiIODecl:
\_io_decl: (data_in)
|vpiName:data_in
|vpiDirection:2
|vpiExpr:
\_logic_net: (data_in), line:28
|vpiIODecl:
\_io_decl: (push)
|vpiName:push
|vpiDirection:2
|vpiExpr:
\_logic_net: (push), line:26
|vpiInterface:
\_interface: work@l2_fifo_interface (fifo), file:third_party/cores/taiga/l2_arbiter/l2_arbiter.sv, line:258
|vpiModport:
\_modport: (structure)
|vpiGenScopeArray:
\_gen_scope_array: (genblk1), line:37, parent:mem_data
|vpiName:genblk1
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.mem_data.genblk1
|vpiGenScope:
\_gen_scope: , parent:genblk1
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.mem_data.genblk1
|vpiGenScopeArray:
\_gen_scope_array: (genblk1), line:54
|vpiName:genblk1
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.mem_data.genblk1.genblk1
|vpiGenScope:
\_gen_scope: , parent:genblk1
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.mem_data.genblk1.genblk1
|vpiNet:
\_logic_net: (write_index), line:58
|vpiName:write_index
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.mem_data.genblk1.genblk1.write_index
|vpiNetType:36
|vpiRange:
\_range: , line:58
|vpiLeftRange:
\_constant: , line:58
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiRightRange:
\_constant: , line:58
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (read_index), line:59
|vpiName:read_index
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.mem_data.genblk1.genblk1.read_index
|vpiNetType:36
|vpiRange:
\_range: , line:59
|vpiLeftRange:
\_constant: , line:59
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiRightRange:
\_constant: , line:59
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiProcess:
\_always: , line:67
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:67
|vpiCondition:
\_operation: , line:67
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:67
|vpiName:clk
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.mem_data.genblk1.genblk1.clk
|vpiStmt:
\_begin: , line:67
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.mem_data.genblk1.genblk1
|vpiStmt:
\_if_else: , line:68
|vpiCondition:
\_ref_obj: (rst), line:68
|vpiName:rst
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.mem_data.genblk1.genblk1.rst
|vpiStmt:
\_begin: , line:68
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.mem_data.genblk1.genblk1
|vpiStmt:
\_assignment: , line:69
|vpiOpType:82
|vpiLhs:
\_ref_obj: (read_index), line:69
|vpiName:read_index
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.mem_data.genblk1.genblk1.read_index
|vpiRhs:
\_constant: , line:69
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiStmt:
\_assignment: , line:70
|vpiOpType:82
|vpiLhs:
\_ref_obj: (write_index), line:70
|vpiName:write_index
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.mem_data.genblk1.genblk1.write_index
|vpiRhs:
\_constant: , line:70
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiElseStmt:
\_begin: , line:72
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.mem_data.genblk1.genblk1
|vpiStmt:
\_assignment: , line:73
|vpiOpType:82
|vpiLhs:
\_ref_obj: (read_index), line:73
|vpiName:read_index
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.mem_data.genblk1.genblk1.read_index
|vpiRhs:
\_operation: , line:73
|vpiOpType:24
|vpiOperand:
\_ref_obj: (read_index), line:73
|vpiName:read_index
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.mem_data.genblk1.genblk1.read_index
|vpiOperand:
\_ref_obj: (fifo.pop), line:73
|vpiName:fifo.pop
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.mem_data.genblk1.genblk1.fifo.pop
|vpiStmt:
\_assignment: , line:74
|vpiOpType:82
|vpiLhs:
\_ref_obj: (write_index), line:74
|vpiName:write_index
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.mem_data.genblk1.genblk1.write_index
|vpiRhs:
\_operation: , line:74
|vpiOpType:24
|vpiOperand:
\_ref_obj: (write_index), line:74
|vpiName:write_index
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.mem_data.genblk1.genblk1.write_index
|vpiOperand:
\_ref_obj: (fifo.push), line:74
|vpiName:fifo.push
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.mem_data.genblk1.genblk1.fifo.push
|vpiProcess:
\_always: , line:81
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:81
|vpiCondition:
\_operation: , line:81
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:81
|vpiName:clk
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.mem_data.genblk1.genblk1.clk
|vpiStmt:
\_begin: , line:81
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.mem_data.genblk1.genblk1
|vpiStmt:
\_if_stmt: , line:82
|vpiCondition:
\_ref_obj: (fifo.push), line:82
|vpiName:fifo.push
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.mem_data.genblk1.genblk1.fifo.push
|vpiStmt:
\_assignment: , line:83
|vpiOpType:82
|vpiLhs:
\_bit_select: (lut_ram), line:83
|vpiName:lut_ram
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.mem_data.genblk1.genblk1.lut_ram
|vpiIndex:
\_ref_obj: (write_index), line:83
|vpiName:write_index
|vpiRhs:
\_ref_obj: (fifo.data_in), line:83
|vpiName:fifo.data_in
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.mem_data.genblk1.genblk1.fifo.data_in
|vpiProcess:
\_always: , line:86
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:86
|vpiCondition:
\_operation: , line:86
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:86
|vpiName:clk
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.mem_data.genblk1.genblk1.clk
|vpiStmt:
\_begin: , line:86
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.mem_data.genblk1.genblk1
|vpiStmt:
\_if_else: , line:87
|vpiCondition:
\_ref_obj: (rst), line:87
|vpiName:rst
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.mem_data.genblk1.genblk1.rst
|vpiStmt:
\_begin: , line:87
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.mem_data.genblk1.genblk1
|vpiStmt:
\_assignment: , line:88
|vpiOpType:82
|vpiLhs:
\_bit_select: (count_v), line:88
|vpiName:count_v
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.mem_data.genblk1.genblk1.count_v
|vpiIndex:
\_constant: , line:88
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiRhs:
\_constant: , line:88
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiStmt:
\_for_stmt: , line:89
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.mem_data.genblk1.genblk1
|vpiCondition:
\_operation: , line:89
|vpiOpType:21
|vpiOperand:
\_ref_obj: (i), line:89
|vpiName:i
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.mem_data.genblk1.genblk1.i
|vpiOperand:
\_ref_obj: (FIFO_DEPTH), line:89
|vpiName:FIFO_DEPTH
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.mem_data.genblk1.genblk1.FIFO_DEPTH
|vpiForInitStmt:
\_assign_stmt:
|vpiRhs:
\_constant: , line:89
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiLhs:
\_int_var: (i), line:89
|vpiName:i
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.mem_data.genblk1.genblk1.i
|vpiForIncStmt:
\_operation: , line:89
|vpiOpType:62
|vpiOperand:
\_ref_obj: (i), line:89
|vpiName:i
|vpiStmt:
\_assignment: , line:89
|vpiOpType:82
|vpiLhs:
\_bit_select: (count_v), line:89
|vpiName:count_v
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.mem_data.genblk1.genblk1.count_v
|vpiIndex:
\_ref_obj: (i), line:89
|vpiName:i
|vpiRhs:
\_constant: , line:89
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiElseStmt:
\_if_else: , line:91
|vpiCondition:
\_operation: , line:91
|vpiOpType:28
|vpiOperand:
\_ref_obj: (fifo.push), line:91
|vpiName:fifo.push
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.mem_data.genblk1.genblk1.fifo.push
|vpiOperand:
\_operation: , line:91
|vpiOpType:4
|vpiOperand:
\_ref_obj: (fifo.pop), line:91
|vpiName:fifo.pop
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.mem_data.genblk1.genblk1.fifo.pop
|vpiStmt:
\_assignment: , line:92
|vpiOpType:82
|vpiLhs:
\_ref_obj: (count_v), line:92
|vpiName:count_v
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.mem_data.genblk1.genblk1.count_v
|vpiRhs:
\_operation: , line:92
|vpiOpType:33
|vpiOperand:
\_part_select: , line:92, parent:count_v
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (count_v)
|vpiLeftRange:
\_operation: , line:92
|vpiOpType:11
|vpiOperand:
\_ref_obj: (FIFO_DEPTH), line:92
|vpiName:FIFO_DEPTH
|vpiOperand:
\_constant: , line:92
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:92
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiOperand:
\_constant: , line:92
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiElseStmt:
\_if_stmt: , line:93
|vpiCondition:
\_operation: , line:93
|vpiOpType:28
|vpiOperand:
\_operation: , line:93
|vpiOpType:4
|vpiOperand:
\_ref_obj: (fifo.push), line:93
|vpiName:fifo.push
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.mem_data.genblk1.genblk1.fifo.push
|vpiOperand:
\_ref_obj: (fifo.pop), line:93
|vpiName:fifo.pop
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.mem_data.genblk1.genblk1.fifo.pop
|vpiStmt:
\_assignment: , line:94
|vpiOpType:82
|vpiLhs:
\_ref_obj: (count_v), line:94
|vpiName:count_v
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.mem_data.genblk1.genblk1.count_v
|vpiRhs:
\_operation: , line:94
|vpiOpType:33
|vpiOperand:
\_constant: , line:94
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiOperand:
\_part_select: , line:94, parent:count_v
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (count_v)
|vpiLeftRange:
\_ref_obj: (FIFO_DEPTH), line:94
|vpiName:FIFO_DEPTH
|vpiRightRange:
\_constant: , line:94
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiArrayNet:
\_array_net: (lut_ram), line:56
|vpiName:lut_ram
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.mem_data.genblk1.genblk1.lut_ram
|vpiSize:8
|vpiNet:
\_logic_net: , parent:lut_ram
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.mem_data.genblk1.genblk1.lut_ram
|vpiNetType:36
|vpiRange:
\_range: , line:56
|vpiLeftRange:
\_constant: , line:56
|vpiDecompile:-1
|INT:-1
|vpiRightRange:
\_constant: , line:56
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiRange:
\_range: , line:56
|vpiLeftRange:
\_constant: , line:56
|vpiConstType:7
|vpiDecompile:7
|vpiSize:32
|INT:7
|vpiRightRange:
\_constant: , line:56
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiArrayNet:
\_array_net: (count_v), line:61
|vpiName:count_v
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.mem_data.genblk1.genblk1.count_v
|vpiSize:9
|vpiNet:
\_logic_net: , parent:count_v
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.mem_data.genblk1.genblk1.count_v
|vpiNetType:36
|vpiRange:
\_range: , line:61
|vpiLeftRange:
\_constant: , line:61
|vpiConstType:7
|vpiDecompile:8
|vpiSize:32
|INT:8
|vpiRightRange:
\_constant: , line:61
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiContAssign:
\_cont_assign: , line:65
|vpiRhs:
\_bit_select: (lut_ram), line:65
|vpiName:lut_ram
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.mem_data.genblk1.genblk1.lut_ram
|vpiIndex:
\_ref_obj: (read_index), line:65
|vpiName:read_index
|vpiLhs:
\_ref_obj: (fifo.data_out), line:65
|vpiName:fifo.data_out
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.mem_data.genblk1.genblk1.fifo.data_out
|vpiContAssign:
\_cont_assign: , line:78
|vpiRhs:
\_bit_select: (count_v), line:78
|vpiName:count_v
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.mem_data.genblk1.genblk1.count_v
|vpiIndex:
\_ref_obj: (FIFO_DEPTH), line:78
|vpiName:FIFO_DEPTH
|vpiLhs:
\_ref_obj: (fifo.full), line:78
|vpiName:fifo.full
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.mem_data.genblk1.genblk1.fifo.full
|vpiContAssign:
\_cont_assign: , line:79
|vpiRhs:
\_operation: , line:79
|vpiOpType:4
|vpiOperand:
\_bit_select: (count_v), line:79
|vpiName:count_v
|vpiIndex:
\_constant: , line:79
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiLhs:
\_ref_obj: (fifo.valid), line:79
|vpiName:fifo.valid
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.mem_data.genblk1.genblk1.fifo.valid
|vpiNet:
\_logic_net: (clk), line:25, parent:mem_data
|vpiNet:
\_logic_net: (wr_clk), line:26, parent:mem_data
|vpiNet:
\_logic_net: (rd_clk), line:27, parent:mem_data
|vpiNet:
\_logic_net: (rst), line:29, parent:mem_data
|vpiNet:
\_logic_net: (fifo), line:30, parent:mem_data
|vpiName:fifo
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.mem_data.fifo
|vpiInstance:
\_module: work@l2_arbiter (l2_arb), file:third_party/cores/taiga/examples/zedboard/taiga_wrapper.sv, line:239
|vpiParameter:
\_parameter: (ASYNC), line:23
|vpiName:ASYNC
|INT:0
|vpiParameter:
\_parameter: (DATA_WIDTH), line:258
|vpiName:DATA_WIDTH
|INT:0
|vpiParameter:
\_parameter: (FIFO_DEPTH), line:258
|vpiName:FIFO_DEPTH
|INT:8
|vpiModule:
\_module: work@l2_fifo (mem_returndata), file:third_party/cores/taiga/l2_arbiter/l2_arbiter.sv, line:271, parent:l2_arb
|vpiDefName:work@l2_fifo
|vpiName:mem_returndata
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.mem_returndata
|vpiPort:
\_port: (clk), line:25, parent:mem_returndata
|vpiName:clk
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (clk), line:271
|vpiName:clk
|vpiActual:
\_logic_net: (clk), line:27, parent:l2_arb
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (clk), line:25, parent:mem_returndata
|vpiName:clk
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.mem_returndata.clk
|vpiNetType:36
|vpiPort:
\_port: (wr_clk), line:26, parent:mem_returndata
|vpiName:wr_clk
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (wr_clk), line:271
|vpiName:wr_clk
|vpiActual:
\_logic_net: (wr_clk), line:77, parent:l2_arb
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (wr_clk), line:26, parent:mem_returndata
|vpiName:wr_clk
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.mem_returndata.wr_clk
|vpiNetType:36
|vpiPort:
\_port: (rd_clk), line:27, parent:mem_returndata
|vpiName:rd_clk
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (rd_clk), line:271
|vpiName:rd_clk
|vpiActual:
\_logic_net: (rd_clk), line:77, parent:l2_arb
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (rd_clk), line:27, parent:mem_returndata
|vpiName:rd_clk
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.mem_returndata.rd_clk
|vpiNetType:36
|vpiPort:
\_port: (rst), line:29, parent:mem_returndata
|vpiName:rst
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (rst), line:271
|vpiName:rst
|vpiActual:
\_logic_net: (rst), line:28, parent:l2_arb
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (rst), line:29, parent:mem_returndata
|vpiName:rst
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.mem_returndata.rst
|vpiNetType:36
|vpiPort:
\_port: (fifo), line:30, parent:mem_returndata
|vpiName:fifo
|vpiDirection:5
|vpiHighConn:
\_ref_obj: (fifo), line:271
|vpiName:fifo
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_modport: (structure)
|vpiName:structure
|vpiIODecl:
\_io_decl: (push)
|vpiName:push
|vpiDirection:1
|vpiExpr:
\_logic_net: (push), line:26
|vpiName:push
|vpiNetType:36
|vpiIODecl:
\_io_decl: (pop)
|vpiName:pop
|vpiDirection:1
|vpiExpr:
\_logic_net: (pop), line:27
|vpiName:pop
|vpiNetType:36
|vpiIODecl:
\_io_decl: (data_in)
|vpiName:data_in
|vpiDirection:1
|vpiExpr:
\_logic_net: (data_in), line:28
|vpiName:data_in
|vpiNetType:36
|vpiRange:
\_range: , line:28
|vpiLeftRange:
\_constant: , line:28
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:28
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (data_out)
|vpiName:data_out
|vpiDirection:2
|vpiExpr:
\_logic_net: (data_out), line:29
|vpiName:data_out
|vpiNetType:36
|vpiRange:
\_range: , line:29
|vpiLeftRange:
\_constant: , line:29
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:29
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (valid)
|vpiName:valid
|vpiDirection:2
|vpiExpr:
\_logic_net: (valid), line:30
|vpiName:valid
|vpiNetType:36
|vpiIODecl:
\_io_decl: (full)
|vpiName:full
|vpiDirection:2
|vpiExpr:
\_logic_net: (full), line:31
|vpiName:full
|vpiNetType:36
|vpiIODecl:
\_io_decl: (empty)
|vpiName:empty
|vpiDirection:2
|vpiExpr:
\_logic_net: (empty), line:32
|vpiName:empty
|vpiNetType:36
|vpiInterface:
\_interface: work@l2_fifo_interface (fifo), file:third_party/cores/taiga/l2_arbiter/l2_arbiter.sv, line:271
|vpiDefName:work@l2_fifo_interface
|vpiName:fifo
|vpiModport:
\_modport: (dequeue)
|vpiName:dequeue
|vpiIODecl:
\_io_decl: (valid)
|vpiName:valid
|vpiDirection:1
|vpiExpr:
\_logic_net: (valid), line:30
|vpiIODecl:
\_io_decl: (data_out)
|vpiName:data_out
|vpiDirection:1
|vpiExpr:
\_logic_net: (data_out), line:29
|vpiIODecl:
\_io_decl: (pop)
|vpiName:pop
|vpiDirection:2
|vpiExpr:
\_logic_net: (pop), line:27
|vpiInterface:
\_interface: work@l2_fifo_interface (fifo), file:third_party/cores/taiga/l2_arbiter/l2_arbiter.sv, line:271
|vpiModport:
\_modport: (enqueue)
|vpiName:enqueue
|vpiIODecl:
\_io_decl: (full)
|vpiName:full
|vpiDirection:1
|vpiExpr:
\_logic_net: (full), line:31
|vpiIODecl:
\_io_decl: (empty)
|vpiName:empty
|vpiDirection:1
|vpiExpr:
\_logic_net: (empty), line:32
|vpiIODecl:
\_io_decl: (data_in)
|vpiName:data_in
|vpiDirection:2
|vpiExpr:
\_logic_net: (data_in), line:28
|vpiIODecl:
\_io_decl: (push)
|vpiName:push
|vpiDirection:2
|vpiExpr:
\_logic_net: (push), line:26
|vpiInterface:
\_interface: work@l2_fifo_interface (fifo), file:third_party/cores/taiga/l2_arbiter/l2_arbiter.sv, line:271
|vpiModport:
\_modport: (structure)
|vpiGenScopeArray:
\_gen_scope_array: (genblk1), line:37, parent:mem_returndata
|vpiName:genblk1
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.mem_returndata.genblk1
|vpiGenScope:
\_gen_scope: , parent:genblk1
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.mem_returndata.genblk1
|vpiGenScopeArray:
\_gen_scope_array: (genblk1), line:54
|vpiName:genblk1
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.mem_returndata.genblk1.genblk1
|vpiGenScope:
\_gen_scope: , parent:genblk1
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.mem_returndata.genblk1.genblk1
|vpiNet:
\_logic_net: (write_index), line:58
|vpiName:write_index
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.mem_returndata.genblk1.genblk1.write_index
|vpiNetType:36
|vpiRange:
\_range: , line:58
|vpiLeftRange:
\_constant: , line:58
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiRightRange:
\_constant: , line:58
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (read_index), line:59
|vpiName:read_index
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.mem_returndata.genblk1.genblk1.read_index
|vpiNetType:36
|vpiRange:
\_range: , line:59
|vpiLeftRange:
\_constant: , line:59
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiRightRange:
\_constant: , line:59
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiProcess:
\_always: , line:67
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:67
|vpiCondition:
\_operation: , line:67
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:67
|vpiName:clk
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.mem_returndata.genblk1.genblk1.clk
|vpiStmt:
\_begin: , line:67
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.mem_returndata.genblk1.genblk1
|vpiStmt:
\_if_else: , line:68
|vpiCondition:
\_ref_obj: (rst), line:68
|vpiName:rst
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.mem_returndata.genblk1.genblk1.rst
|vpiStmt:
\_begin: , line:68
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.mem_returndata.genblk1.genblk1
|vpiStmt:
\_assignment: , line:69
|vpiOpType:82
|vpiLhs:
\_ref_obj: (read_index), line:69
|vpiName:read_index
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.mem_returndata.genblk1.genblk1.read_index
|vpiRhs:
\_constant: , line:69
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiStmt:
\_assignment: , line:70
|vpiOpType:82
|vpiLhs:
\_ref_obj: (write_index), line:70
|vpiName:write_index
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.mem_returndata.genblk1.genblk1.write_index
|vpiRhs:
\_constant: , line:70
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiElseStmt:
\_begin: , line:72
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.mem_returndata.genblk1.genblk1
|vpiStmt:
\_assignment: , line:73
|vpiOpType:82
|vpiLhs:
\_ref_obj: (read_index), line:73
|vpiName:read_index
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.mem_returndata.genblk1.genblk1.read_index
|vpiRhs:
\_operation: , line:73
|vpiOpType:24
|vpiOperand:
\_ref_obj: (read_index), line:73
|vpiName:read_index
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.mem_returndata.genblk1.genblk1.read_index
|vpiOperand:
\_ref_obj: (fifo.pop), line:73
|vpiName:fifo.pop
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.mem_returndata.genblk1.genblk1.fifo.pop
|vpiStmt:
\_assignment: , line:74
|vpiOpType:82
|vpiLhs:
\_ref_obj: (write_index), line:74
|vpiName:write_index
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.mem_returndata.genblk1.genblk1.write_index
|vpiRhs:
\_operation: , line:74
|vpiOpType:24
|vpiOperand:
\_ref_obj: (write_index), line:74
|vpiName:write_index
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.mem_returndata.genblk1.genblk1.write_index
|vpiOperand:
\_ref_obj: (fifo.push), line:74
|vpiName:fifo.push
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.mem_returndata.genblk1.genblk1.fifo.push
|vpiProcess:
\_always: , line:81
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:81
|vpiCondition:
\_operation: , line:81
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:81
|vpiName:clk
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.mem_returndata.genblk1.genblk1.clk
|vpiStmt:
\_begin: , line:81
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.mem_returndata.genblk1.genblk1
|vpiStmt:
\_if_stmt: , line:82
|vpiCondition:
\_ref_obj: (fifo.push), line:82
|vpiName:fifo.push
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.mem_returndata.genblk1.genblk1.fifo.push
|vpiStmt:
\_assignment: , line:83
|vpiOpType:82
|vpiLhs:
\_bit_select: (lut_ram), line:83
|vpiName:lut_ram
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.mem_returndata.genblk1.genblk1.lut_ram
|vpiIndex:
\_ref_obj: (write_index), line:83
|vpiName:write_index
|vpiRhs:
\_ref_obj: (fifo.data_in), line:83
|vpiName:fifo.data_in
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.mem_returndata.genblk1.genblk1.fifo.data_in
|vpiProcess:
\_always: , line:86
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:86
|vpiCondition:
\_operation: , line:86
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:86
|vpiName:clk
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.mem_returndata.genblk1.genblk1.clk
|vpiStmt:
\_begin: , line:86
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.mem_returndata.genblk1.genblk1
|vpiStmt:
\_if_else: , line:87
|vpiCondition:
\_ref_obj: (rst), line:87
|vpiName:rst
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.mem_returndata.genblk1.genblk1.rst
|vpiStmt:
\_begin: , line:87
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.mem_returndata.genblk1.genblk1
|vpiStmt:
\_assignment: , line:88
|vpiOpType:82
|vpiLhs:
\_bit_select: (count_v), line:88
|vpiName:count_v
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.mem_returndata.genblk1.genblk1.count_v
|vpiIndex:
\_constant: , line:88
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiRhs:
\_constant: , line:88
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiStmt:
\_for_stmt: , line:89
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.mem_returndata.genblk1.genblk1
|vpiCondition:
\_operation: , line:89
|vpiOpType:21
|vpiOperand:
\_ref_obj: (i), line:89
|vpiName:i
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.mem_returndata.genblk1.genblk1.i
|vpiOperand:
\_ref_obj: (FIFO_DEPTH), line:89
|vpiName:FIFO_DEPTH
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.mem_returndata.genblk1.genblk1.FIFO_DEPTH
|vpiForInitStmt:
\_assign_stmt:
|vpiRhs:
\_constant: , line:89
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiLhs:
\_int_var: (i), line:89
|vpiName:i
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.mem_returndata.genblk1.genblk1.i
|vpiForIncStmt:
\_operation: , line:89
|vpiOpType:62
|vpiOperand:
\_ref_obj: (i), line:89
|vpiName:i
|vpiStmt:
\_assignment: , line:89
|vpiOpType:82
|vpiLhs:
\_bit_select: (count_v), line:89
|vpiName:count_v
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.mem_returndata.genblk1.genblk1.count_v
|vpiIndex:
\_ref_obj: (i), line:89
|vpiName:i
|vpiRhs:
\_constant: , line:89
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiElseStmt:
\_if_else: , line:91
|vpiCondition:
\_operation: , line:91
|vpiOpType:28
|vpiOperand:
\_ref_obj: (fifo.push), line:91
|vpiName:fifo.push
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.mem_returndata.genblk1.genblk1.fifo.push
|vpiOperand:
\_operation: , line:91
|vpiOpType:4
|vpiOperand:
\_ref_obj: (fifo.pop), line:91
|vpiName:fifo.pop
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.mem_returndata.genblk1.genblk1.fifo.pop
|vpiStmt:
\_assignment: , line:92
|vpiOpType:82
|vpiLhs:
\_ref_obj: (count_v), line:92
|vpiName:count_v
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.mem_returndata.genblk1.genblk1.count_v
|vpiRhs:
\_operation: , line:92
|vpiOpType:33
|vpiOperand:
\_part_select: , line:92, parent:count_v
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (count_v)
|vpiLeftRange:
\_operation: , line:92
|vpiOpType:11
|vpiOperand:
\_ref_obj: (FIFO_DEPTH), line:92
|vpiName:FIFO_DEPTH
|vpiOperand:
\_constant: , line:92
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:92
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiOperand:
\_constant: , line:92
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiElseStmt:
\_if_stmt: , line:93
|vpiCondition:
\_operation: , line:93
|vpiOpType:28
|vpiOperand:
\_operation: , line:93
|vpiOpType:4
|vpiOperand:
\_ref_obj: (fifo.push), line:93
|vpiName:fifo.push
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.mem_returndata.genblk1.genblk1.fifo.push
|vpiOperand:
\_ref_obj: (fifo.pop), line:93
|vpiName:fifo.pop
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.mem_returndata.genblk1.genblk1.fifo.pop
|vpiStmt:
\_assignment: , line:94
|vpiOpType:82
|vpiLhs:
\_ref_obj: (count_v), line:94
|vpiName:count_v
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.mem_returndata.genblk1.genblk1.count_v
|vpiRhs:
\_operation: , line:94
|vpiOpType:33
|vpiOperand:
\_constant: , line:94
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiOperand:
\_part_select: , line:94, parent:count_v
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (count_v)
|vpiLeftRange:
\_ref_obj: (FIFO_DEPTH), line:94
|vpiName:FIFO_DEPTH
|vpiRightRange:
\_constant: , line:94
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiArrayNet:
\_array_net: (lut_ram), line:56
|vpiName:lut_ram
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.mem_returndata.genblk1.genblk1.lut_ram
|vpiSize:8
|vpiNet:
\_logic_net: , parent:lut_ram
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.mem_returndata.genblk1.genblk1.lut_ram
|vpiNetType:36
|vpiRange:
\_range: , line:56
|vpiLeftRange:
\_constant: , line:56
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:56
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiRange:
\_range: , line:56
|vpiLeftRange:
\_constant: , line:56
|vpiConstType:7
|vpiDecompile:7
|vpiSize:32
|INT:7
|vpiRightRange:
\_constant: , line:56
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiArrayNet:
\_array_net: (count_v), line:61
|vpiName:count_v
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.mem_returndata.genblk1.genblk1.count_v
|vpiSize:9
|vpiNet:
\_logic_net: , parent:count_v
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.mem_returndata.genblk1.genblk1.count_v
|vpiNetType:36
|vpiRange:
\_range: , line:61
|vpiLeftRange:
\_constant: , line:61
|vpiConstType:7
|vpiDecompile:8
|vpiSize:32
|INT:8
|vpiRightRange:
\_constant: , line:61
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiContAssign:
\_cont_assign: , line:65
|vpiRhs:
\_bit_select: (lut_ram), line:65
|vpiName:lut_ram
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.mem_returndata.genblk1.genblk1.lut_ram
|vpiIndex:
\_ref_obj: (read_index), line:65
|vpiName:read_index
|vpiLhs:
\_ref_obj: (fifo.data_out), line:65
|vpiName:fifo.data_out
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.mem_returndata.genblk1.genblk1.fifo.data_out
|vpiContAssign:
\_cont_assign: , line:78
|vpiRhs:
\_bit_select: (count_v), line:78
|vpiName:count_v
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.mem_returndata.genblk1.genblk1.count_v
|vpiIndex:
\_ref_obj: (FIFO_DEPTH), line:78
|vpiName:FIFO_DEPTH
|vpiLhs:
\_ref_obj: (fifo.full), line:78
|vpiName:fifo.full
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.mem_returndata.genblk1.genblk1.fifo.full
|vpiContAssign:
\_cont_assign: , line:79
|vpiRhs:
\_operation: , line:79
|vpiOpType:4
|vpiOperand:
\_bit_select: (count_v), line:79
|vpiName:count_v
|vpiIndex:
\_constant: , line:79
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiLhs:
\_ref_obj: (fifo.valid), line:79
|vpiName:fifo.valid
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.mem_returndata.genblk1.genblk1.fifo.valid
|vpiNet:
\_logic_net: (clk), line:25, parent:mem_returndata
|vpiNet:
\_logic_net: (wr_clk), line:26, parent:mem_returndata
|vpiNet:
\_logic_net: (rd_clk), line:27, parent:mem_returndata
|vpiNet:
\_logic_net: (rst), line:29, parent:mem_returndata
|vpiNet:
\_logic_net: (fifo), line:30, parent:mem_returndata
|vpiName:fifo
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.mem_returndata.fifo
|vpiInstance:
\_module: work@l2_arbiter (l2_arb), file:third_party/cores/taiga/examples/zedboard/taiga_wrapper.sv, line:239
|vpiParameter:
\_parameter: (ASYNC), line:23
|vpiName:ASYNC
|INT:0
|vpiParameter:
\_parameter: (DATA_WIDTH), line:271
|vpiName:DATA_WIDTH
|INT:32
|vpiParameter:
\_parameter: (FIFO_DEPTH), line:271
|vpiName:FIFO_DEPTH
|INT:8
|vpiGenScopeArray:
\_gen_scope_array: (genblk1[0]), line:88, parent:l2_arb
|vpiName:genblk1[0]
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk1[0]
|vpiGenScope:
\_gen_scope: , parent:genblk1[0]
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk1[0]
|vpiContAssign:
\_cont_assign: , line:90
|vpiRhs:
\_bit_select: (request.request_push), line:90
|vpiName:request.request_push
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk1[0].request.request_push
|vpiIndex:
\_ref_obj: (i), line:90
|vpiName:i
|vpiLhs:
\_ref_obj: (input_fifos[i].push), line:90
|vpiName:input_fifos[i].push
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk1[0].input_fifos[i].push
|vpiContAssign:
\_cont_assign: , line:93
|vpiRhs:
\_bit_select: (request.addr), line:93
|vpiName:request.addr
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk1[0].request.addr
|vpiIndex:
\_ref_obj: (i), line:93
|vpiName:i
|vpiLhs:
\_ref_obj: (requests_in[i].addr), line:93
|vpiName:requests_in[i].addr
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk1[0].requests_in[i].addr
|vpiContAssign:
\_cont_assign: , line:94
|vpiRhs:
\_bit_select: (request.be), line:94
|vpiName:request.be
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk1[0].request.be
|vpiIndex:
\_ref_obj: (i), line:94
|vpiName:i
|vpiLhs:
\_ref_obj: (requests_in[i].be), line:94
|vpiName:requests_in[i].be
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk1[0].requests_in[i].be
|vpiContAssign:
\_cont_assign: , line:95
|vpiRhs:
\_bit_select: (request.rnw), line:95
|vpiName:request.rnw
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk1[0].request.rnw
|vpiIndex:
\_ref_obj: (i), line:95
|vpiName:i
|vpiLhs:
\_ref_obj: (requests_in[i].rnw), line:95
|vpiName:requests_in[i].rnw
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk1[0].requests_in[i].rnw
|vpiContAssign:
\_cont_assign: , line:96
|vpiRhs:
\_bit_select: (request.is_amo), line:96
|vpiName:request.is_amo
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk1[0].request.is_amo
|vpiIndex:
\_ref_obj: (i), line:96
|vpiName:i
|vpiLhs:
\_ref_obj: (requests_in[i].is_amo), line:96
|vpiName:requests_in[i].is_amo
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk1[0].requests_in[i].is_amo
|vpiContAssign:
\_cont_assign: , line:97
|vpiRhs:
\_bit_select: (request.amo_type_or_burst_size), line:97
|vpiName:request.amo_type_or_burst_size
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk1[0].request.amo_type_or_burst_size
|vpiIndex:
\_ref_obj: (i), line:97
|vpiName:i
|vpiLhs:
\_ref_obj: (requests_in[i].amo_type_or_burst_size), line:97
|vpiName:requests_in[i].amo_type_or_burst_size
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk1[0].requests_in[i].amo_type_or_burst_size
|vpiContAssign:
\_cont_assign: , line:98
|vpiRhs:
\_bit_select: (request.sub_id), line:98
|vpiName:request.sub_id
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk1[0].request.sub_id
|vpiIndex:
\_ref_obj: (i), line:98
|vpiName:i
|vpiLhs:
\_ref_obj: (requests_in[i].sub_id), line:98
|vpiName:requests_in[i].sub_id
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk1[0].requests_in[i].sub_id
|vpiContAssign:
\_cont_assign: , line:99
|vpiRhs:
\_bit_select: (requests_in), line:99
|vpiName:requests_in
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk1[0].requests_in
|vpiIndex:
\_ref_obj: (i), line:99
|vpiName:i
|vpiLhs:
\_ref_obj: (input_fifos[i].data_in), line:99
|vpiName:input_fifos[i].data_in
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk1[0].input_fifos[i].data_in
|vpiContAssign:
\_cont_assign: , line:101
|vpiRhs:
\_operation: , line:101
|vpiOpType:28
|vpiOperand:
\_operation: , line:101
|vpiOpType:28
|vpiOperand:
\_bit_select: (input_fifos.valid), line:101
|vpiName:input_fifos.valid
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk1[0].input_fifos.valid
|vpiIndex:
\_ref_obj: (i), line:101
|vpiName:i
|vpiOperand:
\_ref_obj: (arb.grantee_v), line:101
|vpiName:arb.grantee_v
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk1[0].arb.grantee_v
|vpiOperand:
\_operation: , line:101
|vpiOpType:4
|vpiOperand:
\_ref_obj: (mem_addr_fifo.full), line:101
|vpiName:mem_addr_fifo.full
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk1[0].mem_addr_fifo.full
|vpiLhs:
\_ref_obj: (input_fifos[i].pop), line:101
|vpiName:input_fifos[i].pop
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk1[0].input_fifos[i].pop
|vpiContAssign:
\_cont_assign: , line:103
|vpiRhs:
\_bit_select: (input_fifos.full), line:103
|vpiName:input_fifos.full
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk1[0].input_fifos.full
|vpiIndex:
\_ref_obj: (i), line:103
|vpiName:i
|vpiLhs:
\_ref_obj: (request[i].request_full), line:103
|vpiName:request[i].request_full
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk1[0].request[i].request_full
|vpiContAssign:
\_cont_assign: , line:109
|vpiRhs:
\_bit_select: (input_fifos.data_out), line:109
|vpiName:input_fifos.data_out
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk1[0].input_fifos.data_out
|vpiIndex:
\_ref_obj: (i), line:109
|vpiName:i
|vpiLhs:
\_bit_select: (requests), line:109
|vpiName:requests
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk1[0].requests
|vpiIndex:
\_ref_obj: (i), line:109
|vpiName:i
|vpiContAssign:
\_cont_assign: , line:110
|vpiRhs:
\_bit_select: (input_fifos.valid), line:110
|vpiName:input_fifos.valid
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk1[0].input_fifos.valid
|vpiIndex:
\_ref_obj: (i), line:110
|vpiName:i
|vpiLhs:
\_ref_obj: (arb.requests), line:110
|vpiName:arb.requests
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk1[0].arb.requests
|vpiModule:
\_module: work@l2_fifo (input_fifo), file:third_party/cores/taiga/l2_arbiter/l2_arbiter.sv, line:106
|vpiDefName:work@l2_fifo
|vpiName:input_fifo
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk1[0].input_fifo
|vpiPort:
\_port: (clk), line:25, parent:input_fifo
|vpiName:clk
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (clk), line:106
|vpiName:clk
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (clk), line:25, parent:input_fifo
|vpiName:clk
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk1[0].input_fifo.clk
|vpiNetType:36
|vpiPort:
\_port: (wr_clk), line:26, parent:input_fifo
|vpiName:wr_clk
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (wr_clk), line:106
|vpiName:wr_clk
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (wr_clk), line:26, parent:input_fifo
|vpiName:wr_clk
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk1[0].input_fifo.wr_clk
|vpiNetType:36
|vpiPort:
\_port: (rd_clk), line:27, parent:input_fifo
|vpiName:rd_clk
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (rd_clk), line:106
|vpiName:rd_clk
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (rd_clk), line:27, parent:input_fifo
|vpiName:rd_clk
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk1[0].input_fifo.rd_clk
|vpiNetType:36
|vpiPort:
\_port: (rst), line:29, parent:input_fifo
|vpiName:rst
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (rst), line:106
|vpiName:rst
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (rst), line:29, parent:input_fifo
|vpiName:rst
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk1[0].input_fifo.rst
|vpiNetType:36
|vpiPort:
\_port: (fifo), line:30, parent:input_fifo
|vpiName:fifo
|vpiDirection:5
|vpiHighConn:
\_ref_obj: (fifo), line:106
|vpiName:fifo
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_modport: (structure)
|vpiName:structure
|vpiIODecl:
\_io_decl: (push)
|vpiName:push
|vpiDirection:1
|vpiExpr:
\_logic_net: (push), line:26
|vpiName:push
|vpiNetType:36
|vpiIODecl:
\_io_decl: (pop)
|vpiName:pop
|vpiDirection:1
|vpiExpr:
\_logic_net: (pop), line:27
|vpiName:pop
|vpiNetType:36
|vpiIODecl:
\_io_decl: (data_in)
|vpiName:data_in
|vpiDirection:1
|vpiExpr:
\_logic_net: (data_in), line:28
|vpiName:data_in
|vpiNetType:36
|vpiRange:
\_range: , line:28
|vpiLeftRange:
\_constant: , line:28
|vpiDecompile:-1
|INT:-1
|vpiRightRange:
\_constant: , line:28
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (data_out)
|vpiName:data_out
|vpiDirection:2
|vpiExpr:
\_logic_net: (data_out), line:29
|vpiName:data_out
|vpiNetType:36
|vpiRange:
\_range: , line:29
|vpiLeftRange:
\_constant: , line:29
|vpiDecompile:-1
|INT:-1
|vpiRightRange:
\_constant: , line:29
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (valid)
|vpiName:valid
|vpiDirection:2
|vpiExpr:
\_logic_net: (valid), line:30
|vpiName:valid
|vpiNetType:36
|vpiIODecl:
\_io_decl: (full)
|vpiName:full
|vpiDirection:2
|vpiExpr:
\_logic_net: (full), line:31
|vpiName:full
|vpiNetType:36
|vpiIODecl:
\_io_decl: (empty)
|vpiName:empty
|vpiDirection:2
|vpiExpr:
\_logic_net: (empty), line:32
|vpiName:empty
|vpiNetType:36
|vpiInterface:
\_interface: work@l2_fifo_interface (fifo), file:third_party/cores/taiga/l2_arbiter/l2_arbiter.sv, line:106
|vpiDefName:work@l2_fifo_interface
|vpiName:fifo
|vpiModport:
\_modport: (dequeue)
|vpiName:dequeue
|vpiIODecl:
\_io_decl: (valid)
|vpiName:valid
|vpiDirection:1
|vpiExpr:
\_logic_net: (valid), line:30
|vpiIODecl:
\_io_decl: (data_out)
|vpiName:data_out
|vpiDirection:1
|vpiExpr:
\_logic_net: (data_out), line:29
|vpiIODecl:
\_io_decl: (pop)
|vpiName:pop
|vpiDirection:2
|vpiExpr:
\_logic_net: (pop), line:27
|vpiInterface:
\_interface: work@l2_fifo_interface (fifo), file:third_party/cores/taiga/l2_arbiter/l2_arbiter.sv, line:106
|vpiModport:
\_modport: (enqueue)
|vpiName:enqueue
|vpiIODecl:
\_io_decl: (full)
|vpiName:full
|vpiDirection:1
|vpiExpr:
\_logic_net: (full), line:31
|vpiIODecl:
\_io_decl: (empty)
|vpiName:empty
|vpiDirection:1
|vpiExpr:
\_logic_net: (empty), line:32
|vpiIODecl:
\_io_decl: (data_in)
|vpiName:data_in
|vpiDirection:2
|vpiExpr:
\_logic_net: (data_in), line:28
|vpiIODecl:
\_io_decl: (push)
|vpiName:push
|vpiDirection:2
|vpiExpr:
\_logic_net: (push), line:26
|vpiInterface:
\_interface: work@l2_fifo_interface (fifo), file:third_party/cores/taiga/l2_arbiter/l2_arbiter.sv, line:106
|vpiModport:
\_modport: (structure)
|vpiGenScopeArray:
\_gen_scope_array: (genblk1), line:37, parent:input_fifo
|vpiName:genblk1
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk1[0].input_fifo.genblk1
|vpiGenScope:
\_gen_scope: , parent:genblk1
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk1[0].input_fifo.genblk1
|vpiGenScopeArray:
\_gen_scope_array: (genblk1), line:54
|vpiName:genblk1
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk1[0].input_fifo.genblk1.genblk1
|vpiGenScope:
\_gen_scope: , parent:genblk1
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk1[0].input_fifo.genblk1.genblk1
|vpiNet:
\_logic_net: (write_index), line:58
|vpiName:write_index
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk1[0].input_fifo.genblk1.genblk1.write_index
|vpiNetType:36
|vpiRange:
\_range: , line:58
|vpiLeftRange:
\_constant: , line:58
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:58
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (read_index), line:59
|vpiName:read_index
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk1[0].input_fifo.genblk1.genblk1.read_index
|vpiNetType:36
|vpiRange:
\_range: , line:59
|vpiLeftRange:
\_constant: , line:59
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:59
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiProcess:
\_always: , line:67
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:67
|vpiCondition:
\_operation: , line:67
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:67
|vpiName:clk
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk1[0].input_fifo.genblk1.genblk1.clk
|vpiStmt:
\_begin: , line:67
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk1[0].input_fifo.genblk1.genblk1
|vpiStmt:
\_if_else: , line:68
|vpiCondition:
\_ref_obj: (rst), line:68
|vpiName:rst
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk1[0].input_fifo.genblk1.genblk1.rst
|vpiStmt:
\_begin: , line:68
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk1[0].input_fifo.genblk1.genblk1
|vpiStmt:
\_assignment: , line:69
|vpiOpType:82
|vpiLhs:
\_ref_obj: (read_index), line:69
|vpiName:read_index
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk1[0].input_fifo.genblk1.genblk1.read_index
|vpiRhs:
\_constant: , line:69
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiStmt:
\_assignment: , line:70
|vpiOpType:82
|vpiLhs:
\_ref_obj: (write_index), line:70
|vpiName:write_index
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk1[0].input_fifo.genblk1.genblk1.write_index
|vpiRhs:
\_constant: , line:70
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiElseStmt:
\_begin: , line:72
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk1[0].input_fifo.genblk1.genblk1
|vpiStmt:
\_assignment: , line:73
|vpiOpType:82
|vpiLhs:
\_ref_obj: (read_index), line:73
|vpiName:read_index
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk1[0].input_fifo.genblk1.genblk1.read_index
|vpiRhs:
\_operation: , line:73
|vpiOpType:24
|vpiOperand:
\_ref_obj: (read_index), line:73
|vpiName:read_index
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk1[0].input_fifo.genblk1.genblk1.read_index
|vpiOperand:
\_ref_obj: (fifo.pop), line:73
|vpiName:fifo.pop
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk1[0].input_fifo.genblk1.genblk1.fifo.pop
|vpiStmt:
\_assignment: , line:74
|vpiOpType:82
|vpiLhs:
\_ref_obj: (write_index), line:74
|vpiName:write_index
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk1[0].input_fifo.genblk1.genblk1.write_index
|vpiRhs:
\_operation: , line:74
|vpiOpType:24
|vpiOperand:
\_ref_obj: (write_index), line:74
|vpiName:write_index
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk1[0].input_fifo.genblk1.genblk1.write_index
|vpiOperand:
\_ref_obj: (fifo.push), line:74
|vpiName:fifo.push
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk1[0].input_fifo.genblk1.genblk1.fifo.push
|vpiProcess:
\_always: , line:81
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:81
|vpiCondition:
\_operation: , line:81
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:81
|vpiName:clk
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk1[0].input_fifo.genblk1.genblk1.clk
|vpiStmt:
\_begin: , line:81
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk1[0].input_fifo.genblk1.genblk1
|vpiStmt:
\_if_stmt: , line:82
|vpiCondition:
\_ref_obj: (fifo.push), line:82
|vpiName:fifo.push
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk1[0].input_fifo.genblk1.genblk1.fifo.push
|vpiStmt:
\_assignment: , line:83
|vpiOpType:82
|vpiLhs:
\_bit_select: (lut_ram), line:83
|vpiName:lut_ram
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk1[0].input_fifo.genblk1.genblk1.lut_ram
|vpiIndex:
\_ref_obj: (write_index), line:83
|vpiName:write_index
|vpiRhs:
\_ref_obj: (fifo.data_in), line:83
|vpiName:fifo.data_in
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk1[0].input_fifo.genblk1.genblk1.fifo.data_in
|vpiProcess:
\_always: , line:86
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:86
|vpiCondition:
\_operation: , line:86
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:86
|vpiName:clk
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk1[0].input_fifo.genblk1.genblk1.clk
|vpiStmt:
\_begin: , line:86
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk1[0].input_fifo.genblk1.genblk1
|vpiStmt:
\_if_else: , line:87
|vpiCondition:
\_ref_obj: (rst), line:87
|vpiName:rst
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk1[0].input_fifo.genblk1.genblk1.rst
|vpiStmt:
\_begin: , line:87
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk1[0].input_fifo.genblk1.genblk1
|vpiStmt:
\_assignment: , line:88
|vpiOpType:82
|vpiLhs:
\_bit_select: (count_v), line:88
|vpiName:count_v
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk1[0].input_fifo.genblk1.genblk1.count_v
|vpiIndex:
\_constant: , line:88
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiRhs:
\_constant: , line:88
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiStmt:
\_for_stmt: , line:89
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk1[0].input_fifo.genblk1.genblk1
|vpiCondition:
\_operation: , line:89
|vpiOpType:21
|vpiOperand:
\_ref_obj: (i), line:89
|vpiName:i
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk1[0].input_fifo.genblk1.genblk1.i
|vpiOperand:
\_ref_obj: (FIFO_DEPTH), line:89
|vpiName:FIFO_DEPTH
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk1[0].input_fifo.genblk1.genblk1.FIFO_DEPTH
|vpiForInitStmt:
\_assign_stmt:
|vpiRhs:
\_constant: , line:89
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiLhs:
\_int_var: (i), line:89
|vpiName:i
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk1[0].input_fifo.genblk1.genblk1.i
|vpiForIncStmt:
\_operation: , line:89
|vpiOpType:62
|vpiOperand:
\_ref_obj: (i), line:89
|vpiName:i
|vpiStmt:
\_assignment: , line:89
|vpiOpType:82
|vpiLhs:
\_bit_select: (count_v), line:89
|vpiName:count_v
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk1[0].input_fifo.genblk1.genblk1.count_v
|vpiIndex:
\_ref_obj: (i), line:89
|vpiName:i
|vpiRhs:
\_constant: , line:89
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiElseStmt:
\_if_else: , line:91
|vpiCondition:
\_operation: , line:91
|vpiOpType:28
|vpiOperand:
\_ref_obj: (fifo.push), line:91
|vpiName:fifo.push
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk1[0].input_fifo.genblk1.genblk1.fifo.push
|vpiOperand:
\_operation: , line:91
|vpiOpType:4
|vpiOperand:
\_ref_obj: (fifo.pop), line:91
|vpiName:fifo.pop
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk1[0].input_fifo.genblk1.genblk1.fifo.pop
|vpiStmt:
\_assignment: , line:92
|vpiOpType:82
|vpiLhs:
\_ref_obj: (count_v), line:92
|vpiName:count_v
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk1[0].input_fifo.genblk1.genblk1.count_v
|vpiRhs:
\_operation: , line:92
|vpiOpType:33
|vpiOperand:
\_part_select: , line:92, parent:count_v
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (count_v)
|vpiLeftRange:
\_operation: , line:92
|vpiOpType:11
|vpiOperand:
\_ref_obj: (FIFO_DEPTH), line:92
|vpiName:FIFO_DEPTH
|vpiOperand:
\_constant: , line:92
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:92
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiOperand:
\_constant: , line:92
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiElseStmt:
\_if_stmt: , line:93
|vpiCondition:
\_operation: , line:93
|vpiOpType:28
|vpiOperand:
\_operation: , line:93
|vpiOpType:4
|vpiOperand:
\_ref_obj: (fifo.push), line:93
|vpiName:fifo.push
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk1[0].input_fifo.genblk1.genblk1.fifo.push
|vpiOperand:
\_ref_obj: (fifo.pop), line:93
|vpiName:fifo.pop
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk1[0].input_fifo.genblk1.genblk1.fifo.pop
|vpiStmt:
\_assignment: , line:94
|vpiOpType:82
|vpiLhs:
\_ref_obj: (count_v), line:94
|vpiName:count_v
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk1[0].input_fifo.genblk1.genblk1.count_v
|vpiRhs:
\_operation: , line:94
|vpiOpType:33
|vpiOperand:
\_constant: , line:94
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiOperand:
\_part_select: , line:94, parent:count_v
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (count_v)
|vpiLeftRange:
\_ref_obj: (FIFO_DEPTH), line:94
|vpiName:FIFO_DEPTH
|vpiRightRange:
\_constant: , line:94
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiArrayNet:
\_array_net: (lut_ram), line:56
|vpiName:lut_ram
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk1[0].input_fifo.genblk1.genblk1.lut_ram
|vpiSize:4
|vpiNet:
\_logic_net: , parent:lut_ram
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk1[0].input_fifo.genblk1.genblk1.lut_ram
|vpiNetType:36
|vpiRange:
\_range: , line:56
|vpiLeftRange:
\_constant: , line:56
|vpiDecompile:-1
|INT:-1
|vpiRightRange:
\_constant: , line:56
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiRange:
\_range: , line:56
|vpiLeftRange:
\_constant: , line:56
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiRightRange:
\_constant: , line:56
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiArrayNet:
\_array_net: (count_v), line:61
|vpiName:count_v
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk1[0].input_fifo.genblk1.genblk1.count_v
|vpiSize:5
|vpiNet:
\_logic_net: , parent:count_v
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk1[0].input_fifo.genblk1.genblk1.count_v
|vpiNetType:36
|vpiRange:
\_range: , line:61
|vpiLeftRange:
\_constant: , line:61
|vpiConstType:7
|vpiDecompile:4
|vpiSize:32
|INT:4
|vpiRightRange:
\_constant: , line:61
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiContAssign:
\_cont_assign: , line:65
|vpiRhs:
\_bit_select: (lut_ram), line:65
|vpiName:lut_ram
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk1[0].input_fifo.genblk1.genblk1.lut_ram
|vpiIndex:
\_ref_obj: (read_index), line:65
|vpiName:read_index
|vpiLhs:
\_ref_obj: (fifo.data_out), line:65
|vpiName:fifo.data_out
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk1[0].input_fifo.genblk1.genblk1.fifo.data_out
|vpiContAssign:
\_cont_assign: , line:78
|vpiRhs:
\_bit_select: (count_v), line:78
|vpiName:count_v
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk1[0].input_fifo.genblk1.genblk1.count_v
|vpiIndex:
\_ref_obj: (FIFO_DEPTH), line:78
|vpiName:FIFO_DEPTH
|vpiLhs:
\_ref_obj: (fifo.full), line:78
|vpiName:fifo.full
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk1[0].input_fifo.genblk1.genblk1.fifo.full
|vpiContAssign:
\_cont_assign: , line:79
|vpiRhs:
\_operation: , line:79
|vpiOpType:4
|vpiOperand:
\_bit_select: (count_v), line:79
|vpiName:count_v
|vpiIndex:
\_constant: , line:79
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiLhs:
\_ref_obj: (fifo.valid), line:79
|vpiName:fifo.valid
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk1[0].input_fifo.genblk1.genblk1.fifo.valid
|vpiNet:
\_logic_net: (clk), line:25, parent:input_fifo
|vpiNet:
\_logic_net: (wr_clk), line:26, parent:input_fifo
|vpiNet:
\_logic_net: (rd_clk), line:27, parent:input_fifo
|vpiNet:
\_logic_net: (rst), line:29, parent:input_fifo
|vpiNet:
\_logic_net: (fifo), line:30, parent:input_fifo
|vpiName:fifo
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk1[0].input_fifo.fifo
|vpiParameter:
\_parameter: (ASYNC), line:23
|vpiName:ASYNC
|INT:0
|vpiParameter:
\_parameter: (DATA_WIDTH), line:106
|vpiName:DATA_WIDTH
|INT:0
|vpiParameter:
\_parameter: (FIFO_DEPTH), line:106
|vpiName:FIFO_DEPTH
|INT:4
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (L2_DATA_ATTRIBUTES_FIFO_DEPTH), line:41
|vpiName:L2_DATA_ATTRIBUTES_FIFO_DEPTH
|INT:16
|vpiParameter:
\_parameter: (L2_ID_W), line:46
|vpiName:L2_ID_W
|INT:3
|vpiParameter:
\_parameter: (L2_INPUT_FIFO_DEPTHS), line:34
|vpiName:L2_INPUT_FIFO_DEPTHS
|INT:4
|vpiParameter:
\_parameter: (L2_INVALIDATION_FIFO_DEPTHS), line:35
|vpiName:L2_INVALIDATION_FIFO_DEPTHS
|INT:4
|vpiParameter:
\_parameter: (L2_MEM_ADDR_FIFO_DEPTH), line:39
|vpiName:L2_MEM_ADDR_FIFO_DEPTH
|INT:8
|vpiParameter:
\_parameter: (L2_NUM_PORTS), line:26
|vpiName:L2_NUM_PORTS
|INT:2
|vpiParameter:
\_parameter: (L2_READ_RETURN_FIFO_DEPTHS), line:36
|vpiName:L2_READ_RETURN_FIFO_DEPTHS
|INT:1
|vpiParameter:
\_parameter: (L2_SUB_ID_W), line:27
|vpiName:L2_SUB_ID_W
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiParameter:
\_parameter: (i), line:88
|vpiName:i
|INT:0
|vpiGenScopeArray:
\_gen_scope_array: (genblk1[1]), line:88, parent:l2_arb
|vpiName:genblk1[1]
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk1[1]
|vpiGenScope:
\_gen_scope: , parent:genblk1[1]
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk1[1]
|vpiContAssign:
\_cont_assign: , line:90
|vpiRhs:
\_bit_select: (request.request_push), line:90
|vpiName:request.request_push
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk1[1].request.request_push
|vpiIndex:
\_ref_obj: (i), line:90
|vpiName:i
|vpiLhs:
\_ref_obj: (input_fifos[i].push), line:90
|vpiName:input_fifos[i].push
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk1[1].input_fifos[i].push
|vpiContAssign:
\_cont_assign: , line:93
|vpiRhs:
\_bit_select: (request.addr), line:93
|vpiName:request.addr
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk1[1].request.addr
|vpiIndex:
\_ref_obj: (i), line:93
|vpiName:i
|vpiLhs:
\_ref_obj: (requests_in[i].addr), line:93
|vpiName:requests_in[i].addr
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk1[1].requests_in[i].addr
|vpiContAssign:
\_cont_assign: , line:94
|vpiRhs:
\_bit_select: (request.be), line:94
|vpiName:request.be
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk1[1].request.be
|vpiIndex:
\_ref_obj: (i), line:94
|vpiName:i
|vpiLhs:
\_ref_obj: (requests_in[i].be), line:94
|vpiName:requests_in[i].be
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk1[1].requests_in[i].be
|vpiContAssign:
\_cont_assign: , line:95
|vpiRhs:
\_bit_select: (request.rnw), line:95
|vpiName:request.rnw
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk1[1].request.rnw
|vpiIndex:
\_ref_obj: (i), line:95
|vpiName:i
|vpiLhs:
\_ref_obj: (requests_in[i].rnw), line:95
|vpiName:requests_in[i].rnw
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk1[1].requests_in[i].rnw
|vpiContAssign:
\_cont_assign: , line:96
|vpiRhs:
\_bit_select: (request.is_amo), line:96
|vpiName:request.is_amo
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk1[1].request.is_amo
|vpiIndex:
\_ref_obj: (i), line:96
|vpiName:i
|vpiLhs:
\_ref_obj: (requests_in[i].is_amo), line:96
|vpiName:requests_in[i].is_amo
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk1[1].requests_in[i].is_amo
|vpiContAssign:
\_cont_assign: , line:97
|vpiRhs:
\_bit_select: (request.amo_type_or_burst_size), line:97
|vpiName:request.amo_type_or_burst_size
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk1[1].request.amo_type_or_burst_size
|vpiIndex:
\_ref_obj: (i), line:97
|vpiName:i
|vpiLhs:
\_ref_obj: (requests_in[i].amo_type_or_burst_size), line:97
|vpiName:requests_in[i].amo_type_or_burst_size
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk1[1].requests_in[i].amo_type_or_burst_size
|vpiContAssign:
\_cont_assign: , line:98
|vpiRhs:
\_bit_select: (request.sub_id), line:98
|vpiName:request.sub_id
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk1[1].request.sub_id
|vpiIndex:
\_ref_obj: (i), line:98
|vpiName:i
|vpiLhs:
\_ref_obj: (requests_in[i].sub_id), line:98
|vpiName:requests_in[i].sub_id
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk1[1].requests_in[i].sub_id
|vpiContAssign:
\_cont_assign: , line:99
|vpiRhs:
\_bit_select: (requests_in), line:99
|vpiName:requests_in
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk1[1].requests_in
|vpiIndex:
\_ref_obj: (i), line:99
|vpiName:i
|vpiLhs:
\_ref_obj: (input_fifos[i].data_in), line:99
|vpiName:input_fifos[i].data_in
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk1[1].input_fifos[i].data_in
|vpiContAssign:
\_cont_assign: , line:101
|vpiRhs:
\_operation: , line:101
|vpiOpType:28
|vpiOperand:
\_operation: , line:101
|vpiOpType:28
|vpiOperand:
\_bit_select: (input_fifos.valid), line:101
|vpiName:input_fifos.valid
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk1[1].input_fifos.valid
|vpiIndex:
\_ref_obj: (i), line:101
|vpiName:i
|vpiOperand:
\_ref_obj: (arb.grantee_v), line:101
|vpiName:arb.grantee_v
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk1[1].arb.grantee_v
|vpiOperand:
\_operation: , line:101
|vpiOpType:4
|vpiOperand:
\_ref_obj: (mem_addr_fifo.full), line:101
|vpiName:mem_addr_fifo.full
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk1[1].mem_addr_fifo.full
|vpiLhs:
\_ref_obj: (input_fifos[i].pop), line:101
|vpiName:input_fifos[i].pop
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk1[1].input_fifos[i].pop
|vpiContAssign:
\_cont_assign: , line:103
|vpiRhs:
\_bit_select: (input_fifos.full), line:103
|vpiName:input_fifos.full
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk1[1].input_fifos.full
|vpiIndex:
\_ref_obj: (i), line:103
|vpiName:i
|vpiLhs:
\_ref_obj: (request[i].request_full), line:103
|vpiName:request[i].request_full
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk1[1].request[i].request_full
|vpiContAssign:
\_cont_assign: , line:109
|vpiRhs:
\_bit_select: (input_fifos.data_out), line:109
|vpiName:input_fifos.data_out
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk1[1].input_fifos.data_out
|vpiIndex:
\_ref_obj: (i), line:109
|vpiName:i
|vpiLhs:
\_bit_select: (requests), line:109
|vpiName:requests
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk1[1].requests
|vpiIndex:
\_ref_obj: (i), line:109
|vpiName:i
|vpiContAssign:
\_cont_assign: , line:110
|vpiRhs:
\_bit_select: (input_fifos.valid), line:110
|vpiName:input_fifos.valid
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk1[1].input_fifos.valid
|vpiIndex:
\_ref_obj: (i), line:110
|vpiName:i
|vpiLhs:
\_ref_obj: (arb.requests), line:110
|vpiName:arb.requests
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk1[1].arb.requests
|vpiModule:
\_module: work@l2_fifo (input_fifo), file:third_party/cores/taiga/l2_arbiter/l2_arbiter.sv, line:106
|vpiDefName:work@l2_fifo
|vpiName:input_fifo
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk1[1].input_fifo
|vpiPort:
\_port: (clk), line:25, parent:input_fifo
|vpiName:clk
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (clk), line:106
|vpiName:clk
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (clk), line:25, parent:input_fifo
|vpiName:clk
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk1[1].input_fifo.clk
|vpiNetType:36
|vpiPort:
\_port: (wr_clk), line:26, parent:input_fifo
|vpiName:wr_clk
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (wr_clk), line:106
|vpiName:wr_clk
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (wr_clk), line:26, parent:input_fifo
|vpiName:wr_clk
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk1[1].input_fifo.wr_clk
|vpiNetType:36
|vpiPort:
\_port: (rd_clk), line:27, parent:input_fifo
|vpiName:rd_clk
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (rd_clk), line:106
|vpiName:rd_clk
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (rd_clk), line:27, parent:input_fifo
|vpiName:rd_clk
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk1[1].input_fifo.rd_clk
|vpiNetType:36
|vpiPort:
\_port: (rst), line:29, parent:input_fifo
|vpiName:rst
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (rst), line:106
|vpiName:rst
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (rst), line:29, parent:input_fifo
|vpiName:rst
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk1[1].input_fifo.rst
|vpiNetType:36
|vpiPort:
\_port: (fifo), line:30, parent:input_fifo
|vpiName:fifo
|vpiDirection:5
|vpiHighConn:
\_ref_obj: (fifo), line:106
|vpiName:fifo
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_modport: (structure)
|vpiName:structure
|vpiIODecl:
\_io_decl: (push)
|vpiName:push
|vpiDirection:1
|vpiExpr:
\_logic_net: (push), line:26
|vpiName:push
|vpiNetType:36
|vpiIODecl:
\_io_decl: (pop)
|vpiName:pop
|vpiDirection:1
|vpiExpr:
\_logic_net: (pop), line:27
|vpiName:pop
|vpiNetType:36
|vpiIODecl:
\_io_decl: (data_in)
|vpiName:data_in
|vpiDirection:1
|vpiExpr:
\_logic_net: (data_in), line:28
|vpiName:data_in
|vpiNetType:36
|vpiRange:
\_range: , line:28
|vpiLeftRange:
\_constant: , line:28
|vpiDecompile:-1
|INT:-1
|vpiRightRange:
\_constant: , line:28
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (data_out)
|vpiName:data_out
|vpiDirection:2
|vpiExpr:
\_logic_net: (data_out), line:29
|vpiName:data_out
|vpiNetType:36
|vpiRange:
\_range: , line:29
|vpiLeftRange:
\_constant: , line:29
|vpiDecompile:-1
|INT:-1
|vpiRightRange:
\_constant: , line:29
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (valid)
|vpiName:valid
|vpiDirection:2
|vpiExpr:
\_logic_net: (valid), line:30
|vpiName:valid
|vpiNetType:36
|vpiIODecl:
\_io_decl: (full)
|vpiName:full
|vpiDirection:2
|vpiExpr:
\_logic_net: (full), line:31
|vpiName:full
|vpiNetType:36
|vpiIODecl:
\_io_decl: (empty)
|vpiName:empty
|vpiDirection:2
|vpiExpr:
\_logic_net: (empty), line:32
|vpiName:empty
|vpiNetType:36
|vpiInterface:
\_interface: work@l2_fifo_interface (fifo), file:third_party/cores/taiga/l2_arbiter/l2_arbiter.sv, line:106
|vpiDefName:work@l2_fifo_interface
|vpiName:fifo
|vpiModport:
\_modport: (dequeue)
|vpiName:dequeue
|vpiIODecl:
\_io_decl: (valid)
|vpiName:valid
|vpiDirection:1
|vpiExpr:
\_logic_net: (valid), line:30
|vpiIODecl:
\_io_decl: (data_out)
|vpiName:data_out
|vpiDirection:1
|vpiExpr:
\_logic_net: (data_out), line:29
|vpiIODecl:
\_io_decl: (pop)
|vpiName:pop
|vpiDirection:2
|vpiExpr:
\_logic_net: (pop), line:27
|vpiInterface:
\_interface: work@l2_fifo_interface (fifo), file:third_party/cores/taiga/l2_arbiter/l2_arbiter.sv, line:106
|vpiModport:
\_modport: (enqueue)
|vpiName:enqueue
|vpiIODecl:
\_io_decl: (full)
|vpiName:full
|vpiDirection:1
|vpiExpr:
\_logic_net: (full), line:31
|vpiIODecl:
\_io_decl: (empty)
|vpiName:empty
|vpiDirection:1
|vpiExpr:
\_logic_net: (empty), line:32
|vpiIODecl:
\_io_decl: (data_in)
|vpiName:data_in
|vpiDirection:2
|vpiExpr:
\_logic_net: (data_in), line:28
|vpiIODecl:
\_io_decl: (push)
|vpiName:push
|vpiDirection:2
|vpiExpr:
\_logic_net: (push), line:26
|vpiInterface:
\_interface: work@l2_fifo_interface (fifo), file:third_party/cores/taiga/l2_arbiter/l2_arbiter.sv, line:106
|vpiModport:
\_modport: (structure)
|vpiGenScopeArray:
\_gen_scope_array: (genblk1), line:37, parent:input_fifo
|vpiName:genblk1
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk1[1].input_fifo.genblk1
|vpiGenScope:
\_gen_scope: , parent:genblk1
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk1[1].input_fifo.genblk1
|vpiGenScopeArray:
\_gen_scope_array: (genblk1), line:54
|vpiName:genblk1
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk1[1].input_fifo.genblk1.genblk1
|vpiGenScope:
\_gen_scope: , parent:genblk1
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk1[1].input_fifo.genblk1.genblk1
|vpiNet:
\_logic_net: (write_index), line:58
|vpiName:write_index
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk1[1].input_fifo.genblk1.genblk1.write_index
|vpiNetType:36
|vpiRange:
\_range: , line:58
|vpiLeftRange:
\_constant: , line:58
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:58
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (read_index), line:59
|vpiName:read_index
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk1[1].input_fifo.genblk1.genblk1.read_index
|vpiNetType:36
|vpiRange:
\_range: , line:59
|vpiLeftRange:
\_constant: , line:59
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:59
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiProcess:
\_always: , line:67
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:67
|vpiCondition:
\_operation: , line:67
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:67
|vpiName:clk
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk1[1].input_fifo.genblk1.genblk1.clk
|vpiStmt:
\_begin: , line:67
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk1[1].input_fifo.genblk1.genblk1
|vpiStmt:
\_if_else: , line:68
|vpiCondition:
\_ref_obj: (rst), line:68
|vpiName:rst
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk1[1].input_fifo.genblk1.genblk1.rst
|vpiStmt:
\_begin: , line:68
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk1[1].input_fifo.genblk1.genblk1
|vpiStmt:
\_assignment: , line:69
|vpiOpType:82
|vpiLhs:
\_ref_obj: (read_index), line:69
|vpiName:read_index
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk1[1].input_fifo.genblk1.genblk1.read_index
|vpiRhs:
\_constant: , line:69
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiStmt:
\_assignment: , line:70
|vpiOpType:82
|vpiLhs:
\_ref_obj: (write_index), line:70
|vpiName:write_index
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk1[1].input_fifo.genblk1.genblk1.write_index
|vpiRhs:
\_constant: , line:70
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiElseStmt:
\_begin: , line:72
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk1[1].input_fifo.genblk1.genblk1
|vpiStmt:
\_assignment: , line:73
|vpiOpType:82
|vpiLhs:
\_ref_obj: (read_index), line:73
|vpiName:read_index
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk1[1].input_fifo.genblk1.genblk1.read_index
|vpiRhs:
\_operation: , line:73
|vpiOpType:24
|vpiOperand:
\_ref_obj: (read_index), line:73
|vpiName:read_index
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk1[1].input_fifo.genblk1.genblk1.read_index
|vpiOperand:
\_ref_obj: (fifo.pop), line:73
|vpiName:fifo.pop
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk1[1].input_fifo.genblk1.genblk1.fifo.pop
|vpiStmt:
\_assignment: , line:74
|vpiOpType:82
|vpiLhs:
\_ref_obj: (write_index), line:74
|vpiName:write_index
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk1[1].input_fifo.genblk1.genblk1.write_index
|vpiRhs:
\_operation: , line:74
|vpiOpType:24
|vpiOperand:
\_ref_obj: (write_index), line:74
|vpiName:write_index
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk1[1].input_fifo.genblk1.genblk1.write_index
|vpiOperand:
\_ref_obj: (fifo.push), line:74
|vpiName:fifo.push
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk1[1].input_fifo.genblk1.genblk1.fifo.push
|vpiProcess:
\_always: , line:81
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:81
|vpiCondition:
\_operation: , line:81
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:81
|vpiName:clk
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk1[1].input_fifo.genblk1.genblk1.clk
|vpiStmt:
\_begin: , line:81
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk1[1].input_fifo.genblk1.genblk1
|vpiStmt:
\_if_stmt: , line:82
|vpiCondition:
\_ref_obj: (fifo.push), line:82
|vpiName:fifo.push
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk1[1].input_fifo.genblk1.genblk1.fifo.push
|vpiStmt:
\_assignment: , line:83
|vpiOpType:82
|vpiLhs:
\_bit_select: (lut_ram), line:83
|vpiName:lut_ram
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk1[1].input_fifo.genblk1.genblk1.lut_ram
|vpiIndex:
\_ref_obj: (write_index), line:83
|vpiName:write_index
|vpiRhs:
\_ref_obj: (fifo.data_in), line:83
|vpiName:fifo.data_in
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk1[1].input_fifo.genblk1.genblk1.fifo.data_in
|vpiProcess:
\_always: , line:86
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:86
|vpiCondition:
\_operation: , line:86
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:86
|vpiName:clk
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk1[1].input_fifo.genblk1.genblk1.clk
|vpiStmt:
\_begin: , line:86
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk1[1].input_fifo.genblk1.genblk1
|vpiStmt:
\_if_else: , line:87
|vpiCondition:
\_ref_obj: (rst), line:87
|vpiName:rst
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk1[1].input_fifo.genblk1.genblk1.rst
|vpiStmt:
\_begin: , line:87
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk1[1].input_fifo.genblk1.genblk1
|vpiStmt:
\_assignment: , line:88
|vpiOpType:82
|vpiLhs:
\_bit_select: (count_v), line:88
|vpiName:count_v
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk1[1].input_fifo.genblk1.genblk1.count_v
|vpiIndex:
\_constant: , line:88
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiRhs:
\_constant: , line:88
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiStmt:
\_for_stmt: , line:89
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk1[1].input_fifo.genblk1.genblk1
|vpiCondition:
\_operation: , line:89
|vpiOpType:21
|vpiOperand:
\_ref_obj: (i), line:89
|vpiName:i
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk1[1].input_fifo.genblk1.genblk1.i
|vpiOperand:
\_ref_obj: (FIFO_DEPTH), line:89
|vpiName:FIFO_DEPTH
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk1[1].input_fifo.genblk1.genblk1.FIFO_DEPTH
|vpiForInitStmt:
\_assign_stmt:
|vpiRhs:
\_constant: , line:89
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiLhs:
\_int_var: (i), line:89
|vpiName:i
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk1[1].input_fifo.genblk1.genblk1.i
|vpiForIncStmt:
\_operation: , line:89
|vpiOpType:62
|vpiOperand:
\_ref_obj: (i), line:89
|vpiName:i
|vpiStmt:
\_assignment: , line:89
|vpiOpType:82
|vpiLhs:
\_bit_select: (count_v), line:89
|vpiName:count_v
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk1[1].input_fifo.genblk1.genblk1.count_v
|vpiIndex:
\_ref_obj: (i), line:89
|vpiName:i
|vpiRhs:
\_constant: , line:89
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiElseStmt:
\_if_else: , line:91
|vpiCondition:
\_operation: , line:91
|vpiOpType:28
|vpiOperand:
\_ref_obj: (fifo.push), line:91
|vpiName:fifo.push
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk1[1].input_fifo.genblk1.genblk1.fifo.push
|vpiOperand:
\_operation: , line:91
|vpiOpType:4
|vpiOperand:
\_ref_obj: (fifo.pop), line:91
|vpiName:fifo.pop
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk1[1].input_fifo.genblk1.genblk1.fifo.pop
|vpiStmt:
\_assignment: , line:92
|vpiOpType:82
|vpiLhs:
\_ref_obj: (count_v), line:92
|vpiName:count_v
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk1[1].input_fifo.genblk1.genblk1.count_v
|vpiRhs:
\_operation: , line:92
|vpiOpType:33
|vpiOperand:
\_part_select: , line:92, parent:count_v
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (count_v)
|vpiLeftRange:
\_operation: , line:92
|vpiOpType:11
|vpiOperand:
\_ref_obj: (FIFO_DEPTH), line:92
|vpiName:FIFO_DEPTH
|vpiOperand:
\_constant: , line:92
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:92
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiOperand:
\_constant: , line:92
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiElseStmt:
\_if_stmt: , line:93
|vpiCondition:
\_operation: , line:93
|vpiOpType:28
|vpiOperand:
\_operation: , line:93
|vpiOpType:4
|vpiOperand:
\_ref_obj: (fifo.push), line:93
|vpiName:fifo.push
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk1[1].input_fifo.genblk1.genblk1.fifo.push
|vpiOperand:
\_ref_obj: (fifo.pop), line:93
|vpiName:fifo.pop
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk1[1].input_fifo.genblk1.genblk1.fifo.pop
|vpiStmt:
\_assignment: , line:94
|vpiOpType:82
|vpiLhs:
\_ref_obj: (count_v), line:94
|vpiName:count_v
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk1[1].input_fifo.genblk1.genblk1.count_v
|vpiRhs:
\_operation: , line:94
|vpiOpType:33
|vpiOperand:
\_constant: , line:94
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiOperand:
\_part_select: , line:94, parent:count_v
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (count_v)
|vpiLeftRange:
\_ref_obj: (FIFO_DEPTH), line:94
|vpiName:FIFO_DEPTH
|vpiRightRange:
\_constant: , line:94
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiArrayNet:
\_array_net: (lut_ram), line:56
|vpiName:lut_ram
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk1[1].input_fifo.genblk1.genblk1.lut_ram
|vpiSize:4
|vpiNet:
\_logic_net: , parent:lut_ram
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk1[1].input_fifo.genblk1.genblk1.lut_ram
|vpiNetType:36
|vpiRange:
\_range: , line:56
|vpiLeftRange:
\_constant: , line:56
|vpiDecompile:-1
|INT:-1
|vpiRightRange:
\_constant: , line:56
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiRange:
\_range: , line:56
|vpiLeftRange:
\_constant: , line:56
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiRightRange:
\_constant: , line:56
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiArrayNet:
\_array_net: (count_v), line:61
|vpiName:count_v
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk1[1].input_fifo.genblk1.genblk1.count_v
|vpiSize:5
|vpiNet:
\_logic_net: , parent:count_v
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk1[1].input_fifo.genblk1.genblk1.count_v
|vpiNetType:36
|vpiRange:
\_range: , line:61
|vpiLeftRange:
\_constant: , line:61
|vpiConstType:7
|vpiDecompile:4
|vpiSize:32
|INT:4
|vpiRightRange:
\_constant: , line:61
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiContAssign:
\_cont_assign: , line:65
|vpiRhs:
\_bit_select: (lut_ram), line:65
|vpiName:lut_ram
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk1[1].input_fifo.genblk1.genblk1.lut_ram
|vpiIndex:
\_ref_obj: (read_index), line:65
|vpiName:read_index
|vpiLhs:
\_ref_obj: (fifo.data_out), line:65
|vpiName:fifo.data_out
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk1[1].input_fifo.genblk1.genblk1.fifo.data_out
|vpiContAssign:
\_cont_assign: , line:78
|vpiRhs:
\_bit_select: (count_v), line:78
|vpiName:count_v
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk1[1].input_fifo.genblk1.genblk1.count_v
|vpiIndex:
\_ref_obj: (FIFO_DEPTH), line:78
|vpiName:FIFO_DEPTH
|vpiLhs:
\_ref_obj: (fifo.full), line:78
|vpiName:fifo.full
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk1[1].input_fifo.genblk1.genblk1.fifo.full
|vpiContAssign:
\_cont_assign: , line:79
|vpiRhs:
\_operation: , line:79
|vpiOpType:4
|vpiOperand:
\_bit_select: (count_v), line:79
|vpiName:count_v
|vpiIndex:
\_constant: , line:79
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiLhs:
\_ref_obj: (fifo.valid), line:79
|vpiName:fifo.valid
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk1[1].input_fifo.genblk1.genblk1.fifo.valid
|vpiNet:
\_logic_net: (clk), line:25, parent:input_fifo
|vpiNet:
\_logic_net: (wr_clk), line:26, parent:input_fifo
|vpiNet:
\_logic_net: (rd_clk), line:27, parent:input_fifo
|vpiNet:
\_logic_net: (rst), line:29, parent:input_fifo
|vpiNet:
\_logic_net: (fifo), line:30, parent:input_fifo
|vpiName:fifo
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk1[1].input_fifo.fifo
|vpiParameter:
\_parameter: (ASYNC), line:23
|vpiName:ASYNC
|INT:0
|vpiParameter:
\_parameter: (DATA_WIDTH), line:106
|vpiName:DATA_WIDTH
|INT:0
|vpiParameter:
\_parameter: (FIFO_DEPTH), line:106
|vpiName:FIFO_DEPTH
|INT:4
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (L2_DATA_ATTRIBUTES_FIFO_DEPTH), line:41
|vpiName:L2_DATA_ATTRIBUTES_FIFO_DEPTH
|INT:16
|vpiParameter:
\_parameter: (L2_ID_W), line:46
|vpiName:L2_ID_W
|INT:3
|vpiParameter:
\_parameter: (L2_INPUT_FIFO_DEPTHS), line:34
|vpiName:L2_INPUT_FIFO_DEPTHS
|INT:4
|vpiParameter:
\_parameter: (L2_INVALIDATION_FIFO_DEPTHS), line:35
|vpiName:L2_INVALIDATION_FIFO_DEPTHS
|INT:4
|vpiParameter:
\_parameter: (L2_MEM_ADDR_FIFO_DEPTH), line:39
|vpiName:L2_MEM_ADDR_FIFO_DEPTH
|INT:8
|vpiParameter:
\_parameter: (L2_NUM_PORTS), line:26
|vpiName:L2_NUM_PORTS
|INT:2
|vpiParameter:
\_parameter: (L2_READ_RETURN_FIFO_DEPTHS), line:36
|vpiName:L2_READ_RETURN_FIFO_DEPTHS
|INT:1
|vpiParameter:
\_parameter: (L2_SUB_ID_W), line:27
|vpiName:L2_SUB_ID_W
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiParameter:
\_parameter: (i), line:88
|vpiName:i
|INT:1
|vpiGenScopeArray:
\_gen_scope_array: (genblk2[0]), line:118, parent:l2_arb
|vpiName:genblk2[0]
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk2[0]
|vpiGenScope:
\_gen_scope: , parent:genblk2[0]
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk2[0]
|vpiContAssign:
\_cont_assign: , line:120
|vpiRhs:
\_bit_select: (request.wr_data_push), line:120
|vpiName:request.wr_data_push
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk2[0].request.wr_data_push
|vpiIndex:
\_ref_obj: (i), line:120
|vpiName:i
|vpiLhs:
\_ref_obj: (input_data_fifos[i].push), line:120
|vpiName:input_data_fifos[i].push
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk2[0].input_data_fifos[i].push
|vpiContAssign:
\_cont_assign: , line:121
|vpiRhs:
\_bit_select: (request.wr_data), line:121
|vpiName:request.wr_data
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk2[0].request.wr_data
|vpiIndex:
\_ref_obj: (i), line:121
|vpiName:i
|vpiLhs:
\_ref_obj: (input_data_fifos[i].data_in), line:121
|vpiName:input_data_fifos[i].data_in
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk2[0].input_data_fifos[i].data_in
|vpiContAssign:
\_cont_assign: , line:123
|vpiRhs:
\_bit_select: (input_data_fifos.full), line:123
|vpiName:input_data_fifos.full
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk2[0].input_data_fifos.full
|vpiIndex:
\_ref_obj: (i), line:123
|vpiName:i
|vpiLhs:
\_ref_obj: (request[i].data_full), line:123
|vpiName:request[i].data_full
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk2[0].request[i].data_full
|vpiContAssign:
\_cont_assign: , line:129
|vpiRhs:
\_operation: , line:129
|vpiOpType:26
|vpiOperand:
\_operation: , line:129
|vpiOpType:26
|vpiOperand:
\_ref_obj: (data_attributes.valid), line:129
|vpiName:data_attributes.valid
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk2[0].data_attributes.valid
|vpiOperand:
\_operation: , line:129
|vpiOpType:14
|vpiOperand:
\_ref_obj: (current_attr.id), line:129
|vpiName:current_attr.id
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk2[0].current_attr.id
|vpiOperand:
\_ref_obj: (i), line:129
|vpiName:i
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk2[0].i
|vpiOperand:
\_operation: , line:129
|vpiOpType:4
|vpiOperand:
\_ref_obj: (mem_data_fifo.full), line:129
|vpiName:mem_data_fifo.full
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk2[0].mem_data_fifo.full
|vpiLhs:
\_ref_obj: (input_data_fifos[i].pop), line:129
|vpiName:input_data_fifos[i].pop
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk2[0].input_data_fifos[i].pop
|vpiContAssign:
\_cont_assign: , line:131
|vpiRhs:
\_bit_select: (input_data_fifos.data_out), line:131
|vpiName:input_data_fifos.data_out
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk2[0].input_data_fifos.data_out
|vpiIndex:
\_ref_obj: (i), line:131
|vpiName:i
|vpiLhs:
\_bit_select: (input_data), line:131
|vpiName:input_data
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk2[0].input_data
|vpiIndex:
\_ref_obj: (i), line:131
|vpiName:i
|vpiModule:
\_module: work@l2_fifo (input_data_fifo), file:third_party/cores/taiga/l2_arbiter/l2_arbiter.sv, line:126
|vpiDefName:work@l2_fifo
|vpiName:input_data_fifo
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk2[0].input_data_fifo
|vpiPort:
\_port: (clk), line:25, parent:input_data_fifo
|vpiName:clk
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (clk), line:126
|vpiName:clk
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (clk), line:25, parent:input_data_fifo
|vpiName:clk
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk2[0].input_data_fifo.clk
|vpiNetType:36
|vpiPort:
\_port: (wr_clk), line:26, parent:input_data_fifo
|vpiName:wr_clk
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (wr_clk), line:126
|vpiName:wr_clk
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (wr_clk), line:26, parent:input_data_fifo
|vpiName:wr_clk
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk2[0].input_data_fifo.wr_clk
|vpiNetType:36
|vpiPort:
\_port: (rd_clk), line:27, parent:input_data_fifo
|vpiName:rd_clk
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (rd_clk), line:126
|vpiName:rd_clk
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (rd_clk), line:27, parent:input_data_fifo
|vpiName:rd_clk
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk2[0].input_data_fifo.rd_clk
|vpiNetType:36
|vpiPort:
\_port: (rst), line:29, parent:input_data_fifo
|vpiName:rst
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (rst), line:126
|vpiName:rst
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (rst), line:29, parent:input_data_fifo
|vpiName:rst
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk2[0].input_data_fifo.rst
|vpiNetType:36
|vpiPort:
\_port: (fifo), line:30, parent:input_data_fifo
|vpiName:fifo
|vpiDirection:5
|vpiHighConn:
\_ref_obj: (fifo), line:126
|vpiName:fifo
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_modport: (structure)
|vpiName:structure
|vpiIODecl:
\_io_decl: (push)
|vpiName:push
|vpiDirection:1
|vpiExpr:
\_logic_net: (push), line:26
|vpiName:push
|vpiNetType:36
|vpiIODecl:
\_io_decl: (pop)
|vpiName:pop
|vpiDirection:1
|vpiExpr:
\_logic_net: (pop), line:27
|vpiName:pop
|vpiNetType:36
|vpiIODecl:
\_io_decl: (data_in)
|vpiName:data_in
|vpiDirection:1
|vpiExpr:
\_logic_net: (data_in), line:28
|vpiName:data_in
|vpiNetType:36
|vpiRange:
\_range: , line:28
|vpiLeftRange:
\_constant: , line:28
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:28
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (data_out)
|vpiName:data_out
|vpiDirection:2
|vpiExpr:
\_logic_net: (data_out), line:29
|vpiName:data_out
|vpiNetType:36
|vpiRange:
\_range: , line:29
|vpiLeftRange:
\_constant: , line:29
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:29
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (valid)
|vpiName:valid
|vpiDirection:2
|vpiExpr:
\_logic_net: (valid), line:30
|vpiName:valid
|vpiNetType:36
|vpiIODecl:
\_io_decl: (full)
|vpiName:full
|vpiDirection:2
|vpiExpr:
\_logic_net: (full), line:31
|vpiName:full
|vpiNetType:36
|vpiIODecl:
\_io_decl: (empty)
|vpiName:empty
|vpiDirection:2
|vpiExpr:
\_logic_net: (empty), line:32
|vpiName:empty
|vpiNetType:36
|vpiInterface:
\_interface: work@l2_fifo_interface (fifo), file:third_party/cores/taiga/l2_arbiter/l2_arbiter.sv, line:126
|vpiDefName:work@l2_fifo_interface
|vpiName:fifo
|vpiModport:
\_modport: (dequeue)
|vpiName:dequeue
|vpiIODecl:
\_io_decl: (valid)
|vpiName:valid
|vpiDirection:1
|vpiExpr:
\_logic_net: (valid), line:30
|vpiIODecl:
\_io_decl: (data_out)
|vpiName:data_out
|vpiDirection:1
|vpiExpr:
\_logic_net: (data_out), line:29
|vpiIODecl:
\_io_decl: (pop)
|vpiName:pop
|vpiDirection:2
|vpiExpr:
\_logic_net: (pop), line:27
|vpiInterface:
\_interface: work@l2_fifo_interface (fifo), file:third_party/cores/taiga/l2_arbiter/l2_arbiter.sv, line:126
|vpiModport:
\_modport: (enqueue)
|vpiName:enqueue
|vpiIODecl:
\_io_decl: (full)
|vpiName:full
|vpiDirection:1
|vpiExpr:
\_logic_net: (full), line:31
|vpiIODecl:
\_io_decl: (empty)
|vpiName:empty
|vpiDirection:1
|vpiExpr:
\_logic_net: (empty), line:32
|vpiIODecl:
\_io_decl: (data_in)
|vpiName:data_in
|vpiDirection:2
|vpiExpr:
\_logic_net: (data_in), line:28
|vpiIODecl:
\_io_decl: (push)
|vpiName:push
|vpiDirection:2
|vpiExpr:
\_logic_net: (push), line:26
|vpiInterface:
\_interface: work@l2_fifo_interface (fifo), file:third_party/cores/taiga/l2_arbiter/l2_arbiter.sv, line:126
|vpiModport:
\_modport: (structure)
|vpiGenScopeArray:
\_gen_scope_array: (genblk1), line:37, parent:input_data_fifo
|vpiName:genblk1
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk2[0].input_data_fifo.genblk1
|vpiGenScope:
\_gen_scope: , parent:genblk1
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk2[0].input_data_fifo.genblk1
|vpiGenScopeArray:
\_gen_scope_array: (genblk1), line:54
|vpiName:genblk1
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk2[0].input_data_fifo.genblk1.genblk1
|vpiGenScope:
\_gen_scope: , parent:genblk1
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk2[0].input_data_fifo.genblk1.genblk1
|vpiNet:
\_logic_net: (write_index), line:58
|vpiName:write_index
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk2[0].input_data_fifo.genblk1.genblk1.write_index
|vpiNetType:36
|vpiRange:
\_range: , line:58
|vpiLeftRange:
\_constant: , line:58
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:58
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (read_index), line:59
|vpiName:read_index
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk2[0].input_data_fifo.genblk1.genblk1.read_index
|vpiNetType:36
|vpiRange:
\_range: , line:59
|vpiLeftRange:
\_constant: , line:59
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:59
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiProcess:
\_always: , line:67
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:67
|vpiCondition:
\_operation: , line:67
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:67
|vpiName:clk
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk2[0].input_data_fifo.genblk1.genblk1.clk
|vpiStmt:
\_begin: , line:67
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk2[0].input_data_fifo.genblk1.genblk1
|vpiStmt:
\_if_else: , line:68
|vpiCondition:
\_ref_obj: (rst), line:68
|vpiName:rst
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk2[0].input_data_fifo.genblk1.genblk1.rst
|vpiStmt:
\_begin: , line:68
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk2[0].input_data_fifo.genblk1.genblk1
|vpiStmt:
\_assignment: , line:69
|vpiOpType:82
|vpiLhs:
\_ref_obj: (read_index), line:69
|vpiName:read_index
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk2[0].input_data_fifo.genblk1.genblk1.read_index
|vpiRhs:
\_constant: , line:69
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiStmt:
\_assignment: , line:70
|vpiOpType:82
|vpiLhs:
\_ref_obj: (write_index), line:70
|vpiName:write_index
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk2[0].input_data_fifo.genblk1.genblk1.write_index
|vpiRhs:
\_constant: , line:70
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiElseStmt:
\_begin: , line:72
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk2[0].input_data_fifo.genblk1.genblk1
|vpiStmt:
\_assignment: , line:73
|vpiOpType:82
|vpiLhs:
\_ref_obj: (read_index), line:73
|vpiName:read_index
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk2[0].input_data_fifo.genblk1.genblk1.read_index
|vpiRhs:
\_operation: , line:73
|vpiOpType:24
|vpiOperand:
\_ref_obj: (read_index), line:73
|vpiName:read_index
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk2[0].input_data_fifo.genblk1.genblk1.read_index
|vpiOperand:
\_ref_obj: (fifo.pop), line:73
|vpiName:fifo.pop
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk2[0].input_data_fifo.genblk1.genblk1.fifo.pop
|vpiStmt:
\_assignment: , line:74
|vpiOpType:82
|vpiLhs:
\_ref_obj: (write_index), line:74
|vpiName:write_index
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk2[0].input_data_fifo.genblk1.genblk1.write_index
|vpiRhs:
\_operation: , line:74
|vpiOpType:24
|vpiOperand:
\_ref_obj: (write_index), line:74
|vpiName:write_index
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk2[0].input_data_fifo.genblk1.genblk1.write_index
|vpiOperand:
\_ref_obj: (fifo.push), line:74
|vpiName:fifo.push
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk2[0].input_data_fifo.genblk1.genblk1.fifo.push
|vpiProcess:
\_always: , line:81
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:81
|vpiCondition:
\_operation: , line:81
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:81
|vpiName:clk
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk2[0].input_data_fifo.genblk1.genblk1.clk
|vpiStmt:
\_begin: , line:81
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk2[0].input_data_fifo.genblk1.genblk1
|vpiStmt:
\_if_stmt: , line:82
|vpiCondition:
\_ref_obj: (fifo.push), line:82
|vpiName:fifo.push
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk2[0].input_data_fifo.genblk1.genblk1.fifo.push
|vpiStmt:
\_assignment: , line:83
|vpiOpType:82
|vpiLhs:
\_bit_select: (lut_ram), line:83
|vpiName:lut_ram
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk2[0].input_data_fifo.genblk1.genblk1.lut_ram
|vpiIndex:
\_ref_obj: (write_index), line:83
|vpiName:write_index
|vpiRhs:
\_ref_obj: (fifo.data_in), line:83
|vpiName:fifo.data_in
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk2[0].input_data_fifo.genblk1.genblk1.fifo.data_in
|vpiProcess:
\_always: , line:86
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:86
|vpiCondition:
\_operation: , line:86
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:86
|vpiName:clk
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk2[0].input_data_fifo.genblk1.genblk1.clk
|vpiStmt:
\_begin: , line:86
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk2[0].input_data_fifo.genblk1.genblk1
|vpiStmt:
\_if_else: , line:87
|vpiCondition:
\_ref_obj: (rst), line:87
|vpiName:rst
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk2[0].input_data_fifo.genblk1.genblk1.rst
|vpiStmt:
\_begin: , line:87
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk2[0].input_data_fifo.genblk1.genblk1
|vpiStmt:
\_assignment: , line:88
|vpiOpType:82
|vpiLhs:
\_bit_select: (count_v), line:88
|vpiName:count_v
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk2[0].input_data_fifo.genblk1.genblk1.count_v
|vpiIndex:
\_constant: , line:88
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiRhs:
\_constant: , line:88
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiStmt:
\_for_stmt: , line:89
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk2[0].input_data_fifo.genblk1.genblk1
|vpiCondition:
\_operation: , line:89
|vpiOpType:21
|vpiOperand:
\_ref_obj: (i), line:89
|vpiName:i
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk2[0].input_data_fifo.genblk1.genblk1.i
|vpiOperand:
\_ref_obj: (FIFO_DEPTH), line:89
|vpiName:FIFO_DEPTH
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk2[0].input_data_fifo.genblk1.genblk1.FIFO_DEPTH
|vpiForInitStmt:
\_assign_stmt:
|vpiRhs:
\_constant: , line:89
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiLhs:
\_int_var: (i), line:89
|vpiName:i
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk2[0].input_data_fifo.genblk1.genblk1.i
|vpiForIncStmt:
\_operation: , line:89
|vpiOpType:62
|vpiOperand:
\_ref_obj: (i), line:89
|vpiName:i
|vpiStmt:
\_assignment: , line:89
|vpiOpType:82
|vpiLhs:
\_bit_select: (count_v), line:89
|vpiName:count_v
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk2[0].input_data_fifo.genblk1.genblk1.count_v
|vpiIndex:
\_ref_obj: (i), line:89
|vpiName:i
|vpiRhs:
\_constant: , line:89
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiElseStmt:
\_if_else: , line:91
|vpiCondition:
\_operation: , line:91
|vpiOpType:28
|vpiOperand:
\_ref_obj: (fifo.push), line:91
|vpiName:fifo.push
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk2[0].input_data_fifo.genblk1.genblk1.fifo.push
|vpiOperand:
\_operation: , line:91
|vpiOpType:4
|vpiOperand:
\_ref_obj: (fifo.pop), line:91
|vpiName:fifo.pop
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk2[0].input_data_fifo.genblk1.genblk1.fifo.pop
|vpiStmt:
\_assignment: , line:92
|vpiOpType:82
|vpiLhs:
\_ref_obj: (count_v), line:92
|vpiName:count_v
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk2[0].input_data_fifo.genblk1.genblk1.count_v
|vpiRhs:
\_operation: , line:92
|vpiOpType:33
|vpiOperand:
\_part_select: , line:92, parent:count_v
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (count_v)
|vpiLeftRange:
\_operation: , line:92
|vpiOpType:11
|vpiOperand:
\_ref_obj: (FIFO_DEPTH), line:92
|vpiName:FIFO_DEPTH
|vpiOperand:
\_constant: , line:92
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:92
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiOperand:
\_constant: , line:92
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiElseStmt:
\_if_stmt: , line:93
|vpiCondition:
\_operation: , line:93
|vpiOpType:28
|vpiOperand:
\_operation: , line:93
|vpiOpType:4
|vpiOperand:
\_ref_obj: (fifo.push), line:93
|vpiName:fifo.push
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk2[0].input_data_fifo.genblk1.genblk1.fifo.push
|vpiOperand:
\_ref_obj: (fifo.pop), line:93
|vpiName:fifo.pop
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk2[0].input_data_fifo.genblk1.genblk1.fifo.pop
|vpiStmt:
\_assignment: , line:94
|vpiOpType:82
|vpiLhs:
\_ref_obj: (count_v), line:94
|vpiName:count_v
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk2[0].input_data_fifo.genblk1.genblk1.count_v
|vpiRhs:
\_operation: , line:94
|vpiOpType:33
|vpiOperand:
\_constant: , line:94
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiOperand:
\_part_select: , line:94, parent:count_v
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (count_v)
|vpiLeftRange:
\_ref_obj: (FIFO_DEPTH), line:94
|vpiName:FIFO_DEPTH
|vpiRightRange:
\_constant: , line:94
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiArrayNet:
\_array_net: (lut_ram), line:56
|vpiName:lut_ram
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk2[0].input_data_fifo.genblk1.genblk1.lut_ram
|vpiSize:4
|vpiNet:
\_logic_net: , parent:lut_ram
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk2[0].input_data_fifo.genblk1.genblk1.lut_ram
|vpiNetType:36
|vpiRange:
\_range: , line:56
|vpiLeftRange:
\_constant: , line:56
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:56
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiRange:
\_range: , line:56
|vpiLeftRange:
\_constant: , line:56
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiRightRange:
\_constant: , line:56
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiArrayNet:
\_array_net: (count_v), line:61
|vpiName:count_v
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk2[0].input_data_fifo.genblk1.genblk1.count_v
|vpiSize:5
|vpiNet:
\_logic_net: , parent:count_v
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk2[0].input_data_fifo.genblk1.genblk1.count_v
|vpiNetType:36
|vpiRange:
\_range: , line:61
|vpiLeftRange:
\_constant: , line:61
|vpiConstType:7
|vpiDecompile:4
|vpiSize:32
|INT:4
|vpiRightRange:
\_constant: , line:61
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiContAssign:
\_cont_assign: , line:65
|vpiRhs:
\_bit_select: (lut_ram), line:65
|vpiName:lut_ram
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk2[0].input_data_fifo.genblk1.genblk1.lut_ram
|vpiIndex:
\_ref_obj: (read_index), line:65
|vpiName:read_index
|vpiLhs:
\_ref_obj: (fifo.data_out), line:65
|vpiName:fifo.data_out
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk2[0].input_data_fifo.genblk1.genblk1.fifo.data_out
|vpiContAssign:
\_cont_assign: , line:78
|vpiRhs:
\_bit_select: (count_v), line:78
|vpiName:count_v
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk2[0].input_data_fifo.genblk1.genblk1.count_v
|vpiIndex:
\_ref_obj: (FIFO_DEPTH), line:78
|vpiName:FIFO_DEPTH
|vpiLhs:
\_ref_obj: (fifo.full), line:78
|vpiName:fifo.full
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk2[0].input_data_fifo.genblk1.genblk1.fifo.full
|vpiContAssign:
\_cont_assign: , line:79
|vpiRhs:
\_operation: , line:79
|vpiOpType:4
|vpiOperand:
\_bit_select: (count_v), line:79
|vpiName:count_v
|vpiIndex:
\_constant: , line:79
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiLhs:
\_ref_obj: (fifo.valid), line:79
|vpiName:fifo.valid
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk2[0].input_data_fifo.genblk1.genblk1.fifo.valid
|vpiNet:
\_logic_net: (clk), line:25, parent:input_data_fifo
|vpiNet:
\_logic_net: (wr_clk), line:26, parent:input_data_fifo
|vpiNet:
\_logic_net: (rd_clk), line:27, parent:input_data_fifo
|vpiNet:
\_logic_net: (rst), line:29, parent:input_data_fifo
|vpiNet:
\_logic_net: (fifo), line:30, parent:input_data_fifo
|vpiName:fifo
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk2[0].input_data_fifo.fifo
|vpiParameter:
\_parameter: (ASYNC), line:23
|vpiName:ASYNC
|INT:0
|vpiParameter:
\_parameter: (DATA_WIDTH), line:126
|vpiName:DATA_WIDTH
|INT:32
|vpiParameter:
\_parameter: (FIFO_DEPTH), line:126
|vpiName:FIFO_DEPTH
|INT:4
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (L2_DATA_ATTRIBUTES_FIFO_DEPTH), line:41
|vpiName:L2_DATA_ATTRIBUTES_FIFO_DEPTH
|INT:16
|vpiParameter:
\_parameter: (L2_ID_W), line:46
|vpiName:L2_ID_W
|INT:3
|vpiParameter:
\_parameter: (L2_INPUT_FIFO_DEPTHS), line:34
|vpiName:L2_INPUT_FIFO_DEPTHS
|INT:4
|vpiParameter:
\_parameter: (L2_INVALIDATION_FIFO_DEPTHS), line:35
|vpiName:L2_INVALIDATION_FIFO_DEPTHS
|INT:4
|vpiParameter:
\_parameter: (L2_MEM_ADDR_FIFO_DEPTH), line:39
|vpiName:L2_MEM_ADDR_FIFO_DEPTH
|INT:8
|vpiParameter:
\_parameter: (L2_NUM_PORTS), line:26
|vpiName:L2_NUM_PORTS
|INT:2
|vpiParameter:
\_parameter: (L2_READ_RETURN_FIFO_DEPTHS), line:36
|vpiName:L2_READ_RETURN_FIFO_DEPTHS
|INT:1
|vpiParameter:
\_parameter: (L2_SUB_ID_W), line:27
|vpiName:L2_SUB_ID_W
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiParameter:
\_parameter: (i), line:118
|vpiName:i
|INT:0
|vpiGenScopeArray:
\_gen_scope_array: (genblk2[1]), line:118, parent:l2_arb
|vpiName:genblk2[1]
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk2[1]
|vpiGenScope:
\_gen_scope: , parent:genblk2[1]
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk2[1]
|vpiContAssign:
\_cont_assign: , line:120
|vpiRhs:
\_bit_select: (request.wr_data_push), line:120
|vpiName:request.wr_data_push
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk2[1].request.wr_data_push
|vpiIndex:
\_ref_obj: (i), line:120
|vpiName:i
|vpiLhs:
\_ref_obj: (input_data_fifos[i].push), line:120
|vpiName:input_data_fifos[i].push
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk2[1].input_data_fifos[i].push
|vpiContAssign:
\_cont_assign: , line:121
|vpiRhs:
\_bit_select: (request.wr_data), line:121
|vpiName:request.wr_data
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk2[1].request.wr_data
|vpiIndex:
\_ref_obj: (i), line:121
|vpiName:i
|vpiLhs:
\_ref_obj: (input_data_fifos[i].data_in), line:121
|vpiName:input_data_fifos[i].data_in
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk2[1].input_data_fifos[i].data_in
|vpiContAssign:
\_cont_assign: , line:123
|vpiRhs:
\_bit_select: (input_data_fifos.full), line:123
|vpiName:input_data_fifos.full
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk2[1].input_data_fifos.full
|vpiIndex:
\_ref_obj: (i), line:123
|vpiName:i
|vpiLhs:
\_ref_obj: (request[i].data_full), line:123
|vpiName:request[i].data_full
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk2[1].request[i].data_full
|vpiContAssign:
\_cont_assign: , line:129
|vpiRhs:
\_operation: , line:129
|vpiOpType:26
|vpiOperand:
\_operation: , line:129
|vpiOpType:26
|vpiOperand:
\_ref_obj: (data_attributes.valid), line:129
|vpiName:data_attributes.valid
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk2[1].data_attributes.valid
|vpiOperand:
\_operation: , line:129
|vpiOpType:14
|vpiOperand:
\_ref_obj: (current_attr.id), line:129
|vpiName:current_attr.id
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk2[1].current_attr.id
|vpiOperand:
\_ref_obj: (i), line:129
|vpiName:i
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk2[1].i
|vpiOperand:
\_operation: , line:129
|vpiOpType:4
|vpiOperand:
\_ref_obj: (mem_data_fifo.full), line:129
|vpiName:mem_data_fifo.full
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk2[1].mem_data_fifo.full
|vpiLhs:
\_ref_obj: (input_data_fifos[i].pop), line:129
|vpiName:input_data_fifos[i].pop
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk2[1].input_data_fifos[i].pop
|vpiContAssign:
\_cont_assign: , line:131
|vpiRhs:
\_bit_select: (input_data_fifos.data_out), line:131
|vpiName:input_data_fifos.data_out
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk2[1].input_data_fifos.data_out
|vpiIndex:
\_ref_obj: (i), line:131
|vpiName:i
|vpiLhs:
\_bit_select: (input_data), line:131
|vpiName:input_data
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk2[1].input_data
|vpiIndex:
\_ref_obj: (i), line:131
|vpiName:i
|vpiModule:
\_module: work@l2_fifo (input_data_fifo), file:third_party/cores/taiga/l2_arbiter/l2_arbiter.sv, line:126
|vpiDefName:work@l2_fifo
|vpiName:input_data_fifo
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk2[1].input_data_fifo
|vpiPort:
\_port: (clk), line:25, parent:input_data_fifo
|vpiName:clk
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (clk), line:126
|vpiName:clk
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (clk), line:25, parent:input_data_fifo
|vpiName:clk
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk2[1].input_data_fifo.clk
|vpiNetType:36
|vpiPort:
\_port: (wr_clk), line:26, parent:input_data_fifo
|vpiName:wr_clk
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (wr_clk), line:126
|vpiName:wr_clk
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (wr_clk), line:26, parent:input_data_fifo
|vpiName:wr_clk
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk2[1].input_data_fifo.wr_clk
|vpiNetType:36
|vpiPort:
\_port: (rd_clk), line:27, parent:input_data_fifo
|vpiName:rd_clk
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (rd_clk), line:126
|vpiName:rd_clk
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (rd_clk), line:27, parent:input_data_fifo
|vpiName:rd_clk
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk2[1].input_data_fifo.rd_clk
|vpiNetType:36
|vpiPort:
\_port: (rst), line:29, parent:input_data_fifo
|vpiName:rst
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (rst), line:126
|vpiName:rst
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (rst), line:29, parent:input_data_fifo
|vpiName:rst
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk2[1].input_data_fifo.rst
|vpiNetType:36
|vpiPort:
\_port: (fifo), line:30, parent:input_data_fifo
|vpiName:fifo
|vpiDirection:5
|vpiHighConn:
\_ref_obj: (fifo), line:126
|vpiName:fifo
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_modport: (structure)
|vpiName:structure
|vpiIODecl:
\_io_decl: (push)
|vpiName:push
|vpiDirection:1
|vpiExpr:
\_logic_net: (push), line:26
|vpiName:push
|vpiNetType:36
|vpiIODecl:
\_io_decl: (pop)
|vpiName:pop
|vpiDirection:1
|vpiExpr:
\_logic_net: (pop), line:27
|vpiName:pop
|vpiNetType:36
|vpiIODecl:
\_io_decl: (data_in)
|vpiName:data_in
|vpiDirection:1
|vpiExpr:
\_logic_net: (data_in), line:28
|vpiName:data_in
|vpiNetType:36
|vpiRange:
\_range: , line:28
|vpiLeftRange:
\_constant: , line:28
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:28
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (data_out)
|vpiName:data_out
|vpiDirection:2
|vpiExpr:
\_logic_net: (data_out), line:29
|vpiName:data_out
|vpiNetType:36
|vpiRange:
\_range: , line:29
|vpiLeftRange:
\_constant: , line:29
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:29
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (valid)
|vpiName:valid
|vpiDirection:2
|vpiExpr:
\_logic_net: (valid), line:30
|vpiName:valid
|vpiNetType:36
|vpiIODecl:
\_io_decl: (full)
|vpiName:full
|vpiDirection:2
|vpiExpr:
\_logic_net: (full), line:31
|vpiName:full
|vpiNetType:36
|vpiIODecl:
\_io_decl: (empty)
|vpiName:empty
|vpiDirection:2
|vpiExpr:
\_logic_net: (empty), line:32
|vpiName:empty
|vpiNetType:36
|vpiInterface:
\_interface: work@l2_fifo_interface (fifo), file:third_party/cores/taiga/l2_arbiter/l2_arbiter.sv, line:126
|vpiDefName:work@l2_fifo_interface
|vpiName:fifo
|vpiModport:
\_modport: (dequeue)
|vpiName:dequeue
|vpiIODecl:
\_io_decl: (valid)
|vpiName:valid
|vpiDirection:1
|vpiExpr:
\_logic_net: (valid), line:30
|vpiIODecl:
\_io_decl: (data_out)
|vpiName:data_out
|vpiDirection:1
|vpiExpr:
\_logic_net: (data_out), line:29
|vpiIODecl:
\_io_decl: (pop)
|vpiName:pop
|vpiDirection:2
|vpiExpr:
\_logic_net: (pop), line:27
|vpiInterface:
\_interface: work@l2_fifo_interface (fifo), file:third_party/cores/taiga/l2_arbiter/l2_arbiter.sv, line:126
|vpiModport:
\_modport: (enqueue)
|vpiName:enqueue
|vpiIODecl:
\_io_decl: (full)
|vpiName:full
|vpiDirection:1
|vpiExpr:
\_logic_net: (full), line:31
|vpiIODecl:
\_io_decl: (empty)
|vpiName:empty
|vpiDirection:1
|vpiExpr:
\_logic_net: (empty), line:32
|vpiIODecl:
\_io_decl: (data_in)
|vpiName:data_in
|vpiDirection:2
|vpiExpr:
\_logic_net: (data_in), line:28
|vpiIODecl:
\_io_decl: (push)
|vpiName:push
|vpiDirection:2
|vpiExpr:
\_logic_net: (push), line:26
|vpiInterface:
\_interface: work@l2_fifo_interface (fifo), file:third_party/cores/taiga/l2_arbiter/l2_arbiter.sv, line:126
|vpiModport:
\_modport: (structure)
|vpiGenScopeArray:
\_gen_scope_array: (genblk1), line:37, parent:input_data_fifo
|vpiName:genblk1
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk2[1].input_data_fifo.genblk1
|vpiGenScope:
\_gen_scope: , parent:genblk1
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk2[1].input_data_fifo.genblk1
|vpiGenScopeArray:
\_gen_scope_array: (genblk1), line:54
|vpiName:genblk1
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk2[1].input_data_fifo.genblk1.genblk1
|vpiGenScope:
\_gen_scope: , parent:genblk1
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk2[1].input_data_fifo.genblk1.genblk1
|vpiNet:
\_logic_net: (write_index), line:58
|vpiName:write_index
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk2[1].input_data_fifo.genblk1.genblk1.write_index
|vpiNetType:36
|vpiRange:
\_range: , line:58
|vpiLeftRange:
\_constant: , line:58
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:58
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (read_index), line:59
|vpiName:read_index
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk2[1].input_data_fifo.genblk1.genblk1.read_index
|vpiNetType:36
|vpiRange:
\_range: , line:59
|vpiLeftRange:
\_constant: , line:59
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:59
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiProcess:
\_always: , line:67
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:67
|vpiCondition:
\_operation: , line:67
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:67
|vpiName:clk
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk2[1].input_data_fifo.genblk1.genblk1.clk
|vpiStmt:
\_begin: , line:67
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk2[1].input_data_fifo.genblk1.genblk1
|vpiStmt:
\_if_else: , line:68
|vpiCondition:
\_ref_obj: (rst), line:68
|vpiName:rst
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk2[1].input_data_fifo.genblk1.genblk1.rst
|vpiStmt:
\_begin: , line:68
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk2[1].input_data_fifo.genblk1.genblk1
|vpiStmt:
\_assignment: , line:69
|vpiOpType:82
|vpiLhs:
\_ref_obj: (read_index), line:69
|vpiName:read_index
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk2[1].input_data_fifo.genblk1.genblk1.read_index
|vpiRhs:
\_constant: , line:69
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiStmt:
\_assignment: , line:70
|vpiOpType:82
|vpiLhs:
\_ref_obj: (write_index), line:70
|vpiName:write_index
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk2[1].input_data_fifo.genblk1.genblk1.write_index
|vpiRhs:
\_constant: , line:70
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiElseStmt:
\_begin: , line:72
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk2[1].input_data_fifo.genblk1.genblk1
|vpiStmt:
\_assignment: , line:73
|vpiOpType:82
|vpiLhs:
\_ref_obj: (read_index), line:73
|vpiName:read_index
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk2[1].input_data_fifo.genblk1.genblk1.read_index
|vpiRhs:
\_operation: , line:73
|vpiOpType:24
|vpiOperand:
\_ref_obj: (read_index), line:73
|vpiName:read_index
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk2[1].input_data_fifo.genblk1.genblk1.read_index
|vpiOperand:
\_ref_obj: (fifo.pop), line:73
|vpiName:fifo.pop
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk2[1].input_data_fifo.genblk1.genblk1.fifo.pop
|vpiStmt:
\_assignment: , line:74
|vpiOpType:82
|vpiLhs:
\_ref_obj: (write_index), line:74
|vpiName:write_index
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk2[1].input_data_fifo.genblk1.genblk1.write_index
|vpiRhs:
\_operation: , line:74
|vpiOpType:24
|vpiOperand:
\_ref_obj: (write_index), line:74
|vpiName:write_index
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk2[1].input_data_fifo.genblk1.genblk1.write_index
|vpiOperand:
\_ref_obj: (fifo.push), line:74
|vpiName:fifo.push
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk2[1].input_data_fifo.genblk1.genblk1.fifo.push
|vpiProcess:
\_always: , line:81
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:81
|vpiCondition:
\_operation: , line:81
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:81
|vpiName:clk
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk2[1].input_data_fifo.genblk1.genblk1.clk
|vpiStmt:
\_begin: , line:81
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk2[1].input_data_fifo.genblk1.genblk1
|vpiStmt:
\_if_stmt: , line:82
|vpiCondition:
\_ref_obj: (fifo.push), line:82
|vpiName:fifo.push
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk2[1].input_data_fifo.genblk1.genblk1.fifo.push
|vpiStmt:
\_assignment: , line:83
|vpiOpType:82
|vpiLhs:
\_bit_select: (lut_ram), line:83
|vpiName:lut_ram
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk2[1].input_data_fifo.genblk1.genblk1.lut_ram
|vpiIndex:
\_ref_obj: (write_index), line:83
|vpiName:write_index
|vpiRhs:
\_ref_obj: (fifo.data_in), line:83
|vpiName:fifo.data_in
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk2[1].input_data_fifo.genblk1.genblk1.fifo.data_in
|vpiProcess:
\_always: , line:86
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:86
|vpiCondition:
\_operation: , line:86
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:86
|vpiName:clk
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk2[1].input_data_fifo.genblk1.genblk1.clk
|vpiStmt:
\_begin: , line:86
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk2[1].input_data_fifo.genblk1.genblk1
|vpiStmt:
\_if_else: , line:87
|vpiCondition:
\_ref_obj: (rst), line:87
|vpiName:rst
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk2[1].input_data_fifo.genblk1.genblk1.rst
|vpiStmt:
\_begin: , line:87
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk2[1].input_data_fifo.genblk1.genblk1
|vpiStmt:
\_assignment: , line:88
|vpiOpType:82
|vpiLhs:
\_bit_select: (count_v), line:88
|vpiName:count_v
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk2[1].input_data_fifo.genblk1.genblk1.count_v
|vpiIndex:
\_constant: , line:88
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiRhs:
\_constant: , line:88
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiStmt:
\_for_stmt: , line:89
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk2[1].input_data_fifo.genblk1.genblk1
|vpiCondition:
\_operation: , line:89
|vpiOpType:21
|vpiOperand:
\_ref_obj: (i), line:89
|vpiName:i
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk2[1].input_data_fifo.genblk1.genblk1.i
|vpiOperand:
\_ref_obj: (FIFO_DEPTH), line:89
|vpiName:FIFO_DEPTH
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk2[1].input_data_fifo.genblk1.genblk1.FIFO_DEPTH
|vpiForInitStmt:
\_assign_stmt:
|vpiRhs:
\_constant: , line:89
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiLhs:
\_int_var: (i), line:89
|vpiName:i
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk2[1].input_data_fifo.genblk1.genblk1.i
|vpiForIncStmt:
\_operation: , line:89
|vpiOpType:62
|vpiOperand:
\_ref_obj: (i), line:89
|vpiName:i
|vpiStmt:
\_assignment: , line:89
|vpiOpType:82
|vpiLhs:
\_bit_select: (count_v), line:89
|vpiName:count_v
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk2[1].input_data_fifo.genblk1.genblk1.count_v
|vpiIndex:
\_ref_obj: (i), line:89
|vpiName:i
|vpiRhs:
\_constant: , line:89
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiElseStmt:
\_if_else: , line:91
|vpiCondition:
\_operation: , line:91
|vpiOpType:28
|vpiOperand:
\_ref_obj: (fifo.push), line:91
|vpiName:fifo.push
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk2[1].input_data_fifo.genblk1.genblk1.fifo.push
|vpiOperand:
\_operation: , line:91
|vpiOpType:4
|vpiOperand:
\_ref_obj: (fifo.pop), line:91
|vpiName:fifo.pop
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk2[1].input_data_fifo.genblk1.genblk1.fifo.pop
|vpiStmt:
\_assignment: , line:92
|vpiOpType:82
|vpiLhs:
\_ref_obj: (count_v), line:92
|vpiName:count_v
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk2[1].input_data_fifo.genblk1.genblk1.count_v
|vpiRhs:
\_operation: , line:92
|vpiOpType:33
|vpiOperand:
\_part_select: , line:92, parent:count_v
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (count_v)
|vpiLeftRange:
\_operation: , line:92
|vpiOpType:11
|vpiOperand:
\_ref_obj: (FIFO_DEPTH), line:92
|vpiName:FIFO_DEPTH
|vpiOperand:
\_constant: , line:92
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:92
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiOperand:
\_constant: , line:92
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiElseStmt:
\_if_stmt: , line:93
|vpiCondition:
\_operation: , line:93
|vpiOpType:28
|vpiOperand:
\_operation: , line:93
|vpiOpType:4
|vpiOperand:
\_ref_obj: (fifo.push), line:93
|vpiName:fifo.push
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk2[1].input_data_fifo.genblk1.genblk1.fifo.push
|vpiOperand:
\_ref_obj: (fifo.pop), line:93
|vpiName:fifo.pop
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk2[1].input_data_fifo.genblk1.genblk1.fifo.pop
|vpiStmt:
\_assignment: , line:94
|vpiOpType:82
|vpiLhs:
\_ref_obj: (count_v), line:94
|vpiName:count_v
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk2[1].input_data_fifo.genblk1.genblk1.count_v
|vpiRhs:
\_operation: , line:94
|vpiOpType:33
|vpiOperand:
\_constant: , line:94
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiOperand:
\_part_select: , line:94, parent:count_v
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (count_v)
|vpiLeftRange:
\_ref_obj: (FIFO_DEPTH), line:94
|vpiName:FIFO_DEPTH
|vpiRightRange:
\_constant: , line:94
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiArrayNet:
\_array_net: (lut_ram), line:56
|vpiName:lut_ram
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk2[1].input_data_fifo.genblk1.genblk1.lut_ram
|vpiSize:4
|vpiNet:
\_logic_net: , parent:lut_ram
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk2[1].input_data_fifo.genblk1.genblk1.lut_ram
|vpiNetType:36
|vpiRange:
\_range: , line:56
|vpiLeftRange:
\_constant: , line:56
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:56
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiRange:
\_range: , line:56
|vpiLeftRange:
\_constant: , line:56
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiRightRange:
\_constant: , line:56
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiArrayNet:
\_array_net: (count_v), line:61
|vpiName:count_v
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk2[1].input_data_fifo.genblk1.genblk1.count_v
|vpiSize:5
|vpiNet:
\_logic_net: , parent:count_v
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk2[1].input_data_fifo.genblk1.genblk1.count_v
|vpiNetType:36
|vpiRange:
\_range: , line:61
|vpiLeftRange:
\_constant: , line:61
|vpiConstType:7
|vpiDecompile:4
|vpiSize:32
|INT:4
|vpiRightRange:
\_constant: , line:61
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiContAssign:
\_cont_assign: , line:65
|vpiRhs:
\_bit_select: (lut_ram), line:65
|vpiName:lut_ram
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk2[1].input_data_fifo.genblk1.genblk1.lut_ram
|vpiIndex:
\_ref_obj: (read_index), line:65
|vpiName:read_index
|vpiLhs:
\_ref_obj: (fifo.data_out), line:65
|vpiName:fifo.data_out
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk2[1].input_data_fifo.genblk1.genblk1.fifo.data_out
|vpiContAssign:
\_cont_assign: , line:78
|vpiRhs:
\_bit_select: (count_v), line:78
|vpiName:count_v
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk2[1].input_data_fifo.genblk1.genblk1.count_v
|vpiIndex:
\_ref_obj: (FIFO_DEPTH), line:78
|vpiName:FIFO_DEPTH
|vpiLhs:
\_ref_obj: (fifo.full), line:78
|vpiName:fifo.full
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk2[1].input_data_fifo.genblk1.genblk1.fifo.full
|vpiContAssign:
\_cont_assign: , line:79
|vpiRhs:
\_operation: , line:79
|vpiOpType:4
|vpiOperand:
\_bit_select: (count_v), line:79
|vpiName:count_v
|vpiIndex:
\_constant: , line:79
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiLhs:
\_ref_obj: (fifo.valid), line:79
|vpiName:fifo.valid
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk2[1].input_data_fifo.genblk1.genblk1.fifo.valid
|vpiNet:
\_logic_net: (clk), line:25, parent:input_data_fifo
|vpiNet:
\_logic_net: (wr_clk), line:26, parent:input_data_fifo
|vpiNet:
\_logic_net: (rd_clk), line:27, parent:input_data_fifo
|vpiNet:
\_logic_net: (rst), line:29, parent:input_data_fifo
|vpiNet:
\_logic_net: (fifo), line:30, parent:input_data_fifo
|vpiName:fifo
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk2[1].input_data_fifo.fifo
|vpiParameter:
\_parameter: (ASYNC), line:23
|vpiName:ASYNC
|INT:0
|vpiParameter:
\_parameter: (DATA_WIDTH), line:126
|vpiName:DATA_WIDTH
|INT:32
|vpiParameter:
\_parameter: (FIFO_DEPTH), line:126
|vpiName:FIFO_DEPTH
|INT:4
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (L2_DATA_ATTRIBUTES_FIFO_DEPTH), line:41
|vpiName:L2_DATA_ATTRIBUTES_FIFO_DEPTH
|INT:16
|vpiParameter:
\_parameter: (L2_ID_W), line:46
|vpiName:L2_ID_W
|INT:3
|vpiParameter:
\_parameter: (L2_INPUT_FIFO_DEPTHS), line:34
|vpiName:L2_INPUT_FIFO_DEPTHS
|INT:4
|vpiParameter:
\_parameter: (L2_INVALIDATION_FIFO_DEPTHS), line:35
|vpiName:L2_INVALIDATION_FIFO_DEPTHS
|INT:4
|vpiParameter:
\_parameter: (L2_MEM_ADDR_FIFO_DEPTH), line:39
|vpiName:L2_MEM_ADDR_FIFO_DEPTH
|INT:8
|vpiParameter:
\_parameter: (L2_NUM_PORTS), line:26
|vpiName:L2_NUM_PORTS
|INT:2
|vpiParameter:
\_parameter: (L2_READ_RETURN_FIFO_DEPTHS), line:36
|vpiName:L2_READ_RETURN_FIFO_DEPTHS
|INT:1
|vpiParameter:
\_parameter: (L2_SUB_ID_W), line:27
|vpiName:L2_SUB_ID_W
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiParameter:
\_parameter: (i), line:118
|vpiName:i
|INT:1
|vpiGenScopeArray:
\_gen_scope_array: (genblk3[0]), line:202, parent:l2_arb
|vpiName:genblk3[0]
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk3[0]
|vpiGenScope:
\_gen_scope: , parent:genblk3[0]
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk3[0]
|vpiProcess:
\_always: , line:203
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:203
|vpiCondition:
\_operation: , line:203
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:203
|vpiName:clk
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk3[0].clk
|vpiStmt:
\_begin: , line:203
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk3[0]
|vpiStmt:
\_if_else: , line:204
|vpiCondition:
\_ref_obj: (rst), line:204
|vpiName:rst
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk3[0].rst
|vpiStmt:
\_begin: , line:204
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk3[0]
|vpiStmt:
\_assignment: , line:205
|vpiOpType:82
|vpiLhs:
\_ref_obj: (request[i].con_result), line:205
|vpiName:request[i].con_result
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk3[0].request[i].con_result
|vpiRhs:
\_constant: , line:205
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiStmt:
\_assignment: , line:206
|vpiOpType:82
|vpiLhs:
\_ref_obj: (request[i].con_valid), line:206
|vpiName:request[i].con_valid
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk3[0].request[i].con_valid
|vpiRhs:
\_constant: , line:206
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiElseStmt:
\_begin: , line:208
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk3[0]
|vpiStmt:
\_assignment: , line:209
|vpiOpType:82
|vpiLhs:
\_ref_obj: (request[i].con_result), line:209
|vpiName:request[i].con_result
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk3[0].request[i].con_result
|vpiRhs:
\_operation: , line:209
|vpiOpType:4
|vpiOperand:
\_ref_obj: (mem.abort), line:209
|vpiName:mem.abort
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk3[0].mem.abort
|vpiStmt:
\_assignment: , line:210
|vpiOpType:82
|vpiLhs:
\_ref_obj: (request[i].con_valid), line:210
|vpiName:request[i].con_valid
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk3[0].request[i].con_valid
|vpiRhs:
\_operation: , line:210
|vpiOpType:28
|vpiOperand:
\_operation: , line:210
|vpiOpType:28
|vpiOperand:
\_ref_obj: (reserv_sc), line:210
|vpiName:reserv_sc
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk3[0].reserv_sc
|vpiOperand:
\_ref_obj: (reserv_valid), line:210
|vpiName:reserv_valid
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk3[0].reserv_valid
|vpiOperand:
\_bit_select: (reserv_id_v), line:210
|vpiName:reserv_id_v
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk3[0].reserv_id_v
|vpiIndex:
\_ref_obj: (i), line:210
|vpiName:i
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk3[0].i
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (L2_DATA_ATTRIBUTES_FIFO_DEPTH), line:41
|vpiName:L2_DATA_ATTRIBUTES_FIFO_DEPTH
|INT:16
|vpiParameter:
\_parameter: (L2_ID_W), line:46
|vpiName:L2_ID_W
|INT:3
|vpiParameter:
\_parameter: (L2_INPUT_FIFO_DEPTHS), line:34
|vpiName:L2_INPUT_FIFO_DEPTHS
|INT:4
|vpiParameter:
\_parameter: (L2_INVALIDATION_FIFO_DEPTHS), line:35
|vpiName:L2_INVALIDATION_FIFO_DEPTHS
|INT:4
|vpiParameter:
\_parameter: (L2_MEM_ADDR_FIFO_DEPTH), line:39
|vpiName:L2_MEM_ADDR_FIFO_DEPTH
|INT:8
|vpiParameter:
\_parameter: (L2_NUM_PORTS), line:26
|vpiName:L2_NUM_PORTS
|INT:2
|vpiParameter:
\_parameter: (L2_READ_RETURN_FIFO_DEPTHS), line:36
|vpiName:L2_READ_RETURN_FIFO_DEPTHS
|INT:1
|vpiParameter:
\_parameter: (L2_SUB_ID_W), line:27
|vpiName:L2_SUB_ID_W
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiParameter:
\_parameter: (i), line:202
|vpiName:i
|INT:0
|vpiGenScopeArray:
\_gen_scope_array: (genblk3[1]), line:202, parent:l2_arb
|vpiName:genblk3[1]
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk3[1]
|vpiGenScope:
\_gen_scope: , parent:genblk3[1]
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk3[1]
|vpiProcess:
\_always: , line:203
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:203
|vpiCondition:
\_operation: , line:203
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:203
|vpiName:clk
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk3[1].clk
|vpiStmt:
\_begin: , line:203
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk3[1]
|vpiStmt:
\_if_else: , line:204
|vpiCondition:
\_ref_obj: (rst), line:204
|vpiName:rst
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk3[1].rst
|vpiStmt:
\_begin: , line:204
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk3[1]
|vpiStmt:
\_assignment: , line:205
|vpiOpType:82
|vpiLhs:
\_ref_obj: (request[i].con_result), line:205
|vpiName:request[i].con_result
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk3[1].request[i].con_result
|vpiRhs:
\_constant: , line:205
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiStmt:
\_assignment: , line:206
|vpiOpType:82
|vpiLhs:
\_ref_obj: (request[i].con_valid), line:206
|vpiName:request[i].con_valid
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk3[1].request[i].con_valid
|vpiRhs:
\_constant: , line:206
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiElseStmt:
\_begin: , line:208
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk3[1]
|vpiStmt:
\_assignment: , line:209
|vpiOpType:82
|vpiLhs:
\_ref_obj: (request[i].con_result), line:209
|vpiName:request[i].con_result
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk3[1].request[i].con_result
|vpiRhs:
\_operation: , line:209
|vpiOpType:4
|vpiOperand:
\_ref_obj: (mem.abort), line:209
|vpiName:mem.abort
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk3[1].mem.abort
|vpiStmt:
\_assignment: , line:210
|vpiOpType:82
|vpiLhs:
\_ref_obj: (request[i].con_valid), line:210
|vpiName:request[i].con_valid
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk3[1].request[i].con_valid
|vpiRhs:
\_operation: , line:210
|vpiOpType:28
|vpiOperand:
\_operation: , line:210
|vpiOpType:28
|vpiOperand:
\_ref_obj: (reserv_sc), line:210
|vpiName:reserv_sc
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk3[1].reserv_sc
|vpiOperand:
\_ref_obj: (reserv_valid), line:210
|vpiName:reserv_valid
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk3[1].reserv_valid
|vpiOperand:
\_bit_select: (reserv_id_v), line:210
|vpiName:reserv_id_v
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk3[1].reserv_id_v
|vpiIndex:
\_ref_obj: (i), line:210
|vpiName:i
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk3[1].i
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (L2_DATA_ATTRIBUTES_FIFO_DEPTH), line:41
|vpiName:L2_DATA_ATTRIBUTES_FIFO_DEPTH
|INT:16
|vpiParameter:
\_parameter: (L2_ID_W), line:46
|vpiName:L2_ID_W
|INT:3
|vpiParameter:
\_parameter: (L2_INPUT_FIFO_DEPTHS), line:34
|vpiName:L2_INPUT_FIFO_DEPTHS
|INT:4
|vpiParameter:
\_parameter: (L2_INVALIDATION_FIFO_DEPTHS), line:35
|vpiName:L2_INVALIDATION_FIFO_DEPTHS
|INT:4
|vpiParameter:
\_parameter: (L2_MEM_ADDR_FIFO_DEPTH), line:39
|vpiName:L2_MEM_ADDR_FIFO_DEPTH
|INT:8
|vpiParameter:
\_parameter: (L2_NUM_PORTS), line:26
|vpiName:L2_NUM_PORTS
|INT:2
|vpiParameter:
\_parameter: (L2_READ_RETURN_FIFO_DEPTHS), line:36
|vpiName:L2_READ_RETURN_FIFO_DEPTHS
|INT:1
|vpiParameter:
\_parameter: (L2_SUB_ID_W), line:27
|vpiName:L2_SUB_ID_W
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiParameter:
\_parameter: (i), line:202
|vpiName:i
|INT:1
|vpiGenScopeArray:
\_gen_scope_array: (genblk4[0]), line:218, parent:l2_arb
|vpiName:genblk4[0]
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk4[0]
|vpiGenScope:
\_gen_scope: , parent:genblk4[0]
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk4[0]
|vpiContAssign:
\_cont_assign: , line:220
|vpiRhs:
\_bit_select: (request.inv_ack), line:220
|vpiName:request.inv_ack
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk4[0].request.inv_ack
|vpiIndex:
\_ref_obj: (i), line:220
|vpiName:i
|vpiLhs:
\_ref_obj: (inv_response_fifos[i].pop), line:220
|vpiName:inv_response_fifos[i].pop
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk4[0].inv_response_fifos[i].pop
|vpiContAssign:
\_cont_assign: , line:221
|vpiRhs:
\_bit_select: (inv_response_fifos.data_out), line:221
|vpiName:inv_response_fifos.data_out
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk4[0].inv_response_fifos.data_out
|vpiIndex:
\_ref_obj: (i), line:221
|vpiName:i
|vpiLhs:
\_ref_obj: (request[i].inv_addr), line:221
|vpiName:request[i].inv_addr
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk4[0].request[i].inv_addr
|vpiContAssign:
\_cont_assign: , line:222
|vpiRhs:
\_bit_select: (inv_response_fifos.valid), line:222
|vpiName:inv_response_fifos.valid
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk4[0].inv_response_fifos.valid
|vpiIndex:
\_ref_obj: (i), line:222
|vpiName:i
|vpiLhs:
\_ref_obj: (request[i].inv_valid), line:222
|vpiName:request[i].inv_valid
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk4[0].request[i].inv_valid
|vpiContAssign:
\_cont_assign: , line:227
|vpiRhs:
\_operation: , line:227
|vpiOpType:28
|vpiOperand:
\_operation: , line:227
|vpiOpType:28
|vpiOperand:
\_ref_obj: (reserv_valid), line:227
|vpiName:reserv_valid
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk4[0].reserv_valid
|vpiOperand:
\_ref_obj: (reserv_store), line:227
|vpiName:reserv_store
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk4[0].reserv_store
|vpiOperand:
\_operation: , line:227
|vpiOpType:4
|vpiOperand:
\_bit_select: (reserv_id_v), line:227
|vpiName:reserv_id_v
|vpiIndex:
\_ref_obj: (i), line:227
|vpiName:i
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk4[0].i
|vpiLhs:
\_ref_obj: (inv_response_fifos[i].push), line:227
|vpiName:inv_response_fifos[i].push
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk4[0].inv_response_fifos[i].push
|vpiContAssign:
\_cont_assign: , line:228
|vpiRhs:
\_bit_select: (requests.addr), line:228
|vpiName:requests.addr
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk4[0].requests.addr
|vpiIndex:
\_ref_obj: (i), line:228
|vpiName:i
|vpiLhs:
\_ref_obj: (inv_response_fifos[i].data_in), line:228
|vpiName:inv_response_fifos[i].data_in
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk4[0].inv_response_fifos[i].data_in
|vpiModule:
\_module: work@l2_fifo (inv_response_fifo), file:third_party/cores/taiga/l2_arbiter/l2_arbiter.sv, line:225
|vpiDefName:work@l2_fifo
|vpiName:inv_response_fifo
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk4[0].inv_response_fifo
|vpiPort:
\_port: (clk), line:25, parent:inv_response_fifo
|vpiName:clk
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (clk), line:225
|vpiName:clk
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (clk), line:25, parent:inv_response_fifo
|vpiName:clk
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk4[0].inv_response_fifo.clk
|vpiNetType:36
|vpiPort:
\_port: (wr_clk), line:26, parent:inv_response_fifo
|vpiName:wr_clk
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (wr_clk), line:225
|vpiName:wr_clk
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (wr_clk), line:26, parent:inv_response_fifo
|vpiName:wr_clk
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk4[0].inv_response_fifo.wr_clk
|vpiNetType:36
|vpiPort:
\_port: (rd_clk), line:27, parent:inv_response_fifo
|vpiName:rd_clk
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (rd_clk), line:225
|vpiName:rd_clk
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (rd_clk), line:27, parent:inv_response_fifo
|vpiName:rd_clk
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk4[0].inv_response_fifo.rd_clk
|vpiNetType:36
|vpiPort:
\_port: (rst), line:29, parent:inv_response_fifo
|vpiName:rst
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (rst), line:225
|vpiName:rst
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (rst), line:29, parent:inv_response_fifo
|vpiName:rst
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk4[0].inv_response_fifo.rst
|vpiNetType:36
|vpiPort:
\_port: (fifo), line:30, parent:inv_response_fifo
|vpiName:fifo
|vpiDirection:5
|vpiHighConn:
\_ref_obj: (fifo), line:225
|vpiName:fifo
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_modport: (structure)
|vpiName:structure
|vpiIODecl:
\_io_decl: (push)
|vpiName:push
|vpiDirection:1
|vpiExpr:
\_logic_net: (push), line:26
|vpiName:push
|vpiNetType:36
|vpiIODecl:
\_io_decl: (pop)
|vpiName:pop
|vpiDirection:1
|vpiExpr:
\_logic_net: (pop), line:27
|vpiName:pop
|vpiNetType:36
|vpiIODecl:
\_io_decl: (data_in)
|vpiName:data_in
|vpiDirection:1
|vpiExpr:
\_logic_net: (data_in), line:28
|vpiName:data_in
|vpiNetType:36
|vpiRange:
\_range: , line:28
|vpiLeftRange:
\_constant: , line:28
|vpiConstType:7
|vpiDecompile:29
|vpiSize:32
|INT:29
|vpiRightRange:
\_constant: , line:28
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (data_out)
|vpiName:data_out
|vpiDirection:2
|vpiExpr:
\_logic_net: (data_out), line:29
|vpiName:data_out
|vpiNetType:36
|vpiRange:
\_range: , line:29
|vpiLeftRange:
\_constant: , line:29
|vpiConstType:7
|vpiDecompile:29
|vpiSize:32
|INT:29
|vpiRightRange:
\_constant: , line:29
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (valid)
|vpiName:valid
|vpiDirection:2
|vpiExpr:
\_logic_net: (valid), line:30
|vpiName:valid
|vpiNetType:36
|vpiIODecl:
\_io_decl: (full)
|vpiName:full
|vpiDirection:2
|vpiExpr:
\_logic_net: (full), line:31
|vpiName:full
|vpiNetType:36
|vpiIODecl:
\_io_decl: (empty)
|vpiName:empty
|vpiDirection:2
|vpiExpr:
\_logic_net: (empty), line:32
|vpiName:empty
|vpiNetType:36
|vpiInterface:
\_interface: work@l2_fifo_interface (fifo), file:third_party/cores/taiga/l2_arbiter/l2_arbiter.sv, line:225
|vpiDefName:work@l2_fifo_interface
|vpiName:fifo
|vpiModport:
\_modport: (dequeue)
|vpiName:dequeue
|vpiIODecl:
\_io_decl: (valid)
|vpiName:valid
|vpiDirection:1
|vpiExpr:
\_logic_net: (valid), line:30
|vpiIODecl:
\_io_decl: (data_out)
|vpiName:data_out
|vpiDirection:1
|vpiExpr:
\_logic_net: (data_out), line:29
|vpiIODecl:
\_io_decl: (pop)
|vpiName:pop
|vpiDirection:2
|vpiExpr:
\_logic_net: (pop), line:27
|vpiInterface:
\_interface: work@l2_fifo_interface (fifo), file:third_party/cores/taiga/l2_arbiter/l2_arbiter.sv, line:225
|vpiModport:
\_modport: (enqueue)
|vpiName:enqueue
|vpiIODecl:
\_io_decl: (full)
|vpiName:full
|vpiDirection:1
|vpiExpr:
\_logic_net: (full), line:31
|vpiIODecl:
\_io_decl: (empty)
|vpiName:empty
|vpiDirection:1
|vpiExpr:
\_logic_net: (empty), line:32
|vpiIODecl:
\_io_decl: (data_in)
|vpiName:data_in
|vpiDirection:2
|vpiExpr:
\_logic_net: (data_in), line:28
|vpiIODecl:
\_io_decl: (push)
|vpiName:push
|vpiDirection:2
|vpiExpr:
\_logic_net: (push), line:26
|vpiInterface:
\_interface: work@l2_fifo_interface (fifo), file:third_party/cores/taiga/l2_arbiter/l2_arbiter.sv, line:225
|vpiModport:
\_modport: (structure)
|vpiGenScopeArray:
\_gen_scope_array: (genblk1), line:37, parent:inv_response_fifo
|vpiName:genblk1
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk4[0].inv_response_fifo.genblk1
|vpiGenScope:
\_gen_scope: , parent:genblk1
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk4[0].inv_response_fifo.genblk1
|vpiGenScopeArray:
\_gen_scope_array: (genblk1), line:54
|vpiName:genblk1
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk4[0].inv_response_fifo.genblk1.genblk1
|vpiGenScope:
\_gen_scope: , parent:genblk1
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk4[0].inv_response_fifo.genblk1.genblk1
|vpiNet:
\_logic_net: (write_index), line:58
|vpiName:write_index
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk4[0].inv_response_fifo.genblk1.genblk1.write_index
|vpiNetType:36
|vpiRange:
\_range: , line:58
|vpiLeftRange:
\_constant: , line:58
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:58
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (read_index), line:59
|vpiName:read_index
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk4[0].inv_response_fifo.genblk1.genblk1.read_index
|vpiNetType:36
|vpiRange:
\_range: , line:59
|vpiLeftRange:
\_constant: , line:59
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:59
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiProcess:
\_always: , line:67
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:67
|vpiCondition:
\_operation: , line:67
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:67
|vpiName:clk
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk4[0].inv_response_fifo.genblk1.genblk1.clk
|vpiStmt:
\_begin: , line:67
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk4[0].inv_response_fifo.genblk1.genblk1
|vpiStmt:
\_if_else: , line:68
|vpiCondition:
\_ref_obj: (rst), line:68
|vpiName:rst
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk4[0].inv_response_fifo.genblk1.genblk1.rst
|vpiStmt:
\_begin: , line:68
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk4[0].inv_response_fifo.genblk1.genblk1
|vpiStmt:
\_assignment: , line:69
|vpiOpType:82
|vpiLhs:
\_ref_obj: (read_index), line:69
|vpiName:read_index
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk4[0].inv_response_fifo.genblk1.genblk1.read_index
|vpiRhs:
\_constant: , line:69
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiStmt:
\_assignment: , line:70
|vpiOpType:82
|vpiLhs:
\_ref_obj: (write_index), line:70
|vpiName:write_index
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk4[0].inv_response_fifo.genblk1.genblk1.write_index
|vpiRhs:
\_constant: , line:70
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiElseStmt:
\_begin: , line:72
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk4[0].inv_response_fifo.genblk1.genblk1
|vpiStmt:
\_assignment: , line:73
|vpiOpType:82
|vpiLhs:
\_ref_obj: (read_index), line:73
|vpiName:read_index
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk4[0].inv_response_fifo.genblk1.genblk1.read_index
|vpiRhs:
\_operation: , line:73
|vpiOpType:24
|vpiOperand:
\_ref_obj: (read_index), line:73
|vpiName:read_index
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk4[0].inv_response_fifo.genblk1.genblk1.read_index
|vpiOperand:
\_ref_obj: (fifo.pop), line:73
|vpiName:fifo.pop
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk4[0].inv_response_fifo.genblk1.genblk1.fifo.pop
|vpiStmt:
\_assignment: , line:74
|vpiOpType:82
|vpiLhs:
\_ref_obj: (write_index), line:74
|vpiName:write_index
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk4[0].inv_response_fifo.genblk1.genblk1.write_index
|vpiRhs:
\_operation: , line:74
|vpiOpType:24
|vpiOperand:
\_ref_obj: (write_index), line:74
|vpiName:write_index
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk4[0].inv_response_fifo.genblk1.genblk1.write_index
|vpiOperand:
\_ref_obj: (fifo.push), line:74
|vpiName:fifo.push
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk4[0].inv_response_fifo.genblk1.genblk1.fifo.push
|vpiProcess:
\_always: , line:81
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:81
|vpiCondition:
\_operation: , line:81
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:81
|vpiName:clk
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk4[0].inv_response_fifo.genblk1.genblk1.clk
|vpiStmt:
\_begin: , line:81
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk4[0].inv_response_fifo.genblk1.genblk1
|vpiStmt:
\_if_stmt: , line:82
|vpiCondition:
\_ref_obj: (fifo.push), line:82
|vpiName:fifo.push
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk4[0].inv_response_fifo.genblk1.genblk1.fifo.push
|vpiStmt:
\_assignment: , line:83
|vpiOpType:82
|vpiLhs:
\_bit_select: (lut_ram), line:83
|vpiName:lut_ram
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk4[0].inv_response_fifo.genblk1.genblk1.lut_ram
|vpiIndex:
\_ref_obj: (write_index), line:83
|vpiName:write_index
|vpiRhs:
\_ref_obj: (fifo.data_in), line:83
|vpiName:fifo.data_in
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk4[0].inv_response_fifo.genblk1.genblk1.fifo.data_in
|vpiProcess:
\_always: , line:86
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:86
|vpiCondition:
\_operation: , line:86
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:86
|vpiName:clk
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk4[0].inv_response_fifo.genblk1.genblk1.clk
|vpiStmt:
\_begin: , line:86
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk4[0].inv_response_fifo.genblk1.genblk1
|vpiStmt:
\_if_else: , line:87
|vpiCondition:
\_ref_obj: (rst), line:87
|vpiName:rst
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk4[0].inv_response_fifo.genblk1.genblk1.rst
|vpiStmt:
\_begin: , line:87
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk4[0].inv_response_fifo.genblk1.genblk1
|vpiStmt:
\_assignment: , line:88
|vpiOpType:82
|vpiLhs:
\_bit_select: (count_v), line:88
|vpiName:count_v
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk4[0].inv_response_fifo.genblk1.genblk1.count_v
|vpiIndex:
\_constant: , line:88
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiRhs:
\_constant: , line:88
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiStmt:
\_for_stmt: , line:89
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk4[0].inv_response_fifo.genblk1.genblk1
|vpiCondition:
\_operation: , line:89
|vpiOpType:21
|vpiOperand:
\_ref_obj: (i), line:89
|vpiName:i
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk4[0].inv_response_fifo.genblk1.genblk1.i
|vpiOperand:
\_ref_obj: (FIFO_DEPTH), line:89
|vpiName:FIFO_DEPTH
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk4[0].inv_response_fifo.genblk1.genblk1.FIFO_DEPTH
|vpiForInitStmt:
\_assign_stmt:
|vpiRhs:
\_constant: , line:89
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiLhs:
\_int_var: (i), line:89
|vpiName:i
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk4[0].inv_response_fifo.genblk1.genblk1.i
|vpiForIncStmt:
\_operation: , line:89
|vpiOpType:62
|vpiOperand:
\_ref_obj: (i), line:89
|vpiName:i
|vpiStmt:
\_assignment: , line:89
|vpiOpType:82
|vpiLhs:
\_bit_select: (count_v), line:89
|vpiName:count_v
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk4[0].inv_response_fifo.genblk1.genblk1.count_v
|vpiIndex:
\_ref_obj: (i), line:89
|vpiName:i
|vpiRhs:
\_constant: , line:89
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiElseStmt:
\_if_else: , line:91
|vpiCondition:
\_operation: , line:91
|vpiOpType:28
|vpiOperand:
\_ref_obj: (fifo.push), line:91
|vpiName:fifo.push
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk4[0].inv_response_fifo.genblk1.genblk1.fifo.push
|vpiOperand:
\_operation: , line:91
|vpiOpType:4
|vpiOperand:
\_ref_obj: (fifo.pop), line:91
|vpiName:fifo.pop
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk4[0].inv_response_fifo.genblk1.genblk1.fifo.pop
|vpiStmt:
\_assignment: , line:92
|vpiOpType:82
|vpiLhs:
\_ref_obj: (count_v), line:92
|vpiName:count_v
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk4[0].inv_response_fifo.genblk1.genblk1.count_v
|vpiRhs:
\_operation: , line:92
|vpiOpType:33
|vpiOperand:
\_part_select: , line:92, parent:count_v
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (count_v)
|vpiLeftRange:
\_operation: , line:92
|vpiOpType:11
|vpiOperand:
\_ref_obj: (FIFO_DEPTH), line:92
|vpiName:FIFO_DEPTH
|vpiOperand:
\_constant: , line:92
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:92
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiOperand:
\_constant: , line:92
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiElseStmt:
\_if_stmt: , line:93
|vpiCondition:
\_operation: , line:93
|vpiOpType:28
|vpiOperand:
\_operation: , line:93
|vpiOpType:4
|vpiOperand:
\_ref_obj: (fifo.push), line:93
|vpiName:fifo.push
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk4[0].inv_response_fifo.genblk1.genblk1.fifo.push
|vpiOperand:
\_ref_obj: (fifo.pop), line:93
|vpiName:fifo.pop
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk4[0].inv_response_fifo.genblk1.genblk1.fifo.pop
|vpiStmt:
\_assignment: , line:94
|vpiOpType:82
|vpiLhs:
\_ref_obj: (count_v), line:94
|vpiName:count_v
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk4[0].inv_response_fifo.genblk1.genblk1.count_v
|vpiRhs:
\_operation: , line:94
|vpiOpType:33
|vpiOperand:
\_constant: , line:94
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiOperand:
\_part_select: , line:94, parent:count_v
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (count_v)
|vpiLeftRange:
\_ref_obj: (FIFO_DEPTH), line:94
|vpiName:FIFO_DEPTH
|vpiRightRange:
\_constant: , line:94
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiArrayNet:
\_array_net: (lut_ram), line:56
|vpiName:lut_ram
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk4[0].inv_response_fifo.genblk1.genblk1.lut_ram
|vpiSize:4
|vpiNet:
\_logic_net: , parent:lut_ram
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk4[0].inv_response_fifo.genblk1.genblk1.lut_ram
|vpiNetType:36
|vpiRange:
\_range: , line:56
|vpiLeftRange:
\_constant: , line:56
|vpiConstType:7
|vpiDecompile:29
|vpiSize:32
|INT:29
|vpiRightRange:
\_constant: , line:56
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiRange:
\_range: , line:56
|vpiLeftRange:
\_constant: , line:56
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiRightRange:
\_constant: , line:56
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiArrayNet:
\_array_net: (count_v), line:61
|vpiName:count_v
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk4[0].inv_response_fifo.genblk1.genblk1.count_v
|vpiSize:5
|vpiNet:
\_logic_net: , parent:count_v
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk4[0].inv_response_fifo.genblk1.genblk1.count_v
|vpiNetType:36
|vpiRange:
\_range: , line:61
|vpiLeftRange:
\_constant: , line:61
|vpiConstType:7
|vpiDecompile:4
|vpiSize:32
|INT:4
|vpiRightRange:
\_constant: , line:61
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiContAssign:
\_cont_assign: , line:65
|vpiRhs:
\_bit_select: (lut_ram), line:65
|vpiName:lut_ram
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk4[0].inv_response_fifo.genblk1.genblk1.lut_ram
|vpiIndex:
\_ref_obj: (read_index), line:65
|vpiName:read_index
|vpiLhs:
\_ref_obj: (fifo.data_out), line:65
|vpiName:fifo.data_out
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk4[0].inv_response_fifo.genblk1.genblk1.fifo.data_out
|vpiContAssign:
\_cont_assign: , line:78
|vpiRhs:
\_bit_select: (count_v), line:78
|vpiName:count_v
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk4[0].inv_response_fifo.genblk1.genblk1.count_v
|vpiIndex:
\_ref_obj: (FIFO_DEPTH), line:78
|vpiName:FIFO_DEPTH
|vpiLhs:
\_ref_obj: (fifo.full), line:78
|vpiName:fifo.full
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk4[0].inv_response_fifo.genblk1.genblk1.fifo.full
|vpiContAssign:
\_cont_assign: , line:79
|vpiRhs:
\_operation: , line:79
|vpiOpType:4
|vpiOperand:
\_bit_select: (count_v), line:79
|vpiName:count_v
|vpiIndex:
\_constant: , line:79
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiLhs:
\_ref_obj: (fifo.valid), line:79
|vpiName:fifo.valid
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk4[0].inv_response_fifo.genblk1.genblk1.fifo.valid
|vpiNet:
\_logic_net: (clk), line:25, parent:inv_response_fifo
|vpiNet:
\_logic_net: (wr_clk), line:26, parent:inv_response_fifo
|vpiNet:
\_logic_net: (rd_clk), line:27, parent:inv_response_fifo
|vpiNet:
\_logic_net: (rst), line:29, parent:inv_response_fifo
|vpiNet:
\_logic_net: (fifo), line:30, parent:inv_response_fifo
|vpiName:fifo
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk4[0].inv_response_fifo.fifo
|vpiParameter:
\_parameter: (ASYNC), line:23
|vpiName:ASYNC
|INT:0
|vpiParameter:
\_parameter: (DATA_WIDTH), line:225
|vpiName:DATA_WIDTH
|INT:30
|vpiParameter:
\_parameter: (FIFO_DEPTH), line:225
|vpiName:FIFO_DEPTH
|INT:4
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (L2_DATA_ATTRIBUTES_FIFO_DEPTH), line:41
|vpiName:L2_DATA_ATTRIBUTES_FIFO_DEPTH
|INT:16
|vpiParameter:
\_parameter: (L2_ID_W), line:46
|vpiName:L2_ID_W
|INT:3
|vpiParameter:
\_parameter: (L2_INPUT_FIFO_DEPTHS), line:34
|vpiName:L2_INPUT_FIFO_DEPTHS
|INT:4
|vpiParameter:
\_parameter: (L2_INVALIDATION_FIFO_DEPTHS), line:35
|vpiName:L2_INVALIDATION_FIFO_DEPTHS
|INT:4
|vpiParameter:
\_parameter: (L2_MEM_ADDR_FIFO_DEPTH), line:39
|vpiName:L2_MEM_ADDR_FIFO_DEPTH
|INT:8
|vpiParameter:
\_parameter: (L2_NUM_PORTS), line:26
|vpiName:L2_NUM_PORTS
|INT:2
|vpiParameter:
\_parameter: (L2_READ_RETURN_FIFO_DEPTHS), line:36
|vpiName:L2_READ_RETURN_FIFO_DEPTHS
|INT:1
|vpiParameter:
\_parameter: (L2_SUB_ID_W), line:27
|vpiName:L2_SUB_ID_W
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiParameter:
\_parameter: (i), line:218
|vpiName:i
|INT:0
|vpiGenScopeArray:
\_gen_scope_array: (genblk4[1]), line:218, parent:l2_arb
|vpiName:genblk4[1]
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk4[1]
|vpiGenScope:
\_gen_scope: , parent:genblk4[1]
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk4[1]
|vpiContAssign:
\_cont_assign: , line:220
|vpiRhs:
\_bit_select: (request.inv_ack), line:220
|vpiName:request.inv_ack
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk4[1].request.inv_ack
|vpiIndex:
\_ref_obj: (i), line:220
|vpiName:i
|vpiLhs:
\_ref_obj: (inv_response_fifos[i].pop), line:220
|vpiName:inv_response_fifos[i].pop
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk4[1].inv_response_fifos[i].pop
|vpiContAssign:
\_cont_assign: , line:221
|vpiRhs:
\_bit_select: (inv_response_fifos.data_out), line:221
|vpiName:inv_response_fifos.data_out
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk4[1].inv_response_fifos.data_out
|vpiIndex:
\_ref_obj: (i), line:221
|vpiName:i
|vpiLhs:
\_ref_obj: (request[i].inv_addr), line:221
|vpiName:request[i].inv_addr
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk4[1].request[i].inv_addr
|vpiContAssign:
\_cont_assign: , line:222
|vpiRhs:
\_bit_select: (inv_response_fifos.valid), line:222
|vpiName:inv_response_fifos.valid
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk4[1].inv_response_fifos.valid
|vpiIndex:
\_ref_obj: (i), line:222
|vpiName:i
|vpiLhs:
\_ref_obj: (request[i].inv_valid), line:222
|vpiName:request[i].inv_valid
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk4[1].request[i].inv_valid
|vpiContAssign:
\_cont_assign: , line:227
|vpiRhs:
\_operation: , line:227
|vpiOpType:28
|vpiOperand:
\_operation: , line:227
|vpiOpType:28
|vpiOperand:
\_ref_obj: (reserv_valid), line:227
|vpiName:reserv_valid
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk4[1].reserv_valid
|vpiOperand:
\_ref_obj: (reserv_store), line:227
|vpiName:reserv_store
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk4[1].reserv_store
|vpiOperand:
\_operation: , line:227
|vpiOpType:4
|vpiOperand:
\_bit_select: (reserv_id_v), line:227
|vpiName:reserv_id_v
|vpiIndex:
\_ref_obj: (i), line:227
|vpiName:i
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk4[1].i
|vpiLhs:
\_ref_obj: (inv_response_fifos[i].push), line:227
|vpiName:inv_response_fifos[i].push
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk4[1].inv_response_fifos[i].push
|vpiContAssign:
\_cont_assign: , line:228
|vpiRhs:
\_bit_select: (requests.addr), line:228
|vpiName:requests.addr
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk4[1].requests.addr
|vpiIndex:
\_ref_obj: (i), line:228
|vpiName:i
|vpiLhs:
\_ref_obj: (inv_response_fifos[i].data_in), line:228
|vpiName:inv_response_fifos[i].data_in
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk4[1].inv_response_fifos[i].data_in
|vpiModule:
\_module: work@l2_fifo (inv_response_fifo), file:third_party/cores/taiga/l2_arbiter/l2_arbiter.sv, line:225
|vpiDefName:work@l2_fifo
|vpiName:inv_response_fifo
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk4[1].inv_response_fifo
|vpiPort:
\_port: (clk), line:25, parent:inv_response_fifo
|vpiName:clk
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (clk), line:225
|vpiName:clk
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (clk), line:25, parent:inv_response_fifo
|vpiName:clk
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk4[1].inv_response_fifo.clk
|vpiNetType:36
|vpiPort:
\_port: (wr_clk), line:26, parent:inv_response_fifo
|vpiName:wr_clk
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (wr_clk), line:225
|vpiName:wr_clk
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (wr_clk), line:26, parent:inv_response_fifo
|vpiName:wr_clk
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk4[1].inv_response_fifo.wr_clk
|vpiNetType:36
|vpiPort:
\_port: (rd_clk), line:27, parent:inv_response_fifo
|vpiName:rd_clk
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (rd_clk), line:225
|vpiName:rd_clk
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (rd_clk), line:27, parent:inv_response_fifo
|vpiName:rd_clk
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk4[1].inv_response_fifo.rd_clk
|vpiNetType:36
|vpiPort:
\_port: (rst), line:29, parent:inv_response_fifo
|vpiName:rst
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (rst), line:225
|vpiName:rst
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (rst), line:29, parent:inv_response_fifo
|vpiName:rst
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk4[1].inv_response_fifo.rst
|vpiNetType:36
|vpiPort:
\_port: (fifo), line:30, parent:inv_response_fifo
|vpiName:fifo
|vpiDirection:5
|vpiHighConn:
\_ref_obj: (fifo), line:225
|vpiName:fifo
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_modport: (structure)
|vpiName:structure
|vpiIODecl:
\_io_decl: (push)
|vpiName:push
|vpiDirection:1
|vpiExpr:
\_logic_net: (push), line:26
|vpiName:push
|vpiNetType:36
|vpiIODecl:
\_io_decl: (pop)
|vpiName:pop
|vpiDirection:1
|vpiExpr:
\_logic_net: (pop), line:27
|vpiName:pop
|vpiNetType:36
|vpiIODecl:
\_io_decl: (data_in)
|vpiName:data_in
|vpiDirection:1
|vpiExpr:
\_logic_net: (data_in), line:28
|vpiName:data_in
|vpiNetType:36
|vpiRange:
\_range: , line:28
|vpiLeftRange:
\_constant: , line:28
|vpiConstType:7
|vpiDecompile:29
|vpiSize:32
|INT:29
|vpiRightRange:
\_constant: , line:28
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (data_out)
|vpiName:data_out
|vpiDirection:2
|vpiExpr:
\_logic_net: (data_out), line:29
|vpiName:data_out
|vpiNetType:36
|vpiRange:
\_range: , line:29
|vpiLeftRange:
\_constant: , line:29
|vpiConstType:7
|vpiDecompile:29
|vpiSize:32
|INT:29
|vpiRightRange:
\_constant: , line:29
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (valid)
|vpiName:valid
|vpiDirection:2
|vpiExpr:
\_logic_net: (valid), line:30
|vpiName:valid
|vpiNetType:36
|vpiIODecl:
\_io_decl: (full)
|vpiName:full
|vpiDirection:2
|vpiExpr:
\_logic_net: (full), line:31
|vpiName:full
|vpiNetType:36
|vpiIODecl:
\_io_decl: (empty)
|vpiName:empty
|vpiDirection:2
|vpiExpr:
\_logic_net: (empty), line:32
|vpiName:empty
|vpiNetType:36
|vpiInterface:
\_interface: work@l2_fifo_interface (fifo), file:third_party/cores/taiga/l2_arbiter/l2_arbiter.sv, line:225
|vpiDefName:work@l2_fifo_interface
|vpiName:fifo
|vpiModport:
\_modport: (dequeue)
|vpiName:dequeue
|vpiIODecl:
\_io_decl: (valid)
|vpiName:valid
|vpiDirection:1
|vpiExpr:
\_logic_net: (valid), line:30
|vpiIODecl:
\_io_decl: (data_out)
|vpiName:data_out
|vpiDirection:1
|vpiExpr:
\_logic_net: (data_out), line:29
|vpiIODecl:
\_io_decl: (pop)
|vpiName:pop
|vpiDirection:2
|vpiExpr:
\_logic_net: (pop), line:27
|vpiInterface:
\_interface: work@l2_fifo_interface (fifo), file:third_party/cores/taiga/l2_arbiter/l2_arbiter.sv, line:225
|vpiModport:
\_modport: (enqueue)
|vpiName:enqueue
|vpiIODecl:
\_io_decl: (full)
|vpiName:full
|vpiDirection:1
|vpiExpr:
\_logic_net: (full), line:31
|vpiIODecl:
\_io_decl: (empty)
|vpiName:empty
|vpiDirection:1
|vpiExpr:
\_logic_net: (empty), line:32
|vpiIODecl:
\_io_decl: (data_in)
|vpiName:data_in
|vpiDirection:2
|vpiExpr:
\_logic_net: (data_in), line:28
|vpiIODecl:
\_io_decl: (push)
|vpiName:push
|vpiDirection:2
|vpiExpr:
\_logic_net: (push), line:26
|vpiInterface:
\_interface: work@l2_fifo_interface (fifo), file:third_party/cores/taiga/l2_arbiter/l2_arbiter.sv, line:225
|vpiModport:
\_modport: (structure)
|vpiGenScopeArray:
\_gen_scope_array: (genblk1), line:37, parent:inv_response_fifo
|vpiName:genblk1
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk4[1].inv_response_fifo.genblk1
|vpiGenScope:
\_gen_scope: , parent:genblk1
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk4[1].inv_response_fifo.genblk1
|vpiGenScopeArray:
\_gen_scope_array: (genblk1), line:54
|vpiName:genblk1
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk4[1].inv_response_fifo.genblk1.genblk1
|vpiGenScope:
\_gen_scope: , parent:genblk1
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk4[1].inv_response_fifo.genblk1.genblk1
|vpiNet:
\_logic_net: (write_index), line:58
|vpiName:write_index
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk4[1].inv_response_fifo.genblk1.genblk1.write_index
|vpiNetType:36
|vpiRange:
\_range: , line:58
|vpiLeftRange:
\_constant: , line:58
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:58
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (read_index), line:59
|vpiName:read_index
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk4[1].inv_response_fifo.genblk1.genblk1.read_index
|vpiNetType:36
|vpiRange:
\_range: , line:59
|vpiLeftRange:
\_constant: , line:59
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:59
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiProcess:
\_always: , line:67
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:67
|vpiCondition:
\_operation: , line:67
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:67
|vpiName:clk
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk4[1].inv_response_fifo.genblk1.genblk1.clk
|vpiStmt:
\_begin: , line:67
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk4[1].inv_response_fifo.genblk1.genblk1
|vpiStmt:
\_if_else: , line:68
|vpiCondition:
\_ref_obj: (rst), line:68
|vpiName:rst
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk4[1].inv_response_fifo.genblk1.genblk1.rst
|vpiStmt:
\_begin: , line:68
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk4[1].inv_response_fifo.genblk1.genblk1
|vpiStmt:
\_assignment: , line:69
|vpiOpType:82
|vpiLhs:
\_ref_obj: (read_index), line:69
|vpiName:read_index
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk4[1].inv_response_fifo.genblk1.genblk1.read_index
|vpiRhs:
\_constant: , line:69
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiStmt:
\_assignment: , line:70
|vpiOpType:82
|vpiLhs:
\_ref_obj: (write_index), line:70
|vpiName:write_index
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk4[1].inv_response_fifo.genblk1.genblk1.write_index
|vpiRhs:
\_constant: , line:70
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiElseStmt:
\_begin: , line:72
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk4[1].inv_response_fifo.genblk1.genblk1
|vpiStmt:
\_assignment: , line:73
|vpiOpType:82
|vpiLhs:
\_ref_obj: (read_index), line:73
|vpiName:read_index
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk4[1].inv_response_fifo.genblk1.genblk1.read_index
|vpiRhs:
\_operation: , line:73
|vpiOpType:24
|vpiOperand:
\_ref_obj: (read_index), line:73
|vpiName:read_index
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk4[1].inv_response_fifo.genblk1.genblk1.read_index
|vpiOperand:
\_ref_obj: (fifo.pop), line:73
|vpiName:fifo.pop
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk4[1].inv_response_fifo.genblk1.genblk1.fifo.pop
|vpiStmt:
\_assignment: , line:74
|vpiOpType:82
|vpiLhs:
\_ref_obj: (write_index), line:74
|vpiName:write_index
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk4[1].inv_response_fifo.genblk1.genblk1.write_index
|vpiRhs:
\_operation: , line:74
|vpiOpType:24
|vpiOperand:
\_ref_obj: (write_index), line:74
|vpiName:write_index
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk4[1].inv_response_fifo.genblk1.genblk1.write_index
|vpiOperand:
\_ref_obj: (fifo.push), line:74
|vpiName:fifo.push
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk4[1].inv_response_fifo.genblk1.genblk1.fifo.push
|vpiProcess:
\_always: , line:81
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:81
|vpiCondition:
\_operation: , line:81
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:81
|vpiName:clk
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk4[1].inv_response_fifo.genblk1.genblk1.clk
|vpiStmt:
\_begin: , line:81
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk4[1].inv_response_fifo.genblk1.genblk1
|vpiStmt:
\_if_stmt: , line:82
|vpiCondition:
\_ref_obj: (fifo.push), line:82
|vpiName:fifo.push
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk4[1].inv_response_fifo.genblk1.genblk1.fifo.push
|vpiStmt:
\_assignment: , line:83
|vpiOpType:82
|vpiLhs:
\_bit_select: (lut_ram), line:83
|vpiName:lut_ram
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk4[1].inv_response_fifo.genblk1.genblk1.lut_ram
|vpiIndex:
\_ref_obj: (write_index), line:83
|vpiName:write_index
|vpiRhs:
\_ref_obj: (fifo.data_in), line:83
|vpiName:fifo.data_in
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk4[1].inv_response_fifo.genblk1.genblk1.fifo.data_in
|vpiProcess:
\_always: , line:86
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:86
|vpiCondition:
\_operation: , line:86
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:86
|vpiName:clk
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk4[1].inv_response_fifo.genblk1.genblk1.clk
|vpiStmt:
\_begin: , line:86
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk4[1].inv_response_fifo.genblk1.genblk1
|vpiStmt:
\_if_else: , line:87
|vpiCondition:
\_ref_obj: (rst), line:87
|vpiName:rst
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk4[1].inv_response_fifo.genblk1.genblk1.rst
|vpiStmt:
\_begin: , line:87
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk4[1].inv_response_fifo.genblk1.genblk1
|vpiStmt:
\_assignment: , line:88
|vpiOpType:82
|vpiLhs:
\_bit_select: (count_v), line:88
|vpiName:count_v
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk4[1].inv_response_fifo.genblk1.genblk1.count_v
|vpiIndex:
\_constant: , line:88
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiRhs:
\_constant: , line:88
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiStmt:
\_for_stmt: , line:89
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk4[1].inv_response_fifo.genblk1.genblk1
|vpiCondition:
\_operation: , line:89
|vpiOpType:21
|vpiOperand:
\_ref_obj: (i), line:89
|vpiName:i
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk4[1].inv_response_fifo.genblk1.genblk1.i
|vpiOperand:
\_ref_obj: (FIFO_DEPTH), line:89
|vpiName:FIFO_DEPTH
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk4[1].inv_response_fifo.genblk1.genblk1.FIFO_DEPTH
|vpiForInitStmt:
\_assign_stmt:
|vpiRhs:
\_constant: , line:89
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiLhs:
\_int_var: (i), line:89
|vpiName:i
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk4[1].inv_response_fifo.genblk1.genblk1.i
|vpiForIncStmt:
\_operation: , line:89
|vpiOpType:62
|vpiOperand:
\_ref_obj: (i), line:89
|vpiName:i
|vpiStmt:
\_assignment: , line:89
|vpiOpType:82
|vpiLhs:
\_bit_select: (count_v), line:89
|vpiName:count_v
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk4[1].inv_response_fifo.genblk1.genblk1.count_v
|vpiIndex:
\_ref_obj: (i), line:89
|vpiName:i
|vpiRhs:
\_constant: , line:89
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiElseStmt:
\_if_else: , line:91
|vpiCondition:
\_operation: , line:91
|vpiOpType:28
|vpiOperand:
\_ref_obj: (fifo.push), line:91
|vpiName:fifo.push
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk4[1].inv_response_fifo.genblk1.genblk1.fifo.push
|vpiOperand:
\_operation: , line:91
|vpiOpType:4
|vpiOperand:
\_ref_obj: (fifo.pop), line:91
|vpiName:fifo.pop
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk4[1].inv_response_fifo.genblk1.genblk1.fifo.pop
|vpiStmt:
\_assignment: , line:92
|vpiOpType:82
|vpiLhs:
\_ref_obj: (count_v), line:92
|vpiName:count_v
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk4[1].inv_response_fifo.genblk1.genblk1.count_v
|vpiRhs:
\_operation: , line:92
|vpiOpType:33
|vpiOperand:
\_part_select: , line:92, parent:count_v
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (count_v)
|vpiLeftRange:
\_operation: , line:92
|vpiOpType:11
|vpiOperand:
\_ref_obj: (FIFO_DEPTH), line:92
|vpiName:FIFO_DEPTH
|vpiOperand:
\_constant: , line:92
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:92
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiOperand:
\_constant: , line:92
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiElseStmt:
\_if_stmt: , line:93
|vpiCondition:
\_operation: , line:93
|vpiOpType:28
|vpiOperand:
\_operation: , line:93
|vpiOpType:4
|vpiOperand:
\_ref_obj: (fifo.push), line:93
|vpiName:fifo.push
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk4[1].inv_response_fifo.genblk1.genblk1.fifo.push
|vpiOperand:
\_ref_obj: (fifo.pop), line:93
|vpiName:fifo.pop
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk4[1].inv_response_fifo.genblk1.genblk1.fifo.pop
|vpiStmt:
\_assignment: , line:94
|vpiOpType:82
|vpiLhs:
\_ref_obj: (count_v), line:94
|vpiName:count_v
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk4[1].inv_response_fifo.genblk1.genblk1.count_v
|vpiRhs:
\_operation: , line:94
|vpiOpType:33
|vpiOperand:
\_constant: , line:94
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiOperand:
\_part_select: , line:94, parent:count_v
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (count_v)
|vpiLeftRange:
\_ref_obj: (FIFO_DEPTH), line:94
|vpiName:FIFO_DEPTH
|vpiRightRange:
\_constant: , line:94
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiArrayNet:
\_array_net: (lut_ram), line:56
|vpiName:lut_ram
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk4[1].inv_response_fifo.genblk1.genblk1.lut_ram
|vpiSize:4
|vpiNet:
\_logic_net: , parent:lut_ram
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk4[1].inv_response_fifo.genblk1.genblk1.lut_ram
|vpiNetType:36
|vpiRange:
\_range: , line:56
|vpiLeftRange:
\_constant: , line:56
|vpiConstType:7
|vpiDecompile:29
|vpiSize:32
|INT:29
|vpiRightRange:
\_constant: , line:56
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiRange:
\_range: , line:56
|vpiLeftRange:
\_constant: , line:56
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiRightRange:
\_constant: , line:56
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiArrayNet:
\_array_net: (count_v), line:61
|vpiName:count_v
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk4[1].inv_response_fifo.genblk1.genblk1.count_v
|vpiSize:5
|vpiNet:
\_logic_net: , parent:count_v
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk4[1].inv_response_fifo.genblk1.genblk1.count_v
|vpiNetType:36
|vpiRange:
\_range: , line:61
|vpiLeftRange:
\_constant: , line:61
|vpiConstType:7
|vpiDecompile:4
|vpiSize:32
|INT:4
|vpiRightRange:
\_constant: , line:61
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiContAssign:
\_cont_assign: , line:65
|vpiRhs:
\_bit_select: (lut_ram), line:65
|vpiName:lut_ram
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk4[1].inv_response_fifo.genblk1.genblk1.lut_ram
|vpiIndex:
\_ref_obj: (read_index), line:65
|vpiName:read_index
|vpiLhs:
\_ref_obj: (fifo.data_out), line:65
|vpiName:fifo.data_out
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk4[1].inv_response_fifo.genblk1.genblk1.fifo.data_out
|vpiContAssign:
\_cont_assign: , line:78
|vpiRhs:
\_bit_select: (count_v), line:78
|vpiName:count_v
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk4[1].inv_response_fifo.genblk1.genblk1.count_v
|vpiIndex:
\_ref_obj: (FIFO_DEPTH), line:78
|vpiName:FIFO_DEPTH
|vpiLhs:
\_ref_obj: (fifo.full), line:78
|vpiName:fifo.full
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk4[1].inv_response_fifo.genblk1.genblk1.fifo.full
|vpiContAssign:
\_cont_assign: , line:79
|vpiRhs:
\_operation: , line:79
|vpiOpType:4
|vpiOperand:
\_bit_select: (count_v), line:79
|vpiName:count_v
|vpiIndex:
\_constant: , line:79
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiLhs:
\_ref_obj: (fifo.valid), line:79
|vpiName:fifo.valid
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk4[1].inv_response_fifo.genblk1.genblk1.fifo.valid
|vpiNet:
\_logic_net: (clk), line:25, parent:inv_response_fifo
|vpiNet:
\_logic_net: (wr_clk), line:26, parent:inv_response_fifo
|vpiNet:
\_logic_net: (rd_clk), line:27, parent:inv_response_fifo
|vpiNet:
\_logic_net: (rst), line:29, parent:inv_response_fifo
|vpiNet:
\_logic_net: (fifo), line:30, parent:inv_response_fifo
|vpiName:fifo
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk4[1].inv_response_fifo.fifo
|vpiParameter:
\_parameter: (ASYNC), line:23
|vpiName:ASYNC
|INT:0
|vpiParameter:
\_parameter: (DATA_WIDTH), line:225
|vpiName:DATA_WIDTH
|INT:30
|vpiParameter:
\_parameter: (FIFO_DEPTH), line:225
|vpiName:FIFO_DEPTH
|INT:4
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (L2_DATA_ATTRIBUTES_FIFO_DEPTH), line:41
|vpiName:L2_DATA_ATTRIBUTES_FIFO_DEPTH
|INT:16
|vpiParameter:
\_parameter: (L2_ID_W), line:46
|vpiName:L2_ID_W
|INT:3
|vpiParameter:
\_parameter: (L2_INPUT_FIFO_DEPTHS), line:34
|vpiName:L2_INPUT_FIFO_DEPTHS
|INT:4
|vpiParameter:
\_parameter: (L2_INVALIDATION_FIFO_DEPTHS), line:35
|vpiName:L2_INVALIDATION_FIFO_DEPTHS
|INT:4
|vpiParameter:
\_parameter: (L2_MEM_ADDR_FIFO_DEPTH), line:39
|vpiName:L2_MEM_ADDR_FIFO_DEPTH
|INT:8
|vpiParameter:
\_parameter: (L2_NUM_PORTS), line:26
|vpiName:L2_NUM_PORTS
|INT:2
|vpiParameter:
\_parameter: (L2_READ_RETURN_FIFO_DEPTHS), line:36
|vpiName:L2_READ_RETURN_FIFO_DEPTHS
|INT:1
|vpiParameter:
\_parameter: (L2_SUB_ID_W), line:27
|vpiName:L2_SUB_ID_W
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiParameter:
\_parameter: (i), line:218
|vpiName:i
|INT:1
|vpiGenScopeArray:
\_gen_scope_array: (genblk5[0]), line:283, parent:l2_arb
|vpiName:genblk5[0]
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk5[0]
|vpiGenScope:
\_gen_scope: , parent:genblk5[0]
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk5[0]
|vpiContAssign:
\_cont_assign: , line:285
|vpiRhs:
\_bit_select: (request.rd_data_ack), line:285
|vpiName:request.rd_data_ack
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk5[0].request.rd_data_ack
|vpiIndex:
\_ref_obj: (i), line:285
|vpiName:i
|vpiLhs:
\_ref_obj: (returndata_fifos[i].pop), line:285
|vpiName:returndata_fifos[i].pop
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk5[0].returndata_fifos[i].pop
|vpiContAssign:
\_cont_assign: , line:286
|vpiRhs:
\_bit_select: (returndata_fifos.data_out), line:286
|vpiName:returndata_fifos.data_out
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk5[0].returndata_fifos.data_out
|vpiIndex:
\_ref_obj: (i), line:286
|vpiName:i
|vpiLhs:
\_bit_select: (return_data), line:286
|vpiName:return_data
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk5[0].return_data
|vpiIndex:
\_ref_obj: (i), line:286
|vpiName:i
|vpiContAssign:
\_cont_assign: , line:287
|vpiRhs:
\_bit_select: (return_data.data), line:287
|vpiName:return_data.data
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk5[0].return_data.data
|vpiIndex:
\_ref_obj: (i), line:287
|vpiName:i
|vpiLhs:
\_ref_obj: (request[i].rd_data), line:287
|vpiName:request[i].rd_data
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk5[0].request[i].rd_data
|vpiContAssign:
\_cont_assign: , line:288
|vpiRhs:
\_bit_select: (return_data.sub_id), line:288
|vpiName:return_data.sub_id
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk5[0].return_data.sub_id
|vpiIndex:
\_ref_obj: (i), line:288
|vpiName:i
|vpiLhs:
\_ref_obj: (request[i].rd_sub_id), line:288
|vpiName:request[i].rd_sub_id
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk5[0].request[i].rd_sub_id
|vpiContAssign:
\_cont_assign: , line:289
|vpiRhs:
\_bit_select: (returndata_fifos.valid), line:289
|vpiName:returndata_fifos.valid
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk5[0].returndata_fifos.valid
|vpiIndex:
\_ref_obj: (i), line:289
|vpiName:i
|vpiLhs:
\_ref_obj: (request[i].rd_data_valid), line:289
|vpiName:request[i].rd_data_valid
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk5[0].request[i].rd_data_valid
|vpiContAssign:
\_cont_assign: , line:294
|vpiRhs:
\_bit_select: (return_push), line:294
|vpiName:return_push
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk5[0].return_push
|vpiIndex:
\_ref_obj: (i), line:294
|vpiName:i
|vpiLhs:
\_ref_obj: (returndata_fifos[i].push), line:294
|vpiName:returndata_fifos[i].push
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk5[0].returndata_fifos[i].push
|vpiContAssign:
\_cont_assign: , line:295
|vpiRhs:
\_operation: , line:295
|vpiOpType:33
|vpiOperand:
\_ref_obj: (mem_return_data.sub_id), line:295
|vpiName:mem_return_data.sub_id
|vpiOperand:
\_ref_obj: (mem_return_data.data), line:295
|vpiName:mem_return_data.data
|vpiLhs:
\_ref_obj: (returndata_fifos[i].data_in), line:295
|vpiName:returndata_fifos[i].data_in
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk5[0].returndata_fifos[i].data_in
|vpiModule:
\_module: work@l2_fifo (returndata_fifo), file:third_party/cores/taiga/l2_arbiter/l2_arbiter.sv, line:292
|vpiDefName:work@l2_fifo
|vpiName:returndata_fifo
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk5[0].returndata_fifo
|vpiPort:
\_port: (clk), line:25, parent:returndata_fifo
|vpiName:clk
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (clk), line:292
|vpiName:clk
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (clk), line:25, parent:returndata_fifo
|vpiName:clk
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk5[0].returndata_fifo.clk
|vpiNetType:36
|vpiPort:
\_port: (wr_clk), line:26, parent:returndata_fifo
|vpiName:wr_clk
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (wr_clk), line:292
|vpiName:wr_clk
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (wr_clk), line:26, parent:returndata_fifo
|vpiName:wr_clk
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk5[0].returndata_fifo.wr_clk
|vpiNetType:36
|vpiPort:
\_port: (rd_clk), line:27, parent:returndata_fifo
|vpiName:rd_clk
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (rd_clk), line:292
|vpiName:rd_clk
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (rd_clk), line:27, parent:returndata_fifo
|vpiName:rd_clk
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk5[0].returndata_fifo.rd_clk
|vpiNetType:36
|vpiPort:
\_port: (rst), line:29, parent:returndata_fifo
|vpiName:rst
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (rst), line:292
|vpiName:rst
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (rst), line:29, parent:returndata_fifo
|vpiName:rst
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk5[0].returndata_fifo.rst
|vpiNetType:36
|vpiPort:
\_port: (fifo), line:30, parent:returndata_fifo
|vpiName:fifo
|vpiDirection:5
|vpiHighConn:
\_ref_obj: (fifo), line:292
|vpiName:fifo
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_modport: (structure)
|vpiName:structure
|vpiIODecl:
\_io_decl: (push)
|vpiName:push
|vpiDirection:1
|vpiExpr:
\_logic_net: (push), line:26
|vpiName:push
|vpiNetType:36
|vpiIODecl:
\_io_decl: (pop)
|vpiName:pop
|vpiDirection:1
|vpiExpr:
\_logic_net: (pop), line:27
|vpiName:pop
|vpiNetType:36
|vpiIODecl:
\_io_decl: (data_in)
|vpiName:data_in
|vpiDirection:1
|vpiExpr:
\_logic_net: (data_in), line:28
|vpiName:data_in
|vpiNetType:36
|vpiRange:
\_range: , line:28
|vpiLeftRange:
\_constant: , line:28
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:28
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (data_out)
|vpiName:data_out
|vpiDirection:2
|vpiExpr:
\_logic_net: (data_out), line:29
|vpiName:data_out
|vpiNetType:36
|vpiRange:
\_range: , line:29
|vpiLeftRange:
\_constant: , line:29
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:29
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (valid)
|vpiName:valid
|vpiDirection:2
|vpiExpr:
\_logic_net: (valid), line:30
|vpiName:valid
|vpiNetType:36
|vpiIODecl:
\_io_decl: (full)
|vpiName:full
|vpiDirection:2
|vpiExpr:
\_logic_net: (full), line:31
|vpiName:full
|vpiNetType:36
|vpiIODecl:
\_io_decl: (empty)
|vpiName:empty
|vpiDirection:2
|vpiExpr:
\_logic_net: (empty), line:32
|vpiName:empty
|vpiNetType:36
|vpiInterface:
\_interface: work@l2_fifo_interface (fifo), file:third_party/cores/taiga/l2_arbiter/l2_arbiter.sv, line:292
|vpiDefName:work@l2_fifo_interface
|vpiName:fifo
|vpiModport:
\_modport: (dequeue)
|vpiName:dequeue
|vpiIODecl:
\_io_decl: (valid)
|vpiName:valid
|vpiDirection:1
|vpiExpr:
\_logic_net: (valid), line:30
|vpiIODecl:
\_io_decl: (data_out)
|vpiName:data_out
|vpiDirection:1
|vpiExpr:
\_logic_net: (data_out), line:29
|vpiIODecl:
\_io_decl: (pop)
|vpiName:pop
|vpiDirection:2
|vpiExpr:
\_logic_net: (pop), line:27
|vpiInterface:
\_interface: work@l2_fifo_interface (fifo), file:third_party/cores/taiga/l2_arbiter/l2_arbiter.sv, line:292
|vpiModport:
\_modport: (enqueue)
|vpiName:enqueue
|vpiIODecl:
\_io_decl: (full)
|vpiName:full
|vpiDirection:1
|vpiExpr:
\_logic_net: (full), line:31
|vpiIODecl:
\_io_decl: (empty)
|vpiName:empty
|vpiDirection:1
|vpiExpr:
\_logic_net: (empty), line:32
|vpiIODecl:
\_io_decl: (data_in)
|vpiName:data_in
|vpiDirection:2
|vpiExpr:
\_logic_net: (data_in), line:28
|vpiIODecl:
\_io_decl: (push)
|vpiName:push
|vpiDirection:2
|vpiExpr:
\_logic_net: (push), line:26
|vpiInterface:
\_interface: work@l2_fifo_interface (fifo), file:third_party/cores/taiga/l2_arbiter/l2_arbiter.sv, line:292
|vpiModport:
\_modport: (structure)
|vpiGenScopeArray:
\_gen_scope_array: (genblk1), line:37, parent:returndata_fifo
|vpiName:genblk1
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk5[0].returndata_fifo.genblk1
|vpiGenScope:
\_gen_scope: , parent:genblk1
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk5[0].returndata_fifo.genblk1
|vpiGenScopeArray:
\_gen_scope_array: (genblk1), line:39
|vpiName:genblk1
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk5[0].returndata_fifo.genblk1.genblk1
|vpiGenScope:
\_gen_scope: , parent:genblk1
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk5[0].returndata_fifo.genblk1.genblk1
|vpiNet:
\_logic_net: (write_index), line:58
|vpiName:write_index
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk5[0].returndata_fifo.genblk1.genblk1.write_index
|vpiNetType:36
|vpiRange:
\_range: , line:58
|vpiLeftRange:
\_constant: , line:58
|vpiConstType:7
|vpiDecompile:18446744073709551615
|vpiSize:32
|INT:-1
|vpiRightRange:
\_constant: , line:58
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (read_index), line:59
|vpiName:read_index
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk5[0].returndata_fifo.genblk1.genblk1.read_index
|vpiNetType:36
|vpiRange:
\_range: , line:59
|vpiLeftRange:
\_constant: , line:59
|vpiConstType:7
|vpiDecompile:18446744073709551615
|vpiSize:32
|INT:-1
|vpiRightRange:
\_constant: , line:59
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiProcess:
\_always: , line:40
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:40
|vpiCondition:
\_operation: , line:40
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:40
|vpiName:clk
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk5[0].returndata_fifo.genblk1.genblk1.clk
|vpiStmt:
\_begin: , line:40
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk5[0].returndata_fifo.genblk1.genblk1
|vpiStmt:
\_if_else: , line:41
|vpiCondition:
\_ref_obj: (rst), line:41
|vpiName:rst
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk5[0].returndata_fifo.genblk1.genblk1.rst
|vpiStmt:
\_assignment: , line:42
|vpiOpType:82
|vpiLhs:
\_ref_obj: (fifo.valid), line:42
|vpiName:fifo.valid
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk5[0].returndata_fifo.genblk1.genblk1.fifo.valid
|vpiRhs:
\_constant: , line:42
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiElseStmt:
\_if_else: , line:43
|vpiCondition:
\_ref_obj: (fifo.push), line:43
|vpiName:fifo.push
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk5[0].returndata_fifo.genblk1.genblk1.fifo.push
|vpiStmt:
\_assignment: , line:44
|vpiOpType:82
|vpiLhs:
\_ref_obj: (fifo.valid), line:44
|vpiName:fifo.valid
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk5[0].returndata_fifo.genblk1.genblk1.fifo.valid
|vpiRhs:
\_constant: , line:44
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiElseStmt:
\_assignment: , line:46
|vpiOpType:82
|vpiLhs:
\_ref_obj: (fifo.valid), line:46
|vpiName:fifo.valid
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk5[0].returndata_fifo.genblk1.genblk1.fifo.valid
|vpiRhs:
\_constant: , line:46
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiProcess:
\_always: , line:49
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:49
|vpiCondition:
\_operation: , line:49
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:49
|vpiName:clk
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk5[0].returndata_fifo.genblk1.genblk1.clk
|vpiStmt:
\_begin: , line:49
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk5[0].returndata_fifo.genblk1.genblk1
|vpiStmt:
\_if_stmt: , line:50
|vpiCondition:
\_ref_obj: (fifo.push), line:50
|vpiName:fifo.push
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk5[0].returndata_fifo.genblk1.genblk1.fifo.push
|vpiStmt:
\_assignment: , line:51
|vpiOpType:82
|vpiLhs:
\_ref_obj: (fifo.data_out), line:51
|vpiName:fifo.data_out
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk5[0].returndata_fifo.genblk1.genblk1.fifo.data_out
|vpiRhs:
\_ref_obj: (fifo.data_in), line:51
|vpiName:fifo.data_in
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk5[0].returndata_fifo.genblk1.genblk1.fifo.data_in
|vpiProcess:
\_always: , line:67
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:67
|vpiCondition:
\_operation: , line:67
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:67
|vpiName:clk
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk5[0].returndata_fifo.genblk1.genblk1.clk
|vpiStmt:
\_begin: , line:67
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk5[0].returndata_fifo.genblk1.genblk1
|vpiStmt:
\_if_else: , line:68
|vpiCondition:
\_ref_obj: (rst), line:68
|vpiName:rst
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk5[0].returndata_fifo.genblk1.genblk1.rst
|vpiStmt:
\_begin: , line:68
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk5[0].returndata_fifo.genblk1.genblk1
|vpiStmt:
\_assignment: , line:69
|vpiOpType:82
|vpiLhs:
\_ref_obj: (read_index), line:69
|vpiName:read_index
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk5[0].returndata_fifo.genblk1.genblk1.read_index
|vpiRhs:
\_constant: , line:69
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiStmt:
\_assignment: , line:70
|vpiOpType:82
|vpiLhs:
\_ref_obj: (write_index), line:70
|vpiName:write_index
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk5[0].returndata_fifo.genblk1.genblk1.write_index
|vpiRhs:
\_constant: , line:70
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiElseStmt:
\_begin: , line:72
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk5[0].returndata_fifo.genblk1.genblk1
|vpiStmt:
\_assignment: , line:73
|vpiOpType:82
|vpiLhs:
\_ref_obj: (read_index), line:73
|vpiName:read_index
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk5[0].returndata_fifo.genblk1.genblk1.read_index
|vpiRhs:
\_operation: , line:73
|vpiOpType:24
|vpiOperand:
\_ref_obj: (read_index), line:73
|vpiName:read_index
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk5[0].returndata_fifo.genblk1.genblk1.read_index
|vpiOperand:
\_ref_obj: (fifo.pop), line:73
|vpiName:fifo.pop
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk5[0].returndata_fifo.genblk1.genblk1.fifo.pop
|vpiStmt:
\_assignment: , line:74
|vpiOpType:82
|vpiLhs:
\_ref_obj: (write_index), line:74
|vpiName:write_index
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk5[0].returndata_fifo.genblk1.genblk1.write_index
|vpiRhs:
\_operation: , line:74
|vpiOpType:24
|vpiOperand:
\_ref_obj: (write_index), line:74
|vpiName:write_index
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk5[0].returndata_fifo.genblk1.genblk1.write_index
|vpiOperand:
\_ref_obj: (fifo.push), line:74
|vpiName:fifo.push
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk5[0].returndata_fifo.genblk1.genblk1.fifo.push
|vpiProcess:
\_always: , line:81
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:81
|vpiCondition:
\_operation: , line:81
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:81
|vpiName:clk
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk5[0].returndata_fifo.genblk1.genblk1.clk
|vpiStmt:
\_begin: , line:81
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk5[0].returndata_fifo.genblk1.genblk1
|vpiStmt:
\_if_stmt: , line:82
|vpiCondition:
\_ref_obj: (fifo.push), line:82
|vpiName:fifo.push
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk5[0].returndata_fifo.genblk1.genblk1.fifo.push
|vpiStmt:
\_assignment: , line:83
|vpiOpType:82
|vpiLhs:
\_bit_select: (lut_ram), line:83
|vpiName:lut_ram
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk5[0].returndata_fifo.genblk1.genblk1.lut_ram
|vpiIndex:
\_ref_obj: (write_index), line:83
|vpiName:write_index
|vpiRhs:
\_ref_obj: (fifo.data_in), line:83
|vpiName:fifo.data_in
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk5[0].returndata_fifo.genblk1.genblk1.fifo.data_in
|vpiProcess:
\_always: , line:86
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:86
|vpiCondition:
\_operation: , line:86
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:86
|vpiName:clk
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk5[0].returndata_fifo.genblk1.genblk1.clk
|vpiStmt:
\_begin: , line:86
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk5[0].returndata_fifo.genblk1.genblk1
|vpiStmt:
\_if_else: , line:87
|vpiCondition:
\_ref_obj: (rst), line:87
|vpiName:rst
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk5[0].returndata_fifo.genblk1.genblk1.rst
|vpiStmt:
\_begin: , line:87
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk5[0].returndata_fifo.genblk1.genblk1
|vpiStmt:
\_assignment: , line:88
|vpiOpType:82
|vpiLhs:
\_bit_select: (count_v), line:88
|vpiName:count_v
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk5[0].returndata_fifo.genblk1.genblk1.count_v
|vpiIndex:
\_constant: , line:88
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiRhs:
\_constant: , line:88
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiStmt:
\_for_stmt: , line:89
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk5[0].returndata_fifo.genblk1.genblk1
|vpiCondition:
\_operation: , line:89
|vpiOpType:21
|vpiOperand:
\_ref_obj: (i), line:89
|vpiName:i
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk5[0].returndata_fifo.genblk1.genblk1.i
|vpiOperand:
\_ref_obj: (FIFO_DEPTH), line:89
|vpiName:FIFO_DEPTH
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk5[0].returndata_fifo.genblk1.genblk1.FIFO_DEPTH
|vpiForInitStmt:
\_assign_stmt:
|vpiRhs:
\_constant: , line:89
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiLhs:
\_int_var: (i), line:89
|vpiName:i
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk5[0].returndata_fifo.genblk1.genblk1.i
|vpiForIncStmt:
\_operation: , line:89
|vpiOpType:62
|vpiOperand:
\_ref_obj: (i), line:89
|vpiName:i
|vpiStmt:
\_assignment: , line:89
|vpiOpType:82
|vpiLhs:
\_bit_select: (count_v), line:89
|vpiName:count_v
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk5[0].returndata_fifo.genblk1.genblk1.count_v
|vpiIndex:
\_ref_obj: (i), line:89
|vpiName:i
|vpiRhs:
\_constant: , line:89
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiElseStmt:
\_if_else: , line:91
|vpiCondition:
\_operation: , line:91
|vpiOpType:28
|vpiOperand:
\_ref_obj: (fifo.push), line:91
|vpiName:fifo.push
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk5[0].returndata_fifo.genblk1.genblk1.fifo.push
|vpiOperand:
\_operation: , line:91
|vpiOpType:4
|vpiOperand:
\_ref_obj: (fifo.pop), line:91
|vpiName:fifo.pop
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk5[0].returndata_fifo.genblk1.genblk1.fifo.pop
|vpiStmt:
\_assignment: , line:92
|vpiOpType:82
|vpiLhs:
\_ref_obj: (count_v), line:92
|vpiName:count_v
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk5[0].returndata_fifo.genblk1.genblk1.count_v
|vpiRhs:
\_operation: , line:92
|vpiOpType:33
|vpiOperand:
\_part_select: , line:92, parent:count_v
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (count_v)
|vpiLeftRange:
\_operation: , line:92
|vpiOpType:11
|vpiOperand:
\_ref_obj: (FIFO_DEPTH), line:92
|vpiName:FIFO_DEPTH
|vpiOperand:
\_constant: , line:92
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:92
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiOperand:
\_constant: , line:92
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiElseStmt:
\_if_stmt: , line:93
|vpiCondition:
\_operation: , line:93
|vpiOpType:28
|vpiOperand:
\_operation: , line:93
|vpiOpType:4
|vpiOperand:
\_ref_obj: (fifo.push), line:93
|vpiName:fifo.push
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk5[0].returndata_fifo.genblk1.genblk1.fifo.push
|vpiOperand:
\_ref_obj: (fifo.pop), line:93
|vpiName:fifo.pop
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk5[0].returndata_fifo.genblk1.genblk1.fifo.pop
|vpiStmt:
\_assignment: , line:94
|vpiOpType:82
|vpiLhs:
\_ref_obj: (count_v), line:94
|vpiName:count_v
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk5[0].returndata_fifo.genblk1.genblk1.count_v
|vpiRhs:
\_operation: , line:94
|vpiOpType:33
|vpiOperand:
\_constant: , line:94
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiOperand:
\_part_select: , line:94, parent:count_v
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (count_v)
|vpiLeftRange:
\_ref_obj: (FIFO_DEPTH), line:94
|vpiName:FIFO_DEPTH
|vpiRightRange:
\_constant: , line:94
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiArrayNet:
\_array_net: (lut_ram), line:56
|vpiName:lut_ram
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk5[0].returndata_fifo.genblk1.genblk1.lut_ram
|vpiSize:1
|vpiNet:
\_logic_net: , parent:lut_ram
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk5[0].returndata_fifo.genblk1.genblk1.lut_ram
|vpiNetType:36
|vpiRange:
\_range: , line:56
|vpiLeftRange:
\_constant: , line:56
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:56
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiRange:
\_range: , line:56
|vpiLeftRange:
\_constant: , line:56
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiRightRange:
\_constant: , line:56
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiArrayNet:
\_array_net: (count_v), line:61
|vpiName:count_v
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk5[0].returndata_fifo.genblk1.genblk1.count_v
|vpiSize:2
|vpiNet:
\_logic_net: , parent:count_v
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk5[0].returndata_fifo.genblk1.genblk1.count_v
|vpiNetType:36
|vpiRange:
\_range: , line:61
|vpiLeftRange:
\_constant: , line:61
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:61
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiContAssign:
\_cont_assign: , line:65
|vpiRhs:
\_bit_select: (lut_ram), line:65
|vpiName:lut_ram
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk5[0].returndata_fifo.genblk1.genblk1.lut_ram
|vpiIndex:
\_ref_obj: (read_index), line:65
|vpiName:read_index
|vpiLhs:
\_ref_obj: (fifo.data_out), line:65
|vpiName:fifo.data_out
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk5[0].returndata_fifo.genblk1.genblk1.fifo.data_out
|vpiContAssign:
\_cont_assign: , line:78
|vpiRhs:
\_bit_select: (count_v), line:78
|vpiName:count_v
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk5[0].returndata_fifo.genblk1.genblk1.count_v
|vpiIndex:
\_ref_obj: (FIFO_DEPTH), line:78
|vpiName:FIFO_DEPTH
|vpiLhs:
\_ref_obj: (fifo.full), line:78
|vpiName:fifo.full
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk5[0].returndata_fifo.genblk1.genblk1.fifo.full
|vpiContAssign:
\_cont_assign: , line:79
|vpiRhs:
\_operation: , line:79
|vpiOpType:4
|vpiOperand:
\_bit_select: (count_v), line:79
|vpiName:count_v
|vpiIndex:
\_constant: , line:79
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiLhs:
\_ref_obj: (fifo.valid), line:79
|vpiName:fifo.valid
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk5[0].returndata_fifo.genblk1.genblk1.fifo.valid
|vpiNet:
\_logic_net: (clk), line:25, parent:returndata_fifo
|vpiNet:
\_logic_net: (wr_clk), line:26, parent:returndata_fifo
|vpiNet:
\_logic_net: (rd_clk), line:27, parent:returndata_fifo
|vpiNet:
\_logic_net: (rst), line:29, parent:returndata_fifo
|vpiNet:
\_logic_net: (fifo), line:30, parent:returndata_fifo
|vpiName:fifo
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk5[0].returndata_fifo.fifo
|vpiParameter:
\_parameter: (ASYNC), line:23
|vpiName:ASYNC
|INT:0
|vpiParameter:
\_parameter: (DATA_WIDTH), line:292
|vpiName:DATA_WIDTH
|INT:32
|vpiParameter:
\_parameter: (FIFO_DEPTH), line:292
|vpiName:FIFO_DEPTH
|INT:1
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (L2_DATA_ATTRIBUTES_FIFO_DEPTH), line:41
|vpiName:L2_DATA_ATTRIBUTES_FIFO_DEPTH
|INT:16
|vpiParameter:
\_parameter: (L2_ID_W), line:46
|vpiName:L2_ID_W
|INT:3
|vpiParameter:
\_parameter: (L2_INPUT_FIFO_DEPTHS), line:34
|vpiName:L2_INPUT_FIFO_DEPTHS
|INT:4
|vpiParameter:
\_parameter: (L2_INVALIDATION_FIFO_DEPTHS), line:35
|vpiName:L2_INVALIDATION_FIFO_DEPTHS
|INT:4
|vpiParameter:
\_parameter: (L2_MEM_ADDR_FIFO_DEPTH), line:39
|vpiName:L2_MEM_ADDR_FIFO_DEPTH
|INT:8
|vpiParameter:
\_parameter: (L2_NUM_PORTS), line:26
|vpiName:L2_NUM_PORTS
|INT:2
|vpiParameter:
\_parameter: (L2_READ_RETURN_FIFO_DEPTHS), line:36
|vpiName:L2_READ_RETURN_FIFO_DEPTHS
|INT:1
|vpiParameter:
\_parameter: (L2_SUB_ID_W), line:27
|vpiName:L2_SUB_ID_W
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiParameter:
\_parameter: (i), line:283
|vpiName:i
|INT:0
|vpiGenScopeArray:
\_gen_scope_array: (genblk5[1]), line:283, parent:l2_arb
|vpiName:genblk5[1]
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk5[1]
|vpiGenScope:
\_gen_scope: , parent:genblk5[1]
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk5[1]
|vpiContAssign:
\_cont_assign: , line:285
|vpiRhs:
\_bit_select: (request.rd_data_ack), line:285
|vpiName:request.rd_data_ack
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk5[1].request.rd_data_ack
|vpiIndex:
\_ref_obj: (i), line:285
|vpiName:i
|vpiLhs:
\_ref_obj: (returndata_fifos[i].pop), line:285
|vpiName:returndata_fifos[i].pop
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk5[1].returndata_fifos[i].pop
|vpiContAssign:
\_cont_assign: , line:286
|vpiRhs:
\_bit_select: (returndata_fifos.data_out), line:286
|vpiName:returndata_fifos.data_out
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk5[1].returndata_fifos.data_out
|vpiIndex:
\_ref_obj: (i), line:286
|vpiName:i
|vpiLhs:
\_bit_select: (return_data), line:286
|vpiName:return_data
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk5[1].return_data
|vpiIndex:
\_ref_obj: (i), line:286
|vpiName:i
|vpiContAssign:
\_cont_assign: , line:287
|vpiRhs:
\_bit_select: (return_data.data), line:287
|vpiName:return_data.data
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk5[1].return_data.data
|vpiIndex:
\_ref_obj: (i), line:287
|vpiName:i
|vpiLhs:
\_ref_obj: (request[i].rd_data), line:287
|vpiName:request[i].rd_data
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk5[1].request[i].rd_data
|vpiContAssign:
\_cont_assign: , line:288
|vpiRhs:
\_bit_select: (return_data.sub_id), line:288
|vpiName:return_data.sub_id
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk5[1].return_data.sub_id
|vpiIndex:
\_ref_obj: (i), line:288
|vpiName:i
|vpiLhs:
\_ref_obj: (request[i].rd_sub_id), line:288
|vpiName:request[i].rd_sub_id
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk5[1].request[i].rd_sub_id
|vpiContAssign:
\_cont_assign: , line:289
|vpiRhs:
\_bit_select: (returndata_fifos.valid), line:289
|vpiName:returndata_fifos.valid
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk5[1].returndata_fifos.valid
|vpiIndex:
\_ref_obj: (i), line:289
|vpiName:i
|vpiLhs:
\_ref_obj: (request[i].rd_data_valid), line:289
|vpiName:request[i].rd_data_valid
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk5[1].request[i].rd_data_valid
|vpiContAssign:
\_cont_assign: , line:294
|vpiRhs:
\_bit_select: (return_push), line:294
|vpiName:return_push
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk5[1].return_push
|vpiIndex:
\_ref_obj: (i), line:294
|vpiName:i
|vpiLhs:
\_ref_obj: (returndata_fifos[i].push), line:294
|vpiName:returndata_fifos[i].push
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk5[1].returndata_fifos[i].push
|vpiContAssign:
\_cont_assign: , line:295
|vpiRhs:
\_operation: , line:295
|vpiOpType:33
|vpiOperand:
\_ref_obj: (mem_return_data.sub_id), line:295
|vpiName:mem_return_data.sub_id
|vpiOperand:
\_ref_obj: (mem_return_data.data), line:295
|vpiName:mem_return_data.data
|vpiLhs:
\_ref_obj: (returndata_fifos[i].data_in), line:295
|vpiName:returndata_fifos[i].data_in
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk5[1].returndata_fifos[i].data_in
|vpiModule:
\_module: work@l2_fifo (returndata_fifo), file:third_party/cores/taiga/l2_arbiter/l2_arbiter.sv, line:292
|vpiDefName:work@l2_fifo
|vpiName:returndata_fifo
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk5[1].returndata_fifo
|vpiPort:
\_port: (clk), line:25, parent:returndata_fifo
|vpiName:clk
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (clk), line:292
|vpiName:clk
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (clk), line:25, parent:returndata_fifo
|vpiName:clk
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk5[1].returndata_fifo.clk
|vpiNetType:36
|vpiPort:
\_port: (wr_clk), line:26, parent:returndata_fifo
|vpiName:wr_clk
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (wr_clk), line:292
|vpiName:wr_clk
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (wr_clk), line:26, parent:returndata_fifo
|vpiName:wr_clk
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk5[1].returndata_fifo.wr_clk
|vpiNetType:36
|vpiPort:
\_port: (rd_clk), line:27, parent:returndata_fifo
|vpiName:rd_clk
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (rd_clk), line:292
|vpiName:rd_clk
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (rd_clk), line:27, parent:returndata_fifo
|vpiName:rd_clk
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk5[1].returndata_fifo.rd_clk
|vpiNetType:36
|vpiPort:
\_port: (rst), line:29, parent:returndata_fifo
|vpiName:rst
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (rst), line:292
|vpiName:rst
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (rst), line:29, parent:returndata_fifo
|vpiName:rst
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk5[1].returndata_fifo.rst
|vpiNetType:36
|vpiPort:
\_port: (fifo), line:30, parent:returndata_fifo
|vpiName:fifo
|vpiDirection:5
|vpiHighConn:
\_ref_obj: (fifo), line:292
|vpiName:fifo
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_modport: (structure)
|vpiName:structure
|vpiIODecl:
\_io_decl: (push)
|vpiName:push
|vpiDirection:1
|vpiExpr:
\_logic_net: (push), line:26
|vpiName:push
|vpiNetType:36
|vpiIODecl:
\_io_decl: (pop)
|vpiName:pop
|vpiDirection:1
|vpiExpr:
\_logic_net: (pop), line:27
|vpiName:pop
|vpiNetType:36
|vpiIODecl:
\_io_decl: (data_in)
|vpiName:data_in
|vpiDirection:1
|vpiExpr:
\_logic_net: (data_in), line:28
|vpiName:data_in
|vpiNetType:36
|vpiRange:
\_range: , line:28
|vpiLeftRange:
\_constant: , line:28
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:28
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (data_out)
|vpiName:data_out
|vpiDirection:2
|vpiExpr:
\_logic_net: (data_out), line:29
|vpiName:data_out
|vpiNetType:36
|vpiRange:
\_range: , line:29
|vpiLeftRange:
\_constant: , line:29
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:29
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (valid)
|vpiName:valid
|vpiDirection:2
|vpiExpr:
\_logic_net: (valid), line:30
|vpiName:valid
|vpiNetType:36
|vpiIODecl:
\_io_decl: (full)
|vpiName:full
|vpiDirection:2
|vpiExpr:
\_logic_net: (full), line:31
|vpiName:full
|vpiNetType:36
|vpiIODecl:
\_io_decl: (empty)
|vpiName:empty
|vpiDirection:2
|vpiExpr:
\_logic_net: (empty), line:32
|vpiName:empty
|vpiNetType:36
|vpiInterface:
\_interface: work@l2_fifo_interface (fifo), file:third_party/cores/taiga/l2_arbiter/l2_arbiter.sv, line:292
|vpiDefName:work@l2_fifo_interface
|vpiName:fifo
|vpiModport:
\_modport: (dequeue)
|vpiName:dequeue
|vpiIODecl:
\_io_decl: (valid)
|vpiName:valid
|vpiDirection:1
|vpiExpr:
\_logic_net: (valid), line:30
|vpiIODecl:
\_io_decl: (data_out)
|vpiName:data_out
|vpiDirection:1
|vpiExpr:
\_logic_net: (data_out), line:29
|vpiIODecl:
\_io_decl: (pop)
|vpiName:pop
|vpiDirection:2
|vpiExpr:
\_logic_net: (pop), line:27
|vpiInterface:
\_interface: work@l2_fifo_interface (fifo), file:third_party/cores/taiga/l2_arbiter/l2_arbiter.sv, line:292
|vpiModport:
\_modport: (enqueue)
|vpiName:enqueue
|vpiIODecl:
\_io_decl: (full)
|vpiName:full
|vpiDirection:1
|vpiExpr:
\_logic_net: (full), line:31
|vpiIODecl:
\_io_decl: (empty)
|vpiName:empty
|vpiDirection:1
|vpiExpr:
\_logic_net: (empty), line:32
|vpiIODecl:
\_io_decl: (data_in)
|vpiName:data_in
|vpiDirection:2
|vpiExpr:
\_logic_net: (data_in), line:28
|vpiIODecl:
\_io_decl: (push)
|vpiName:push
|vpiDirection:2
|vpiExpr:
\_logic_net: (push), line:26
|vpiInterface:
\_interface: work@l2_fifo_interface (fifo), file:third_party/cores/taiga/l2_arbiter/l2_arbiter.sv, line:292
|vpiModport:
\_modport: (structure)
|vpiGenScopeArray:
\_gen_scope_array: (genblk1), line:37, parent:returndata_fifo
|vpiName:genblk1
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk5[1].returndata_fifo.genblk1
|vpiGenScope:
\_gen_scope: , parent:genblk1
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk5[1].returndata_fifo.genblk1
|vpiGenScopeArray:
\_gen_scope_array: (genblk1), line:39
|vpiName:genblk1
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk5[1].returndata_fifo.genblk1.genblk1
|vpiGenScope:
\_gen_scope: , parent:genblk1
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk5[1].returndata_fifo.genblk1.genblk1
|vpiNet:
\_logic_net: (write_index), line:58
|vpiName:write_index
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk5[1].returndata_fifo.genblk1.genblk1.write_index
|vpiNetType:36
|vpiRange:
\_range: , line:58
|vpiLeftRange:
\_constant: , line:58
|vpiConstType:7
|vpiDecompile:18446744073709551615
|vpiSize:32
|INT:-1
|vpiRightRange:
\_constant: , line:58
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (read_index), line:59
|vpiName:read_index
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk5[1].returndata_fifo.genblk1.genblk1.read_index
|vpiNetType:36
|vpiRange:
\_range: , line:59
|vpiLeftRange:
\_constant: , line:59
|vpiConstType:7
|vpiDecompile:18446744073709551615
|vpiSize:32
|INT:-1
|vpiRightRange:
\_constant: , line:59
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiProcess:
\_always: , line:40
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:40
|vpiCondition:
\_operation: , line:40
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:40
|vpiName:clk
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk5[1].returndata_fifo.genblk1.genblk1.clk
|vpiStmt:
\_begin: , line:40
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk5[1].returndata_fifo.genblk1.genblk1
|vpiStmt:
\_if_else: , line:41
|vpiCondition:
\_ref_obj: (rst), line:41
|vpiName:rst
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk5[1].returndata_fifo.genblk1.genblk1.rst
|vpiStmt:
\_assignment: , line:42
|vpiOpType:82
|vpiLhs:
\_ref_obj: (fifo.valid), line:42
|vpiName:fifo.valid
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk5[1].returndata_fifo.genblk1.genblk1.fifo.valid
|vpiRhs:
\_constant: , line:42
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiElseStmt:
\_if_else: , line:43
|vpiCondition:
\_ref_obj: (fifo.push), line:43
|vpiName:fifo.push
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk5[1].returndata_fifo.genblk1.genblk1.fifo.push
|vpiStmt:
\_assignment: , line:44
|vpiOpType:82
|vpiLhs:
\_ref_obj: (fifo.valid), line:44
|vpiName:fifo.valid
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk5[1].returndata_fifo.genblk1.genblk1.fifo.valid
|vpiRhs:
\_constant: , line:44
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiElseStmt:
\_assignment: , line:46
|vpiOpType:82
|vpiLhs:
\_ref_obj: (fifo.valid), line:46
|vpiName:fifo.valid
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk5[1].returndata_fifo.genblk1.genblk1.fifo.valid
|vpiRhs:
\_constant: , line:46
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiProcess:
\_always: , line:49
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:49
|vpiCondition:
\_operation: , line:49
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:49
|vpiName:clk
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk5[1].returndata_fifo.genblk1.genblk1.clk
|vpiStmt:
\_begin: , line:49
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk5[1].returndata_fifo.genblk1.genblk1
|vpiStmt:
\_if_stmt: , line:50
|vpiCondition:
\_ref_obj: (fifo.push), line:50
|vpiName:fifo.push
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk5[1].returndata_fifo.genblk1.genblk1.fifo.push
|vpiStmt:
\_assignment: , line:51
|vpiOpType:82
|vpiLhs:
\_ref_obj: (fifo.data_out), line:51
|vpiName:fifo.data_out
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk5[1].returndata_fifo.genblk1.genblk1.fifo.data_out
|vpiRhs:
\_ref_obj: (fifo.data_in), line:51
|vpiName:fifo.data_in
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk5[1].returndata_fifo.genblk1.genblk1.fifo.data_in
|vpiProcess:
\_always: , line:67
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:67
|vpiCondition:
\_operation: , line:67
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:67
|vpiName:clk
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk5[1].returndata_fifo.genblk1.genblk1.clk
|vpiStmt:
\_begin: , line:67
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk5[1].returndata_fifo.genblk1.genblk1
|vpiStmt:
\_if_else: , line:68
|vpiCondition:
\_ref_obj: (rst), line:68
|vpiName:rst
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk5[1].returndata_fifo.genblk1.genblk1.rst
|vpiStmt:
\_begin: , line:68
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk5[1].returndata_fifo.genblk1.genblk1
|vpiStmt:
\_assignment: , line:69
|vpiOpType:82
|vpiLhs:
\_ref_obj: (read_index), line:69
|vpiName:read_index
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk5[1].returndata_fifo.genblk1.genblk1.read_index
|vpiRhs:
\_constant: , line:69
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiStmt:
\_assignment: , line:70
|vpiOpType:82
|vpiLhs:
\_ref_obj: (write_index), line:70
|vpiName:write_index
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk5[1].returndata_fifo.genblk1.genblk1.write_index
|vpiRhs:
\_constant: , line:70
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiElseStmt:
\_begin: , line:72
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk5[1].returndata_fifo.genblk1.genblk1
|vpiStmt:
\_assignment: , line:73
|vpiOpType:82
|vpiLhs:
\_ref_obj: (read_index), line:73
|vpiName:read_index
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk5[1].returndata_fifo.genblk1.genblk1.read_index
|vpiRhs:
\_operation: , line:73
|vpiOpType:24
|vpiOperand:
\_ref_obj: (read_index), line:73
|vpiName:read_index
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk5[1].returndata_fifo.genblk1.genblk1.read_index
|vpiOperand:
\_ref_obj: (fifo.pop), line:73
|vpiName:fifo.pop
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk5[1].returndata_fifo.genblk1.genblk1.fifo.pop
|vpiStmt:
\_assignment: , line:74
|vpiOpType:82
|vpiLhs:
\_ref_obj: (write_index), line:74
|vpiName:write_index
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk5[1].returndata_fifo.genblk1.genblk1.write_index
|vpiRhs:
\_operation: , line:74
|vpiOpType:24
|vpiOperand:
\_ref_obj: (write_index), line:74
|vpiName:write_index
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk5[1].returndata_fifo.genblk1.genblk1.write_index
|vpiOperand:
\_ref_obj: (fifo.push), line:74
|vpiName:fifo.push
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk5[1].returndata_fifo.genblk1.genblk1.fifo.push
|vpiProcess:
\_always: , line:81
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:81
|vpiCondition:
\_operation: , line:81
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:81
|vpiName:clk
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk5[1].returndata_fifo.genblk1.genblk1.clk
|vpiStmt:
\_begin: , line:81
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk5[1].returndata_fifo.genblk1.genblk1
|vpiStmt:
\_if_stmt: , line:82
|vpiCondition:
\_ref_obj: (fifo.push), line:82
|vpiName:fifo.push
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk5[1].returndata_fifo.genblk1.genblk1.fifo.push
|vpiStmt:
\_assignment: , line:83
|vpiOpType:82
|vpiLhs:
\_bit_select: (lut_ram), line:83
|vpiName:lut_ram
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk5[1].returndata_fifo.genblk1.genblk1.lut_ram
|vpiIndex:
\_ref_obj: (write_index), line:83
|vpiName:write_index
|vpiRhs:
\_ref_obj: (fifo.data_in), line:83
|vpiName:fifo.data_in
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk5[1].returndata_fifo.genblk1.genblk1.fifo.data_in
|vpiProcess:
\_always: , line:86
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , line:86
|vpiCondition:
\_operation: , line:86
|vpiOpType:39
|vpiOperand:
\_ref_obj: (clk), line:86
|vpiName:clk
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk5[1].returndata_fifo.genblk1.genblk1.clk
|vpiStmt:
\_begin: , line:86
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk5[1].returndata_fifo.genblk1.genblk1
|vpiStmt:
\_if_else: , line:87
|vpiCondition:
\_ref_obj: (rst), line:87
|vpiName:rst
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk5[1].returndata_fifo.genblk1.genblk1.rst
|vpiStmt:
\_begin: , line:87
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk5[1].returndata_fifo.genblk1.genblk1
|vpiStmt:
\_assignment: , line:88
|vpiOpType:82
|vpiLhs:
\_bit_select: (count_v), line:88
|vpiName:count_v
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk5[1].returndata_fifo.genblk1.genblk1.count_v
|vpiIndex:
\_constant: , line:88
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiRhs:
\_constant: , line:88
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiStmt:
\_for_stmt: , line:89
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk5[1].returndata_fifo.genblk1.genblk1
|vpiCondition:
\_operation: , line:89
|vpiOpType:21
|vpiOperand:
\_ref_obj: (i), line:89
|vpiName:i
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk5[1].returndata_fifo.genblk1.genblk1.i
|vpiOperand:
\_ref_obj: (FIFO_DEPTH), line:89
|vpiName:FIFO_DEPTH
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk5[1].returndata_fifo.genblk1.genblk1.FIFO_DEPTH
|vpiForInitStmt:
\_assign_stmt:
|vpiRhs:
\_constant: , line:89
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiLhs:
\_int_var: (i), line:89
|vpiName:i
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk5[1].returndata_fifo.genblk1.genblk1.i
|vpiForIncStmt:
\_operation: , line:89
|vpiOpType:62
|vpiOperand:
\_ref_obj: (i), line:89
|vpiName:i
|vpiStmt:
\_assignment: , line:89
|vpiOpType:82
|vpiLhs:
\_bit_select: (count_v), line:89
|vpiName:count_v
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk5[1].returndata_fifo.genblk1.genblk1.count_v
|vpiIndex:
\_ref_obj: (i), line:89
|vpiName:i
|vpiRhs:
\_constant: , line:89
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiElseStmt:
\_if_else: , line:91
|vpiCondition:
\_operation: , line:91
|vpiOpType:28
|vpiOperand:
\_ref_obj: (fifo.push), line:91
|vpiName:fifo.push
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk5[1].returndata_fifo.genblk1.genblk1.fifo.push
|vpiOperand:
\_operation: , line:91
|vpiOpType:4
|vpiOperand:
\_ref_obj: (fifo.pop), line:91
|vpiName:fifo.pop
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk5[1].returndata_fifo.genblk1.genblk1.fifo.pop
|vpiStmt:
\_assignment: , line:92
|vpiOpType:82
|vpiLhs:
\_ref_obj: (count_v), line:92
|vpiName:count_v
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk5[1].returndata_fifo.genblk1.genblk1.count_v
|vpiRhs:
\_operation: , line:92
|vpiOpType:33
|vpiOperand:
\_part_select: , line:92, parent:count_v
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (count_v)
|vpiLeftRange:
\_operation: , line:92
|vpiOpType:11
|vpiOperand:
\_ref_obj: (FIFO_DEPTH), line:92
|vpiName:FIFO_DEPTH
|vpiOperand:
\_constant: , line:92
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:92
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiOperand:
\_constant: , line:92
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiElseStmt:
\_if_stmt: , line:93
|vpiCondition:
\_operation: , line:93
|vpiOpType:28
|vpiOperand:
\_operation: , line:93
|vpiOpType:4
|vpiOperand:
\_ref_obj: (fifo.push), line:93
|vpiName:fifo.push
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk5[1].returndata_fifo.genblk1.genblk1.fifo.push
|vpiOperand:
\_ref_obj: (fifo.pop), line:93
|vpiName:fifo.pop
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk5[1].returndata_fifo.genblk1.genblk1.fifo.pop
|vpiStmt:
\_assignment: , line:94
|vpiOpType:82
|vpiLhs:
\_ref_obj: (count_v), line:94
|vpiName:count_v
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk5[1].returndata_fifo.genblk1.genblk1.count_v
|vpiRhs:
\_operation: , line:94
|vpiOpType:33
|vpiOperand:
\_constant: , line:94
|vpiConstType:3
|vpiDecompile:'b0
|vpiSize:1
|BIN:0
|vpiOperand:
\_part_select: , line:94, parent:count_v
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (count_v)
|vpiLeftRange:
\_ref_obj: (FIFO_DEPTH), line:94
|vpiName:FIFO_DEPTH
|vpiRightRange:
\_constant: , line:94
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiArrayNet:
\_array_net: (lut_ram), line:56
|vpiName:lut_ram
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk5[1].returndata_fifo.genblk1.genblk1.lut_ram
|vpiSize:1
|vpiNet:
\_logic_net: , parent:lut_ram
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk5[1].returndata_fifo.genblk1.genblk1.lut_ram
|vpiNetType:36
|vpiRange:
\_range: , line:56
|vpiLeftRange:
\_constant: , line:56
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:56
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiRange:
\_range: , line:56
|vpiLeftRange:
\_constant: , line:56
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiRightRange:
\_constant: , line:56
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiArrayNet:
\_array_net: (count_v), line:61
|vpiName:count_v
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk5[1].returndata_fifo.genblk1.genblk1.count_v
|vpiSize:2
|vpiNet:
\_logic_net: , parent:count_v
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk5[1].returndata_fifo.genblk1.genblk1.count_v
|vpiNetType:36
|vpiRange:
\_range: , line:61
|vpiLeftRange:
\_constant: , line:61
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:61
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiContAssign:
\_cont_assign: , line:65
|vpiRhs:
\_bit_select: (lut_ram), line:65
|vpiName:lut_ram
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk5[1].returndata_fifo.genblk1.genblk1.lut_ram
|vpiIndex:
\_ref_obj: (read_index), line:65
|vpiName:read_index
|vpiLhs:
\_ref_obj: (fifo.data_out), line:65
|vpiName:fifo.data_out
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk5[1].returndata_fifo.genblk1.genblk1.fifo.data_out
|vpiContAssign:
\_cont_assign: , line:78
|vpiRhs:
\_bit_select: (count_v), line:78
|vpiName:count_v
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk5[1].returndata_fifo.genblk1.genblk1.count_v
|vpiIndex:
\_ref_obj: (FIFO_DEPTH), line:78
|vpiName:FIFO_DEPTH
|vpiLhs:
\_ref_obj: (fifo.full), line:78
|vpiName:fifo.full
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk5[1].returndata_fifo.genblk1.genblk1.fifo.full
|vpiContAssign:
\_cont_assign: , line:79
|vpiRhs:
\_operation: , line:79
|vpiOpType:4
|vpiOperand:
\_bit_select: (count_v), line:79
|vpiName:count_v
|vpiIndex:
\_constant: , line:79
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiLhs:
\_ref_obj: (fifo.valid), line:79
|vpiName:fifo.valid
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk5[1].returndata_fifo.genblk1.genblk1.fifo.valid
|vpiNet:
\_logic_net: (clk), line:25, parent:returndata_fifo
|vpiNet:
\_logic_net: (wr_clk), line:26, parent:returndata_fifo
|vpiNet:
\_logic_net: (rd_clk), line:27, parent:returndata_fifo
|vpiNet:
\_logic_net: (rst), line:29, parent:returndata_fifo
|vpiNet:
\_logic_net: (fifo), line:30, parent:returndata_fifo
|vpiName:fifo
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.genblk5[1].returndata_fifo.fifo
|vpiParameter:
\_parameter: (ASYNC), line:23
|vpiName:ASYNC
|INT:0
|vpiParameter:
\_parameter: (DATA_WIDTH), line:292
|vpiName:DATA_WIDTH
|INT:32
|vpiParameter:
\_parameter: (FIFO_DEPTH), line:292
|vpiName:FIFO_DEPTH
|INT:1
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (L2_DATA_ATTRIBUTES_FIFO_DEPTH), line:41
|vpiName:L2_DATA_ATTRIBUTES_FIFO_DEPTH
|INT:16
|vpiParameter:
\_parameter: (L2_ID_W), line:46
|vpiName:L2_ID_W
|INT:3
|vpiParameter:
\_parameter: (L2_INPUT_FIFO_DEPTHS), line:34
|vpiName:L2_INPUT_FIFO_DEPTHS
|INT:4
|vpiParameter:
\_parameter: (L2_INVALIDATION_FIFO_DEPTHS), line:35
|vpiName:L2_INVALIDATION_FIFO_DEPTHS
|INT:4
|vpiParameter:
\_parameter: (L2_MEM_ADDR_FIFO_DEPTH), line:39
|vpiName:L2_MEM_ADDR_FIFO_DEPTH
|INT:8
|vpiParameter:
\_parameter: (L2_NUM_PORTS), line:26
|vpiName:L2_NUM_PORTS
|INT:2
|vpiParameter:
\_parameter: (L2_READ_RETURN_FIFO_DEPTHS), line:36
|vpiName:L2_READ_RETURN_FIFO_DEPTHS
|INT:1
|vpiParameter:
\_parameter: (L2_SUB_ID_W), line:27
|vpiName:L2_SUB_ID_W
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiParameter:
\_parameter: (i), line:283
|vpiName:i
|INT:1
|vpiNet:
\_logic_net: (clk), line:27, parent:l2_arb
|vpiNet:
\_logic_net: (rst), line:28, parent:l2_arb
|vpiNet:
\_logic_net: (advance), line:53, parent:l2_arb
|vpiName:advance
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.advance
|vpiNetType:36
|vpiNet:
\_logic_net: (reserv_valid), line:57, parent:l2_arb
|vpiName:reserv_valid
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.reserv_valid
|vpiNetType:36
|vpiNet:
\_logic_net: (reserv_lr), line:58, parent:l2_arb
|vpiName:reserv_lr
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.reserv_lr
|vpiNetType:36
|vpiNet:
\_logic_net: (reserv_sc), line:59, parent:l2_arb
|vpiName:reserv_sc
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.reserv_sc
|vpiNetType:36
|vpiNet:
\_logic_net: (reserv_store), line:60, parent:l2_arb
|vpiName:reserv_store
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.reserv_store
|vpiNetType:36
|vpiNet:
\_logic_net: (reserv_id), line:63, parent:l2_arb
|vpiName:reserv_id
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.reserv_id
|vpiNetType:36
|vpiRange:
\_range: , line:63
|vpiLeftRange:
\_constant: , line:63
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiRightRange:
\_constant: , line:63
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (reserv_id_v), line:64, parent:l2_arb
|vpiName:reserv_id_v
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.reserv_id_v
|vpiNetType:36
|vpiRange:
\_range: , line:64
|vpiLeftRange:
\_constant: , line:64
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:64
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (write_done), line:66, parent:l2_arb
|vpiName:write_done
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.write_done
|vpiNetType:36
|vpiNet:
\_logic_net: (burst_count), line:67, parent:l2_arb
|vpiName:burst_count
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.burst_count
|vpiNetType:36
|vpiRange:
\_range: , line:67
|vpiLeftRange:
\_constant: , line:67
|vpiConstType:7
|vpiDecompile:4
|vpiSize:32
|INT:4
|vpiRightRange:
\_constant: , line:67
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (return_push), line:75, parent:l2_arb
|vpiName:return_push
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.return_push
|vpiNetType:36
|vpiRange:
\_range: , line:75
|vpiLeftRange:
\_constant: , line:75
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:75
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (wr_clk), line:77, parent:l2_arb
|vpiNet:
\_logic_net: (rd_clk), line:77, parent:l2_arb
|vpiNet:
\_logic_net: (request), line:30, parent:l2_arb
|vpiName:request
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.request
|vpiNet:
\_logic_net: (mem), line:31, parent:l2_arb
|vpiName:mem
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.mem
|vpiArrayNet:
\_array_net: (input_data), line:71, parent:l2_arb
|vpiName:input_data
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.input_data
|vpiSize:2
|vpiNet:
\_logic_net: , parent:input_data
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.input_data
|vpiNetType:36
|vpiRange:
\_range: , line:71
|vpiLeftRange:
\_constant: , line:71
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:71
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiRange:
\_range: , line:71
|vpiLeftRange:
\_constant: , line:71
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:71
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiVariables:
\_struct_var: (mem_addr_fifo_data_out), line:50, parent:l2_arb
|vpiName:mem_addr_fifo_data_out
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.mem_addr_fifo_data_out
|vpiTypespec:
\_struct_typespec: (l2_mem_request_t), line:58
|vpiVariables:
\_array_var: (requests_in), parent:l2_arb
|vpiArrayType:1
|vpiName:requests_in
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.requests_in
|vpiRandType:1
|vpiVisibility:1
|vpiSize:2
|vpiReg:
\_struct_var: , line:51, parent:requests_in
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.requests_in
|vpiTypespec:
\_struct_typespec: (l2_request_t), line:49
|vpiRange:
\_range: , line:51
|vpiLeftRange:
\_constant: , line:51
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:51
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiVariables:
\_struct_var: (arb_request), line:54, parent:l2_arb
|vpiName:arb_request
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.arb_request
|vpiTypespec:
\_struct_typespec: (l2_request_t), line:49
|vpiVariables:
\_struct_var: (mem_request), line:55, parent:l2_arb
|vpiName:mem_request
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.mem_request
|vpiTypespec:
\_struct_typespec: (l2_mem_request_t), line:58
|vpiVariables:
\_array_var: (requests), parent:l2_arb
|vpiArrayType:1
|vpiName:requests
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.requests
|vpiRandType:1
|vpiVisibility:1
|vpiSize:2
|vpiReg:
\_struct_var: , line:61, parent:requests
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.requests
|vpiTypespec:
\_struct_typespec: (l2_request_t), line:49
|vpiRange:
\_range: , line:61
|vpiLeftRange:
\_constant: , line:61
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:61
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiVariables:
\_struct_var: (reserv_request), line:62, parent:l2_arb
|vpiName:reserv_request
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.reserv_request
|vpiTypespec:
\_struct_typespec: (l2_request_t), line:49
|vpiVariables:
\_struct_var: (new_attr), line:68, parent:l2_arb
|vpiName:new_attr
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.new_attr
|vpiTypespec:
\_struct_typespec: (l2_data_attributes_t), line:68
|vpiVariables:
\_struct_var: (current_attr), line:69, parent:l2_arb
|vpiName:current_attr
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.current_attr
|vpiTypespec:
\_struct_typespec: (l2_data_attributes_t), line:68
|vpiVariables:
\_struct_var: (mem_return_data), line:73, parent:l2_arb
|vpiName:mem_return_data
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.mem_return_data
|vpiTypespec:
\_struct_typespec: (l2_mem_return_data_t), line:75
|vpiVariables:
\_array_var: (return_data), parent:l2_arb
|vpiArrayType:1
|vpiName:return_data
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.return_data
|vpiRandType:1
|vpiVisibility:1
|vpiSize:2
|vpiReg:
\_struct_var: , line:74, parent:return_data
|vpiFullName:work@taiga_wrapper.genblk1.l2_arb.return_data
|vpiTypespec:
\_struct_typespec: (l2_return_data_t), line:81
|vpiRange:
\_range: , line:74
|vpiLeftRange:
\_constant: , line:74
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:74
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (L2_DATA_ATTRIBUTES_FIFO_DEPTH), line:41
|vpiName:L2_DATA_ATTRIBUTES_FIFO_DEPTH
|INT:16
|vpiParameter:
\_parameter: (L2_ID_W), line:46
|vpiName:L2_ID_W
|INT:3
|vpiParameter:
\_parameter: (L2_INPUT_FIFO_DEPTHS), line:34
|vpiName:L2_INPUT_FIFO_DEPTHS
|INT:4
|vpiParameter:
\_parameter: (L2_INVALIDATION_FIFO_DEPTHS), line:35
|vpiName:L2_INVALIDATION_FIFO_DEPTHS
|INT:4
|vpiParameter:
\_parameter: (L2_MEM_ADDR_FIFO_DEPTH), line:39
|vpiName:L2_MEM_ADDR_FIFO_DEPTH
|INT:8
|vpiParameter:
\_parameter: (L2_NUM_PORTS), line:26
|vpiName:L2_NUM_PORTS
|INT:2
|vpiParameter:
\_parameter: (L2_READ_RETURN_FIFO_DEPTHS), line:36
|vpiName:L2_READ_RETURN_FIFO_DEPTHS
|INT:1
|vpiParameter:
\_parameter: (L2_SUB_ID_W), line:27
|vpiName:L2_SUB_ID_W
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiModule:
\_module: work@axi_to_arb (l2_to_mem), file:third_party/cores/taiga/examples/zedboard/taiga_wrapper.sv, line:240
|vpiDefName:work@axi_to_arb
|vpiName:l2_to_mem
|vpiFullName:work@taiga_wrapper.genblk1.l2_to_mem
|vpiPort:
\_port: (clk), line:30, parent:l2_to_mem
|vpiName:clk
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (clk), line:240
|vpiName:clk
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (clk), line:30, parent:l2_to_mem
|vpiName:clk
|vpiFullName:work@taiga_wrapper.genblk1.l2_to_mem.clk
|vpiNetType:36
|vpiPort:
\_port: (rst), line:31, parent:l2_to_mem
|vpiName:rst
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (rst), line:240
|vpiName:rst
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (rst), line:31, parent:l2_to_mem
|vpiName:rst
|vpiFullName:work@taiga_wrapper.genblk1.l2_to_mem.rst
|vpiNetType:36
|vpiPort:
\_port: (axi_arready), line:34, parent:l2_to_mem
|vpiName:axi_arready
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (axi_arready), line:240
|vpiName:axi_arready
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (axi_arready), line:34, parent:l2_to_mem
|vpiName:axi_arready
|vpiFullName:work@taiga_wrapper.genblk1.l2_to_mem.axi_arready
|vpiNetType:36
|vpiPort:
\_port: (axi_arvalid), line:35, parent:l2_to_mem
|vpiName:axi_arvalid
|vpiDirection:2
|vpiHighConn:
\_ref_obj: (axi_arvalid), line:240
|vpiName:axi_arvalid
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (axi_arvalid), line:35, parent:l2_to_mem
|vpiName:axi_arvalid
|vpiFullName:work@taiga_wrapper.genblk1.l2_to_mem.axi_arvalid
|vpiNetType:36
|vpiPort:
\_port: (axi_araddr), line:36, parent:l2_to_mem
|vpiName:axi_araddr
|vpiDirection:2
|vpiHighConn:
\_ref_obj: (axi_araddr), line:240
|vpiName:axi_araddr
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (axi_araddr), line:36, parent:l2_to_mem
|vpiName:axi_araddr
|vpiFullName:work@taiga_wrapper.genblk1.l2_to_mem.axi_araddr
|vpiNetType:36
|vpiRange:
\_range: , line:36
|vpiLeftRange:
\_constant: , line:36
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:36
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiPort:
\_port: (axi_arlen), line:37, parent:l2_to_mem
|vpiName:axi_arlen
|vpiDirection:2
|vpiHighConn:
\_ref_obj: (axi_arlen), line:240
|vpiName:axi_arlen
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (axi_arlen), line:37, parent:l2_to_mem
|vpiName:axi_arlen
|vpiFullName:work@taiga_wrapper.genblk1.l2_to_mem.axi_arlen
|vpiNetType:36
|vpiRange:
\_range: , line:37
|vpiLeftRange:
\_constant: , line:37
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiRightRange:
\_constant: , line:37
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiPort:
\_port: (axi_arsize), line:38, parent:l2_to_mem
|vpiName:axi_arsize
|vpiDirection:2
|vpiHighConn:
\_ref_obj: (axi_arsize), line:240
|vpiName:axi_arsize
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (axi_arsize), line:38, parent:l2_to_mem
|vpiName:axi_arsize
|vpiFullName:work@taiga_wrapper.genblk1.l2_to_mem.axi_arsize
|vpiNetType:36
|vpiRange:
\_range: , line:38
|vpiLeftRange:
\_constant: , line:38
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiRightRange:
\_constant: , line:38
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiPort:
\_port: (axi_arburst), line:39, parent:l2_to_mem
|vpiName:axi_arburst
|vpiDirection:2
|vpiHighConn:
\_ref_obj: (axi_arburst), line:240
|vpiName:axi_arburst
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (axi_arburst), line:39, parent:l2_to_mem
|vpiName:axi_arburst
|vpiFullName:work@taiga_wrapper.genblk1.l2_to_mem.axi_arburst
|vpiNetType:36
|vpiRange:
\_range: , line:39
|vpiLeftRange:
\_constant: , line:39
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:39
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiPort:
\_port: (axi_arprot), line:40, parent:l2_to_mem
|vpiName:axi_arprot
|vpiDirection:2
|vpiHighConn:
\_ref_obj: (axi_arprot), line:240
|vpiName:axi_arprot
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (axi_arprot), line:40, parent:l2_to_mem
|vpiName:axi_arprot
|vpiFullName:work@taiga_wrapper.genblk1.l2_to_mem.axi_arprot
|vpiNetType:36
|vpiRange:
\_range: , line:40
|vpiLeftRange:
\_constant: , line:40
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiRightRange:
\_constant: , line:40
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiPort:
\_port: (axi_arcache), line:41, parent:l2_to_mem
|vpiName:axi_arcache
|vpiDirection:2
|vpiHighConn:
\_ref_obj: (axi_arcache), line:240
|vpiName:axi_arcache
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (axi_arcache), line:41, parent:l2_to_mem
|vpiName:axi_arcache
|vpiFullName:work@taiga_wrapper.genblk1.l2_to_mem.axi_arcache
|vpiNetType:36
|vpiRange:
\_range: , line:41
|vpiLeftRange:
\_constant: , line:41
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiRightRange:
\_constant: , line:41
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiPort:
\_port: (axi_arid), line:42, parent:l2_to_mem
|vpiName:axi_arid
|vpiDirection:2
|vpiHighConn:
\_ref_obj: (axi_arid), line:240
|vpiName:axi_arid
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (axi_arid), line:42, parent:l2_to_mem
|vpiName:axi_arid
|vpiFullName:work@taiga_wrapper.genblk1.l2_to_mem.axi_arid
|vpiNetType:36
|vpiRange:
\_range: , line:42
|vpiLeftRange:
\_constant: , line:42
|vpiConstType:7
|vpiDecompile:4
|vpiSize:32
|INT:4
|vpiRightRange:
\_constant: , line:42
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiPort:
\_port: (axi_rready), line:45, parent:l2_to_mem
|vpiName:axi_rready
|vpiDirection:2
|vpiHighConn:
\_ref_obj: (axi_rready), line:240
|vpiName:axi_rready
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (axi_rready), line:45, parent:l2_to_mem
|vpiName:axi_rready
|vpiFullName:work@taiga_wrapper.genblk1.l2_to_mem.axi_rready
|vpiNetType:36
|vpiPort:
\_port: (axi_rvalid), line:46, parent:l2_to_mem
|vpiName:axi_rvalid
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (axi_rvalid), line:240
|vpiName:axi_rvalid
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (axi_rvalid), line:46, parent:l2_to_mem
|vpiName:axi_rvalid
|vpiFullName:work@taiga_wrapper.genblk1.l2_to_mem.axi_rvalid
|vpiNetType:36
|vpiPort:
\_port: (axi_rdata), line:47, parent:l2_to_mem
|vpiName:axi_rdata
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (axi_rdata), line:240
|vpiName:axi_rdata
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (axi_rdata), line:47, parent:l2_to_mem
|vpiName:axi_rdata
|vpiFullName:work@taiga_wrapper.genblk1.l2_to_mem.axi_rdata
|vpiNetType:36
|vpiRange:
\_range: , line:47
|vpiLeftRange:
\_constant: , line:47
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:47
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiPort:
\_port: (axi_rresp), line:48, parent:l2_to_mem
|vpiName:axi_rresp
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (axi_rresp), line:240
|vpiName:axi_rresp
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (axi_rresp), line:48, parent:l2_to_mem
|vpiName:axi_rresp
|vpiFullName:work@taiga_wrapper.genblk1.l2_to_mem.axi_rresp
|vpiNetType:36
|vpiRange:
\_range: , line:48
|vpiLeftRange:
\_constant: , line:48
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:48
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiPort:
\_port: (axi_rlast), line:49, parent:l2_to_mem
|vpiName:axi_rlast
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (axi_rlast), line:240
|vpiName:axi_rlast
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (axi_rlast), line:49, parent:l2_to_mem
|vpiName:axi_rlast
|vpiFullName:work@taiga_wrapper.genblk1.l2_to_mem.axi_rlast
|vpiNetType:36
|vpiPort:
\_port: (axi_rid), line:50, parent:l2_to_mem
|vpiName:axi_rid
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (axi_rid), line:240
|vpiName:axi_rid
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (axi_rid), line:50, parent:l2_to_mem
|vpiName:axi_rid
|vpiFullName:work@taiga_wrapper.genblk1.l2_to_mem.axi_rid
|vpiNetType:36
|vpiRange:
\_range: , line:50
|vpiLeftRange:
\_constant: , line:50
|vpiConstType:7
|vpiDecompile:4
|vpiSize:32
|INT:4
|vpiRightRange:
\_constant: , line:50
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiPort:
\_port: (axi_awready), line:53, parent:l2_to_mem
|vpiName:axi_awready
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (axi_awready), line:240
|vpiName:axi_awready
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (axi_awready), line:53, parent:l2_to_mem
|vpiName:axi_awready
|vpiFullName:work@taiga_wrapper.genblk1.l2_to_mem.axi_awready
|vpiNetType:36
|vpiPort:
\_port: (axi_awvalid), line:54, parent:l2_to_mem
|vpiName:axi_awvalid
|vpiDirection:2
|vpiHighConn:
\_ref_obj: (axi_awvalid), line:240
|vpiName:axi_awvalid
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (axi_awvalid), line:54, parent:l2_to_mem
|vpiName:axi_awvalid
|vpiFullName:work@taiga_wrapper.genblk1.l2_to_mem.axi_awvalid
|vpiNetType:36
|vpiPort:
\_port: (axi_awaddr), line:55, parent:l2_to_mem
|vpiName:axi_awaddr
|vpiDirection:2
|vpiHighConn:
\_ref_obj: (axi_awaddr), line:240
|vpiName:axi_awaddr
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (axi_awaddr), line:55, parent:l2_to_mem
|vpiName:axi_awaddr
|vpiFullName:work@taiga_wrapper.genblk1.l2_to_mem.axi_awaddr
|vpiNetType:36
|vpiRange:
\_range: , line:55
|vpiLeftRange:
\_constant: , line:55
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:55
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiPort:
\_port: (axi_awlen), line:56, parent:l2_to_mem
|vpiName:axi_awlen
|vpiDirection:2
|vpiHighConn:
\_ref_obj: (axi_awlen), line:240
|vpiName:axi_awlen
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (axi_awlen), line:56, parent:l2_to_mem
|vpiName:axi_awlen
|vpiFullName:work@taiga_wrapper.genblk1.l2_to_mem.axi_awlen
|vpiNetType:36
|vpiRange:
\_range: , line:56
|vpiLeftRange:
\_constant: , line:56
|vpiConstType:7
|vpiDecompile:7
|vpiSize:32
|INT:7
|vpiRightRange:
\_constant: , line:56
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiPort:
\_port: (axi_awsize), line:57, parent:l2_to_mem
|vpiName:axi_awsize
|vpiDirection:2
|vpiHighConn:
\_ref_obj: (axi_awsize), line:240
|vpiName:axi_awsize
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (axi_awsize), line:57, parent:l2_to_mem
|vpiName:axi_awsize
|vpiFullName:work@taiga_wrapper.genblk1.l2_to_mem.axi_awsize
|vpiNetType:36
|vpiRange:
\_range: , line:57
|vpiLeftRange:
\_constant: , line:57
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiRightRange:
\_constant: , line:57
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiPort:
\_port: (axi_awburst), line:58, parent:l2_to_mem
|vpiName:axi_awburst
|vpiDirection:2
|vpiHighConn:
\_ref_obj: (axi_awburst), line:240
|vpiName:axi_awburst
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (axi_awburst), line:58, parent:l2_to_mem
|vpiName:axi_awburst
|vpiFullName:work@taiga_wrapper.genblk1.l2_to_mem.axi_awburst
|vpiNetType:36
|vpiRange:
\_range: , line:58
|vpiLeftRange:
\_constant: , line:58
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:58
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiPort:
\_port: (axi_awcache), line:60, parent:l2_to_mem
|vpiName:axi_awcache
|vpiDirection:2
|vpiHighConn:
\_ref_obj: (axi_awcache), line:240
|vpiName:axi_awcache
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (axi_awcache), line:60, parent:l2_to_mem
|vpiName:axi_awcache
|vpiFullName:work@taiga_wrapper.genblk1.l2_to_mem.axi_awcache
|vpiNetType:36
|vpiRange:
\_range: , line:60
|vpiLeftRange:
\_constant: , line:60
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiRightRange:
\_constant: , line:60
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiPort:
\_port: (axi_awprot), line:61, parent:l2_to_mem
|vpiName:axi_awprot
|vpiDirection:2
|vpiHighConn:
\_ref_obj: (axi_awprot), line:240
|vpiName:axi_awprot
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (axi_awprot), line:61, parent:l2_to_mem
|vpiName:axi_awprot
|vpiFullName:work@taiga_wrapper.genblk1.l2_to_mem.axi_awprot
|vpiNetType:36
|vpiRange:
\_range: , line:61
|vpiLeftRange:
\_constant: , line:61
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiRightRange:
\_constant: , line:61
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiPort:
\_port: (axi_wready), line:64, parent:l2_to_mem
|vpiName:axi_wready
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (axi_wready), line:240
|vpiName:axi_wready
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (axi_wready), line:64, parent:l2_to_mem
|vpiName:axi_wready
|vpiFullName:work@taiga_wrapper.genblk1.l2_to_mem.axi_wready
|vpiNetType:36
|vpiPort:
\_port: (axi_wvalid), line:65, parent:l2_to_mem
|vpiName:axi_wvalid
|vpiDirection:2
|vpiHighConn:
\_ref_obj: (axi_wvalid), line:240
|vpiName:axi_wvalid
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (axi_wvalid), line:65, parent:l2_to_mem
|vpiName:axi_wvalid
|vpiFullName:work@taiga_wrapper.genblk1.l2_to_mem.axi_wvalid
|vpiNetType:36
|vpiPort:
\_port: (axi_wdata), line:66, parent:l2_to_mem
|vpiName:axi_wdata
|vpiDirection:2
|vpiHighConn:
\_ref_obj: (axi_wdata), line:240
|vpiName:axi_wdata
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (axi_wdata), line:66, parent:l2_to_mem
|vpiName:axi_wdata
|vpiFullName:work@taiga_wrapper.genblk1.l2_to_mem.axi_wdata
|vpiNetType:36
|vpiRange:
\_range: , line:66
|vpiLeftRange:
\_constant: , line:66
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:66
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiPort:
\_port: (axi_wstrb), line:67, parent:l2_to_mem
|vpiName:axi_wstrb
|vpiDirection:2
|vpiHighConn:
\_ref_obj: (axi_wstrb), line:240
|vpiName:axi_wstrb
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (axi_wstrb), line:67, parent:l2_to_mem
|vpiName:axi_wstrb
|vpiFullName:work@taiga_wrapper.genblk1.l2_to_mem.axi_wstrb
|vpiNetType:36
|vpiRange:
\_range: , line:67
|vpiLeftRange:
\_constant: , line:67
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiRightRange:
\_constant: , line:67
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiPort:
\_port: (axi_wlast), line:68, parent:l2_to_mem
|vpiName:axi_wlast
|vpiDirection:2
|vpiHighConn:
\_ref_obj: (axi_wlast), line:240
|vpiName:axi_wlast
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (axi_wlast), line:68, parent:l2_to_mem
|vpiName:axi_wlast
|vpiFullName:work@taiga_wrapper.genblk1.l2_to_mem.axi_wlast
|vpiNetType:36
|vpiPort:
\_port: (axi_bready), line:71, parent:l2_to_mem
|vpiName:axi_bready
|vpiDirection:2
|vpiHighConn:
\_ref_obj: (axi_bready), line:240
|vpiName:axi_bready
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (axi_bready), line:71, parent:l2_to_mem
|vpiName:axi_bready
|vpiFullName:work@taiga_wrapper.genblk1.l2_to_mem.axi_bready
|vpiNetType:36
|vpiPort:
\_port: (axi_bvalid), line:72, parent:l2_to_mem
|vpiName:axi_bvalid
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (axi_bvalid), line:240
|vpiName:axi_bvalid
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (axi_bvalid), line:72, parent:l2_to_mem
|vpiName:axi_bvalid
|vpiFullName:work@taiga_wrapper.genblk1.l2_to_mem.axi_bvalid
|vpiNetType:36
|vpiPort:
\_port: (axi_bresp), line:73, parent:l2_to_mem
|vpiName:axi_bresp
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (axi_bresp), line:240
|vpiName:axi_bresp
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (axi_bresp), line:73, parent:l2_to_mem
|vpiName:axi_bresp
|vpiFullName:work@taiga_wrapper.genblk1.l2_to_mem.axi_bresp
|vpiNetType:36
|vpiRange:
\_range: , line:73
|vpiLeftRange:
\_constant: , line:73
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:73
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiPort:
\_port: (l2), line:78, parent:l2_to_mem
|vpiName:l2
|vpiDirection:5
|vpiHighConn:
\_ref_obj: (l2), line:240
|vpiName:l2
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_modport: (slave)
|vpiName:slave
|vpiIODecl:
\_io_decl: (addr)
|vpiName:addr
|vpiDirection:1
|vpiExpr:
\_logic_net: (addr), line:70
|vpiName:addr
|vpiNetType:36
|vpiRange:
\_range: , line:70
|vpiLeftRange:
\_constant: , line:70
|vpiConstType:7
|vpiDecompile:29
|vpiSize:32
|INT:29
|vpiRightRange:
\_constant: , line:70
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (be)
|vpiName:be
|vpiDirection:1
|vpiExpr:
\_logic_net: (be), line:71
|vpiName:be
|vpiNetType:36
|vpiRange:
\_range: , line:71
|vpiLeftRange:
\_constant: , line:71
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiRightRange:
\_constant: , line:71
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (rnw)
|vpiName:rnw
|vpiDirection:1
|vpiExpr:
\_logic_net: (rnw), line:72
|vpiName:rnw
|vpiNetType:36
|vpiIODecl:
\_io_decl: (is_amo)
|vpiName:is_amo
|vpiDirection:1
|vpiExpr:
\_logic_net: (is_amo), line:73
|vpiName:is_amo
|vpiNetType:36
|vpiIODecl:
\_io_decl: (amo_type_or_burst_size)
|vpiName:amo_type_or_burst_size
|vpiDirection:1
|vpiExpr:
\_logic_net: (amo_type_or_burst_size), line:74
|vpiName:amo_type_or_burst_size
|vpiNetType:36
|vpiRange:
\_range: , line:74
|vpiLeftRange:
\_constant: , line:74
|vpiConstType:7
|vpiDecompile:4
|vpiSize:32
|INT:4
|vpiRightRange:
\_constant: , line:74
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (id)
|vpiName:id
|vpiDirection:1
|vpiExpr:
\_logic_net: (id), line:75
|vpiName:id
|vpiNetType:36
|vpiRange:
\_range: , line:75
|vpiLeftRange:
\_constant: , line:75
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiRightRange:
\_constant: , line:75
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (request_valid)
|vpiName:request_valid
|vpiDirection:1
|vpiExpr:
\_logic_net: (request_valid), line:78
|vpiName:request_valid
|vpiNetType:36
|vpiIODecl:
\_io_decl: (abort)
|vpiName:abort
|vpiDirection:1
|vpiExpr:
\_logic_net: (abort), line:80
|vpiName:abort
|vpiNetType:36
|vpiIODecl:
\_io_decl: (request_pop)
|vpiName:request_pop
|vpiDirection:2
|vpiExpr:
\_logic_net: (request_pop), line:77
|vpiName:request_pop
|vpiNetType:36
|vpiIODecl:
\_io_decl: (wr_data)
|vpiName:wr_data
|vpiDirection:1
|vpiExpr:
\_logic_net: (wr_data), line:82
|vpiName:wr_data
|vpiNetType:36
|vpiRange:
\_range: , line:82
|vpiLeftRange:
\_constant: , line:82
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:82
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (wr_data_valid)
|vpiName:wr_data_valid
|vpiDirection:1
|vpiExpr:
\_logic_net: (wr_data_valid), line:83
|vpiName:wr_data_valid
|vpiNetType:36
|vpiIODecl:
\_io_decl: (wr_data_read)
|vpiName:wr_data_read
|vpiDirection:2
|vpiExpr:
\_logic_net: (wr_data_read), line:84
|vpiName:wr_data_read
|vpiNetType:36
|vpiIODecl:
\_io_decl: (rd_data)
|vpiName:rd_data
|vpiDirection:2
|vpiExpr:
\_logic_net: (rd_data), line:86
|vpiName:rd_data
|vpiNetType:36
|vpiRange:
\_range: , line:86
|vpiLeftRange:
\_constant: , line:86
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:86
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (rd_id)
|vpiName:rd_id
|vpiDirection:2
|vpiExpr:
\_logic_net: (rd_id), line:87
|vpiName:rd_id
|vpiNetType:36
|vpiRange:
\_range: , line:87
|vpiLeftRange:
\_constant: , line:87
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiRightRange:
\_constant: , line:87
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiIODecl:
\_io_decl: (rd_data_valid)
|vpiName:rd_data_valid
|vpiDirection:2
|vpiExpr:
\_logic_net: (rd_data_valid), line:88
|vpiName:rd_data_valid
|vpiNetType:36
|vpiInterface:
\_interface: work@l2_memory_interface (l2), file:third_party/cores/taiga/examples/zedboard/taiga_wrapper.sv, line:240
|vpiDefName:work@l2_memory_interface
|vpiName:l2
|vpiModport:
\_modport: (master)
|vpiName:master
|vpiIODecl:
\_io_decl: (addr)
|vpiName:addr
|vpiDirection:2
|vpiExpr:
\_logic_net: (addr), line:70
|vpiIODecl:
\_io_decl: (be)
|vpiName:be
|vpiDirection:2
|vpiExpr:
\_logic_net: (be), line:71
|vpiIODecl:
\_io_decl: (rnw)
|vpiName:rnw
|vpiDirection:2
|vpiExpr:
\_logic_net: (rnw), line:72
|vpiIODecl:
\_io_decl: (is_amo)
|vpiName:is_amo
|vpiDirection:2
|vpiExpr:
\_logic_net: (is_amo), line:73
|vpiIODecl:
\_io_decl: (amo_type_or_burst_size)
|vpiName:amo_type_or_burst_size
|vpiDirection:2
|vpiExpr:
\_logic_net: (amo_type_or_burst_size), line:74
|vpiIODecl:
\_io_decl: (id)
|vpiName:id
|vpiDirection:2
|vpiExpr:
\_logic_net: (id), line:75
|vpiIODecl:
\_io_decl: (request_valid)
|vpiName:request_valid
|vpiDirection:2
|vpiExpr:
\_logic_net: (request_valid), line:78
|vpiIODecl:
\_io_decl: (abort)
|vpiName:abort
|vpiDirection:2
|vpiExpr:
\_logic_net: (abort), line:80
|vpiIODecl:
\_io_decl: (request_pop)
|vpiName:request_pop
|vpiDirection:1
|vpiExpr:
\_logic_net: (request_pop), line:77
|vpiIODecl:
\_io_decl: (wr_data)
|vpiName:wr_data
|vpiDirection:2
|vpiExpr:
\_logic_net: (wr_data), line:82
|vpiIODecl:
\_io_decl: (wr_data_valid)
|vpiName:wr_data_valid
|vpiDirection:2
|vpiExpr:
\_logic_net: (wr_data_valid), line:83
|vpiIODecl:
\_io_decl: (wr_data_read)
|vpiName:wr_data_read
|vpiDirection:1
|vpiExpr:
\_logic_net: (wr_data_read), line:84
|vpiIODecl:
\_io_decl: (rd_data)
|vpiName:rd_data
|vpiDirection:1
|vpiExpr:
\_logic_net: (rd_data), line:86
|vpiIODecl:
\_io_decl: (rd_id)
|vpiName:rd_id
|vpiDirection:1
|vpiExpr:
\_logic_net: (rd_id), line:87
|vpiIODecl:
\_io_decl: (rd_data_valid)
|vpiName:rd_data_valid
|vpiDirection:1
|vpiExpr:
\_logic_net: (rd_data_valid), line:88
|vpiInterface:
\_interface: work@l2_memory_interface (l2), file:third_party/cores/taiga/examples/zedboard/taiga_wrapper.sv, line:240
|vpiModport:
\_modport: (slave)
|vpiModule:
\_module: work@amo_alu (amo_unit), file:third_party/cores/taiga/core/axi_to_arb.sv, line:140, parent:l2_to_mem
|vpiDefName:work@amo_alu
|vpiName:amo_unit
|vpiFullName:work@taiga_wrapper.genblk1.l2_to_mem.amo_unit
|vpiPort:
\_port: (amo_alu_inputs), line:27, parent:amo_unit
|vpiName:amo_alu_inputs
|vpiDirection:1
|vpiTypedef:
\_struct_typespec: (amo_alu_inputs_t), line:356
|vpiHighConn:
\_ref_obj: (amo_alu_inputs), line:140
|vpiName:amo_alu_inputs
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (amo_alu_inputs), line:27, parent:amo_unit
|vpiName:amo_alu_inputs
|vpiFullName:work@taiga_wrapper.genblk1.l2_to_mem.amo_unit.amo_alu_inputs
|vpiPort:
\_port: (result), line:28, parent:amo_unit
|vpiName:result
|vpiDirection:2
|vpiHighConn:
\_ref_obj: (result), line:140
|vpiName:result
|vpiLowConn:
\_ref_obj:
|vpiActual:
\_logic_net: (result), line:28, parent:amo_unit
|vpiName:result
|vpiFullName:work@taiga_wrapper.genblk1.l2_to_mem.amo_unit.result
|vpiNetType:36
|vpiRange:
\_range: , line:28
|vpiLeftRange:
\_constant: , line:28
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:28
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (amo_alu_inputs), line:27, parent:amo_unit
|vpiNet:
\_logic_net: (result), line:28, parent:amo_unit
|vpiNet:
\_logic_net: (rs1_smaller_than_rs2), line:31, parent:amo_unit
|vpiName:rs1_smaller_than_rs2
|vpiFullName:work@taiga_wrapper.genblk1.l2_to_mem.amo_unit.rs1_smaller_than_rs2
|vpiNetType:36
|vpiNet:
\_logic_net: (rs1_ext), line:32, parent:amo_unit
|vpiName:rs1_ext
|vpiFullName:work@taiga_wrapper.genblk1.l2_to_mem.amo_unit.rs1_ext
|vpiNetType:36
|vpiNet:
\_logic_net: (rs2_ext), line:33, parent:amo_unit
|vpiName:rs2_ext
|vpiFullName:work@taiga_wrapper.genblk1.l2_to_mem.amo_unit.rs2_ext
|vpiNetType:36
|vpiInstance:
\_module: work@axi_to_arb (l2_to_mem), file:third_party/cores/taiga/examples/zedboard/taiga_wrapper.sv, line:240
|vpiParameter:
\_parameter: (ALU_UNIT_WB_ID), line:190
|vpiName:ALU_UNIT_WB_ID
|INT:32
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (BRANCH_PREDICTOR_WAYS), line:159
|vpiName:BRANCH_PREDICTOR_WAYS
|INT:9
|vpiParameter:
\_parameter: (BRANCH_TABLE_ENTRIES), line:160
|vpiName:BRANCH_TABLE_ENTRIES
|INT:4
|vpiParameter:
\_parameter: (BRANCH_UNIT_ID), line:195
|vpiName:BRANCH_UNIT_ID
|INT:8
|vpiParameter:
\_parameter: (BUS_ADDR_H), line:107
|vpiName:BUS_ADDR_H
|INT:1
|vpiParameter:
\_parameter: (BUS_ADDR_L), line:106
|vpiName:BUS_ADDR_L
|INT:0
|vpiParameter:
\_parameter: (BUS_BIT_CHECK), line:108
|vpiName:BUS_BIT_CHECK
|INT:1
|vpiParameter:
\_parameter: (BUS_TYPE), line:89
|vpiName:BUS_TYPE
|INT:5
|vpiParameter:
\_parameter: (COUNTER_W), line:42
|vpiName:COUNTER_W
|INT:33
|vpiParameter:
\_parameter: (CPU_ID), line:38
|vpiName:CPU_ID
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_ADDR_WIDTH), line:113
|vpiName:C_M_AXI_ADDR_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_DATA_WIDTH), line:114
|vpiName:C_M_AXI_DATA_WIDTH
|INT:1
|vpiParameter:
\_parameter: (DCACHE_LINES), line:133
|vpiName:DCACHE_LINES
|INT:-2146435073
|vpiParameter:
\_parameter: (DCACHE_LINE_ADDR_W), line:135
|vpiName:DCACHE_LINE_ADDR_W
|INT:1073741824
|vpiParameter:
\_parameter: (DCACHE_LINE_W), line:136
|vpiName:DCACHE_LINE_W
|INT:1342177279
|vpiParameter:
\_parameter: (DCACHE_SUB_LINE_ADDR_W), line:137
|vpiName:DCACHE_SUB_LINE_ADDR_W
|INT:4
|vpiParameter:
\_parameter: (DCACHE_TAG_W), line:138
|vpiName:DCACHE_TAG_W
|INT:1610612736
|vpiParameter:
\_parameter: (DCACHE_WAYS), line:134
|vpiName:DCACHE_WAYS
|INT:4
|vpiParameter:
\_parameter: (DIV_ALGORITHM), line:67
|vpiName:DIV_ALGORITHM
|INT:0
|vpiParameter:
\_parameter: (DIV_UNIT_WB_ID), line:192
|vpiName:DIV_UNIT_WB_ID
|INT:2
|vpiParameter:
\_parameter: (DTLB_DEPTH), line:152
|vpiName:DTLB_DEPTH
|INT:512
|vpiParameter:
\_parameter: (DTLB_WAYS), line:151
|vpiName:DTLB_WAYS
|INT:32
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (ENABLE_M_MODE), line:34
|vpiName:ENABLE_M_MODE
|INT:1
|vpiParameter:
\_parameter: (ENABLE_S_MODE), line:36
|vpiName:ENABLE_S_MODE
|INT:0
|vpiParameter:
\_parameter: (ENABLE_TRACE_INTERFACE), line:172
|vpiName:ENABLE_TRACE_INTERFACE
|INT:2
|vpiParameter:
\_parameter: (FETCH_BUFFER_DEPTH), line:168
|vpiName:FETCH_BUFFER_DEPTH
|INT:512
|vpiParameter:
\_parameter: (FPGA_VENDOR), line:27
|vpiName:FPGA_VENDOR
|STRING:"xilinx"
|vpiParameter:
\_parameter: (GC_UNIT_ID), line:196
|vpiName:GC_UNIT_ID
|INT:4
|vpiParameter:
\_parameter: (ICACHE_LINES), line:121
|vpiName:ICACHE_LINES
|INT:2
|vpiParameter:
\_parameter: (ICACHE_LINE_ADDR_W), line:123
|vpiName:ICACHE_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_LINE_W), line:124
|vpiName:ICACHE_LINE_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_SUB_LINE_ADDR_W), line:125
|vpiName:ICACHE_SUB_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_TAG_W), line:126
|vpiName:ICACHE_TAG_W
|INT:-2147483648
|vpiParameter:
\_parameter: (ICACHE_WAYS), line:122
|vpiName:ICACHE_WAYS
|INT:1
|vpiParameter:
\_parameter: (ITLB_DEPTH), line:146
|vpiName:ITLB_DEPTH
|INT:32
|vpiParameter:
\_parameter: (ITLB_WAYS), line:145
|vpiName:ITLB_WAYS
|INT:4
|vpiParameter:
\_parameter: (L1_CONNECTIONS), line:177
|vpiName:L1_CONNECTIONS
|INT:9
|vpiParameter:
\_parameter: (L1_DCACHE_ID), line:178
|vpiName:L1_DCACHE_ID
|INT:4
|vpiParameter:
\_parameter: (L1_DMMU_ID), line:179
|vpiName:L1_DMMU_ID
|INT:2
|vpiParameter:
\_parameter: (L1_ICACHE_ID), line:180
|vpiName:L1_ICACHE_ID
|INT:19
|vpiParameter:
\_parameter: (L1_IMMU_ID), line:181
|vpiName:L1_IMMU_ID
|INT:0
|vpiParameter:
\_parameter: (LS_UNIT_WB_ID), line:191
|vpiName:LS_UNIT_WB_ID
|INT:1
|vpiParameter:
\_parameter: (MAX_INFLIGHT_COUNT), line:167
|vpiName:MAX_INFLIGHT_COUNT
|INT:19
|vpiParameter:
\_parameter: (MEMORY_ADDR_H), line:103
|vpiName:MEMORY_ADDR_H
|INT:12
|vpiParameter:
\_parameter: (MEMORY_ADDR_L), line:102
|vpiName:MEMORY_ADDR_L
|INT:11
|vpiParameter:
\_parameter: (MEMORY_BIT_CHECK), line:104
|vpiName:MEMORY_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (MUL_UNIT_WB_ID), line:193
|vpiName:MUL_UNIT_WB_ID
|INT:512
|vpiParameter:
\_parameter: (NUM_UNITS), line:188
|vpiName:NUM_UNITS
|INT:2
|vpiParameter:
\_parameter: (NUM_WB_UNITS), line:186
|vpiName:NUM_WB_UNITS
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (RAS_DEPTH), line:161
|vpiName:RAS_DEPTH
|INT:2
|vpiParameter:
\_parameter: (RESET_VEC), line:39
|vpiName:RESET_VEC
|INT:-2147483648
|vpiParameter:
\_parameter: (SCRATCH_ADDR_H), line:99
|vpiName:SCRATCH_ADDR_H
|INT:9
|vpiParameter:
\_parameter: (SCRATCH_ADDR_L), line:98
|vpiName:SCRATCH_ADDR_L
|INT:8
|vpiParameter:
\_parameter: (SCRATCH_BIT_CHECK), line:100
|vpiName:SCRATCH_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (USE_AMO), line:70
|vpiName:USE_AMO
|INT:1
|vpiParameter:
\_parameter: (USE_BRANCH_PREDICTOR), line:158
|vpiName:USE_BRANCH_PREDICTOR
|INT:2
|vpiParameter:
\_parameter: (USE_BUS), line:88
|vpiName:USE_BUS
|INT:4
|vpiParameter:
\_parameter: (USE_DCACHE), line:92
|vpiName:USE_DCACHE
|INT:6
|vpiParameter:
\_parameter: (USE_DIV), line:49
|vpiName:USE_DIV
|INT:1
|vpiParameter:
\_parameter: (USE_DTAG_INVALIDATIONS), line:140
|vpiName:USE_DTAG_INVALIDATIONS
|INT:1879048191
|vpiParameter:
\_parameter: (USE_D_SCRATCH_MEM), line:79
|vpiName:USE_D_SCRATCH_MEM
|INT:3
|vpiParameter:
\_parameter: (USE_ICACHE), line:93
|vpiName:USE_ICACHE
|INT:7
|vpiParameter:
\_parameter: (USE_I_SCRATCH_MEM), line:78
|vpiName:USE_I_SCRATCH_MEM
|INT:2
|vpiParameter:
\_parameter: (USE_MUL), line:48
|vpiName:USE_MUL
|INT:1
|vpiParameter:
\_parameter: (WB_UNITS_WIDTH), line:187
|vpiName:WB_UNITS_WIDTH
|INT:32
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiNet:
\_logic_net: (clk), line:30, parent:l2_to_mem
|vpiNet:
\_logic_net: (rst), line:31, parent:l2_to_mem
|vpiNet:
\_logic_net: (axi_arready), line:34, parent:l2_to_mem
|vpiNet:
\_logic_net: (axi_arvalid), line:35, parent:l2_to_mem
|vpiNet:
\_logic_net: (axi_araddr), line:36, parent:l2_to_mem
|vpiNet:
\_logic_net: (axi_arlen), line:37, parent:l2_to_mem
|vpiNet:
\_logic_net: (axi_arsize), line:38, parent:l2_to_mem
|vpiNet:
\_logic_net: (axi_arburst), line:39, parent:l2_to_mem
|vpiNet:
\_logic_net: (axi_arprot), line:40, parent:l2_to_mem
|vpiNet:
\_logic_net: (axi_arcache), line:41, parent:l2_to_mem
|vpiNet:
\_logic_net: (axi_arid), line:42, parent:l2_to_mem
|vpiNet:
\_logic_net: (axi_rready), line:45, parent:l2_to_mem
|vpiNet:
\_logic_net: (axi_rvalid), line:46, parent:l2_to_mem
|vpiNet:
\_logic_net: (axi_rdata), line:47, parent:l2_to_mem
|vpiNet:
\_logic_net: (axi_rresp), line:48, parent:l2_to_mem
|vpiNet:
\_logic_net: (axi_rlast), line:49, parent:l2_to_mem
|vpiNet:
\_logic_net: (axi_rid), line:50, parent:l2_to_mem
|vpiNet:
\_logic_net: (axi_awready), line:53, parent:l2_to_mem
|vpiNet:
\_logic_net: (axi_awvalid), line:54, parent:l2_to_mem
|vpiNet:
\_logic_net: (axi_awaddr), line:55, parent:l2_to_mem
|vpiNet:
\_logic_net: (axi_awlen), line:56, parent:l2_to_mem
|vpiNet:
\_logic_net: (axi_awsize), line:57, parent:l2_to_mem
|vpiNet:
\_logic_net: (axi_awburst), line:58, parent:l2_to_mem
|vpiNet:
\_logic_net: (axi_awcache), line:60, parent:l2_to_mem
|vpiNet:
\_logic_net: (axi_awprot), line:61, parent:l2_to_mem
|vpiNet:
\_logic_net: (axi_wready), line:64, parent:l2_to_mem
|vpiNet:
\_logic_net: (axi_wvalid), line:65, parent:l2_to_mem
|vpiNet:
\_logic_net: (axi_wdata), line:66, parent:l2_to_mem
|vpiNet:
\_logic_net: (axi_wstrb), line:67, parent:l2_to_mem
|vpiNet:
\_logic_net: (axi_wlast), line:68, parent:l2_to_mem
|vpiNet:
\_logic_net: (axi_bready), line:71, parent:l2_to_mem
|vpiNet:
\_logic_net: (axi_bvalid), line:72, parent:l2_to_mem
|vpiNet:
\_logic_net: (axi_bresp), line:73, parent:l2_to_mem
|vpiNet:
\_logic_net: (pop_request), line:82, parent:l2_to_mem
|vpiName:pop_request
|vpiFullName:work@taiga_wrapper.genblk1.l2_to_mem.pop_request
|vpiNetType:36
|vpiNet:
\_logic_net: (read_modify_write), line:84, parent:l2_to_mem
|vpiName:read_modify_write
|vpiFullName:work@taiga_wrapper.genblk1.l2_to_mem.read_modify_write
|vpiNetType:36
|vpiNet:
\_logic_net: (read_modify_write_in_progress), line:85, parent:l2_to_mem
|vpiName:read_modify_write_in_progress
|vpiFullName:work@taiga_wrapper.genblk1.l2_to_mem.read_modify_write_in_progress
|vpiNetType:36
|vpiNet:
\_logic_net: (address_phase_complete), line:86, parent:l2_to_mem
|vpiName:address_phase_complete
|vpiFullName:work@taiga_wrapper.genblk1.l2_to_mem.address_phase_complete
|vpiNetType:36
|vpiNet:
\_logic_net: (amo_result), line:87, parent:l2_to_mem
|vpiName:amo_result
|vpiFullName:work@taiga_wrapper.genblk1.l2_to_mem.amo_result
|vpiNetType:36
|vpiRange:
\_range: , line:87
|vpiLeftRange:
\_constant: , line:87
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:87
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (amo_result_r), line:88, parent:l2_to_mem
|vpiName:amo_result_r
|vpiFullName:work@taiga_wrapper.genblk1.l2_to_mem.amo_result_r
|vpiNetType:36
|vpiRange:
\_range: , line:88
|vpiLeftRange:
\_constant: , line:88
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:88
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (read_count), line:89, parent:l2_to_mem
|vpiName:read_count
|vpiFullName:work@taiga_wrapper.genblk1.l2_to_mem.read_count
|vpiNetType:36
|vpiRange:
\_range: , line:89
|vpiLeftRange:
\_constant: , line:89
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiRightRange:
\_constant: , line:89
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (amo_write_ready), line:90, parent:l2_to_mem
|vpiName:amo_write_ready
|vpiFullName:work@taiga_wrapper.genblk1.l2_to_mem.amo_write_ready
|vpiNetType:36
|vpiNet:
\_logic_net: (write_reference_burst_count), line:91, parent:l2_to_mem
|vpiName:write_reference_burst_count
|vpiFullName:work@taiga_wrapper.genblk1.l2_to_mem.write_reference_burst_count
|vpiNetType:36
|vpiRange:
\_range: , line:91
|vpiLeftRange:
\_constant: , line:91
|vpiConstType:7
|vpiDecompile:4
|vpiSize:32
|INT:4
|vpiRightRange:
\_constant: , line:91
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (write_in_progress), line:96, parent:l2_to_mem
|vpiName:write_in_progress
|vpiFullName:work@taiga_wrapper.genblk1.l2_to_mem.write_in_progress
|vpiNetType:36
|vpiNet:
\_logic_net: (write_transfer_complete), line:97, parent:l2_to_mem
|vpiName:write_transfer_complete
|vpiFullName:work@taiga_wrapper.genblk1.l2_to_mem.write_transfer_complete
|vpiNetType:36
|vpiNet:
\_logic_net: (pop), line:99, parent:l2_to_mem
|vpiName:pop
|vpiFullName:work@taiga_wrapper.genblk1.l2_to_mem.pop
|vpiNetType:36
|vpiNet:
\_logic_net: (write_burst_count), line:101, parent:l2_to_mem
|vpiName:write_burst_count
|vpiFullName:work@taiga_wrapper.genblk1.l2_to_mem.write_burst_count
|vpiNetType:36
|vpiRange:
\_range: , line:101
|vpiLeftRange:
\_constant: , line:101
|vpiConstType:7
|vpiDecompile:4
|vpiSize:32
|INT:4
|vpiRightRange:
\_constant: , line:101
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (burst_count), line:102, parent:l2_to_mem
|vpiName:burst_count
|vpiFullName:work@taiga_wrapper.genblk1.l2_to_mem.burst_count
|vpiNetType:36
|vpiRange:
\_range: , line:102
|vpiLeftRange:
\_constant: , line:102
|vpiConstType:7
|vpiDecompile:4
|vpiSize:32
|INT:4
|vpiRightRange:
\_constant: , line:102
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (burst_count_r), line:102, parent:l2_to_mem
|vpiName:burst_count_r
|vpiFullName:work@taiga_wrapper.genblk1.l2_to_mem.burst_count_r
|vpiNetType:36
|vpiRange:
\_range: , line:102
|vpiLeftRange:
\_constant: , line:102
|vpiConstType:7
|vpiDecompile:4
|vpiSize:32
|INT:4
|vpiRightRange:
\_constant: , line:102
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (on_last_burst), line:103, parent:l2_to_mem
|vpiName:on_last_burst
|vpiFullName:work@taiga_wrapper.genblk1.l2_to_mem.on_last_burst
|vpiNetType:36
|vpiNet:
\_logic_net: (l2), line:78, parent:l2_to_mem
|vpiName:l2
|vpiFullName:work@taiga_wrapper.genblk1.l2_to_mem.l2
|vpiVariables:
\_struct_var: (amo_alu_inputs), line:93, parent:l2_to_mem
|vpiName:amo_alu_inputs
|vpiFullName:work@taiga_wrapper.genblk1.l2_to_mem.amo_alu_inputs
|vpiTypespec:
\_struct_typespec: (amo_alu_inputs_t), line:356
|vpiParameter:
\_parameter: (ALU_UNIT_WB_ID), line:190
|vpiName:ALU_UNIT_WB_ID
|INT:32
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (BRANCH_PREDICTOR_WAYS), line:159
|vpiName:BRANCH_PREDICTOR_WAYS
|INT:9
|vpiParameter:
\_parameter: (BRANCH_TABLE_ENTRIES), line:160
|vpiName:BRANCH_TABLE_ENTRIES
|INT:4
|vpiParameter:
\_parameter: (BRANCH_UNIT_ID), line:195
|vpiName:BRANCH_UNIT_ID
|INT:8
|vpiParameter:
\_parameter: (BUS_ADDR_H), line:107
|vpiName:BUS_ADDR_H
|INT:1
|vpiParameter:
\_parameter: (BUS_ADDR_L), line:106
|vpiName:BUS_ADDR_L
|INT:0
|vpiParameter:
\_parameter: (BUS_BIT_CHECK), line:108
|vpiName:BUS_BIT_CHECK
|INT:1
|vpiParameter:
\_parameter: (BUS_TYPE), line:89
|vpiName:BUS_TYPE
|INT:5
|vpiParameter:
\_parameter: (COUNTER_W), line:42
|vpiName:COUNTER_W
|INT:33
|vpiParameter:
\_parameter: (CPU_ID), line:38
|vpiName:CPU_ID
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_ADDR_WIDTH), line:113
|vpiName:C_M_AXI_ADDR_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_DATA_WIDTH), line:114
|vpiName:C_M_AXI_DATA_WIDTH
|INT:1
|vpiParameter:
\_parameter: (DCACHE_LINES), line:133
|vpiName:DCACHE_LINES
|INT:-2146435073
|vpiParameter:
\_parameter: (DCACHE_LINE_ADDR_W), line:135
|vpiName:DCACHE_LINE_ADDR_W
|INT:1073741824
|vpiParameter:
\_parameter: (DCACHE_LINE_W), line:136
|vpiName:DCACHE_LINE_W
|INT:1342177279
|vpiParameter:
\_parameter: (DCACHE_SUB_LINE_ADDR_W), line:137
|vpiName:DCACHE_SUB_LINE_ADDR_W
|INT:4
|vpiParameter:
\_parameter: (DCACHE_TAG_W), line:138
|vpiName:DCACHE_TAG_W
|INT:1610612736
|vpiParameter:
\_parameter: (DCACHE_WAYS), line:134
|vpiName:DCACHE_WAYS
|INT:4
|vpiParameter:
\_parameter: (DIV_ALGORITHM), line:67
|vpiName:DIV_ALGORITHM
|INT:0
|vpiParameter:
\_parameter: (DIV_UNIT_WB_ID), line:192
|vpiName:DIV_UNIT_WB_ID
|INT:2
|vpiParameter:
\_parameter: (DTLB_DEPTH), line:152
|vpiName:DTLB_DEPTH
|INT:512
|vpiParameter:
\_parameter: (DTLB_WAYS), line:151
|vpiName:DTLB_WAYS
|INT:32
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (ENABLE_M_MODE), line:34
|vpiName:ENABLE_M_MODE
|INT:1
|vpiParameter:
\_parameter: (ENABLE_S_MODE), line:36
|vpiName:ENABLE_S_MODE
|INT:0
|vpiParameter:
\_parameter: (ENABLE_TRACE_INTERFACE), line:172
|vpiName:ENABLE_TRACE_INTERFACE
|INT:2
|vpiParameter:
\_parameter: (FETCH_BUFFER_DEPTH), line:168
|vpiName:FETCH_BUFFER_DEPTH
|INT:512
|vpiParameter:
\_parameter: (FPGA_VENDOR), line:27
|vpiName:FPGA_VENDOR
|STRING:"xilinx"
|vpiParameter:
\_parameter: (GC_UNIT_ID), line:196
|vpiName:GC_UNIT_ID
|INT:4
|vpiParameter:
\_parameter: (ICACHE_LINES), line:121
|vpiName:ICACHE_LINES
|INT:2
|vpiParameter:
\_parameter: (ICACHE_LINE_ADDR_W), line:123
|vpiName:ICACHE_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_LINE_W), line:124
|vpiName:ICACHE_LINE_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_SUB_LINE_ADDR_W), line:125
|vpiName:ICACHE_SUB_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_TAG_W), line:126
|vpiName:ICACHE_TAG_W
|INT:-2147483648
|vpiParameter:
\_parameter: (ICACHE_WAYS), line:122
|vpiName:ICACHE_WAYS
|INT:1
|vpiParameter:
\_parameter: (ITLB_DEPTH), line:146
|vpiName:ITLB_DEPTH
|INT:32
|vpiParameter:
\_parameter: (ITLB_WAYS), line:145
|vpiName:ITLB_WAYS
|INT:4
|vpiParameter:
\_parameter: (L1_CONNECTIONS), line:177
|vpiName:L1_CONNECTIONS
|INT:9
|vpiParameter:
\_parameter: (L1_DCACHE_ID), line:178
|vpiName:L1_DCACHE_ID
|INT:4
|vpiParameter:
\_parameter: (L1_DMMU_ID), line:179
|vpiName:L1_DMMU_ID
|INT:2
|vpiParameter:
\_parameter: (L1_ICACHE_ID), line:180
|vpiName:L1_ICACHE_ID
|INT:19
|vpiParameter:
\_parameter: (L1_IMMU_ID), line:181
|vpiName:L1_IMMU_ID
|INT:0
|vpiParameter:
\_parameter: (L2_DATA_ATTRIBUTES_FIFO_DEPTH), line:41
|vpiName:L2_DATA_ATTRIBUTES_FIFO_DEPTH
|INT:16
|vpiParameter:
\_parameter: (L2_ID_W), line:46
|vpiName:L2_ID_W
|INT:3
|vpiParameter:
\_parameter: (L2_INPUT_FIFO_DEPTHS), line:34
|vpiName:L2_INPUT_FIFO_DEPTHS
|INT:4
|vpiParameter:
\_parameter: (L2_INVALIDATION_FIFO_DEPTHS), line:35
|vpiName:L2_INVALIDATION_FIFO_DEPTHS
|INT:4
|vpiParameter:
\_parameter: (L2_MEM_ADDR_FIFO_DEPTH), line:39
|vpiName:L2_MEM_ADDR_FIFO_DEPTH
|INT:8
|vpiParameter:
\_parameter: (L2_NUM_PORTS), line:26
|vpiName:L2_NUM_PORTS
|INT:2
|vpiParameter:
\_parameter: (L2_READ_RETURN_FIFO_DEPTHS), line:36
|vpiName:L2_READ_RETURN_FIFO_DEPTHS
|INT:1
|vpiParameter:
\_parameter: (L2_SUB_ID_W), line:27
|vpiName:L2_SUB_ID_W
|INT:2
|vpiParameter:
\_parameter: (LS_UNIT_WB_ID), line:191
|vpiName:LS_UNIT_WB_ID
|INT:1
|vpiParameter:
\_parameter: (MAX_INFLIGHT_COUNT), line:167
|vpiName:MAX_INFLIGHT_COUNT
|INT:19
|vpiParameter:
\_parameter: (MEMORY_ADDR_H), line:103
|vpiName:MEMORY_ADDR_H
|INT:12
|vpiParameter:
\_parameter: (MEMORY_ADDR_L), line:102
|vpiName:MEMORY_ADDR_L
|INT:11
|vpiParameter:
\_parameter: (MEMORY_BIT_CHECK), line:104
|vpiName:MEMORY_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (MUL_UNIT_WB_ID), line:193
|vpiName:MUL_UNIT_WB_ID
|INT:512
|vpiParameter:
\_parameter: (NUM_UNITS), line:188
|vpiName:NUM_UNITS
|INT:2
|vpiParameter:
\_parameter: (NUM_WB_UNITS), line:186
|vpiName:NUM_WB_UNITS
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (RAS_DEPTH), line:161
|vpiName:RAS_DEPTH
|INT:2
|vpiParameter:
\_parameter: (RESET_VEC), line:39
|vpiName:RESET_VEC
|INT:-2147483648
|vpiParameter:
\_parameter: (SCRATCH_ADDR_H), line:99
|vpiName:SCRATCH_ADDR_H
|INT:9
|vpiParameter:
\_parameter: (SCRATCH_ADDR_L), line:98
|vpiName:SCRATCH_ADDR_L
|INT:8
|vpiParameter:
\_parameter: (SCRATCH_BIT_CHECK), line:100
|vpiName:SCRATCH_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (USE_AMO), line:70
|vpiName:USE_AMO
|INT:1
|vpiParameter:
\_parameter: (USE_BRANCH_PREDICTOR), line:158
|vpiName:USE_BRANCH_PREDICTOR
|INT:2
|vpiParameter:
\_parameter: (USE_BUS), line:88
|vpiName:USE_BUS
|INT:4
|vpiParameter:
\_parameter: (USE_DCACHE), line:92
|vpiName:USE_DCACHE
|INT:6
|vpiParameter:
\_parameter: (USE_DIV), line:49
|vpiName:USE_DIV
|INT:1
|vpiParameter:
\_parameter: (USE_DTAG_INVALIDATIONS), line:140
|vpiName:USE_DTAG_INVALIDATIONS
|INT:1879048191
|vpiParameter:
\_parameter: (USE_D_SCRATCH_MEM), line:79
|vpiName:USE_D_SCRATCH_MEM
|INT:3
|vpiParameter:
\_parameter: (USE_ICACHE), line:93
|vpiName:USE_ICACHE
|INT:7
|vpiParameter:
\_parameter: (USE_I_SCRATCH_MEM), line:78
|vpiName:USE_I_SCRATCH_MEM
|INT:2
|vpiParameter:
\_parameter: (USE_MUL), line:48
|vpiName:USE_MUL
|INT:1
|vpiParameter:
\_parameter: (WB_UNITS_WIDTH), line:187
|vpiName:WB_UNITS_WIDTH
|INT:32
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiParameter:
\_parameter: (ALU_UNIT_WB_ID), line:190
|vpiName:ALU_UNIT_WB_ID
|INT:32
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (BRANCH_PREDICTOR_WAYS), line:159
|vpiName:BRANCH_PREDICTOR_WAYS
|INT:9
|vpiParameter:
\_parameter: (BRANCH_TABLE_ENTRIES), line:160
|vpiName:BRANCH_TABLE_ENTRIES
|INT:4
|vpiParameter:
\_parameter: (BRANCH_UNIT_ID), line:195
|vpiName:BRANCH_UNIT_ID
|INT:8
|vpiParameter:
\_parameter: (BUS_ADDR_H), line:107
|vpiName:BUS_ADDR_H
|INT:1
|vpiParameter:
\_parameter: (BUS_ADDR_L), line:106
|vpiName:BUS_ADDR_L
|INT:0
|vpiParameter:
\_parameter: (BUS_BIT_CHECK), line:108
|vpiName:BUS_BIT_CHECK
|INT:1
|vpiParameter:
\_parameter: (BUS_TYPE), line:89
|vpiName:BUS_TYPE
|INT:5
|vpiParameter:
\_parameter: (COUNTER_W), line:42
|vpiName:COUNTER_W
|INT:33
|vpiParameter:
\_parameter: (CPU_ID), line:38
|vpiName:CPU_ID
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_ADDR_WIDTH), line:113
|vpiName:C_M_AXI_ADDR_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_DATA_WIDTH), line:114
|vpiName:C_M_AXI_DATA_WIDTH
|INT:1
|vpiParameter:
\_parameter: (DCACHE_LINES), line:133
|vpiName:DCACHE_LINES
|INT:-2146435073
|vpiParameter:
\_parameter: (DCACHE_LINE_ADDR_W), line:135
|vpiName:DCACHE_LINE_ADDR_W
|INT:1073741824
|vpiParameter:
\_parameter: (DCACHE_LINE_W), line:136
|vpiName:DCACHE_LINE_W
|INT:1342177279
|vpiParameter:
\_parameter: (DCACHE_SUB_LINE_ADDR_W), line:137
|vpiName:DCACHE_SUB_LINE_ADDR_W
|INT:4
|vpiParameter:
\_parameter: (DCACHE_TAG_W), line:138
|vpiName:DCACHE_TAG_W
|INT:1610612736
|vpiParameter:
\_parameter: (DCACHE_WAYS), line:134
|vpiName:DCACHE_WAYS
|INT:4
|vpiParameter:
\_parameter: (DIV_ALGORITHM), line:67
|vpiName:DIV_ALGORITHM
|INT:0
|vpiParameter:
\_parameter: (DIV_UNIT_WB_ID), line:192
|vpiName:DIV_UNIT_WB_ID
|INT:2
|vpiParameter:
\_parameter: (DTLB_DEPTH), line:152
|vpiName:DTLB_DEPTH
|INT:512
|vpiParameter:
\_parameter: (DTLB_WAYS), line:151
|vpiName:DTLB_WAYS
|INT:32
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (ENABLE_M_MODE), line:34
|vpiName:ENABLE_M_MODE
|INT:1
|vpiParameter:
\_parameter: (ENABLE_S_MODE), line:36
|vpiName:ENABLE_S_MODE
|INT:0
|vpiParameter:
\_parameter: (ENABLE_TRACE_INTERFACE), line:172
|vpiName:ENABLE_TRACE_INTERFACE
|INT:2
|vpiParameter:
\_parameter: (FETCH_BUFFER_DEPTH), line:168
|vpiName:FETCH_BUFFER_DEPTH
|INT:512
|vpiParameter:
\_parameter: (FPGA_VENDOR), line:27
|vpiName:FPGA_VENDOR
|STRING:"xilinx"
|vpiParameter:
\_parameter: (GC_UNIT_ID), line:196
|vpiName:GC_UNIT_ID
|INT:4
|vpiParameter:
\_parameter: (ICACHE_LINES), line:121
|vpiName:ICACHE_LINES
|INT:2
|vpiParameter:
\_parameter: (ICACHE_LINE_ADDR_W), line:123
|vpiName:ICACHE_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_LINE_W), line:124
|vpiName:ICACHE_LINE_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_SUB_LINE_ADDR_W), line:125
|vpiName:ICACHE_SUB_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_TAG_W), line:126
|vpiName:ICACHE_TAG_W
|INT:-2147483648
|vpiParameter:
\_parameter: (ICACHE_WAYS), line:122
|vpiName:ICACHE_WAYS
|INT:1
|vpiParameter:
\_parameter: (ITLB_DEPTH), line:146
|vpiName:ITLB_DEPTH
|INT:32
|vpiParameter:
\_parameter: (ITLB_WAYS), line:145
|vpiName:ITLB_WAYS
|INT:4
|vpiParameter:
\_parameter: (L1_CONNECTIONS), line:177
|vpiName:L1_CONNECTIONS
|INT:9
|vpiParameter:
\_parameter: (L1_DCACHE_ID), line:178
|vpiName:L1_DCACHE_ID
|INT:4
|vpiParameter:
\_parameter: (L1_DMMU_ID), line:179
|vpiName:L1_DMMU_ID
|INT:2
|vpiParameter:
\_parameter: (L1_ICACHE_ID), line:180
|vpiName:L1_ICACHE_ID
|INT:19
|vpiParameter:
\_parameter: (L1_IMMU_ID), line:181
|vpiName:L1_IMMU_ID
|INT:0
|vpiParameter:
\_parameter: (L2_DATA_ATTRIBUTES_FIFO_DEPTH), line:41
|vpiName:L2_DATA_ATTRIBUTES_FIFO_DEPTH
|INT:16
|vpiParameter:
\_parameter: (L2_ID_W), line:46
|vpiName:L2_ID_W
|INT:3
|vpiParameter:
\_parameter: (L2_INPUT_FIFO_DEPTHS), line:34
|vpiName:L2_INPUT_FIFO_DEPTHS
|INT:4
|vpiParameter:
\_parameter: (L2_INVALIDATION_FIFO_DEPTHS), line:35
|vpiName:L2_INVALIDATION_FIFO_DEPTHS
|INT:4
|vpiParameter:
\_parameter: (L2_MEM_ADDR_FIFO_DEPTH), line:39
|vpiName:L2_MEM_ADDR_FIFO_DEPTH
|INT:8
|vpiParameter:
\_parameter: (L2_NUM_PORTS), line:26
|vpiName:L2_NUM_PORTS
|INT:2
|vpiParameter:
\_parameter: (L2_READ_RETURN_FIFO_DEPTHS), line:36
|vpiName:L2_READ_RETURN_FIFO_DEPTHS
|INT:1
|vpiParameter:
\_parameter: (L2_SUB_ID_W), line:27
|vpiName:L2_SUB_ID_W
|INT:2
|vpiParameter:
\_parameter: (LS_UNIT_WB_ID), line:191
|vpiName:LS_UNIT_WB_ID
|INT:1
|vpiParameter:
\_parameter: (MAX_INFLIGHT_COUNT), line:167
|vpiName:MAX_INFLIGHT_COUNT
|INT:19
|vpiParameter:
\_parameter: (MEMORY_ADDR_H), line:103
|vpiName:MEMORY_ADDR_H
|INT:12
|vpiParameter:
\_parameter: (MEMORY_ADDR_L), line:102
|vpiName:MEMORY_ADDR_L
|INT:11
|vpiParameter:
\_parameter: (MEMORY_BIT_CHECK), line:104
|vpiName:MEMORY_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (MUL_UNIT_WB_ID), line:193
|vpiName:MUL_UNIT_WB_ID
|INT:512
|vpiParameter:
\_parameter: (NUM_UNITS), line:188
|vpiName:NUM_UNITS
|INT:2
|vpiParameter:
\_parameter: (NUM_WB_UNITS), line:186
|vpiName:NUM_WB_UNITS
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (RAS_DEPTH), line:161
|vpiName:RAS_DEPTH
|INT:2
|vpiParameter:
\_parameter: (RESET_VEC), line:39
|vpiName:RESET_VEC
|INT:-2147483648
|vpiParameter:
\_parameter: (SCRATCH_ADDR_H), line:99
|vpiName:SCRATCH_ADDR_H
|INT:9
|vpiParameter:
\_parameter: (SCRATCH_ADDR_L), line:98
|vpiName:SCRATCH_ADDR_L
|INT:8
|vpiParameter:
\_parameter: (SCRATCH_BIT_CHECK), line:100
|vpiName:SCRATCH_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (USE_AMO), line:70
|vpiName:USE_AMO
|INT:1
|vpiParameter:
\_parameter: (USE_BRANCH_PREDICTOR), line:158
|vpiName:USE_BRANCH_PREDICTOR
|INT:2
|vpiParameter:
\_parameter: (USE_BUS), line:88
|vpiName:USE_BUS
|INT:4
|vpiParameter:
\_parameter: (USE_DCACHE), line:92
|vpiName:USE_DCACHE
|INT:6
|vpiParameter:
\_parameter: (USE_DIV), line:49
|vpiName:USE_DIV
|INT:1
|vpiParameter:
\_parameter: (USE_DTAG_INVALIDATIONS), line:140
|vpiName:USE_DTAG_INVALIDATIONS
|INT:1879048191
|vpiParameter:
\_parameter: (USE_D_SCRATCH_MEM), line:79
|vpiName:USE_D_SCRATCH_MEM
|INT:3
|vpiParameter:
\_parameter: (USE_ICACHE), line:93
|vpiName:USE_ICACHE
|INT:7
|vpiParameter:
\_parameter: (USE_I_SCRATCH_MEM), line:78
|vpiName:USE_I_SCRATCH_MEM
|INT:2
|vpiParameter:
\_parameter: (USE_MUL), line:48
|vpiName:USE_MUL
|INT:1
|vpiParameter:
\_parameter: (WB_UNITS_WIDTH), line:187
|vpiName:WB_UNITS_WIDTH
|INT:32
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
|vpiNet:
\_logic_net: (sys_clk), line:28, parent:work@taiga_wrapper
|vpiNet:
\_logic_net: (ext_reset), line:29, parent:work@taiga_wrapper
|vpiNet:
\_logic_net: (DDR_addr), line:32, parent:work@taiga_wrapper
|vpiNet:
\_logic_net: (DDR_ba), line:33, parent:work@taiga_wrapper
|vpiNet:
\_logic_net: (DDR_cas_n), line:34, parent:work@taiga_wrapper
|vpiNet:
\_logic_net: (DDR_ck_n), line:35, parent:work@taiga_wrapper
|vpiNet:
\_logic_net: (DDR_ck_p), line:36, parent:work@taiga_wrapper
|vpiNet:
\_logic_net: (DDR_cke), line:37, parent:work@taiga_wrapper
|vpiNet:
\_logic_net: (DDR_cs_n), line:38, parent:work@taiga_wrapper
|vpiNet:
\_logic_net: (DDR_dm), line:39, parent:work@taiga_wrapper
|vpiNet:
\_logic_net: (DDR_dq), line:40, parent:work@taiga_wrapper
|vpiNet:
\_logic_net: (DDR_dqs_n), line:41, parent:work@taiga_wrapper
|vpiNet:
\_logic_net: (DDR_dqs_p), line:42, parent:work@taiga_wrapper
|vpiNet:
\_logic_net: (DDR_odt), line:43, parent:work@taiga_wrapper
|vpiNet:
\_logic_net: (DDR_ras_n), line:44, parent:work@taiga_wrapper
|vpiNet:
\_logic_net: (DDR_reset_n), line:45, parent:work@taiga_wrapper
|vpiNet:
\_logic_net: (DDR_we_n), line:46, parent:work@taiga_wrapper
|vpiNet:
\_logic_net: (FIXED_IO_ddr_vrn), line:47, parent:work@taiga_wrapper
|vpiNet:
\_logic_net: (FIXED_IO_ddr_vrp), line:48, parent:work@taiga_wrapper
|vpiNet:
\_logic_net: (FIXED_IO_mio), line:49, parent:work@taiga_wrapper
|vpiNet:
\_logic_net: (FIXED_IO_ps_clk), line:50, parent:work@taiga_wrapper
|vpiNet:
\_logic_net: (FIXED_IO_ps_porb), line:51, parent:work@taiga_wrapper
|vpiNet:
\_logic_net: (FIXED_IO_ps_srstb), line:52, parent:work@taiga_wrapper
|vpiNet:
\_logic_net: (sin), line:54, parent:work@taiga_wrapper
|vpiNet:
\_logic_net: (sout), line:55, parent:work@taiga_wrapper
|vpiNet:
\_logic_net: (clk), line:63, parent:work@taiga_wrapper
|vpiNet:
\_logic_net: (rst), line:64, parent:work@taiga_wrapper
|vpiNet:
\_logic_net: (resetn), line:65, parent:work@taiga_wrapper
|vpiName:resetn
|vpiFullName:work@taiga_wrapper.resetn
|vpiNetType:36
|vpiNet:
\_logic_net: (interrupt), line:73, parent:work@taiga_wrapper
|vpiNet:
\_logic_net: (mem_axi_araddr), line:78, parent:work@taiga_wrapper
|vpiName:mem_axi_araddr
|vpiFullName:work@taiga_wrapper.mem_axi_araddr
|vpiNetType:36
|vpiRange:
\_range: , line:78
|vpiLeftRange:
\_constant: , line:78
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:78
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (mem_axi_arburst), line:79, parent:work@taiga_wrapper
|vpiName:mem_axi_arburst
|vpiFullName:work@taiga_wrapper.mem_axi_arburst
|vpiNetType:36
|vpiRange:
\_range: , line:79
|vpiLeftRange:
\_constant: , line:79
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:79
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (mem_axi_arcache), line:80, parent:work@taiga_wrapper
|vpiName:mem_axi_arcache
|vpiFullName:work@taiga_wrapper.mem_axi_arcache
|vpiNetType:36
|vpiRange:
\_range: , line:80
|vpiLeftRange:
\_constant: , line:80
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiRightRange:
\_constant: , line:80
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (mem_axi_arid), line:81, parent:work@taiga_wrapper
|vpiName:mem_axi_arid
|vpiFullName:work@taiga_wrapper.mem_axi_arid
|vpiNetType:36
|vpiRange:
\_range: , line:81
|vpiLeftRange:
\_constant: , line:81
|vpiConstType:7
|vpiDecompile:5
|vpiSize:32
|INT:5
|vpiRightRange:
\_constant: , line:81
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (mem_axi_arlen), line:82, parent:work@taiga_wrapper
|vpiName:mem_axi_arlen
|vpiFullName:work@taiga_wrapper.mem_axi_arlen
|vpiNetType:36
|vpiRange:
\_range: , line:82
|vpiLeftRange:
\_constant: , line:82
|vpiConstType:7
|vpiDecompile:7
|vpiSize:32
|INT:7
|vpiRightRange:
\_constant: , line:82
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (mem_axi_arlock), line:83, parent:work@taiga_wrapper
|vpiName:mem_axi_arlock
|vpiFullName:work@taiga_wrapper.mem_axi_arlock
|vpiNetType:36
|vpiRange:
\_range: , line:83
|vpiLeftRange:
\_constant: , line:83
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiRightRange:
\_constant: , line:83
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (mem_axi_arprot), line:84, parent:work@taiga_wrapper
|vpiName:mem_axi_arprot
|vpiFullName:work@taiga_wrapper.mem_axi_arprot
|vpiNetType:36
|vpiRange:
\_range: , line:84
|vpiLeftRange:
\_constant: , line:84
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiRightRange:
\_constant: , line:84
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (mem_axi_arqos), line:85, parent:work@taiga_wrapper
|vpiName:mem_axi_arqos
|vpiFullName:work@taiga_wrapper.mem_axi_arqos
|vpiNetType:36
|vpiRange:
\_range: , line:85
|vpiLeftRange:
\_constant: , line:85
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiRightRange:
\_constant: , line:85
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (mem_axi_arready), line:86, parent:work@taiga_wrapper
|vpiName:mem_axi_arready
|vpiFullName:work@taiga_wrapper.mem_axi_arready
|vpiNetType:36
|vpiNet:
\_logic_net: (mem_axi_arregion), line:87, parent:work@taiga_wrapper
|vpiName:mem_axi_arregion
|vpiFullName:work@taiga_wrapper.mem_axi_arregion
|vpiNetType:36
|vpiRange:
\_range: , line:87
|vpiLeftRange:
\_constant: , line:87
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiRightRange:
\_constant: , line:87
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (mem_axi_arsize), line:88, parent:work@taiga_wrapper
|vpiName:mem_axi_arsize
|vpiFullName:work@taiga_wrapper.mem_axi_arsize
|vpiNetType:36
|vpiRange:
\_range: , line:88
|vpiLeftRange:
\_constant: , line:88
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiRightRange:
\_constant: , line:88
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (mem_axi_arvalid), line:89, parent:work@taiga_wrapper
|vpiName:mem_axi_arvalid
|vpiFullName:work@taiga_wrapper.mem_axi_arvalid
|vpiNetType:36
|vpiNet:
\_logic_net: (mem_axi_awaddr), line:90, parent:work@taiga_wrapper
|vpiName:mem_axi_awaddr
|vpiFullName:work@taiga_wrapper.mem_axi_awaddr
|vpiNetType:36
|vpiRange:
\_range: , line:90
|vpiLeftRange:
\_constant: , line:90
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:90
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (mem_axi_awburst), line:91, parent:work@taiga_wrapper
|vpiName:mem_axi_awburst
|vpiFullName:work@taiga_wrapper.mem_axi_awburst
|vpiNetType:36
|vpiRange:
\_range: , line:91
|vpiLeftRange:
\_constant: , line:91
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:91
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (mem_axi_awcache), line:92, parent:work@taiga_wrapper
|vpiName:mem_axi_awcache
|vpiFullName:work@taiga_wrapper.mem_axi_awcache
|vpiNetType:36
|vpiRange:
\_range: , line:92
|vpiLeftRange:
\_constant: , line:92
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiRightRange:
\_constant: , line:92
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (mem_axi_awid), line:93, parent:work@taiga_wrapper
|vpiName:mem_axi_awid
|vpiFullName:work@taiga_wrapper.mem_axi_awid
|vpiNetType:36
|vpiRange:
\_range: , line:93
|vpiLeftRange:
\_constant: , line:93
|vpiConstType:7
|vpiDecompile:5
|vpiSize:32
|INT:5
|vpiRightRange:
\_constant: , line:93
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (mem_axi_awlen), line:94, parent:work@taiga_wrapper
|vpiName:mem_axi_awlen
|vpiFullName:work@taiga_wrapper.mem_axi_awlen
|vpiNetType:36
|vpiRange:
\_range: , line:94
|vpiLeftRange:
\_constant: , line:94
|vpiConstType:7
|vpiDecompile:7
|vpiSize:32
|INT:7
|vpiRightRange:
\_constant: , line:94
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (mem_axi_awlock), line:95, parent:work@taiga_wrapper
|vpiName:mem_axi_awlock
|vpiFullName:work@taiga_wrapper.mem_axi_awlock
|vpiNetType:36
|vpiRange:
\_range: , line:95
|vpiLeftRange:
\_constant: , line:95
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiRightRange:
\_constant: , line:95
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (mem_axi_awprot), line:96, parent:work@taiga_wrapper
|vpiName:mem_axi_awprot
|vpiFullName:work@taiga_wrapper.mem_axi_awprot
|vpiNetType:36
|vpiRange:
\_range: , line:96
|vpiLeftRange:
\_constant: , line:96
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiRightRange:
\_constant: , line:96
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (mem_axi_awqos), line:97, parent:work@taiga_wrapper
|vpiName:mem_axi_awqos
|vpiFullName:work@taiga_wrapper.mem_axi_awqos
|vpiNetType:36
|vpiRange:
\_range: , line:97
|vpiLeftRange:
\_constant: , line:97
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiRightRange:
\_constant: , line:97
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (mem_axi_awready), line:98, parent:work@taiga_wrapper
|vpiName:mem_axi_awready
|vpiFullName:work@taiga_wrapper.mem_axi_awready
|vpiNetType:36
|vpiNet:
\_logic_net: (mem_axi_awregion), line:99, parent:work@taiga_wrapper
|vpiName:mem_axi_awregion
|vpiFullName:work@taiga_wrapper.mem_axi_awregion
|vpiNetType:36
|vpiRange:
\_range: , line:99
|vpiLeftRange:
\_constant: , line:99
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiRightRange:
\_constant: , line:99
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (mem_axi_awsize), line:100, parent:work@taiga_wrapper
|vpiName:mem_axi_awsize
|vpiFullName:work@taiga_wrapper.mem_axi_awsize
|vpiNetType:36
|vpiRange:
\_range: , line:100
|vpiLeftRange:
\_constant: , line:100
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiRightRange:
\_constant: , line:100
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (mem_axi_awvalid), line:101, parent:work@taiga_wrapper
|vpiName:mem_axi_awvalid
|vpiFullName:work@taiga_wrapper.mem_axi_awvalid
|vpiNetType:36
|vpiNet:
\_logic_net: (mem_axi_bid), line:102, parent:work@taiga_wrapper
|vpiName:mem_axi_bid
|vpiFullName:work@taiga_wrapper.mem_axi_bid
|vpiNetType:36
|vpiRange:
\_range: , line:102
|vpiLeftRange:
\_constant: , line:102
|vpiConstType:7
|vpiDecompile:5
|vpiSize:32
|INT:5
|vpiRightRange:
\_constant: , line:102
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (mem_axi_bready), line:103, parent:work@taiga_wrapper
|vpiName:mem_axi_bready
|vpiFullName:work@taiga_wrapper.mem_axi_bready
|vpiNetType:36
|vpiNet:
\_logic_net: (mem_axi_bresp), line:104, parent:work@taiga_wrapper
|vpiName:mem_axi_bresp
|vpiFullName:work@taiga_wrapper.mem_axi_bresp
|vpiNetType:36
|vpiRange:
\_range: , line:104
|vpiLeftRange:
\_constant: , line:104
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:104
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (mem_axi_bvalid), line:105, parent:work@taiga_wrapper
|vpiName:mem_axi_bvalid
|vpiFullName:work@taiga_wrapper.mem_axi_bvalid
|vpiNetType:36
|vpiNet:
\_logic_net: (mem_axi_rdata), line:106, parent:work@taiga_wrapper
|vpiName:mem_axi_rdata
|vpiFullName:work@taiga_wrapper.mem_axi_rdata
|vpiNetType:36
|vpiRange:
\_range: , line:106
|vpiLeftRange:
\_constant: , line:106
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:106
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (mem_axi_rid), line:107, parent:work@taiga_wrapper
|vpiName:mem_axi_rid
|vpiFullName:work@taiga_wrapper.mem_axi_rid
|vpiNetType:36
|vpiRange:
\_range: , line:107
|vpiLeftRange:
\_constant: , line:107
|vpiConstType:7
|vpiDecompile:5
|vpiSize:32
|INT:5
|vpiRightRange:
\_constant: , line:107
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (mem_axi_rlast), line:108, parent:work@taiga_wrapper
|vpiName:mem_axi_rlast
|vpiFullName:work@taiga_wrapper.mem_axi_rlast
|vpiNetType:36
|vpiNet:
\_logic_net: (mem_axi_rready), line:109, parent:work@taiga_wrapper
|vpiName:mem_axi_rready
|vpiFullName:work@taiga_wrapper.mem_axi_rready
|vpiNetType:36
|vpiNet:
\_logic_net: (mem_axi_rresp), line:110, parent:work@taiga_wrapper
|vpiName:mem_axi_rresp
|vpiFullName:work@taiga_wrapper.mem_axi_rresp
|vpiNetType:36
|vpiRange:
\_range: , line:110
|vpiLeftRange:
\_constant: , line:110
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:110
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (mem_axi_rvalid), line:111, parent:work@taiga_wrapper
|vpiName:mem_axi_rvalid
|vpiFullName:work@taiga_wrapper.mem_axi_rvalid
|vpiNetType:36
|vpiNet:
\_logic_net: (mem_axi_wdata), line:112, parent:work@taiga_wrapper
|vpiName:mem_axi_wdata
|vpiFullName:work@taiga_wrapper.mem_axi_wdata
|vpiNetType:36
|vpiRange:
\_range: , line:112
|vpiLeftRange:
\_constant: , line:112
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:112
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (mem_axi_wlast), line:113, parent:work@taiga_wrapper
|vpiName:mem_axi_wlast
|vpiFullName:work@taiga_wrapper.mem_axi_wlast
|vpiNetType:36
|vpiNet:
\_logic_net: (mem_axi_wready), line:114, parent:work@taiga_wrapper
|vpiName:mem_axi_wready
|vpiFullName:work@taiga_wrapper.mem_axi_wready
|vpiNetType:36
|vpiNet:
\_logic_net: (mem_axi_wstrb), line:115, parent:work@taiga_wrapper
|vpiName:mem_axi_wstrb
|vpiFullName:work@taiga_wrapper.mem_axi_wstrb
|vpiNetType:36
|vpiRange:
\_range: , line:115
|vpiLeftRange:
\_constant: , line:115
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiRightRange:
\_constant: , line:115
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (mem_axi_wvalid), line:116, parent:work@taiga_wrapper
|vpiName:mem_axi_wvalid
|vpiFullName:work@taiga_wrapper.mem_axi_wvalid
|vpiNetType:36
|vpiNet:
\_logic_net: (mem_axi_wid), line:117, parent:work@taiga_wrapper
|vpiName:mem_axi_wid
|vpiFullName:work@taiga_wrapper.mem_axi_wid
|vpiNetType:36
|vpiRange:
\_range: , line:117
|vpiLeftRange:
\_constant: , line:117
|vpiConstType:7
|vpiDecompile:5
|vpiSize:32
|INT:5
|vpiRightRange:
\_constant: , line:117
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (ACLK), line:119, parent:work@taiga_wrapper
|vpiName:ACLK
|vpiFullName:work@taiga_wrapper.ACLK
|vpiNetType:36
|vpiNet:
\_logic_net: (bus_axi_araddr), line:120, parent:work@taiga_wrapper
|vpiName:bus_axi_araddr
|vpiFullName:work@taiga_wrapper.bus_axi_araddr
|vpiNetType:36
|vpiRange:
\_range: , line:120
|vpiLeftRange:
\_constant: , line:120
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:120
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (bus_axi_arready), line:121, parent:work@taiga_wrapper
|vpiName:bus_axi_arready
|vpiFullName:work@taiga_wrapper.bus_axi_arready
|vpiNetType:36
|vpiNet:
\_logic_net: (bus_axi_arvalid), line:122, parent:work@taiga_wrapper
|vpiName:bus_axi_arvalid
|vpiFullName:work@taiga_wrapper.bus_axi_arvalid
|vpiNetType:36
|vpiNet:
\_logic_net: (bus_axi_awaddr), line:123, parent:work@taiga_wrapper
|vpiName:bus_axi_awaddr
|vpiFullName:work@taiga_wrapper.bus_axi_awaddr
|vpiNetType:36
|vpiRange:
\_range: , line:123
|vpiLeftRange:
\_constant: , line:123
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:123
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (bus_axi_awready), line:124, parent:work@taiga_wrapper
|vpiName:bus_axi_awready
|vpiFullName:work@taiga_wrapper.bus_axi_awready
|vpiNetType:36
|vpiNet:
\_logic_net: (bus_axi_awvalid), line:125, parent:work@taiga_wrapper
|vpiName:bus_axi_awvalid
|vpiFullName:work@taiga_wrapper.bus_axi_awvalid
|vpiNetType:36
|vpiNet:
\_logic_net: (bus_axi_bready), line:126, parent:work@taiga_wrapper
|vpiName:bus_axi_bready
|vpiFullName:work@taiga_wrapper.bus_axi_bready
|vpiNetType:36
|vpiNet:
\_logic_net: (bus_axi_bresp), line:127, parent:work@taiga_wrapper
|vpiName:bus_axi_bresp
|vpiFullName:work@taiga_wrapper.bus_axi_bresp
|vpiNetType:36
|vpiRange:
\_range: , line:127
|vpiLeftRange:
\_constant: , line:127
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:127
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (bus_axi_bvalid), line:128, parent:work@taiga_wrapper
|vpiName:bus_axi_bvalid
|vpiFullName:work@taiga_wrapper.bus_axi_bvalid
|vpiNetType:36
|vpiNet:
\_logic_net: (bus_axi_rdata), line:129, parent:work@taiga_wrapper
|vpiName:bus_axi_rdata
|vpiFullName:work@taiga_wrapper.bus_axi_rdata
|vpiNetType:36
|vpiRange:
\_range: , line:129
|vpiLeftRange:
\_constant: , line:129
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:129
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (bus_axi_rready), line:130, parent:work@taiga_wrapper
|vpiName:bus_axi_rready
|vpiFullName:work@taiga_wrapper.bus_axi_rready
|vpiNetType:36
|vpiNet:
\_logic_net: (bus_axi_rresp), line:131, parent:work@taiga_wrapper
|vpiName:bus_axi_rresp
|vpiFullName:work@taiga_wrapper.bus_axi_rresp
|vpiNetType:36
|vpiRange:
\_range: , line:131
|vpiLeftRange:
\_constant: , line:131
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:131
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (bus_axi_rvalid), line:132, parent:work@taiga_wrapper
|vpiName:bus_axi_rvalid
|vpiFullName:work@taiga_wrapper.bus_axi_rvalid
|vpiNetType:36
|vpiNet:
\_logic_net: (bus_axi_wdata), line:133, parent:work@taiga_wrapper
|vpiName:bus_axi_wdata
|vpiFullName:work@taiga_wrapper.bus_axi_wdata
|vpiNetType:36
|vpiRange:
\_range: , line:133
|vpiLeftRange:
\_constant: , line:133
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:133
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (bus_axi_wready), line:134, parent:work@taiga_wrapper
|vpiName:bus_axi_wready
|vpiFullName:work@taiga_wrapper.bus_axi_wready
|vpiNetType:36
|vpiNet:
\_logic_net: (bus_axi_wstrb), line:135, parent:work@taiga_wrapper
|vpiName:bus_axi_wstrb
|vpiFullName:work@taiga_wrapper.bus_axi_wstrb
|vpiNetType:36
|vpiRange:
\_range: , line:135
|vpiLeftRange:
\_constant: , line:135
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiRightRange:
\_constant: , line:135
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (bus_axi_wvalid), line:136, parent:work@taiga_wrapper
|vpiName:bus_axi_wvalid
|vpiFullName:work@taiga_wrapper.bus_axi_wvalid
|vpiNetType:36
|vpiNet:
\_logic_net: (processor_reset), line:138, parent:work@taiga_wrapper
|vpiName:processor_reset
|vpiFullName:work@taiga_wrapper.processor_reset
|vpiNetType:36
|vpiNet:
\_logic_net: (axi_arready), line:142, parent:work@taiga_wrapper
|vpiName:axi_arready
|vpiFullName:work@taiga_wrapper.axi_arready
|vpiNetType:36
|vpiNet:
\_logic_net: (axi_arvalid), line:143, parent:work@taiga_wrapper
|vpiName:axi_arvalid
|vpiFullName:work@taiga_wrapper.axi_arvalid
|vpiNetType:36
|vpiNet:
\_logic_net: (axi_araddr), line:144, parent:work@taiga_wrapper
|vpiName:axi_araddr
|vpiFullName:work@taiga_wrapper.axi_araddr
|vpiNetType:36
|vpiRange:
\_range: , line:144
|vpiLeftRange:
\_constant: , line:144
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:144
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (axi_arlen), line:145, parent:work@taiga_wrapper
|vpiName:axi_arlen
|vpiFullName:work@taiga_wrapper.axi_arlen
|vpiNetType:36
|vpiRange:
\_range: , line:145
|vpiLeftRange:
\_constant: , line:145
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiRightRange:
\_constant: , line:145
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (axi_arsize), line:146, parent:work@taiga_wrapper
|vpiName:axi_arsize
|vpiFullName:work@taiga_wrapper.axi_arsize
|vpiNetType:36
|vpiRange:
\_range: , line:146
|vpiLeftRange:
\_constant: , line:146
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiRightRange:
\_constant: , line:146
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (axi_arburst), line:147, parent:work@taiga_wrapper
|vpiName:axi_arburst
|vpiFullName:work@taiga_wrapper.axi_arburst
|vpiNetType:36
|vpiRange:
\_range: , line:147
|vpiLeftRange:
\_constant: , line:147
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:147
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (axi_arprot), line:148, parent:work@taiga_wrapper
|vpiName:axi_arprot
|vpiFullName:work@taiga_wrapper.axi_arprot
|vpiNetType:36
|vpiRange:
\_range: , line:148
|vpiLeftRange:
\_constant: , line:148
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiRightRange:
\_constant: , line:148
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (axi_arcache), line:149, parent:work@taiga_wrapper
|vpiName:axi_arcache
|vpiFullName:work@taiga_wrapper.axi_arcache
|vpiNetType:36
|vpiRange:
\_range: , line:149
|vpiLeftRange:
\_constant: , line:149
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiRightRange:
\_constant: , line:149
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (axi_arid), line:150, parent:work@taiga_wrapper
|vpiName:axi_arid
|vpiFullName:work@taiga_wrapper.axi_arid
|vpiNetType:36
|vpiRange:
\_range: , line:150
|vpiLeftRange:
\_constant: , line:150
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiRightRange:
\_constant: , line:150
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (axi_arlock), line:151, parent:work@taiga_wrapper
|vpiName:axi_arlock
|vpiFullName:work@taiga_wrapper.axi_arlock
|vpiNetType:36
|vpiRange:
\_range: , line:151
|vpiLeftRange:
\_constant: , line:151
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:151
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (axi_arqos), line:152, parent:work@taiga_wrapper
|vpiName:axi_arqos
|vpiFullName:work@taiga_wrapper.axi_arqos
|vpiNetType:36
|vpiRange:
\_range: , line:152
|vpiLeftRange:
\_constant: , line:152
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiRightRange:
\_constant: , line:152
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (axi_rready), line:155, parent:work@taiga_wrapper
|vpiName:axi_rready
|vpiFullName:work@taiga_wrapper.axi_rready
|vpiNetType:36
|vpiNet:
\_logic_net: (axi_rvalid), line:156, parent:work@taiga_wrapper
|vpiName:axi_rvalid
|vpiFullName:work@taiga_wrapper.axi_rvalid
|vpiNetType:36
|vpiNet:
\_logic_net: (axi_rdata), line:157, parent:work@taiga_wrapper
|vpiName:axi_rdata
|vpiFullName:work@taiga_wrapper.axi_rdata
|vpiNetType:36
|vpiRange:
\_range: , line:157
|vpiLeftRange:
\_constant: , line:157
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:157
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (axi_rresp), line:158, parent:work@taiga_wrapper
|vpiName:axi_rresp
|vpiFullName:work@taiga_wrapper.axi_rresp
|vpiNetType:36
|vpiRange:
\_range: , line:158
|vpiLeftRange:
\_constant: , line:158
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:158
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (axi_rlast), line:159, parent:work@taiga_wrapper
|vpiName:axi_rlast
|vpiFullName:work@taiga_wrapper.axi_rlast
|vpiNetType:36
|vpiNet:
\_logic_net: (axi_rid), line:160, parent:work@taiga_wrapper
|vpiName:axi_rid
|vpiFullName:work@taiga_wrapper.axi_rid
|vpiNetType:36
|vpiRange:
\_range: , line:160
|vpiLeftRange:
\_constant: , line:160
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiRightRange:
\_constant: , line:160
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (axi_awready), line:163, parent:work@taiga_wrapper
|vpiName:axi_awready
|vpiFullName:work@taiga_wrapper.axi_awready
|vpiNetType:36
|vpiNet:
\_logic_net: (axi_awvalid), line:164, parent:work@taiga_wrapper
|vpiName:axi_awvalid
|vpiFullName:work@taiga_wrapper.axi_awvalid
|vpiNetType:36
|vpiNet:
\_logic_net: (axi_awaddr), line:165, parent:work@taiga_wrapper
|vpiName:axi_awaddr
|vpiFullName:work@taiga_wrapper.axi_awaddr
|vpiNetType:36
|vpiRange:
\_range: , line:165
|vpiLeftRange:
\_constant: , line:165
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:165
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (axi_awlen), line:166, parent:work@taiga_wrapper
|vpiName:axi_awlen
|vpiFullName:work@taiga_wrapper.axi_awlen
|vpiNetType:36
|vpiRange:
\_range: , line:166
|vpiLeftRange:
\_constant: , line:166
|vpiConstType:7
|vpiDecompile:7
|vpiSize:32
|INT:7
|vpiRightRange:
\_constant: , line:166
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (axi_awsize), line:167, parent:work@taiga_wrapper
|vpiName:axi_awsize
|vpiFullName:work@taiga_wrapper.axi_awsize
|vpiNetType:36
|vpiRange:
\_range: , line:167
|vpiLeftRange:
\_constant: , line:167
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiRightRange:
\_constant: , line:167
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (axi_awburst), line:168, parent:work@taiga_wrapper
|vpiName:axi_awburst
|vpiFullName:work@taiga_wrapper.axi_awburst
|vpiNetType:36
|vpiRange:
\_range: , line:168
|vpiLeftRange:
\_constant: , line:168
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:168
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (axi_awlock), line:169, parent:work@taiga_wrapper
|vpiName:axi_awlock
|vpiFullName:work@taiga_wrapper.axi_awlock
|vpiNetType:36
|vpiRange:
\_range: , line:169
|vpiLeftRange:
\_constant: , line:169
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:169
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (axi_awqos), line:170, parent:work@taiga_wrapper
|vpiName:axi_awqos
|vpiFullName:work@taiga_wrapper.axi_awqos
|vpiNetType:36
|vpiRange:
\_range: , line:170
|vpiLeftRange:
\_constant: , line:170
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiRightRange:
\_constant: , line:170
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (axi_awid), line:171, parent:work@taiga_wrapper
|vpiName:axi_awid
|vpiFullName:work@taiga_wrapper.axi_awid
|vpiNetType:36
|vpiRange:
\_range: , line:171
|vpiLeftRange:
\_constant: , line:171
|vpiConstType:7
|vpiDecompile:5
|vpiSize:32
|INT:5
|vpiRightRange:
\_constant: , line:171
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (axi_awcache), line:173, parent:work@taiga_wrapper
|vpiName:axi_awcache
|vpiFullName:work@taiga_wrapper.axi_awcache
|vpiNetType:36
|vpiRange:
\_range: , line:173
|vpiLeftRange:
\_constant: , line:173
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiRightRange:
\_constant: , line:173
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (axi_awprot), line:174, parent:work@taiga_wrapper
|vpiName:axi_awprot
|vpiFullName:work@taiga_wrapper.axi_awprot
|vpiNetType:36
|vpiRange:
\_range: , line:174
|vpiLeftRange:
\_constant: , line:174
|vpiConstType:7
|vpiDecompile:2
|vpiSize:32
|INT:2
|vpiRightRange:
\_constant: , line:174
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (axi_wready), line:177, parent:work@taiga_wrapper
|vpiName:axi_wready
|vpiFullName:work@taiga_wrapper.axi_wready
|vpiNetType:36
|vpiNet:
\_logic_net: (axi_wvalid), line:178, parent:work@taiga_wrapper
|vpiName:axi_wvalid
|vpiFullName:work@taiga_wrapper.axi_wvalid
|vpiNetType:36
|vpiNet:
\_logic_net: (axi_wdata), line:179, parent:work@taiga_wrapper
|vpiName:axi_wdata
|vpiFullName:work@taiga_wrapper.axi_wdata
|vpiNetType:36
|vpiRange:
\_range: , line:179
|vpiLeftRange:
\_constant: , line:179
|vpiConstType:7
|vpiDecompile:31
|vpiSize:32
|INT:31
|vpiRightRange:
\_constant: , line:179
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (axi_wstrb), line:180, parent:work@taiga_wrapper
|vpiName:axi_wstrb
|vpiFullName:work@taiga_wrapper.axi_wstrb
|vpiNetType:36
|vpiRange:
\_range: , line:180
|vpiLeftRange:
\_constant: , line:180
|vpiConstType:7
|vpiDecompile:3
|vpiSize:32
|INT:3
|vpiRightRange:
\_constant: , line:180
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (axi_wlast), line:181, parent:work@taiga_wrapper
|vpiName:axi_wlast
|vpiFullName:work@taiga_wrapper.axi_wlast
|vpiNetType:36
|vpiNet:
\_logic_net: (axi_wid), line:182, parent:work@taiga_wrapper
|vpiName:axi_wid
|vpiFullName:work@taiga_wrapper.axi_wid
|vpiNetType:36
|vpiRange:
\_range: , line:182
|vpiLeftRange:
\_constant: , line:182
|vpiConstType:7
|vpiDecompile:5
|vpiSize:32
|INT:5
|vpiRightRange:
\_constant: , line:182
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (axi_bready), line:186, parent:work@taiga_wrapper
|vpiName:axi_bready
|vpiFullName:work@taiga_wrapper.axi_bready
|vpiNetType:36
|vpiNet:
\_logic_net: (axi_bvalid), line:187, parent:work@taiga_wrapper
|vpiName:axi_bvalid
|vpiFullName:work@taiga_wrapper.axi_bvalid
|vpiNetType:36
|vpiNet:
\_logic_net: (axi_bresp), line:188, parent:work@taiga_wrapper
|vpiName:axi_bresp
|vpiFullName:work@taiga_wrapper.axi_bresp
|vpiNetType:36
|vpiRange:
\_range: , line:188
|vpiLeftRange:
\_constant: , line:188
|vpiConstType:7
|vpiDecompile:1
|vpiSize:32
|INT:1
|vpiRightRange:
\_constant: , line:188
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (axi_bid), line:189, parent:work@taiga_wrapper
|vpiName:axi_bid
|vpiFullName:work@taiga_wrapper.axi_bid
|vpiNetType:36
|vpiRange:
\_range: , line:189
|vpiLeftRange:
\_constant: , line:189
|vpiConstType:7
|vpiDecompile:5
|vpiSize:32
|INT:5
|vpiRightRange:
\_constant: , line:189
|vpiConstType:7
|vpiDecompile:0
|vpiSize:32
|INT:0
|vpiNet:
\_logic_net: (axi_clk), line:192, parent:work@taiga_wrapper
|vpiName:axi_clk
|vpiFullName:work@taiga_wrapper.axi_clk
|vpiNetType:36
|vpiNet:
\_logic_net: (processor_clk), line:193, parent:work@taiga_wrapper
|vpiName:processor_clk
|vpiFullName:work@taiga_wrapper.processor_clk
|vpiNetType:36
|vpiParameter:
\_parameter: (ALU_UNIT_WB_ID), line:190
|vpiName:ALU_UNIT_WB_ID
|INT:32
|vpiParameter:
\_parameter: (ASIDLEN), line:225
|vpiName:ASIDLEN
|INT:11
|vpiParameter:
\_parameter: (BRANCH_PREDICTOR_WAYS), line:159
|vpiName:BRANCH_PREDICTOR_WAYS
|INT:9
|vpiParameter:
\_parameter: (BRANCH_TABLE_ENTRIES), line:160
|vpiName:BRANCH_TABLE_ENTRIES
|INT:4
|vpiParameter:
\_parameter: (BRANCH_UNIT_ID), line:195
|vpiName:BRANCH_UNIT_ID
|INT:8
|vpiParameter:
\_parameter: (BUS_ADDR_H), line:107
|vpiName:BUS_ADDR_H
|INT:1
|vpiParameter:
\_parameter: (BUS_ADDR_L), line:106
|vpiName:BUS_ADDR_L
|INT:0
|vpiParameter:
\_parameter: (BUS_BIT_CHECK), line:108
|vpiName:BUS_BIT_CHECK
|INT:1
|vpiParameter:
\_parameter: (BUS_TYPE), line:89
|vpiName:BUS_TYPE
|INT:5
|vpiParameter:
\_parameter: (COUNTER_W), line:42
|vpiName:COUNTER_W
|INT:33
|vpiParameter:
\_parameter: (CPU_ID), line:38
|vpiName:CPU_ID
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_ADDR_WIDTH), line:113
|vpiName:C_M_AXI_ADDR_WIDTH
|INT:0
|vpiParameter:
\_parameter: (C_M_AXI_DATA_WIDTH), line:114
|vpiName:C_M_AXI_DATA_WIDTH
|INT:1
|vpiParameter:
\_parameter: (DCACHE_LINES), line:133
|vpiName:DCACHE_LINES
|INT:-2146435073
|vpiParameter:
\_parameter: (DCACHE_LINE_ADDR_W), line:135
|vpiName:DCACHE_LINE_ADDR_W
|INT:1073741824
|vpiParameter:
\_parameter: (DCACHE_LINE_W), line:136
|vpiName:DCACHE_LINE_W
|INT:1342177279
|vpiParameter:
\_parameter: (DCACHE_SUB_LINE_ADDR_W), line:137
|vpiName:DCACHE_SUB_LINE_ADDR_W
|INT:4
|vpiParameter:
\_parameter: (DCACHE_TAG_W), line:138
|vpiName:DCACHE_TAG_W
|INT:1610612736
|vpiParameter:
\_parameter: (DCACHE_WAYS), line:134
|vpiName:DCACHE_WAYS
|INT:4
|vpiParameter:
\_parameter: (DIV_ALGORITHM), line:67
|vpiName:DIV_ALGORITHM
|INT:0
|vpiParameter:
\_parameter: (DIV_UNIT_WB_ID), line:192
|vpiName:DIV_UNIT_WB_ID
|INT:2
|vpiParameter:
\_parameter: (DTLB_DEPTH), line:152
|vpiName:DTLB_DEPTH
|INT:512
|vpiParameter:
\_parameter: (DTLB_WAYS), line:151
|vpiName:DTLB_WAYS
|INT:32
|vpiParameter:
\_parameter: (ECODE_W), line:28
|vpiName:ECODE_W
|INT:10
|vpiParameter:
\_parameter: (ENABLE_M_MODE), line:34
|vpiName:ENABLE_M_MODE
|INT:1
|vpiParameter:
\_parameter: (ENABLE_S_MODE), line:36
|vpiName:ENABLE_S_MODE
|INT:0
|vpiParameter:
\_parameter: (ENABLE_TRACE_INTERFACE), line:172
|vpiName:ENABLE_TRACE_INTERFACE
|INT:2
|vpiParameter:
\_parameter: (FETCH_BUFFER_DEPTH), line:168
|vpiName:FETCH_BUFFER_DEPTH
|INT:512
|vpiParameter:
\_parameter: (FPGA_VENDOR), line:27
|vpiName:FPGA_VENDOR
|STRING:"xilinx"
|vpiParameter:
\_parameter: (GC_UNIT_ID), line:196
|vpiName:GC_UNIT_ID
|INT:4
|vpiParameter:
\_parameter: (ICACHE_LINES), line:121
|vpiName:ICACHE_LINES
|INT:2
|vpiParameter:
\_parameter: (ICACHE_LINE_ADDR_W), line:123
|vpiName:ICACHE_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_LINE_W), line:124
|vpiName:ICACHE_LINE_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_SUB_LINE_ADDR_W), line:125
|vpiName:ICACHE_SUB_LINE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (ICACHE_TAG_W), line:126
|vpiName:ICACHE_TAG_W
|INT:-2147483648
|vpiParameter:
\_parameter: (ICACHE_WAYS), line:122
|vpiName:ICACHE_WAYS
|INT:1
|vpiParameter:
\_parameter: (ITLB_DEPTH), line:146
|vpiName:ITLB_DEPTH
|INT:32
|vpiParameter:
\_parameter: (ITLB_WAYS), line:145
|vpiName:ITLB_WAYS
|INT:4
|vpiParameter:
\_parameter: (L1_CONNECTIONS), line:177
|vpiName:L1_CONNECTIONS
|INT:9
|vpiParameter:
\_parameter: (L1_DCACHE_ID), line:178
|vpiName:L1_DCACHE_ID
|INT:4
|vpiParameter:
\_parameter: (L1_DMMU_ID), line:179
|vpiName:L1_DMMU_ID
|INT:2
|vpiParameter:
\_parameter: (L1_ICACHE_ID), line:180
|vpiName:L1_ICACHE_ID
|INT:19
|vpiParameter:
\_parameter: (L1_IMMU_ID), line:181
|vpiName:L1_IMMU_ID
|INT:0
|vpiParameter:
\_parameter: (L2_DATA_ATTRIBUTES_FIFO_DEPTH), line:41
|vpiName:L2_DATA_ATTRIBUTES_FIFO_DEPTH
|INT:16
|vpiParameter:
\_parameter: (L2_ID_W), line:46
|vpiName:L2_ID_W
|INT:3
|vpiParameter:
\_parameter: (L2_INPUT_FIFO_DEPTHS), line:34
|vpiName:L2_INPUT_FIFO_DEPTHS
|INT:4
|vpiParameter:
\_parameter: (L2_INVALIDATION_FIFO_DEPTHS), line:35
|vpiName:L2_INVALIDATION_FIFO_DEPTHS
|INT:4
|vpiParameter:
\_parameter: (L2_MEM_ADDR_FIFO_DEPTH), line:39
|vpiName:L2_MEM_ADDR_FIFO_DEPTH
|INT:8
|vpiParameter:
\_parameter: (L2_NUM_PORTS), line:26
|vpiName:L2_NUM_PORTS
|INT:2
|vpiParameter:
\_parameter: (L2_READ_RETURN_FIFO_DEPTHS), line:36
|vpiName:L2_READ_RETURN_FIFO_DEPTHS
|INT:1
|vpiParameter:
\_parameter: (L2_SUB_ID_W), line:27
|vpiName:L2_SUB_ID_W
|INT:2
|vpiParameter:
\_parameter: (LS_UNIT_WB_ID), line:191
|vpiName:LS_UNIT_WB_ID
|INT:1
|vpiParameter:
\_parameter: (MAX_INFLIGHT_COUNT), line:167
|vpiName:MAX_INFLIGHT_COUNT
|INT:19
|vpiParameter:
\_parameter: (MEMORY_ADDR_H), line:103
|vpiName:MEMORY_ADDR_H
|INT:12
|vpiParameter:
\_parameter: (MEMORY_ADDR_L), line:102
|vpiName:MEMORY_ADDR_L
|INT:11
|vpiParameter:
\_parameter: (MEMORY_BIT_CHECK), line:104
|vpiName:MEMORY_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (MEM_LINES), line:61
|vpiName:MEM_LINES
|INT:4096
|vpiParameter:
\_parameter: (MUL_UNIT_WB_ID), line:193
|vpiName:MUL_UNIT_WB_ID
|INT:512
|vpiParameter:
\_parameter: (NUM_UNITS), line:188
|vpiName:NUM_UNITS
|INT:2
|vpiParameter:
\_parameter: (NUM_WB_UNITS), line:186
|vpiName:NUM_WB_UNITS
|INT:2
|vpiParameter:
\_parameter: (PAGE_ADDR_W), line:27
|vpiName:PAGE_ADDR_W
|INT:0
|vpiParameter:
\_parameter: (RAS_DEPTH), line:161
|vpiName:RAS_DEPTH
|INT:2
|vpiParameter:
\_parameter: (RESET_VEC), line:39
|vpiName:RESET_VEC
|INT:-2147483648
|vpiParameter:
\_parameter: (SCRATCH_ADDR_H), line:99
|vpiName:SCRATCH_ADDR_H
|INT:9
|vpiParameter:
\_parameter: (SCRATCH_ADDR_L), line:98
|vpiName:SCRATCH_ADDR_L
|INT:8
|vpiParameter:
\_parameter: (SCRATCH_BIT_CHECK), line:100
|vpiName:SCRATCH_BIT_CHECK
|INT:10
|vpiParameter:
\_parameter: (SCRATCH_MEM_KB), line:60
|vpiName:SCRATCH_MEM_KB
|INT:16
|vpiParameter:
\_parameter: (USE_AMO), line:70
|vpiName:USE_AMO
|INT:1
|vpiParameter:
\_parameter: (USE_BRANCH_PREDICTOR), line:158
|vpiName:USE_BRANCH_PREDICTOR
|INT:2
|vpiParameter:
\_parameter: (USE_BUS), line:88
|vpiName:USE_BUS
|INT:4
|vpiParameter:
\_parameter: (USE_DCACHE), line:92
|vpiName:USE_DCACHE
|INT:6
|vpiParameter:
\_parameter: (USE_DIV), line:49
|vpiName:USE_DIV
|INT:1
|vpiParameter:
\_parameter: (USE_DTAG_INVALIDATIONS), line:140
|vpiName:USE_DTAG_INVALIDATIONS
|INT:1879048191
|vpiParameter:
\_parameter: (USE_D_SCRATCH_MEM), line:79
|vpiName:USE_D_SCRATCH_MEM
|INT:3
|vpiParameter:
\_parameter: (USE_ICACHE), line:93
|vpiName:USE_ICACHE
|INT:7
|vpiParameter:
\_parameter: (USE_I_SCRATCH_MEM), line:78
|vpiName:USE_I_SCRATCH_MEM
|INT:2
|vpiParameter:
\_parameter: (USE_MUL), line:48
|vpiName:USE_MUL
|INT:1
|vpiParameter:
\_parameter: (WB_UNITS_WIDTH), line:187
|vpiName:WB_UNITS_WIDTH
|INT:32
|vpiParameter:
\_parameter: (XLEN), line:26
|vpiName:XLEN
|INT:1
Object: \work_div_unit_core_wrapper of type 3000
Object: \work_avalon_interface of type 601
Object: \addr of type 36
Object: \read of type 36
Object: \write of type 36
Object: \byteenable of type 36
Object: \readdata of type 36
Object: \writedata of type 36
Object: \waitrequest of type 36
Object: \readdatavalid of type 36
Object: \writeresponsevalid of type 36
Object: \master of type 606
Object: \readdata of type 28
Object: \waitrequest of type 28
Object: \readdatavalid of type 28
Object: \writeresponsevalid of type 28
Object: \addr of type 28
Object: \read of type 28
Object: \write of type 28
Object: \byteenable of type 28
Object: \writedata of type 28
Object: \slave of type 606
Object: \readdata of type 28
Object: \waitrequest of type 28
Object: \readdatavalid of type 28
Object: \writeresponsevalid of type 28
Object: \addr of type 28
Object: \read of type 28
Object: \write of type 28
Object: \byteenable of type 28
Object: \writedata of type 28
Object: \work_axi_interface of type 601
Object: \arready of type 36
Object: \arvalid of type 36
Object: \araddr of type 36
Object: \arlen of type 36
Object: \arsize of type 36
Object: \arburst of type 36
Object: \arcache of type 36
Object: \arid of type 36
Object: \rready of type 36
Object: \rvalid of type 36
Object: \rdata of type 36
Object: \rresp of type 36
Object: \rlast of type 36
Object: \rid of type 36
Object: \awready of type 36
Object: \awvalid of type 36
Object: \awaddr of type 36
Object: \awlen of type 36
Object: \awsize of type 36
Object: \awburst of type 36
Object: \awcache of type 36
Object: \awid of type 36
Object: \wready of type 36
Object: \wvalid of type 36
Object: \wdata of type 36
Object: \wstrb of type 36
Object: \wlast of type 36
Object: \bready of type 36
Object: \bvalid of type 36
Object: \bresp of type 36
Object: \bid of type 36
Object: \master of type 606
Object: \arready of type 28
Object: \rvalid of type 28
Object: \rdata of type 28
Object: \rresp of type 28
Object: \rlast of type 28
Object: \rid of type 28
Object: \awready of type 28
Object: \wready of type 28
Object: \bvalid of type 28
Object: \bresp of type 28
Object: \bid of type 28
Object: \arvalid of type 28
Object: \araddr of type 28
Object: \arlen of type 28
Object: \arsize of type 28
Object: \arburst of type 28
Object: \arcache of type 28
Object: \arid of type 28
Object: \rready of type 28
Object: \awvalid of type 28
Object: \awaddr of type 28
Object: \awlen of type 28
Object: \awsize of type 28
Object: \awburst of type 28
Object: \awcache of type 28
Object: \awid of type 28
Object: \wvalid of type 28
Object: \wdata of type 28
Object: \wstrb of type 28
Object: \wlast of type 28
Object: \bready of type 28
Object: \slave of type 606
Object: \arvalid of type 28
Object: \araddr of type 28
Object: \arlen of type 28
Object: \arsize of type 28
Object: \arburst of type 28
Object: \arcache of type 28
Object: \rready of type 28
Object: \awvalid of type 28
Object: \awaddr of type 28
Object: \awlen of type 28
Object: \awsize of type 28
Object: \awburst of type 28
Object: \awcache of type 28
Object: \arid of type 28
Object: \wvalid of type 28
Object: \wdata of type 28
Object: \wstrb of type 28
Object: \wlast of type 28
Object: \awid of type 28
Object: \bready of type 28
Object: \arready of type 28
Object: \rvalid of type 28
Object: \rdata of type 28
Object: \rresp of type 28
Object: \rlast of type 28
Object: \rid of type 28
Object: \awready of type 28
Object: \wready of type 28
Object: \bvalid of type 28
Object: \bresp of type 28
Object: \bid of type 28
Object: \work_branch_predictor_interface of type 601
Object: \if_pc of type 36
Object: \new_mem_request of type 36
Object: \next_pc of type 36
Object: \branch_flush_pc of type 36
Object: \predicted_pc of type 36
Object: \use_prediction of type 36
Object: \update_way of type 36
Object: \use_ras of type 36
Object: \metadata of type 36
Object: \branch_predictor of type 606
Object: \if_pc of type 28
Object: \new_mem_request of type 28
Object: \next_pc of type 28
Object: \branch_flush_pc of type 28
Object: \predicted_pc of type 28
Object: \use_prediction of type 28
Object: \update_way of type 28
Object: \use_ras of type 28
Object: \metadata of type 28
Object: \fetch of type 606
Object: \branch_flush_pc of type 28
Object: \predicted_pc of type 28
Object: \use_prediction of type 28
Object: \update_way of type 28
Object: \use_ras of type 28
Object: \metadata of type 28
Object: \if_pc of type 28
Object: \new_mem_request of type 28
Object: \next_pc of type 28
Object: \work_csr_exception_interface of type 601
Object: \valid of type 36
Object: \code of type 36
Object: \pc of type 36
Object: \addr of type 36
Object: \illegal_instruction of type 36
Object: \csr_pc of type 36
Object: \csr of type 606
Object: \valid of type 28
Object: \code of type 28
Object: \pc of type 28
Object: \addr of type 28
Object: \illegal_instruction of type 28
Object: \csr_pc of type 28
Object: \econtrol of type 606
Object: \valid of type 28
Object: \code of type 28
Object: \pc of type 28
Object: \addr of type 28
Object: \illegal_instruction of type 28
Object: \csr_pc of type 28
Object: \work_exception_interface of type 601
Object: \valid of type 36
Object: \ack of type 36
Object: \code of type 36
Object: \pc of type 36
Object: \addr of type 36
Object: \id of type 36
Object: \econtrol of type 606
Object: \valid of type 28
Object: \code of type 28
Object: \pc of type 28
Object: \addr of type 28
Object: \id of type 28
Object: \ack of type 28
Object: \unit of type 606
Object: \valid of type 28
Object: \code of type 28
Object: \pc of type 28
Object: \addr of type 28
Object: \id of type 28
Object: \ack of type 28
Object: \work_fetch_sub_unit_interface of type 601
Object: \stage1_addr of type 36
Object: \stage2_addr of type 36
Object: \data_out of type 36
Object: \data_valid of type 36
Object: \ready of type 36
Object: \new_request of type 36
Object: \flush of type 36
Object: \fetch of type 606
Object: \stage1_addr of type 28
Object: \stage2_addr of type 28
Object: \new_request of type 28
Object: \flush of type 28
Object: \data_out of type 28
Object: \data_valid of type 28
Object: \ready of type 28
Object: \sub_unit of type 606
Object: \stage1_addr of type 28
Object: \stage2_addr of type 28
Object: \new_request of type 28
Object: \flush of type 28
Object: \data_out of type 28
Object: \data_valid of type 28
Object: \ready of type 28
Object: \work_fifo_interface of type 601
Object: \push of type 36
Object: \pop of type 36
Object: \data_in of type 36
Object: \data_out of type 36
Object: \valid of type 36
Object: \full of type 36
Object: \supress_push of type 36
Object: \dequeue of type 606
Object: \valid of type 28
Object: \data_out of type 28
Object: \pop of type 28
Object: \enqueue of type 606
Object: \full of type 28
Object: \data_in of type 28
Object: \push of type 28
Object: \supress_push of type 28
Object: \structure of type 606
Object: \push of type 28
Object: \pop of type 28
Object: \data_in of type 28
Object: \supress_push of type 28
Object: \data_out of type 28
Object: \valid of type 28
Object: \full of type 28
Object: \work_l1_arbiter_request_interface of type 601
Object: \addr of type 36
Object: \data of type 36
Object: \rnw of type 36
Object: \be of type 36
Object: \size of type 36
Object: \is_amo of type 36
Object: \amo of type 36
Object: \request of type 36
Object: \ack of type 36
Object: \master of type 606
Object: \addr of type 28
Object: \data of type 28
Object: \rnw of type 28
Object: \be of type 28
Object: \size of type 28
Object: \is_amo of type 28
Object: \amo of type 28
Object: \request of type 28
Object: \ack of type 28
Object: \slave of type 606
Object: \addr of type 28
Object: \data of type 28
Object: \rnw of type 28
Object: \be of type 28
Object: \size of type 28
Object: \is_amo of type 28
Object: \amo of type 28
Object: \request of type 28
Object: \ack of type 28
Object: \work_l1_arbiter_return_interface of type 601
Object: \inv_addr of type 36
Object: \inv_valid of type 36
Object: \inv_ack of type 36
Object: \data of type 36
Object: \data_valid of type 36
Object: \master of type 606
Object: \inv_addr of type 28
Object: \inv_valid of type 28
Object: \data of type 28
Object: \data_valid of type 28
Object: \inv_ack of type 28
Object: \slave of type 606
Object: \inv_addr of type 28
Object: \inv_valid of type 28
Object: \data of type 28
Object: \data_valid of type 28
Object: \inv_ack of type 28
Object: \work_l2_arbitration_interface of type 601
Object: \requests of type 36
Object: \grantee_i of type 36
Object: \grantee_v of type 36
Object: \grantee_valid of type 36
Object: \strobe of type 36
Object: \master of type 606
Object: \requests of type 28
Object: \strobe of type 28
Object: \grantee_i of type 28
Object: \grantee_v of type 28
Object: \grantee_valid of type 28
Object: \slave of type 606
Object: \requests of type 28
Object: \strobe of type 28
Object: \grantee_i of type 28
Object: \grantee_v of type 28
Object: \grantee_valid of type 28
Object: \work_l2_fifo_interface of type 601
Object: \push of type 36
Object: \pop of type 36
Object: \data_in of type 36
Object: \data_out of type 36
Object: \valid of type 36
Object: \full of type 36
Object: \empty of type 36
Object: \dequeue of type 606
Object: \valid of type 28
Object: \data_out of type 28
Object: \pop of type 28
Object: \enqueue of type 606
Object: \full of type 28
Object: \empty of type 28
Object: \data_in of type 28
Object: \push of type 28
Object: \structure of type 606
Object: \push of type 28
Object: \pop of type 28
Object: \data_in of type 28
Object: \data_out of type 28
Object: \valid of type 28
Object: \full of type 28
Object: \empty of type 28
Object: \work_l2_memory_interface of type 601
Object: \addr of type 36
Object: \be of type 36
Object: \rnw of type 36
Object: \is_amo of type 36
Object: \amo_type_or_burst_size of type 36
Object: \id of type 36
Object: \request_pop of type 36
Object: \request_valid of type 36
Object: \abort of type 36
Object: \wr_data of type 36
Object: \wr_data_valid of type 36
Object: \wr_data_read of type 36
Object: \rd_data of type 36
Object: \rd_id of type 36
Object: \rd_data_valid of type 36
Object: \master of type 606
Object: \addr of type 28
Object: \be of type 28
Object: \rnw of type 28
Object: \is_amo of type 28
Object: \amo_type_or_burst_size of type 28
Object: \id of type 28
Object: \request_valid of type 28
Object: \abort of type 28
Object: \request_pop of type 28
Object: \wr_data of type 28
Object: \wr_data_valid of type 28
Object: \wr_data_read of type 28
Object: \rd_data of type 28
Object: \rd_id of type 28
Object: \rd_data_valid of type 28
Object: \slave of type 606
Object: \addr of type 28
Object: \be of type 28
Object: \rnw of type 28
Object: \is_amo of type 28
Object: \amo_type_or_burst_size of type 28
Object: \id of type 28
Object: \request_valid of type 28
Object: \abort of type 28
Object: \request_pop of type 28
Object: \wr_data of type 28
Object: \wr_data_valid of type 28
Object: \wr_data_read of type 28
Object: \rd_data of type 28
Object: \rd_id of type 28
Object: \rd_data_valid of type 28
Object: \work_l2_requester_interface of type 601
Object: \addr of type 36
Object: \be of type 36
Object: \rnw of type 36
Object: \is_amo of type 36
Object: \amo_type_or_burst_size of type 36
Object: \sub_id of type 36
Object: \request_push of type 36
Object: \request_full of type 36
Object: \inv_addr of type 36
Object: \inv_valid of type 36
Object: \inv_ack of type 36
Object: \con_result of type 36
Object: \con_valid of type 36
Object: \wr_data of type 36
Object: \wr_data_push of type 36
Object: \data_full of type 36
Object: \rd_data of type 36
Object: \rd_sub_id of type 36
Object: \rd_data_valid of type 36
Object: \rd_data_ack of type 36
Object: \master of type 606
Object: \addr of type 28
Object: \be of type 28
Object: \rnw of type 28
Object: \is_amo of type 28
Object: \amo_type_or_burst_size of type 28
Object: \sub_id of type 28
Object: \request_push of type 28
Object: \request_full of type 28
Object: \inv_addr of type 28
Object: \inv_valid of type 28
Object: \inv_ack of type 28
Object: \con_result of type 28
Object: \con_valid of type 28
Object: \wr_data of type 28
Object: \wr_data_push of type 28
Object: \data_full of type 28
Object: \rd_data of type 28
Object: \rd_sub_id of type 28
Object: \rd_data_valid of type 28
Object: \rd_data_ack of type 28
Object: \slave of type 606
Object: \addr of type 28
Object: \be of type 28
Object: \rnw of type 28
Object: \is_amo of type 28
Object: \amo_type_or_burst_size of type 28
Object: \sub_id of type 28
Object: \request_push of type 28
Object: \request_full of type 28
Object: \inv_addr of type 28
Object: \inv_valid of type 28
Object: \inv_ack of type 28
Object: \con_result of type 28
Object: \con_valid of type 28
Object: \wr_data of type 28
Object: \wr_data_push of type 28
Object: \data_full of type 28
Object: \rd_data of type 28
Object: \rd_sub_id of type 28
Object: \rd_data_valid of type 28
Object: \rd_data_ack of type 28
Object: \work_local_memory_interface of type 601
Object: \addr of type 36
Object: \en of type 36
Object: \be of type 36
Object: \data_in of type 36
Object: \data_out of type 36
Object: \master of type 606
Object: \addr of type 28
Object: \en of type 28
Object: \be of type 28
Object: \data_in of type 28
Object: \data_out of type 28
Object: \slave of type 606
Object: \addr of type 28
Object: \en of type 28
Object: \be of type 28
Object: \data_in of type 28
Object: \data_out of type 28
Object: \work_ls_sub_unit_interface of type 601
Object: \data_valid of type 36
Object: \ready of type 36
Object: \new_request of type 36
Object: \ls of type 606
Object: \new_request of type 28
Object: \data_valid of type 28
Object: \ready of type 28
Object: \sub_unit of type 606
Object: \new_request of type 28
Object: \data_valid of type 28
Object: \ready of type 28
Object: \work_mmu_interface of type 601
Object: \new_request of type 36
Object: \execute of type 36
Object: \rnw of type 36
Object: \virtual_address of type 36
Object: \write_entry of type 36
Object: \new_phys_addr of type 36
Object: \ppn of type 36
Object: \mxr of type 36
Object: \pum of type 36
Object: \privilege of type 36
Object: \csr of type 606
Object: \ppn of type 28
Object: \mxr of type 28
Object: \pum of type 28
Object: \privilege of type 28
Object: \mmu of type 606
Object: \virtual_address of type 28
Object: \new_request of type 28
Object: \execute of type 28
Object: \rnw of type 28
Object: \ppn of type 28
Object: \mxr of type 28
Object: \pum of type 28
Object: \privilege of type 28
Object: \write_entry of type 28
Object: \new_phys_addr of type 28
Object: \tlb of type 606
Object: \write_entry of type 28
Object: \new_phys_addr of type 28
Object: \new_request of type 28
Object: \virtual_address of type 28
Object: \execute of type 28
Object: \rnw of type 28
Object: \work_post_issue_forwarding_interface of type 601
Object: \id of type 36
Object: \data of type 36
Object: \data_valid of type 36
Object: \unit of type 606
Object: \data of type 28
Object: \data_valid of type 28
Object: \id of type 28
Object: \wb of type 606
Object: \data of type 28
Object: \data_valid of type 28
Object: \id of type 28
Object: \work_ras_interface of type 601
Object: \push of type 36
Object: \pop of type 36
Object: \new_addr of type 36
Object: \addr of type 36
Object: \valid of type 36
Object: \branch_unit of type 606
Object: \push of type 28
Object: \pop of type 28
Object: \new_addr of type 28
Object: \fetch of type 606
Object: \addr of type 28
Object: \valid of type 28
Object: \self of type 606
Object: \push of type 28
Object: \pop of type 28
Object: \new_addr of type 28
Object: \addr of type 28
Object: \valid of type 28
Object: \work_register_file_decode_interface of type 601
Object: \future_rd_addr of type 36
Object: \rs1_addr of type 36
Object: \rs1_data of type 36
Object: \rs2_addr of type 36
Object: \rs2_data of type 36
Object: \id of type 36
Object: \uses_rs1 of type 36
Object: \uses_rs2 of type 36
Object: \rs1_conflict of type 36
Object: \rs2_conflict of type 36
Object: \rs2_id of type 36
Object: \instruction_issued of type 36
Object: \decode of type 606
Object: \future_rd_addr of type 28
Object: \rs1_addr of type 28
Object: \rs2_addr of type 28
Object: \instruction_issued of type 28
Object: \id of type 28
Object: \uses_rs1 of type 28
Object: \uses_rs2 of type 28
Object: \rs1_conflict of type 28
Object: \rs2_conflict of type 28
Object: \rs1_data of type 28
Object: \rs2_data of type 28
Object: \rs2_id of type 28
Object: \unit of type 606
Object: \future_rd_addr of type 28
Object: \rs1_addr of type 28
Object: \rs2_addr of type 28
Object: \instruction_issued of type 28
Object: \id of type 28
Object: \uses_rs1 of type 28
Object: \uses_rs2 of type 28
Object: \rs1_conflict of type 28
Object: \rs2_conflict of type 28
Object: \rs1_data of type 28
Object: \rs2_data of type 28
Object: \rs2_id of type 28
Object: \work_register_file_writeback_interface of type 601
Object: \rd_addr of type 36
Object: \retiring of type 36
Object: \rd_nzero of type 36
Object: \rd_data of type 36
Object: \id of type 36
Object: \rs1_id of type 36
Object: \rs2_id of type 36
Object: \rs1_data of type 36
Object: \rs2_data of type 36
Object: \rs1_valid of type 36
Object: \rs2_valid of type 36
Object: \unit of type 606
Object: \rd_addr of type 28
Object: \retiring of type 28
Object: \rd_nzero of type 28
Object: \rd_data of type 28
Object: \id of type 28
Object: \rs1_data of type 28
Object: \rs2_data of type 28
Object: \rs1_valid of type 28
Object: \rs2_valid of type 28
Object: \rs1_id of type 28
Object: \rs2_id of type 28
Object: \writeback of type 606
Object: \rd_addr of type 28
Object: \retiring of type 28
Object: \rd_nzero of type 28
Object: \rd_data of type 28
Object: \id of type 28
Object: \rs1_data of type 28
Object: \rs2_data of type 28
Object: \rs1_valid of type 28
Object: \rs2_valid of type 28
Object: \rs1_id of type 28
Object: \rs2_id of type 28
Object: \work_tlb_interface of type 601
Object: \virtual_address of type 36
Object: \new_request of type 36
Object: \rnw of type 36
Object: \execute of type 36
Object: \complete of type 36
Object: \physical_address of type 36
Object: \flush of type 36
Object: \flush_complete of type 36
Object: \fence of type 606
Object: \flush of type 28
Object: \flush_complete of type 28
Object: \mem of type 606
Object: \new_request of type 28
Object: \virtual_address of type 28
Object: \rnw of type 28
Object: \execute of type 28
Object: \complete of type 28
Object: \physical_address of type 28
Object: \tlb of type 606
Object: \virtual_address of type 28
Object: \new_request of type 28
Object: \flush of type 28
Object: \rnw of type 28
Object: \execute of type 28
Object: \complete of type 28
Object: \physical_address of type 28
Object: \flush_complete of type 28
Object: \work_tracking_interface of type 601
Object: \issue_id of type 36
Object: \id_available of type 36
Object: \inflight_packet of type 36
Object: \issued of type 36
Object: \issue_unit_id of type 36
Object: \decode of type 606
Object: \issue_id of type 28
Object: \id_available of type 28
Object: \inflight_packet of type 28
Object: \issued of type 28
Object: \issue_unit_id of type 28
Object: \wb of type 606
Object: \issue_id of type 28
Object: \id_available of type 28
Object: \inflight_packet of type 28
Object: \issued of type 28
Object: \issue_unit_id of type 28
Object: \work_unit_issue_interface of type 601
Object: \possible_issue of type 36
Object: \new_request of type 36
Object: \new_request_r of type 36
Object: \instruction_id of type 36
Object: \ready of type 36
Object: \decode of type 606
Object: \ready of type 28
Object: \possible_issue of type 28
Object: \new_request of type 28
Object: \new_request_r of type 28
Object: \instruction_id of type 28
Object: \unit of type 606
Object: \ready of type 28
Object: \possible_issue of type 28
Object: \new_request of type 28
Object: \new_request_r of type 28
Object: \instruction_id of type 28
Object: \work_unsigned_division_interface of type 601
Object: \start of type 36
Object: \dividend of type 36
Object: \divisor of type 36
Object: \remainder of type 36
Object: \quotient of type 36
Object: \done of type 36
Object: \divisor_is_zero of type 36
Object: \divider of type 606
Object: \remainder of type 28
Object: \quotient of type 28
Object: \done of type 28
Object: \divisor_is_zero of type 28
Object: \dividend of type 28
Object: \divisor of type 28
Object: \start of type 28
Object: \requester of type 606
Object: \remainder of type 28
Object: \quotient of type 28
Object: \done of type 28
Object: \divisor_is_zero of type 28
Object: \dividend of type 28
Object: \divisor of type 28
Object: \start of type 28
Object: \work_wishbone_interface of type 601
Object: \addr of type 36
Object: \we of type 36
Object: \sel of type 36
Object: \readdata of type 36
Object: \writedata of type 36
Object: \stb of type 36
Object: \cyc of type 36
Object: \ack of type 36
Object: \master of type 606
Object: \readdata of type 28
Object: \ack of type 28
Object: \addr of type 28
Object: \we of type 28
Object: \sel of type 28
Object: \writedata of type 28
Object: \stb of type 28
Object: \cyc of type 28
Object: \slave of type 606
Object: \readdata of type 28
Object: \ack of type 28
Object: \addr of type 28
Object: \we of type 28
Object: \sel of type 28
Object: \writedata of type 28
Object: \stb of type 28
Object: \cyc of type 28
Object: \work_div_unit_core_wrapper of type 32
Object: \clk of type 44
Object: \rst of type 44
Object: \start of type 44
Object: \ack of type 44
Object: \A of type 44
Object: of type 115
Object: of type 7
Object: of type 7
Object: \B of type 44
Object: of type 115
Object: of type 7
Object: of type 7
Object: \Q of type 44
Object: of type 115
Object: of type 7
Object: of type 7
Object: \R of type 44
Object: of type 115
Object: of type 7
Object: of type 7
Object: \complete of type 44
Object: \B_is_zero of type 44
Object: \div_core of type 32
Object: \clk of type 44
Object: \rst of type 44
Object: \start of type 44
Object: \ack of type 44
Object: \A of type 44
Object: \B of type 44
Object: \Q of type 44
Object: \R of type 44
Object: \complete of type 44
Object: \B_is_zero of type 44
Object: \div_block of type 32
Object: \clk of type 44
Object: \rst of type 44
Object: \div of type 44
Object: \clk of type 36
Object: \rst of type 36
Object: \terminate of type 36
Object: \new_PR of type 36
Object: of type 115
Object: \div.DATA_WIDTH of type 608
Object: of type 7
Object: \PR of type 36
Object: of type 115
Object: \div.DATA_WIDTH of type 608
Object: of type 7
Object: \shift_count of type 36
Object: of type 115
Object: of type 39
Object: \div.DATA_WIDTH of type 608
Object: of type 7
Object: of type 7
Object: \negative_sub_rst of type 36
Object: \div of type 36
Object: \div_block of type 32
Object: \clk of type 44
Object: \rst of type 44
Object: \div of type 44
Object: \clk of type 36
Object: \rst of type 36
Object: \terminate of type 36
Object: \terminate_early of type 36
Object: \new_PR of type 36
Object: of type 115
Object: \div.DATA_WIDTH of type 608
Object: of type 7
Object: \PR of type 36
Object: of type 115
Object: \div.DATA_WIDTH of type 608
Object: of type 7
Object: \shift_count of type 36
Object: of type 115
Object: of type 39
Object: \div.DATA_WIDTH of type 608
Object: of type 7
Object: of type 7
Object: \negative_sub_rst of type 36
Object: \div of type 36
Object: \div_block of type 32
Object: \clk of type 44
Object: \rst of type 44
Object: \div of type 44
Object: \clk of type 36
Object: \rst of type 36
Object: \terminate of type 36
Object: \new_PR of type 36
Object: of type 115
Object: \div.DATA_WIDTH of type 608
Object: of type 7
Object: \PR of type 36
Object: of type 115
Object: \div.DATA_WIDTH of type 608
Object: of type 7
Object: \shift_count of type 36
Object: of type 115
Object: of type 39
Object: \div.DATA_WIDTH of type 608
Object: of type 7
Object: of type 7
Object: \negative_sub_rst of type 36
Object: \AR_r of type 36
Object: of type 115
Object: of type 39
Object: \div.DATA_WIDTH of type 608
Object: of type 7
Object: of type 7
Object: \Q_temp of type 36
Object: of type 115
Object: of type 39
Object: \div.DATA_WIDTH of type 608
Object: of type 7
Object: of type 7
Object: \shift_num_R of type 36
Object: of type 115
Object: of type 7
Object: of type 7
Object: \shift_num_Q of type 36
Object: of type 115
Object: of type 7
Object: of type 7
Object: \combined of type 36
Object: of type 115
Object: of type 39
Object: \div.DATA_WIDTH of type 608
Object: of type 7
ERROR: Encountered unhandled operation: 25